PRELIMINARY PRODUCT SPECIFICATIONS (R) Integrated Circuits Group LH28F160S3HT-L10A Flash Memory 16M (2M x 8/1M x 16) (Model No.: LHF16KA7) Issue Date: March 22, 2001 sharp LHF16KA7 Handle this document carefully for it contains material protected by international copyright law. Any reproduction, full or in part, of this material is prohibited without the express written permission of the company. When using the products covered herein, please observe the conditions written herein and the precautions outlined in the following paragraphs. In no event shall the company be liable for any damages resulting from failure to strictly adhere to these conditions and precautions. (1) The products covered herein are designed and manufactured for the following application areas. When using the products covered herein for the equipment listed in Paragraph (2), even for the following application areas, be sure to observe the precautions given in Paragraph (2). Never use the products for the equipment listed in Paragraph (3). *Office electronics *Instrumentation and measuring equipment *Machine tools *Audiovisual equipment *Home appliance *Communication equipment other than for trunk lines (2) Those contemplating using the products covered herein for the following equipment which demands high reliability, should first contact a sales representative of the company and then accept responsibility for incorporating into the design fail-safe operation, redundancy, and other appropriate measures for ensuring reliability and safety of the equipment and the overall system. *Control and safety devices for airplanes, trains, automobiles, and other transportation equipment *Mainframe computers *Traffic control systems *Gas leak detectors and automatic cutoff devices *Rescue and security equipment *Other safety devices and safety equipment, etc. (3) Do not use the products covered herein for the following equipment which demands extremely high performance in terms of functionality, reliability, or accuracy. *Aerospace equipment *Communications equipment for trunk lines *Control equipment for the nuclear power industry *Medical equipment related to life support, etc. (4) Please direct all queries and comments regarding the interpretation of the above three Paragraphs to a sales representative of the company. Please direct all queries regarding the products covered herein to a sales representative of the company. Rev. 2.0 sharp 1 LHF16KA7 CONTENTS PAGE PAGE 1 INTRODUCTION ...................................................... 3 5 DESIGN CONSIDERATIONS .................................30 1.1 Product Overview ................................................ 3 5.1 Three-Line Output Control .................................30 5.2 STS and Block Erase, Full Chip Erase, (Multi) 2 PRINCIPLES OF OPERATION ................................ 6 Word/Byte Write and Block Lock-Bit Configuration 2.1 Data Protection ................................................... 7 Polling................................................................30 5.3 Power Supply Decoupling ..................................30 3 BUS OPERATION.................................................... 7 5.4 VPP Trace on Printed Circuit Boards ..................30 3.1 Read ................................................................... 7 5.5 VCC, VPP, RP# Transitions.................................31 3.2 Output Disable .................................................... 7 5.6 Power-Up/Down Protection................................31 3.3 Standby ............................................................... 7 5.7 Power Dissipation ..............................................31 3.4 Deep Power-Down .............................................. 7 3.5 Read Identifier Codes Operation ......................... 8 6 ELECTRICAL SPECIFICATIONS...........................32 3.6 Query Operation.................................................. 8 6.1 Absolute Maximum Ratings ...............................32 3.7 Write.................................................................... 8 6.2 Operating Conditions .........................................32 6.2.1 Capacitance .................................................32 4 COMMAND DEFINITIONS ....................................... 8 6.2.2 AC Input/Output Test Conditions ..................33 4.1 Read Array Command....................................... 11 6.2.3 DC Characteristics........................................34 4.2 Read Identifier Codes Command ...................... 11 6.2.4 AC Characteristics - Read-Only Operations .36 4.3 Read Status Register Command....................... 11 6.2.5 AC Characteristics - Write Operations..........39 4.4 Clear Status Register Command....................... 11 6.2.6 Alternative CE#-Controlled Writes ................42 4.5 Query Command............................................... 12 6.2.7 Reset Operations .........................................45 4.5.1 Block Status Register .................................. 12 6.2.8 Block Erase, Full Chip Erase, (Multi) 4.5.2 CFI Query Identification String..................... 13 Word/Byte Write and Block Lock-Bit 4.5.3 System Interface Information....................... 13 Configuration Performance...........................46 4.5.4 Device Geometry Definition ......................... 14 4.5.5 SCS OEM Specific Extended Query Table .. 14 7 ADDITIONAL INFORMATION ................................48 4.6 Block Erase Command...................................... 15 7.1 Ordering Information ..........................................48 4.7 Full Chip Erase Command ................................ 15 4.8 Word/Byte Write Command............................... 16 4.9 Multi Word/Byte Write Command ...................... 16 4.10 Block Erase Suspend Command..................... 17 4.11 (Multi) Word/Byte Write Suspend Command... 17 4.12 Set Block Lock-Bit Command.......................... 18 4.13 Clear Block Lock-Bits Command..................... 18 4.14 STS Configuration Command ......................... 19 Rev. 2.0 sharp 2 LHF16KA7 LH28F160S3HT-L10A 16M-BIT (2MBx8/1MBx16) Smart 3 Flash MEMORY Smart 3 Technology 2.7V or 3.3V VCC 2.7V, 3.3V or 5V VPP Common Flash Interface (CFI) Universal & Upgradable Interface Scalable Command Set (SCS) High Speed Write Performance 32 Bytes x 2 plane Page Buffer 2.7 s/Byte Write Transfer Rate High Speed Read Performance 100ns(3.3V0.3V), 120ns(2.7V-3.6V) Operating Temperature -40C to +85C Enhanced Automated Suspend Options Write Suspend to Read Block Erase Suspend to Write Block Erase Suspend to Read High-Density Symmetrically-Blocked Architecture Thirty-two 64K-byte Erasable Blocks SRAM-Compatible Write Interface User-Configurable x8 or x16 Operation Enhanced Data Protection Features Absolute Protection with VPP=GND Flexible Block Locking Erase/Write Lockout during Power Transitions Extended Cycling Capability 100,000 Block Erase Cycles 3.2 Million Block Erase Cycles/Chip Low Power Management Deep Power-Down Mode Automatic Power Savings Mode Decreases ICC in Static Mode Automated Write and Erase Command User Interface Status Register Industry-Standard Packaging 56-Lead TSOP ETOXTM* V Nonvolatile Flash Technology CMOS Process (P-type silicon substrate) Not designed or rated as radiation hardened SHARP's LH28F160S3HT-L10A Flash memory with Smart 3 technology is a high-density, low-cost, nonvolatile, read/write storage solution for a wide range of applications. Its symmetrically-blocked architecture, flexible voltage and extended cycling provide for highly flexible component suitable for resident flash arrays, SIMMs and memory cards. Its enhanced suspend capabilities provide for an ideal solution for code + data storage applications. For secure code storage applications, such as networking, where code is either directly executed out of flash or downloaded to DRAM, the LH28F160S3HT-L10A offers three levels of protection: absolute protection with VPP at GND, selective hardware block locking, or flexible software block locking. These alternatives give designers ultimate control of their code security needs. The LH28F160S3HT-L10A is conformed to the flash Scalable Command Set (SCS) and the Common Flash Interface (CFI) specification which enable universal and upgradable interface, enable the highest system/device data transfer rates and minimize device and system-level implementation costs. The LH28F160S3HT-L10A is manufactured on SHARP's 0.35m ETOXTM* V process technology. It come in industry-standard package: the 56-Lead TSOP ideal for board constrained applications. *ETOX is a trademark of Intel Corporation. Rev. 2.0 sharp LHF16KA7 1 INTRODUCTION This datasheet contains LH28F160S3HT-L10A specifications. Section 1 provides a flash memory overview. Sections 2, 3, 4, and 5 describe the memory organization and functionality. Section 6 covers electrical specifications. 1.1 Product Overview The LH28F160S3HT-L10A is a high-performance 16M-bit Smart 3 Flash memory organized as 2MBx8/1MBx16. The 2MB of data is arranged in thirty-two 64K-byte blocks which are individually erasable, lockable, and unlockable in-system. The memory map is shown in Figure 3. Smart 3 technology provides a choice of VCC and VPP combinations, as shown in Table 1, to meet system performance and power expectations. 2.7V VCC consumes approximately one-fifth the power of 5V VCC. VPP at 2.7V, 3.3V and 5V eliminates the need for a separate 12V converter, while VPP=5V maximizes erase and write performance. In addition to flexible erase and program voltages, the dedicated VPP pin gives complete data protection when VPPVPPLK. Table 1. VCC and VPP Voltage Combinations Offered by Smart 3 Technology VCC Voltage VPP Voltage 2.7V 2.7V, 3.3V, 5V 3.3V 3.3V, 5V Internal VCC and VPP detection Circuitry automatically configures the device for optimized read and write operations. A Command User Interface (CUI) serves as the interface between the system processor and internal operation of the device. A valid command sequence written to the CUI initiates device automation. An internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for block erase, full chip erase, (multi) word/byte write and block lock-bit configuration operations. A block erase operation erases one of the device's 64K-byte blocks typically within 0.41s (3.3V VCC, 5V VPP) independent of other blocks. Each block can be independently erased 100,000 times (3.2 million block erases per device). Block erase suspend mode allows system software to suspend block erase to read or write data from any other block. A word/byte write is performed in byte increments typically within 12.95s (3.3V VCC, 5V VPP). A multi word/byte write has high speed write performance of 2.7s/byte (3.3V VCC, 5V VPP). (Multi) Word/byte 3 write suspend mode enables the system to read data or execute code from any other flash memory array location. Individual block locking uses a combination of bits and WP#, Thirty-two block lock-bits, to lock and unlock blocks. Block lock-bits gate block erase, full chip erase and (multi) word/byte write operations. Block lock-bit configuration operations (Set Block Lock-Bit and Clear Block Lock-Bits commands) set and cleared block lock-bits. The status register indicates when the WSM's block erase, full chip erase, (multi) word/byte write or block lock-bit configuration operation is finished. The STS output gives an additional indicator of WSM activity by providing both a hardware signal of status (versus software polling) and status masking (interrupt masking for background block erase, for example). Status polling using STS minimizes both CPU overhead and system power consumption. STS pin can be configured to different states using the Configuration command. The STS pin defaults to RY/BY# operation. When low, STS indicates that the WSM is performing a block erase, full chip erase, (multi) word/byte write or block lock-bit configuration. STS-High Z indicates that the WSM is ready for a new command, block erase is suspended and (multi) word/byte write are inactive, (multi) word/byte write are suspended, or the device is in deep power-down mode. The other 3 alternate configurations are all pulse mode for use as a system interrupt. The access time is 100ns (tAVQV) over the extended temperature range (-40C to +85C) and VCC supply voltage range of 3.0V-3.6V. At lower VCC voltage, the access time is 120ns (2.7V-3.6V). The Automatic Power Savings (APS) feature substantially reduces active current when the device is in static mode (addresses not switching). In APS mode, the typical ICCR current is 3 mA at 3.3V VCC. When either CE0# or CE1#, and RP# pins are at VCC, the ICC CMOS standby mode is enabled. When the RP# pin is at GND, deep power-down mode is enabled which minimizes power consumption and provides write protection during reset. A reset time (tPHQV) is required from RP# switching high until outputs are valid. Likewise, the device has a wake time (tPHEL) from RP#-high until writes to the CUI are recognized. With RP# at GND, the WSM is reset and the status register is cleared. The device is available in 56-Lead TSOP (Thin Small Outline Package, 1.2 mm thick). Pinout is shown in Figure 2. Rev. 2.0 sharp 4 LHF16KA7 DQ0-DQ15 Input Buffer Output Buffer I/O Logic Idenrifier Register Page Buffer Status Register VCC BYTE# CE# Data Register Output Multiplexer Query ROM WE# Command Register OE# RP# WP# Multiplexer Data Comparator A0-A20 Input Buffer Y Decoder Address Latch X Decoder Y Gating STS Write State Machine Program/Erase Voltage Switch VPP VCC 32 64KByte Blocks GND Address Counter Figure 1. Block Diagram NC CE1# NC A20 A19 A18 A17 A16 VCC A15 A14 A13 A12 CE0# VPP RP# A11 A10 A9 A8 GND A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 LEAD TSOP STANDARD PINOUT 14mm x 20mm TOP VIEW 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 WP# WE# OE# STS DQ15 DQ7 DQ14 DQ6 GND DQ13 DQ5 DQ12 DQ4 VCC GND DQ11 DQ3 DQ10 DQ2 VCC DQ9 DQ1 DQ8 DQ0 A0 BYTE# NC NC Figure 2. TSOP 56-Lead Pinout (Normal Bend) Rev. 2.0 sharp Symbol Type A0-A20 INPUT DQ0-DQ15 INPUT/ OUTPUT CE0#, CE1# INPUT RP# INPUT OE# INPUT WE# INPUT STS OPEN DRAIN OUTPUT WP# INPUT BYTE# INPUT VPP SUPPLY VCC SUPPLY GND NC SUPPLY LHF16KA7 5 Table 2. Pin Descriptions Name and Function ADDRESS INPUTS: Inputs for addresses during read and write operations. Addresses are internally latched during a write cycle. A0: Byte Select Address. Not used in x16 mode(can be floated). A1-A4: Column Address. Selects 1 of 16 bit lines. A5-A15: Row Address. Selects 1 of 2048 word lines. A16-A20 : Block Address. DATA INPUT/OUTPUTS: DQ0-DQ7:Inputs data and commands during CUI write cycles; outputs data during memory array, status register, query, and identifier code read cycles. Data pins float to highimpedance when the chip is deselected or outputs are disabled. Data is internally latched during a write cycle. DQ8-DQ15:Inputs data during CUI write cycles in x16 mode; outputs data during memory array read cycles in x16 mode; not used for status register, query and identifier code read mode. Data pins float to high-impedance when the chip is deselected, outputs are disabled, or in x8 mode(Byte#=VIL). Data is internally latched during a write cycle. CHIP ENABLE: Activates the device's control logic, input buffers decoders, and sense amplifiers. Either CE0# or CE1# VIH deselects the device and reduces power consumption to standby levels. Both CE0# and CE1# must be VIL to select the devices. RESET/DEEP POWER-DOWN: Puts the device in deep power-down mode and resets internal automation. RP# VIH enables normal operation. When driven VIL, RP# inhibits write operations which provides data protection during power transitions. Exit from deep power-down sets the device to read array mode. OUTPUT ENABLE: Gates the device's outputs during a read cycle. WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data are latched on the rising edge of the WE# pulse. STS (RY/BY#): Indicates the status of the internal WSM. When configured in level mode (default mode), it acts as a RY/BY# pin. When low, the WSM is performing an internal operation (block erase, full chip erase, (multi) word/byte write or block lock-bit configuration). STS High Z indicates that the WSM is ready for new commands, block erase is suspended, and (multi) word/byte write is inactive, (multi) word/byte write is suspended or the device is in deep power-down mode. For alternate configurations of the STATUS pin, see the Configuration command. WRITE PROTECT: Master control for block locking. When VIL, Locked blocks can not be erased and programmed, and block lock-bits can not be set and reset. BYTE ENABLE: BYTE# VIL places device in x8 mode. All data is then input or output on DQ0-7, and DQ8-15 float. BYTE# VIH places the device in x16 mode , and turns off the A0 input buffer. BLOCK ERASE, FULL CHIP ERASE, (MULTI) WORD/BYTE WRITE, BLOCK LOCKBIT CONFIGURATION POWER SUPPLY: For erasing array blocks, writing bytes or configuring block lock-bits. With VPPVPPLK, memory contents cannot be altered. Block erase, full chip erase, (multi) word/byte write and block lock-bit configuration with an invalid VPP (see DC Characteristics) produce spurious results and should not be attempted. DEVICE POWER SUPPLY: Internal detection configures the device for 2.7V or 3.3V operation. To switch from one voltage to another, ramp VCC down to GND and then ramp VCC to the new voltage. Do not float any power pins. With VCCVLKO, all write attempts to the flash memory are inhibited. Device operations at invalid VCC voltage (see DC Characteristics) produce spurious results and should not be attempted. GROUND: Do not float any ground pins. NO CONNECT: Lead is not internal connected; it may be driven or floated. Rev. 2.0 sharp 6 LHF16KA7 2 PRINCIPLES OF OPERATION 1FFFFF The LH28F160S3HT-L10A Flash memory includes an on-chip WSM to manage block erase, full chip erase, (multi) word/byte write and block lock-bit configuration functions. It allows for: 100% TTL-level control inputs, fixed power supplies during block erase, full chip erase, (multi) word/byte write and block lock-bit configuration, and minimal processor overhead with RAM-Like interface timings. After initial device power-up or return from deep power-down mode (see Bus Operations), the device defaults to read array mode. Manipulation of external memory control pins allow array read, standby, and output disable operations. Status register, query structure and identifier codes can be accessed through the CUI independent of the VPP voltage. High voltage on VPP enables successful block erase, full chip erase, (multi) word/byte write and block lock-bit configuration. All functions associated with altering memory contentsblock erase, full chip erase, (multi) word/byte write and block lock-bit configuration, status, query and identifier codesare accessed via the CUI and verified through the status register. Commands are written using standard microprocessor write timings. The CUI contents serve as input to the WSM, which controls the block erase, full chip erase, (multi) word/byte write and block lockbit configuration. The internal algorithms are regulated by the WSM, including pulse repetition, internal verification, and margining of data. Addresses and data are internally latch during write cycles. Writing the appropriate command outputs array data, accesses the identifier codes, outputs query structure or outputs status register data. Interface software that initiates and polls progress of block erase, full chip erase, (multi) word/byte write and block lock-bit configuration can be stored in any block. This code is copied to and executed from system RAM during flash memory updates. After successful completion, reads are again possible via the Read Array command. Block erase suspend allows system software to suspend a block erase to read or write data from any other block. Write suspend allows system software to suspend a (multi) word/byte write to read data from any other flash memory array location. 1F0000 1EFFFF 1E0000 1DFFFF 1D0000 1CFFFF 1C0000 1BFFFF 1B0000 1AFFFF 1A0000 19FFFF 190000 18FFFF 180000 17FFFF 170000 16FFFF 160000 15FFFF 150000 14FFFF 140000 13FFFF 130000 12FFFF 120000 11FFFF 110000 10FFFF 100000 0FFFFF 0F0000 0EFFFF 0E0000 0DFFFF 0D0000 0CFFFF 0C0000 0BFFFF 0B0000 0AFFFF 0A0000 09FFFF 090000 08FFFF 080000 07FFFF 070000 06FFFF 060000 05FFFF 050000 04FFFF 040000 03FFFF 030000 02FFFF 020000 01FFFF 010000 00FFFF 64K-byte Block 31 64K-byte Block 30 64K-byte Block 29 64K-byte Block 28 64K-byte Block 27 64K-byte Block 26 64K-byte Block 25 64K-byte Block 24 64K-byte Block 23 64K-byte Block 22 64K-byte Block 21 64K-byte Block 20 64K-byte Block 19 64K-byte Block 18 64K-byte Block 17 64K-byte Block 16 64K-byte Block 15 64K-byte Block 14 64K-byte Block 13 64K-byte Block 12 64K-byte Block 11 64K-byte Block 10 64K-byte Block 9 64K-byte Block 8 64K-byte Block 7 64K-byte Block 6 64K-byte Block 5 64K-byte Block 4 64K-byte Block 3 64K-byte Block 2 64K-byte Block 1 64K-byte Block 0 000000 Figure 3. Memory Map Rev. 2.0 sharp 7 LHF16KA7 2.1 Data Protection 3.2 Output Disable Depending on the application, the system designer may choose to make the VPP power supply switchable (available only when block erase, full chip erase, (multi) word/byte write and block lock-bit configuration are required) or hardwired to VPPH1/2/3. The device accommodates either design practice and encourages optimization of the processor-memory interface. With OE# at a logic-high level (VIH), the device outputs are disabled. Output pins DQ0-DQ15 are placed in a high-impedance state. When VPPVPPLK, memory contents cannot be altered. The CUI, with multi-step block erase, full chip erase, (multi) word/byte write and block lock-bit configuration command sequences, provides protection from unwanted operations even when high voltage is applied to VPP. All write functions are disabled when VCC is below the write lockout voltage VLKO or when RP# is at VIL. The device's block locking capability provides additional protection from inadvertent code or data alteration by gating block erase, full chip erase and (multi) word/byte write operations. 3 BUS OPERATION The local CPU reads and writes flash memory insystem. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles. 3.1 Read Information can be read from any block, identifier codes, query structure, or status register independent of the VPP voltage. RP# must be at VIH. The first task is to write the appropriate read mode command (Read Array, Read Identifier Codes, Query or Read Status Register) to the CUI. Upon initial device power-up or after exit from deep power-down mode, the device automatically resets to read array mode. Five control pins dictate the data flow in and out of the component: CE# (CE0#, CE1#), OE#, WE#, RP# and WP#. CE0#, CE1# and OE# must be driven active to obtain data at the outputs. CE0#, CE1# is the device selection control, and when active enables the selected memory device. OE# is the data output (DQ0-DQ15) control and when active drives the selected memory data onto the I/O bus. WE# and RP# must be at VIH. Figure 17, 18 illustrates a read cycle. 3.3 Standby Either CE0# or CE1# at a logic-high level (VIH) places the device in standby mode which substantially reduces device power consumption. DQ0-DQ15 outputs are placed in a high-impedance state independent of OE#. If deselected during block erase, full chip erase, (multi) word/byte write and block lock-bit configuration, the device continues functioning, and consuming active power until the operation completes. 3.4 Deep Power-Down RP# at VIL initiates the deep power-down mode. In read modes, RP#-low deselects the memory, places output drivers in a high-impedance state and turns off all internal circuits. RP# must be held low for a minimum of 100 ns. Time tPHQV is required after return from power-down until initial memory access outputs are valid. After this wake-up interval, normal operation is restored. The CUI is reset to read array mode and status register is set to 80H. During block erase, full chip erase, (multi) word/byte write or block lock-bit configuration modes, RP#-low will abort the operation. STS remains low until the reset operation is complete. Memory contents being altered are no longer valid; the data may be partially erased or written. Time tPHWL is required after RP# goes to logic-high (VIH) before another command can be written. As with any automated device, it is important to assert RP# during system reset. When the system comes out of reset, it expects to read from the flash memory. Automated flash memories provide status information when accessed during block erase, full chip erase, (multi) word/byte write and block lock-bit configuration. If a CPU reset occurs with no flash memory reset, proper CPU initialization may not occur because the flash memory may be providing status information instead of array data. SHARP's flash memories allow proper CPU initialization following a system reset through the use of the RP# input. In this application, RP# is controlled by the same RESET# signal that resets the system CPU. Rev. 2.0 sharp LHF16KA7 8 3.5 Read Identifier Codes Operation 3.6 Query Operation The read identifier codes operation outputs the manufacturer code, device code, block status codes for each block (see Figure 4). Using the manufacturer and device codes, the system CPU can automatically match the device with its proper algorithms. The block status codes identify locked or unlocked block setting and erase completed or erase uncompleted condition. The query operation outputs the query structure. Query database is stored in the 48Byte ROM. Query structure allows system software to gain critical information for controlling the flash component. Query structure are always presented on the lowestorder data output (DQ0-DQ7) only. Writing commands to the CUI enable reading of device data and identifier codes. They also control inspection and clearing of the status register. When VCC=VCC1/2 and VPP=VPPH1/2/3, the CUI additionally controls block erase, full chip erase, (multi) word/byte write and block lock-bit configuration. 1FFFFF Reserved for Future Implementation 1F0006 1F0005 1F0004 1F0003 Block 31 Status Code Reserved for Future Implementation Block 31 1F0000 1EFFFF (Blocks 2 through 30) 020000 01FFFF 4 COMMAND DEFINITIONS Block 1 Status Code Reserved for Future Implementation Block 1 010000 00FFFF Reserved for Future Implementation 000006 000005 000004 000003 000002 000001 000000 The Block Erase command requires appropriate command data and an address within the block to be erased. The Word/byte Write command requires the command and address of the location to be written. Set Block Lock-Bit command requires the command and block address within the device (Block Lock) to be locked. The Clear Block Lock-Bits command requires the command and address within the device. The CUI does not occupy an addressable memory location. It is written when WE# and CE# are active. The address and data needed to execute a command are latched on the rising edge of WE# or CE# (whichever goes high first). Standard microprocessor write timings are used. Figures 19 and 20 illustrate WE# and CE#-controlled write operations. Reserved for Future Implementation 010006 010005 010004 010003 3.7 Write When the VPP voltage VPPLK, Read operations from the status register, identifier codes, query, or blocks are enabled. Placing VPPH1/2/3 on VPP enables successful block erase, full chip erase, (multi) word/byte write and block lock-bit configuration operations. Device operations are selected by writing specific commands into the CUI. Table 4 defines these commands. Block 0 Status Code Device Code Manufacturer Code Block 0 Figure 4. Device Identifier Code Memory Map Rev. 2.0 sharp Mode Read Output Disable Notes 1,2,3,9 3 Standby 3 Deep Power-Down Read Identifier Codes 4 Query 9 Write 3,7,8,9 Mode Read Output Disable 9 LHF16KA7 9 Notes 1,2,3,9 3 Standby 3 Deep Power-Down Read Identifier Codes 4 Query 9 9 Table 3. Bus Operations(BYTE#=VIH) RP# CE0# CE1# OE# WE# Address VIH VIL VIL VIL VIH X VIH VIL VIL VIH VIH X VIH VIH VIH VIH VIL X X X VIL VIH VIL X X X X X See VIH VIL VIL VIL VIH Figure 4 See Table VIH VIL VIL VIL VIH 7~11 VIH VIL VIL VIH VIL X Table 3.1. Bus Operations(BYTE#=VIL) RP# CE0# CE1# OE# WE# Address VIH VIL VIL VIL VIH X VIH VIL VIL VIH VIH X VIH VIH VIH VIH VIL X X X VIL VIH VIL X X X X X See VIH VIL VIL VIL VIH Figure 4 See Table VIH VIL VIL VIL VIH 7~11 VIH VIL VIL VIH VIL X VPP X X DQ0-15 DOUT High Z STS X X X High Z X X High Z High Z X Note 5 High Z X Note 6 High Z X DIN X VPP X X DQ0-7 DOUT High Z STS X X X High Z X X High Z High Z X Note 5 High Z X Note 6 High Z Write 3,7,8,9 X DIN X NOTES: 1. Refer to DC Characteristics. When VPPVPPLK, memory contents can be read, but not altered. 2. X can be VIL or VIH for control pins and addresses, and VPPLK or VPPH1/2/3 for VPP. See DC Characteristics for VPPLK and VPPH1/2/3 voltages. 3. STS is VOL (if configured to RY/BY# mode) when the WSM is executing internal block erase, full chip erase, (multi) word/byte write or block lock-bit configuration algorithms. It is floated during when the WSM is not busy, in block erase suspend mode with (multi) word/byte write inactive, (multi) word/byte write suspend mode, or deep power-down mode. 4. RP# at GND0.2V ensures the lowest deep power-down current. 5. See Section 4.2 for read identifier code data. 6. See Section 4.5 for query data. 7. Command writes involving block erase, full chip erase, (multi) word/byte write or block lock-bit configuration are reliably executed when VPP=VPPH1/2/3 and VCC=VCC1/2. 8. Refer to Table 4 for valid DIN during a write operation. 9. Don't use the timing both OE# and WE# are VIL. Rev. 2.0 sharp LHF16KA7 10 Table 4. Command Definitions(10) Bus Cycles Notes First Bus Cycle Req'd Oper(1) Addr(2) Data(3) 1 Write X FFH 4 Write X 90H 2 Write X 98H 2 2 Write X 70H 1 Write X 50H 2 5 Write BA 20H 2 Write X 30H 2 5,6 Write WA 40H Second Bus Cycle Command Oper(1) Addr(2) Data(3) Read Array/Reset Read Identifier Codes Read IA ID Query Read QA QD Read Status Register Read X SRD Clear Status Register Block Erase Setup/Confirm Write BA D0H Full Chip Erase Setup/Confirm Write X D0H Word/Byte Write Setup/Write Write WA WD Alternate Word/Byte Write 2 5,6 Write WA 10H Write WA WD Setup/Write Multi Word/Byte Write 4 9 Write WA E8H Write WA N-1 Setup/Confirm Block Erase and (Multi) 1 5 Write X B0H Word/byte Write Suspend Confirm and Block Erase and 1 5 Write X D0H (Multi) Word/byte Write Resume Block Lock-Bit Set Setup/Confirm 2 7 Write BA 60H Write BA 01H Block Lock-Bit Reset 2 8 Write X 60H Write X D0H Setup/Confirm STS Configuration 2 Write X B8H Write X 00H Level-Mode for Erase and Write (RY/BY# Mode) STS Configuration 2 Write X B8H Write X 01H Pulse-Mode for Erase STS Configuration 2 Write X B8H Write X 02H Pulse-Mode for Write STS Configuration 2 Write X B8H Write X 03H Pulse-Mode for Erase and Write NOTES: 1. BUS operations are defined in Table 3 and Table 3.1. 2. X=Any valid address within the device. IA=Identifier Code Address: see Figure 4. QA=Query Offset Address. BA=Address within the block being erased or locked. WA=Address of memory location to be written. 3. SRD=Data read from status register. See Table 14 for a description of the status register bits. WD=Data to be written at location WA. Data is latched on the rising edge of WE# or CE# (whichever goes high first). ID=Data read from identifier codes. QD=Data read from query database. 4. Following the Read Identifier Codes command, read operations access manufacturer, device and block status codes. See Section 4.2 for read identifier code data. 5. If the block is locked, WP# must be at VIH to enable block erase or (multi) word/byte write operations. Attempts to issue a block erase or (multi) word/byte write to a locked block while RP# is VIH. 6. Either 40H or 10H are recognized by the WSM as the byte write setup. 7. A block lock-bit can be set while WP# is VIH. 8. WP# must be at VIH to clear block lock-bits. The clear block lock-bits operation simultaneously clears all block lock-bits. 9. Following the Third Bus Cycle, inputs the write address and write data of 'N' times. Finally, input the confirm command 'D0H'. 10. Commands other than those shown above are reserved by SHARP for future device implementations and should not be used. Rev. 2.0 sharp 11 LHF16KA7 4.1 Read Array Command 4.3 Read Status Register Command Upon initial device power-up and after exit from deep power-down mode, the device defaults to read array mode. This operation is also initiated by writing the Read Array command. The device remains enabled for reads until another command is written. Once the internal WSM has started a block erase, full chip erase, (multi) word/byte write or block lock-bit configuration, the device will not recognize the Read Array command until the WSM completes its operation unless the WSM is suspended via an Erase Suspend and (Multi) Word/byte Write Suspend command. The Read Array command functions independently of the VPP voltage and RP# must be VIH. The status register may be read to determine when a block erase, full chip erase, (multi) word/byte write or block lock-bit configuration is complete and whether the operation completed successfully(see Table 14). It may be read at any time by writing the Read Status Register command. After writing this command, all subsequent read operations output data from the status register until another valid command is written. The status register contents are latched on the falling edge of OE# or CE#(Either CE0# or CE1#), whichever occurs. OE# or CE#(Either CE0# or CE1#) must toggle to VIH before further reads to update the status register latch. The Read Status Register command functions independently of the VPP voltage. RP# must be VIH. 4.2 Read Identifier Codes Command The identifier code operation is initiated by writing the Read Identifier Codes command. Following the command write, read cycles from addresses shown in Figure 4 retrieve the manufacturer, device, block lock configuration and block erase status (see Table 5 for identifier code values). To terminate the operation, write another valid command. Like the Read Array command, the Read Identifier Codes command functions independently of the VPP voltage and RP# must be VIH. Following the Read Identifier Codes command, the following information can be read: Table 5. Identifier Codes Code Address Data 00000 Manufacture Code B0 00001 00002 Device Code D0 00003 X0004(1) Block Status Code X0005(1) DQ0=0 *Block is Unlocked DQ0=1 *Block is Locked *Last erase operation DQ1=0 completed successfully *Last erase operation did DQ1=1 not completed successfully DQ2-7 *Reserved for Future Use NOTE: 1. X selects the specific block status code to be read. See Figure 4 for the device identifier code memory map. The extended status register may be read to determine multi word/byte write availability(see Table 14.1). The extended status register may be read at any time by writing the Multi Word/Byte Write command. After writing this command, all subsequent read operations output data from the extended status register, until another valid command is written. Multi Word/Byte Write command must be re-issued to update the extended status register latch. 4.4 Clear Status Register Command Status register bits SR.5, SR.4, SR.3 and SR.1 are set to "1"s by the WSM and can only be reset by the Clear Status Register command. These bits indicate various failure conditions (see Table 14). By allowing system software to reset these bits, several operations (such as cumulatively erasing or locking multiple blocks or writing several bytes in sequence) may be performed. The status register may be polled to determine if an error occurs during the sequence. To clear the status register, the Clear Status Register command (50H) is written. It functions independently of the applied VPP Voltage. RP# must be VIH. This command is not functional during block erase, full chip erase, (multi) word/byte write block lock-bit configuration, block erase suspend or (multi) word/byte write suspend modes. Rev. 2.0 sharp 12 LHF16KA7 4.5 Query Command Query database can be read by writing Query command (98H). Following the command write, read cycle from address shown in Table 7~11 retrieve the critical information to write, erase and otherwise control the flash component. A0 of query offset address is ignored when X8 mode (BYTE#=VIL). Query data are always presented on the low-byte data output (DQ0-DQ7). In x16 mode, high-byte (DQ8-DQ15) outputs 00H. The bytes not assigned to any information or reserved for future use are set to "0". This command functions independently of the VPP voltage. RP# must be VIH. Table 6. Example of Query Structure Output Mode Offset Address Output DQ15~8 DQ7~0 A 5, A 4, A 3, A 2, A 1, A 0 1 , 0 , 0 , 0 , 0 , 0 (20H) High Z "Q" "Q" X8 mode 1 , 0 , 0 , 0 , 0 , 1 (21H) High Z 1, 0 , 0 , 0 , 1 , 0 (22H) High Z "R" 1 , 0 , 0 , 0 , 1 , 1 (23H) High Z "R" A 5, A 4, A 3, A 2, A 1 X16 mode 1 , 0 , 0 , 0 , 0 (10H) 00H "Q" 1 , 0 , 0 , 0 , 1 (11H) 00H "R" 4.5.1 Block Status Register This field provides lock configuration and erase status for the specified block. These informations are only available when device is ready (SR.7=1). If block erase or full chip erase operation is finished irregulary, block erase status bit will be set to "1". If bit 1 is "1", this block is invalid. Table 7. Query Block Status Register Offset (Word Address) (BA+2)H Length 01H Description Block Status Register bit0 Block Lock Configuration 0=Block is unlocked 1=Block is Locked bit1 Block Erase Status 0=Last erase operation completed successfully 1=Last erase operation not completed successfully bit2-7 reserved for future use Note: 1. BA=The beginning of a Block Address. Rev. 2.0 sharp 13 LHF16KA7 4.5.2 CFI Query Identification String The Identification String provides verification that the component supports the Common Flash Interface specification. Additionally, it indicates which version of the spec and which Vendor-specified command set(s) is(are) supported. Table 8. CFI Query Identification String Offset (Word Address) 10H,11H,12H Length 03H 13H,14H 02H 15H,16H 02H 17H,18H 02H 19H,1AH 02H Description Query Unique ASCII string "QRY" 51H,52H,59H Primary Vendor Command Set and Control Interface ID Code 01H,00H (SCS ID Code) Address for Primary Algorithm Extended Query Table 31H,00H (SCS Extended Query Table Offset) Alternate Vendor Command Set and Control Interface ID Code 0000H (0000H means that no alternate exists) Address for Alternate Algorithm Extended Query Table 0000H (0000H means that no alternate exists) 4.5.3 System Interface Information The following device information can be useful in optimizing system interface software. Table 9. System Information String Offset (Word Address) 1BH Length 01H 1CH 01H 1DH 01H 1EH 01H 1FH 01H 20H 01H 21H 01H 22H 01H 23H 01H 24H 01H 25H 01H 26H 01H Description VCC Logic Supply Minimum Write/Erase voltage 27H (2.7V) VCC Logic Supply Maximum Write/Erase voltage 55H (5.5V) VPP Programming Supply Minimum Write/Erase voltage 27H (2.7V) VPP Programming Supply Maximum Write/Erase voltage 55H (5.5V) Typical Timeout per Single Byte/Word Write 03H (23=8s) Typical Timeout for Maximum Size Buffer Write (32 Bytes) 06H (26=64s) Typical Timeout per Individual Block Erase 0AH (0AH=10, 210=1024ms) Typical Timeout for Full Chip Erase 0FH (0FH=15, 215=32768ms) Maximum Timeout per Single Byte/Word Write, 2N times of typical. 04H (24=16, 8sx16=128s) Maximum Timeout Maximum Size Buffer Write, 2N times of typical. 04H (24=16, 64sx16=1024s) Maximum Timeout per Individual Block Erase, 2N times of typical. 04H (24=16, 1024msx16=16384ms) Maximum Timeout for Full Chip Erase, 2N times of typical. 04H (24=16, 32768msx16=524288ms) Rev. 2.0 sharp 14 LHF16KA7 4.5.4 Device Geometry Definition This field provides critical details of the flash device geometry. Table 10. Device Geometry Definition Offset (Word Address) 27H Length 01H 28H,29H 02H 2AH,2BH 02H 2CH 01H 2DH,2EH 02H 2FH,30H 02H Description Device Size 15H (15H=21, 221=2097152=2M Bytes) Flash Device Interface description 02H,00H (x8/x16 supports x8 and x16 via BYTE#) Maximum Number of Bytes in Multi word/byte write 05H,00H (25=32 Bytes ) Number of Erase Block Regions within device 01H (symmetrically blocked) The Number of Erase Blocks 1FH,00H (1FH=31 ==> 31+1=32 Blocks) The Number of "256 Bytes" cluster in a Erase block 00H,01H (0100H=256 ==>256 Bytes x 256= 64K Bytes in a Erase Block) 4.5.5 SCS OEM Specific Extended Query Table Certain flash features and commands may be optional in a vendor-specific algorithm specification. The optional vendor-specific Query table(s) may be used to specify this and other types of information. These structures are defined solely by the flash vendor(s). Table 11. SCS OEM Specific Extended Query Table Offset (Word Address) 31H,32H,33H 34H 35H 36H,37H, 38H,39H 3AH 3BH,3CH 3DH 3EH 3FH Length Description 03H PRI 50H,52H,49H 01H 31H (1) Major Version Number , ASCII 01H 30H (0) Minor Version Number, ASCII 04H 0FH,00H,00H,00H Optional Command Support bit0=1 : Chip Erase Supported bit1=1 : Suspend Erase Supported bit2=1 : Suspend Write Supported bit3=1 : Lock/Unlock Supported bit4=0 : Queued Erase Not Supported bit5-31=0 : reserved for future use 01H 01H Supported Functions after Suspend bit0=1 : Write Supported after Erase Suspend bit1-7=0 : reserved for future use 02H 03H,00H Block Status Register Mask bit0=1 : Block Status Register Lock Bit [BSR.0] active bit1=1 : Block Status Register Valid Bit [BSR.1] active bit2-15=0 : reserved for future use 01H VCC Logic Supply Optimum Write/Erase voltage(highest performance) 50H(5.0V) 01H VPP Programming Supply Optimum Write/Erase voltage(highest performance) 50H(5.0V) reserved Reserved for future versions of the SCS Specification Rev. 2.0 sharp LHF16KA7 4.6 Block Erase Command Block erase is executed one block at a time and initiated by a two-cycle command. A block erase setup is first written, followed by an block erase confirm. This command sequence requires appropriate sequencing and an address within the block to be erased (erase changes all block data to FFH). Block preconditioning, erase and verify are handled internally by the WSM (invisible to the system). After the two-cycle block erase sequence is written, the device automatically outputs status register data when read (see Figure 5). The CPU can detect block erase completion by analyzing the output data of the STS pin or status register bit SR.7. When the block erase is complete, status register bit SR.5 should be checked. If a block erase error is detected, the status register should be cleared before system software attempts corrective actions. The CUI remains in read status register mode until a new command is issued. This two-step command sequence of set-up followed by execution ensures that block contents are not accidentally erased. An invalid Block Erase command sequence will result in both status register bits SR.4 and SR.5 being set to "1". Also, reliable block erasure can only occur when VCC=VCC1/2 and VPP=VPPH1/2/3. In the absence of this high voltage, block contents are protected against erasure. If block erase is attempted while VPPVPPLK, SR.3 and SR.5 will be set to "1". Successful block erase requires that the corresponding block lock-bit be cleared or if set, that WP#=VIH. If block erase is attempted when the corresponding block lock-bit is set and WP#=VIL, SR.1 and SR.5 will be set to "1". 15 erase setup is first written, followed by a full chip erase confirm. After a confirm command is written, device erases the all unlocked blocks from block 0 to Block 31 block by block. This command sequence requires appropriate sequencing. Block preconditioning, erase and verify are handled internally by the WSM (invisible to the system). After the two-cycle full chip erase sequence is written, the device automatically outputs status register data when read (see Figure 6). The CPU can detect full chip erase completion by analyzing the output data of the STS pin or status register bit SR.7. When the full chip erase is complete, status register bit SR.5 should be checked. If erase error is detected, the status register should be cleared before system software attempts corrective actions. The CUI remains in read status register mode until a new command is issued. If error is detected on a block during full chip erase operation, WSM stops erasing. Reading the block valid status by issuing Read ID Codes command or Query command informs which blocks failed to its erase. This two-step command sequence of set-up followed by execution ensures that block contents are not accidentally erased. An invalid Full Chip Erase command sequence will result in both status register bits SR.4 and SR.5 being set to "1". Also, reliable full chip erasure can only occur when VCC=VCC1/2 and VPP=VPPH1/2/3. In the absence of this high voltage, block contents are protected against erasure. If full chip erase is attempted while VPPVPPLK, SR.3 and SR.5 will be set to "1". When WP#=VIH, all blocks are erased independent of block lock-bits status. When WP#=VIL, only unlocked blocks are erased. In this case, SR.1 and SR.5 will not be set to "1". Full chip erase can not be suspended. 4.7 Full Chip Erase Command This command followed by a confirm command (D0H) erases all of the unlocked blocks. A full chip Rev. 2.0 sharp LHF16KA7 4.8 Word/Byte Write Command Word/byte write is executed by a two-cycle command sequence. Word/Byte Write setup (standard 40H or alternate 10H) is written, followed by a second write that specifies the address and data (latched on the rising edge of WE#). The WSM then takes over, controlling the word/byte write and write verify algorithms internally. After the word/byte write sequence is written, the device automatically outputs status register data when read (see Figure 7). The CPU can detect the completion of the word/byte write event by analyzing the STS pin or status register bit SR.7. When word/byte write is complete, status register bit SR.4 should be checked. If word/byte write error is detected, the status register should be cleared. The internal WSM verify only detects errors for "1"s that do not successfully write to "0"s. The CUI remains in read status register mode until it receives another command. Reliable word/byte writes can only occur when VCC=VCC1/2 and VPP=VPPH1/2/3. In the absence of this high voltage, memory contents are protected against word/byte writes. If word/byte write is attempted while VPPVPPLK, status register bits SR.3 and SR.4 will be set to "1". Successful word/byte write requires that the corresponding block lock-bit be cleared or, if set, that WP#=VIH. If word/byte write is attempted when the corresponding block lock-bit is set and WP#=VIL, SR.1 and SR.4 will be set to "1". Word/byte write operations with VIL<WP#<VIH produce spurious results and should not be attempted. 4.9 Multi Word/Byte Write Command Multi word/byte write is executed by at least fourcycle or up to 35-cycle command sequence. Up to 32 bytes in x8 mode (16 words in x16 mode) can be loaded into the buffer and written to the Flash Array. First, multi word/byte write setup (E8H) is written with the write address. At this point, the device automatically outputs extended status register data (XSR) when read (see Figure 8, 9). If extended status register bit XSR.7 is 0, no Multi Word/Byte Write command is available and multi word/byte write setup which just has been written is ignored. To retry, 16 continue monitoring XSR.7 by writing multi word/byte write setup with write address until XSR.7 transitions to 1. When XSR.7 transitions to 1, the device is ready for loading the data to the buffer. A word/byte count (N)-1 is written with write address. After writing a word/byte count(N)-1, the device automatically turns back to output status register data. The word/byte count (N)-1 must be less than or equal to 1FH in x8 mode (0FH in x16 mode). On the next write, device start address is written with buffer data. Subsequent writes provide additional device address and data, depending on the count. All subsequent address must lie within the start address plus the count. After the final buffer data is written, write confirm (D0H) must be written. This initiates WSM to begin copying the buffer data to the Flash Array. An invalid Multi Word/Byte Write command sequence will result in both status register bits SR.4 and SR.5 being set to "1". For additional multi word/byte write, write another multi word/byte write setup and check XSR.7. The Multi Word/Byte Write command can be queued while WSM is busy as long as XSR.7 indicates "1", because LH28F160S3HT-L10A has two buffers. If an error occurs while writing, the device will stop writing and flush next multi word/byte write command loaded in multi word/byte write command. Status register bit SR.4 will be set to "1". No multi word/byte write command is available if either SR.4 or SR.5 are set to "1". SR.4 and SR.5 should be cleared before issuing multi word/byte write command. If a multi word/byte write command is attempted past an erase block boundary, the device will write the data to Flash Array up to an erase block boundary and then stop writing. Status register bits SR.4 and SR.5 will be set to "1". Reliable multi byte writes can only occur when VCC=VCC1/2 and VPP=VPPH1/2/3. In the absence of this high voltage, memory contents are protected against multi word/byte writes. If multi word/byte write is attempted while VPPVPPLK, status register bits SR.3 and SR.4 will be set to "1". Successful multi word/byte write requires that the corresponding block lock-bit be cleared or, if set, that WP#=VIH. If multi byte write is attempted when the corresponding block lock-bit is set and WP#=VIL, SR.1 and SR.4 will be set to "1". Rev. 2.0 sharp LHF16KA7 4.10 Block Erase Suspend Command The Block Erase Suspend command allows blockerase interruption to read or (multi) word/byte-write data in another block of memory. Once the blockerase process starts, writing the Block Erase Suspend command requests that the WSM suspend the block erase sequence at a predetermined point in the algorithm. The device outputs status register data when read after the Block Erase Suspend command is written. Polling status register bits SR.7 and SR.6 can determine when the block erase operation has been suspended (both will be set to "1"). STS will also transition to High Z. Specification tWHRH2 defines the block erase suspend latency. At this point, a Read Array command can be written to read data from blocks other than that which is suspended. A (Multi) Word/Byte Write command sequence can also be issued during erase suspend to program data in other blocks. Using the (Multi) Word/Byte Write Suspend command (see Section 4.11), a (multi) word/byte write operation can also be suspended. During a (multi) word/byte write operation with block erase suspended, status register bit SR.7 will return to "0" and the STS (if set to RY/BY#) output will transition to VOL. However, SR.6 will remain "1" to indicate block erase suspend status. The only other valid commands while block erase is suspended are Read Status Register and Block Erase Resume. After a Block Erase Resume command is written to the flash memory, the WSM will continue the block erase process. Status register bits SR.6 and SR.7 will automatically clear and STS will return to VOL. After the Erase Resume command is written, the device automatically outputs status register data when read (see Figure 10). VPP must remain at VPPH1/2/3 (the same VPP level used for block erase) while block erase is suspended. RP# must also remain at VIH. WP# must also remain at the same level used for block erase. BYTE# must be the same level as writing the Block Erase command when the Block Erase Resume command is written. Block erase cannot resume until (multi) word/byte 17 write operations initiated during block erase suspend have completed. 4.11 (Multi) Word/Byte Write Suspend Command The (Multi) Word/Byte Write Suspend command allows (multi) word/byte write interruption to read data in other flash memory locations. Once the (multi) word/byte write process starts, writing the (Multi) Word/Byte Write Suspend command requests that the WSM suspend the (multi) word/byte write sequence at a predetermined point in the algorithm. The device continues to output status register data when read after the (Multi) Word/Byte Write Suspend command is written. Polling status register bits SR.7 and SR.2 can determine when the (multi) word/byte write operation has been suspended (both will be set to "1"). STS will also transition to High Z. Specification tWHRH1 defines the (multi) word/byte write suspend latency. At this point, a Read Array command can be written to read data from locations other than that which is suspended. The only other valid commands while (multi) word/byte write is suspended are Read Status Register and (Multi) Word/Byte Write Resume. After (Multi) Word/Byte Write Resume command is written to the flash memory, the WSM will continue the (multi) word/byte write process. Status register bits SR.2 and SR.7 will automatically clear and STS will return to VOL. After the (Multi) Word/Byte Write command is written, the device automatically outputs status register data when read (see Figure 11). VPP must remain at VPPH1/2/3 (the same VPP level used for (multi) word/byte write) while in (multi) word/byte write suspend mode. RP# must also remain at VIH. WP# must also remain at the same level used for (multi) word/byte write. BYTE# must be the same level as writing the (Multi) Word/Byte Write command when the (Multi) Word/Byte Write Resume command is written. Rev. 2.0 sharp LHF16KA7 4.12 Set Block Lock-Bit Command A flexible block locking and unlocking scheme is enabled via block lock-bits. The block lock-bits gate program and erase operations With WP#=VIH, individual block lock-bits can be set using the Set Block Lock-Bit command. See Table 13 for a summary of hardware and software write protection options. Set block lock-bit is executed by a two-cycle command sequence. The set block lock-bit setup along with appropriate block or device address is written followed by either the set block lock-bit confirm (and an address within the block to be locked). The WSM then controls the set block lock-bit algorithm. After the sequence is written, the device automatically outputs status register data when read (see Figure 12). The CPU can detect the completion of the set block lock-bit event by analyzing the STS pin output or status register bit SR.7. When the set block lock-bit operation is complete, status register bit SR.4 should be checked. If an error is detected, the status register should be cleared. The CUI will remain in read status register mode until a new command is issued. This two-step sequence of set-up followed by execution ensures that block lock-bits are not accidentally set. An invalid Set Block Lock-Bit command will result in status register bits SR.4 and SR.5 being set to "1". Also, reliable operations occur only when VCC=VCC1/2 and VPP=VPPH1/2/3. In the absence of this high voltage, block lock-bit contents are protected against alteration. A successful set block lock-bit operation requires WP#=VIH. If it is attempted with WP#=VIL, SR.1 and SR.4 will be set to "1" and the operation will fail. Set block lock-bit operations with WP#<VIH produce spurious results and should not be attempted. 18 block lock-bits can be cleared using only the Clear Block Lock-Bits command. See Table 13 for a summary of hardware and software write protection options. Clear block lock-bits operation is executed by a twocycle command sequence. A clear block lock-bits setup is first written. After the command is written, the device automatically outputs status register data when read (see Figure 13). The CPU can detect completion of the clear block lock-bits event by analyzing the STS Pin output or status register bit SR.7. When the operation is complete, status register bit SR.5 should be checked. If a clear block lock-bit error is detected, the status register should be cleared. The CUI will remain in read status register mode until another command is issued. This two-step sequence of set-up followed by execution ensures that block lock-bits are not accidentally cleared. An invalid Clear Block Lock-Bits command sequence will result in status register bits SR.4 and SR.5 being set to "1". Also, a reliable clear block lock-bits operation can only occur when VCC=VCC1/2 and VPP=VPPH1/2/3. If a clear block lockbits operation is attempted while VPPVPPLK, SR.3 and SR.5 will be set to "1". In the absence of this high voltage, the block lock-bits content are protected against alteration. A successful clear block lock-bits operation requires WP#=VIH. If it is attempted with WP#=VIL, SR.1 and SR.5 will be set to "1" and the operation will fail. Clear block lock-bits operations with VIH<RP# produce spurious results and should not be attempted. If a clear block lock-bits operation is aborted due to VPP or VCC transitioning out of valid range or RP# active transition, block lock-bit values are left in an undetermined state. A repeat of clear block lock-bits is required to initialize block lock-bit contents to known values. 4.13 Clear Block Lock-Bits Command All set block lock-bits are cleared in parallel via the Clear Block Lock-Bits command. With WP#=VIH, Rev. 2.0 sharp 19 LHF16KA7 4.14 STS Configuration Command The Status (STS) pin can be configured to different states using the STS Configuration command. Once the STS pin has been configured, it remains in that configuration until another configuration command is issued, the device is powered down or RP# is set to VIL. Upon initial device power-up and after exit from deep power-down mode, the STS pin defaults to RY/BY# operation where STS low indicates that the WSM is busy. STS High Z indicates that the WSM is ready for a new operation. To reconfigure the STS pin to other modes, the STS Configuration is issued followed by the appropriate configuration code. The three alternate configurations are all pulse mode for use as a system interrupt. The STS Configuration command functions independently of the VPP voltage and RP# must be VIH. Table 12. STS Configuration Coding Description Configuration Effects Bits Set STS pin to default level mode (RY/BY#). RY/BY# in the default 00H level-mode of operation will indicate WSM status condition. Set STS pin to pulsed output signal for specific erase operation. In this mode, STS provides low pulse at 01H the completion of BLock Erase, Full Chip Erase and Clear Block Lock-bits operations. Set STS pin to pulsed output signal for a specific write operation. In this 02H mode, STS provides low pulse at the completion of (Multi) Byte Write and Set Block Lock-bit operation. Set STS pin to pulsed output signal for specific write and erase operation. STS provides low pulse 03H at the completion of Block Erase, Full Chip Erase, (Multi) Word/Byte Write and Block Lock-bit Configuration operations. Table 13. Write Protection Alternatives Operation Block Erase, (Multi) Word/Byte Write Block Lock-Bit 0 VIL or VIH 1 VIL WP# VIH Full Chip Erase Set Block Lock-Bit Clear Block Lock-Bits 0,1 X X X VIL VIH VIL VIH VIL VIH Effect Block Erase and (Multi) Word/Byte Write Enabled Block is Locked. Block Erase and (Multi) Word/Byte Write Disabled Block Lock-Bit Override. Block Erase and (Multi) Word/Byte Write Enabled All unlocked blocks are erased, locked blocks are not erased All blocks are erased Set Block Lock-Bit Disabled Set Block Lock-Bit Enabled Clear Block Lock-Bits Disabled Clear Block Lock-Bits Enabled Rev. 2.0 sharp 20 LHF16KA7 WSMS BESS 7 6 Table 14. Status Register Definition ECBLBS WSBLBS VPPS WSS 5 4 3 2 DPS R 1 0 NOTES: SR.7 = WRITE STATE MACHINE STATUS 1 = Ready 0 = Busy Check STS or SR.7 to determine block erase, full chip erase, (multi) word/byte write or block lock-bit configuration completion. SR.6-0 are invalid while SR.7="0". SR.6 = BLOCK ERASE SUSPEND STATUS 1 = Block Erase Suspended 0 = Block Erase in Progress/Completed SR.5 = ERASE AND CLEAR BLOCK LOCK-BITS STATUS 1 = Error in Erase or Clear Blocl Lock-Bits 0 = Successful Erase or Clear Block Lock-Bits SR.4 = WRITE AND SET BLOCK LOCK-BIT STATUS 1 = Error in Write or Set Block Lock-Bit 0 = Successful Write or Set Block Lock-Bit SR.3 = VPP STATUS 1 = VPP Low Detect, Operation Abort 0 = VPP OK SR.2 = WRITE SUSPEND STATUS 1 = Write Suspended 0 = Write in Progress/Completed SR.1 = DEVICE PROTECT STATUS 1 = Block Lock-Bit and/or WP# Lock Detected, Operation Abort 0 = Unlock If both SR.5 and SR.4 are "1"s after a block erase, full chip erase, (multi) word/byte write, block lock-bit configuration or STS configuration attempt, an improper command sequence was entered. SR.3 does not provide a continuous indication of VPP level. The WSM interrogates and indicates the VPP level only after block erase, full chip erase, (multi) word/byte write or block lock-bit configuration command sequences. SR.3 is not guaranteed to reports accurate feedback only when VPPVPPH1/2/3. SR.1 does not provide a continuous indication of block lock-bit values. The WSM interrogates block lock-bit, and WP# only after block erase, full chip erase, (multi) word/byte write or block lock-bit configuration command sequences. It informs the system, depending on the attempted operation, if the block lock-bit is set and/or WP# is not VIH. Reading the block lock configuration codes after writing the Read Identifier Codes command indicates block lock-bit status. SR.0 is reserved for future use and should be masked out when polling the status register. SR.0 = RESERVED FOR FUTURE ENHANCEMENTS SMS R 7 6 Table 14.1. Extended Status Register Definition R R R R 5 4 3 2 R R 1 0 NOTES: XSR.7 = STATE MACHINE STATUS 1 = Multi Word/Byte Write available 0 = Multi Word/Byte Write not available After issue a Multi Word/Byte Write command: XSR.7 indicates that a next Multi Word/Byte Write command is available. XSR.6-0=RESERVED FOR FUTURE ENHANCEMENTS XSR.6-0 is reserved for future use and should be masked out when polling the extended status register. Rev. 2.0 sharp 21 LHF16KA7 Start Write 70H Read Status Bus Operation Command Write Read Status Register Data=70H Addr=X Status Register Data Read Register Comments Check SR.7 Standby 0 SR.7= 1 Write 20H, Block Address 1=WSM Ready 0=WSM Busy Write Erase Setup Data=20H Addr=Within Block to be Erased Write Erase Confirm Data=D0H Addr=Within Block to be Erased Write D0H, Block Address Status Register Data Read Read Status Check SR.7 Register Suspend Block Erase Loop No 0 SR.7= Suspend Block Erase Standby 1=WSM Ready 0=WSM Busy Repeat for subsequent block erasures. Yes Full status check can be done after each block erase or after a sequence of block erasures. 1 Write FFH after the last operation to place device in read array mode. Full Status Check if Desired Block Erase Complete FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above) Bus Operation Command Standby 1 VPP Range Error SR.3= Comments Check SR.3 1=VPP Error Detect Check SR.1 1=Device Protect Detect 0 Standby 1 Device Protect Error SR.1= 0 Standby 1 SR.4,5= Command Sequence Error 0 Standby WP#=VIL,Block Lock-Bit is Set Only required for systems implementing lock-bit configuration Check SR.4,5 Both 1=Command Sequence Error Check SR.5 1=Block Erase Error SR.5,SR.4,SR.3 and SR.1 are only cleared by the Clear Status Register Command in cases where multiple blocks are erased 1 SR.5= Block Erase Error before full status is checked. If error is detected, clear the Status Register before attempting retry or other error recovery. 0 Block Erase Successful Figure 5. Automated Block Erase Flowchart Rev. 2.0 sharp 22 LHF16KA7 Start Write 70H Read Status Bus Operation Command Write Read Status Register Data=70H Addr=X Status Register Data Read Register Comments Check SR.7 SR.7= Standby 0 1 Write Write 30H Write Write D0H 1=WSM Ready 0=WSM Busy Setup Data=30H Addr=X Full Chip Erase Confirm Data=D0H Addr=X Full Chip Erase Status Register Data Read Read Status Check SR.7 SR.7= 1=WSM Ready 0=WSM Busy Standby Register Full status check can be done after each full chip erase. 0 Write FFH after the last operation to place device in read array mode. 1 Full Status Check if Desired Full Chip Erase Complete FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above) Bus Operation Command Standby 1 VPP Range Error SR.3= Standby 0 1 SR.4,5= Command Sequence Standby Error Comments Check SR.3 1=VPP Error Detect Check SR.4,5 Both 1=Command Sequence Error Check SR.5 1=Full Chip Erase Error SR.5,SR.4,SR.3 and SR.1 are only cleared by the Clear Status 0 Register Command in cases where multiple blocks are erased 1 SR.5= Full Chip Erase Error before full status is checked. If error is detected, clear the Status Register before attempting retry or other error recovery. 0 Full Chip Erase Successful Figure 6. Automated Full Chip Erase Flowchart Rev. 2.0 sharp 23 LHF16KA7 Start Bus Operation Command Write 70H Write Read Status Register Read Status Register Read Comments Data=70H Addr=X Status Register Data Check SR.7 Standby SR.7= 1=WSM Ready 0=WSM Busy 0 Write Setup Word/Byte Write Data=40H or 10H Addr=Location to Be Written Write 40H or 10H, Address Write Word/Byte Write Data=Data to Be Written Addr=Location to Be Written Write Word/Byte Data and Address Read 1 Read Status Register Check SR.7 Suspend Word/Byte No SR.7= Status Register Data 1=WSM Ready 0=WSM Busy Write Loop Suspend Word/Byte Write 0 Standby Repeat for subsequent word/byte writes. Yes 1 SR full status check can be done after each word/byte write, or after a sequence of word/byte writes. Write FFH after the last word/byte write operation to place device in read array mode. Full Status Check if Desired Word/byte Write Complete FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above) Bus Operation Command Standby 1 VPP Range Error SR.3= Standby 1 Device Protect Error SR.1= 0 Standby 1 0 Word/Byte Write Successful Check SR.3 1=VPP Error Detect Check SR.1 1=Device Protect Detect 0 SR.4= Comments Word/byte Write Error WP#=VIL,Block Lock-Bit is Set Only required for systems implementing lock-bit configuration Check SR.4 1=Data Write Error SR.4,SR.3 and SR.1 are only cleared by the Clear Status Register command in cases where multiple locations are written before full status is checked. If error is detected, clear the Status Register before attempting retry or other error recovery. Figure 7. Automated Word/byte Write Flowchart Rev. 2.0 sharp 24 LHF16KA7 Start Write E8H, Start Address Bus Operation Read Extend Status Register Write Command Setup Multi Word/Byte Write Comments Data=E8H Addr=Start Address No 0 Write Buffer Time Out XSR.7= Read Extended Status Register Data Standby 1=Multi Word/Byte Write Ready 0=Multi Word/Byte Write Busy Write (Note1) Data=Word or Byte Count (N)-1 Addr=Start Address Write (Note2,3) Data=Buffer Data Addr=Start Address Write (Note4,5) Data=Buffer Data Addr=Device Address Yes 1 Check XSR.7 Write Word or Byte Count (N)-1, Start Address Write Buffer Data, Start Address X=1 Yes Write Data=D0H Addr=X Read Status Register Data X=N No Check SR.7 Yes Abort Buffer Write Commnad? Write Another Block Address No Multi Word/Byte Write Abort Write Buffer Data, Device Address Standby 1=WSM Ready 0=WSM Busy 1. Byte or word count values on DQ0-7 are loaded into the count register. 2. Write Buffer contents will be programmed at the start address. 3. Align the start address on a Write Buffer boundary for maximum programming performance. 4.The device aborts the Multi Word/Byte Write command if the current address is outside of the original block address. 5.The Status Register indicates an "improper command sequence" if the Multi Word/Byte command is aborted. Follow this with a Clear Status Register command. SR full status check can be done after each multi word/byte write, X=X+1 or after a sequence of multi word/byte writes. Write D0H Write FFH after the last multi word/byte write operation to place device in read array mode. Another Buffer Write ? Yes No Read Status Register No SR.7= 0 Suspend Multi Word/Byte Write Loop Suspend Yes Multi Word/Byte Write 1 Full Status Check if Desired Multi Word/Byte Write Complete Figure 8. Automated Multi Word/Byte Write Flowchart Rev. 2.0 sharp 25 LHF16KA7 FULL STATUS CHECK PROCEDURE FOR MULTI WORD/BYTE WRITE OPERATION Bus Read Status Register Operation Standby 1 Command Comments Check SR.3 1=VPP Error Detect VPP Range Error SR.3= Check SR.1 1=Device Protect Detect 0 Standby 1 SR.1= Device Protect Error Standby 0 1 SR.4,5= Command Sequence Error Standby WP#=VIL,Block Lock-Bit is Set Only required for systems implementing lock-bit configuration Check SR.4,5 Both 1=Command Sequence Error Check SR.4 1=Data Write Error SR.5,SR.4,SR.3 and SR.1 are only cleared by the Clear Status Register command in cases where multiple locations are written before 0 1 SR.4= Multi Word/Byte Write Error full status is checked. If error is detected, clear the Status Register before attempting retry or other error recovery. 0 Multi Word/Byte Write Successful Figure 9. Full Status Check Procedure for Automated Multi Word/Byte Write Rev. 2.0 sharp 26 LHF16KA7 Start Bus Operation Write Write B0H Command Erase Suspend Comments Data=B0H Addr=X Status Register Data Read Addr=X Read Status Register Check SR.7 1=WSM Ready Standby 0=WSM Busy 0 SR.7= Check SR.6 1=Block Erase Suspended Standby 0=Block Erase Completed 1 Write 0 SR.6= Erase Resume Data=D0H Addr=X Block Erase Completed 1 Read Read or Write ? Read Array Data (Multi) Word/Byte Write (Multi) Word/Byte Write Loop No Done? Yes Write D0H Write FFH Block Erase Resumed Read Array Data Figure 10. Block Erase Suspend/Resume Flowchart Rev. 2.0 sharp 27 LHF16KA7 Start Bus Operation Write B0H Write Command (Multi) Word/Byte Write Suspend Data=B0H Addr=X Status Register Data Read Read Status Register Comments Addr=X Check SR.7 1=WSM Ready Standby 0=WSM Busy SR.7= 0 Check SR.2 1=(Multi) Word/Byte Write 1 Suspended 0=(Multi) Word/Byte Write Standby Completed SR.2= 0 (Multi) Word/Byte Write Completed Write Read Array Data=FFH Addr=X 1 Read Array locations other Read than that being written. Write FFH Write (Multi) Word/Byte Write Resume Data=D0H Addr=X Read Array Data Done No Reading Yes Write D0H Write FFH (Multi) Word/Byte Write Resumed Read Array Data Figure 11. (Multi) Word/Byte Write Suspend/Resume Flowchart Rev. 2.0 sharp 28 LHF16KA7 Start Bus Operation Write 60H, Write Block Address Command Set Block Lock-Bit Setup Write 01H, Set Block Block Address Write Lock-Bit Confirm Comments Data=60H Addr=Block Address Data=01H, Addr=Block Address Read Status Register SR.7= Status Register Data Read Check SR.7 0 Standby 1=WSM Ready 0=WSM Busy 1 Repeat for subsequent block lock-bit set operations. Full status check can be done after each block lock-bit set operation Full Status Check if Desired or after a sequence of block lock-bit set operations. Write FFH after the last block lock-bit set operation to place device in read array mode. Set Block Lock-Bit Complete FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above) Bus Operation Command Standby 1 Comments Check SR.3 1=VPP Error Detect VPP Range Error SR.3= 0 Standby Check SR.1 1=Device Protect Detect WP#=VIL Standby Both 1=Command Check SR.4,5 1 Device Protect Error SR.1= Sequence Error 0 Standby 1 SR.4,5= Command Sequence Error Check SR.4 1=Set Block Lock-Bit Error SR.5,SR.4,SR.3 and SR.1 are only cleared by the Clear Status Register command in cases where multiple block lock-bits are set before full status is checked. 0 If error is detected, clear the Status Register before attempting retry or other error recovery. 1 SR.4= Set Block Lock-Bit Error 0 Set Block Lock-Bit Successful Figure 12. Set Block Lock-Bit Flowchart Rev. 2.0 sharp 29 LHF16KA7 Start Write 60H Bus Operation Command Write Clear Block Lock-Bits Setup Data=60H Addr=X Clear Block Data=D0H Addr=X Write Lock-Bits Confirm Comments Write D0H Read Status Register Data Read Status Register Check SR.7 Standby SR.7= 0 1=WSM Ready 0=WSM Busy Write FFH after the Clear Block Lock-Bits operation to place device in read array mode. 1 Full Status Check if Desired Clear Block Lock-Bits Complete FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above) Bus Operation Command Standby 1 Comments Check SR.3 1=VPP Error Detect VPP Range Error SR.3= Standby 0 Check SR.1 1=Device Protect Detect WP#=VIL Check SR.4,5 1 Device Protect Error SR.1= Standby Both 1=Command Sequence Error 0 Standby 1 SR.4,5= Command Sequence Error Check SR.5 1=Clear Block Lock-Bits Error SR.5,SR.4,SR.3 and SR.1 are only cleared by the Clear Status Register command. If error is detected, clear the Status Register before attempting 0 retry or other error recovery. 1 SR.5= Clear Block Lock-Bits Error 0 Clear Block Lock-Bits Successful Figure 13. Clear Block Lock-Bits Flowchart Rev. 2.0 sharp LHF16KA7 5 DESIGN CONSIDERATIONS 5.1 Three-Line Output Control The device will often be used in large memory arrays. SHARP provides three control inputs to accommodate multiple memory connections. ThreeLine control provides for: a. Lowest possible memory power dissipation. b. Complete assurance that data bus contention will not occur. To use these control inputs efficiently, an address decoder should enable CE# while OE# should be connected to all memory devices and the system's READ# control line. This assures that only selected memory devices have active outputs while deselected memory devices are in standby mode. RP# should be connected to the system POWERGOOD signal to prevent unintended writes during system power transitions. POWERGOOD should also toggle during system reset. 5.2 STS and Block Erase, Full Chip Erase, (Multi) Word/Byte Write and Block Lock-Bit Configuration Polling STS is an open drain output that should be connected to VCC by a pullup resistor to provide a hardware method of detecting block erase, full chip erase, (multi) word/byte write and block lock-bit configuration completion. In default mode, it transitions low after block erase, full chip erase, (multi) word/byte write or block lock-bit configuration commands and returns to VOH when the WSM has finished executing the internal algorithm. For alternate STS pin configurations, see the Configuration command. 30 STS, in default mode, is also High Z when the device is in block erase suspend (with (multi) word/byte write inactive), (multi) word/byte write suspend or deep power-down modes. 5.3 Power Supply Decoupling Flash memory power switching characteristics require careful device decoupling. System designers are interested in three supply current issues; standby current levels, active current levels and transient peaks produced by falling and rising edges of CE# and OE#. Transient current magnitudes depend on the device outputs' capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. Each device should have a 0.1F ceramic capacitor connected between its VCC and GND and between its VPP and GND. These high-frequency, low inductance capacitors should be placed as close as possible to package leads. Additionally, for every eight devices, a 4.7F electrolytic capacitor should be placed at the array's power supply connection between VCC and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace inductance. 5.4 VPP Trace on Printed Circuit Boards Updating flash memories that reside in the target system requires that the printed circuit board designer pay attention to the VPP Power supply trace. The VPP pin supplies the memory cell current for block erase, full chip erase, (multi) word/byte write and block lock-bit configuration. Use similar trace widths and layout considerations given to the VCC power bus. Adequate VPP supply traces and decoupling will decrease VPP voltage spikes and overshoots. STS can be connected to an interrupt input of the system CPU or controller. It is active at all times. Rev. 2.0 sharp LHF16KA7 5.5 VCC, VPP, RP# Transitions Block erase, full chip erase, (multi) word/byte write and block lock-bit configuration are not guaranteed if VPP falls outside of a valid VPPH1/2/3 range, VCC falls outside of a valid VCC1/2 range, or RP#=VIL. If VPP error is detected, status register bit SR.3 is set to "1" along with SR.4 or SR.5, depending on the attempted operation. If RP# transitions to VIL during block erase, full chip erase, (multi) word/byte write or block lock-bit configuration, STS(if set to RY/BY# mode) will remain low until the reset operation is complete. Then, the operation will abort and the device will enter deep power-down. The aborted operation may leave data partially altered. Therefore, the command sequence must be repeated after normal operation is restored. Device power-off or RP# transitions to VIL clear the status register. The CUI latches commands issued by system software and is not altered by VPP or CE# transitions or WSM actions. Its state is read array mode upon power-up, after exit from deep power-down or after VCC transitions below VLKO. After block erase, full chip erase, (multi) word/byte write or block lock-bit configuration, even after VPP transitions down to VPPLK, the CUI must be placed in read array mode via the Read Array command if subsequent access to the memory array is desired. 5.6 Power-Up/Down Protection The device is designed to offer protection against accidental block and full chip erasure, (multi) word/byte writing or block lock-bit configuration during power transitions. Upon power-up, the device is indifferent as to which power supply (VPP or VCC) 31 powers-up first. Internal circuitry resets the CUI to read array mode at power-up. A system designer must guard against spurious writes for VCC voltages above VLKO when VPP is active. Since both WE# and CE# must be low for a command write, driving either to VIH will inhibit writes. The CUI's two-step command sequence architecture provides added level of protection against data alteration. In-system block lock and unlock capability prevents inadvertent data alteration. The device is disabled while RP#=VIL regardless of its control inputs state. 5.7 Power Dissipation When designing portable systems, designers must consider battery power consumption not only during device operation, but also for data retention during system idle time. Flash memory's nonvolatility increases usable battery life because data is retained when system power is removed. In addition, deep power-down mode ensures extremely low power consumption even when system power is applied. For example, portable computing products and other power sensitive applications that use an array of devices for solid-state storage can consume negligible power by lowering RP# to VIL standby or sleep modes. If access is again needed, the devices can be read following the tPHQV and tPHWL wake-up cycles required after RP# is first raised to VIH. See AC Characteristics Read Only and Write Operations and Figures 17, 18, 19, 20 for more information. Rev. 2.0 sharp 32 LHF16KA7 6 ELECTRICAL SPECIFICATIONS 6.1 Absolute Maximum Ratings* Operating Temperature During Read, Erase, Write and Block Lock-Bit Configuration .....-40C to +85C(1) Temperature under Bias............... -40C to +85C Storage Temperature........................ -65C to +125C Voltage On Any Pin (except VCC, VPP)............... -0.5V to VCC+0.5V(2) VCC Suply Voltage ............................-0.2V to +7.0V(2) VPP Update Voltage during Erase, Write and Block Lock-Bit Configuration ......-0.2V to +7.0V(2) *WARNING: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability. NOTES: 1. Operating temperature is for extended temperature product defined by this specification. 2. All specified voltages are with respect to GND. Minimum DC voltage is -0.5V on input/output pins and -0.2V on VCC and VPP pins. During transitions, this level may undershoot to -2.0V for periods <20ns. Maximum DC voltage on input/output pins and VCC is VCC+0.5V which, during transitions, may overshoot to VCC+2.0V for periods <20ns. 3. Output shorted for no more than one second. No more than one output shorted at a time. Output Short Circuit Current ........................ 100mA(3) 6.2 Operating Conditions Temperature and VCC Operating Conditions Symbol Parameter Min. Max. Unit TA Operating Temperature -40 +85 C VCC1 VCC Supply Voltage (2.7V-3.6V) 2.7 3.6 V VCC2 VCC Supply Voltage (3.3V0.3V) 3.0 3.6 V Test Condition Ambient Temperature 6.2.1 CAPACITANCE(1) Symbol Parameter CIN Input Capacitance COUT Output Capacitance NOTE: 1. Sampled, not 100% tested. TA=+25C, f=1MHz Typ. Max. 7 10 9 12 Unit pF pF Condition VIN=0.0V VOUT=0.0V Rev. 2.0 sharp 33 LHF16KA7 6.2.2 AC INPUT/OUTPUT TEST CONDITIONS 2.7 1.35 INPUT TEST POINTS 1.35 OUTPUT 0.0 AC test inputs are driven at 2.7V for a Logic "1" and 0.0V for a Logic "0." Input timing begins, and output timing ends, at 1.35V. Input rise and fall times (10% to 90%) <10 ns. Figure 14. Transient Input/Output Reference Waveform for VCC=2.7V-3.6V 3.0 INPUT TEST POINTS 1.5 1.5 OUTPUT 0.0 AC test inputs are driven at 3.0V for a Logic "1" and 0.0V for a Logic "0." Input timing begins, and output timing ends, at 1.5V. Input rise and fall times (10% to 90%) <10 ns. Figure 15. Transient Input/Output Reference Waveform for VCC=3.3V0.3V Test Configuration Capacitance Loading Value Test Configuration CL(pF) VCC=3.3V0.3V, 2.7V-3.6V 50 1.3V 1N914 RL=3.3k DEVICE UNDER TEST CL Includes Jig Capacitance OUT CL Figure 16. Transient Equivalent Testing Load Circuit Rev. 2.0 sharp 34 LHF16KA7 6.2.3 DC CHARACTERISTICS Sym. Parameter ILI Input Load Current ILO Output Leakage Current ICCS VCC Standby Current ICCD ICCR ICCW ICCE ICCWS ICCES IPPS IPPR IPPD IPPW IPPE IPPWS IPPES VCC Deep Power-Down Current VCC Read Current VCC Write Current ((Multi) W/B Write or Set Block Lock Bit) VCC Erase Current (Block Erase, Full Chip Erase, Clear Block Lock Bits) VCC Write or Block Erase Suspend Current VPP Standby Current VPP Read Current VPP Deep Power-Down Current VPP Write Current ((Multi) W/B Write or Set Block Lock Bit) VPP Erase Current (Block Erase, Full Chip Erase, Clear Block Lock Bits) VPP Write or Block Erase Suspend Current DC Characteristics VCC=2.7V VCC=3.3V Notes Typ. Max. Typ. Max. 1 0.5 0.5 20 100 20 100 A 1 4 1 4 mA 20 20 A 25 25 mA 30 30 mA 17 17 17 17 mA mA mA mA mA mA Test Conditions VCC=VCCMax. VIN=VCC or GND VCC=VCCMax. VOUT=VCC or GND CMOS Inputs VCC=VCCMax. CE#=RP#=VCC0.2V TTL Inputs VCC=VCCMax. CE#=RP#=VIH RP#=GND0.2V IOUT(STS)=0mA CMOS Inputs VCC=VCCMax. CE#=GND f=5MHz, IOUT=0mA TTL Inputs VCC=VCCMax., CE#=VIL f=5MHz, IOUT=0mA VPP=2.7V-3.6V VPP=3.3V0.3V VPP=5.0V0.5V VPP=2.7V-3.6V VPP=3.3V0.3V VPP=5.0V0.5V 1 0.5 Unit A 0.5 A 1,3,6 1 1,5,6 17 17 17 17 17 17 1 6 1 6 mA CE#=VIH 2 10 15 200 2 10 15 200 A A VPPVCC VPP>VCC 0.1 5 0.1 5 A RP#=GND0.2V 80 80 80 40 40 40 80 80 40 40 mA mA mA mA mA mA VPP=2.7V-3.6V VPP=3.3V0.3V VPP=5.0V0.5V VPP=2.7V-3.6V VPP=3.3V0.3V VPP=5.0V0.5V 200 10 200 A VPP=VPPH1/2/3 1,7 1,7 1,2 1 1 1 1,7 1,7 1 10 Rev. 2.0 sharp Sym. Parameter VIL Input Low Voltage VIH Input High Voltage VOL Output Low Voltage VOH1 Output High Voltage (TTL) Output High Voltage (CMOS) VOH2 35 LHF16KA7 DC Characteristics (Continued) VCC=2.7V VCC=3.3V Notes Min. Max. Min. Max. 7 -0.5 0.8 -0.5 0.8 7 VCC VCC 2.0 2.0 +0.5 +0.5 3,7 0.4 0.4 3,7 3,7 2.4 2.4 0.85 VCC VCC -0.4 0.85 VCC VCC -0.4 Unit V Test Conditions V V V V V VCC=VCCMin. IOL=2mA VCC=VCCMin. IOH=-2.5mA VCC=VCCMin. IOH=-2.5mA VCC=VCCMin. IOH=-100A VPPLK VPP Lockout Voltage during 4,7 1.5 1.5 V Normal Operations VPPH1 VPP Voltage during Write or 2.7 3.6 V Erase Operations VPPH2 VPP Voltage during Write or 3.0 3.6 3.0 3.6 V Erase Operations VPPH3 VPP Voltage during Write or 4.5 5.5 4.5 5.5 V Erase Operations VLKO VCC Lockout Voltage 2.0 2.0 V NOTES: 1. All currents are in RMS unless otherwise noted. Typical values at nominal VCC voltage and TA=+25C. 2. ICCWS and ICCES are specified with the device de-selected. If read or byte written while in erase suspend mode, the device's current draw is the sum of ICCWS or ICCES and ICCR or ICCW, respectively. 3. Includes STS. 4. Block erases, full chip erases, (multi) word/byte writes and block lock-bit configurations are inhibited when VPPVPPLK, and not guaranteed in the range between VPPLK(max.) and VPPH1(min.), between VPPH1(max.) and VPPH2(min.), between VPPH2(max.) and VPPH3(min.) and above VPPH3(max.). 5. Automatic Power Savings (APS) reduces typical ICCR to 3mA at 2.7V and 3.3V VCC in static operation. 6. CMOS inputs are either VCC0.2V or GND0.2V. TTL inputs are either VIL or VIH. 7. Sampled, not 100% tested. Rev. 2.0 sharp 36 LHF16KA7 6.2.4 AC CHARACTERISTICS - READ-ONLY OPERATIONS(1) Sym. tAVAV tAVQV tELQV tPHQV tGLQV tELQX tEHQZ tGLQX tGHQZ tOH VCC=2.7V-3.6V, TA=-40C to +85C Versions(4) Parameter Notes Read Cycle Time Address to Output Delay CE# to Output Delay RP# High to Output Delay OE# to Output Delay CE# to Output in Low Z CE# High to Output in High Z OE# to Output in Low Z OE# High to Output in High Z Output Hold from Address, CE# or OE# Change, Whichever Occurs First tFLQV BYTE# to Output Delay tFHQV tFLQZ BYTE# to Output in High Z tELFL CE# Low to BYTE# High or Low tELFH NOTE: See 3.3V VCC Read-Only Operations for notes 1 through 4. Sym. tAVAV tAVQV tELQV tPHQV tGLQV tELQX tEHQZ tGLQX tGHQZ tOH 2 2 3 3 3 3 3 0 Unit ns ns ns ns ns ns ns ns ns ns 3 120 ns 3 30 ns 3 5 ns VCC=3.3V0.3V, TA=-40C to +85C Versions(4) Parameter Notes Read Cycle Time Address to Output Delay CE# to Output Delay RP# High to Output Delay OE# to Output Delay CE# to Output in Low Z CE# High to Output in High Z OE# to Output in Low Z OE# High to Output in High Z Output Hold from Address, CE# or OE# Change, Whichever Occurs First LH28F160S3H-L120 Min. Max. 120 120 120 600 50 0 50 0 20 2 2 3 3 3 3 3 LH28F160S3H-L100 Min. Max. 100 100 100 600 45 0 50 0 20 0 tFLQV BYTE# to Output Delay 3 100 tFHQV tFLQZ BYTE# to Output in High Z 3 30 tELFL CE# Low to BYTE# High or Low 3 5 tELFH NOTES: 1. See AC Input/Output Reference Waveform for maximum allowable input slew rate. 2. OE# may be delayed up to tELQV-tGLQV after the falling edge of CE# without impact on tELQV. 3. Sampled, not 100% tested. 4. See Ordering Information for device speeds (valid operational combinations). Unit ns ns ns ns ns ns ns ns ns ns ns ns ns Rev. 2.0 sharp VIH 37 LHF16KA7 Standby Device Address Selection Data Valid Address Stable ADDRESSES(A) VIL tAVAV VIH CE#(E) tEHQZ VIL VIH OE#(G) tGHQZ VIL VIH WE#(W) tGLQV VIL tELQV tOH tGLQX tELQX VOH DATA(D/Q) HIGH Z Valid Output VOL HIGH Z tAVQV VCC tPHQV VIH RP#(P) VIL NOTE: CE# is defined as the latter of CE0# and CE1# going Low or the first of CE0# or CE1# going High. Figure 17. AC Waveform for Read Operations Rev. 2.0 sharp VIH 38 LHF16KA7 Standby Device Address Selection Data Valid Address Stable ADDRESSES(A) VIL tAVAV VIH CE#(E) tEHQZ VIL tAVFL=tELFL VIH OE#(G) tGHQZ tELFL VIL tFLQV=tAVQV VIH BYTE#(F) tGLQV VIL tELQV tGLQX tELQX VOH DATA(D/Q) (DQ0-DQ7) HIGH Z VOL tOH Data Output Valid Output HIGH Z tAVQV tFLQZ VOH DATA(D/Q) (DQ8-DQ15) HIGH Z Data Output HIGH Z VOL NOTE: CE# is defined as the latter of CE0# and CE1# going Low or the first of CE0# or CE1# going High. Figure 18. BYTE# Timing Waveforms Rev. 2.0 sharp 39 LHF16KA7 6.2.5 AC CHARACTERISTICS - WRITE OPERATIONS(1) Sym. VCC=2.7V-3.6V, TA=-40C to +85C Versions(5) Parameter Notes tAVAV Write Cycle Time tPHWL RP# High Recovery to WE# Going Low tELWL CE# Setup to WE# Going Low tWLWH WE# Pulse Width tSHWH WP# VIH Setup to WE# Going High tVPWH VPP Setup to WE# Going High tAVWH Address Setup to WE# Going High tDVWH Data Setup to WE# Going High tWHDX Data Hold from WE# High tWHAX Address Hold from WE# High tWHEH CE# Hold from WE# High tWHWL WE# Pulse Width High tWHRL WE# High to STS Going Low tWHGL Write Recovery before Read tQVVL VPP Hold from Valid SRD, STS High Z tQVSL WP# VIH Hold from Valid SRD, STS High Z tFVWH BYTE# Setup to WE# Going High tWHFV BYTE# Hold from WE# High NOTE: See 3.3V VCC WE#-Controlled Writes for notes 1 through 6. 2 2 2 3 3 2,4 2,4 LH28F160S3H-L120 Min. Max. 120 1 10 50 100 100 50 50 5 5 10 30 100 0 0 0 50 NOTE 6 Unit ns s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Rev. 2.0 sharp Sym. 40 LHF16KA7 VCC=3.3V0.3V, TA=-40C to +85C Versions(5) Parameter Notes LH28F160S3H-L100 Min. Max. 100 1 10 50 100 100 50 50 5 5 10 30 100 0 0 0 50 NOTE 6 Unit tAVAV Write Cycle Time ns tPHWL RP# High Recovery to WE# Going Low 2 s tELWL CE# Setup to WE# Going Low ns tWLWH WE# Pulse Width ns tSHWH WP# VIH Setup to WE# Going High 2 ns tVPWH VPP Setup to WE# Going High 2 ns tAVWH Address Setup to WE# Going High 3 ns tDVWH Data Setup to WE# Going High 3 ns tWHDX Data Hold from WE# High ns tWHAX Address Hold from WE# High ns tWHEH CE# Hold from WE# High ns tWHWL WE# Pulse Width High ns tWHRL WE# High to STS Going Low ns tWHGL Write Recovery before Read ns tQVVL VPP Hold from Valid SRD, STS High Z 2,4 ns tQVSL WP# VIH Hold from Valid SRD, STS High Z 2,4 ns tFVWH BYTE# Setup to WE# Going High ns tWHFV BYTE# Hold from WE# High ns NOTES: 1. Read timing characteristics during block erase, full chip erase, (multi) wrod/byte write and block lock-bit configuration operations are the same as during read-only operations. Refer to AC Characteristics for read-only operations. 2. Sampled, not 100% tested. 3. Refer to Table 4 for valid AIN and DIN for block erase, full chip erase, (multi) word/byte write or block lock-bit configuration. 4. VPP should be held at VPPH1/2/3 until determination of block erase, full chip erase, (multi) word/byte write or block lock-bit configuration success (SR.1/3/4/5=0). 5. See Ordering Information for device speeds (valid operational combinations). 6. BYTE# should be in stable until determination of block erase, full chip erase, (multi) word/byte write, block lockbit configuration or STS configuration success (SR.7=1). Rev. 2.0 sharp 41 LHF16KA7 2 3 4 5 AIN ADDRESSES(A) } } AIN VIL tWHAX tAVWH tAVAV VIH 6 } } } } 1 VIH CE#(E) VIL tELWL tWHEH tWHGL VIH OE#(G) VIL tWHQV1,2,3,4 tWHWL VIH WE#(W) VIL VIH DATA(D/Q) High Z tWLWH tDVWH tWHDX DIN Valid SRD DIN VIL tPHWL tFVWH DIN tWHFV VIH BYTE#(F) VIL tWHRL High Z STS(R) VOL tSHWH tQVSL VIH WP#(S) VIL VIH RP#(P) VIL tVPWH VPPH3,2,1 tQVVL VPP(V) VPPLK VIL NOTES: 1. VCC power-up and standby. 2. Write each setup command. 3. Write each confirm command or valid address and data. 4. Automated erase or program delay. 5. Read status register data. 6. Write Read Array command. 7. CE# is defined as the latter of CE0# and CE1# going Low or the first of CE0# or CE1# going High. Figure 19. AC Waveform for WE#-Controlled Write Operations Rev. 2.0 sharp 42 LHF16KA7 6.2.6 ALTERNATIVE CE#-CONTROLLED WRITES(1) Sym. VCC=2.7V-3.6V, TA=-40C to +85C Versions(5) Parameter Notes tAVAV Write Cycle Time tPHEL RP# High Recovery to CE# Going Low 2 tWLEL WE# Setup to CE# Going Low tELEH CE# Pulse Width tSHEH WP# VIH Setup to CE# Going High 2 tVPEH VPP Setup to CE# Going High 2 tAVEH Address Setup to CE# Going High 3 tDVEH Data Setup to CE# Going High 3 tEHDX Data Hold from CE# High tEHAX Address Hold from CE# High tEHWH WE# Hold from CE# High tEHEL CE# Pulse Width High tEHRL CE# High to STS Going Low tEHGL Write Recovery before Read tQVVL VPP Hold from Valid SRD, STS High Z 2,4 tQVSL WP# VIH Hold from Valid SRD, STS High Z 2,4 tFVEH BYTE# Setup to CE# Going HIgh tEHFV BYTE# Hold from CE# High NOTE: See 3.3V VCC Alternative CE#-Controlled Writes for notes 1 through 6. LH28F160S3H-L120 Min. Max. 120 1 0 70 100 100 50 50 5 5 0 25 100 0 0 0 50 NOTE 6 Unit ns s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Rev. 2.0 sharp Sym. 43 LHF16KA7 VCC=3.3V0.3V, TA=-40C to +85C Versions(5) Parameter Notes LH28F160S3H-L100 Min. Max. 100 1 0 70 100 100 50 50 5 5 0 25 100 0 0 0 50 NOTE 6 Unit tAVAV Write Cycle Time ns tPHEL RP# High Recovery to CE# Going Low 2 s tWLEL WE# Setup to CE# Going Low ns tELEH CE# Pulse Width ns tSHEH WP# VIH Setup to CE# Going High 2 ns tVPEH VPP Setup to CE# Going High 2 ns tAVEH Address Setup to CE# Going High 3 ns tDVEH Data Setup to CE# Going High 3 ns tEHDX Data Hold from CE# High ns tEHAX Address Hold from CE# High ns tEHWH WE# Hold from CE# High ns tEHEL CE# Pulse Width High ns tEHRL CE# High to STS Going Low ns tEHGL Write Recovery before Read ns tQVVL VPP Hold from Valid SRD, STS High Z 2,4 ns tQVSL WP# VIH Hold from Valid SRD, STS High Z 2,4 ns tFVEH BYTE# Setup to CE# Going High ns tEHFV BYTE# Hold from CE# High ns NOTES: 1. In systems where CE# defines the write pulse width (within a longer WE# timing waveform), all setup, hold and inactive WE# times should be measured relative to the CE# waveform. 2. Sampled, not 100% tested. 3. Refer to Table 4 for valid AIN and DIN for block erase, full chip erase, (multi) word/byte write or block lock-bit configuration. 4. VPP should be held at VPPH1/2/3 until determination of block erase, full chip erase, (multi) word/byte write or block lock-bit configuration success (SR.1/3/4/5=0). 5. See Ordering Information for device speeds (valid operational combinations). 6. BYTE# should be in stable until determination of block erase, full chip erase, (multi) word/byte write, block lockbit configuration or STS configuration success (SR.7=1). Rev. 2.0 sharp 44 LHF16KA7 2 3 5 4 AIN } } VIH ADDRESSES(A) 6 } } } } 1 AIN VIL tEHAX tAVEH tAVAV VIH tEHEL CE#(E) VIL tELEH tDVEH VIH tEHGL OE#(G) VIL VIH WE#(W) VIL VIH DATA(D/Q) High Z tEHQV1,2,3,4 tEHWH tEHDX tWLEL Valid SRD DIN DIN VIL tPHEL tFVEH DIN tEHFV VIH BYTE#(F) VIL tEHRL High Z STS(R) VOL tSHEH tQVSL VIH WP#(S) VIL VIH RP#(P) VIL tVPEH VPPH3,2,1 tQVVL VPP(V) VPPLK VIL NOTES: 1. VCC power-up and standby. 2. Write each setup command. 3. Write each confirm command or valid address and data. 4. Automated erase or program delay. 5. Read status register data. 6. Write Read Array command. 7. CE# is defined as the latter of CE0# and CE1# going Low or the first of CE0# or CE1# going High. Figure 20. AC Waveform for CE#-Controlled Write Operations Rev. 2.0 sharp LHF16KA7 45 6.2.7 RESET OPERATIONS High Z STS(R) VOL VIH RP#(P) VIL tPLPH (A)Reset During Read Array Mode High Z STS(R) VOL tPLRH VIH RP#(P) VIL tPLPH (B)Reset During Block Erase, Full Chip Erase, (Multi) Word/Byte Write or Block Lock-Bit Configuretion 2.7/3.3V VCC VIL t23VPH VIH RP#(P) VIL (C)VCC Power Up Timing Figure 21. AC Waveform for Reset Operation Reset AC Specifications VCC=2.7V Notes Min. Max. VCC=3.3V Symbol Parameter Min. Max. Unit tPLPH RP# Pulse Low Time (If RP# is tied to VCC, this specification is 100 100 ns not applicable) tPLRH RP# Low to Reset during Block Erase, 1,2 21.5 21.1 s Full Chip Erase, (Multi) Word/Byte Write or Block Lock-Bit Configuration t23VPH VCC at 2.7V to RP# High 3 100 100 ns VCC at 3.0V to RP# High NOTES: 1. If RP# is asserted while a block erase, full chip erase, (multi) word/byte write or block lock-bit configuration operation is not executing, the reset will complete within 100ns. 2. A reset time, tPHQV, is required from the latter of STS going High Z or RP# going high until outputs are valid. 3. When the device power-up, holding RP# low minimum 100ns is required after VCC has been in predefined range and also has been in stable there. Rev. 2.0 sharp 46 LHF16KA7 6.2.8 BLOCK ERASE, FULL CHIP ERASE, (MULTI) WORD/BYTE WRITE AND BLOCK LOCK-BIT CONFIGURATION PERFORMANCE(3) Sym. tWHQV1 tEHQV1 tWHQV1 tEHQV1 tWHQV2 tEHQV2 Parameter Word/Byte Write Time (using W/B write, in word mode) Word/Byte Write Time (using W/B write, in byte mode) Word/Byte Write Time (using multi word/byte write) Block Write Time (using W/B write, in word mode) Block Write Time (using W/B write, in byte mode) Block Write Time (using multi word/byte write) Block Erase Time VCC=2.7V-3.6V, TA=-40C to +85C VPP=2.7V-3.6V VPP=3.0V-3.6V (1) Notes Typ. Max. Typ.(1) Max. VPP=4.5V-5.5V Typ.(1) Max. Unit 2 22.19 250 22.19 250 13.2 180 s 2 19.9 250 19.9 250 13.2 180 s 2 5.76 250 5.76 250 2.76 180 s 2 0.73 8.2 0.73 8.2 0.44 4.8 s 2 1.31 16.5 1.31 16.5 0.87 10.9 s 2 0.37 4.1 0.37 4.1 0.18 2 s 2 0.56 10 0.56 10 0.42 10 s Full Chip Erase Time 17.9 320 17.9 320 13.4 320 s tWHQV3 Set Block Lock-Bit Time 2 22.17 250 22.17 250 13.2 180 s tEHQV3 tWHQV4 Clear Block Lock-Bits Time 2 0.56 10 0.56 10 0.42 10 s tEHQV4 tWHRH1 Write Suspend Latency Time 7.24 10.2 7.24 10.2 6.73 9.48 s tEHRH1 to Read tWHRH2 Erase Suspend Latency 15.5 21.5 15.5 21.5 12.54 17.54 s tEHRH2 Time to Read NOTE: See 3.3V VCC Block Erase, Full Chip Erase, (Multi) Word/Byte Write and Block Lock-Bit Configuration Performance for notes 1 through 3. Rev. 2.0 sharp Sym. tWHQV1 tEHQV1 tWHQV1 tEHQV1 tWHQV2 tEHQV2 47 LHF16KA7 VCC=3.3V0.3V, TA=-40C to +85C VPP=3.0V-3.6V Notes Typ.(1) Max. Parameter Word/Byte Write Time (using W/B write, in word mode) Word/Byte Write Time (using W/B write, in byte mode) Word/Byte Write Time (using multi word/byte write) Block Write Time (using W/B write, in word mode) Block Write Time (using W/B write, in byte mode) Block Write Time (using multi word/byte write) Block Erase Time VPP=4.5V-5.5V Typ.(1) Max. Unit 2 21.75 250 12.95 180 s 2 19.51 250 12.95 180 s 2 5.66 250 2.7 180 s 2 0.72 8.2 0.43 4.8 s 2 1.28 16.5 0.85 10.9 s 2 0.36 4.1 0.18 2 s 2 0.55 10 0.41 10 s Full Chip Erase Time 17.6 320 13.1 320 s tWHQV3 Set Block Lock-Bit Time 2 21.75 250 12.95 180 s tEHQV3 tWHQV4 Clear Block Lock-Bits Time 2 0.55 10 0.41 10 s tEHQV4 tWHRH1 Write Suspend Latency Time to Read 7.1 10 6.6 9.3 s tEHRH1 tWHRH2 Erase Suspend Latency Time to Read 15.2 21.1 12.3 17.2 s tEHRH2 NOTES: 1. Typical values measured at TA=+25C and nominal voltages. Assumes corresponding block lock-bits are not set. Subject to change based on device characterization. 2. Excludes system-level overhead. 3. Sampled but not 100% tested. Rev. 2.0 sharp 48 LHF16KA7 7 ADDITIONAL INFORMATION 7.1 Ordering Information Product line designator for all SHARP Flash products L H2 8F 1 6 0S3HT - L 1 0A Device Density 160 = 16-Mbit Architecture S = Regular Block Power Supply Type 3 = Smart 3 Technology Operating Temperature Blank = 0C ~ +70C H = -40C ~ +85C Option Order Code 1 LH28F160S3HT-L10A Access Speed (ns) 10:100ns (3.3V), 120ns (2.7V) 13:130ns (3.3V), 150ns (2.7V) Package T = 56-Lead TSOP R = 56-Lead TSOP(Reverse Bend) NS = 56-Lead SSOP B = 64-Ball CSP D = 64-Lead SDIP Valid Operational Combinations VCC=2.7V-3.6V VCC=3.3V0.3V 50pF load, 50pF load, 1.35V I/O Levels 1.5V I/O Levels LH28F160S3H-L120 LH28F160S3H-L100 Rev. 2.0 sharp Flash memory LHFXXKXX family Data Protection Noises having a level exceeding the limit specified in this document may be generated under specific operating conditions on some systems. Such noises, when induced onto WE# signal or power supply, may be interpreted as false commands, causing undesired memory updating. To protect the data stored in the flash memory against unwanted overwriting, systems operating with the flash memory should have the following write protect designs, as appropriate: 1) Protecting data in specific block Setting the lock bit of the desired block and pulling WP# low disables the writing operation on that block. By using this feature, the flash memory space can be divided into, for example, the program section (locked section) and data section (unlocked section). By controlling WP#, desired blocks can be locked/unlocked through the software. For further information on setting/resetting lock bit, refer to the chapter 4.12 and 4.13. 2) Data protection through VPP When the level of VPP is lower than VPPLK (lockout voltage), write operation on the flash memory is disabled. All blocks are locked and the data in the blocks are completely write protected. For the lockout voltage, refer to the chapter 6.2.3. 3) Data protection through RP# When the RP# is kept low during power up and power down sequence such as voltage transition, write operation on the flash memory is disabled, write protecting all blocks. For the details of RP# control, refer to the chapter 5.6 and 6.2.7. Rev. 1.90 sharp i A-1 RECOMMENDED OPERATING CONDITIONS A-1.1 At Device Power-Up AC timing illustrated in Figure A-1 is recommended for the supply voltages and the control signals at device power-up. If the timing in the figure is ignored, the device may not operate correctly. VCC(min) VCC GND tVR t2VPH *1 tR tPHQV VIH RP# (P) (RST#) VCCW *2 (V) VIL VCCWH1/2 (VPPH1/2) GND (VPP) tR or tF tR or tF tAVQV VIH Valid Address ADDRESS (A) VIL tF tR tELQV VIH CE# (E) VIL VIH WE# (W) VIL tF tR tGLQV VIH OE# (G) VIL VIH WP# (S) VIL VOH DATA (D/Q) VOL High Z Valid Output *1 t5VPH for the device in 5V operations. *2 To prevent the unwanted writes, system designers should consider the VCCW (VPP) switch, which connects VCCW (VPP) to GND during read operations and VCCWH1/2 (VPPH1/2) during write or erase operations. See the application note AP-007-SW-E for details. Figure A-1. AC Timing at Device Power-Up For the AC specifications tVR, tR, tF in the figure, refer to the next page. See the "ELECTRICAL SPECIFICATIONS" described in specifications for the supply voltage range, the operating temperature and the AC specifications not shown in the next page. Rev. 1.10 sharp ii A-1.1.1 Rise and Fall Time Symbol Parameter Notes Min. Max. Unit 1 0.5 30000 s/V tVR VCC Rise Time tR Input Signal Rise Time 1, 2 1 s/V tF Input Signal Fall Time 1, 2 1 s/V NOTES: 1. Sampled, not 100% tested. 2. This specification is applied for not only the device power-up but also the normal operations. tR(Max.) and tF(Max.) for RP# (RST#) are 100s/V. Rev. 1.10 sharp iii A-1.2 Glitch Noises Do not input the glitch noises which are below VIH (Min.) or above VIL (Max.) on address, data, reset, and control signals, as shown in Figure A-2 (b). The acceptable glitch noises are illustrated in Figure A-2 (a). Input Signal Input Signal VIH (Min.) VIH (Min.) VIL (Max.) VIL (Max.) Input Signal Input Signal (a) Acceptable Glitch Noises (b) NOT Acceptable Glitch Noises Figure A-2. Waveform for Glitch Noises See the "DC CHARACTERISTICS" described in specifications for VIH (Min.) and VIL (Max.). Rev. 1.10 sharp iv A-2 RELATED DOCUMENT INFORMATION(1) Document No. Document Name AP-001-SD-E Flash Memory Family Software Drivers AP-006-PT-E Data Protection Method of SHARP Flash Memory AP-007-SW-E RP#, VPP Electric Potential Switching Circuit NOTE: 1. International customers should contact their local SHARP or distribution sales office. Rev. 1.10 SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. Suggested applications (if any) are for standard use; See Important Restrictions for limitations on special applications. See Limited Warranty for SHARP's product warranty. The Limited Warranty is in lieu, and exclusive of, all other warranties, express or implied. ALL EXPRESS AND IMPLIED WARRANTIES, INCLUDING THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR USE AND FITNESS FOR A PARTICULAR PURPOSE, ARE SPECIFICALLY EXCLUDED. In no event will SHARP be liable, or in any way responsible, for any incidental or consequential economic or property damage. NORTH AMERICA EUROPE JAPAN SHARP Microelectronics of the Americas 5700 NW Pacific Rim Blvd. Camas, WA 98607, U.S.A. Phone: (1) 360-834-2500 Fax: (1) 360-834-8903 Fast Info: (1) 800-833-9437 www.sharpsma.com SHARP Microelectronics Europe Division of Sharp Electronics (Europe) GmbH Sonninstrasse 3 20097 Hamburg, Germany Phone: (49) 40-2376-2286 Fax: (49) 40-2376-2232 www.sharpsme.com SHARP Corporation Electronic Components & Devices 22-22 Nagaike-cho, Abeno-Ku Osaka 545-8522, Japan Phone: (81) 6-6621-1221 Fax: (81) 6117-725300/6117-725301 www.sharp-world.com TAIWAN SINGAPORE KOREA SHARP Electronic Components (Taiwan) Corporation 8F-A, No. 16, Sec. 4, Nanking E. Rd. Taipei, Taiwan, Republic of China Phone: (886) 2-2577-7341 Fax: (886) 2-2577-7326/2-2577-7328 SHARP Electronics (Singapore) PTE., Ltd. 438A, Alexandra Road, #05-01/02 Alexandra Technopark, Singapore 119967 Phone: (65) 271-3566 Fax: (65) 271-3855 SHARP Electronic Components (Korea) Corporation RM 501 Geosung B/D, 541 Dohwa-dong, Mapo-ku Seoul 121-701, Korea Phone: (82) 2-711-5813 ~ 8 Fax: (82) 2-711-5819 CHINA HONG KONG SHARP Microelectronics of China (Shanghai) Co., Ltd. 28 Xin Jin Qiao Road King Tower 16F Pudong Shanghai, 201206 P.R. China Phone: (86) 21-5854-7710/21-5834-6056 Fax: (86) 21-5854-4340/21-5834-6057 Head Office: No. 360, Bashen Road, Xin Development Bldg. 22 Waigaoqiao Free Trade Zone Shanghai 200131 P.R. China Email: smc@china.global.sharp.co.jp SHARP-ROXY (Hong Kong) Ltd. 3rd Business Division, 17/F, Admiralty Centre, Tower 1 18 Harcourt Road, Hong Kong Phone: (852) 28229311 Fax: (852) 28660779 www.sharp.com.hk Shenzhen Representative Office: Room 13B1, Tower C, Electronics Science & Technology Building Shen Nan Zhong Road Shenzhen, P.R. China Phone: (86) 755-3273731 Fax: (86) 755-3273735