AOZ1050PI - ALPHA & OMEGA SEMICONDUCTORS

Rev. 1.0 June 2011 www.aosmd.com Page 1 of 14

AOZ1050PI

EZBuck™ 2 A Synchronous Buck Regulator

General Description

The AOZ1050PI is a high efficiency, easy to use, 2 A

synchronous buck regulator . The AOZ1050PI works from

4.5 V to 18 V input volt ag e rang e, and provide s up to 2 A

of continuous output current with an output voltage

adjustable down to 0.8 V.

The AOZ1050PI comes in an exposed pad SO-8

package and is rated over a -40 °C to +85 °C operating

ambient temperature range.

Features

z4.5 V to 18 V operating input voltage range

zSynchronous Buck: 80 mΩ internal high-side switch

and 50 mΩ internal low-side switch (at 12 V)

zUp to 95 % efficiency

zExternal soft start

zOutput voltage adjustable to 0.8 V

z2 A continuous output current

z500 kHz PWM operation

zCycle-by-cycle current limit

zPre-bias start-up

zShort-circuit protection

zThermal shutdown

zExposed pad SO-8 package

Applications

zPoint of load DC/DC converters

zLCD TV

zSet top boxes

zDVD and Blu-ray players/recorders

zCable modems

Typical Application

Figure 1. 3.3 V 2 A Synchronous Buck Regulator, Fs = 500 kHz

VIN

VOUT

PGND

COMP

AGND

C2, C3

22µF

CSS

10µF

L1 4.7µH

AOZ1050PI

Not Recommended For New Designs

Replacement Parts:

AOZ6662DI

AOZ6682CI

AOZ1050PI

Rev. 1.0 June 2011 www.aosmd.com Page 2 of 14

Ordering Information

AOS Green Products use reduced levels of Halogens, and are also RoHS compliant.

Please visit www.aosmd.com/web/quality/rohs_compliant.jsp for additional information.

Pin Configuration

Pin Description

Part Number Ambient Temperature Range Package Environmental

AOZ1050PI -40 °C to +85 °C EPAD SO-8 Green Product

PGND

VIN

GND

Exposed Pad SO-8

(Top View)

PAD

(LX)

COMP

Pin Number Pin Name Pin Function

1 PGND Power ground. PGND needs to be electrically connected to AGND.

2 VIN Supply voltage input. When VIN rises above the UVLO threshold and EN is logic high,

the device starts up.

3 AGND Analog ground. AGND is the reference point for controller section. AGND needs to be

electrically connected to PGND.

4 FB Feedback input. The FB pin is used to set the output voltage via a resistive voltage divider

between the output and AGND.

5 COMP External loop compensation pin. Connect a RC network between COMP and AGND to

compensate the control loop.

6 EN Enable pin. Pull EN to logic high to enable the device. Pull EN to logic low to disable the

device. If on/off control in not needed, connect EN to VIN and do not leave it open.

7 SS Soft-start pin. 5 µA current charging current.

8 NC No Connect Pin. Pin 8 is not internally connected. Connect this pin externally to LX and

use it for better thermal performance.

Exposed pad LX Switching node. LX is the drai n of the internal PFET. LX is used as the thermal pad of the

power stage.

Not Recommended For New Designs

AOZ1050PI

Rev. 1.0 June 2011 www.aosmd.com Page 3 of 14

Block Diagram

Absolute Maximum Ratings

Exceeding the Absolute Maximum Ratings may da mage the

device.

Note:

1. Devices are inherently ESD sensitive, handling precautions are

required. Human body model rating: 1.5 kΩ in series with 100 pF.

Recommended Operating Conditions

The device is not guaranteed to operate beyond the Maximum

Recommended Operating Conditions.

Note:

2. The value of ΘJA is measured with the device mounted on a 1-in2

FR-4 board with 2 oz. Copper, in a still air environment with

TA = 25 °C. The value in any given application depends on the

user’s specific board design.

500kHz

Oscillator

AGND PGND

VIN

COMP

OTP

Internal

+5V

ILimit

PWM

Control

Logic

5V LDO

Regulator

UVLO

& POR

Softstart

Reference

& Bias

0.8V

5µA

PWM

Comp

Level

Shifter

FET

Driver

ISen

EAmp

–

Parameter Rating

Supply Voltage (VIN) 20 V

LX to AGND -0.7 V to VIN+0.3 V

LX to AGND (20 ns) -5 V to 22 V

EN to AGND -0.3 V to VIN+0.3 V

FB, SS, COMP to AGND -0.3 V to 6.0 V

PGND to AGND -0.3 V to +0.3 V

Junction Temperature (TJ) +150 °C

Storage Temperature (TS) -65 °C to +150 °C

ESD Rating(1) 2.0 kV

Parameter Rating

Supply Voltage (VIN) 4.5 V to 18 V

Output Voltage Range 0.8 V to 0.85 • VIN

Ambient Temperature (TA) -40 °C to +85 °C

Package Thermal Resistance

Exposed Pad SO-8 (ΘJA)(2) 50 °C/W

Not Recommended For New Designs

AOZ1050PI

Rev. 1.0 June 2011 www.aosmd.com Page 4 of 14

Electrical Characteristics

TA = 25 °C, VIN = VEN = 12 V, VOUT = 3.3 V unless otherwise specified(3)

Note:

3. Specification in BOLD indicate an ambient temper ature range of -40 °C to +85 °C. These specifications are guaranteed by design.

Symbol Parameter Conditions Min. Typ. Max. Units

VIN Supply Voltage 4.5 18 V

VUVLO Input Under-Voltage Lockout

Threshold VIN Rising

VIN Falling 4.1

3.7 V

IIN Supply Current (Quiescent) IOUT = 0, VFB = 1.2 V, VEN > 1.2 V 1.6 2.5 mA

IOFF Shutdown Supply Current VEN = 0 V 110µA

VFB Feedback Voltage TA = 25 °C 0.788 0.8 0.812 V

Load Regulation 0.5 %

Line Regulation 1%

IFB Feedback Voltage Input Current 200 nA

VEN EN Input Threshold Off Threshold

On Threshold 2

0.6 V

VHYS EN Input Hysteresis 100 mV

EN Leakage Current 1µA

SS Time CSS = 16 nF 2 ms

MODULATOR

fOFrequency 400 500 600 kHz

DMAX Maximum Duty Cycle 85 %

TMIN Controllable Minimum On Time 150 ns

Current Sense Transconductance 7 A / V

Error Amplifier Tr ansconductance 200 µA / V

PROTECTION

ILIM Current Limit 2.5 3.5 A

Over-Temperature Shutdown Limit TJ Rising

TJ Falling 150

100 °C

OUTPUT STAGE

High-Side Switch On-Resistance VIN = 12 V

VIN = 5 V 80

120 mΩ

Low-Side Switch On-Resistance VIN = 12 V

VIN = 5 V 50

60 mΩ

Not Recommended For New Designs

Rev. 1.0 June 2011 www.aosmd.com Page 5 of 14

AOZ1050PI

Typical Performance Characteristics

Circuit of Figure 1. TA = 25 °C, VIN = VEN = 12 V, VOUT = 3.3 V unless otherwise specified.

Light Load Operation

2µs/div

Start Up to Full Load

2ms/div

Full Load Operation

2µs/div

Vin

200mV/div

20mV/div

1A/div

VLX

5V/div

Vin

5V/div

1V/div

lin

1A/div

50% to 100% Load Transient

200µs/div

200mV/div

1A/div

Vin

100mV/div

20mV/div

1A/div

VLX

5V/div

Not Recommended For New Designs

AOZ1050PI

Rev. 1.0 June 2011 www.aosmd.com Page 6 of 14

Efficiency

Detailed Description

The AOZ1050PI is a current-mode step down regulator

with an integrated high-side PMOS switch and a low-side

NMOS switch. The AOZ1050PI operates from a 4.5 V to

18 V input voltage range and supplies up to 2 A of load

current. Features includ e enable control, power-on reset,

input under voltage lockout, output over voltage

protection, external soft-start and thermal shut down.

The AOZ1050PI is available in an exposed pad SO-8

package.

Enable and Soft Start

The AOZ1050PI has an external sof t st art feature to limit

in-rush current and ensure the output voltage ramps up

smoothly to regulation voltage. The soft start process

begins when the input voltage rises to 4.1 V and voltage

on the EN pin is HIGH. In the soft start process, the

FB volt age is ramped to follow th e voltage of the soft st art

pin until it reaches 0.8 V. The voltage of the soft-start pin

is charged by an internal 5 µA current.

The EN pin of the AOZ1050PI is a ctive high. Connect the

EN pin to VIN if the enable function is not used. Pulling

EN to ground will disable the AOZ1050PI. Do not leave

EN open. The voltage on the EN pin must be above 2 V

to enable the AOZ1050PI. When the EN pin voltage falls

below 0.6 V, the AOZ1050PI is disabled.

Steady-State Operation

Under heavy load steady-state conditions, the converter

operates in fixed frequency and Continuous-Conduction

Mode (CCM).

The AOZ1050PI integrates an internal P-MOSFET as the

high-side switch. In ductor current is sensed by amplifying

the voltage drop across the drain to source of the high

side power MOSFET. Output voltage is divided down by

the external voltage divider at the FB pin. The difference

of the FB pin voltage and reference voltage is amplified

by the internal transconductance error amplifier. The

error voltage, which shows on the COMP pin, is

compared against the current signal, which is the sum of

inductor current signal and ramp compensation signal, at

the PWM comparator input. If the current signal is less

than the error volt a ge, the inte rnal hig h-side switch is on.

The inductor current flows from the input through the

inductor to the output. When the current signal exceeds

the error volt age, the high-side switch is off. The inductor

current is freewheeling through the internal low-side

N-MOSFET switch to output. The internal adaptive FET

driver guarantees no turn on overlap of both the

high-side and the low-side switch.

Efficiency (VIN = 12V) vs. Load Current

100

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

Load Current (A )

Efficiency (%)

5V OUTP UT

3.3V OUTP UT

1. 8V OUTP UT

1. 2V OUTP UT

Not Recommended For New Designs

AOZ1050PI

Rev. 1.0 June 2011 www.aosmd.com Page 7 of 14

Compared with regulators using freewheeling Schottky

diodes, the AOZ1050PI uses a freewheeling NMOSFET

to realize synchronous rectification. This greatly

improves the converter efficiency and reduces power

loss in the low-side switch.

The AOZ1050PI uses a P-Channel MOSFET as the

high-side switch. This saves the bootstrap capacitor

normally seen in a circuit using an NMOS switch. It also

allows 100 % turn-on of th e hig h- sid e swit ch to ach iev e

linear regulation mode of operation. The minimum

voltage drop from VIN to VO is the load current times DC

resistance of the MOSFET plus DC resist ance of the

buck inductor. It can be calculated by equation below:

where;

VO_MAX is the maximum output voltage,

VIN is the input voltage from 4.5 V to 18 V,

IO is the output current from 0 A to 2 A, and

RDS(ON) is the on resistance of the internal MOSFET.

Output Voltage Programming

Output voltage can be set by feeding back the output to

the FB pin using a resistor divider network as shown in

Figure 1. The resistor divider network includes R1 and

R2. Usually, a design is started by picking a fixed R2

value and calculating the required R1 with the equation

below:

Some stand ard value of R1 and R2 for the most common

output voltages are listed in Table 1.

Table 1.

The combination of R1 a nd R2 sho uld be large enough to

avoid drawing excessive current from the output, which

will cause power loss.

Since the switch duty cycle ca n be as high as 100 %, the

maximum output voltage can be set as high as the input

voltage minus the voltage drop on the up pe r PM OS an d

the inductor.

Protection Features

The AOZ1050PI has multiple protection features to

prevent system circuit damage under abnormal

conditions.

Over Current Protection (OCP)

The sensed inductor current signal is also used for over

current prot ec tio n. Sinc e th e AOZ 1 05 0 PI em plo ys pe a k

current mode control, the COMP pin voltage is

proportional to the peak inductor current. The COMP pin

voltage is limited to be between 0.4 V and 2.5 V internally.

The peak inductor current is automatically limited

cycle-by-cycle.

When the output is shorted to ground under fault

conditions, the inductor current slowly decays during a

switching cycle because the output voltage is 0 V.

To prevent catastrophic failure, a secondary current limit

is designed inside the AOZ1050PI. The measured

inductor current is compared against a preset voltage

which represent s the current limit, between 3.5 A and 5.0

A. When the output current is greater than the current

limit, the high side switch will be turned off. The converter

will initiate a soft start once the over-current condition is

resolved.

Power-On Reset (POR)

A power-on reset circuit monitors the input voltage. When

the input voltage exceeds 4.1 V, the converter starts

operation. When input voltage falls below 3.7 V, the

converter will be shut down.

Thermal Protection

An internal temperature sensor monitors the junction

temperature. The sensor shuts down the internal control

circuit and high side PMOS if the junction temperature

exceeds 150 ºC. The regulator will restart automatically

under the control of the soft-start circuit when the junction

temperature decreases to 100 ºC.

VO (V) R1 (kΩ) R2 (kΩ)

0.8 1.0 Open

1.2 4.99 10

1.5 10 11.5

1.8 12.7 10.2

2.5 21.5 10

3.3 31.1 10

5.0 52.3 10

VO_MAX VIN IORDS ON()

×–=

VO0.8 1 R1

-------+

⎝⎠

⎜⎟

⎛⎞

×=

Not Recommended For New Designs

AOZ1050PI

Rev. 1.0 June 2011 www.aosmd.com Page 8 of 14

Application Information

The basic AOZ1050PI application circuit is show in

Figure 1. Component selection is explained below.

Input Capacitor

The input ca pacitor must be connected to the VIN p in and

the PGND pin of AOZ1050PI to maintain steady input

voltage and filter out the pulsing input current. The

voltage rating of input capacitor must be greater than

maximum input voltage plus ripple voltage.

The input ripple voltage can be approximated by

equation below:

Since the input current is discontinuous in a buck

converter, the current stress on the input capacitor is

another concern whe n selecting the capacitor. For a buck

circuit, the RMS value of input capacitor current can be

calculated by:

if we let m equal the conversion ratio:

The relationship between the input capacitor RMS

current and voltage conv er sio n ra tio is calcula te d an d

shown in Figure 2 below. It can be seen that when VO is

half of VIN, CIN is under the worst current stress. The

worst current stress on CIN is 0.5 x IO.

Figure 2. ICIN vs. Voltage Convers ion Ratio

For reliable operation and best performance, the input

capacitors must have a current rating higher than

ICIN_RMS at the worst operating conditio ns. Ceramic

capacitors are preferred for input capacitors because of

their low ESR and high current rating. Depending on the

application circuits, other low ESR tantalum capacitors

may be used. When se lecting ceramic capacitors, X5R or

X7R type dielectric ceramic capacitors should be used

for their better tem p er at ur e an d vo ltage characteristics.

Note that the ripple current rating from capacitor

manufactures are based on a certain operating life time.

Further de-rating may need to be considered for long

term reliability.

Inductor

The inductor is used to supply constant current to output

when it is driven by a switching volt age. For a given input

and output voltage, inductance and switching frequency

together decide the inductor ripple current, which is:

The peak inductor current is:

High inductance gives low inductor ripple current but

requires larger size inductor to avoid saturation. Low

ripple current reduces inductor core losses. It also

reduces RMS current through inductor and switches,

which results in less conduction loss. Usually, peak to

peak ripple current on the inductor is designed to be

20 % to 40 % of output current.

When selecting the inductor, confirm it is able to handle

the peak current without saturation at the highest

operating temperature.

The inductor takes the highest current in a buck circuit.

The conduction loss on the inducto r needs to be checked

for thermal and efficiency requirements.

Surface mount indu ctors in differ ent shape and styles are

available from Coilcraft, Elytone and Murata. Shielded

inductors are small an d radiate less EMI noise. However,

they cost more than unshielded inductors. The choice

depends on EMI requirement, price and size.

ΔVIN IO

----------------- 1VO

VIN

---------–

⎝⎠

⎜⎟

⎛⎞

VIN

---------

××=

ICIN_RMS IOVO

VIN

---------1VO

VIN

---------–

⎝⎠

⎜⎟

⎛⎞

×=

VIN

---------m=

0.1

0.2

0.3

0.4

0.5

0 0.5 1

CIN_RMS

(m)

ΔILVO

fL×

-----------1VO

VIN

---------–

⎝⎠

⎜⎟

⎛⎞

×=

ILpeak IOΔIL

--------+=

Not Recommended For New Designs

AOZ1050PI

Rev. 1.0 June 2011 www.aosmd.com Page 9 of 14

Output Capacitor

The output capacitor is selected based on the DC output

voltage rating, output ripple voltage specification and

ripple current rating.

The selected output capacitor must have a higher rated

voltage specification than the maximum desired output

voltage including ripple. De-rating needs to be

considered for long term reliability.

Output ripple voltage specification is another important

factor for selecting the output capacitor. In a buck

converter circuit, output ripple voltage is determined by

inductor value, switching frequen c y, output capacitor

value and ESR. It can be calculated by the equation

below:

where,

CO is output capacitor value, and

ESRCO is the equivalent series resistance of the output

capacitor.

When a low ESR ceramic capa citor is u sed as the ou tput

capacitor, the impedance of the cap acitor at the switching

frequency dominates. Output ripple is mainly caused by

capacitor value and inductor ripple current. The output

ripple voltage calculation ca n be simp lifie d to :

If the impedance of ESR at switching frequency

dominates, the output r ipple volt age is mainly decided by

capacitor ESR and inductor ripple current. The output

ripple voltage calculation can be further simplified to:

For lower output ripple voltage across the entire

operating temperature range, X5R or X7R dielectric type

of ceramic, or other low ESR tantalum capacitors are

recommended as output capacitors.

In a buck converter, output capacitor current is

continuous. The RMS current of output capacitor is

decided by the peak to peak inductor ripple current. It can

be calculated by:

Usually, the ripple current rating of the ou tput capacitor is

a smaller issue because of the low current stress. When

the buck inductor is selected to be very small and

inductor ripple current is high, the output capacitor could

be overstressed.

Loop Compensation

The AOZ1050PI employs peak current mode control for

ease of use and fast transient response. Peak current

mode control eliminates the double pole effect of the

output L&C filter. It also greatly simplifies the

compensation loop design.

With peak current mode control, the buck power stage

can be simplified to be a one-pole and one-zero system

in frequency domain. The pole is dominant pole can be

calculated by:

The zero is a ESR zero due to the output capacitor and

its ESR. It is can be calculated by:

where;

CO is the output filter capacitor,

RL is load resistor value, and

ESRCO is the equivalent series resistance of output capacitor.

The compensation design shapes the converter control

loop transfer function for the desired gain and phase.

Several dif ferent types of compensation networ ks can be

used with the AOZ1050PI. For most cases, a series

capacitor and resistor network connected to the

COMP pin set s the pole-zero and is a dequate for a st able

high-bandwidth control loop.

In the AOZ1050PI, FB and COMP are the inverting input

and the output of the internal error amplifier. A series

R and C compensation network connected to COMP

provides one pole and one zero. The pole is:

where;

GEA is the error amplifier transconductance, which is 200 x 10-6

A/V,

GVEA is the error amplifier voltage gain, which is 500 V/V, and

CC is the compensation capacitor in Figure 1.

ΔVOΔILESRCO 1

8fC

××

-------------------------+

⎝⎠

⎛⎞

×=

ΔVOΔIL1

8fC

××

-------------------------

×=

ΔVOΔILESRCO

×=

ICO_RMS ΔIL

----------=

fP11

2πCORL

××

-----------------------------------=

fZ11

2πCOESRCO

××

------------------------------------------------=

fP2GEA

2πCCGVEA

××

-------------------------------------------=

Not Recommended For New Designs

AOZ1050PI

Rev. 1.0 June 2011 www.aosmd.com Page 10 of 14

The zero given by the external compensation network,

capacitor CC and resistor RC, is located at:

To design the compensation circuit, a target crossover

frequency fC to close the loop must be selected. The

system crossover frequency is where the control loop

has unity gain. The crossover is the also called the

converter bandwidth. Generally a higher bandwidth

means faster response to load transients. However, the

bandwidth should not be too high because of system

stability concern. When designing the compensation

loop, converter stability under all line and load condition

must be considered.

Usually, it is recommended to set the bandwidth to be

equal or less than 1/10 of the switching frequency.

The strategy for choosing RC and CC is to set the cross

over frequency with RC and set the compensator zero

with CC. Using selected crossover frequency, fC, to

calculate RC:

where;

fC is the desired crossover frequency. For best performance,

fC is set to be about 1/10 of the switching frequency;

VFB is 0.8V,

GEA is the error amplifier transconductance, which is

200 x 10-6 A/V, and

GCS is the current sense circuit transconductance, which is

8 A/V

The compensation capacitor CC and resistor RC to gether

make a zero. This zero is put somewhere close to the

dominate pole fp1 but lower than 1/5 of the selected

crossover frequency. CC can is selected by:

The above equation can be simplified to:

An easy-to-use application software which helps to

design and simulate the compensation loop can be found

at www.aosmd.com.

Thermal Management and Layout

Considerations

In the AOZ1050PI buck regulator circuit, high pulsing

current flows through two circuit loops. The first loop

starts from the input capacitors, to the VIN pin, to the

LX pad, to the filter inductor, to the output capacitor and

load, and then returns to the input capacitor through

ground. Current flows in the first loop when the high side

switch is on. The second loop starts from the inductor,

to the output capacitors and load, to the low side

NMOSFET. Current flows in the second loop when the

low side NMOSFET is on.

In PCB layout, minimizing the area of the two loops will

reduce the noise of the circuit and improves efficiency.

A ground plane is strongly recommended to connect the

input capacitor, the output capacitor, and th e PGN D pin

of the AOZ1050PI.

In the AOZ1050PI buck regulator circuit, the major power

dissipating components are the AOZ1050PI and the

output inductor. The total power dissipation of converter

circuit can be measured by input power minus output

power:

The power dissipation of the inductor can be

approximately calculated by the output current and DCR

value of the inductor:

The actual junction temperature can be calculated by the

power dissipation in the AOZ1050PI and the thermal

impedance from junction to ambient:

The maximum junction tempera ture of the AOZ1 050PI is

150 ºC, which limits the maximum load current cap ability.

The thermal performance of the AOZ1050PI is strongly

affected by the PCB layout. Care should be taken during

the design process to ensure that the IC will operate

under the recommended environmental conditions.

fZ21

2πCCRC

××

-----------------------------------=

RCfCVO

VFB

---------- 2πCC

GEA GCS

------------------------------

××=

CC1.5

2πRCfP1

××

-----------------------------------=

CCCORL

---------------------=

Ptotal_loss VIN IIN VOIO

×–×=

Pinductor_loss IO2Rinductor 1.1××=

Tjunction Ptotal_loss Pinductor_loss

–()Θ×JA

Not Recommended For New Designs

AOZ1050PI

Rev. 1.0 June 2011 www.aosmd.com Page 11 of 14

Layout Considerations

The AOZ1050PI is an exposed pad SO-8 package.

Several layout tips are listed for th e be st ele ctr ic an d

thermal perfor ma n ce .

1. The exposed pad (LX) is connected to the internal

PFET and NFET drains. Connected a large copper

plane to the LX pin to help th er ma l diss ipation.

2. Do not use a thermal relief connection to the VIN pin

or the PGND pin. Pour a maximized copper area to

the PGND pin and the VIN pin to help thermal

dissipation.

3. The input cap acitor should be connected as close as

possible to the VIN pin and the PGND pin.

4. A ground plane is preferred. If a ground plane is not

used, separate PGND from AGND and only connect

them at one point to avoid the PGND pin noise

coupling to the AGN D pin.

5. Make the current trace from the LX pad to L to Co to

the PGND as short as possible.

6. Pour copper plane on all unused board area and

connect it to stable DC nodes, like VIN, GND or

VOUT.

7. Keep sensitive signal trace away from the LX pad.

Not Recommended For New Designs

AOZ1050PI

Rev. 1.0 June 2011 www.aosmd.com Page 12 of 14

Package Dimensions, SO-8 EP1

Notes:

1. Package body sizes exclude mold flash and gate burrs.

2. Dimension L is measured in gauge plane.

3. Tolerance 0.10mm unless otherwise specified.

4. Controlling dimension is millimeter, converted inch dimensions are not necessarily exact.

5. Die pad exposure size is according to lead frame design.

6. Followed from JEDEC MS-012

Symbols

| L1–L1' |

Dimensions in millimeters

RECOMMENDED LAND PATTERN

Min.

1.40

0.00

1.40

0.31

0.17

4.80

3.20

3.10

5.80

—

3.80

2.21

0.40

—

0°

—

UNIT: mm

Nom.

1.55

0.05

1.50

0.406

—

4.96

3.40

3.30

6.00

1.27

3.90

2.41

0.40 REF

0.95

—

3°

0.04

1.04 REF

Max.

1.70

0.10

1.60

0.51

0.25

5.00

3.60

3.50

6.20

—

4.00

2.61

1.27

0.10

8°

0.12

Dimensions in inches

E1 E

E3E2

Note 5 L1'

Gauge plane

0.2500 C

7 (4x)

3.70

2.20

2.87

2.71 5.74

1.27 0.80

0.635

eA1

A2 A

Symbols

| L1–L1' |

Min.

0.055

0.000

0.055

0.012

0.007

0.189

0.126

0.122

0.228

—

0.150

0.087

0.016

—

0°

—

Nom.

0.061

0.002

0.059

0.016

—

0.195

0.134

0.130

0.236

0.050

0.153

0.095

0.016 REF

0.037

—

3°

0.002

0.041 REF

Max.

0.067

0.004

0.063

0.020

0.010

0.197

0.142

0.138

0.244

—

0.157

0.103

0.050

0.004

8°

0.005

Not Recommended For New Designs

AOZ1050PI

Rev. 1.0 June 2011 www.aosmd.com Page 13 of 14

Tape and Reel Dimensions, SO-8 EP1

Carrier Tape

Reel

Tape Size

12mm Reel Size

ø330 M

ø330.00

±0.50

Package

SO-8

(12mm)

6.40

±0.10

5.20

±0.10

2.10

±0.10

1.60

±0.10

1.50

±0.10

12.00

±0.10

1.75

±0.10

5.50

±0.10

8.00

±0.10

4.00

±0.10

2.00

±0.10

0.25

±0.10

ø97.00

±0.10

UNIT: mm

Trailer Tape

300mm min. or

75 empty pockets

Components Tape

Orientation in Pocket Leader Tape

500mm min. or

125 empty pockets

Feeding Direction

TD1

13.00

±0.30

17.40

±1.00

ø13.00

+0.50/-0.20

10.60 S

2.00

±0.50

—R

—V

—

Leader/Trailer and Orientation

UNIT: mm

Not Recommended For New Designs

AOZ1050PI

Rev. 1.0 June 2011 www.aosmd.com Page 14 of 14

Part Marking

Z1050PI

FAY Part Number Code

Assembly Lot Code

Year & Week Code

WLT

Fab & Assembly Location

As used herein:

1. Life support devices or systems are devices or

systems which, (a) are intended for surgical implant into

the body or (b) support or sustain life, and (c) whose

failure to perform when properly used in accordance

with instructions for use provided in the labeling, can be

reasonably expected to result in a significant injury of

the user.

2. A critical component in any component of a life

support, device, or system whose failure to perfor m can

be reasonably expected to cause the failure of the life

support device or system, or to affect its safety or

effectiveness.

LEGAL DISCLAIMER

Alpha and Omega Semiconductor makes no representations or warranties with respect to the accuracy

or completeness of the information provided herein and takes no liabilities for the consequences of use of

such information or any product described herein. Alpha and Omega Semiconductor reserves the right to

make changes to such information at any time without further notice. This document does not constitute the grant

of any intellectual property rights or representation of non-infringement of any third-party’s intellectual property

rights. Customer shall comply with applicable legal requirements, including all applicable export control rules,

regulations, and limitations.

LIFE SUPPORT POLICY

ALPHA & OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL

COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS.

Not Recommended For New Designs