ATA6630-GLQW - Atmel - Datasheet.Directory

9117I-AUTO-10/14

Features

●Master and slave operation possible

●Supply voltage up to 40V

●Operating voltage VS = 5V to 27V

●Typically 10µA supply current during Sleep Mode

●Typically 35µA supply current in Silent Mode

●Linear low-drop voltage regulator, 85mA current capability:

●Normal, Fail-safe, and Silent Mode

●Atmel® ATA6628 VCC = 3.3V ±2%

●Atmel ATA6630 VCC = 5.0V ±2%

●In Sleep Mode VCC is switched off

●VCC- undervoltage detection (4ms reset time) and watchdog reset logical

combined at open drain output NRES

●High-speed Mode for transmission rates up to 200kBaud

●Internal 1:6 voltage divider for VBattery Sensing

●Negative trigger input for watchdog

●Boosting the voltage regulator possible with an external NPN transistor

●LIN physical layer according to LIN 2.0, 2.1 and SAEJ2602-2

●Wake-up capability via LIN-bus, Wake pin, or Kl_15 pin

●INH output to control an external voltage regulator or to switch off the master pull

up resistor

●Bus pin is overtemperature and short-circuit protected versus GND and battery

●Adjustable watchdog time via external resistor

●Advanced EMC and ESD performance

●Fulfills the OEM “Hardware Requirements for LIN in Automotive Applications

Rev.1.1”

●Interference and damage protection according to ISO7637

●Qualified according to AEC-Q100

●Package: QFN 5mm × 5mm with 20 pins (Moisture Sensitivity Level 1)

ATA6628/ATA6630

LIN Bus Transceiver with 3.3V (5V) Regulator and

Watchdog

DATASHEET

ATA6628/ATA6630 [DATASHEET]

9117I–AUTO–10/14

1. Description

The Atmel® ATA6628 is a fully integrated LIN transceiver, which complies with the LIN 2.0, 2.1 and SAEJ2602-2

specifications. It has a low-drop voltage regulator for 3.3V/85mA output and a window watchdog. The Atmel ATA6630 has

the same functionality as the Atmel ATA6628; however, it uses a 5V/85mA regulator. The voltage regulator is able to source

up to 85mA, but the output current can be boosted by using an external NPN transistor. This chip combination makes it

possible to develop inexpensive, simple, yet powerful slave and master nodes for LIN-bus systems. Atmel

ATA6628/ATA6630 are designed to handle the low-speed data communication in vehicles, e.g., in convenience electronics.

Improved slope control at the LIN-driver ensures secure data communication up to 20kBaud. The bus output is designed to

withstand high voltage. Sleep Mode and Silent Mode guarantee minimized current consumption even in the case of a

floating or a short circuited LIN- bus.

Figure 1-1. Block Diagram

High

Speed

Mode

Adjustable

Watchdog

Oscillator

Short Circuit and

Overtemperature

Protection

TXD

Time-out

Timer

Edge

Detection

Internal Testing

Unit

Control Unit

Slew Rate Control

Wake-up

Bus Timer

Undervoltage

Reset

Normal/Silent/

Fail-safe Mode

3.3V/5V

RF Filter

Watchdog

RXD

NTRIGGNDPV

PVCC

TMMODE

TXD

SP_MODE

KL_15

WAKE

Receiver

59163

Normal and

Fail-safe

Mode

LIN

WD_OSC

NRES

PVCC

VCC

DIV_ON

VBATT

Normal and

Fail-safe

Mode

INH

ATA6628/ATA6630 [DATASHEET]

9117I–AUTO–10/14

2. Pin Configuration

Figure 2-1. Pinning QFN20

Table 2-1. Pin Description

Pin Symbol Function

1VBATT Battery supply for the voltage divider

2EN Enables the device into Normal Mode

3NTRIG Low-level watchdog trigger input from microcontroller; if not needed, connect to PVCC

4WAKE High-voltage input for local wake-up request; if not needed, connect to VS

5 GND System ground

6LIN LIN-bus line input/output

7RXD Receive data output

8DIV_ON Input to switch on the internal voltage divider, active high; if not needed, connect to GND

9PV Voltage divider output

10 SP_MODE Input to switch the transceiver in High-speed Mode, active high

11 INH Battery related High-side switch

12 TXD Transmit data input; active low output (strong pull down) after a local wake up request

13 NRES Output undervoltage and watchdog reset (open drain)

14 WD_OSC External resistor for adjustable watchdog timing; if not needed, connect to GND

15 TM For factory testing only (tie to ground)

16 MODE Low watchdog is on; high watchdog is off

17 KL_15 Ignition detection (edge sensitive); if not needed, connect to GND

18 PVCC 3.3V/5V regulator sense input pin, connect to VCC

19 VCC 3.3V/5V regulator output/driver pin, connect to PVCC

20 VS Battery supply

Backside Heat slug is connected to GND

67 8 109

20 19 18

QFN 5mm x 5mm

0.65mm pitch

20 lead

Atmel

ATA6628/30

INH

TXD

NRES

WD_OSC

MODE

KL15

PVCC

VCC

SP_MODE

DIV_ON

RXD

LIN

GND

WAKE

NTRIG

VBATT

ATA6628/ATA6630 [DATASHEET]

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3. Functional Description

3.1 Physical Layer Compatibility

Since the LIN physical layer is independent from higher LIN layers (e.g., the LIN protocol layer), all nodes with a LIN physical

layer according to revision 2.x can be mixed with LIN physical layer nodes, which, according to older versions (i.e., LIN 1.0,

LIN 1.1, LIN 1.2, LIN 1.3), are without any restrictions.

3.2 Supply Pin (VS)

The LIN operating voltage is VS = 5V to 27V. An undervoltage detection is implemented to disable data transmission if VS

falls below VSth in order to avoid false bus messages. After switching on VS, the IC starts in Fail-safe Mode, and the voltage

regulator is switched on (i.e., 3.3V/5V/85mA output capability).

The supply current is typically 10µA in Sleep Mode and 35µA in Silent Mode.

3.3 Ground Pin (GND)

The Atmel® ATA6628/ATA6630 does not affect the LIN Bus in the event of GND disconnection. It is able to handle a ground

shift up to 11.5% of VS. The mandatory system ground is pin 5.

3.4 Voltage Regulator Output Pin (VCC)

The internal 3.3V/5V voltage regulator is capable of driving loads up to 85mA. It is able to supply the microcontroller and

other ICs on the PCB and is protected against overloads by means of current limitation and overtemperature shut-down.

Furthermore, the output voltage is monitored and will cause a reset signal at the NRES output pin if it drops below a defined

threshold Vthun. To boost up the maximum load current, an external NPN transistor may be used, with its base connected to

the VCC pin and its emitter connected to PVCC.

3.5 Voltage Regulator Sense Pin (PVCC)

The PVCC is the sense input pin of the 3.3V/5V voltage regulator. For normal applications (i.e., when only using the internal

output transistor), this pin must be connected to the VCC pin. If an external boosting transistor is used, the PVCC pin must

be connected to the output of this transistor, i.e., its emitter terminal.

3.6 Bus Pin (LIN)

A low-side driver with internal current limitation and thermal shutdown and an internal pull-up resistor compliant with the LIN

2.x specification are implemented. The allowed voltage range is between –27V and +40V. Reverse currents from the LIN

bus to VS are suppressed, even in the event of GND shifts or battery disconnection. LIN receiver thresholds are compatible

with the LIN protocol specification. The fall time from recessive to dominant bus state and the rise time from dominant to

recessive bus state are slope controlled.

3.7 Input/Output Pin (TXD)

In Normal Mode the TXD pin is the microcontroller interface used to control the state of the LIN output. TXD must be pulled

to ground in order to have a low LIN-bus. If TXD is high or not connected (internal pull-up resistor), the LIN output transistor

is turned off, and the bus is in recessive state. During Fail-safe Mode, this pin is used as output and is signalling the fail-safe

source. It is current-limited to < 8mA.

3.8 TXD Dominant Time-out Function

The TXD input has an internal pull-up resistor. An internal timer prevents the bus line from being driven permanently in

dominant state. If TXD is forced to low for longer than tDOM, the LIN-bus driver is switched to recessive state. Nevertheless,

when switching to Sleep Mode, the actual level at the TXD pin is relevant.

To reactivate the LIN bus driver after a TXD time-out has occurred, switch TXD to high (> 10µs).

ATA6628/ATA6630 [DATASHEET]

9117I–AUTO–10/14

3.9 Output Pin (RXD)

This output pin reports the state of the LIN-bus to the microcontroller. LIN high (recessive state) is reported by a high level at

RXD; LIN low (dominant state) is reported by a low level at RXD. The output has an internal pull-up resistor with typically

5kΩ to PVCC. The AC characteristics can be defined with an external load capacitor of 20pF.

The output is short-circuit protected. RXD is switched off in Unpowered Mode (i.e., VS = 0V).

During Fail-safe Mode it is signalling the fail-safe source.

3.10 Enable Input Pin (EN)

The Enable Input pin controls the operation mode of the device. If EN is high, the circuit is in Normal Mode, with transmission

paths from TXD to LIN and from LIN to RXD both active. The VCC voltage regulator operates with 3.3V/5V/85mA output

capability.

If EN is switched to low while TXD is still high, the device is forced to Silent Mode. No data transmission is then possible, and

the current consumption is reduced to IVS typ. 35µA. The VCC regulator has its full functionality.

If EN is switched to low while TXD is low, the device is forced to Sleep Mode. No data transmission is possible, and the

voltage regulator is switched off.

3.11 Wake Input Pin (WAKE)

The WAKE Input pin is a high-voltage input used to wake up the device from Sleep Mode or Silent Mode. It is usually

connected to an external switch in the application to generate a local wake-up. A pull-up current source, typically 10µA, is

implemented.

If a local wake-up is not needed in the application, connect the WAKE pin directly to the VS pin.

3.12 Mode Input Pin (MODE)

Connect the MODE pin directly or via an external resistor to GND for normal watchdog operation. To debug the software of

the connected microcontroller, connect MODE pin to PVCC and the watchdog is switched off.

Note: If you do not use the watchdog, connect pin MODE directly to PVCC.

3.13 TM Input Pin

The TM pin is used for final production measurements at Atmel®. In all applications, it has to be connected to GND.

3.14 KL_15 Pin

The KL_15 pin is a high-voltage input used to wake up the device from Sleep or Silent Mode. It is an edge-sensitive pin (low-

to-high transition). It is usually connected to ignition to generate a local wake-up in the application when the ignition is

switched on. Although KL_15 pin is at high voltage (VBatt), it is possible to switch the IC into Sleep or Silent Mode. Connect

the KL_15 pin directly to GND if you do not need it. A debounce timer with a typical TdbKl_15 of 160µs is implemented.

The input voltage threshold can be adjusted by varying the external resistor due to the input current IKL_15. To protect this pin

against voltage transients, a serial resistor of 47kΩ and a ceramic capacitor of 100nF are recommended. With this RC

combination you can increase the wake-up time TwKL_15 and, therefore, the sensitivity against transients on the ignition

KL_15.

You can also increase the wake-up time using external capacitors with higher values.

3.15 INH Output Pin

The INH Output pin is used to switch an external voltage regulator on during Normal and Fail-safe Mode. The INH Output is

a high-side switch, which is switched-off in Sleep and Silent Mode. It is possible to switch off the external 1kΩ master resistor

via the INH pin for master node applications.

3.16 Reset Output Pin (NRES)

The Reset Output pin, an open drain output, switches to low during VCC undervoltage or a watchdog failure.

ATA6628/ATA6630 [DATASHEET]

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3.17 WD_OSC Output Pin

The WD_OSC Output pin provides a typical voltage of 1.2V, which supplies an external resistor with values between 34kΩ

and 120kΩ to adjust the watchdog oscillator time.

If the watchdog is disabled, this voltage is switched off and you can either tie to GND or leave this pin open.

3.18 NTRIG Input Pin

The NTRIG Input pin is the trigger input for the window watchdog. A pull-up resistor is implemented. A negative edge

followed by a low phase longer than ttrigmin triggers the watchdog.

3.19 Wake-up Events from Sleep or Silent Mode

●LIN-bus

●WAKE pin

●EN pin

●KL_15

3.20 DIV_ON Input Pin

The DIV_ON pin is a low voltage input. It is used to switch on or off the internal voltage divider PV output directly with no time

limitation (see Table 3-1 on page 6). It is switched on if DIV_ON is high or it is switched off if DIV_ON is low. In Sleep Mode

the DIV_ON functionality is disabled and PV is off. An internal pull-down resistor is implemented.

3.21 VBATT Input Pin

The VBATT is a high voltage input pin to supply the internal voltage divider. In an application with battery voltage monitoring,

this pin is connected to VBattery via a 47Ω resistor in series and a 10nF capacitor to GND (see Figure 9-2 on page 31). The

divider ratio is 1:6.

3.22 PV Output Pin

For applications with battery monitoring, this pin is directly connected to the ADC of a microcontroller. For buffering the ADC

input an external capacitor might be needed. This pin guarantees a voltage and temperature stable output of a VBattery ratio.

The PV output pin is controlled by the DIV_ON input pin.

3.23 SP_MODE Input Pin

The SP_MODE pin is a low-voltage input. High-speed Mode of the transceiver can be activated via a high level during

Normal Mode. Return to LIN 2.x Transceiver Mode with slope control is possible if you switch the SP_MODE pin to low.

Table 3-1. Table of Voltage Divider

Mode of Operation Input DiV_ON Voltage Divider Output PV

Fail-safe/Normal/

High-speed/Silent

0Off

1On

Sleep 0Off

1Off

ATA6628/ATA6630 [DATASHEET]

9117I–AUTO–10/14

4. Modes of Operation

Figure 4-1. Modes of Operation

4.1 Normal Mode

This is the normal transmitting and receiving mode. The voltage regulator is active and can source up to 85mA. The

undervoltage detection is activated. The watchdog needs a trigger signal from NTRIG to avoid resets at NRES. If NRES is

switched to low, the IC changes its state to Fail-safe Mode.

Table 4-1. Table of Modes

Mode of

Operation Transceiver Pin LIN VCC Pin Mode Watchdog

WD_OSC Pin INH

Unpowered Off Recessive On GND On On Off

Fail-safe Off Recessive 3.3V/5V GND On 1.23V On

Normal/ High-

speed On TXD

depending 3.3V/5V GND On 1.23V On

Silent Off Recessive 3.3V/5V GND Off 0V Off

Sleep Off Recessive 0V GND Off 0V Off

Unpowered Mode

(See Section 4.5)

a: VS > VSthF

b: VS < VSthU

c: Bus wake-up event

d: Wake up from WAKE or KL_15 pin

Fail-safe Mode

VCC: 3.3V/5V

with undervoltage monitoring

Communication: OFF

Watchdog: ON

Silent Mode

VCC: 3.3V/5V

with undervoltage monitoring

Communication: OFF

Watchdog: OFF

Sleep Mode

VCC: switched off

Communication: OFF

Watchdog: OFF

Go to silent command

TXD = 0

EN = 0

TXD = 1

EN = 0

EN = 1

c + d + e

c + d

Normal Mode

VCC: 3.3V/5V

with undervoltage detection

watchdog: ON

High level at

pin SP_MODE:

High-speed Mode

Transceiver ≤ 200kBaud

LIN 2.1

Transceiver

≤20kBaud

TXD time-out

timer on

Go to sleep command

e: NRES switches to low

Go to normal command

ATA6628/ATA6630 [DATASHEET]

9117I–AUTO–10/14

4.2 Silent Mode

A falling edge at EN when TXD is high switches the IC into Silent Mode. The TXD Signal has to be logic high during the

Mode Select window (see Figure 4-2 on page 8). The transmission path is disabled in Silent Mode. The INH output is

switched off and the voltage divider can be activated by the DIV_ON pin. The overall supply current from VBatt is a

combination of the IVSsilent = 35µA plus the VCC regulator output current IVCC.

The internal slave termination between the LIN pin and the VS pin is disabled in Silent Mode to minimize the current

consumption in the event that the LIN pin is short-circuited to GND. Only a weak pull-up current (typically 10µA) between the

LIN pin and the VS pin is present. Silent Mode can be activated independently from the actual level on the LIN, WAKE, or

KL_15 pins. If an undervoltage condition occurs, NRES is switched to low, and the IC changes its state to Fail-safe Mode.

A voltage less than the LIN Pre_Wake detection VLINL at the LIN pin activates the internal LIN receiver and starts the wake-

up detection timer.

Figure 4-2. Switch to Silent Mode

Delay time silent mode

td_silent = maximum 20μs

Mode select window

LIN switches directly to recessive mode

td = 3.2μs

LIN

VCC

NRES

TXD

Normal Mode Silent Mode

ATA6628/ATA6630 [DATASHEET]

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A falling edge at the LIN pin followed by a dominant bus level maintained for a certain time period (> tbus) and the following

rising edge at the LIN pin (see Figure 4-3 on page 9) result in a remote wake-up request which is only possible if TXD is high.

The device switches from Silent Mode to Fail-safe Mode. The internal LIN slave termination resistor is switched on. The

remote wake-up request is indicated by a low level at the RXD pin to interrupt the microcontroller (see Figure 4-3 on page 9).

EN high can be used to switch directly to Normal Mode.

Figure 4-3. LIN Wake-up from Silent Mode

Watchdog off Start watchdog lead time td

Watchdog

Undervoltage detection active

Silent mode 3.3V/5V Fail safe mode 3.3V/5V Normal mode

Low

Fail-safe mode Normal mode

EN High

Node in silent mode

HighHigh

NRES

VCC

voltage

regulator

RXD

LIN bus

Bus wake-up filtering time

tbus

TXD

Don't care

ATA6628/ATA6630 [DATASHEET]

9117I–AUTO–10/14

4.3 Sleep Mode

A falling edge at EN when TXD is low switches the IC into Sleep Mode. The TXD Signal has to be logic low during the Mode

Select window (Figure 4-4 on page 10). In order to avoid any influence to the LIN-pin during switching into sleep mode it is

possible to switch the EN up to 3.2µs earlier to Low than the TXD. The best and easiest way are two falling edges at TXD

and EN at the same time. The transmission path is disabled in Sleep Mode. The supply current IVSsleep from VBatt is typically

10µA.

The INH output, the PV output and the VCC regulator are switched off. NRES and RXD are low. The internal slave

termination between the LIN pin and VS pin is disabled to minimize the current consumption in the event that the LIN pin is

short-circuited to GND. Only a weak pull-up current (typically 10µA) between the LIN pin and the VS pin is present. Sleep

Mode can be activated independently from the current level on the LIN, WAKE, or KL_15 pin.

A voltage less than the LIN Pre_Wake detection VLINL at the LIN pin activates the internal LIN receiver and starts the wake-

up detection timer.

Figure 4-4. Switch to Sleep Mode

Delay time sleep mode

td_sleep = maximum 20μs

LIN switches directly to recessive mode

td = 3.2μs

LIN

VCC

NRES

TXD

Sleep Mode

Normal Mode

Mode select window

ATA6628/ATA6630 [DATASHEET]

9117I–AUTO–10/14

A falling edge at the LIN pin followed by a dominant bus level maintained for a certain time period (> tbus) and a rising edge

at pin LIN result in a remote wake-up request. The device switches from Sleep Mode to Fail-safe Mode.

The VCC regulator is activated, and the internal LIN slave termination resistor is switched on. The remote wake-up request

is indicated by a low level at the RXD pin to interrupt the microcontroller (see Figure 4-5 on page 11).

EN high can be used to switch directly to Normal Mode. If EN is still high after VCC ramp up and undervoltage reset time, the

IC switches to the Normal Mode.

Figure 4-5. LIN Wake Up from Sleep Mode

Regulator wake-up time

Off state

On state

Low

Fail-safe Mode Normal Mode

EN High

Microcontroller

Reset

time

Low

Watchdog

NRES

VCC

voltage

regulator

RXD

LIN bus

Bus wake-up filtering time

tbus

TXD

Watchdog off Start watchdog lead time td

start-up time delay

ATA6628/ATA6630 [DATASHEET]

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4.4 Sleep or Silent Mode: Behavior at a Floating LIN-bus or a Short Circuited LIN to GND

In Sleep or in Silent Mode the device has a very low current consumption even during short-circuits or floating conditions on

the bus. A floating bus can arise if the Master pull-up resistor is missing, e.g., if it is switched off when the LIN- Master is in

sleep mode or even if the power supply of the Master node is switched off.

In order to minimize the current consumption IVS in sleep or silent mode during voltage levels at the LIN-pin below the LIN

pre-wake threshold, the receiver is activated only for a specific time tmon. If tmon elapses while the voltage at the bus is lower

than Pre-wake detection low (VLINL) and higher than the LIN dominant level, the receiver is switched off again and the circuit

changes back to sleep respectively Silent Mode. The current consumption is then IVSsleep_short or IVSsilent_short (typ. 10µA more

than IVSsleep respectively IVSsilent). If a dominant state is reached on the bus no wake-up will occur. Even if the voltage rises

above the Pre-wake detection high (VLINH), the IC will stay in sleep respectively silent mode (see Figure 4-6).

This means the LIN-bus must be above the Pre-wake detection threshold VLINH for a few microseconds before a new LIN

wake-up is possible.

Figure 4-6. Floating LIN-bus during Sleep or Silent Mode

IVSsleep/silent IVSsleep/silent

IVSfail

VBUSdom

VLINL

IVS

tmon

LIN Pre-wake

LIN dominant state

LIN BUS

Mode of

operation

Int. Pull-up

Resistor

RLIN

Wake-up Detection Phase

off (disabled)

Sleep/Silent Mode Sleep/Silent Mode

IVSsleep_short /

IVSsilent_short

ATA6628/ATA6630 [DATASHEET]

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If the ATA6628/ATA6630 is in Sleep or Silent Mode and the voltage level at the LIN-bus is in dominant state (VLIN < VBUSdom)

for a time period exceeding tmon (during a short circuit at LIN, for example), the IC switches back to Sleep Mode respectively

Silent Mode. The VS current consumption then is IVSsleep_short or IVSsilent_short (typ. 10µA more than IVSsleep respectively

IVSsilent). After a positive edge at pin LIN the IC switches directly to Fail-safe Mode (see Figure 4-7 on page 13).

Figure 4-7. Short Circuit to GND on the LIN bus During Sleep- or Silent Mode

Sleep/Silent

Mode

IVSsleep/silent

IVSfail

VBUSdom

VLINL

LIN Pre-wake

LIN dominant state

LIN BUS

IVS

Mode of

operation

Int. Pull-up

Resistor

RLIN

off (disabled) on (enabled)

Wake-up Detection PhaseSleep/Silent Mode Fail-Safe Mode

tmon

VSsleep_short /

VSsilent_short

ATA6628/ATA6630 [DATASHEET]

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4.5 Fail-safe Mode

The device automatically switches to Fail-safe Mode at system power-up. The voltage regulator is switched on (see Figure

5-1 on page 18). The NRES output remains low for tres = 4ms and gives a reset to the microcontroller. LIN communication is

switched off. The IC stays in this mode until EN is switched to high. The IC then changes to Normal Mode. A power down of

VBatt (VS<VS

thU) during Silent or Sleep Mode switches the IC into Fail-safe Mode after power up. A low at NRES switches

into Fail-safe Mode directly. During Fail-safe Mode, the TXD pin is an output and signals the fail-safe source. The watchdog

is switched on.

The LIN SBC can operate in different Modes, like Normal, Silent, or Sleep Mode. The functionality of these modes is

described in Table 4-2.

A wake-up event from either Silent or Sleep Mode will be signalled to the microcontroller using the two pins RXD and TXD.

The coding is shown in Table 4-3.

A wake-up event will switch the IC to the Fail-safe Mode.

Table 4-2. TXD, RXD Depending from Operation Modes

Different Modes TXD RXD

Fail-safe Mode Signalling fail-safe sources (see Table 4-3 and Table 4-4)

Normal Mode Follows data transmission

Silent Mode High High

Sleep Mode Low Low

Table 4-3. Signalling Fail-safe Sources

Fail-safe Sources TXD RXD

LIN wake-up (pin LIN) Low Low

Local wake-up (at pin Wake, pin KL15) Low High

VSth (battery) undervoltage detection High Low

Table 4-4. Signalling in Fail-safe Mode after Reset (NRES was Low), Shows the Reset Source at TXD and RXD

Pins

Fail-safe Sources TXD RXD

VCC undervoltage at NRES High Low

Watchdog reset at NRES High High

ATA6628/ATA6630 [DATASHEET]

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4.6 Unpowered Mode

If you connect battery voltage to the application circuit, the voltage at the VS pin increases according to the block capacitor

(see Figure 5-1 on page 18). After VS is higher than the VS undervoltage threshold VSth, the IC mode changes from

Unpowered Mode to Fail-safe Mode. The VCC output voltage reaches its nominal value after tVCC. This time, tVCC, depends

on the VCC capacitor and the load.

The NRES is low for the reset time delay treset. During this time, treset, no mode change is possible.

IF VS drops below VSth, then the IC switches to Unpowered Mode. The behavior of VCC, NRES and LIN is shown in Figure

4-8. The watchdog needs to be triggered.

Figure 4-8. VCC versus VS for the VCC = 3.3V Regulator

4.7 High-speed Mode

If SP_MODE pin is high and the IC is in Normal Mode, the slew rate control is switched off. The slope time of the LIN falling

edge is tS_Fall < 2µs. The slope time of the LIN rising edge strongly depends on the LIN capacitive and resistive load. To

achieve a high baud rate it is recommended to use a small resistor (500Ω) and a low capacitor. This allows very fast data

transmission up to 200kBaud, e.g., for electronic control (ECU) tests and microcontroller program or data download. In this

mode superior EMC performance is not guaranteed.

VCC

LIN

NRES

Regulator drop voltage V

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6

(V)

4.5

3.5

5.5

2.5

1.5

0.5

V (V)

ATA6628/ATA6630 [DATASHEET]

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5. Wake-up Scenarios from Silent or Sleep Mode

5.1 Remote Wake-up via Dominant Bus State

A voltage less than the LIN Pre_Wake detection VLINL at the LIN pin activates the internal LIN receiver and starts the wake-

up detection timer.

A falling edge at the LIN pin followed by a dominant bus level VBUSdom maintained for a certain time period (> tBUS) and a

rising edge at pin LIN result in a remote wake-up request. A remote wake-up from Silent Mode is only possible if TXD is high.

The device switches from Silent or Sleep Mode to Fail-safe Mode. The VCC voltage regulator is/remains activated, the INH

pin is switched to high, and the internal slave termination resistor is switched on. The remote wake-up request is indicated by

a low level at the RXD pin to generate an interrupt for the microcontroller and a strong pull down at TXD.

5.2 Local Wake-up via Pin WAKE

A falling edge at the WAKE pin followed by a low level maintained for a certain time period (> tWAKE) results in a local wake-

up request. The device switches to Fail-safe Mode. The internal slave termination resistor is switched on. The local wake-up

request is indicated by a low level at the TXD pin to generate an interrupt for the microcontroller. When the Wake pin is low,

it is possible to switch to Silent or Sleep Mode via pin EN. In this case, the wake-up signal has to be switched to high > 10µs

before the negative edge at WAKE starts a new local wake-up request.

5.3 Local Wake-up via Pin KL_15

A positive edge at pin KL_15 followed by a high voltage level for a certain time period (> tKL_15) results in a local wake-up

request. The device switches into the Fail-safe Mode. The internal slave termination resistor is switched on. The extra long

wake-up time ensures that no transients at KL_15 create a wake-up. The local wake-up request is indicated by a low level at

the TXD pin to generate an interrupt for the microcontroller. During high-level voltage at pin KL_15, it is possible to switch to

Silent or Sleep Mode via pin EN. In this case, the wake-up signal has to be switched to low > 250µs before the positive edge

at KL_15 starts a new local wake-up request. With an external RC combination, the time can be increased.

5.4 Wake-up Source Recognition

The device can distinguish between different wake-up sources (see Table 4-4 on page 14).

The wake-up source can be read on the TXD and RXD pin in Fail-safe Mode. These flags are immediately reset if the

microcontroller sets the EN pin to high (see Figure 4-3 on page 9 and Figure 4-5 on page 11) and the IC is in Normal mode.

ATA6628/ATA6630 [DATASHEET]

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5.5 Fail-safe Features

●During a short-circuit at LIN to VBattery, the output limits the output current to IBUS_lim. Due to the power dissipation, the

chip temperature exceeds TLINoff, and the LIN output is switched off. The chip cools down and after a hysteresis of

Thys, switches the output on again. RXD stays on high because LIN is high. During LIN overtemperature switch-off,

the VCC regulator works independently.

●During a short-circuit from LIN to GND the IC can be switched into Sleep or Silent Mode and even in this case the

current consumption is lower than 30µA in Sleep Mode and lower than 70µA in Silent Mode. If the short-circuit

disappears, the IC starts with a remote wake-up.

●Sleep or Silent Mode: During a floating condition on the bus the IC switches back to Sleep Mode/Silent Mode

automatically and thereby the current consumption is lower than 30µA/70µA.

●The reverse current is < 2µA at the LIN pin during loss of VBatt. This is optimal behavior for bus systems where some

slave nodes are supplied from battery or ignition.

●During a short circuit at VCC, the output limits the output current to IVCClim. Because of undervoltage, NRES switches

to low and sends a reset to the microcontroller. The IC switches into Fail-safe Mode. If the chip temperature exceeds

the value TVCCoff, the VCC output switches off. The chip cools down and after a hysteresis of Thys, switches the output

on again. Because of the Fail-safe Mode, the VCC voltage will switch on again and the microcontroller can start with

its normal operation.

●EN pin provides a pull-down resistor to force the transceiver into recessive mode if EN is disconnected.

●RXD pin is set floating if VBatt is disconnected.

●TXD pin provides a pull-up resistor to force the transceiver into recessive mode if TXD is disconnected.

●If TXD is short-circuited to GND, it is possible to switch to Sleep Mode via ENABLE

●After switching the IC into Normal Mode the TXD pin must be pulled to high longer than 10µs in order to activate the

LIN driver. This feature prevents the bus from being driven into dominant state when the IC is switched into Normal

Mode and TXD is low.

●If the WD_OSC pin has a short-circuit to GND and the NTRIG Signal has a period time > 27ms a reset is guaranteed.

●If the resistor at the WD_OSC pin is disconnected and the NTRIG Signal has a period time < 46ms a reset is

guaranteed.

●If there is no NTRIG signal and a short-circuit at WD_OSC to GND the NRES switches to low after 90ms. For an open

circuit (no resistor) at WD_OSC it switches to low after 390ms.

ATA6628/ATA6630 [DATASHEET]

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5.6 Voltage Regulator

The voltage regulator needs an external capacitor for compensation and for smoothing the disturbances from the

microcontroller. It is recommended to use an electrolythic capacitor with C > 1.8µF and a ceramic capacitor with C = 100nF.

The values of these capacitors can be varied by the customer, depending on the application.

The main power dissipation of the IC is created from the VCC output current IVCC, which is needed for the application. In

Figure 5-2 on page 18 the safe operating area of the Atmel® ATA6630 is shown.

Figure 5-1. VCC Voltage Regulator: Ramp-up and Undervoltage Detection

Figure 5-2. Power Dissipation: Safe Operating Area: VCC Output Current versus Supply Voltage VS at Different

Ambient Temperatures Due to Rthja = 35K/W

For microcontroller programming, it may be necessary to supply the VCC output via an external power supply while the VS

Pin of the system basis chip is disconnected. This will not affect the system basis chip.

NRES

5V/3.3V

Vthun

Tres_f

TReset

TVCC

5.5V/3.8V

12V

VCC

5 6 7 8 9 101112131415161718

Tamb = 105°C

Tamb = 115°C

Tamb = 125°C

VS (V)

IVCC (mA)

ATA6628/ATA6630 [DATASHEET]

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6. Watchdog

The watchdog anticipates a trigger signal from the microcontroller at the NTRIG (negative edge) input within a time window

of Twd. The trigger signal must exceed a minimum time ttrigmin > 200ns. If a triggering signal is not received, a reset signal will

be generated at output NRES. The timing basis of the watchdog is provided by the internal oscillator. Its time period, Tosc, is

adjustable via the external resistor Rwd_osc (34kΩ to 120kΩ).

During Silent or Sleep Mode the watchdog is switched off to reduce current consumption.

The minimum time for the first watchdog pulse is required after the undervoltage reset at NRES disappears. It is defined as

lead time td. After wake up from Sleep or Silent Mode, the lead time td starts with the negative edge of the RXD output.

6.1 Typical Timing Sequence with RWD_OSC = 51kΩ

The trigger signal Twd is adjustable between 20ms and 64ms using the external resistor RWD_OSC.

For example, with an external resistor of RWD_OSC = 51kΩ ±1%, the typical parameters of the watchdog are as follows:

tosc = 0.405 × RWD_OSC – 0.0004 × (RWD_OSC)2 (RWD_OSC in kΩ ; tosc in µs)

tOSC = 19.6µs due to 51kΩ

td = 7895 × 19.6µs = 155ms

t1 = 1053 × 19.6µs = 20.6ms

t2 = 1105 × 19.6µs = 21.6ms

tnres = constant = 4ms

After ramping up the battery voltage, the 5V regulator is switched on. The reset output NRES stays low for the time treset

(typically 4ms), then it switches to high, and the watchdog waits for the trigger sequence from the microcontroller. The lead

time, td, follows the reset and is td= 155ms. In this time, the first watchdog pulse from the microcontroller is required. If the

trigger pulse NTRIG occurs during this time, the time t1 starts immediately. If no trigger signal occurs during the time td, a

watchdog reset with tNRES = 4 ms will reset the microcontroller after td= 155ms. The times t1 and t2 have a fixed relationship.

A triggering signal from the microcontroller is anticipated within the time frame of t2= 21.6ms. To avoid false triggering from

glitches, the trigger pulse must be longer than tTRIG,min > 200ns. This slope serves to restart the watchdog sequence. If the

triggering signal fails in this open window t2, the NRES output will be drawn to ground. A triggering signal during the closed

window t1 immediately switches NRES to low.

Figure 6-1. Timing Sequence with RWD_OSC = 51kΩ

tnres = 4ms

Undervoltage Reset Watchdog Reset

treset = 4ms

ttrig > 200ns

t1 = 20.6ms t2 = 21ms

twd

td = 155ms

VCC

3.3V/5V

NTRIG

NRES

ATA6628/ATA6630 [DATASHEET]

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6.2 Worst Case Calculation with RWD_OSC = 51kΩ

The internal oscillator has a tolerance of 20%. This means that t1 and t2 can also vary by 20%. The worst case calculation for

the watchdog period twd is calculated as follows.

The ideal watchdog time twd is between the maximum t1 and the minimum t1 plus the minimum t2.

t1,min = 0.8 × t1 = 16.5ms, t1,max = 1.2 × t1 = 24.8ms

t2,min = 0.8 × t2 = 17.3ms, t2,max = 1.2 × t2 = 26ms

twdmax = t1min + t2min = 16.5ms + 17.3ms = 33.8ms

twdmin = t1max = 24.8ms

twd = 29.3ms ±4.5ms (±15%)

A microcontroller with an oscillator tolerance of ±15% is sufficient to supply the trigger inputs correctly.

Table 6-1. Typical Watchdog Timings

RWD_OSC

kΩ

Oscillator

Period

tosc/µs

Lead

Time

td/ms

Closed

Window

t1/ms

Open Window

t2/ms

Trigger Period from

Microcontroller twd/ms

Reset Time

tnres/ms

34 13.3 105 14.0 14.7 19.9 4

51 19.61 154.8 20.64 21.67 29.32 4

91 33.54 264.80 35.32 37.06 50.14 4

120 42.84 338.22 45.11 47.34 64.05 4

ATA6628/ATA6630 [DATASHEET]

9117I–AUTO–10/14

7. Absolute Maximum Ratings

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating

only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this

specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Parameters Symbol Min. Typ. Max. Unit

Supply voltage VSVS–0.3 +40 V

Pulse time ≤500ms

Ta=25°C

Output current IVCC ≤85mA

VS+40 V

Pulse time ≤2min

Ta=25°C

Output current IVCC ≤85mA

VS27 V

WAKE (with 2.7kΩ serial resistor)

KL_15 (with 47kΩ/100nF)

VBATT (with 47Ω/10nF)

DC voltage

Transient voltage due to ISO7637 (coupling

1nF)

–1

–150

+40

+100

INH

- DC voltage –0.3 VS + 0.3 V

LIN, VBATT

- DC voltage –27 +40 V

Logic pins (RxD, TxD, EN, NRES, NTRIG,

WD_OSC, MODE, TM, DIV_ON,

SP_MODE, PV)

–0.3 VCC + 0.5V V

Output current NRES INRES +2 mA

PVCC DC voltage

VCC DC voltage

–0.3

+5.5

+6.5

ESD according to IBEE LIN EMC

Test Spec. 1.0 following IEC 61000-4-2

- Pin VS, LIN to GND

- Pin WAKE (2.7kΩ, serial resistor) to GND

- Pin KL_15 (47kΩ/100nF) to GND

- Pin VBATT (10nF) to GND

±8 KV

HBM ESD

ANSI/ESD-STM5.1

JESD22-A114

AEC-Q100 (002)

MIL-STD-883 (M3015.7)

±3 KV

CDM ESD STM 5.3.1 ±750 V

MM ESD

EIA/JESD22-A115

ESD STM5.2

AEC-Q100 (002)

±200 V

ESD HBM following STM5.1 with 1.5kΩ

100pF

- Pin VS, LIN, KL_15, WAKE to GND

±6 KV

Junction temperature Tj–40 +150 °C

Storage temperature Ts–55 +150 °C

ATA6628/ATA6630 [DATASHEET]

9117I–AUTO–10/14

8. Thermal Characteristics

Parameters Symbol Min. Typ. Max. Unit

Thermal resistance junction to heat slug Rthjc 10 K/W

Thermal resistance junction to ambient,

where heat slug is soldered to PCB

according to Jedec

Rthja 35 K/W

Thermal shutdown of VCC regulator 150 165 170 °C

Thermal shutdown of LIN output 150 165 170 °C

Thermal shutdown hysteresis 10 °C

9. Electrical Characteristics

5V < VS < 27V, –40°C < Tj < 150°C, unless otherwise specified. All values refer to GND pins

No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type*

1VS Pin

1.1 Nominal DC voltage range VS VS527 V A

1.2 Supply current in Sleep

Mode

Sleep Mode

VLIN > VS – 0.5V

VS < 14V

VS IVSsleep 210 14 µA A

Sleep Mode, VLIN = 0V

Bus shorted to GND

VS < 14V

VS IVSsleep_short 320 30 µA A

1.3 Supply current in Silent

Mode

Bus recessive

VS < 14V

Without load at VCC

VS IVSsilent 20 35 50 µA A

Silent Mode

VS < 14V

Bus shorted to GND

Without load at VCC

VS IVSsilent_short 25 45 70 µA A

1.4 Supply current in Normal

Mode

Bus recessive

VS < 14V

Without load at VCC

VS IVSrec 0.3 0.8 mA A

1.5 Supply current in Normal

Mode

Bus recessive

VS < 14V

VCC load current 50mA

VS IVSdom 50 53 mA A

1.6 Supply current in Fail-safe

Mode

Bus recessive, RXD is low

VS < 14V

Without load at VCC

for ATA6628

for ATA6630

IVSfail

1.0

1.5

2.0

1.7 VS undervoltage threshold

Switch to Unpowered

Mode VS VSthU 3.7 4.2 4.7 V A

Switch to Fail-safe Mode VS VSthF 4.0 4.5 5.0 V A

1.8 VS undervoltage threshold

hysteresis VS VSth_hys 0.3 V A

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

ATA6628/ATA6630 [DATASHEET]

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2RXD Output Pin

2.1 Low-level output sink

current

Normal Mode

VLIN =0V

VRXD =0.4V

RXD IRXD 1.3 2.5 8mA A

2.2 Low-level output voltage IRXD = 1mA RXD VRXDL 0.4 V A

2.3 Internal resistor to PVCC RXD RRXD 3 5 7 kΩA

3TXD Input/Output Pin

3.1 Low-level voltage input TXD VTXDL –0.3 +0.8 V A

3.2 High-level voltage input TXD VTXDH 2VCC +

0.3V V A

3.3 Pull-up resistor VTXD =0V TXD RTXD 125 250 400 kΩA

3.4 High-level leakage current VTXD =V

CC TXD ITXD –3 +3 µA A

3.5 Low-level output sink

current

Fail-safe Mode, wake up

VLIN = VS

VWAKE = 0V

VTXD = 0.4V

TXD ITXDwake 22.5 8mA A

4EN Input Pin

4.1 Low-level voltage input EN VENL –0.3 +0.8 V A

4.2 High-level voltage input EN VENH 2VCC +

0.3V V A

4.3 Pull-down resistor VEN = VCC EN REN 50 125 200 kΩA

4.4 Low-level input current VEN = 0V EN IEN –3 +3 µA A

5NTRIG Watchdog Input Pin

5.1 Low-level voltage input NTRIG VNTRIGL –0.3 +0.8 V A

5.2 High-level voltage input NTRIG VNTRIGH 2VCC +

0.3V V A

5.3 Pull-up resistor VNTRIG = 0V NTRIG RNTRIG 125 250 400 kΩA

5.4 High-level leakage current VNTRIG = VCC NTRIG INTRIG –3 +3 µA A

6Mode Input Pin

6.1 Low-level voltage input MODE VMODEL –0.3 +0.8 V A

6.2 High-level voltage input MODE VMODEH 2VCC +

0.3V V A

6.3 High-level leakage current VMODE = VCC or

VMODE = 0V MODE IMODE –3 +3 µA A

7INH Output Pin

7.1 High-level voltage IINH = –15mA INH VINHH VS – 0.75 VSV A

7.2 Switch-on resistance

between VS and INH INH RINH 30 50 ΩA

7.3 Leakage current Sleep Mode

VINH = 0V/27V, VS = 27V INH IINHL –3 +3 µA A

9. Electrical Characteristics (Continued)

5V < VS < 27V, –40°C < Tj < 150°C, unless otherwise specified. All values refer to GND pins

No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type*

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

ATA6628/ATA6630 [DATASHEET]

9117I–AUTO–10/14

8LIN Bus Driver

8.1 Driver recessive output

voltage Load1/Load2 LIN VBUSrec 0.9 × VSVSV A

8.2 Driver dominant voltage VVS = 7V

Rload = 500ΩLIN V_LoSUP 1.2 V A

8.3 Driver dominant voltage VVS = 18V

Rload = 500ΩLIN V_HiSUP 2 V A

8.4 Driver dominant voltage VVS = 7.0V

Rload = 1000ΩLIN V_LoSUP_1k 0.6 V A

8.5 Driver dominant voltage VVS = 18V

Rload = 1000Ω LIN V_HiSUP_1k 0.8 V A

8.6 Pull-up resistor to VS The serial diode is

mandatory LIN RLIN 20 30 47 kΩA

8.7 Voltage drop at the serial

diodes

In pull-up path with Rslave

ISerDiode = 10mA LIN VSerDiode 0.4 1.0 V D

8.8 LIN current limitation

VBUS = VBatt_max LIN IBUS_LIM 70 120 200 mA A

8.9

Input leakage current at the

receiver including pull-up

resistor as specified

Input leakage current

Driver off

VBUS = 0V

VBatt = 12V

LIN IBUS_PAS_do

–1 –0.35 mA A

8.10 Leakage current LIN

recessive

Driver off

8V < VBatt < 18V

8V < VBUS < 18V

VBUS ≥ VBatt

LIN IBUS_PAS_rec 10 20 µA A

8.11

Leakage current at GND

loss, control unit

disconnected from ground.

Loss of local ground must

not affect communication in

the residual network.

GNDDevice = VS

VBatt = 12V

0V < VBUS < 18V

LIN IBUS_NO_gnd –10 +0.5 +10 µA A

8.12

Leakage current at loss of

battery. Node has to sustain

the current that can flow

under this condition. Bus

must remain operational

under this condition.

VBatt disconnected

VSUP_Device = GND

0V < VBUS < 18V

LIN IBUS_NO_bat 0.1 2µA A

8.13 Capacitance on pin LIN to

GND LIN CLIN 20 pF D

9LIN Bus Receiver

9.1 Center of receiver threshold VBUS_CNT =

(Vth_dom + Vth_rec)/2 LIN VBUS_CNT

0.475 ×

0.5 ×

0.525 ×

V A

9.2 Receiver dominant state VEN = VCC LIN VBUSdom 0.4 × VSV A

9.3 Receiver recessive state VEN = VCC LIN VBUSrec 0.6 × VSV A

9.4 Receiver input hysteresis Vhys = Vth_rec – Vth_dom LIN VBUShys

0.028 ×

0.1 × VS

0.175 ×

V A

9. Electrical Characteristics (Continued)

5V < VS < 27V, –40°C < Tj < 150°C, unless otherwise specified. All values refer to GND pins

No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type*

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

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9117I–AUTO–10/14

9.5 Pre_Wake detection LIN

High-level input voltage LIN VLINH VS – 2V VS +

0.3V V A

9.6 Pre_Wake detection LIN

Low-level input voltage Activates the LIN receiver LIN VLINL –27 VS –

3.3V V A

10 Internal Timers

10.1 Dominant time for wake-up

via LIN bus VLIN = 0V LIN tbus 30 90 150 µs A

10.2

Time delay for mode change

from Fail-safe into Normal

Mode via EN pin

VEN = VCC EN tnorm 515 20 µs A

10.3

Time delay for mode change

from Normal Mode to Sleep

Mode via EN pin

VEN = 0V EN tsleep 816 25 µs A

10.4 TXD dominant time-out time VTXD = 0V TXD tdom 27 55 70 ms A

10.5

Time delay for mode change

from Silent Mode into

Normal Mode via EN

VEN = VCC EN ts_n 515 40 µs A

10.6 Monitoring time for wake-up

over LIN bus LIN tmon 610 15 ms A

LIN Bus Driver AC Parameter with Different Bus Loads

Load 1 (small): 1nF, 1kΩ ; Load 2 (large): 10nF, 500Ω ; RRXD =5kΩ; CRXD = 20pF;

Load 3 (medium): 6.8nF, 660Ω characterized on samples; 10.7 and 10.8 specifies the timing parameters for proper operation of

20Kbit/s, 10.9 and 10.10 at 10.4Kbit/s

10.7 Duty cycle 1

THRec(max) = 0.744 × VS

THDom(max) = 0.581 × VS

VS = 7.0V to 18V

tBit = 50µs

D1 = tbus_rec(min)/(2 × tBit)

LIN D1 0.396 A

10.8 Duty cycle 2

THRec(min) = 0.422 × VS

THDom(min) = 0.284 × VS

VS = 7.6V to 18V

tBit = 50µs

D2 = tbus_rec(max)/(2 × tBit)

LIN D2 0.581 A

10.9 Duty cycle 3

THRec(max) = 0.778 × VS

THDom(max) = 0.616 × VS

VS = 7.0V to 18V

tBit = 96µs

D3 = tbus_rec(min)/(2 × tBit)

LIN D3 0.417 A

10.10 Duty cycle 4

THRec(min) = 0.389 × VS

THDom(min) = 0.251 × VS

VS = 7.6V to 18V

tBit = 96µs

D4 = tbus_rec(max)/(2 × tBit)

LIN D4 0.590 A

10.11 Slope time falling and rising

edge at LIN VS = 7.0V to 18V LIN tSLOPE_fall

tSLOPE_rise

3.5 22.5 µs A

9. Electrical Characteristics (Continued)

5V < VS < 27V, –40°C < Tj < 150°C, unless otherwise specified. All values refer to GND pins

No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type*

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

ATA6628/ATA6630 [DATASHEET]

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11 Receiver Electrical AC Parameters of the LIN Physical Layer, LIN Receiver, RXD Load Conditions (CRXD): 20pF

11.1 Propagation delay of

receiver (Figure 9-1)

VS = 7.0V to 18V

trx_pd = max(trx_pdr , trx_pdf)RXD trx_pd 6µs A

11.2

Symmetry of receiver

propagation delay rising

edge minus falling edge

VS = 7.0V to 18V

trx_sym = trx_pdr – trx_pdf

RXD trx_sym –2 +2 µs A

12 NRES Open Drain Output Pin

12.1 Low-level output voltage VS ≥ 5.5V

INRES = 1mA NRES VNRESL 0.14 V A

12.2 Low-level output low 10kΩ to 5V

VCC = 0V NRES VNRESLL 0.14 V A

12.3 Undervoltage reset time VS ≥ 5.5V

CNRES = 20pF NRES treset 246ms A

12.4 Reset debounce time for

falling edge

VS ≥ 5.5V

CNRES = 20pF NRES tres_f 1.5 10 µs A

12.5 Switch off leakage current VNRES = 5.5V NRES –3 +3 µA A

13 Watchdog Oscillator

13.1 Voltage at WD_OSC in

Normal or Fail-safe Mode

IWD_OSC = –200µA

VVS ≥ 4V WD_OSC VWD_OSC 1.13 1.23 1.33 V A

13.2 Possible values of resistor Resistor ±1% WD_OSC ROSC 34 120 kΩA

13.3 Oscillator period ROSC = 34kΩtOSC 10.65 13.3 15.97 µs A

13.4 Oscillator period ROSC = 51kΩtOSC 15.68 19.6 23.52 µs A

13.5 Oscillator period ROSC = 91kΩtOSC 26.83 33.5 40.24 µs A

13.6 Oscillator period ROSC = 120kΩtOSC 34.2 42.8 51.4 µs A

14 Watchdog Timing Relative to tOSC

14.1 Watchdog lead time after

Reset td7895 cycles A

14.2 Watchdog closed window t11053 cycles A

14.3 Watchdog open window t21105 cycles A

14.4 Watchdog reset time NRES NRES tnres 3.2 44.8 ms A

15 KL_15 Pin

15.1 High-level input voltage

RV = 47kΩPositive edge initializes a

wake-up KL_15 VKL_15H 4VS +

0.3V V A

15.2 Low-level input voltage

RV = 47kΩKL_15 VKL_15L –1 +2 V A

15.3 KL_15 pull-down current VS < 27V

VKL_15 = 27V KL_15 IKL_15 50 60 µA A

15.4 Internal debounce time Without external capacitor KL_15 TdbKL_15 80 160 250 µs A

15.5 KL_15 wake-up time RV = 47kΩ, C = 100nF KL_15 TwKL_15 0.4 24.5 ms C

9. Electrical Characteristics (Continued)

5V < VS < 27V, –40°C < Tj < 150°C, unless otherwise specified. All values refer to GND pins

No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type*

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

ATA6628/ATA6630 [DATASHEET]

9117I–AUTO–10/14

16 WAKE Pin

16.1 High-level input voltage WAKE VWAKEH VS – 1V VS +

0.3V V A

16.2 Low-level input voltage Initializes a wake-up

signal WAKE VWAKEL –1 VS –

3.3V V A

16.3 WAKE pull-up current VS < 27V, VWAKE = 0V WAKE IWAKE –30 –10 µA A

16.4 High-level leakage current VS = 27V, VWAKE = 27V WAKE IWAKEL –5 +5 µA A

16.5 Time of low pulse for

wake-up via WAKE pin VWAKE = 0V WAKE IWAKEL 30 70 150 µs A

17 VCC Voltage Regulator ATA6628 in Normal/Fail-safe and Silent Mode, VCC and PVCC Short-circuited

17.1 Output voltage VCC

4V < VS < 18V

(0mA to 50mA) VCC VCCnor 3.234 3.366 V A

4.5V < VS < 18V

(0mA to 85mA) VCC VCCnor 3.234 3.366 V C

17.2 Output voltage VCC at low

VS 3V < VS < 4V VCC VCClow VS – VD3.366 V A

17.3 Regulator drop voltage VS > 3V, IVCC = –15mA VS, VCC VD200 mV A

17.4 Regulator drop voltage VS > 3V, IVCC = –50mA VS, VCC VD500 700 mV A

17.5 Line regulation 4V < VS < 18V VCC VCCline 0.1 0.2 % A

17.6 Load regulation 5mA < IVCC < 50mA VCC VCCload 0.1 0.5 % A

17.7 Power supply ripple

rejection

10Hz to 100kHz

CVCC = 10µF

VS = 14V, IVCC = –15mA

VCC 50 dB D

17.8 Output current limitation VS > 4V VCC IVCClim –240 –160 –85 mA A

17.9 External load capacity

0.2Ω < ESR < 5Ω at

100kHz

for phase margin ≥ 60° VCC Cload 1.8 10 µF D

ESR < 0.2Ω at 100kHz

for phase margin ≥ 30°

17.10 VCC undervoltage threshold Referred to VCC

VS > 4V VCC VthunN 2.8 3.2 V A

17.11 Hysteresis of undervoltage

threshold

Referred to VCC

VS > 4V VCC Vhysthun 150 mV A

17.12 Ramp-up time VS > 4V to

VCC = 3.3V

CVCC = 2.2µF

Iload = –5mA at VCC VCC TVCC 320 500 µs A

18 VCC Voltage Regulator Atmel ATA6630 in Normal/Fail-safe and Silent Mode, VCC and PVCC Short-circuited

18.1 Output voltage VCC

5.5V < VS < 18V

(0mA to 50mA) VCC VCCnor 4.9 5.1 V A

6V < VS < 18V

(0mA to 85mA) VCC VCCnor 4.9 5.1 V C

18.2 Output voltage VCC at low

VS 4V < VS < 5.5V VCC VCClow VS – VD5.1 V A

18.3 Regulator drop voltage VS > 4V, IVCC = –20mA VS, VCC VD1 250 mV A

18.4 Regulator drop voltage VS > 4V, IVCC = –50mA VS, VCC VD2 400 600 mV A

9. Electrical Characteristics (Continued)

5V < VS < 27V, –40°C < Tj < 150°C, unless otherwise specified. All values refer to GND pins

No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type*

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

ATA6628/ATA6630 [DATASHEET]

9117I–AUTO–10/14

18.5 Regulator drop voltage VS > 3.3V, IVCC = –15mA VS, VCC VD3 200 mV A

18.6 Line regulation 5.5V < VS < 18V VCC VCCline 0.1 0.2 % A

18.7 Load regulation 5mA < IVCC < 50mA

100kHz VCC VCCload 0.1 0.5 % A

18.8 Power supply ripple

rejection

10Hz to 100kHz

CVCC = 10µF

VS = 14V, IVCC = –15mA

VCC 50 dB D

18.9 Output current limitation VS > 5.5V VCC IVCClim –240 –130 –85 mA A

18.10 External load capacity

0.2Ω < ESR < 5Ω at

100kHz

for phase margin ≥ 60° VCC Cload 1.8 10 µF D

ESR < 0.2Ω at 100kHz

for phase margin ≥ 30°

18.11 VCC undervoltage threshold Referred to VCC

VS > 5.5V VCC VthunN 4.2 4.8 V A

18.12 Hysteresis of undervoltage

threshold

Referred to VCC

VS > 5.5V VCC Vhysthun 250 mV A

18.13 Ramp-up time VS > 5.5V to

VCC = 5V

CVCC = 2.2µF

Iload = –5mA at VCC VCC tVCC 370 600 µs A

19 DIV_ON Input Pin

19.1 Low-level voltage input DIV_ON VDIV_ON –0.3 +0.8 V A

19.2 High-level voltage input DIV_ON VDIV_ON 2 VCC + 0.3 V A

19.3 Pull-down resistor VDIV_ON = VCC DIV_ON RDIV_ON 125 250 400 kΩA

19.4 Low-level input current VDIV_ON = 0V DIV_ON IDIV_ON –3 +3 µA A

20 SP_MODE Input Pin

20.1 Low-level voltage input SP_MODE VSP_MODE –0.3 +0.8 V A

20.2 High-level voltage input SP_MODE VSP_MODE 2 VCC + 0.3 V A

20.3 Pull-down resistor VSP_MODE = VCC SP_MODE RSP_MODE 50 125 200 kΩA

20.4 Low-level input current VSP_MODE = 0V SP_MODE ISP_MODE –3 +3 µA A

21 LIN Driver in High-speed Mode (VSP_Mode = VCC)

21.1 Transmission Baud rate VS = 7V to 18V

RLIN = 500Ω, CLIN = 600pF LIN SP 200 kBaud C

21.2 Slope time LIN falling edge VS = 7V to 18V LIN tSL_fall 1 2 µs A

21.3 Slope time LIN rising edge,

depending on RC-load

VS = 14V

RLIN = 500Ω, CLIN = 600pF LIN tSL_rise 1.3 µs D

9. Electrical Characteristics (Continued)

5V < VS < 27V, –40°C < Tj < 150°C, unless otherwise specified. All values refer to GND pins

No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type*

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

ATA6628/ATA6630 [DATASHEET]

9117I–AUTO–10/14

22 ATA6628 Voltage Divider

22.1 Divider ratio VS = 5V to 15V PV 1:6 A

22.2 Divider ratio error –2 +2 % A

22.3 Divider temperature drift 3ppm/°C C

22.4 VBATT range of divider

linearity VBATT 615 V A

22.5 VBATT input current VBATT = 14V VBATT 100 220 µA A

22.6 Maximum output Voltage at

PV VBATT 15V to 40V VBATT 2.5 3.1 3.5 V A

22.7 Pin capacitance PV 2pF

23 ATA6630 Voltage Divider

23.1 Divider ratio VS = 5V to 26V PV 1:6 A

23.2 Divider ratio error –2 +2 % A

23.3 Divider temperature drift 3ppm/°C C

23.4 VBATT range of divider

linearity VBATT 626 V A

23.5 VBATT input current VBATT = 14V VBATT 100 220 µA A

23.6 Maximum output Voltage at

PV VBATT 26V to 40V PV 4.4 4.8 5.2 V A

23.7 Pin capacitance PV 2pF

9. Electrical Characteristics (Continued)

5V < VS < 27V, –40°C < Tj < 150°C, unless otherwise specified. All values refer to GND pins

No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type*

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

ATA6628/ATA6630 [DATASHEET]

9117I–AUTO–10/14

Figure 9-1. Definition of Bus Timing Characteristics

TXD

(Input to transmitting node)

(Transceiver supply

of transmitting node)

RXD

(Output of receiving node1)

RXD

(Output of receiving node2)

LIN Bus Signal

Thresholds of

receiving node1

Thresholds of

receiving node2

tBus_rec(max)

trx_pdr(1)

trx_pdf(2)

trx_pdr(2)

trx_pdf(1)

tBus_dom(min)

tBus_dom(max)

THRec(max)

THDom(max)

THRec(min)

THDom(min)

tBus_rec(min)

tBit tBit

tBit

ATA6628/ATA6630 [DATASHEET]

9117I–AUTO–10/14

Figure 9-2. Typical Application Circuit

67 8 109

20 19 18

MLP 5mm x 5mm

0.65mm pitch

20 lead

Atmel

ATA6628

ATA6630

INH

TXD

NRES

LIN sub bus

WD_OSC

Master node

pull-up

KL_15

MODE

PVCC

VCC

DIV_ON

RXD

LIN

SP_

GND

WAKE

Wake

switch

51kΩ

10kΩ

1kΩ

2.7kΩ

47Ω

10kΩ

47kΩ

10kΩ

NTRIG

Microcontroller

ADC

SP_MODE

DIV_ON

RESET

TXD

RXD

VCC

INH

Ignition

KL15

KL30

VBattery

VBATT

debug

220pF

100nF10μF +

100nF

10nF

10μF

100nF

MODE

GND

ATA6628/ATA6630 [DATASHEET]

9117I–AUTO–10/14

Figure 9-3. Application Circuit with External NPN-Transistor

67 8 109

20 19 18

QFN 5x5mm

0.65mm pitch

20 lead

Atmel

ATA6628/

ATA6630

TXD

INH

NRES

LIN Sub Bus

WD_OSC

Master node

pull-up

MODE

PVCC

KL_15

VCC

SP_MODE

LIN

RXD

DIV_ON

GND

WAKE

Wake

switch

51kΩ

10kΩ 1kΩ

2.7kΩ

10kΩ

47Ω

NTRIG

Microcontroller

RESET

GND

TXD

RXD

VCC

INH

KL30

VBattery

VBATT

ADC

DIV_ON

SP_MODE

220pF

100nF

22nF

100nF

10μF +

100nF 10μF

47kΩ

Debug

Ignition

KL15

2.2μF

3.3Ω

T1 *)

MJD31C

*) Note that the output voltage PVCC is no longer short-ciruit protected when boosting the output current by an external NPN-transistor.

ATA6628/ATA6630 [DATASHEET]

9117I–AUTO–10/14

Figure 9-4. LIN Slave Application with Minimum External Devices

67 8 109

20 19 18 16

TXD

NRES

LIN Sub Bus

WD_OSC

INH

KL_15

PVCC

VCC

MODE

SP_MODE

DIV_ON

RXD

LIN

GND

WAKE

10kΩ

NTRIG

Microcontroller

RESET

TXD

GND

RXD

VBATT

220pF

100nF

VCC

22μF +

100nF

10μF +

QFN 5x5mm

0.65mm pitch

20 lead

Atmel

ATA6628/

ATA6630

KL30

VBattery

Note: No watchdog, no Battery voltage measurement, no local wake up, INH output not used

ATA6628/ATA6630 [DATASHEET]

9117I–AUTO–10/14

11. Package Information

10. Ordering Information

Extended Type Number Package Remarks

ATA6628-GLQW QFN20 3.3V LIN system-basis-chip, Pb-free, 6k, taped and reeled

ATA6630-GLQW QFN20 5V LIN system-basis-chip, Pb-free, 6k, taped and reeled

COMMON DIMENSIONS

(Unit of Measure = mm)

Package Drawing Contact:

packagedrawings@atmel.com

GPC

SYMBOL MIN NOM MAX NOTE

0.8A 0.85 0.9

0A1 0.035 0.05

0.16A3 0.21 0.26

4.9D 55.1

3.0D2 3.1 3.2

4.9E 55.1

3.0E2 3.1 3.2

0.55L0.6 0.65

0.25b0.3 0.35

e0.65

DRAWING NO.

REV. TITLE

6.543-5129.02-4 1

10/18/13

Package: VQFN_5x5_20L

Exposed pad 3.1x3.1

Dimensions in mm

specifications

according to DIN

technical drawings

PIN 1 ID

Z 10:1

Top View

Side View

Bottom View

20 16

ATA6628/ATA6630 [DATASHEET]

9117I–AUTO–10/14

12. Revision History

Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this

document.

Revision No. History

9117I-AUTO-10/14 • Section 10 “Ordering Information” on page 34 updated

• Section 11 “Package Information” on page 34 updated

9117H-AUTO-01/13 • Section 9 “Electrical Characteristics” numbers 22.1, 22.4 and 22.6 on pages 29 changed

9117G-AUTO-03/11

• Features on page 1 changed

• Section 1 “Description” on pages 1 to 2 changed

• Table 2-1 “Pin Description” on page 3 changed

• Section 3 “Functional Description” on page 4 to 7 changed

• Section 4 “Modes of Operation” on pages 8 to 16 changed

• Section 5 “Wake-up Scenarios from Silent or Sleep Mode” on pages 17 to 19 changed

• Section 7 “Absolute Maximum Ratings” on page 22 changed

• Section 9 “Electrical Characteristics” numbers 1.2, 1.3, 1.7, 1.8, 17.1, 17.9, 18.1, 18.10, 21.1,

21.2, 21.3, 23.1, 23.4 and 23.6 on pages 23 to 29 changed

9117F-AUTO-10/10 • Section 9 “Electrical Characteristics” numbers 1.6, 1.7, 10.3, 21.3, 22.4, 22.6, 23.4 on pages

23 to 29 changed

9117E-AUTO-07/10 • Section 6 “Watchdog” on pages 20 to 21 changed

9117D-AUTO-05/10

• Features on page 1 changed

• Pin Description table: row Pin 16 changed

• Text under heading 3.3, 3.8, 3.11, 3.12, 4.2, 5.1, 5.5, 6 changed

• Figures 4-5, 6-1 changed

• Figure 9-1 heading changed

• Figures 9-2 and 9-3 added

• Abs.Max.Rat.Table -> Parameter text in row “ESD according...” changed

• Abs.Max.Rat.Table -> Values in row “ESD HBM following....” changed

• El.Char.Table -> rows changed: 1.2, 1.3, 1.6, 1.7, 7.1,10.4, 17.12, 12.1, 12.2, 17.5, 17.6, 17.7,

17.8, 18.6, 18.7, 18.8, 18.9, 18.13, 11.5, 23.5

• El.Char.Table -> row 8.13 added

XXX

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