Datasheet RL78/G12 R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 RENESAS MCU True Low Power Platform (as low as 63 A/MHz), 1.8V to 5.5V operation, 2 to 16 Kbyte Flash, 31 DMIPS at 24MHz, for General Purpose Applications 1. OUTLINE 1.1 Features Ultra-low power consumption technology VDD = single power supply voltage of 1.8 to 5.5 V which can operate at a low voltage HALT mode STOP mode SNOOZE mode RL78 CPU core CISC architecture with 3-stage pipeline Minimum instruction execution time: Can be changed from high speed (0.04167 s: @ 24 MHz operation with high-speed on-chip oscillator) to ultra-low speed (1 s: @ 1 MHz operation) Address space: 1 MB General-purpose registers: (8-bit register x 8) x 4 banks On-chip RAM: 256 B to 2 KB Code flash memory Code flash memory: 2 to 16 KB Block size: 1 KB Prohibition of block erase and rewriting (security function) On-chip debug function Data flash memory Note Data flash memory: 2 KB Back ground operation (BGO): Instructions are executed from the program memory while rewriting the data flash memory. Number of rewrites: 1,000,000 times (TYP.) Voltage of rewrites: VDD = 1.8 to 5.5 V High-speed on-chip oscillator Select from 24 MHz, 16 MHz, 12 MHz, 8 MHz, 6 MHz, 4 MHz, 3 MHz, 2 MHz, and 1 MHz High accuracy: +/- 1.0 % (VDD = 1.8 to 5.5 V, TA = -20 to +85 C) Power management and reset function On-chip power-on-reset (POR) circuit On-chip voltage detector (LVD) (Select interrupt and reset from 12 levels) Multiplier and divider/multiply-accumulator 16 bits x 16 bits = 32 bits (Unsigned or signed) 32 bits x 32 bits = 32 bits (Unsigned) 16 bits x 16 bits + 32 bits = 32 bits (Unsigned or signed) Serial interface CSI UART 2 Simplified I C communication 2 I C communication : 1 to 3 channels : 1 to 3 channels : 0 to 3 channels : 1 channel Timer 16-bit timer : 4 to 8 channels 12-bit interval timer : 1 channel Watchdog timer : 1 channel (operable with the dedicated low-speed on-chip oscillator) Self-programming (with flash shield window function) Operating ambient temperature TA = -40 to +85 C (A: Consumer applications, D: Industrial applications) TA = -40 to +105 C (G: Industrial applications) Note DMA (Direct Memory Access) controller Note 2 channels Number of clocks during transfer between 8/16-bit SFR and internal RAM: 2 clocks A/D converter 8/10-bit resolution A/D converter (VDD = 1.8 to 5.5 V) 8 to 11 channels, internal reference voltage (1.45 V), and temperature sensor Note I/O port I/O port: 18 to 26 (N-ch open drain I/O [withstand voltage of 6 V]: 2, N-ch open drain I/O [VDD withstand voltage]: 4 to 9) Can be set to N-ch open drain, TTL input buffer, and on-chip pull-up resistor Different potential interface: Can connect to a 1.8/2.5/3 V device On-chip key interrupt function On-chip clock output/buzzer output controller Others On-chip BCD (binary-coded decimal) correction circuit Note Can be selected only in HS (high-speed main) mode. Remark The functions mounted depend on the product. See 1.7 Outline of Functions. * There is difference in specifications between every product. Please refer to specification for details. R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 1 of 106 RL78/G12 1. OUTLINE ROM, RAM capacities Code flash Data flash RAM 20 pins 24 pins 30 pins 16 KB 2 KB 2 KB R5F102AA 2 KB 1.5 KB 12 KB 2KB 1 KB 8 KB 2 KB 768 B 4 KB 2KB 512 B 2 KB 2 KB 256 B Notes 1. R5F1026A Note 1 R5F1036A Note 1 R5F10269 Note 1 R5F10369 Note 1 R5F10268 Note 1 R5F10368 Note 1 R5F103AA R5F1027A Note 1 R5F1037A Note 1 R5F10279 Note 1 R5F102A9 R5F10379 Note 1 R5F103A9 R5F10278 Note 1 R5F102A8 R5F10378 Note 1 R5F103A8 R5F10267 R5F10277 R5F102A7 R5F10367 R5F10377 R5F103A7 R5F10266 Note 2 R5F10366 Note 2 This is 640 bytes when the self-programming function or data flash function is used. (For details, see CHAPTER 3 CPU ARCHITECTURE.) 2. The self-programming function cannot be used for R5F10266 and R5F10366. Caution When the flash memory is rewritten via a user program, the code flash area and RAM area are used because each library is used. When using the library, refer to RL78 Family Flash Self Programming Library Type01 User's Manual and RL78 Family Data Flash Library Type04 User's Manual. R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 2 of 106 RL78/G12 1. OUTLINE 1.2 List of Part Numbers Figure 1-1. Part Number, Memory Size, and Package of RL78/G12 <R> Part No. R 5 F 1 0 2 A A A x x x S P #V0 Packaging specifications: #U5 #V0, #V5 #W5 #X0, #X5 : Tray (HWQFN) : Tray (LSSOP30), Tube (LSSOP20) : Embossed Tape (HWQFN) : Embossed Tape (LSSOP30, LSSOP20) Package type: SP : LSSOP, 0.65 mm pitch NA : HWQFN, 0.50 mm pitch ROM number (Omitted with blank products) Classification: A : Consumer applications, TA = -40C to +85C D : Industrial applications, TA = -40C to +85C G : Industrial applications, TA = -40C to +105C ROM capacity: 6 : 7: 8: 9 : A : 2 KB 4 KB 8 KB 12 KB 16 KB Pin count: 6 : 20-pin 7 : 24-pin A : 30-pin RL78/G12 group Note 1 102 103Notes 1, 2 Memory type: F : Flash memory Renesas MCU Renesas semiconductor product Notes 1. For details about the differences between the R5F102 products and the R5F103 products of RL78/G12, see 1.1 Differences between the R5F102 Products and the R5F103 Products. 2. Products only for "A: Consumer applications (TA = -40 to +85C)" and "D: Industrial applications (TA = -40 to +85C)" R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 3 of 106 RL78/G12 1. OUTLINE Table 1-1. List of Ordering Part Numbers Pin count <R> 20 pins Package 20-pin plastic LSSOP (4.4 6.5 mm, 0.65 mm pitch) Data flash Mounted Not mounted <R> 24 pins 24-pin plastic HWQFN (4 4 mm, 0.5 mm pitch) Mounted Fields of Application Part Number A R5F1026AASP#V5, R5F10269ASP#V5, R5F10268ASP#V5, R5F10267ASP#V5, R5F10266ASP#V5 R5F1026AASP#X5, R5F10269ASP#X5, R5F10268ASP#X5, R5F10267ASP#X5, R5F10266ASP#X5 D R5F1026ADSP#V5, R5F10269DSP#V5, R5F10268DSP#V5, R5F10267DSP#V5, R5F10266DSP#V5 R5F1026ADSP#X5, R5F10269DSP#X5, R5F10268DSP#X5, R5F10267DSP#X5, R5F10266DSP#X5 G R5F1026AGSP#V5, R5F10269GSP#V5, R5F10268GSP#V5, R5F10267GSP#V5, R5F10266GSP#V5 R5F1026AGSP#X5, R5F10269GSP#X5, R5F10268GSP#X5, R5F10267GSP#X5, R5F10266GSP#X5 A R5F1036AASP#V5, R5F10369ASP#V5, R5F10368ASP#V5, R5F10367ASP#V5, R5F10366ASP#V5 R5F1036AASP#X5, R5F10369ASP#X5, R5F10368ASP#X5, R5F10367ASP#X5, R5F10366ASP#X5 D R5F1036ADSP#V5, R5F10369DSP#V5, R5F10368DSP#V5, R5F10367DSP#V5, R5F10366DSP#V5 R5F1036ADSP#X5, R5F10369DSP#X5, R5F10368DSP#X5, R5F10367DSP#X5, R5F10366DSP#X5 A R5F1027AANA#U5, R5F10279ANA#U5, R5F10278ANA#U5, R5F10277ANA#U5 R5F1027AANA#W5, R5F10279ANA#W5, R5F10278ANA#W5, R5F10277ANA#W5 D R5F1027ADNA#U5, R5F10279DNA#U5, R5F10278DNA#U5, R5F10277DNA#U5 R5F1027ADNA#W5, R5F10279DNA#W5, R5F10278DNA#W5, R5F10277DNA#W5 Not mounted G R5F1027AGNA#U5, R5F10279GNA#U5, R5F10278GNA#U5, R5F10277GNA#U5 R5F1027AGNA#W5, R5F10279GNA#W5, R5F10278GNA#W5, R5F10277GNA#W5 A R5F1037AANA#V5, R5F10379ANA#V5, R5F10378ANA#V5, R5F10377ANA#V5 R5F1037AANA#X5, R5F10379ANA#X5, R5F10378ANA#X5, R5F10377ANA#X5 D R5F1037ADNA#V5, R5F10379DNA#V5, R5F10378DNA#V5, R5F10377DNA#V5 A R5F102AAASP#V0, R5F102A9ASP#V0, R5F102A8ASP#V0, R5F102A7ASP#V0 R5F102AAASP#X0, R5F102A9ASP#X0, R5F102A8ASP#X0, R5F102A7ASP#X0 D R5F102AADSP#V0, R5F102A9DSP#V0, R5F102A8DSP#V0, R5F102A7DSP#V0 R5F102AADSP#X0, R5F102A9DSP#X0, R5F102A8DSP#X0, R5F102A7DSP#X0 G R5F102AAGSP#V0, R5F102A9GSP#V0, R5F102A8GSP#V0, R5F102A7GSP#V0 R5F102AAGSP#X0, R5F102A9GSP#X0, R5F102A8GSP#X0, R5F102A7GSP#X0 A R5F103AAASP#V0, R5F103A9ASP#V0, R5F103A8ASP#V0, R5F103A7ASP#V0 R5F103AAASP#X0, R5F103A9ASP#X0, R5F103A8ASP#X0, R5F103A7ASP#X0 D R5F103AADSP#V0, R5F103A9DSP#V0, R5F103A8DSP#V0, R5F103A7DSP#V0 R5F103AADSP#X0, R5F103A9DSP#X0, R5F103A8DSP#X0, R5F103A7DSP#X0 R5F1037ADNA#X5, R5F10379DNA#X5, R5F10378DNA#X5, R5F10377DNA#X5 30 pins 30-pin plastic LSSOP (7.62 mm (300), 0.65 mm pitch ) Mounted Not mounted Note For fields of application, see Figure 1-1 Part Number, Memory Size, and Package of RL78/G12. Caution The ordering part numbers represent the numbers at the time of publication. For the latest ordering part numbers, refer to the target product page of the Renesas Electronics website. R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 4 of 106 RL78/G12 1. OUTLINE 1.3 Differences between the R5F102 Products and the R5F103 Products The following are differences between the R5F102 products and the R5F103 products. Whether the data flash memory is mounted or not High-speed on-chip oscillator oscillation frequency accuracy Number of channels in serial interface Whether the DMA function is mounted or not Whether a part of the safety functions are mounted or not 1.3.1 Data Flash The data flash memory of 2 KB is mounted on the R5F102 products, but not on the R5F103 products. Product Data Flash R5F102 products 2KB R5F1026A, R5F1027A, R5F102AA, R5F10269, R5F10279, R5F102A9, R5F10268, R5F10278, R5F102A8, R5F10267, R5F10277, R5F102A7, R5F10266 Note R5F103 products Not mounted R5F1036A, R5F1037A, R5F103AA, R5F10369, R5F10379, R5F103A9, R5F10368, R5F10378 R5F103A8, R5F10367, R5F10377, R5F103A7, R5F10366 Note The RAM in the R5F10266 has capacity as small as 256 bytes. Depending on the customer's program specification, the stack area to execute the data flash library may not be kept and data may not be written to or erased from the data flash memory. Caution When the flash memory is rewritten via a user program, the code flash area and RAM area are used because each library is used. When using the library, refer to RL78 Family Flash Self Programming Library Type01 User's Manual and RL78 Family Data Flash Library Type04 User's Manual. R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 5 of 106 RL78/G12 1. OUTLINE 1.3.2 On-chip oscillator characteristics (1) High-speed on-chip oscillator oscillation frequency of the R5F102 products Oscillator Condition MIN MAX Unit High-speed on-chip TA = -20 to +85 C -1.0 +1.0 % oscillator oscillation TA = -40 to -20 C -1.5 +1.5 frequency accuracy TA = +85 to +105 C -2.0 +2.0 (2) High-speed on-chip oscillator oscillation frequency of the R5F103 products Oscillator Condition MIN MAX Unit High-speed on-chip TA = -40 to + 85 C -5.0 +5.0 % oscillator oscillation frequency accuracy 1.3.3 Peripheral Functions The following are differences in peripheral functions between the R5F102 products and the R5F103 products. R5F102 product RL78/G12 20, 24 pin 30 pin product product Serial interface product product 1 channel 3 channels 1 channel CSI 2 channels 3 channels 1 channel 2 channels 3 channels None Simplified I C DMA function R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 30 pin UART 2 Safety function R5F103 product 20, 24 pin 2 channels None CRC operation Yes None RAM guard Yes None SFR guard Yes None Page 6 of 106 RL78/G12 1. OUTLINE 1.4 Pin Configuration (Top View) 1.4.1 20-pin products 20-pin plastic LSSOP (4.4 6.5 mm, 0.65 mm pitch) 1 2 3 4 5 6 7 8 9 10 RL78/G12 (Top View) <R> P20/ANI0/AV REFP P42/ANI21/SCK01Note/SCL01Note/TI03/TO03 P41/ANI22/SO01Note/SDA01Note/TI02/TO02/INTP1 P40/KR0/TOOL0 P125/KR1/SI01Note/RESET P137/INTP0 P122/KR2/X2/EXCLK/(TI02)/(INTP2) P121/KR3/X1/(TI03)/(INTP3) VSS VDD 20 19 18 17 16 15 14 13 12 11 P21/ANI1/AV REFM P22/ANI2 P23/ANI3 P10/ANI16/PCLBUZ0/SCK00/SCL00Note P11/ANI17/SI00/RxD0/SDA00 Note/TOOLRxD P12/ANI18/SO00/TxD0/TOOLTxD P13/ANI19/TI00/TO00/INTP2 P14/ANI20/TI01/TO01/INTP3 P61/KR5/SDAA0/(RxD0) P60/KR4/SCLA0/(TxD0) Note Provided only in the R5F102 products. Remarks 1. For pin identification, see 1.5 Pin Identification. 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). See Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR). R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 7 of 106 RL78/G12 1. OUTLINE 1.4.2 24-pin products P23/ANI3 Note P10/ANI16/PCLBUZ0/SCK00/SCL00 P11/ANI17/SI00/RxD0/SDA00Note/TOOLRxD P12/ANI18/SO00/TxD0/TOOLTxD P13/ANI19/TO00/INTP2 P14/ANI20/TO01/INTP3 24-pin plastic HWQFN (4 4 mm, 0.5 mm pitch) exposed die pad P22/ANI2 P21/ANI1/AVREFM P20/ANI0/AVREFP Note Note P42/ANI21/SCK01 /SCL01 /TI03/TO03 Note Note P41/ANI22/SO01 /SDA01 /TI02/TO02/INTP1 P40/KR0/TOOL0 18 17 16 15 14 13 19 12 20 11 21 RL78/G12 10 22 (Top View) 9 23 8 24 7 1 2 3 4 5 6 P61/KR5/SDAA0/(RxD0) P60/KR4/SCLA0/(TxD0) P03/KR9 P02/KR8/(SCK01)Note/(SCL01)Note P01/KR7/(SO01)Note/(SDA01)Note P00/KR6/(SI01)Note INDEX MARK Note P125/KR1/SI01 /RESET P137/INTP0 P122/KR2/X2/EXCLK/(TI02)/(INTP2) P121/KR3/X1/(TI03)/(INTP3) VSS VDD <R> Note Provided only in the R5F102 products. Remarks 1. For pin identification, see 1.5 Pin Identification. 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). See Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR). 3. It is recommended to connect an exposed die pad to Vss. R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 8 of 106 RL78/G12 1. OUTLINE 1.4.3 30-pin products 30-pin plastic LSSOP (7.62 mm (300), 0.65 mm pitch) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RL78/G12 (Top View) <R> P20/ANI0/AVREFP P01/ANI16/TO00/RxD1Note Note P00/ANI17/TI00/TxD1 P120/ANI19 P40/TOOL0 RESET P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS VDD P60/SCLA0 P61/SDAA0 P31/TI03/TO03/INTP4/PCLBUZ0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 P21/ANI1/AVREFM P22/ANI2 P23/ANI3 P147/ANI18 P10/SCK00/SCL00Note/(TI07/TO07) P11/SI00/RxD0/TOOLRxD/SDA00Note/(TI06/TO06) P12/SO00/TxD0/TOOLTxD/(TI05/TO05) P13/TxD2Note/SO20Note/(SDAA0)Note/(TI04/TO04) P14/RxD2Note/SI20Note/SDA20Note/(SCLA0)Note/(TI03/TO03) P15/PCLBUZ1/SCK20Note/SCL20Note/(TI02/TO02) P16/TI01/TO01/INTP5/(RxD0) P17/TI02/TO02/(TxD0) Note P51/INTP2/SO11 Note Note P50/INTP1/SI11 /SDA11 P30/INTP3/SCK11Note/SCL11Note Note Provided only in the R5F102 products. Caution Connect the REGC pin to VSS via capacitor (0.47 to 1 F). Remarks 1. For pin identification, see 1.5 Pin Identification. 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). See Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR). R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 9 of 106 RL78/G12 1. OUTLINE 1.5 Pin Identification ANI0 to ANI3, ANI16 to ANI22: AVREFM: REGC: Regulator Capacitance Analog input RESET: Reset Analog Reference Voltage Minus RxD0 to RxD2: Receive Data AVREFP: Analog reference voltage plus SCK00, SCK01, SCK11, EXCLK: External Clock Input SCK20: (Main System Clock) SCL00, SCL01, Interrupt Request From Peripheral SCL11, SCL20, SCLA0: INTP0 to INTP5 Serial Clock Input/Output Serial Clock Input/Output KR0 to KR9: Key Return SDA00, SDA01, SDA11, P00 to P03: Port 0 SDA20, SDAA0: Serial Data Input/Output P10 to P17: Port 1 SI00, SI01, SI11, SI20: Serial Data Input P20 to P23: Port 2 SO00, SO01, SO11, P30 to P31: Port 3 SO20: Serial Data Output P40 to P42: Port 4 TI00 to TI07: Timer Input P50, P51: Port 5 TO00 to TO07: Timer Output P60, P61: Port 6 TOOL0: Data Input/Output for Tool P120 to P122, P125: Port 12 TOOLRxD, TOOLTxD: Data Input/Output for External P137: Port 13 P147: Port 14 TxD0 to TxD2: Transmit Data PCLBUZ0, PCLBUZ1: Programmable Clock Output/ VDD: Power supply VSS: Ground X1, X2: Crystal Oscillator (Main System Buzzer Output Device Clock) R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 10 of 106 RL78/G12 1. OUTLINE 1.6 Block Diagram 1.6.1 20-pin products TAU0 (4ch) TI00/TO00 ch00 TI01/TO01 ch01 TI02/TO02 ch02 TI03/TO03 ch03 PORT 1 5 P10 to P14 PORT 2 4 P20 to P23 PORT 4 3 P40 to P42 PORT 6 2 P60, P61 PORT 12 3 P121, P122, P125 SAU0 (2ch) RxD0 TxD0 SCK00 SI00 SO00 UART0 Code flash: 16 KB Data flash: 2 KBNote PORT 13 P137 CSI00 Buzzer/clock output control SCK01 SI01 SO01 CSI01 SCL00 SDA00 IIC00 SCL01 SDA01 IIC01Note Note Note PCLBUZ0 Interrupt control RL78 CPU core Key return 6ch 6 KR0 to KR5 Interrupt control 4ch 4 INTP0 to INTP3 Note DMA 2ch RAM 1.5 KB Note CRC Window watchdog timer TOOL0 Multiplier & divider multiplyaccumulator SCLA0 SDAA0 12-bit Intervaltimer On-chip debug BCD adjustment IICA0 RESET Clock Generator + Reset Generator Main OSC 1 to 20 MHz X1 X2/EXCLK Power-on reset/voltage detector VDD Note Low Speed On-chip oscillator 15 kHz 10-bit A/D converter 11ch 9 ANI2, ANI3, ANI16 to ANI22 ANI0/AVREFP ANI1/AVREFM High-Speed on-chip oscillator 1 to 24 MHz VSS TOOL TOOL TxD RxD Provided only in the R5F102 products. R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 11 of 106 RL78/G12 1. OUTLINE 1.6.2 24-pin products TAU0 (4ch) TI00/TO00 ch00 TI01/TO01 ch01 TI02/TO02 ch02 TI03/TO03 ch03 Port 0 4 P00 to P03 Port 1 5 P10 to P14 Port 2 4 P20 to P23 Port 4 3 P40 to P42 Port 6 2 P60, P61 Port 12 3 P121, P122, 125 SAU0 (2ch) RxD0 TxD0 UART0 SCK00 SI00 SO00 CSI00 SCK01 SI01 SO01 Code flash: 16 KB Data flash: 2 KBNote P137 Port 13 Buzzer/clock output control CSI01 Note SCL00 SDA00 IIC00 Note SCL01 SDA01 IIC01 Note PCLBUZ0 Interrupt control RL78 CPU core Key return 10ch 10 Interrupt control 4ch 4 DMA 2ch RAM 1.5 KB CRC On-chip debug BCD adjustment IICA0 SCLA0 SDAA0 Multiplier & divider/ multiplyaccumulator RESET Clock Generator + Reset Generator Main OSC 1to 20 MHz X1 X2/EXCLK Low Speed On-chip oscillator 15 KHz 12-bit Interval timer 10-bit A/D converter 11ch 9 ANI2, ANI3, ANI16 to ANI22 ANI0/AVREFP ANI1/AVREFM High-Speed On-chip oscillator 1 to 24 MHz Poer-on reset/voltage detector IICA0 VDD INTP0 to INTP3 Note Window watchdog timer TOOL0 KR0 to KR9 Note VSS TOOL TOOL TxD RxD Note Provided only in the R5F102 products. R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 12 of 106 RL78/G12 1. OUTLINE 1.6.3 30-pin products TAU (8ch) TI00 TO00 ch0 TI01/TO01 ch1 TI02/TO02 ch2 Port 0 2 P00, P01 TI03/TO03 ch3 Port 1 8 P10 to P17 (TI04/TO04) ch4 Port 2 4 P20 to P23 (TI05/TO05) ch5 Port 3 2 P30, P31 (TI06/TO06) ch6 (TI07/TO07) ch7 P40 Port 4 SAU0 (4ch) RxD0 TxD0 RxD1 TxD1 SCK00 SI00 SO00 SCK11 SI11 SO11 Code flash: 16 KB Note Data flash: 2 KB Port 5 2 P50, P51 Port 6 2 P60, P61 Port 12 2 UART0 P120 Note UART1 CSI00 RL78 CPU core Port 13 P137 Port 14 P147 Note DMA 2ch Note CSI11 SCL00 SDA00 IIC00 SCL11 SDA11 IIC11 RAM 2 KB Note Buzzer/clock output control Interrupt control 6ch Note CRC SAU0 (2ch) RxD2 TxD2 UART2 SCK20 SI20 SO20 CSI20 SCL20 SDA20 IIC20 2 6 PCLBUZ0, PCLBUZ1 INTP0 to INTP5 Note RESET Note Clock Generator + Reset Generator Main OSC 1 to 20 MHz X1 X2/EXCLK Window watchdog timer Low Speed On-chip oscillator 15 KHz 12-bit Interval timer High-Speed On-chip oscillator 1 to 24 MHz Poer-on reset/voltage detector VDD TOOL0 P121, P122 Interrupt control VSS TOOL TOOL TxD RxD 10-bit A/D converter 8ch 6 ANI2, ANI3, ANI16 to ANI19 ANI0/AVREFP ANI1/AVREFM On-chip debug VOLTAGE REGULATOR REGC BCD adjustment Multiplier & divider/ multiplyaccumulator SCLA0 SDAA0 IICA0 Note Provided only in the R5F102 products. Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). See Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR). R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 13 of 106 RL78/G12 1. OUTLINE 1.7 Outline of Functions This outline describes the function at the time when Peripheral I/O redirection register (PIOR) is set to 00H. (1/2) Item 20-pin R5F1026x Code flash memory Data flash memory RAM 24-pin R5F1036x 2 to 16 KB R5F1027x R5F1037x 2 KB Note 1 256 B to 1.5 KB Main High-speed system clock R5F102Ax R5F103Ax 4 to 16 KB 2 KB 2 KB 512 B to 1.5 KB Address space <R> 30-pin 512 B to 2KB 1 MB X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK) system HS (High-speed main) mode : 1 to 20 MHz (VDD = 2.7 to 5.5 V), clock HS (High-speed main) mode : 1 to 16 MHz (VDD = 2.4 to 5.5 V), LS (Low-speed main) mode : 1 to 8 MHz (VDD = 1.8 to 5.5 V) High-speed on-chip HS (High-speed main) mode : 1 to 24 MHz (VDD = 2.7 to 5.5 V), oscillator clock HS (High-speed main) mode : 1 to 16 MHz (VDD = 2.4 to 5.5 V), LS (Low-speed main) mode : 1 to 8 MHz (VDD = 1.8 to 5.5 V) Low-speed on-chip oscillator clock 15 kHz (TYP) General-purpose register (8-bit register 8) 4 banks Minimum instruction execution time 0.04167 s (High-speed on-chip oscillator clock: fIH = 24 MHz operation) 0.05 s (High-speed system clock: fMX = 20 MHz operation) Instruction set Data transfer (8/16 bits) Adder and subtractor/logical operation (8/16 bits) Multiplication (8 bits 8 bits) Rotate, barrel shift, and bit manipulation (set, reset, test, and Boolean operation), etc. I/O port Total CMOS I/O CMOS input 18 22 26 12 16 21 (N-ch O.D. I/O (N-ch O.D. I/O (N-ch O.D. I/O [VDD withstand voltage]: 4) [VDD withstand voltage]: 5) [VDD withstand voltage]: 9) 4 4 3 N-ch open-drain I/O 2 (6 V tolerance) Timer 16-bit timer 4 channels Watchdog timer 1 channel 12-bit Interval timer 1 channel Timer output 4 channels (PWM outputs: 3 Notes 1. 8 channels 8 channels Note 3 ) (PWM outputs: 7 Note 3 Note 2 ) The self-programming function cannot be used in the R5F10266 and R5F10366. 2. The maximum number of channels when PIOR0 is set to 1. 3. The number of PWM outputs varies depending on the setting of channels in use (the number of masters and slaves). (See 6.9.3 Operation as multiple PWM output function.) Caution When the flash memory is rewritten via a user program, the code flash area and RAM area are used because each library is used. When using the library, refer to RL78 Family Flash Self Programming Library Type01 User's Manual and RL78 Family Data Flash Library Type04 User's Manual. R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 14 of 106 RL78/G12 1. OUTLINE (2/2) Item 20-pin R5F1026x 24-pin R5F1036x R5F1027x Clock output/buzzer output 30-pin R5F1037x R5F102Ax 1 R5F103Ax 2 2.44 kHz to 10 MHz: (Peripheral hardware clock: fMAIN = 20 MHz operation) 8/10-bit resolution A/D converter Serial interface 11 channels 8 channels [R5F1026x (20-pin), R5F1027x (24-pin)] 2 CSI: 2 channels/Simplified I C: 2 channels/UART: 1 channel [R5F102Ax (30-pin)] 2 CSI: 1 channel/Simplified I C: 1 channel/UART: 1 channel 2 CSI: 1 channel/Simplified I C: 1 channel/UART: 1 channel 2 CSI: 1 channel/Simplified I C: 1 channel/UART: 1 channel [R5F1036x (20-pin), R5F1037x (24-pin)] 2 CSI: 1 channel/Simplified I C: 0 channel/UART: 1 channel [R5F103Ax (30-pin)] 2 CSI: 1 channel/Simplified I C: 0 channel/UART: 1 channel 2 I C bus 1 channel Multiplier and divider/multiply- 16 bits 16 bits = 32 bits (unsigned or signed) accumulator 32 bits 32 bits = 32 bits (unsigned) 16 bits 16 bits + 32 bits = 32 bits (unsigned or signed) DMA controller Vectored interrupt Internal sources External 2 channels 2 channels 2 channels 18 16 18 16 26 19 5 Key interrupt 6 6 10 Reset by RESET pin Reset Internal reset by watchdog timer Internal reset by power-on-reset Internal reset by voltage detector Internal reset by illegal instruction execution Note Internal reset by RAM parity error Internal reset by illegal-memory access Power-on-reset circuit Voltage detector Power-on-reset: 1.51 V (TYP) Power-down-reset: 1.50 V (TYP) Rising edge : 1.88 to 4.06 V (12 stages) Falling edge : 1.84 to 3.98 V (12 stages) On-chip debug function Provided Power supply voltage VDD = 1.8 to 5.5 V Operating ambient temperature TA = 40 to +85C (A: Consumer applications, D: Industrial applications), TA = 40 to +105C (G: Industrial applications) Note The illegal instruction is generated when instruction code FFH is executed. Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip debug emulator. R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 15 of 106 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C) RL78/G12 <R> 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C) <R> This chapter describes the following electrical specifications. Target products <R> A: Consumer applications TA = -40 to +85C R5F102xxAxx, R5F103xxAxx D: Industrial applications TA = -40 to +85C <R> R5F102xxDxx, R5F103xxDxx G: Industrial applications when TA = -40 to +105C products is used in the range of TA = -40 to +85C <R> R5F102xxGxx Cautions 1. The RL78 microcontrollers have an on-chip debug function, which is provided for development and evaluation. Do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not liable for problems occurring when the on-chip debug function is used. 2. The pins mounted depend on the product. Refer to 2.1 Port Functions to 2.2.1 Functions for each product. R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 16 of 106 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C) RL78/G12 2.1 Absolute Maximum Ratings Absolute Maximum Ratings (TA = 25C) Parameter Supply Voltage Symbols Conditions Ratings VDD REGC terminal input Note1 voltage VIREGC REGC Unit 0.5 to + 6.5 V 0.3 to +2.8 V and 0.3 to VDD + 0.3 Note 2 Input Voltage VI1 Other than P60, P61 VI2 P60, P61 (N-ch open drain) Output Voltage VO Analog input voltage VAI 0.3 to VDD + 0.3 IOH1 V Note 3 V 0.3 to 6.5 0.3 to VDD + 0.3 V 0.3 to VDD + 0.3 20-, 24-pin products: ANI0 to ANI3, ANI16 to ANI22 V and 0.3 to Notes 3, 4 AVREF(+)+0.3 30-pin products: ANI0 to ANI3, ANI16 to ANI19 Output current, high Note 3 Per pin Other than P20 to P23 40 mA Total of all pins All the terminals other than P20 to P23 170 mA 20-, 24-pin products: P40 to P42 70 mA , 20-, 24-pin products: P00 to P03 P10 to P14 30-pin products: P10 to P17, P30, P31, P50, P51, P147 100 mA P20 to P23 0.5 mA 2 mA 30-pin products: P00, P01, P40, P120 Note 5 IOH2 Per pin Total of all pins Output current, low IOL1 Per pin Other than P20 to P23 40 mA Total of all pins All the terminals other than P20 to P23 170 mA 20-, 24-pin products: P40 to P42 30-pin products: P00, P01, P40, P120 70 mA 100 mA 1 mA 5 mA Note 5 , 20-, 24-pin products: P00 to P03 P10 to P14, P60, P61 30-pin products: P10 to P17, P30, P31, P50, P51, P60, P61, P147 IOL2 Per pin Total of all pins P20 to P23 Operating ambient temperature TA 40 to +85 C Storage temperature Tstg 65 to +150 C Notes 1. 2. 3. 4. 5. 30-pin product only. Connect the REGC pin to VSS via a capacitor (0.47 to 1 F). This value determines the absolute maximum rating of the REGC pin. Do not use it with voltage applied. Must be 6.5 V or lower. Do not exceed AVREF (+) + 0.3 V in case of A/D conversion target pin. 24-pin products only. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remarks 1. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. 2. AVREF(+) : + side reference voltage of the A/D converter. 3. VSS : Reference voltage R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 17 of 106 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C) RL78/G12 2.2 Oscillator Characteristics 2.2.1 X1 oscillator characteristics (TA = 40 to +85C, 1.8 V VDD VDD 5.5 V, VSS = 0 V) Parameter Resonator X1 clock oscillation Note frequency (fX) Note Conditions MIN. TYP. MAX. Ceramic resonator / 2.7 V VDD 5.5 V 1.0 20.0 crystal oscillator 1.8 V VDD < 2.7 V 1.0 8.0 Unit MHz Indicates only permissible oscillator frequency ranges. Refer to AC Characteristics for instruction execution time. Request evaluation by the manufacturer of the oscillator circuit mounted on a board to check the oscillator characteristics. Caution Since the CPU is started by the high-speed on-chip oscillator clock after a reset release, check the X1 clock oscillation stabilization time using the oscillation stabilization time counter status register (OSTC) by the user. Determine the oscillation stabilization time of the OSTC register and the oscillation stabilization time select register (OSTS) after sufficiently evaluating the oscillation stabilization time with the resonator to be used. Remark When using the X1 oscillator, refer to 5.4 System Clock Oscillator. 2.2.2 On-chip oscillator characteristics (TA = 40 to +85C, 1.8 V VDD 5.5 V, VSS = 0 V) Oscillators High-speed on-chip oscillator clock frequency Parameters Conditions MIN. MAX. Unit 1 24 MHz TA = 20 to +85C -1.0 +1.0 % TA = 40 to 20C -1.5 +1.5 % -5.0 +5.0 % fIH TYP. Notes 1, 2 High-speed on-chip oscillator R5F102 products clock frequency accuracy R5F103 products Low-speed on-chip oscillator 15 fIL kHz clock frequency Low-speed on-chip oscillator -15 +15 % clock frequency accuracy Notes 1. High-speed on-chip oscillator frequency is selected by bits 0 to 3 of option byte (000C2H) and bits 0 to 2 of HOCODIV register. 2. This only indicates the oscillator characteristics. Refer to AC Characteristics for instruction execution time. R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 18 of 106 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C) RL78/G12 2.3 DC Characteristics 2.3.1 Pin characteristics (TA = 40 to +85C, 1.8 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Note 1 Output current, high IOH1 (1/4) Conditions MIN. 20-, 24-pin products: Note 4 Per pin for P00 to P03 TYP. MAX. Unit 10.0 mA Note 2 , P10 to P14, P40 to P42 30-pin products: Per pin for P00, P01, P10 to P17, P30, P31, P40, P50, P51, P120, P147 4.0 V VDD 5.5 V 30.0 mA Total of P40 to P42 2.7 V VDD < 4.0 V 6.0 mA 30-pin products: 1.8 V VDD < 2.7 V 4.5 mA 4.0 V VDD 5.5 V 80.0 mA 2.7 V VDD < 4.0 V 18.0 mA 1.8 V VDD < 2.7 V 10.0 mA 100 mA Per pin for P20 to P23 0.1 mA Total of all pins 0.4 mA 20-, 24-pin products: Total of P00, P01, P40, P120 (When duty 70% Note 3 ) 20-, 24-pin products: Note 4 Total of P00 to P03 , P10 to P14 30-pin products: Total of P10 to P17, P30, P31, P50, P51, P147 (When duty 70% Note 3 ) Total of all pins (When duty 70% Note 3 IOH2 Notes 1. ) value of current at which the device operation is guaranteed even if the current flows from the VDD pin to an output pin. 2. 3. However, do not exceed the total current value. The output current value under conditions where the duty factor 70%. If duty factor 70%: The output current value can be calculated with the following expression (where n represents the duty factor as a percentage). Total output current of pins = (IOH x 0.7)/(n x 0.01) <Example> Where n = 80% and IOH = 10.0 mA Total output current of pins = (10.0 x 0.7)/(80 x 0.01) 8.7 mA However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A current higher than the absolute maximum rating must not flow into one pin. 4. 24-pin products only. Caution P10 to P12 and P41 for 20-pin products, P01, P10 to P12, and P41 for 24-pin products, and P00, P10 to P15, P17, and P50 for 30-pin products do not output high level in N-ch open-drain mode. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 19 of 106 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C) RL78/G12 (TA = 40 to +85C, 1.8 V VDD 5.5 V, VSS = 0 V) Parameter Output current, low Symbol Note 1 (2/4) Conditions MIN. 20-, 24-pin products: IOL1 Per pin for P00 to P03 Note 4 TYP. MAX. Unit 20.0 mA Note 2 , P10 to P14, P40 to P42 30-pin products: Per pin for P00, P01, P10 to P17, P30, P31, P40, P50, P51, P120, P147 15.0 Per pin for P60, P61 mA Note 2 20-, 24-pin products: 4.0 V VDD 5.5 V 60.0 mA Total of P40 to P42 2.7 V VDD < 4.0 V 9.0 mA 30-pin products: 1.8 V VDD < 2.7 V 1.8 mA 4.0 V VDD 5.5 V 80.0 mA 2.7 V VDD < 4.0 V 27.0 mA 1.8 V VDD < 2.7 V 5.4 mA 140 mA Per pin for P20 to P23 0.4 mA Total of all pins 1.6 mA Total of P00, P01, P40, P120 (When duty 70% Note 3 ) 20-, 24-pin products: Note 4 , Total of P00 to P03 P10 to P14, P60, P61 30-pin products: Total of P10 to P17, P30, P31, P50, P51, P60, P61, P147 (When duty 70% Note 3 ) Total of all pins (When duty 70% Note 3 IOL2 Notes 1. ) Value of current at which the device operation is guaranteed even if the current flows from an output pin to the VSS pin. 2. However, do not exceed the total current value. 3. The output current value under conditions where the duty factor 70%. If duty factor 70%: The output current value can be calculated with the following expression (where n represents the duty factor as a percentage). Total output current of pins = (IOL x 0.7)/(n x 0.01) <Example> Where n = 80% and IOL = 10.0 mA Total output current of pins = (10.0 x 0.7)/(80 x 0.01) 8.7 mA However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A current higher than the absolute maximum rating must not flow into one pin. 4. Remark 24-pin products only. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 20 of 106 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C) RL78/G12 (TA = 40 to +85C, 1.8 V VDD 5.5 V, VSS = 0 V) Parameter Input voltage, high Symbol VIH1 (3/4) Conditions MIN. Normal input buffer 20-, 24-pin products: P00 to P03 TYP. MAX. Unit 0.8VDD VDD V Note 2 , P10 to P14, P40 to P42 30-pin products: P00, P01, P10 to P17, P30, P31, P40, P50, P51, P120, P147 VIH2 4.0 V VDD 5.5 V 2.2 VDD V 20-, 24-pin products: P10, P11 3.3 V VDD < 4.0 V 2.0 VDD V 1.8 V VDD < 3.3 V 1.5 VDD V 0.7VDD VDD V 0.7VDD 6.0 V 0.8VDD VDD V 0 0.2VDD V 4.0 V VDD 5.5 V 0 0.8 V 20-, 24-pin products: P10, P11 3.3 V VDD < 4.0 V 0 0.5 V 1.8 V VDD < 3.3 V 0 0.32 V 0 0.3VDD V 0 0.3VDD V 0 0.2VDD V TTL input buffer 30-pin products: P01, P10, P11, P13 to P17 Input voltage, low VIH3 P20 to P23 VIH4 P60, P61 Note 1 VIH5 P121, P122, P125 , P137, EXCLK, RESET VIL1 Normal input buffer 20-, 24-pin products: P00 to P03 Note 2 , P10 to P14, P40 to P42 30-pin products: P00, P01, P10 to P17, P30, P31, P40, P50, P51, P120, P147 VIL2 TTL input buffer 30-pin products: P01, P10, P11, P13 to P17 Output voltage, high VIL3 P20 to P23 VIL4 P60, P61 Note 1 VIL5 P121, P122, P125 VOH1 20-, 24-pin products: P00 to P03 , P137, EXCLK, RESET Note 2 , P10 to P14, 4.0 V VDD 5.5 V, P40 to P42 4.0 V VDD 5.5 V, 30-pin products: IOH1 = 3.0 mA P00, P01, P10 to P17, P30, 2.7 V VDD 5.5 V, P31, P40, P50, P51, P120, IOH1 = 2.0 mA P147 VDD1.5 V VDD0.7 V VDD0.6 V VDD0.5 V VDD0.5 V IOH1 = 10.0 mA 1.8 V VDD 5.5 V, IOH1 = 1.5 mA VOH2 Notes 1. 2. P20 to P23 IOH2 = 100 A 20, 24-pin products only. 24-pin products only. Caution The maximum value of VIH of pins P10 to P12 and P41 for 20-pin products, P01, P10 to P12, and P41 for 24pin products, and P00, P10 to P15, P17, and P50 for 30-pin products is VDD even in N-ch open-drain mode. High level is not output in the N-ch open-drain mode. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 21 of 106 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C) RL78/G12 (TA = 40 to +85C, 1.8 V VDD 5.5 V, VSS = 0 V) Parameter Output voltage, low Symbol VOL1 (4/4) Conditions 20-, 24-pin products: P00 to P03 Note , P10 to P14, TYP. 4.0 V VDD 5.5 V, MAX. Unit 1.3 V 0.7 V 0.6 V 0.4 V 0.4 V IOL1 = 20.0 mA P40 to P42 4.0 V VDD 5.5 V, 30-pin products: P00, P01, IOL1 = 8.5 mA P10 to P17, P30, P31, P40, 2.7 V VDD 5.5 V, P50, P51, P120, P147 MIN. IOL1 = 3.0 mA 2.7 V VDD 5.5 V, IOL1 = 1.5 mA 1.8 V VDD 5.5 V, IOL1 = 0.6 mA VOL2 P20 to P23 IOL2 = 400 A 0.4 V VOL3 P60, P61 4.0 V VDD 5.5 V, 2.0 V 0.4 V 0.4 V 0.4 V VI = VDD 1 A VI = VDD Input port or external clock input 1 A 10 A 1 A 1 A 10 A 100 k IOL1 = 15.0 mA 4.0 V VDD 5.5 V, IOL1 = 5.0 mA 2.7 V VDD 5.5 V, IOL1 = 3.0 mA 1.8 V VDD 5.5 V, IOL1 = 2.0 mA Input leakage current, ILIH1 Other than P121, P122 high ILIH2 P121, P122 (X1, X2/EXCLK) When resonator connected Input leakage current, ILIL1 Other than P121, VI = VSS P122 low ILIL2 P121, P122 VI = VSS Input port or external (X1, X2/EXCLK) clock input When resonator connected On-chip pull-up RU 20-, 24-pin products: P00 to P03 resistance VI = VSS, input port 10 20 Note , P10 to P14, P40 to P42, P125, RESET 30-pin products: P00, P01, P10 to P17, P30, P31, P40, P50, P51, P120, P147 Note 24-pin products only. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 22 of 106 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C) RL78/G12 2.3.2 Supply current characteristics (1) 20-, 24-pin products (TA = 40 to +85C, 1.8 V VDD 5.5 V, VSS = 0 V) Parameter Supply current Symbol IDD1 Note 1 (1/2) Conditions Note 3 Operating HS(High-speed fIH = 24 MHz Note 4 mode main) mode MIN. Basic VDD = 5.0 V operation VDD = 3.0 V 1.5 Normal 5.0 3.3 5.0 VDD = 5.0 V 2.5 3.7 VDD = 3.0 V 2.5 3.7 VDD = 3.0 V 1.2 1.8 VDD = 2.0 V 1.2 1.8 Square wave input 2.8 4.4 Resonator connection 3.0 4.6 Square wave input 2.8 4.4 Resonator connection 3.0 4.6 Square wave input 1.8 2.6 Resonator connection 1.8 2.6 Square wave input 1.8 2.6 Resonator connection 1.8 2.6 Square wave input 1.1 1.7 Resonator connection 1.1 1.7 Square wave input 1.1 1.7 Resonator connection 1.1 1.7 fIH = 8 MHz Note 2 Note4 , VDD = 5.0 V Note 2 fMX = 20 MHz , VDD = 3.0 V Note 2 fMX = 10 MHz , VDD = 5.0 V Note 2 fMX = 10 MHz , VDD = 3.0 V LS(Low-speed main) mode Note 4 Note 2 fMX = 8 MHz , VDD = 3.0 V Note 2 fMX = 8 MHz , VDD = 2.0 V Notes 1. mA mA mA Note 4 HS(High-speed fMX = 20 MHz main) mode 1.5 3.3 Note 3 Unit mA VDD = 5.0 V fIH = 16 MHz main) mode MAX. operation VDD = 3.0 V Note 3 LS(Low-speed TYP. mA mA mA mA mA mA Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is fixed to VDD or VSS. The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. 2. When high-speed on-chip oscillator clock is stopped. 3. When high-speed system clock is stopped 4. Relationship between operation voltage width, operation frequency of CPU and operation mode is as follows. HS(High speed main) mode: VDD = 2.7 V to 5.5 V @1 MHz to 24 MHz VDD = 2.4 V to 5.5 V @1 MHz to 16 MHz LS(Low speed main) mode: Remarks 1. VDD = 1.8 V to 5.5 V @1 MHz to 8 MHz fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) 2. fIH: high-speed on-chip oscillator clock frequency 3. Temperature condition of the TYP. value is TA = 25C. R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 23 of 106 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C) RL78/G12 (1) 20-, 24-pin products (TA = 40 to +85C, 1.8 V VDD 5.5 V, VSS = 0 V) Parameter Supply current Symbol IDD2 (2/2) Conditions Note 2 Note 1 HALT HS (High-speed mode main) mode MIN. Note 4 fIH = 24 MHz fIH = 16 MHz LS (Low-speed Note 4 fIH = 8 MHz Note 6 Note 3 fMX = 20 MHz , VDD = 5.0 V Note 3 fMX = 20 MHz , VDD = 3.0 V Note 3 fMX = 10 MHz , VDD = 5.0 V Note 3 fMX = 10 MHz , VDD = 3.0 V LS (Low-speed main) mode Note 6 Note 3 fMX = 8 MHz , VDD = 3.0 V Note 3 fMX = 8 MHz , VDD = 2.0 V IDD3 Notes 1. Note 5 Unit VDD = 5.0 V 440 1210 A VDD = 3.0 V 440 1210 VDD = 5.0 V 400 950 VDD = 3.0 V 400 950 VDD = 3.0 V 270 542 VDD = 2.0 V 270 542 Square wave input 280 1000 Resonator connection 450 1170 Square wave input 280 1000 Resonator connection 450 1170 Square wave input 190 590 Resonator connection 260 660 Square wave input 190 590 Resonator connection 260 660 Square wave input 110 360 Resonator connection 150 416 Square wave input 110 360 Resonator connection 150 416 A A Note 6 HS (High-speed main) mode MAX. Note 6 Note 4 main) mode TYP. STOP TA = 40C 0.19 0.50 mode TA = +25C 0.24 0.50 TA = +50C 0.32 0.80 TA = +70C 0.48 1.20 TA = +85C 0.74 2.20 A A A A A A A Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is fixed to VDD or VSS. The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. 2. During HALT instruction execution by flash memory. 3. When high-speed on-chip oscillator clock is stopped. 4. When high-speed system clock is stopped. 5. Not including the current flowing into the 12-bit interval timer and watchdog timer. 6. Relationship between operation voltage width, operation frequency of CPU and operation mode is as follows. HS(High speed main) mode: VDD = 2.7 V to 5.5 V @1 MHz to 24 MHz VDD = 2.4 V to 5.5 V @1 MHz to 16 MHz LS(Low speed main) mode: Remarks 1. VDD = 1.8 V to 5.5 V @1 MHz to 8 MHz fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) 2. fIH: high-speed on-chip oscillator clock frequency 3. Except temperature condition of the TYP. value is TA = 25C, other than STOP mode R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 24 of 106 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C) RL78/G12 (2) 30-pin products (TA = 40 to +85C, 1.8 V VDD 5.5 V, VSS = 0 V) Parameter Supply current Symbol (1/2) Conditions Operating HS (High-speed IDD1 Note 1 mode main) mode Note 3 MIN. Basic fIH = 24 MHz Note 4 VDD = 5.0 V 1.5 operation VDD = 3.0 V 1.5 Normal 3.7 5.5 3.7 5.5 VDD = 5.0 V 2.7 4.0 VDD = 3.0 V 2.7 4.0 VDD = 3.0 V 1.2 1.8 VDD = 2.0 V 1.2 1.8 Square wave input 3.0 4.6 Resonator connection 3.2 4.8 Square wave input 3.0 4.6 Resonator connection 3.2 4.8 Square wave input 1.9 2.7 Resonator connection 1.9 2.7 Square wave input 1.9 2.7 Resonator connection 1.9 2.7 Square wave input 1.1 1.7 Resonator connection 1.1 1.7 Square wave input 1.1 1.7 Resonator connection 1.1 1.7 fIH = 8 MHz Note 4 Note 2 fMX = 20 MHz , VDD = 5.0 V Note 2 fMX = 20 MHz , VDD = 3.0 V Note 2 fMX = 10 MHz , VDD = 5.0 V Note 2 fMX = 10 MHz , VDD = 3.0 V LS (Low-speed main) mode Note 4 Note 2 fMX = 8 MHz , VDD = 3.0 V Note 2 fMX = 8 MHz , VDD = 2.0 V Notes 1. mA mA mA Note 4 HS (High-speed main) mode Note 3 Unit mA VDD = 5.0 V Note 3 main) mode MAX. operation VDD = 3.0 V fIH = 16 MHz LS (Low-speed TYP. mA mA mA mA mA mA Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is fixed to VDD or VSS. The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. 2. When high-speed on-chip oscillator clock is stopped. 3. When high-speed system clock is stopped 4. Relationship between operation voltage width, operation frequency of CPU and operation mode is as follows. HS(High speed main) mode: VDD = 2.7 V to 5.5 V @1 MHz to 24 MHz VDD = 2.4 V to 5.5 V @1 MHz to 16 MHz LS(Low speed main) mode: Remarks 1. VDD = 1.8 V to 5.5 V @1 MHz to 8 MHz fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) 2. fIH: high-speed on-chip oscillator clock frequency 3. Temperature condition of the TYP. value is TA = 25C. R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 25 of 106 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C) RL78/G12 (2) 30-pin products (TA = 40 to +85C, 1.8 V VDD 5.5 V, VSS = 0 V) Parameter Supply current Symbol IDD2 (2/2) Conditions Note 2 Note 1 HALT HS (High-speed mode main) mode MIN. Note 4 fIH = 24 MHz fIH = 16 MHz LS (Low-speed Note 4 fIH = 8 MHz Note 6 Note 3 fMX = 20 MHz , VDD = 5.0 V Note 3 fMX = 20 MHz , VDD = 3.0 V Note 3 fMX = 10 MHz , VDD = 5.0 V Note 3 fMX = 10 MHz , VDD = 3.0 V LS (Low-speed main) mode Note 6 Note 3 fMX = 8 MHz , VDD = 3.0 V Note 3 fMX = 8 MHz VDD = 2.0 V Note 5 IDD3 Notes 1. Unit VDD = 5.0 V 440 1280 A VDD = 3.0 V 440 1280 VDD = 5.0 V 400 1000 VDD = 3.0 V 400 1000 VDD = 3.0 V 260 530 VDD = 2.0 V 260 530 Square wave input 280 1000 Resonator connection 450 1170 Square wave input 280 1000 Resonator connection 450 1170 Square wave input 190 600 Resonator connection 260 670 Square wave input 190 600 Resonator connection 260 670 Square wave input 95 330 Resonator connection 145 380 Square wave input 95 330 Resonator connection 145 380 A A Note 6 HS (High-speed main) mode MAX. Note 6 Note 4 main) mode TYP. STOP TA = 40C 0.18 0.50 mode TA = +25C 0.23 0.50 TA = +50C 0.30 1.10 TA = +70C 0.46 1.90 TA = +85C 0.75 3.30 A A A A A A A Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is fixed to VDD or VSS. The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. 2. During HALT instruction execution by flash memory. 3. When high-speed on-chip oscillator clock is stopped. 4. When high-speed system clock is stopped. 5. Not including the current flowing into the 12-bit interval timer and watchdog timer. 6. Relationship between operation voltage width, operation frequency of CPU and operation mode is as follows. HS (High speed main) mode: VDD = 2.7 V to 5.5 V @1 MHz to 24 MHz VDD = 2.4 V to 5.5 V @1 MHz to 16 MHz LS (Low speed main) mode: VDD = 1.8 V to 5.5 V @1 MHz to 8 MHz Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) 2. fIH: high-speed on-chip oscillator clock frequency 3. Except STOP mode, temperature condition of the TYP. value is TA = 25C. R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 26 of 106 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C) RL78/G12 (3) Peripheral functions (Common to all products) (TA = 40 to +85C, 1.8 V VDD 5.5 V, VSS = 0 V) Parameter Low-speed Symbol IFIL Conditions MIN. Note 1 TYP. MAX. Unit 0.20 A 0.02 A 0.22 A onchip oscillator operating current 12-bit interval ITMKA timer operating Notes 1, 2, 3 current Watchdog timer IWDT operating current Notes 1, 2, 4 A/D converter operating current IADC fIL = 15 kHz Notes 1, 5 When conversion at maximum speed Normal mode, AVREFP = VDD = 5.0 V 1.30 1.70 mA Low voltage mode, AVREFP = VDD = 3.0 V 0.50 0.70 mA 75.0 A Note 1 75.0 A A A/D converter IADREF reference voltage operating current Note 1 Temperature sensor operating current ITMPS LVD operating ILVD Notes 1, 6 0.08 IFSP Notes 1, 8 2.00 12.20 mA 2.00 12.20 mA 0.50 0.60 mA 1.20 1.44 mA 0.70 0.84 mA current Selfprogramming operating current BGO operating IBGO Notes 1, 7 current SNOOZE ISNOZ Note 1 ADC operation operating current The mode is performed Note 9 The A/D conversion operations are performed, Low voltage mode, AVREFP = VDD = 3.0 V CSI/UART operation Notes 1. Current flowing to the VDD. 2. When high speed on-chip oscillator and high-speed system clock are stopped. 3. Current flowing only to the 12-bit interval timer (excluding the operating current of the low-speed on-chip oscillator). The current value of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3, and IFIL and ITMKA when the 12-bit interval timer operates. 4. Current flowing only to the watchdog timer (including the operating current of the low-speed on-chip oscillator). The current value of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and IWDT when the watchdog timer operates. 5. Current flowing only to the A/D converter. The current value of the RL78 microcontrollers is the sum of IDD1 or IDD2 and IADC when the A/D converter operates in an operation mode or the HALT mode. 6. Current flowing only to the LVD circuit. The current value of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and ILVD when the LVD circuit operates. 7. Current flowing only during data flash rewrite. 8. Current flowing only during self programming. 9. For shift time to the SNOOZE mode, see 17.3.3 SNOOZE mode. Remarks 1. fIL: Low-speed on-chip oscillator clock frequency 2. Temperature condition of the TYP. value is TA = 25C R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 27 of 106 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C) RL78/G12 2.4 AC Characteristics (TA = 40 to +85C, 1.8 V VDD 5.5 V, VSS = 0 V) Items Instruction cycle (minimum Symbol TCY instruction execution time) Conditions MIN. TYP. MAX. Unit Main system HS (High- 2.7 V VDD 5.5 V 0.04167 1 s clock (fMAIN) speed main) 2.4 V VDD 2.7 V 0.0625 1 s operation mode 1.8 V VDD 5.5 V 0.125 1 s LS (Lowspeed main) mode During self HS (High- 2.7 V VDD 5.5 V 0.04167 1 s programming speed main) 2.4 V VDD 2.7 V 0.0625 1 s 1.8 V VDD 5.5 V 0.125 1 s 2.7 V VDD 5.5 V 1.0 20.0 MHz 2.4 V VDD 2.7 V 1.0 16.0 MHz 1.8 V VDD 2.4 V 1.0 8.0 MHz 2.7 V VDD 5.5 V 24 ns 2.4 V VDD 2.7 V 30 ns 1.8 V VDD 2.4 V 60 ns 1/fMCK + ns mode LS (Lowspeed main) mode External main system clock fEX frequency External main system clock tEXH, tEXL input high-level width, lowlevel width TI00 to TI07 input high-level tTIH, tTIL width, low-level width TO00 to TO07 output 10 fTO frequency PCLBUZ0, or PCLBUZ1 fPCL output frequency INTP0 to INTP5 input high- 4.0 V VDD 5.5 V 12 MHz 2.7 V VDD 4.0 V 8 MHz 1.8 V VDD 2.7 V 4 MHz 4.0 V VDD 5.5 V 16 MHz 2.7 V VDD 4.0 V 8 MHz 1.8 V VDD 2.7 V 4 MHz 1 s tKR 250 ns tRSL 10 s tINTH, tINTL level width, low-level width KR0 to KR9 input available width RESET low-level width Remark fMCK: Timer array unit operation clock frequency (Operation clock to be set by the timer clock select register 0 (TPS0) and the CKS0n bit of timer mode register 0n (TMR0n). n: Channel number (n = 0 to 7)) R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 28 of 106 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C) RL78/G12 Minimum Instruction Execution Time during Main System Clock Operation TCY vs VDD (HS (high-speed main) mode) Cycle time TCY [s] 10 1.0 When the high-speed on-chip oscillator clock is selected During self programming When high-speed system clock is selected 0.1 0.0625 0.04167 0.01 0 1.0 2.0 3.0 2.4 2.7 4.0 5.0 5.5 6.0 Supply voltage V DD [V] TCY vs VDD (LS (low-speed main) mode) Cycle time TCY [s] 10 1.0 When the high-speed on-chip oscillator clock is selected During self programming When high-speed system clock is selected 0.125 0.1 0.01 0 1.0 2.0 1.8 3.0 4.0 5.0 5.5 6.0 Supply voltage V DD [V] R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 29 of 106 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C) RL78/G12 AC Timing Test Point VIH/VOH VIH/VOH Test points VIL/VOL VIL/VOL External Main System Clock Timing 1/fEX tEXL tEXH EXCLK TI/TO Timing tTIH tTIL TI00 to TI07 1/fTO TO00 to TO07 Interrupt Request Input Timing tINTL tINTH INTP0 to INTP5 Key Interrupt Input Timing tKR KR0 to KR9 RESET Input Timing tRSL RESET R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 30 of 106 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C) RL78/G12 2.5 Peripheral Functions Characteristics AC Timing Test Point VIH/VOH VIH/VOH Test points VIL/VOL VIL/VOL 2.5.1 Serial array unit (1) During communication at same potential (UART mode) (TA = 40 to +85C, 1.8 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode LS (low-speed main) Mode MIN. MIN. Transfer rate Note 1 Theoretical value of the maximum transfer rate fCLK = fMCK Notes 1. 2. MAX. Unit MAX. fMCK/6 fMCK/6 bps 4.0 1.3 Mbps Note2 Transfer rate in the SNOOZE mode is 4800 bps only. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are: HS (high-speed main) mode: 24 MHz (2.7 V VDD 5.5 V) 16 MHz (2.4 V VDD 5.5 V) LS (low-speed main) mode: 8 MHz (1.8 V VDD 5.5 V) Caution Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). UART mode connection diagram (during communication at same potential) Rx TxDq RL78 microcontroller User's device RxDq Tx UART mode bit width (during communication at same potential) (reference) 1/Transfer rate High-/Low-bit width Baud rate error tolerance TxDq RxDq Remarks 1. 2. q: UART number (q = 0 to 2), g: PIM, POM number (g = 0, 1) fMCK: Serial array unit operation clock frequency (Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10, 11)) R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 31 of 106 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C) RL78/G12 (2) During communication at same potential (CSI mode) (master mode, SCK00... internal clock output, corresponding CSI00 only) (TA = 40 to +85C, 2.7 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) LS (low-speed main) Mode Mode MIN. tKCY1 tKCY1 2/fCLK SCK00 high-/low- tKH1, level width tKL1 SCK00 cycle time SI00 setup time (to SCK00) tSIK1 Note 1 SI00 hold time MIN. MAX. 83.3 250 ns 4.0 V VDD 5.5 V tKCY1/27 tKCY1/250 ns 2.7 V VDD 5.5 V tKCY1/210 tKCY1/250 ns 4.0 V VDD 5.5 V 23 110 ns 2.7 V VDD 5.5 V 33 110 ns 10 10 ns tKSI1 (from SCK00) MAX. Unit Note2 Delay time from tKSO1 C = 20 pF Note 4 10 10 ns SCK00 to SO00 output Note 3 Notes 1. When DAP00 = 0 and CKP00 = 0, or DAP00 = 1 and CKP00 = 1. The SI00 setup time becomes "to SCK00" when DAP00 = 0 and CKP00 = 1, or DAP00 = 1 and CKP00 = 0. 2. When DAP00 = 0 and CKP00 = 0, or DAP00 = 1 and CKP00 = 1. The SI00 hold time becomes "from SCK00" when DAP00 = 0 and CKP00 = 1, or DAP00 = 1 and CKP00 = 0. 3. When DAP00 = 0 and CKP00 = 0, or DAP00 = 1 and CKP00 = 1. The delay time to SO00 output becomes "from SCK00" when DAP00 = 0 and CKP00 = 1, or DAP00 = 1 and CKP00 = 0. 4. C is the load capacitance of the SCK00 and SO00 output lines. Caution Select the normal input buffer for the SI00 pin and the normal output mode for the SO00 and SCK00 pins by using port input mode register 1 (PIM1) and port output mode register 1 (POM1). Remarks 1. This specification is valid only when CSI00's peripheral I/O redirect function is not used. 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the serial clock select register 0 (SPS0) and the CKS00 bit of serial mode register 00 (SMR00).) R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 32 of 106 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C) RL78/G12 (3) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output) (TA = 40 to +85C, 1.8 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed LS (low-speed main) main) Mode Mode MIN. SCKp cycle time tKCY1 SCKp high-/low-level width SIp setup time (to SCKp) tKCY1 4/fCLK 167 500 ns 2.4 V VDD 5.5 V 250 500 ns 1.8 V VDD 5.5 V 500 ns 4.0 V VDD 5.5 V tKCY1/212 tKCY1/250 ns tKL1 2.7 V VDD 5.5 V tKCY1/218 tKCY1/250 ns 2.4 V VDD 5.5 V tKCY1/238 tKCY1/250 ns 1.8 V VDD 5.5 V tKCY1/250 ns 4.0 V VDD 5.5 V 44 110 ns 2.7 V VDD 5.5 V 44 110 ns 2.4 V VDD 5.5 V 75 110 ns 110 ns 19 19 ns tSIK1 tKSI1 Note 2 Delay time from SCKp to SOp output MAX. 2.7 V VDD 5.5 V 1.8 V VDD 5.5 V (from SCKp) MIN. tKH1, Note 1 SIp hold time MAX. Unit tKSO1 C = 30 pF Note4 25 25 ns Note 3 Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes "to SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 4. C is the load capacitance of the SCKp and SOp output lines. Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp and SCKp pins by using port input mode register 1 (PIM1) and port output mode registers 0, 1, 4 (POM0, POM1, POM4). Remarks 1. p: CSI number (p = 00, 01, 11, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0, 1, 3: "1, 3" is only for the R5F102 products) 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0, 1), n: Channel number (n = 0, 1, 3: "1, 3" is only for the R5F102 products.)) R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 33 of 106 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C) RL78/G12 (4) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input) (TA = 40 to +85C, 1.8 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed LS (low-speed main) main) Mode Mode MIN. SCKp cycle time Note4 tKCY2 4.0 V VDD 5.5 V MAX. MIN. Unit MAX. 20 MHz fMCK 8/fMCK ns fMCK 20 MHz 6/fMCK 6/fMCK ns 16 MHz fMCK 8/fMCK ns fMCK 16 MHz 6/fMCK 6/fMCK ns 6/fMCK 6/fMCK ns and 500 and 500 1.8 V VDD 5.5 V 6/fMCK 2.7 V VDD 5.5 V 2.4 V VDD 5.5 V ns and 750 SCKp high-/low-level tKH2, 4.0 V VDD 5.5 V tKCY2/27 tKCY2/27 ns width tKL2 2.7 V VDD 5.5 V tKCY2/28 tKCY2/28 ns 2.4 V VDD 5.5 V tKCY2/218 tKCY2/218 ns 1.8 V VDD 5.5 V tKCY2/218 ns 2.7 V VDD 5.5 V 1/fMCK + 1/fMCK + ns 20 30 1/fMCK + 1/fMCK + 30 30 1/fMCK + SIp setup time (to SCKp) tSIK2 Note 1 2.4 V VDD 5.5 V 1.8 V VDD 5.5 V ns ns 30 SIp hold time (from SCKp) tKSI2 Note 2 Delay time from tKSO2 C = 30 pF Note4 2.7 V VDD 5.5 V SCKp to SOp output Note 3 2.4 V VDD 5.5 V 1.8 V VDD 5.5 V 1/fMCK + 1/fMCK + 31 31 ns 2/fMCK + 2/fMCK + 44 110 2/fMCK + 2/fMCK + 75 110 2/fMCK + ns ns ns 110 Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes "to SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 4. C is the load capacitance of the SOp output lines. 5. Transfer rate in the SNOOZE mode: MAX. 1 Mbps Caution Select the normal input buffer for the SIp and SCKp pins and the normal output mode for the SOp pin by using port input mode register 1 (PIM1) and port output mode registers 0, 1, 4 (POM0, POM1, POM4). R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 34 of 106 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C) RL78/G12 CSI mode connection diagram (during communication at same potential) SCK SCKp RL78 microcontroller SIp SO User's device SOp SI CSI mode serial transfer timing (during communication at same potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) tKCY1, 2 tKL1, 2 tKH1, 2 SCKp tSIK1, 2 SIp tKSI1, 2 Input data tKSO1, 2 SOp Output data CSI mode serial transfer timing (during communication at same potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) tKCY1, 2 tKH1, 2 tKL1, 2 SCKp tSIK1, 2 SIp tKSI1, 2 Input data tKSO1, 2 SOp Output data (Remarks are listed on the next page.) R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 35 of 106 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C) RL78/G12 Remarks 1. p: CSI number (p = 00, 01, 11, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0, 1, 3: "1, 3" is only for the R5F102 products.) 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0, 1), n: Channel number (n = 0, 1, 3: "1, 3" is only for the R5F102 products.)) 2 (5) During communication at same potential (simplified I C mode) (TA = 40 to +85C, 1.8 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode Unit LS (low-speed main) Mode MIN. SCLr clock frequency fSCL MAX. 1.8 V VDD 5.5 V, 400 Note 1 kHz 300 Note 1 kHz Cb = 100 pF, Rb = 3 k 1.8 V VDD < 2.7 V, Cb = 100 pF, Rb = 5 k Hold time when SCLr = "L" tLOW 1.8 V VDD 5.5 V, 1150 ns 1550 ns 1150 ns 1550 ns Cb = 100 pF, Rb = 3 k 1.8 V VDD < 2.7 V, Cb = 100 pF, Rb = 5 k Hold time when SCLr = "H" tHIGH 1.8 V VDD 5.5 V, Cb = 100 pF, Rb = 3 k 1.8 V VDD < 2.7 V, Cb = 100 pF, Rb = 5 k Data setup time (reception) tSU:DAT 1.8 V VDD 5.5 V, 1/fMCK + 145 Note 2 ns 1/fMCK + 230 Note 2 ns Cb = 100 pF, Rb = 3 k 1.8 V VDD < 2.7 V, Cb = 100 pF, Rb = 5 k Data hold time (transmission) tHD:DAT 1.8 V VDD 5.5 V, 0 355 ns 0 405 ns Cb = 100 pF, Rb = 3 k 1.8 V VDD < 2.7 V, Cb = 100 pF, Rb = 5 k Notes 1. 2. The value must also be equal to or less than fMCK/4. Set tSU:DAT so that it will not exceed the hold time when SCLr = "L" or SCLr = "H". Caution Select the N-ch open drain output (VDD tolerance) mode for SDAr by using port output mode register h (POMh). (Remarks are listed on the next page.) R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 36 of 106 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C) RL78/G12 2 Simplified I C mode connection diagram (during communication at same potential) VDD Rb SDA SDAr RL78 microcontroller User's device SCLr SCL 2 Simplified I C mode serial transfer timing (during communication at same potential) 1/fSCL tLOW tHIGH SCLr SDAr tHD:DAT Remarks 1. tSU:DAT Rb []:Communication line (SDAr) pull-up resistance Cb [F]: Communication line (SCLr, SDAr) load capacitance 2. 3. r: IIC number (r = 00, 01, 11, 20), h: = POM number (h = 0, 1, 4, 5) fMCK: Serial array unit operation clock frequency (Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0, 1), n: Channel number (0, 1, 3)) 4. 2 Simplified I C mode is supported only by the R5F102 products. R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 37 of 106 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C) RL78/G12 (6) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode) (TA = 40 to +85C, 1.8 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode MIN. Transfer Note4 rate Reception LS (low-speed main) Mode MAX. 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V Theoretical value of the maximum transfer rate Note3 fMCK = fCLK 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V Theoretical value of the maximum transfer rate MIN. Unit MAX. fMCK/6 fMCK/6 Note1 Note1 4.0 1.3 Mbps fMCK/6 fMCK/6 bps Note1 Note1 4.0 1.3 Mbps bps bps Note3 fMCK = fCLK 1.8 V VDD < 3.3 V, fMCK/6 fMCK/6 1.6 V Vb 2.0 V Notes1, 2 Notes1, 2 4.0 1.3 Mbps Note4 Note4 bps Mbps Theoretical value of the maximum transfer rate Note3 fMCK = fCLK Transmission 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V Theoretical value of the maximum transfer rate Cb = 50 pF, Rb = 1.4 k, Vb = 2.7 V 2.7 V VDD < 4.0 V, 2.8 2.8 Note5 Note5 Note6 Note6 bps Mbps 2.3 V Vb 2.7 V, 1.2 1.2 Note7 Note7 Notes 2, 8 Notes 2, 8 bps 0.43 0.43 Mbps Note9 Note9 Theoretical value of the maximum transfer rate Cb = 50 pF, Rb = 2.7 k, Vb = 2.3 V 1.8 V VDD < 3.3 V, 1.6 V Vb 2.0 V Theoretical value of the maximum transfer rate Cb = 50 pF, Rb = 5.5 k, Vb = 1.6 V Notes 1. Transfer rate in the SNOOZE mode is 4800 bps only. 2. Use it with VDD Vb. 3. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are: HS (high-speed main) mode: 24 MHz (2.7 V VDD 5.5 V) 16 MHz (2.4 V VDD 5.5 V) LS (low-speed main) mode: 4. 8 MHz (1.8 V VDD 5.5 V) The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 4.0 V VDD 5.5 V and 2.7 V Vb 4.0 V 1 Maximum transfer rate = {Cb x Rb x ln (1 2.2 )} x 3 Vb [bps] 2.2 1 {Cb x Rb x ln (1 )} Vb Transfer rate 2 Baud rate error (theoretical value) = ( 1 ) x Number of transferred bits Transfer rate x 100 [%] * This value is the theoretical value of the relative difference between the transmission and reception sides. R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 38 of 106 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C) RL78/G12 5. This value as an example is calculated when the conditions described in the "Conditions" column are met. Refer to Note 4 above to calculate the maximum transfer rate under conditions of the customer. 6. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 2.7 V VDD < 4.0 V and 2.3 V Vb 2.7 V 1 Maximum transfer rate = {Cb x Rb x ln (1 2.0 )} x 3 Vb [bps] 2.0 1 {Cb x Rb x ln (1 )} Vb Transfer rate 2 Baud rate error (theoretical value) = ( 1 ) x Number of transferred bits Transfer rate x 100 [%] * This value is the theoretical value of the relative difference between the transmission and reception sides. 7. This value as an example is calculated when the conditions described in the "Conditions" column are met. Refer to Note 6 above to calculate the maximum transfer rate under conditions of the customer. 8. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 1.8 V VDD < 3.3 V, 1.6 V Vb 2.0 V 1 Maximum transfer rate = {Cb x Rb x ln (1 1.5 )} x 3 Vb [bps] 1.5 1 {Cb x Rb x ln (1 )} Vb Transfer rate 2 Baud rate error (theoretical value) = ( 1 ) x Number of transferred bits Transfer rate x 100 [%] * This value is the theoretical value of the relative difference between the transmission and reception sides. 9. This value as an example is calculated when the conditions described in the "Conditions" column are met. Refer to Note 8 above to calculate the maximum transfer rate under conditions of the customer. Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance) mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 39 of 106 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C) RL78/G12 UART mode connection diagram (during communication at different potential) Vb Rb Rx TxDq RL78 microcontroller User's device RxDq Tx UART mode bit width (during communication at different potential) (reference) 1/Transfer rate Low-bit width High-bit width Baud rate error tolerance TxDq 1/Transfer rate High-/Low-bit width Baud rate error tolerance RxDq Remarks 1. Rb[]: Communication line (TxDq) pull-up resistance, Cb[F]: Communication line (TxDq) load capacitance, Vb[V]: Communication line voltage 2. q: UART number (q = 0 to 2), g: PIM and POM number (g = 0, 1) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10, 11)) 4. UART0 of the 20- and 24-pin products supports communication at different potential only when the peripheral I/O redirection function is not used. R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 40 of 106 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C) RL78/G12 (7) Communication at different potential (2.5 V, 3 V) (CSI mode) (master mode, SCK00... internal clock output, corresponding CSI00 only) (TA = 40 to +85C, 2.7 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed LS (low-speed main) Mode main) Mode MIN. SCK00 cycle time tKCY1 tKCY1 2/fCLK 4.0 V VDD 5.5 V, MAX. MIN. Unit MAX. 200 1150 ns 300 1150 ns tKCY1/2 tKCY1/2 ns 50 50 tKCY1/2 tKCY1/2 120 120 tKCY1/2 tKCY1/2 7 50 2.7 V Vb 4.0 V, Cb = 20 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k SCK00 high-level width tKH1 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 20 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k SCK00 low-level width tKL1 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 20 pF, Rb = 1.4 k (to SCK00) tSIK1 ns tKCY1/2 tKCY1/2 Cb = 20 pF, Rb = 2.7 k 10 50 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, 58 479 ns 121 479 ns 10 10 ns 10 10 ns 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, SI00 setup time ns ns Note 1 Cb = 20 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k SI00 hold time (from SCK00) tKSI1 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, Note 1 Cb = 20 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k Delay time from SCK00 to SO00 output tKSO1 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, 60 60 ns 130 130 ns Note 1 Cb = 20 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k SI00 setup time (to SCK00) tSIK1 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, 23 110 ns 33 110 ns 10 10 ns 10 10 ns Note 2 Cb = 20 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k SI00 hold time (from SCK00) tKSI1 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, Note 2 Cb = 20 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k Delay time from SCK00 to SO00 output tKSO1 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, 10 10 ns 10 10 ns Note 2 Cb = 20 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k (Notes, Caution, and Remarks are listed on the next page.) R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 41 of 106 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C) RL78/G12 Notes 1. When DAP00 = 0 and CKP00 = 0, or DAP00 = 1 and CKP00 = 1 2. When DAP00 = 0 and CKP00 = 1, or DAP00 = 1 and CKP00 = 0. Caution Select the TTL input buffer for the SI00 pin and the N-ch open drain output (VDD tolerance) mode for the SO00 pin and SCK00 pin by using port input mode register 1 (PIM1) and port output mode register 1 (POM1). For VIH and VIL, see the DC characteristics with TTL input buffer selected. Remarks 1. Rb []:Communication line (SCK00, SO00) pull-up resistance, Cb [F]: Communication line (SCK00, SO00) load capacitance, Vb [V]: Communication line voltage 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the serial clock select register 0 (SPS0) and the CKS00 bit of serial mode register 00 (SMR00).) R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 42 of 106 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C) RL78/G12 (8) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output) (1/3) (TA = 40 to +85C, 1.8 V VDD VDD 5.5 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) LS (low-speed main) Mode Mode MIN. SCKp cycle time tKCY1 tKCY1 4/fCLK 4.0 V VDD 5.5 V, MAX. MIN. Unit MAX. 300 1150 ns 500 1150 ns 1150 1150 ns tKCY1/2 75 tKCY1/275 ns tKCY1/2 170 tKCY1/2170 ns tKCY1/2 458 tKCY1/2458 ns tKCY1/2 12 tKCY1/250 ns tKCY1/2 18 tKCY1/250 ns tKCY1/2 50 tKCY1/250 ns 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 1.8 V VDD < 3.3 V, 1.6 V Vb 2.0 V Note , Cb = 30 pF, Rb = 5.5 k SCKp high-level width tKH1 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 1.8 V VDD < 3.3 V, 1.6 V Vb 2.0 V Note , Cb = 30 pF, Rb = 5.5 k SCKp low-level width tKL1 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 1.8 V VDD < 3.3 V, 1.6 V Vb 2.0 V Note , Cb = 30 pF, Rb = 5.5 k Note Use it with VDD Vb. Cautions 1. Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode for the SOp pin and SCKp pin by using port input mode register 1 (PIM1) and port output mode register 1 (POM1). For VIH and VIL, see the DC characteristics with TTL input buffer selected. 2. CSI01 and CSI11 cannot communicate at different potential. Remarks 1. Rb []: Communication line (SCKp, SOp) pull-up resistance, Cb [F]: Communication line (SCKp, SOp) load capacitance, Vb [V]: Communication line voltage 2. p: CSI number (p = 00, 20) R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 43 of 106 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C) RL78/G12 (8) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output) (2/3) (TA = 40 to +85C, 1.8 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed LS (low-speed main) Mode main) Mode MIN. SIp setup time (to SCKp) tSIK1 Note 1 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, MAX. MIN. Unit MAX. 81 479 ns 177 479 ns 479 479 ns 19 19 ns 19 19 ns 19 19 ns Cb = 30 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 1.8 V VDD < 3.3 V, 1.6 V Vb 2.0 V Note 2 , Cb = 30 pF, Rb = 5.5 k SIp hold time (from SCKp) tKSI1 Note 1 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 1.8 V VDD < 3.3 V, 1.6 V Vb 2.0 V Note 2 , Cb = 30 pF, Rb = 5.5 k Delay time from tKSO1 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, 100 100 ns 195 195 ns 483 483 ns Cb = 30 pF, Rb = 1.4 k SCKp to SOp output Note 1 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 1.8 V VDD < 3.3 V, 1.6 V Vb 2.0 V Note 2 , Cb = 30 pF, Rb = 5.5 k Notes 1. 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. Use it with VDD Vb. (Cautions and Remarks are listed on the next page.) R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 44 of 106 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C) RL78/G12 (8) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output) (3/3) (TA = 40 to +85C, 1.8 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed LS (low-speed main) Mode main) Mode MIN. SIp setup time (to SCKp) 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, tSIK1 Note 1 MAX. MIN. Unit MAX. 44 110 ns 44 110 ns 110 110 ns 19 19 ns 19 19 ns 19 19 ns Cb = 30 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 1.8 V VDD < 3.3 V, 1.6 V Vb 2.0 V Note 2 , Cb = 30 pF, Rb = 5.5 k SIp hold time (from SCKp) 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, tKSI1 Note 1 Cb = 30 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 1.8 V VDD < 3.3 V, 1.6 V Vb 2.0 V Note 2 , Cb = 30 pF, Rb = 5.5 k Delay time from 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, tKSO1 25 25 ns 25 25 ns 25 25 ns Cb = 30 pF, Rb = 1.4 k SCKp to SOp output Note 1 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 1.8 V VDD < 3.3 V, 1.6 V Vb 2.0 V Note 2 , Cb = 30 pF, Rb = 5.5 k Notes 1. 2. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Use it with VDD Vb. Cautions 1. Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode for the SOp pin and SCKp pin by using port input mode register 1 (PIM1) and port output mode register 1 (POM1). For VIH and VIL, see the DC characteristics with TTL input buffer selected. 2. Remarks 1. CSI01 and CSI11 cannot communicate at different potential. Rb []: Communication line (SCKp, SOp) pull-up resistance, Cb [F]: Communication line (SCKp, SOp) load capacitance, Vb [V]: Communication line voltage 2. p: CSI number (p = 00, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0) CSI mode connection diagram (during communication at different potential) Vb <Master> Rb SCKp RL78 microcontroller R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Vb Rb SCK SIp SO SOp SI User's device Page 45 of 106 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C) RL78/G12 CSI mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1) t KCY1 t KL1 t KH1 SCKp t SIK1 SIp t KSI1 Input data t KSO1 SOp Output data CSI mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) tKCY1 tKL1 tKH1 SCKp tSIK1 SIp tKSI1 Input data tKSO1 SOp R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Output data Page 46 of 106 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C) RL78/G12 (9) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (slave mode, SCKp... external clock input) (TA = 40 to +85C, 1.8 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) LS (low-speed main) Mode Mode MIN. SCKp cycle time Note 1 tKCY2 MAX. MIN. Unit MAX. 4.0 V VDD 5.5 V, 20 MHz < fMCK 24 MHz 12/fMCK ns 2.7 V Vb 4.0 V 8 MHz < fMCK 20 MHz 10/fMCK ns 4 MHz < fMCK 8 MHz 8/fMCK 16/fMCK ns fMCK 4 MHz 6/fMCK 10/fMCK ns 2.7 V VDD < 4.0 V, 20 MHz < fMCK 24 MHz 16/fMCK ns 2.3 V Vb 2.7 V 16 MHz < fMCK 20 MHz 14/fMCK ns 8 MHz < fMCK 16 MHz 12/fMCK ns 4 MHz < fMCK 8 MHz 8/fMCK 16/fMCK ns fMCK 4 MHz 6/fMCK 10/fMCK ns 1.8 V VDD < 3.3 V, 20 MHz < fMCK 24 MHz 36/fMCK ns 1.6 V Vb 2.0 V 16 MHz < fMCK 20 MHz 32/fMCK ns 8 MHz < fMCK 16 MHz 26/fMCK ns 4 MHz < fMCK 8 MHz 16/fMCK 16/fMCK ns fMCK 4 MHz 10/fMCK 10/fMCK ns Note 2 SCKp high-/low-level tKH2, 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V tKCY2/2 12 tKCY2/2 50 ns width tKL2 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V tKCY2/2 18 tKCY2/2 50 ns tKCY2/2 50 tKCY2/2 50 ns 1/fMCK + 20 1/fMCK + 30 ns 1/fMCK + 20 1/fMCK + 30 ns 1/fMCK + 30 1/fMCK + 30 ns 1/fMCK + 31 1/fMCK + 31 ns 1.8 V VDD < 3.3 V, 1.6 V Vb 2.0 V SIp setup time (to SCKp) tSIK2 Note 3 Note 2 4.0 V VDD 5.5 V, 2.7 V VDD 4.0 V 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V 1.8 V VDD < 3.3 V, 1.6 V VDD 2.0 V SIp hold time (from SCKp) tKSI2 Note 4 Delay time from tKSO2 SCKp to SOp output Note 2 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k 2/fMCK + 2/fMCK + 120 573 2/fMCK + 2/fMCK + 214 573 2/fMCK + 2/fMCK + 573 573 ns Note 5 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 1.8 V VDD < 3.3 V, 1.6 V Vb 2.0 V Note 2 , Cb = 30 pF, Rb = 5.5 k Notes 1. 2. 3. ns ns Transfer rate in the SNOOZE mode: MAX. 1 Mbps Use it with VDD Vb. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes "to SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 5. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Cautions 1. Select the TTL input buffer for the SIp and SCKp pins and the N-ch open drain output (VDD tolerance) mode for the SOp pin by using port input mode register 1 (PIM1) and port output mode register 1 (POM1). For VIH and VIL, see the DC characteristics with TTL input buffer selected. 2. CSI01 and CSI11 cannot communicate at different potential. R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 47 of 106 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C) RL78/G12 CSI mode connection diagram (during communication at different potential) Vb <Slave> Rb SCKp RL78 microcontroller SCK SIp SO SOp SI User's device Remarks 1. Rb []: Communication line (SOp) pull-up resistance, Cb [F]: Communication line (SOp) load capacitance, Vb [V]: Communication line voltage 2. p: CSI number (p = 00, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 10)) CSI mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) t KCY2 t KH2 t KL2 SCKp t SIK2 t KSI2 Input data SIp t KSO2 SOp R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Output data Page 48 of 106 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C) RL78/G12 CSI mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) t KCY2 t KL2 t KH2 SCKp t SIK2 SIp t KSI2 Input data t KSO2 SOp Remark Output data p: CSI number (p = 00, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0) R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 49 of 106 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C) RL78/G12 2 (10) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I C mode) (TA = 40 to +85C, 1.8 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed LS (low-speed main) Mode main) Mode MIN. SCLr clock frequency fSCL 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, MAX. MIN. Unit MAX. 400 Note1 300 Note1 kHz 400 Note1 300 Note1 kHz 300 Note1 300 Note1 kHz Cb = 100 pF, Rb = 2.8 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 100 pF, Rb = 2.7 k 1.8 V VDD < 3.3 V, 1.6 V Vb 2.0 V, Note2 Cb = 100 pF, Rb = 5.5 k Hold time when SCLr = "L" tLOW 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, 1150 1550 ns 1150 1550 ns 1550 1550 ns 675 610 ns 600 610 ns 610 610 ns 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, 1/fMCK 1/fMCK ns Cb = 100 pF, Rb = 2.8 k + 190 + 190 Note3 Note3 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, 1/fMCK 1/fMCK Cb = 100 pF, Rb = 2.7 k + 190 + 190 Note3 Note3 1/fMCK 1/fMCK + 190 + 190 Note3 Note3 Cb = 100 pF, Rb = 2.8 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 100 pF, Rb = 2.7 k 1.8 V VDD < 3.3 V, 1.6 V Vb 2.0 V, Note2 Cb = 100 pF, Rb = 5.5 k Hold time when SCLr = "H" tHIGH 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 100 pF, Rb = 2.8 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 100 pF, Rb = 2.7 k 1.8 V VDD < 3.3 V, 1.6 V Vb 2.0 V, Note2 Cb = 100 pF, Rb = 5.5 k Data setup time (reception) tSU:DAT 1.8 V VDD < 3.3 V, 1.6 V Vb 2.0 V, Note2 Cb = 100 pF, Rb = 5.5 k Data hold time tHD:DAT (transmission) 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, ns ns 0 355 0 355 ns 0 355 0 355 ns 0 405 0 405 ns Cb = 100 pF, Rb = 2.8 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 100 pF, Rb = 2.7 k 1.8 V VDD < 3.3 V, 1.6 V Vb 2.0 V, Note2 Cb = 100 pF, Rb = 5.5 k Notes 1. The value must also be equal to or less than fMCK/4. 2. Use it with VDD Vb. 3. Set tSU:DAT so that it will not exceed the hold time when SCLr = "L" or SCLr = "H". Cautions 1. Select the TTL input buffer and the N-ch open drain output (VDD tolerance) mode for the SDAr pin and the N-ch open drain output (VDD tolerance) mode for the SCLr pin by using port input mode register 1 (PIM1) and port output mode register 1 (POM1). For VIH and VIL, see the DC characteristics with TTL input buffer selected. 2. IIC01 and IIC11 cannot communicate at different potential. (Remarks are listed on the next page.) R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 50 of 106 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C) RL78/G12 2 Simplified I C mode connection diagram (during communication at different potential) Vb Vb Rb Rb SDA SDAr RL78 microcontroller User's device SCLr SCL 2 Simplified I C mode serial transfer timing (during communication at different potential) 1/f SCL t LOW t HIGH SCLr SDAr t HD : DAT Remarks 1. t SU : DAT Rb []: Communication line (SDAr, SCLr) pull-up resistance, Cb [F]: Communication line (SDAr, SCLr) load capacitance, Vb [V]: Communication line voltage 2. 3. r: IIC Number (r = 00, 20) fMCK: Serial array unit operation clock frequency (Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0,1), n: Channel number (n = 0)) 4. 2 Simplified I C mode is supported only by the R5F102 products. R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 51 of 106 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C) RL78/G12 2.5.2 Serial interface IICA (TA = 40 to +85C, 1.8 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) mode Unit LS (low-speed main) mode Standard Mode MIN. SCLA0 clock frequency fSCL Fast mode: fCLK 3.5 MHz Normal mode: fCLK 1 MHz Setup time of restart condition Hold time Note 1 Hold time when SCLA0 = "L" MAX. 0 Fast Mode MIN. MAX. 0 400 100 kHz kHz tSU:STA 4.7 0.6 s tHD:STA 4.0 0.6 s tLOW 4.7 1.3 s Hold time when SCLA0 = "H" tHIGH 4.0 0.6 s Data setup time (reception) tSU:DAT 250 100 ns Data hold time (transmission) tHD:DAT 0 Setup time of stop condition tSU:STO 4.0 0.6 s Bus-free time tBUF 4.7 1.3 s Note 2 Notes 1. <R> 2. 3.45 0 0.9 s The first clock pulse is generated after this period when the start/restart condition is detected. The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK (acknowledge) timing. Caution Only in the 30-pin products, the values in the above table are applied even when bit 2 (PIOR2) in the peripheral I/O redirection register (PIOR) is 1. At this time, the pin characteristics (IOH1, IOL1, VOH1, VOL1) must satisfy the values in the redirect destination. Remark The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up resistor) at that time in each mode are as follows. Cb = 400 pF, Rb = 2.7 k Cb = 320 pF, Rb = 1.1 k Normal mode: Fast mode: IICA serial transfer timing t LOW tR SCLA0 tHD:DAT tHD:STA t HIGH tF tSU:STA tHD:STA tSU:STO tSU:DAT SDAA0 t BUF Stop condition Start condition R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Restart condition Stop condition Page 52 of 106 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C) RL78/G12 2.6 Analog Characteristics 2.6.1 A/D converter characteristics Classification of A/D converter characteristics Input channel Reference Voltage Reference voltage (+) = AVREFP Reference voltage (+) = VDD Reference voltage (+) = VBGR Reference voltage () = AVREFM Reference voltage () = VSS Reference voltage () = AVREFM ANI0 to ANI3 Refer to 28.6.1 (1). Refer to 28.6.1 (3). Refer to 28.6.1 (4). ANI16 to ANI22 Refer to 28.6.1 (2). Internal reference voltage Refer to 28.6.1 (1). Temperature sensor output voltage (1) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage () = AVREFM/ANI1 (ADREFM = 1), target pin: ANI2, ANI3, internal reference voltage, and temperature sensor output voltage (TA = 40 to +85C, 1.8 V AVREFP VDD 5.5 V, VSS = 0 V, Reference voltage (+) = AVREFP, Reference voltage () = AVREFM = 0 V) Parameter Symbol Resolution Conditions RES Note 1 Overall error AINL Conversion time tCONV Notes 1, 2 Full-scale error Notes 1, 2 Integral linearity error EZS EFS Note 1 Differential linearity error ILE DLE Note 1 Analog input voltage VAIN TYP. 8 10-bit resolution Note 3 AVREFP = VDD 10-bit resolution Target pin: ANI2, ANI3 10-bit resolution Target pin: Internal reference voltage, and temperature sensor output voltage (HS (high-speed main) mode) Zero-scale error MIN. 1.2 MAX. Unit 10 bit 3.5 LSB 7.0 1.2 Note 4 LSB 3.6 V VDD 5.5 V 2.125 39 s 2.7 V VDD 5.5 V 3.1875 39 s 1.8 V VDD 5.5 V 17 39 s 57 95 s 3.6 V VDD 5.5 V 2.375 39 s 2.7 V VDD 5.5 V 3.5625 39 s 2.4 V VDD 5.5 V 17 39 s 0.25 %FSR 10-bit resolution Note 3 AVREFP = VDD 0.50 0.25 10-bit resolution Note 3 AVREFP = VDD 0.50 10-bit resolution Note 3 AVREFP = VDD 5.0 Note 4 2.5 Note 4 1.5 10-bit resolution Note 3 AVREFP = VDD ANI2, ANI3 Note 4 2.0 0 Note 4 AVREFP Note 5 Internal reference voltage (2.4 V VDD 5.5 V, HS (high-speed main) mode) VBGR Temperature sensor output voltage (2.4 V VDD 5.5 V, HS (high-speed main) mode) VTMPS25 Note 5 %FSR %FSR %FSR LSB LSB LSB LSB V V V (Notes are listed on the next page.) R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 53 of 106 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C) RL78/G12 Notes 1. Excludes quantization error (1/2 LSB). 2. This value is indicated as a ratio (%FSR) to the full-scale value. 3. When AVREFP < VDD, the MAX. values are as follows. Overall error: Add 1.0 LSB to the MAX. value when AVREFP = VDD. Zero-scale error/Full-scale error: Add 0.05%FSR to the MAX. value when AVREFP = VDD. Integral linearity error/ Differential linearity error: Add 0.5 LSB to the MAX. value when AVREFP = VDD. 4. Values when the conversion time is set to 57 s (min.) and 95 s (max.). 5. Refer to 28.6.2 Temperature sensor/internal reference voltage characteristics. (2) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage () = AVREFM/ANI1 (ADREFM = 1), target pin: ANI16 to ANI22 (TA = 40 to +85C, 1.8 V AVREFP VDD 5.5 V, VSS = 0 V, Reference voltage (+) = AVREFP, Reference voltage () = AVREFM = 0 V) Parameter Symbol Resolution Conditions RES Overall error Note 1 AINL tCONV 10-bit resolution 1.2 Note 3 1.2 Zero-scale error EZS Full-scale error EFS Integral linearity error ILE error DLE Note 1 VAIN 5.0 LSB 8.5 Note 4 LSB s 3.1875 39 s 17 39 s 57 95 s 0.35 10-bit resolution Note 3 0.60 Note 3 0.60 Note 4 3.5 10-bit resolution Note 3 6.0 Note 4 2.0 10-bit resolution Note 3 ANI16 to ANI22 Note 4 0.35 10-bit resolution AVREFP = VDD Analog input voltage bit 39 AVREFP = VDD Differential linearity 10 2.125 AVREFP = VDD Note 1 Unit 3.6 V VDD 5.5 V AVREFP = VDD Notes 1, 2 MAX. Target ANI pin: ANI16 to ANI22 2.7 V VDD 5.5 V 10-bit resolution 1.8 V VDD 5.5 V Notes 1, 2 TYP. 8 AVREFP = VDD Conversion time MIN. 2.5 0 Note 4 AVREFP %FSR %FSR %FSR %FSR LSB LSB LSB LSB V and VDD Notes 1. Excludes quantization error (1/2 LSB). 2. This value is indicated as a ratio (%FSR) to the full-scale value. 3. When AVREFP VDD, the MAX. values are as follows. Overall error: Add 4.0 LSB to the MAX. value when AVREFP = VDD. Zero-scale error/Full-scale error: Add 0.20%FSR to the MAX. value when AVREFP = VDD. Integral linearity error/ Differential linearity error: Add 2.0 LSB to the MAX. value when AVREFP = VDD. 4. When the conversion time is set to 57 s (min.) and 95 s (max.). R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 54 of 106 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C) RL78/G12 (3) When reference voltage (+) = VDD (ADREFP1 = 0, ADREFP0 = 0), reference voltage () = VSS (ADREFM = 0), target pin: ANI0 to ANI3, ANI16 to ANI22, internal reference voltage, and temperature sensor output voltage (TA = 40 to +85C, 1.8 V VDD 5.5 V, VSS = 0 V, Reference voltage (+) = VDD, Reference voltage () = VSS) Parameter Symbol Resolution Conditions RES Note 1 Overall error AINL MIN. TYP. 8 10-bit resolution 1.2 tCONV tCONV 10 bit 7.0 LSB Note 3 LSB 10-bit resolution 3.6 V VDD 5.5 V 2.125 39 s Target pin: ANI0 to ANI3, 2.7 V VDD 5.5 V 3.1875 39 s 1.8 V VDD 5.5 V 17 39 s 57 95 s 3.6 V VDD 5.5 V 2.375 39 s Target pin: internal reference 2.7 V VDD 5.5 V voltage, and temperature 2.4 V VDD 5.5 V sensor output voltage (HS 3.5625 39 s 17 39 s 0.60 %FSR 0.85 %FSR ANI16 to ANI22 Conversion time Unit 10.5 1.2 Conversion time MAX. 10-bit resolution (high-speed main) mode) Notes 1, 2 Zero-scale error EZS 10-bit resolution Note 3 Full-scale error Notes 1, 2 EFS 10-bit resolution 0.60 %FSR 0.85 %FSR Note 3 Integral linearity error Note 1 ILE 4.0 10-bit resolution 6.5 Differential linearity error Note 1 DLE 2.0 10-bit resolution 2.5 Analog input voltage VAIN ANI0 to ANI3, ANI16 to ANI22 Note 3 0 Internal reference voltage Note 3 VDD VBGR Note 4 LSB LSB LSB LSB V V (2.4 V VDD 5.5 V, HS (high-speed main) mode) Temperature sensor output voltage VTMPS25 Note 4 V (2.4 V VDD 5.5 V, HS (high-speed main) mode) Notes 1. Excludes quantization error (1/2 LSB). 2. This value is indicated as a ratio (%FSR) to the full-scale value. 3. When the conversion time is set to 57 s (min.) and 95 s (max.). 4. Refer to 28.6.2 Temperature sensor/internal reference voltage characteristics. R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 55 of 106 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C) RL78/G12 (4) When reference voltage (+) = Internal reference voltage (ADREFP1 = 1, ADREFP0 = 0), reference voltage () = AVREFM (ADREFM = 1), target pin: ANI0, ANI2, ANI3, and ANI16 to ANI22 (TA = 40 to +85C, 2.4 V VDD 5.5 V, VSS = 0 V, Reference voltage (+) = VBGR Note 3, Reference voltage () = AVREFM Note 4 = 0 V, HS (high-speed main) mode) Parameter Symbol Resolution Conditions MIN. RES Conversion time Notes 1, 2 Zero-scale error Integral linearity error Note 1 Differential linearity error Note 1 Analog input voltage TYP. MAX. 8 Unit bit 39 s 8-bit resolution 0.60 %FSR ILE 8-bit resolution 2.0 LSB DLE 8-bit resolution 1.0 LSB tCONV 8-bit resolution EZS VAIN 17 0 VBGR Note 3 V Notes 1. Excludes quantization error (1/2 LSB). 2. This value is indicated as a ratio (%FSR) to the full-scale value. 3. Refer to 28.6.2 Temperature sensor/internal reference voltage characteristics. 4. When reference voltage () = VSS, the MAX. values are as follows. Zero-scale error: Add 0.35%FSR to the MAX. value when reference voltage () = AVREFM. Integral linearity error: Add 0.5 LSB to the MAX. value when reference voltage () = AVREFM. Differential linearity error: Add 0.2 LSB to the MAX. value when reference voltage () = AVREFM. R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 56 of 106 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C) RL78/G12 2.6.2 Temperature sensor/internal reference voltage characteristics (TA = 40 to +85C, 2.4 V VDD 5.5 V, VSS = 0 V, HS (high-speed main) mode Parameter Symbol Temperature sensor output voltage VTMPS25 Conditions MIN. Setting ADS register = 80H, TYP. MAX. 1.05 Unit V TA = +25C Internal reference voltage VBGR Setting ADS register = 81H Temperature coefficient FVTMPS Temperature sensor output 1.38 1.45 1.50 V 3.6 mV/C voltage that depends on the temperature Operation stabilization wait time tAMP s 5 2.6.3 POR circuit characteristics (TA = 40 to +85C, VSS = 0 V) Parameter Symbol Detection voltage Minimum pulse width Note Note Conditions MIN. TYP. MAX. Unit VPOR Power supply rise time 1.47 1.51 1.55 V VPDR Power supply fall time 1.46 1.50 1.54 V TPW s 300 Minimum time required for a POR reset when VDD exceeds below VPDR. This is also the minimum time required for a POR reset from when VDD exceeds below 0.7 V to when VDD exceeds VPOR while STOP mode is entered or the main system clock is stopped through setting bit 0 (HIOSTOP) and bit 7 (MSTOP) in the clock operation status control register (CSC). TPW Supply voltage (VDD) VPOR VPDR or 0.7 V R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 57 of 106 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C) RL78/G12 2.6.4 LVD circuit characteristics LVD Detection Voltage of Reset Mode and Interrupt Mode (TA = 40 to +85C, VPDR VDD 5.5 V, VSS = 0 V) Parameter Detection supply voltage Symbol VLVD0 VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 VLVD8 VLVD9 VLVD10 VLVD11 Minimum pulse width Detection delay time R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 tLW Conditions Power supply rise time MIN. TYP. MAX. Unit 3.98 4.06 4.14 V Power supply fall time 3.90 3.98 4.06 V Power supply rise time 3.68 3.75 3.82 V Power supply fall time 3.60 3.67 3.74 V Power supply rise time 3.07 3.13 3.19 V Power supply fall time 3.00 3.06 3.12 V Power supply rise time 2.96 3.02 3.08 V Power supply fall time 2.90 2.96 3.02 V Power supply rise time 2.86 2.92 2.97 V Power supply fall time 2.80 2.86 2.91 V Power supply rise time 2.76 2.81 2.87 V Power supply fall time 2.70 2.75 2.81 V Power supply rise time 2.66 2.71 2.76 V Power supply fall time 2.60 2.65 2.70 V Power supply rise time 2.56 2.61 2.66 V Power supply fall time 2.50 2.55 2.60 V Power supply rise time 2.45 2.50 2.55 V Power supply fall time 2.40 2.45 2.50 V Power supply rise time 2.05 2.09 2.13 V Power supply fall time 2.00 2.04 2.08 V Power supply rise time 1.94 1.98 2.02 V Power supply fall time 1.90 1.94 1.98 V Power supply rise time 1.84 1.88 1.91 V Power supply fall time 1.80 1.84 1.87 V s 300 300 s Page 58 of 106 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C) RL78/G12 LVD detection voltage of interrupt & reset mode (TA = 40 to +85C, VPDR VDD 5.5 V, VSS = 0 V) Parameter Symbol Interrupt and reset VLVDB0 mode VLVDB1 Conditions LVIS1, LVIS0 = 1, 0 LVIS1, LVIS0 = 0, 1 LVIS1, LVIS0 = 0, 0 VLVDB3 MAX. Unit 1.80 1.84 1.87 V Rising reset release voltage 1.94 1.98 2.02 V Falling interrupt voltage 1.90 1.94 1.98 V Rising reset release voltage 2.05 2.09 2.13 V Falling interrupt voltage 2.00 2.04 2.08 V Rising reset release voltage 3.07 3.13 3.19 V Falling interrupt voltage 3.00 3.06 3.12 V 2.40 2.45 2.50 V Rising reset release voltage 2.56 2.61 2.66 V Falling interrupt voltage 2.50 2.55 2.60 V Rising reset release voltage 2.66 2.71 2.76 V Falling interrupt voltage 2.60 2.65 2.70 V Rising reset release voltage 3.68 3.75 3.82 V Falling interrupt voltage 3.60 3.67 3.74 V VPOC2, VPOC1, VPOC0 = 0, 1, 0, falling reset voltage LVIS1, LVIS0 = 1, 0 VLVDC1 LVIS1, LVIS0 = 0, 1 VLVDC2 LVIS1, LVIS0 = 0, 0 VLVDC3 VLVDD0 TYP. VPOC2, VPOC1, VPOC0 = 0, 0, 1, falling reset voltage VLVDB2 VLVDC0 MIN. VPOC2, VPOC1, VPOC1 = 0, 1, 1, falling reset voltage VLVDD1 VLVDD2 VLVDD3 LVIS1, LVIS0 = 1, 0 LVIS1, LVIS0 = 0, 1 LVIS1, LVIS0 = 0, 0 2.70 2.75 2.81 V Rising reset release voltage 2.86 2.92 2.97 V Falling interrupt voltage 2.80 2.86 2.91 V Rising reset release voltage 2.96 3.02 3.08 V Falling interrupt voltage 2.90 2.96 3.02 V Rising reset release voltage 3.98 4.06 4.14 V Falling interrupt voltage 3.90 3.98 4.06 V 2.6.5 Power supply voltage rising slope characteristics (TA = 40 to +85C, VSS = 0 V) Parameter Power supply voltage rising slope Caution Symbol Conditions SVDD MIN. TYP. MAX. Unit 54 V/ms Make sure to keep the internal reset state by the LVD circuit or an external reset until VDD reaches the operating voltage range shown in 28.4 AC Characteristics. R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 59 of 106 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C) RL78/G12 <R> 2.7 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = 40 to +85C, VSS = 0 V) Parameter Data retention supply voltage <R> Symbol Conditions VDDDR MIN. 1.46 TYP. Note MAX. Unit 5.5 V Note This depends on the POR detection voltage. For a falling voltage, data in RAM are retained until the voltage reaches the level that triggers a POR reset but not once it reaches the level at which a POR reset is generated. Operation mode STOP mode RAM data retention VDD VDDDR STOP instruction execution Standby release signal (interrupt request) 2.8 Flash Memory Programming Characteristics (TA = 40 to +85C, 1.8 V VDD 5.5 V, VSS = 0 V) <R> Parameter Symbol System clock frequency fCLK Code flash memory rewritable times Cerwr Conditions MIN. TYP. 1 Retained for 20 years 1,000 MAX. Unit 24 MHz Times Notes 1, 2, 3 TA = 85C Data flash memory rewritable times 1,000,000 Retained for 1 year Notes 1, 2, 3 TA = 25C Retained for 5 years 100,000 TA = 85C Retained for 20 years 10,000 TA = 85C Notes 1. 1 erase + 1 write after the erase is regarded as 1 rewrite. The retaining years are until next rewrite after the rewrite. 2. When using flash memory programmer and Renesas Electronics self programming library 3. These are the characteristics of the flash memory and the results obtained from reliability testing by Renesas Electronics Corporation. R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 60 of 106 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C) RL78/G12 2.9 Dedicated Flash Memory Programmer Communication (UART) (TA = 40 to +85C, 1.8 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Transfer rate Conditions MIN. During serial programming TYP. 115,200 MAX. Unit 1,000,000 bps 2.10 Timing of Entry to Flash Memory Programming Modes (TA = 40 to +85C, 1.8 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Time to complete the communication for the initial Conditions MIN. TYP. POR and LVD reset are tSUINIT MAX. Unit 100 ms released before external setting after the external reset is released reset release Time to release the external reset after the TOOL0 tSU POR and LVD reset are pin is set to the low level released before external 10 s 1 ms reset release Time to hold the TOOL0 pin at the low level after POR and LVD reset are tHD the external reset is released released before external (excluding the processing time of the firmware to reset release control the flash memory) <1> <2> <4> <3> RESET tHD + software processing time 1-byte data for setting mode TOOL0 tSU tSUINIT <1> The low level is input to the TOOL0 pin. <2> The external reset is released (POR and LVD reset must be released before the external reset is released.). <3> The TOOL0 pin is set to the high level. <4> Setting of the flash memory programming mode by UART reception and complete the baud rate setting. Remark tSUINIT: Communication for the initial setting must be completed within 100 ms after the external reset is released during this period. tSU: Time to release the external reset after the TOOL0 pin is set to the low level tHD: Time to hold the TOOL0 pin at the low level after the external reset is released (excluding the processing time of the firmware to control the flash memory) R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 61 of 106 RL78/G12 <R> <R> 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = 40 to +105C) This chapter describes the following electrical specifications. Target products G: Industrial applications TA = -40 to +105C <R> R5F102xxGxx Cautions 1. The RL78 microcontrollers have an on-chip debug function, which is provided for development and evaluation. Do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not liable for problems occurring when the on-chip debug function is used. 2. The pins mounted depend on the product. Refer to 2.1 Port Functions to 2.2.1 Functions for each product. 3. Please contact Renesas Electronics sales office for derating of operation under TA = +85C to +105C. Derating is the systematic reduction of load for the sake of improved reliability. Remark When the RL78 microcontroller is used in the range of TA = -40 to +85 C, see CHAPTER 28 ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85 C). <R> There are following differences between the products "G: Industrial applications (TA = -40 to +105C)" and the products "A: Consumer applications, and D: Industrial applications". Parameter Application A: Consumer applications, G: Industrial applications D: Industrial applications Operating ambient temperature TA = -40 to +85C TA = -40 to +105C Operating mode HS (high-speed main) mode: HS (high-speed main) mode only: Operating voltage range 2.7 V VDD 5.5 V@1 MHz to 24 MHz 2.7 V VDD 5.5 V@1 MHz to 24 MHz 2.4 V VDD 5.5 V@1 MHz to 16 MHz 2.4 V VDD 5.5 V@1 MHz to 16 MHz LS (low-speed main) mode: 1.8 V VDD 5.5 V@1 MHz to 8 MHz High-speed on-chip oscillator clock R5F102 products, 1.8 V VDD 5.5 V: R5F102 products, 2.4 V VDD 5.5 V: accuracy 1.0%@ TA = -20 to +85C 2.0%@ TA = +85 to +105C 1.5%@ TA = -40 to -20C 1.0%@ TA = -20 to +85C R5F103 products, 1.8 V VDD 5.5 V: 1.5%@ TA = -40 to -20C 5.0%@ TA = -40 to +85C Serial array unit UART UART CSI: fCLK/2 (supporting 12 Mbps), fCLK/4 2 Voltage detector Remark CSI: fCLK/4 2 Simplified I C communication Simplified I C communication Rise detection voltage: 1.88 V to 4.06 V Rise detection voltage: 2.61 V to 4.06 V (12 levels) (8 levels) Fall detection voltage: 1.84 V to 3.98 V Fall detection voltage: 2.55 V to 3.98 V (12 levels) (8 levels) The electrical characteristics of the products G: Industrial applications (TA = -40 to +105C) are different from those of the products "A: Consumer applications, and D: Industrial applications". For details, refer to 29.1 to 29.10. R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 62 of 106 RL78/G12 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) 3.1 Absolute Maximum Ratings Absolute Maximum Ratings (TA = 25C) Parameter Symbols Supply Voltage VDD REGC terminal input Note1 voltage VIREGC Conditions REGC Ratings Unit 0.5 to + 6.5 V 0.3 to +2.8 V and 0.3 to VDD + 0.3 Note 2 Input Voltage VI1 Other than P60, P61 VI2 P60, P61 (N-ch open drain) Output Voltage VO Analog input voltage VAI 0.3 to VDD + 0.3 IOH1 V Note 3 V 0.3 to 6.5 0.3 to VDD + 0.3 V 0.3 to VDD + 0.3 20, 24-pin products: ANI0 to ANI3, ANI16 to ANI22 V and 0.3 to Notes 3, 4 AVREF(+)+0.3 30-pin products: ANI0 to ANI3, ANI16 to ANI19 Output current, high Note 3 Per pin Other than P20 to P23 40 mA Total of all pins All the terminals other than P20 to P23 170 mA 20-, 24-pin products: P40 to P42 70 mA , 20-, 24-pin products: P00 to P03 P10 to P14 30-pin products: P10 to P17, P30, P31, P50, P51, P147 100 mA P20 to P23 0.5 mA 2 mA 30-pin products: P00, P01, P40, P120 Note 5 IOH2 Per pin Total of all pins Output current, low IOL1 Per pin Other than P20 to P23 40 mA Total of all pins All the terminals other than P20 to P23 170 mA 20-, 24-pin products: P40 to P42 30-pin products: P00, P01, P40, P120 70 mA 100 mA 1 mA 5 mA Note 5 , 20-, 24-pin products: P00 to P03 P10 to P14, P60, P61 30-pin products: P10 to P17, P30, P31, P50, P51, P60, P61, P147 IOL2 Per pin Total of all pins P20 to P23 Operating ambient temperature TA 40 to +105 C Storage temperature Tstg 65 to +150 C Notes 1. 2. 3. 4. 5. 30-pin product only. Connect the REGC pin to VSS via a capacitor (0.47 to 1 F). This value determines the absolute maximum rating of the REGC pin. Do not use it with voltage applied. Must be 6.5 V or lower. Do not exceed AVREF (+) + 0.3 V in case of A/D conversion target pin. 24-pin products only. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remarks 1. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. 2. AVREF(+) : + side reference voltage of the A/D converter. 3. VSS : Reference voltage R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 63 of 106 RL78/G12 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) 3.2 Oscillator Characteristics 3.2.1 X1 oscillator characteristics (TA = 40 to +105C, 2.4 V VDD VDD 5.5 V, VSS = 0 V) Parameter X1 clock oscillation Note frequency (fX) Resonator Conditions MIN. TYP. MAX. Ceramic resonator / 2.7 V VDD 5.5 V 1.0 20.0 crystal oscillator 2.4 V VDD < 2.7 V 1.0 8.0 Unit MHz Note Indicates only permissible oscillator frequency ranges. Refer to AC Characteristics for instruction execution time. Request evaluation by the manufacturer of the oscillator circuit mounted on a board to check the oscillator characteristics. Caution Since the CPU is started by the high-speed on-chip oscillator clock after a reset release, check the X1 clock oscillation stabilization time using the oscillation stabilization time counter status register (OSTC) by the user. Determine the oscillation stabilization time of the OSTC register and the oscillation stabilization time select register (OSTS) after sufficiently evaluating the oscillation stabilization time with the resonator to be used. Remark When using the X1 oscillator, refer to 5.4 System Clock Oscillator. 3.2.2 On-chip oscillator characteristics (TA = 40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Oscillators High-speed on-chip oscillator clock frequency Parameters Conditions MAX. Unit 1 24 MHz TA = 20 to +85C -1.0 +1.0 % TA = 40 to 20C -1.5 +1.5 % TA = +85 to +105C -2.0 +2.0 % fIH MIN. TYP. Notes 1, 2 High-speed on-chip oscillator R5F102 products clock frequency accuracy Low-speed on-chip oscillator 15 fIL kHz clock frequency Low-speed on-chip oscillator -15 +15 % clock frequency accuracy Notes 1. High-speed on-chip oscillator frequency is selected by bits 0 to 3 of option byte (000C2H) and bits 0 to 2 of HOCODIV register. 2. This only indicates the oscillator characteristics. Refer to AC Characteristics for instruction execution time. R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 64 of 106 RL78/G12 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) 3.3 DC Characteristics 3.3.1 Pin characteristics (TA = 40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Note 1 Output current, high IOH1 (1/4) Conditions MIN. 20-, 24-pin products: Note 4 Per pin for P00 to P03 TYP. MAX. Unit 3.0 mA Note 2 , P10 to P14, P40 to P42 30-pin products: Per pin for P00, P01, P10 to P17, P30, P31, P40, P50, P51, P120, P147 4.0 V VDD 5.5 V 9.0 mA Total of P40 to P42 2.7 V VDD < 4.0 V 6.0 mA 30-pin products: 2.4 V VDD < 2.7 V 4.5 mA 4.0 V VDD 5.5 V 27.0 mA 2.7 V VDD < 4.0 V 18.0 mA 2.4 V VDD < 2.7 V 10.0 mA 36.0 mA Per pin for P20 to P23 0.1 mA Total of all pins 0.4 mA 20-, 24-pin products: Total of P00, P01, P40, P120 (When duty 70% Note 3 ) 20-, 24-pin products: Note 4 Total of P00 to P03 , P10 to P14 30-pin products: Total of P10 to P17, P30, P31, P50, P51, P147 (When duty 70% Note 3 ) Total of all pins (When duty 70% Note 3 IOH2 Notes 1. ) value of current at which the device operation is guaranteed even if the current flows from the VDD pin to an output pin. 2. 3. However, do not exceed the total current value. The output current value under conditions where the duty factor 70%. If duty factor 70%: The output current value can be calculated with the following expression (where n represents the duty factor as a percentage). Total output current of pins = (IOH x 0.7)/(n x 0.01) <Example> Where n = 80% and IOH = 10.0 mA Total output current of pins = (10.0 x 0.7)/(80 x 0.01) 8.7 mA However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A current higher than the absolute maximum rating must not flow into one pin. 4. 24-pin products only. Caution P10 to P12 and P41 for 20-pin products, P01, P10 to P12, and P41 for 24-pin products, and P00, P10 to P15, P17, and P50 for 30-pin products do not output high level in N-ch open-drain mode. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 65 of 106 RL78/G12 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) (TA = 40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter Output current, low Symbol Note 1 (2/4) Conditions MIN. 20-, 24-pin products: IOL1 Per pin for P00 to P03 Note 4 TYP. MAX. Unit 8.5 mA Note 2 , P10 to P14, P40 to P42 30-pin products: Per pin for P00, P01, P10 to P17, P30, P31, P40, P50, P51, P120, P147 15.0 Per pin for P60, P61 mA Note 2 20-, 24-pin products: 4.0 V VDD 5.5 V 25.5 mA Total of P40 to P42 2.7 V VDD < 4.0 V 9.0 mA 30-pin products: 2.4 V VDD < 2.7 V 1.8 mA 4.0 V VDD 5.5 V 40.0 mA 2.7 V VDD < 4.0 V 27.0 mA 2.4 V VDD < 2.7 V 5.4 mA 65.5 mA Per pin for P20 to P23 0.4 mA Total of all pins 1.6 mA Total of P00, P01, P40, P120 (When duty 70% Note 3 ) 20-, 24-pin products: Note 4 , Total of P00 to P03 P10 to P14, P60, P61 30-pin products: Total of P10 to P17, P30, P31, P50, P51, P60, P61, P147 (When duty 70% Note 3 ) Total of all pins (When duty 70% Note 3 IOL2 Notes 1. ) Value of current at which the device operation is guaranteed even if the current flows from an output pin to the VSS pin. 2. However, do not exceed the total current value. 3. The output current value under conditions where the duty factor 70%. If duty factor 70%: The output current value can be calculated with the following expression (where n represents the duty factor as a percentage). Total output current of pins = (IOL x 0.7)/(n x 0.01) <Example> Where n = 80% and IOL = 10.0 mA Total output current of pins = (10.0 x 0.7)/(80 x 0.01) 8.7 mA However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A current higher than the absolute maximum rating must not flow into one pin. 4. Remark 24-pin products only. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 66 of 106 RL78/G12 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) (TA = 40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter Input voltage, high Symbol VIH1 (3/4) Conditions MIN. MAX. Unit 0.8VDD VDD V 4.0 V VDD 5.5 V 2.2 VDD V 20-, 24-pin products: P10, P11 3.3 V VDD < 4.0 V 2.0 VDD V 2.4 V VDD < 3.3 V 1.5 VDD V 0.7VDD VDD V 0.7VDD 6.0 V 0.8VDD VDD V 0 0.2VDD V 4.0 V VDD 5.5 V 0 0.8 V 20-, 24-pin products: P10, P11 3.3 V VDD < 4.0 V 0 0.5 V 2.4 V VDD < 3.3 V 0 0.32 V 0 0.3VDD V 0 0.3VDD V 0 0.2VDD V Normal input buffer 20-, 24-pin products: P00 to P03 TYP. Note 2 , P10 to P14, P40 to P42 30-pin products: P00, P01, P10 to P17, P30, P31, P40, P50, P51, P120, P147 VIH2 TTL input buffer 30-pin products: P01, P10, P11, P13 to P17 VIH3 Normal input buffer P20 to P23 VIH4 Input voltage, low P60, P61 Note 1 VIH5 P121, P122, P125 , P137, EXCLK, RESET VIL1 Normal input buffer 20-, 24-pin products: P00 to P03 Note 2 , P10 to P14, P40 to P42 30-pin products: P00, P01, P10 to P17, P30, P31, P40, P50, P51, P120, P147 VIL2 TTL input buffer 30-pin products: P01, P10, P11, P13 to P17 Output voltage, high VIL3 P20 to P23 VIL4 P60, P61 Note 1 VIL5 P121, P122, P125 VOH1 20-, 24-pin products: P00 to P03 , P137, EXCLK, RESET Note 2 , P10 to P14, 4.0 V VDD 5.5 V, VDD0.7 V VDD0.6 V VDD0.5 V VDD0.5 V IOH1 = 3.0 mA P40 to P42 2.7 V VDD 5.5 V, 30-pin products: IOH1 = 2.0 mA P00, P01, P10 to P17, P30, 2.4 V VDD 5.5 V, P31, P40, P50, P51, P120, IOH1 = 1.5 mA P147 VOH2 Notes 1. 2. P20 to P23 IOH2 = 100 A 20, 24-pin products only. 24-pin products only. Caution The maximum value of VIH of pins P10 to P12 and P41 for 20-pin products, P01, P10 to P12, and P41 for 24pin products, and P00, P10 to P15, P17, and P50 for 30-pin products is VDD even in N-ch open-drain mode. High level is not output in the N-ch open-drain mode. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 67 of 106 RL78/G12 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) (TA = 40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter Output voltage, low Symbol VOL1 (4/4) Conditions 20-, 24-pin products: P00 to P03 Note , P10 to P14, TYP. 4.0 V VDD 5.5 V, MAX. Unit 0.7 V 0.6 V 0.4 V 0.4 V IOL1 = 8.5 mA P40 to P42 2.7 V VDD 5.5 V, 30-pin products: P00, P01, IOL1 = 3.0 mA P10 to P17, P30, P31, P40, 2.7 V VDD 5.5 V, P50, P51, P120, P147 MIN. IOL1 = 1.5 mA 2.4 V VDD 5.5 V, IOL1 = 0.6 mA VOL2 P20 to P23 IOL2 = 400 A 0.4 V VOL3 P60, P61 4.0 V VDD 5.5 V, 2.0 V 0.4 V 0.4 V 0.4 V VI = VDD 1 A VI = VDD Input port or external clock input 1 A 10 A VI = VSS 1 A VI = VSS Input port or external clock input 1 A 10 A 100 k IOL1 = 15.0 mA 4.0 V VDD 5.5 V, IOL1 = 5.0 mA 2.7 V VDD 5.5 V, IOL1 = 3.0 mA 2.4 V VDD 5.5 V, IOL1 = 2.0 mA Input leakage current, ILIH1 Other than P121, P122 high ILIH2 P121, P122 (X1, X2/EXCLK) When resonator connected Input leakage current, ILIL1 Other than P121, P122 low ILIL2 P121, P122 (X1, X2/EXCLK) When resonator connected On-chip pull-up RU 20-, 24-pin products: P00 to P03 resistance VI = VSS, input port 10 20 Note , P10 to P14, P40 to P42, P125, RESET 30-pin products: P00, P01, P10 to P17, P30, P31, P40, P50, P51, P120, P147 Note 24-pin products only. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 68 of 106 RL78/G12 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) 3.3.2 Supply current characteristics (1) 20-, 24-pin products (TA = 40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter Supply current Symbol IDD1 Note 1 (1/2) Conditions Operating HS (High-speed mode main) mode Note 3 fIH = 24 MHz Note 4 MIN. VDD = 5.0 V 1.5 operation VDD = 3.0 V 1.5 Normal VDD = 5.0 V 3.3 5.3 operation VDD = 3.0 V 3.3 5.3 VDD = 5.0 V 2.5 3.9 VDD = 3.0 V 2.5 3.9 Square wave input 2.8 4.7 Resonator connection 3.0 4.8 Square wave input 2.8 4.7 Resonator connection 3.0 4.8 Square wave input 1.8 2.8 Resonator connection 1.8 2.8 Square wave input 1.8 2.8 Resonator connection 1.8 2.8 Note 3 Note 2 , VDD = 5.0 V Note 2 fMX = 20 MHz , VDD = 3.0 V Note 2 fMX = 10 MHz , VDD = 5.0 V Note 2 fMX = 10 MHz , VDD = 3.0 V Notes 1. MAX. Basic fIH = 16 MHz fMX = 20 MHz TYP. Unit mA mA mA mA mA mA mA Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is fixed to VDD or VSS. The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. 2. When high-speed on-chip oscillator clock is stopped. 3. When high-speed system clock is stopped 4. Relationship between operation voltage width, operation frequency of CPU and operation mode is as follows. HS(High speed main) mode: VDD = 2.7 V to 5.5 V @1 MHz to 24 MHz VDD = 2.4 V to 5.5 V @1 MHz to 16 MHz Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) 2. fIH: high-speed on-chip oscillator clock frequency 3. Temperature condition of the TYP. value is TA = 25C. R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 69 of 106 RL78/G12 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) (1) 20-, 24-pin products (TA = 40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter Supply current Symbol IDD2 Note 2 Note 1 (2/2) Conditions HALT HS (High-speed mode Note 6 main) mode MIN. Note 4 fIH = 24 MHz Note 4 fIH = 16 MHz Note 3 fMX = 20 MHz , VDD = 5.0 V VDD = 5.0 V 440 2230 A VDD = 3.0 V 440 2230 VDD = 5.0 V 400 1650 VDD = 3.0 V 400 1650 Square wave input 280 1900 450 2000 Square wave input 280 1900 Resonator connection 450 2000 Note 3 Square wave input 190 1010 Resonator connection 260 1090 Square wave input 190 1010 Resonator connection 260 1090 fMX = 10 MHz , , VDD = 5.0 V Note 3 fMX = 10 MHz , VDD = 3.0 V Notes 1. Unit Resonator connection VDD = 3.0 V IDD3 MAX. Note 3 fMX = 20 MHz Note 5 TYP. STOP TA = 40C 0.19 0.50 mode TA = +25C 0.24 0.50 TA = +50C 0.32 0.80 TA = +70C 0.48 1.20 TA = +85C 0.74 2.20 TA = +105C 1.50 10.20 A A A A A A Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is fixed to VDD or VSS. The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. 2. During HALT instruction execution by flash memory. 3. When high-speed on-chip oscillator clock is stopped. 4. When high-speed system clock is stopped. 5. Not including the current flowing into the 12-bit interval timer and watchdog timer. 6. Relationship between operation voltage width, operation frequency of CPU and operation mode is as follows. HS (High speed main) mode: VDD = 2.7 V to 5.5 V @1 MHz to 24 MHz VDD = 2.4 V to 5.5 V @1 MHz to 16 MHz Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) 2. fIH: high-speed on-chip oscillator clock frequency 3. Except temperature condition of the TYP. value is TA = 25C, other than STOP mode R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 70 of 106 RL78/G12 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) (2) 30-pin products (TA = 40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter Supply current Symbol IDD1 Note 1 (1/2) Conditions Operating mode HS (High-speed fIH = 24 MHzNote 3 Note 4 main) mode MIN. Basic MAX. VDD = 5.0 V operation VDD = 3.0 V 1.5 Normal VDD = 5.0 V operation VDD = 3.0 V 3.7 5.8 3.7 5.8 VDD = 5.0 V 2.7 4.2 Note 3 fIH = 16 MHz 1.5 VDD = 3.0 V 2.7 4.2 Square wave input 3.0 4.9 Resonator connection 3.2 5.0 Note 2 Square wave input 3.0 4.9 Resonator connection 3.2 5.0 Square wave input 1.9 2.9 Resonator connection 1.9 2.9 Square wave input 1.9 2.9 Resonator connection 1.9 2.9 fMX = 20 MHz , fMX = 20 MHz , VDD = 3.0 V Note 2 fMX = 10 MHz , VDD = 5.0 V Note 2 fMX = 10 MHz , VDD = 3.0 V Unit mA Note 2 VDD = 5.0 V Notes 1. TYP. mA mA mA mA mA mA Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is fixed to VDD or VSS. The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. 2. When high-speed on-chip oscillator clock is stopped. 3. When high-speed system clock is stopped 4. Relationship between operation voltage width, operation frequency of CPU and operation mode is as follows. HS(High speed main) mode: VDD = 2.7 V to 5.5 V @1 MHz to 24 MHz VDD = 2.4 V to 5.5 V @1 MHz to 16 MHz Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) 2. fIH: high-speed on-chip oscillator clock frequency 3. Temperature condition of the TYP. value is TA = 25C. R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 71 of 106 RL78/G12 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) (2) 30-pin products (TA = 40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter Supply current Symbol IDD2 (2/2) Conditions Note 2 HALT Note 1 mode HS (High-speed main) mode MIN. Note 4 fIH = 24 MHz fIH = 16 MHz Note 3 fMX = 20 MHz , VDD = 5.0 V VDD = 5.0 V 440 2300 A VDD = 3.0 V 440 2300 VDD = 5.0 V 400 1700 VDD = 3.0 V 400 1700 Square wave input 280 1900 Resonator connection 450 2000 Square wave input 280 1900 Resonator connection 450 2000 Note 3 Square wave input 190 1020 Resonator connection 260 1100 Square wave input 190 1020 Resonator connection 260 1100 , VDD = 3.0 V fMX = 10 MHz , VDD = 5.0 V Note 3 fMX = 10 MHz , VDD = 3.0 V Notes 1. Unit Note 3 fMX = 20 MHz IDD3 MAX. Note 6 Note 4 Note 5 TYP. STOP TA = 40C 0.18 0.50 mode TA = +25C 0.23 0.50 TA = +50C 0.30 1.10 TA = +70C 0.46 1.90 TA = +85C 0.75 3.30 TA = +105C 2.94 15.30 A A A A A A Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is fixed to VDD or VSS. The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. 2. During HALT instruction execution by flash memory. 3. When high-speed on-chip oscillator clock is stopped. 4. When high-speed system clock is stopped. 5. Not including the current flowing into the 12-bit interval timer and watchdog timer. 6. Relationship between operation voltage width, operation frequency of CPU and operation mode is as follows. HS (High speed main) mode: VDD = 2.7 V to 5.5 V @1 MHz to 24 MHz VDD = 2.4 V to 5.5 V @1 MHz to 16 MHz Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) 2. fIH: high-speed on-chip oscillator clock frequency 3. Except STOP mode, temperature condition of the TYP. value is TA = 25C. R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 72 of 106 RL78/G12 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) (3) Peripheral functions (Common to all products) (TA = 40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter Low-speed onchip Symbol IFIL Conditions MIN. Note 1 TYP. MAX. Unit 0.20 A 0.02 A 0.22 A oscillator operating current 12-bit interval timer ITMKA operating current Notes 1, 2, 3 Watchdog timer IWDT operating current Notes 1, 2, 4 A/D converter operating current IADC A/D converter reference voltage operating current IADREF Temperature sensor operating current LVD operating current Notes 1, 5 fIL = 15 kHz When conversion at maximum speed Normal mode, AVREFP = VDD = 5.0 V 1.30 1.70 mA Low voltage mode, AVREFP = VDD = 3.0 V 0.50 0.70 mA 75.0 A 75.0 A 0.08 A Note 1 ITMPS Note 1 ILVD Notes 1, 6 Self-programming IFSP operating current Notes 1, 8 BGO operating IBGO current Notes 1, 7 SNOOZE operating ISNOZ current Note 1 ADC operation The mode is performed Note 9 The A/D conversion operations are 2.00 12.20 mA 2.00 12.20 mA 0.50 1.10 mA 1.20 2.04 mA 0.70 1.54 mA performed, Low voltage mode, AVREFP = VDD = 3.0 V CSI/UART operation Notes 1. Current flowing to the VDD. 2. When high speed on-chip oscillator and high-speed system clock are stopped. 3. Current flowing only to the 12-bit interval timer (excluding the operating current of the low-speed on-chip oscillator). The current value of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3, and IFIL and ITMKA when the 12-bit interval timer operates. 4. Current flowing only to the watchdog timer (including the operating current of the low-speed on-chip oscillator). The current value of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and IWDT when the watchdog timer operates. 5. Current flowing only to the A/D converter. The current value of the RL78 microcontrollers is the sum of IDD1 or IDD2 and IADC when the A/D converter operates in an operation mode or the HALT mode. 6. Current flowing only to the LVD circuit. The current value of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and ILVD when the LVD circuit operates. 7. Current flowing only during data flash rewrite. 8. Current flowing only during self programming. 9. For shift time to the SNOOZE mode, see 17.3.3 SNOOZE mode. Remarks 1. fIL: Low-speed on-chip oscillator clock frequency 2. Temperature condition of the TYP. value is TA = 25C R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 73 of 106 RL78/G12 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) 3.4 AC Characteristics (TA = 40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Items Instruction cycle (minimum Symbol TCY instruction execution time) Conditions MIN. TYP. MAX. Unit Main system HS (High- 2.7 V VDD 5.5 V 0.04167 1 s clock (fMAIN) speed main) 2.4 V VDD 2.7 V 0.0625 1 s operation mode During self HS (High- 2.7 V VDD 5.5 V 0.04167 1 s programming speed main) 2.4 V VDD 2.7 V 0.0625 1 s 2.7 V VDD 5.5 V 1.0 20.0 MHz 2.4 V VDD 2.7 V 1.0 16.0 MHz 2.7 V VDD 5.5 V 24 ns 2.4 V VDD 2.7 V 30 ns 1/fMCK + ns mode External main system clock fEX frequency External main system clock tEXH, tEXL input high-level width, lowlevel width TI00 to TI07 input high-level tTIH, tTIL width, low-level width TO00 to TO07 output 10 fTO frequency PCLBUZ0, or PCLBUZ1 fPCL output frequency INTP0 to INTP5 input high- 4.0 V VDD 5.5 V 12 MHz 2.7 V VDD 4.0 V 8 MHz 2.4 V VDD 2.7 V 4 MHz 4.0 V VDD 5.5 V 16 MHz 2.7 V VDD 4.0 V 8 MHz 2.4 V VDD 2.7 V 4 MHz 1 s tKR 250 ns tRSL 10 s tINTH, tINTL level width, low-level width KR0 to KR9 input available width RESET low-level width Remark fMCK: Timer array unit operation clock frequency (Operation clock to be set by the timer clock select register 0 (TPS0) and the CKS0n bit of timer mode register 0n (TMR0n). n: Channel number (n = 0 to 7)) R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 74 of 106 RL78/G12 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) Minimum Instruction Execution Time during Main System Clock Operation TCY vs VDD (HS (high-speed main) mode) Cycle time TCY [s] 10 1.0 When the high-speed on-chip oscillator clock is selected During self programming When high-speed system clock is selected 0.1 0.0625 0.04167 0.01 0 1.0 2.0 3.0 2.4 2.7 4.0 5.0 5.5 6.0 Supply voltage VDD [V] AC Timing Test Point VIH/VOH Test points VIL/VOL VIH/VOH VIL/VOL External Main System Clock Timing 1/fEX tEXL tEXH EXCLK R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 75 of 106 RL78/G12 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) TI/TO Timing tTIH tTIL TI00 to TI07 1/fTO TO00 to TO07 Interrupt Request Input Timing tINTL tINTH INTP0 to INTP5 Key Interrupt Input Timing tKR KR0 to KR9 RESET Input Timing tRSL RESET R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 76 of 106 RL78/G12 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) 3.5 Peripheral Functions Characteristics AC Timing Test Point VIH/VOH VIH/VOH Test points VIL/VOL VIL/VOL 3.5.1 Serial array unit (1) During communication at same potential (UART mode) (TA = 40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode MIN. Transfer rate Note 1 MAX. fMCK/12 bps 2.0 Mbps Theoretical value of the maximum transfer rate fCLK = fMCK Notes 1. 2. Unit Note2 Transfer rate in the SNOOZE mode is 4800 bps only. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are: HS (high-speed main) mode: 24 MHz (2.7 V VDD 5.5 V) 16 MHz (2.4 V VDD 5.5 V) Caution Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). UART mode connection diagram (during communication at same potential) Rx TxDq RL78 microcontroller User's device RxDq Tx UART mode bit width (during communication at same potential) (reference) 1/Transfer rate High-/Low-bit width Baud rate error tolerance TxDq RxDq Remarks 1. 2. q: UART number (q = 0 to 2), g: PIM, POM number (g = 0, 1) fMCK: Serial array unit operation clock frequency (Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10, 11)) R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 77 of 106 RL78/G12 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) (2) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output) (TA = 40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode MIN. SCKp cycle time tKCY1 SCKp high-/low-level width SIp setup time (to SCKp) Note 1 SIp hold time (from SCKp) Note 2 Delay time from SCKp to SOp output tKCY1 4/fCLK Unit MAX. 2.7 V VDD 5.5 V 334 ns 2.4 V VDD 5.5 V 500 ns tKH1, 4.0 V VDD 5.5 V tKCY1/224 ns tKL1 2.7 V VDD 5.5 V tKCY1/236 ns 2.4 V VDD 5.5 V tKCY1/276 ns 4.0 V VDD 5.5 V 66 ns 2.7 V VDD 5.5 V 66 ns 2.4 V VDD 5.5 V 113 ns 38 ns tSIK1 tKSI1 tKSO1 C = 30 pF Note4 50 ns Note 3 Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes "to SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 4. C is the load capacitance of the SCKp and SOp output lines. Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp and SCKp pins by using port input mode register 1 (PIM1) and port output mode registers 0, 1, 4 (POM0, POM1, POM4). Remarks 1. p: CSI number (p = 00, 01, 11, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0, 1, 3) 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0, 1), n: Channel number (n = 0, 1, 3)) R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 78 of 106 RL78/G12 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) (3) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input) (TA = 40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode MIN. SCKp cycle time Note4 tKCY2 4.0 V VDD 5.5 V 2.7 V VDD 5.5 V Unit MAX. 20 MHz fMCK 16/fMCK ns fMCK 20 MHz 12/fMCK ns 16 MHz fMCK 16/fMCK ns fMCK 16 MHz 12/fMCK ns 12/fMCK ns 2.4 V VDD 5.5 V and 1000 SCKp high-/low-level width SIp setup time (to SCKp) tKH2, 4.0 V VDD 5.5 V tKCY2/214 ns tKL2 2.7 V VDD 5.5 V tKCY2/216 ns tSIK2 Note 1 SIp hold time (from SCKp) tKCY2/236 ns 2.7 V VDD 5.5 V 1/fMCK + 40 ns 2.4 V VDD 5.5 V 1/fMCK + 60 ns 1/fMCK + 62 ns tKSI2 Note 2 Delay time from SCKp to SOp output 2.4 V VDD 5.5 V tKSO2 C = 30 pF Note4 Note 3 Notes 1. 2.7 V VDD 5.5 V 2/fMCK + 66 ns 2.4 V VDD 5.5 V 2/fMCK + 113 ns When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes "to SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 4. C is the load capacitance of the SOp output lines. 5. Transfer rate in the SNOOZE mode: MAX. 1 Mbps Caution Select the normal input buffer for the SIp and SCKp pins and the normal output mode for the SOp pin by using port input mode register 1 (PIM1) and port output mode registers 0, 1, 4 (POM0, POM1, POM4). CSI mode connection diagram (during communication at same potential) SCKp RL78 microcontroller SIp SOp R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 SCK SO User's device SI Page 79 of 106 RL78/G12 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) CSI mode serial transfer timing (during communication at same potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) tKCY1, 2 tKL1, 2 tKH1, 2 SCKp tSIK1, 2 SIp tKSI1, 2 Input data tKSO1, 2 SOp Output data CSI mode serial transfer timing (during communication at same potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) tKCY1, 2 tKH1, 2 tKL1, 2 SCKp tSIK1, 2 SIp tKSI1, 2 Input data tKSO1, 2 SOp Remarks 1. 2. Output data p: CSI number (p = 00, 01, 11, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0, 1, 3) fMCK: Serial array unit operation clock frequency (Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0,1), n: Channel number (n = 0, 1, 3)) R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 80 of 106 RL78/G12 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) 2 (4) During communication at same potential (simplified I C mode) (TA = 40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode MIN. SCLr clock frequency fSCL Cb = 100 pF, Rb = 3 k Hold time when SCLr = "L" tLOW Cb = 100 pF, Rb = 3 k 4600 Hold time when SCLr = "H" tHIGH Cb = 100 pF, Rb = 3 k 4600 Data setup time (reception) tSU:DAT Cb = 100 pF, Rb = 3 k Data hold time (transmission) tHD:DAT Cb = 100 pF, Rb = 3 k Notes 1. 2. MAX. 100 1/fMCK + 580 Unit Note 1 kHz ns ns Note 2 0 ns 1420 ns The value must also be equal to or less than fMCK/4. Set tSU:DAT so that it will not exceed the hold time when SCLr = "L" or SCLr = "H". Caution Select the N-ch open drain output (VDD tolerance) mode for SDAr by using port output mode register h (POMh). 2 Simplified I C mode connection diagram (during communication at same potential) VDD Rb SDA SDAr RL78 microcontroller User's device SCLr SCL 2 Simplified I C mode serial transfer timing (during communication at same potential) 1/fSCL tLOW tHIGH SCLr SDAr tHD:DAT Remarks 1. tSU:DAT Rb []:Communication line (SDAr) pull-up resistance Cb [F]: Communication line (SCLr, SDAr) load capacitance 2. 3. r: IIC number (r = 00, 01, 11, 20), h: = POM number (h = 0, 1, 4, 5) fMCK: Serial array unit operation clock frequency (Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0, 1), n: Channel number (0, 1, 3)) R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 81 of 106 RL78/G12 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) (5) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode) (TA = 40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter Symbol HS (high-speed main) Conditions Unit Mode MIN. Transfer rate Reception Note4 4.0 V VDD 5.5 V, MAX. fMCK/12 bps Note 1 2.7 V Vb 4.0 V Theoretical value of the maximum 2.0 Mbps fMCK/12 bps transfer rate Note 2 fMCK = fCLK 2.7 V VDD < 4.0 V, Note 1 2.3 V Vb 2.7 V Theoretical value of the maximum 2.0 Mbps fMCK/12 bps transfer rate Note 2 fMCK = fCLK 2.4 V VDD < 3.3 V, Note 1 1.6 V Vb 2.0 V Theoretical value of the maximum 2.0 Mbps Note 3 bps 2.0 Mbps transfer rate Note 2 fMCK = fCLK Transmission 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V Theoretical value of the maximum transfer rate Note 4 Cb = 50 pF, Rb = 1.4 k, Vb = 2.7 V 2.7 V VDD < 4.0 V, Note 5 bps 1.2 Mbps 2.3 V Vb 2.7 V, Theoretical value of the maximum transfer rate Note 6 Cb = 50 pF, Rb = 2.7 k, Vb = 2.3 V 2.4 V VDD < 3.3 V, Notes bps 2, 7 1.6 V Vb 2.0 V Theoretical value of the maximum 0.43 transfer rate Note 8 Mbps Cb = 50 pF, Rb = 5.5 k, Vb = 1.6 V Notes 1. 2. Transfer rate in the SNOOZE mode is 4800 bps only. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are: HS (high-speed main) mode: 24 MHz (2.7 V VDD 5.5 V) 16 MHz (2.4 V VDD 5.5 V) 3. The smaller maximum transfer rate derived by using fMCK/12 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 4.0 V VDD 5.5 V and 2.7 V Vb 4.0 V 1 Maximum transfer rate = R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 {Cb x Rb x ln (1 2.2 )} x 3 Vb [bps] Page 82 of 106 RL78/G12 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) 2.2 1 {Cb x Rb x ln (1 )} Vb Transfer rate 2 Baud rate error (theoretical value) = ( 1 ) x Number of transferred bits Transfer rate x 100 [%] * This value is the theoretical value of the relative difference between the transmission and reception sides. 4. This value as an example is calculated when the conditions described in the "Conditions" column are met. Refer to Note 3 above to calculate the maximum transfer rate under conditions of the customer. 5. The smaller maximum transfer rate derived by using fMCK/12 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 2.7 V VDD < 4.0 V and 2.3 V Vb 2.7 V 1 Maximum transfer rate = {Cb x Rb x ln (1 2.0 )} x 3 Vb [bps] 2.0 1 {Cb x Rb x ln (1 )} Vb Transfer rate 2 Baud rate error (theoretical value) = ( 1 ) x Number of transferred bits Transfer rate x 100 [%] * This value is the theoretical value of the relative difference between the transmission and reception sides. 6. This value as an example is calculated when the conditions described in the "Conditions" column are met. Refer to Note 5 above to calculate the maximum transfer rate under conditions of the customer. 7. The smaller maximum transfer rate derived by using fMCK/12 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 2.4 V VDD < 3.3 V, 1.6 V Vb 2.0 V 1 Maximum transfer rate = {Cb x Rb x ln (1 1.5 )} x 3 Vb [bps] 1.5 1 {Cb x Rb x ln (1 )} Vb Transfer rate 2 Baud rate error (theoretical value) = ( 1 ) x Number of transferred bits Transfer rate x 100 [%] * This value is the theoretical value of the relative difference between the transmission and reception sides. 8. This value as an example is calculated when the conditions described in the "Conditions" column are met. Refer to Note 7 above to calculate the maximum transfer rate under conditions of the customer. Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance) mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 83 of 106 RL78/G12 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) UART mode connection diagram (during communication at different potential) Vb Rb Rx TxDq RL78 microcontroller User's device RxDq Tx UART mode bit width (during communication at different potential) (reference) 1/Transfer rate Low-bit width High-bit width Baud rate error tolerance TxDq 1/Transfer rate High-/Low-bit width Baud rate error tolerance RxDq Remarks 1. Rb[]: Communication line (TxDq) pull-up resistance, Cb[F]: Communication line (TxDq) load capacitance, Vb[V]: Communication line voltage 2. q: UART number (q = 0 to 2), g: PIM and POM number (g = 0, 1) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10, 11)) 4. UART0 of the 20- and 24-pin products supports communication at different potential only when the peripheral I/O redirection function is not used. R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 84 of 106 RL78/G12 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) (6) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output) (1/3) (TA = 40 to +105C, 2.4 V VDD VDD 5.5 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode MIN. SCKp cycle time tKCY1 tKCY1 4/fCLK 4.0 V VDD 5.5 V, Unit MAX. 600 ns 1000 ns 2300 ns tKCY1/2 150 ns tKCY1/2 340 ns tKCY1/2 916 ns tKCY1/2 24 ns tKCY1/2 36 ns tKCY1/2 100 ns 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 2.4 V VDD < 3.3 V, 1.6 V Vb 2.0 V, Cb = 30 pF, Rb = 5.5 k SCKp high-level width tKH1 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 2.4 V VDD < 3.3 V, 1.6 V Vb 2.0 V, Cb = 30 pF, Rb = 5.5 k SCKp low-level width tKL1 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 2.4 V VDD < 3.3 V, 1.6 V Vb 2.0 V, Cb = 30 pF, Rb = 5.5 k Cautions 1. Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode for the SOp pin and SCKp pin by using port input mode register 1 (PIM1) and port output mode register 1 (POM1). For VIH and VIL, see the DC characteristics with TTL input buffer selected. 2. Remarks 1. CSI01 and CSI11 cannot communicate at different potential. Rb []: Communication line (SCKp, SOp) pull-up resistance, Cb [F]: Communication line (SCKp, SOp) load capacitance, Vb [V]: Communication line voltage 2. p: CSI number (p = 00, 20) R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 85 of 106 RL78/G12 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) (6) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output) (2/3) (TA = 40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode MIN. SIp setup time (to SCKp) tSIK1 Note 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, Unit MAX. 162 ns 354 ns 958 ns 38 ns 38 ns 38 ns Cb = 30 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 2.4 V VDD < 3.3 V, 1.6 V Vb 2.0 V, Cb = 30 pF, Rb = 5.5 k SIp hold time (from SCKp) tKSI1 Note 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 2.4 V VDD < 3.3 V, 1.6 V Vb 2.0 V, Cb = 30 pF, Rb = 5.5 k Delay time from SCKp to SOp output tKSO1 Note 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, 200 ns 390 ns 966 ns Cb = 30 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 2.4 V VDD < 3.3 V, 1.6 V Vb 2.0 V, Cb = 30 pF, Rb = 5.5 k Note When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. (Cautions and Remarks are listed on the next page.) R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 86 of 106 RL78/G12 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) (6) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output) (3/3) (TA = 40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode MIN. SIp setup time (to SCKp) 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, tSIK1 Note Unit MAX. 88 ns 88 ns 220 ns 38 ns 38 ns 38 ns Cb = 30 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 2.4 V VDD < 3.3 V, 1.6 V Vb 2.0 V, Cb = 30 pF, Rb = 5.5 k SIp hold time (from SCKp) 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, tKSI1 Note Cb = 30 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 2.4 V VDD < 3.3 V, 1.6 V Vb 2.0 V, Cb = 30 pF, Rb = 5.5 k Delay time from SCKp to SOp output 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, tKSO1 Note 50 ns 50 ns 50 ns Cb = 30 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 2.4 V VDD < 3.3 V, 1.6 V Vb 2.0 V, Cb = 30 pF, Rb = 5.5 k Note When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Cautions 1. Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode for the SOp pin and SCKp pin by using port input mode register 1 (PIM1) and port output mode register 1 (POM1). For VIH and VIL, see the DC characteristics with TTL input buffer selected. 2. Remarks 1. CSI01 and CSI11 cannot communicate at different potential. Rb []: Communication line (SCKp, SOp) pull-up resistance, Cb [F]: Communication line (SCKp, SOp) load capacitance, Vb [V]: Communication line voltage 2. p: CSI number (p = 00, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0) CSI mode connection diagram (during communication at different potential) Vb <Master> Rb SCKp RL78 microcontroller R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Vb Rb SCK SIp SO SOp SI User's device Page 87 of 106 RL78/G12 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) CSI mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1) t KCY1 t KL1 t KH1 SCKp t SIK1 SIp t KSI1 Input data t KSO1 SOp Output data CSI mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) tKCY1 tKL1 tKH1 SCKp tSIK1 SIp tKSI1 Input data tKSO1 Output data SOp Remark p: CSI number (p = 00, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0) R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 88 of 106 RL78/G12 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) (7) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (slave mode, SCKp... external clock input) (TA = 40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter Symbol HS (high-speed main) Conditions Unit Mode MIN. SCKp cycle time Note 1 tKCY2 MAX. 4.0 V VDD 5.5 V, 20 MHz < fMCK 24 MHz 24/fMCK ns 2.7 V Vb 4.0 V 8 MHz < fMCK 20 MHz 20/fMCK ns 4 MHz < fMCK 8 MHz 16/fMCK ns fMCK 4 MHz 12/fMCK ns 2.7 V VDD < 4.0 V, 20 MHz < fMCK 24 MHz 32/fMCK ns 2.3 V Vb 2.7 V 16 MHz < fMCK 20 MHz 28/fMCK ns 8 MHz < fMCK 16 MHz 24/fMCK ns 4 MHz < fMCK 8 MHz 16/fMCK ns fMCK 4 MHz 12/fMCK ns 2.4 V VDD < 3.3 V, 20 MHz < fMCK 24 MHz 72/fMCK ns 1.6 V Vb 2.0 V 16 MHz < fMCK 20 MHz 64/fMCK ns 8 MHz < fMCK 16 MHz 52/fMCK ns 4 MHz < fMCK 8 MHz 32/fMCK ns fMCK 4 MHz 20/fMCK ns SCKp high-/low-level tKH2, 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V tKCY2/2 24 ns width tKL2 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V tKCY2/2 36 ns 2.4 V VDD < 3.3 V, 1.6 V Vb 2.0 V tKCY2/2 100 ns 4.0 V VDD 5.5 V, 2.7 V VDD 4.0 V 1/fMCK + 40 ns 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V 1/fMCK + 40 ns 2.4 V VDD < 3.3 V, 1.6 V VDD 2.0 V 1/fMCK + 60 ns 1/fMCK + 62 ns SIp setup time (to SCKp) tSIK2 Note 2 SIp hold time (from SCKp) tKSI2 Note 3 Delay time from SCKp to SOp output tKSO2 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, 2/fMCK + Note 4 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, 2/fMCK + 2/fMCK + Cb = 30 pF, Rb = 5.5 k Notes 1. 2. ns 428 Cb = 30 pF, Rb = 2.7 k 2.4 V VDD < 3.3 V, 1.6 V Vb 2.0 V, ns 240 Cb = 30 pF, Rb = 1.4 k ns 1146 Transfer rate in the SNOOZE mode: MAX. 1 Mbps When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes "to SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Cautions 1. Select the TTL input buffer for the SIp and SCKp pins and the N-ch open drain output (VDD tolerance) mode for the SOp pin by using port input mode register 1 (PIM1) and port output mode register 1 (POM1). For VIH and VIL, see the DC characteristics with TTL input buffer selected. 2. CSI01 and CSI11 cannot communicate at different potential. R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 89 of 106 RL78/G12 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) CSI mode connection diagram (during communication at different potential) Vb <Slave> Rb SCKp RL78 microcontroller SCK SIp SO SOp SI User's device CSI mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) t KCY2 t KH2 t KL2 SCKp t SIK2 t KSI2 Input data SIp t KSO2 SOp Output data Remarks 1. Rb []: Communication line (SOp) pull-up resistance, Cb [F]: Communication line (SOp) load capacitance, Vb [V]: Communication line voltage 2. p: CSI number (p = 00, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode register mn (SMRmn)) R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 90 of 106 RL78/G12 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) CSI mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) t KCY2 t KL2 t KH2 SCKp t SIK2 SIp t KSI2 Input data t KSO2 SOp Remark Output data p: CSI number (p = 00, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0) R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 91 of 106 RL78/G12 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) 2 (8) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I C mode) (TA = 40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Unit Mode MIN. SCLr clock frequency fSCL 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, MAX. Note1 kHz Note1 kHz Note1 kHz 100 Cb = 100 pF, Rb = 2.8 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, 100 Cb = 100 pF, Rb = 2.7 k 2.4 V VDD < 3.3 V, 1.6 V Vb 2.0 V, 100 Cb = 100 pF, Rb = 5.5 k Hold time when SCLr = "L" tLOW 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, 4600 ns 4600 ns 4650 ns 2700 ns 2400 ns 1830 ns 1/fMCK ns Cb = 100 pF, Rb = 2.8 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 100 pF, Rb = 2.7 k 2.4 V VDD < 3.3 V, 1.6 V Vb 2.0 V, Cb = 100 pF, Rb = 5.5 k Hold time when SCLr = "H" tHIGH 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 100 pF, Rb = 2.8 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 100 pF, Rb = 2.7 k 2.4 V VDD < 3.3 V, 1.6 V Vb 2.0 V, Cb = 100 pF, Rb = 5.5 k Data setup time (reception) tSU:DAT 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 100 pF, Rb = 2.8 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 100 pF, Rb = 2.7 k 2.4 V VDD < 3.3 V, 1.6 V Vb 2.0 V, Cb = 100 pF, Rb = 5.5 k Data hold time (transmission) tHD:DAT 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, + 760 Note3 1/fMCK + 760 ns Note3 1/fMCK + 570 ns Note3 0 1420 ns 0 1420 ns 0 1215 ns Cb = 100 pF, Rb = 2.8 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 100 pF, Rb = 2.7 k 2.4 V VDD < 3.3 V, 1.6 V Vb 2.0 V, Cb = 100 pF, Rb = 5.5 k Notes 1. 2. The value must also be equal to or less than fMCK/4. Set tSU:DAT so that it will not exceed the hold time when SCLr = "L" or SCLr = "H". Cautions 1. Select the TTL input buffer and the N-ch open drain output (VDD tolerance) mode for the SDAr pin and the N-ch open drain output (VDD tolerance) mode for the SCLr pin by using port input mode register 1 (PIM1) and port output mode register 1 (POM1). For VIH and VIL, see the DC characteristics with TTL input buffer selected. 2. IIC01 and IIC11 cannot communicate at different potential. (Remarks are listed on the next page.) R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 92 of 106 RL78/G12 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) 2 Simplified I C mode connection diagram (during communication at different potential) Vb Vb Rb Rb SDA SDAr RL78 microcontroller User's device SCLr SCL 2 Simplified I C mode serial transfer timing (during communication at different potential) 1/f SCL t LOW t HIGH SCLr SDAr t HD : DAT Remarks 1. t SU : DAT Rb []: Communication line (SDAr, SCLr) pull-up resistance, Cb [F]: Communication line (SDAr, SCLr) load capacitance, Vb [V]: Communication line voltage 2. 3. r: IIC Number (r = 00, 20) fMCK: Serial array unit operation clock frequency (Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0,1), n: Channel number (n = 0)) R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 93 of 106 RL78/G12 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) 3.5.2 Serial interface IICA (TA = 40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) mode Standard Mode MIN. SCLA0 clock frequency fSCL Fast mode: fCLK 3.5 MHz Normal mode: fCLK 1 MHz Setup time of restart condition MAX. tSU:STA 0 Unit Fast Mode MIN. MAX. 0 400 100 kHz kHz 4.7 0.6 s tHD:STA 4.0 0.6 s Hold time when SCLA0 = "L" tLOW 4.7 1.3 s Hold time when SCLA0 = "H" tHIGH 4.0 0.6 s tSU:DAT 250 100 ns Data hold time (transmission) tHD:DAT 0 Setup time of stop condition tSU:STO 4.0 0.6 s Bus-free time tBUF 4.7 1.3 s Hold time Note 1 Data setup time (reception) Note 2 Notes 1. <R> 2. 3.45 0 0.9 s The first clock pulse is generated after this period when the start/restart condition is detected. The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK (acknowledge) timing. Caution Only in the 30-pin products, the values in the above table are applied even when bit 2 (PIOR2) in the peripheral I/O redirection register (PIOR) is 1. At this time, the pin characteristics (IOH1, IOL1, VOH1, VOL1) must satisfy the values in the redirect destination. Remark The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up resistor) at that time in each mode are as follows. Normal mode: Fast mode: Cb = 400 pF, Rb = 2.7 k Cb = 320 pF, Rb = 1.1 k IICA serial transfer timing t LOW tR SCLA0 tHD:DAT tHD:STA t HIGH tF tSU:STA tHD:STA tSU:STO tSU:DAT SDAA0 t BUF Stop condition Start condition R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Restart condition Stop condition Page 94 of 106 RL78/G12 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) 3.6 Analog Characteristics 3.6.1 A/D converter characteristics Classification of A/D converter characteristics Input channel Reference Voltage Reference voltage (+) = AVREFP Reference voltage (+) = VDD Reference voltage (+) = VBGR Reference voltage () = AVREFM Reference voltage () = VSS Reference voltage () = AVREFM ANI0 to ANI3 Refer to 29.6.1 (1). Refer to 29.6.1 (3). Refer to 29.6.1 (4). ANI16 to ANI22 Refer to 29.6.1 (2). Internal reference voltage Refer to 29.6.1 (1). Temperature sensor output voltage (1) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage () = AVREFM/ANI1 (ADREFM = 1), target pin: ANI2, ANI3, internal reference voltage, and temperature sensor output voltage (TA = 40 to +105C, 2.4 V AVREFP VDD 5.5 V, VSS = 0 V, Reference voltage (+) = AVREFP, Reference voltage () = AVREFM = 0 V) Parameter Symbol Resolution Conditions RES MIN. TYP. 8 MAX. Unit 10 bit 3.5 LSB Note 1 Overall error AINL 10-bit resolution Note 3 AVREFP = VDD Conversion time tCONV 10-bit resolution Target pin: ANI2, ANI3 3.6 V VDD 5.5 V 2.125 39 s 2.7 V VDD 5.5 V 3.1875 39 s 2.4 V VDD 5.5 V 17 39 s 10-bit resolution Target pin: Internal reference voltage, and temperature sensor output voltage (HS (high-speed main) mode) 3.6 V VDD 5.5 V 2.375 39 s 2.7 V VDD 5.5 V 3.5625 39 s 2.4 V VDD 5.5 V 17 39 s Notes 1, 2 Zero-scale error Full-scale error Notes 1, 2 Integral linearity error Note 1 Differential linearity error EZS 10-bit resolution Note 3 AVREFP = VDD 0.25 %FSR EFS 10-bit resolution Note 3 AVREFP = VDD 0.25 %FSR ILE 10-bit resolution Note 3 AVREFP = VDD 2.5 LSB DLE 10-bit resolution Note 3 AVREFP = VDD 1.5 LSB VAIN ANI2, ANI3 AVREFP V Note 1 Analog input voltage 1.2 Internal reference voltage (HS (high-speed main) mode) Temperature sensor output voltage (HS (high-speed main) mode) 0 VBGR Note 4 VTMPS25 Note 4 V V (Notes are listed on the next page.) R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 95 of 106 RL78/G12 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) Notes 1. Excludes quantization error (1/2 LSB). 2. This value is indicated as a ratio (%FSR) to the full-scale value. 3. When AVREFP < VDD, the MAX. values are as follows. Overall error: Add 1.0 LSB to the MAX. value when AVREFP = VDD. Zero-scale error/Full-scale error: Add 0.05%FSR to the MAX. value when AVREFP = VDD. Integral linearity error/ Differential linearity error: Add 0.5 LSB to the MAX. value when AVREFP = VDD. 4. Refer to 29.6.2 Temperature sensor/internal reference voltage characteristics. (2) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage () = AVREFM/ANI1 (ADREFM = 1), target pin: ANI16 to ANI22 (TA = 40 to +105C, 2.4 V AVREFP VDD 5.5 V, VSS = 0 V, Reference voltage (+) = AVREFP, Reference voltage () = AVREFM = 0 V) Parameter Symbol Resolution Conditions RES Overall error Note 1 AINL tCONV 10-bit resolution 1.2 Zero-scale error EZS Notes 1, 2 EFS Note 1 ILE error DLE Note 1 VAIN 5.0 LSB 2.125 39 s 39 s 17 39 s 0.35 %FSR 0.35 %FSR 3.5 LSB 2.0 LSB AVREFP V 10-bit resolution Note 3 10-bit resolution Note 3 10-bit resolution Note 3 10-bit resolution AVREFP = VDD Analog input voltage bit 3.1875 AVREFP = VDD Differential linearity 10 3.6 V VDD 5.5 V AVREFP = VDD Integral linearity error Unit Target ANI pin: ANI16 to ANI22 2.7 V VDD 5.5 V 10-bit resolution AVREFP = VDD Full-scale error MAX. Note 3 2.4 V VDD 5.5 V Notes 1, 2 TYP. 8 AVREFP = VDD Conversion time MIN. Note 3 ANI16 to ANI22 0 and VDD Notes 1. Excludes quantization error (1/2 LSB). 2. This value is indicated as a ratio (%FSR) to the full-scale value. 3. When AVREFP VDD, the MAX. values are as follows. Overall error: Add 4.0 LSB to the MAX. value when AVREFP = VDD. Zero-scale error/Full-scale error: Add 0.20%FSR to the MAX. value when AVREFP = VDD. Integral linearity error/ Differential linearity error: Add 2.0 LSB to the MAX. value when AVREFP = VDD. R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 96 of 106 RL78/G12 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) (3) When reference voltage (+) = VDD (ADREFP1 = 0, ADREFP0 = 0), reference voltage () = VSS (ADREFM = 0), target pin: ANI0 to ANI3, ANI16 to ANI22, internal reference voltage, and temperature sensor output voltage (TA = 40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V, Reference voltage (+) = VDD, Reference voltage () = VSS) Parameter Symbol Resolution Conditions RES MIN. TYP. 8 MAX. Unit 10 bit 7.0 LSB 39 s Note 1 Overall error AINL 10-bit resolution Conversion time tCONV 10-bit resolution 3.6 V VDD 5.5 V 2.125 Target pin: ANI0 to ANI3, 2.7 V VDD 5.5 V 3.1875 39 s 2.4 V VDD 5.5 V 17 39 s 3.6 V VDD 5.5 V 2.375 39 s Target pin: internal reference 2.7 V VDD 5.5 V voltage, and temperature 2.4 V VDD 5.5 V sensor output voltage (HS 3.5625 39 s 17 39 s ANI16 to ANI22 Conversion time tCONV 10-bit resolution 1.2 (high-speed main) mode) Notes 1, 2 Zero-scale error Full-scale error Notes 1, 2 Integral linearity error Note 1 Differential linearity error Analog input voltage Note 1 EZS 10-bit resolution 0.60 %FSR EFS 10-bit resolution 0.60 %FSR ILE 10-bit resolution 4.0 LSB DLE 10-bit resolution 2.0 LSB VAIN ANI0 to ANI3, ANI16 to ANI22 VDD V 0 Internal reference voltage VBGR Note 3 V (HS (high-speed main) mode) Temperature sensor output voltage VTMPS25 Note 3 V (HS (high-speed main) mode) Notes 1. Excludes quantization error (1/2 LSB). 2. This value is indicated as a ratio (%FSR) to the full-scale value. 3. Refer to 29.6.2 Temperature sensor/internal reference voltage characteristics. R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 97 of 106 RL78/G12 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) (4) When reference voltage (+) = Internal reference voltage (ADREFP1 = 1, ADREFP0 = 0), reference voltage () = AVREFM (ADREFM = 1), target pin: ANI0, ANI2, ANI3, and ANI16 to ANI22 (TA = 40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V, Reference voltage (+) = VBGR Note 3, Reference voltage () = AVREFM Note 4 = 0 V, HS (high-speed main) mode) Parameter Symbol Resolution Conditions MIN. RES Conversion time Notes 1, 2 Zero-scale error Integral linearity error Note 1 Differential linearity error Note 1 Analog input voltage TYP. MAX. 8 Unit bit 39 s 8-bit resolution 0.60 %FSR ILE 8-bit resolution 2.0 LSB DLE 8-bit resolution 1.0 LSB tCONV 8-bit resolution EZS VAIN 17 0 VBGR Note 3 V Notes 1. Excludes quantization error (1/2 LSB). 2. This value is indicated as a ratio (%FSR) to the full-scale value. 3. Refer to 29.6.2 Temperature sensor/internal reference voltage characteristics. 4. When reference voltage () = VSS, the MAX. values are as follows. Zero-scale error: Add 0.35%FSR to the MAX. value when reference voltage () = AVREFM. Integral linearity error: Add 0.5 LSB to the MAX. value when reference voltage () = AVREFM. Differential linearity error: Add 0.2 LSB to the MAX. value when reference voltage () = AVREFM. R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 98 of 106 RL78/G12 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) 3.6.2 Temperature sensor/internal reference voltage characteristics (TA = 40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V, HS (high-speed main) mode Parameter Symbol Temperature sensor output voltage VTMPS25 Conditions MIN. Setting ADS register = 80H, TYP. MAX. 1.05 Unit V TA = +25C Internal reference voltage VBGR Setting ADS register = 81H Temperature coefficient FVTMPS Temperature sensor output 1.38 1.45 1.50 3.6 V mV/C voltage that depends on the temperature Operation stabilization wait time tAMP s 5 3.6.3 POR circuit characteristics (TA = 40 to +105C, VSS = 0 V) Parameter Symbol Detection voltage Minimum pulse width Note Note Conditions MIN. TYP. MAX. Unit VPOR Power supply rise time 1.45 1.51 1.57 V VPDR Power supply fall time 1.44 1.50 1.56 V TPW s 300 Minimum time required for a POR reset when VDD exceeds below VPDR. This is also the minimum time required for a POR reset from when VDD exceeds below 0.7 V to when VDD exceeds VPOR while STOP mode is entered or the main system clock is stopped through setting bit 0 (HIOSTOP) and bit 7 (MSTOP) in the clock operation status control register (CSC). TPW Supply voltage (VDD) VPOR VPDR or 0.7 V R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 99 of 106 RL78/G12 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) 3.6.4 LVD circuit characteristics LVD Detection Voltage of Reset Mode and Interrupt Mode (TA = 40 to +105C, VPDR VDD 5.5 V, VSS = 0 V) Parameter Detection supply voltage Symbol VLVD0 VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 Minimum pulse width Detection delay time R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 tLW Conditions Power supply rise time MIN. TYP. MAX. Unit 3.90 4.06 4.22 V Power supply fall time 3.83 3.98 4.13 V Power supply rise time 3.60 3.75 3.90 V Power supply fall time 3.53 3.67 3.81 V Power supply rise time 3.01 3.13 3.25 V Power supply fall time 2.94 3.06 3.18 V Power supply rise time 2.90 3.02 3.14 V Power supply fall time 2.85 2.96 3.07 V Power supply rise time 2.81 2.92 3.03 V Power supply fall time 2.75 2.86 2.97 V Power supply rise time 2.70 2.81 2.92 V Power supply fall time 2.64 2.75 2.86 V Power supply rise time 2.61 2.71 2.81 V Power supply fall time 2.55 2.65 2.75 V Power supply rise time 2.51 2.61 2.71 V Power supply fall time 2.45 2.55 2.65 V s 300 300 s Page 100 of 106 RL78/G12 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) LVD detection voltage of interrupt & reset mode (TA = 40 to +105C, VPDR VDD 5.5 V, VSS = 0 V) Parameter Symbol Interrupt and reset VLVDD0 mode VLVDD1 Conditions MIN. TYP. MAX. Unit 2.64 2.75 2.86 V Rising reset release voltage 2.81 2.92 3.03 V Falling interrupt voltage 2.75 2.86 2.97 V Rising reset release voltage 2.90 3.02 3.14 V Falling interrupt voltage 2.85 2.96 3.07 V Rising reset release voltage 3.90 4.06 4.22 V Falling interrupt voltage 3.83 3.98 4.13 V VPOC2, VPOC1, VPOC1 = 0, 1, 1, falling reset voltage VLVDD2 VLVDD3 LVIS1, LVIS0 = 1, 0 LVIS1, LVIS0 = 0, 1 LVIS1, LVIS0 = 0, 0 3.6.5 Power supply voltage rising slope characteristics (TA = 40 to +105C, VSS = 0 V) Parameter Power supply voltage rising slope Caution Symbol Conditions SVDD MIN. TYP. MAX. Unit 54 V/ms Make sure to keep the internal reset state by the LVD circuit or an external reset until VDD reaches the operating voltage range shown in 29.4 AC Characteristics. R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 101 of 106 RL78/G12 <R> 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) 3.7 RAM Data Retention Characteristics (TA = 40 to +105C, VSS = 0 V) Parameter Data retention supply voltage <R> Note Symbol Conditions VDDDR MIN. 1.44 TYP. MAX. Unit 5.5 V Note This depends on the POR detection voltage. For a falling voltage, data in RAM are retained until the voltage reaches the level that triggers a POR reset but not once it reaches the level at which a POR reset is generated. Operation mode STOP mode RAM data retention VDD VDDDR STOP instruction execution Standby release signal (interrupt request) 3.8 Flash Memory Programming Characteristics (TA = 40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter <R> Symbol System clock frequency fCLK Code flash memory rewritable times Cerwr Conditions TYP. 1 Retained for 20 years Notes 1, 2, 3 TA = 85C Data flash memory rewritable times Retained for 1 year Notes 1, 2, 3 TA = 25C TA = 85C Unit 24 MHz Times 1,000,000 Notes 4 100,000 Notes 4 Retained for 20 years TA = 85C 1,000 MAX. Notes 4 Retained for 5 years Notes 1. MIN. 10,000 Notes 4 1 erase + 1 write after the erase is regarded as 1 rewrite. The retaining years are until next rewrite after the rewrite. 2. 3. When using flash memory programmer and Renesas Electronics self programming library These are the characteristics of the flash memory and the results obtained from reliability testing by Renesas Electronics Corporation. 4. This temperature is the average value at which data are retained. R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 102 of 106 RL78/G12 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C) 3.9 Dedicated Flash Memory Programmer Communication (UART) (TA = 40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Transfer rate Conditions MIN. During serial programming TYP. 115,200 MAX. Unit 1,000,000 bps 3.10 Timing of Entry to Flash Memory Programming Modes (TA = 40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Time to complete the communication for the initial tSUINIT Conditions MIN. POR and LVD reset are released TYP. MAX. Unit 100 ms before external release setting after the external reset is released Time to release the external reset after the TOOL0 POR and LVD reset are released tSU pin is set to the low level before external release Time to hold the TOOL0 pin at the low level after the tHD POR and LVD reset are released external reset is released before external release 10 s 1 ms (excluding the processing time of the firmware to control the flash memory) <1> <2> <4> <3> RESET tHD + software processing time 1-byte data for setting mode TOOL0 tSU tSUINIT <1> The low level is input to the TOOL0 pin. <2> The external reset is released (POR and LVD reset must be released before the external reset is released.). <3> The TOOL0 pin is set to the high level. <4> Setting of the flash memory programming mode by UART reception and complete the baud rate setting. Remark tSUINIT: Communication for the initial setting must be completed within 100 ms after the external reset is released during this period. tSU: Time to release the external reset after the TOOL0 pin is set to the low level tHD: Time to hold the TOOL0 pin at the low level after the external reset is released (excluding the processing time of the firmware to control the flash memory) R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 103 of 106 RL78/G12 4. PACKAGE DRAWINGS 4. PACKAGE DRAWINGS 4.1 20-pin products <R> R5F1026AASP, R5F10269ASP, R5F10268ASP, R5F10267ASP, R5F10266ASP R5F1036AASP, R5F10369ASP, R5F10368ASP, R5F10367ASP, R5F10366ASP R5F1026ADSP, R5F10269DSP, R5F10268DSP, R5F10267DSP, R5F10266DSP R5F1036ADSP, R5F10369DSP, R5F10368DSP, R5F10367DSP, R5F10366DSP R5F1026AGSP, R5F10269GSP, R5F10268GSP, R5F10267GSP, R5F10266GSP JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-LSSOP20-4.4x6.5-0.65 PLSP0020JB-A P20MA-65-NAA-1 0.1 2 D detail of lead end 11 20 E 1 c 10 1 L 3 bp A A2 A1 HE e y (UNIT:mm) NOTE 1.Dimensions " 2.Dimension " 1" and " 2" " does not include tr ITEM DIMENSIONS D E 6.50 0.10 4.40 0.10 HE 6.40 0.20 A 1.45 MAX. A1 0.10 0.10 A2 1.15 e bp c L y 0.65 0.12 0.22 0.10 0.05 0.15 0.05 0.02 0.50 0.20 0.10 0 to 10 2012 Renesas Electronics Corporation. All rights reserved. R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 104 of 106 RL78/G12 4. PACKAGE DRAWINGS 4.2 24-pin products <R> R5F1027AANA, R5F10279ANA, R5F10278ANA, R5F10277ANA R5F1037AANA, R5F10379ANA, R5F10378ANA, R5F10377ANA R5F1027ADNA, R5F10279DNA, R5F10278DNA, R5F10277DNA R5F1037ADNA, R5F10379DNA, R5F10378DNA, R5F10377DNA R5F1027AGNA, R5F10279GNA, R5F10278GNA, R5F10277GNA JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-HWQFN24-4x4-0.50 PWQN0024KE-A P24K8-50-CAB-1 0.04 D DETAIL OF A PART E S A A S y S (UNIT:mm) ITEM D2 A EXPOSED DIE PAD 1 6 D 4.00 0.05 E 4.00 0.05 A 0.75 0.05 b 0.25 0.05 0.07 e 7 24 Lp B DIMENSIONS 0.50 0.40 0.10 x 0.05 y 0.05 E2 ITEM 19 12 18 EXPOSED DIE PAD VARIATIONS 13 D2 E2 MIN NOM MAX MIN NOM MAX A 2.45 2.50 2.55 2.45 2.50 2.55 e Lp b x M S AB 2012 Renesas Electronics Corporation. All rights reserved. R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 105 of 106 RL78/G12 4. PACKAGE DRAWINGS 4.3 30-pin products <R> R5F102AAASP, R5F102A9ASP, R5F102A8ASP, R5F102A7ASP R5F103AAASP, R5F103A9ASP, R5F103A8ASP, R5F103A7ASP R5F102AADSP, R5F102A9DSP, R5F102A8DSP, R5F102A7DSP R5F103AADSP, R5F103A9DSP, R5F103A8DSP, R5F103A7DSP R5F102AAGSP, R5F102A9GSP, R5F102A8GSP, R5F102A7GSP JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-LSSOP30-0300-0.65 PLSP0030JB-B S30MC-65-5A4-3 0.18 30 16 detail of lead end F G T P 1 L 15 U E A H I J S C D N M S B M K ITEM A MILLIMETERS 9.85 0.15 B 0.45 MAX. C 0.65 (T.P.) NOTE D 0.24 0.08 0.07 Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition. E 0.1 0.05 F 1.3 0.1 G 1.2 H 8.1 0.2 I 6.1 0.2 J 1.0 0.2 K 0.17 0.03 L 0.5 M 0.13 N 0.10 P 3 T 0.25 U 0.6 0.15 5 3 2012 Renesas Electronics Corporation. All rights reserved. R01DS0193EJ0210 Rev.2.10 Mar 25, 2016 Page 106 of 106 Revision History RL78/G12 Data Sheet Description Rev. Date Page 1.00 Dec 10, 2012 - 2.00 Sep 06, 2013 1 Modification of 1.1 Features 3 Modification of 1.2 List of Part Numbers 4 Modification of Table 1-1. List of Ordering Part Numbers, Note, and Caution 7 to 9 Summary First Edition issued Modification of package name in 1.4.1 to 1.4.3 14 Modification of tables in 1.7 Outline of Functions 17 Modification of description of table in 2.1 Absolute Maximum Ratings (TA = 25C) 18 Modification of table, Note, and Caution in 2.2.1 X1 oscillator characteristics 18 Modification of table in 2.2.2 On-chip oscillator characteristics 19 Modification of Note 3 in 2.3.1 Pin characteristics (1/4) 20 Modification of Note 3 in 2.3.1 Pin characteristics (2/4) 23 Modification of Notes 1 and 2 in (1) 20-, 24-pin products (1/2) 24 Modification of Notes 1 and 3 in (1) 20-, 24-pin products (2/2) 25 Modification of Notes 1 and 2 in (2) 30-pin products (1/2) 26 Modification of Notes 1 and 3 in (2) 30-pin products (2/2) 27 Modification of (3) Peripheral functions (Common to all products) 28 Modification of table in 2.4 AC Characteristics 29 Addition of Minimum Instruction Execution Time during Main System Clock Operation 30 Modification of figures of AC Timing Test Point and External Main System Clock Timing 31 Modification of figure of AC Timing Test Point 31 Modification of description and Note 2 in (1) During communication at same potential (UART mode) 32 Modification of description in (2) During communication at same potential (CSI mode) 33 Modification of description in (3) During communication at same potential (CSI mode) 34 Modification of description in (4) During communication at same potential (CSI mode) 36 Modification of table and Note 2 in (5) During communication at same potential 2 (simplified I C mode) 38, 39 Modification of table and Notes 1 to 9 in (6) Communication at different potential 40 Modification of Remarks 1 to 3 in (6) Communication at different potential (1.8 V, (1.8 V, 2.5 V, 3 V) (UART mode) 2.5 V, 3 V) (UART mode) 41 Modification of table in (7) Communication at different potential (2.5 V, 3 V) (CSI mode) 42 Modification of Caution in (7) Communication at different potential (2.5 V, 3 V) (CSI mode) 43 Modification of table in (8) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (1/3) 44 Modification of table and Notes 1 and 2 in (8) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (2/3) 45 Modification of table, Note 1, and Caution 1 in (8) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (3/3) 47 Modification of table in (9) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) 50 Modification of table, Note 1, and Caution 1 in (10) Communication at different potential 2 (1.8 V, 2.5 V, 3 V) (simplified I C mode) 52 Modification of Remark in 2.5.2 Serial interface IICA 53 Addition of table to 2.6.1 A/D converter characteristics 53 Modification of description in 2.6.1 (1) 54 Modification of Notes 3 to 5 in 2.6.1 (1) 54 Modification of description and Notes 2 to 4 in 2.6.1 (2) C-1 Description Rev. Date Page 2.00 Sep 06, 2013 55 Modification of description and Notes 3 and 4 in 2.6.1 (3) 56 Modification of description and Notes 3 and 4 in 2.6.1 (4) 57 Modification of table in 2.6.2 Temperature sensor/internal reference voltage characteristics 57 Modification of table and Note in 2.6.3 POR circuit characteristics 58 Modification of table in 2.6.4 LVD circuit characteristics 59 Modification of table of LVD detection voltage of interrupt & reset mode 59 Modification of number and title to 2.6.5 Power supply voltage rising slope characteristics 61 Modification of table, figure, and Remark in 2.10 Timing of Entry to Flash Memory Summary Programming Modes 2.10 Mar 25, 2016 62 to 103 Addition of products of industrial applications (G: TA = -40 to +105C) 104 to 106 Addition of products of industrial applications (G: TA = -40 to +105C) 6 Modification of Figure 1-1 Part Number, Memory Size, and Package of RL78/G12 7 Modification of Table 1-1 List of Ordering Part Numbers 8 Addition of product name (RL78/G12) and description (Top View) in 1.4.1 20-pin products 9 Addition of product name (RL78/G12) and description (Top View) in 1.4.2 24-pin products 10 Addition of product name (RL78/G12) and description (Top View) in 1.4.3 30-pin products 15 Modification of description in 1.7 Outline of Functions 16 Modification of description, and addition of target products 52 Modification of note 2 in 2.5.2 Serial interface IICA 60 Modification of title and note, and addition of caution in 2.7 RAM Data Retention Characteristics 60 Modification of conditions in 2.8 Flash Memory Programming Characteristics 62 Modification of description, and addition of target products and remark 94 Modification of note 2 in 3.5.2 Serial interface IICA 102 Modification of title and note in 3.7 RAM Data Retention Characteristics 102 Modification of conditions in 3.8 Flash Memory Programming Characteristics 104 to 106 Addition of package name All trademarks and registered trademarks are the property of their respective owners. SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United States and Japan. Caution: This product uses SuperFlash(R) technology licensed from Silicon Storage Technology, Inc. C-2 NOTES FOR CMOS DEVICES (1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). (2) HANDLING OF UNUSED INPUT PINS: Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. (3) PRECAUTION AGAINST ESD: A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. (4) STATUS BEFORE INITIALIZATION: Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. (5) POWER ON/OFF SEQUENCE: In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. (6) INPUT OF SIGNAL DURING POWER OFF STATE : Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. Notice 1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 2. 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Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or systems manufactured by you. 8. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 9. Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. You should not use Renesas Electronics products or technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. 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