R5F1026AGSP#X0 - RENESAS TECHNOLOGY

Datasheet

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016 Page 1 of 106

R01DS0193EJ0210

Rev.2.10

Mar 25, 2016

RL78/G12

RENESAS MCU

True Low Power Platform (as low as 63 μA/MHz), 1.8V to 5.5V operation,

2 to 16 Kbyte Flash, 31 DMIPS at 24MHz, for General Purpose Applications

1. OUTLINE

1.1 Features

Ultra-low power consumption technology

 V

DD = single power supply voltage of 1.8 to 5.5 V which

can operate at a low voltage

 HALT mode

 STOP mode

 SNOOZE mode

RL78 CPU core

 CISC architecture with 3-stage pipeline

 Minimum instruction execution time: Can be changed

from high speed (0.04167 s: @ 24 MHz operation with

high-speed on-chip oscillator) to ultra-low speed (1 s:

@ 1 MHz operation)

 Address space: 1 MB

 General-purpose registers: (8-bit register x 8) x 4 banks

 On-chip RAM: 256 B to 2 KB

Code flash memory

 Code flash memory: 2 to 16 KB

 Block size: 1 KB

 Prohibition of block erase and rewriting (security

function)

 On-chip debug function

 Self-programming (with flash shield window function)

Data flash memory Note

 Data flash memory: 2 KB

 Back ground operation (BGO): Instructions are

executed from the program memory while rewriting the

data flash memory.

 Number of rewrites: 1,000,000 times (TYP.)

 Voltage of rewrites: VDD = 1.8 to 5.5 V

High-speed on-chip oscillator

 Select from 24 MHz, 16 MHz, 12 MHz, 8 MHz, 6 MHz,

4 MHz, 3 MHz, 2 MHz, and 1 MHz

 High accuracy: +/- 1.0 % (VDD = 1.8 to 5.5 V, TA = -20

to +85 °C)

Operating ambient temp eratu re

 T

A = -40 to +85 °C (A: Consumer applications, D:

Industrial applications)

 T

A = -40 to +105 °C (G: Industrial applications) Note

Power management and reset function

 On-chip power-on-reset (POR) circuit

 On-chip voltage detector (LVD) (Select interrupt and

reset from 12 levels)

DMA (Direct Memory Access) cont roller Note

 2 channels

 Number of clocks during transfer between 8/16-bit SFR

and internal RAM: 2 clocks

Multiplier and divider/multiply-accumulator

 16 bits x 16 bits = 32 bits (Unsigned or signed)

 32 bits x 32 bits = 32 bits (Unsigned)

 16 bits x 16 bits + 32 bits = 32 bits (Unsigned or

signed)

Serial interface

 CSI : 1 to 3 channels

 UART : 1 to 3 channels

 Simplified I2C communication : 0 to 3 channels

 I

2C communication : 1 channel

Timer

 16-bit timer : 4 to 8 channels

 12-bit interval timer : 1 channel

 Watchdog timer : 1 channel (operable with the

dedicated low-speed on-chip

oscillator)

A/D converter

 8/10-bit resolution A/D converter (VDD = 1.8 to 5.5 V)

 8 to 11 channels, internal reference voltage (1.45 V),

and temperature sensor Note

I/O port

 I/O port: 18 to 26

(N-ch open drain I/O [withstand voltage of 6 V]: 2,

N-ch open drain I/O [VDD withstand voltage]: 4 to 9)

 Can be set to N-ch open drain, TTL input buffer, and

on-chip pull-up resistor

 Different potential interface: Can connect to a 1.8/2.5/3

V device

 On-chip key interrupt function

 On-chip clock output/buzzer output controller

Others

 On-chip BCD (binary-coded decimal) correction circuit

Note Can be selected only in HS (high-speed main) mode.

Remark The functions mounted depend on the product.

See 1.7 Outline of Functions.

* There is difference in specifications between every product.

Please refer to specification for details.

RL78/G12 1. OUTLINE

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016

Page 2 of 106

 ROM, RAM capacities

Code flash Data flash RAM 20 pins 24 pins 30 pins

2 KB   R5F102AA



2 KB

  R5F103AA

2 KB R5F1026A Note 1 R5F1027A Note 1 

16 KB



1.5 KB

R5F1036A Note 1 R5F1037A

Note 1 

2KB R5F10269

Note 1 R5F10279

Note 1 R5F102A9 12 KB



1 KB

R5F10369 Note 1 R5F10379

Note 1 R5F103A9

2 KB R5F10268 Note 1 R5F10278

Note 1 R5F102A8 8 KB



768 B

R5F10368 Note 1 R5F10378

Note 1 R5F103A8

2KB R5F10267 R5F10277 R5F102A7 4 KB



512 B

R5F10367 R5F10377 R5F103A7

2 KB R5F10266 Note 2  

2 KB



256 B

R5F10366 Note 2  

Notes 1. This is 640 bytes when the self-programming function or data flash function is used. (For details, see

CHAPTER 3 CPU ARCHITECTURE.)

2. The self-programming function cannot be used for R5F10266 and R5F10366.

Caution When the flash memory is rewritten via a user program, the code flash area and RAM area are used

because each library is used. When using the library, refer to RL78 Family Flash Self Programming Library

Type01 User's Manual and RL78 Family Data Flash Library Type04 User's Manual.

RL78/G12 1. OUTLINE

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016

Page 3 of 106

1.2 List of Part Numbers

Figure 1-1. Part Number, Memory Size, and Package of RL78/G12

Part No. R 5 F 1 0 2 A A A x x x S P #V0

Package type:

ROM number (Omitted with blank products)

ROM capacity:

RL78/G12 group

Renesas MCU

Renesas semiconductor product

: LSSOP, 0.65 mm pitch

NA : HWQFN, 0.50 mm pitch

#U5

#V0, #V5

#W5

#X0, #X5

: 2 KB

: 4 KB

: 8 KB

: 12 KB

: 16 KB

Pin count:

: 20-pin

: 24-pin

: 30-pin

Classification:

A : Consumer applications, TA = -40°C to +85°C

D : Industrial applications, TA = -40°C to +85°C

G : Industrial applications, TA = -40°C to +105°C

Memory type:

F : Flash memory

Packaging specifications:

102

Note 1

103

Notes 1, 2

: Tray (HWQFN)

: Tray (LSSOP30), Tube (LSSOP20)

: Embossed Tape (HWQFN)

: Embossed Tape (LSSOP30, LSSOP20)

Notes 1. For details about the differences between the R5F102 products and the R5F103 products of RL78/G12,

see 1.1 Differences between the R5F102 Products and the R5F103 Products.

2. Products only for "A: Consumer applications (TA = -40 to +85C)" and "D: Industrial applications (TA = -40 to

+85C)"

<R>

RL78/G12 1. OUTLINE

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016

Page 4 of 106

Table 1-1. List of Ordering Part Numbers

count

Package Data flash

Fields of

Application

Part Number

A R5F1026AASP#V5, R5F10269ASP#V5, R5F10268ASP#V5, R5F10267ASP#V5,

R5F10266ASP#V5

R5F1026AASP#X5, R5F10269ASP#X5, R5F10268ASP#X5, R5F10267ASP#X5,

R5F10266ASP#X5

D R5F1026ADSP#V5, R5F10269DSP#V5, R5F10268DSP#V5, R5F10267DSP#V5,

R5F10266DSP#V5

R5F1026ADSP#X5, R5F10269DSP#X5, R5F10268DSP#X5, R5F10267DSP#X5,

R5F10266DSP#X5

Mounted

G R5F1026AGSP#V5, R5F10269GSP#V5, R5F10268GSP#V5, R5F10267GSP#V5,

R5F10266GSP#V5

R5F1026AGSP#X5, R5F10269GSP#X5, R5F10268GSP#X5, R5F10267GSP#X5,

R5F10266GSP#X5

A R5F1036AASP#V5, R5F10369ASP#V5, R5F10368ASP#V5, R5F10367ASP#V5,

R5F10366ASP#V5

R5F1036AASP#X5, R5F10369ASP#X5, R5F10368ASP#X5, R5F10367ASP#X5,

R5F10366ASP#X5

pins

20-pin plastic

LSSOP

(4.4  6.5 mm,

0.65 mm pitch)

Not mounted

D R5F1036ADSP#V5, R5F10369DSP#V5, R5F10368DSP#V5, R5F10367DSP#V5,

R5F10366DSP#V5

R5F1036ADSP#X5, R5F10369DSP#X5, R5F10368DSP#X5, R5F10367DSP#X5,

R5F10366DSP#X5

A R5F1027AANA#U5, R5F10279ANA#U5, R5F10278ANA#U5, R5F10277ANA#U5

R5F1027AANA#W5, R5F10279ANA#W5, R5F10278ANA#W5,

R5F10277ANA#W5

D R5F1027ADNA#U5, R5F10279DNA#U5, R5F10278DNA#U5, R5F10277DNA#U5

R5F1027ADNA#W5, R5F10279DNA#W5, R5F10278DNA#W5,

R5F10277DNA#W5

Mounted

G R5F1027AGNA#U5, R5F10279GNA#U5, R5F10278GNA#U5,

R5F10277GNA#U5

R5F1027AGNA#W5, R5F10279GNA#W5, R5F10278GNA#W5,

R5F10277GNA#W5

A R5F1037AANA#V5, R5F10379ANA#V5, R5F10378ANA#V5, R5F10377ANA#V5

R5F1037AANA#X5, R5F10379ANA#X5, R5F10378ANA#X5, R5F10377ANA#X5

pins

24-pin plastic

HWQFN

(4  4 mm, 0.5

mm pitch)

Not mounted

D R5F1037ADNA#V5, R5F10379DNA#V5, R5F10378DNA#V5, R5F10377DNA#V5

R5F1037ADNA#X5, R5F10379DNA#X5, R5F10378DNA#X5, R5F10377DNA#X5

A R5F102AAASP#V0, R5F102A9ASP#V0, R5F102A8ASP#V0, R5F102A7ASP#V0

R5F102AAASP#X0, R5F102A9ASP#X0, R5F102A8ASP#X0, R5F102A7ASP#X0

D R5F102AADSP#V0, R5F102A9DSP#V0, R5F102A8DSP#V0, R5F102A7DSP#V0

R5F102AADSP#X0, R5F102A9DSP#X0, R5F102A8DSP#X0, R5F102A7DSP#X0

Mounted

G R5F102AAGSP#V0, R5F102A9GSP#V0, R5F102A8GSP#V0,

R5F102A7GSP#V0

R5F102AAGSP#X0, R5F102A9GSP#X0, R5F102A8GSP#X0,

R5F102A7GSP#X0

A R5F103AAASP#V0, R5F103A9ASP#V0, R5F103A8ASP#V0, R5F103A7ASP#V0

R5F103AAASP#X0, R5F103A9ASP#X0, R5F103A8ASP#X0, R5F103A7ASP#X0

pins

30-pin plastic

LSSOP

(7.62 mm

(300), 0.65 mm

pitch )

Not mounted

D R5F103AADSP#V0, R5F103A9DSP#V0, R5F103A8DSP#V0, R5F103A7DSP#V0

R5F103AADSP#X0, R5F103A9DSP#X0, R5F103A8DSP#X0, R5F103A7DSP#X0

Note For fields of application, see Figure 1-1 Part Number, Memory Size, and Package of RL78/G12.

Caution The ordering part numbers represent the numbers at the time of publication. For the latest ordering part

numbers, refer to the target product page of the Renesas Electronics website.

<R>

RL78/G12 1. OUTLINE

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016

Page 5 of 106

1.3 Differences between the R5F102 Products and the R5F103 Products

The following are differences between the R5F102 products and the R5F103 products.

 Whether the data flash memory is mounted or not

 High-speed on-chip oscillator oscillation frequency accuracy

 Number of channels in serial interface

 Whether the DMA function is mounted or not

 Whether a part of the safety functions are mounted or not

1.3.1 Data Flash

The data flash memory of 2 KB is mounted on the R5F102 products, but not on the R5F103 products.

Product Data Flash

R5F102 products

R5F1026A, R5F1027A, R5F102AA,

R5F10269, R5F10279, R5F102A9,

R5F10268, R5F10278, R5F102A8,

R5F10267, R5F10277, R5F102A7,

R5F10266 Note

2KB

R5F103 products

R5F1036A, R5F1037A, R5F103AA,

R5F10369, R5F10379, R5F103A9,

R5F10368, R5F10378 R5F103A8,

R5F10367, R5F10377, R5F103A7,

R5F10366

Not mounted

Note The RAM in the R5F10266 has capacity as small as 256 bytes. Depending on the customer's program

specification, the stack area to execute the data flash library may not be kept and data may not be written to or

erased from the data flash memory.

Caution When the flash memory is rewritten via a user program, the code flash area and RAM area are used

because each library is used. When using the library, refer to RL78 Family Flash Self Programming Library

Type01 User's Manual and RL78 Family Data Flash Library Type04 User's Manual.

RL78/G12 1. OUTLINE

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016

Page 6 of 106

1.3.2 On-chip oscillator characteristics

(1) High-speed on-chip oscillator oscillation frequency of the R5F102 products

Oscillator Condition MIN MAX Unit

TA = -20 to +85 C -1.0 +1.0

TA = -40 to -20 C -1.5 +1.5

High-speed on-chip

oscillator oscillation

frequency accuracy TA = +85 to +105 C -2.0 +2.0

(2) High-speed on-chip oscillator oscillation frequency of the R5F103 products

Oscillator Condition MIN MAX Unit

High-speed on-chip

oscillator oscillation

frequency accuracy

TA = -40 to + 85 C -5.0 +5.0 %

1.3.3 Peripheral Functions

The following are differences in peripheral functions between the R5F102 products and the R5F103 products.

R5F102 product R5F103 product

RL78/G12 20, 24 pin

product

30 pin product 20, 24 pin

product

30 pin

product

UART 1 channel 3 channels 1 channel

CSI 2 channels 3 channels 1 channel

Serial interface

Simplified I2C 2 channels 3 channels None

DMA function 2 channels None

CRC operation Yes None

RAM guard Yes None

Safety function

SFR guard Yes None

RL78/G12 1. OUTLINE

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016

Page 7 of 106

1.4 Pin Configuration (Top View)

1.4.1 20-pin products

 20-pin plastic LSSOP (4.4  6.5 mm, 0.65 mm pitch)

P21/ANI1/AV

REFM

P22/ANI2

P23/ANI3

P10/ANI16/PCLBUZ0/SCK00/SCL00

P11/ANI17/SI00/RxD0/SDA00 /TOOLRxD

P12/ANI18/SO00/TxD0/TOOLTxD

P13/ANI19/TI00/TO00/INTP2

P14/ANI20/TI01/TO01/INTP3

P61/KR5/SDAA0/(RxD0)

P60/KR4/SCLA0/(TxD0)

P20/ANI0/AV

REFP

P40/KR0/TOOL0

P137/INTP0

P122/KR2/X2/EXCLK/(TI02)/(INTP2)

P121/KR3/X1/(TI03)/(INTP3)

P42/ANI21/SCK01 /SCL01

NoteNote

/TI03/TO03

P41/ANI22/SO01 /SDA01

NoteNote

/TI02/TO02/INTP1

P125/KR1/SI01 /RESET

Note

RL78/G12

(Top View)

Note Provided only in the R5F102 products.

Remarks 1. For pin identification, see 1.5 Pin Identification.

2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection

<R>

RL78/G12 1. OUTLINE

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016

Page 8 of 106

1.4.2 24-pin products

 24-pin plastic HWQFN (4  4 mm, 0.5 mm pitch)

1 2 3 4 5 6

18 17 16 15 14 13

P61/KR5/SDAA0/(RxD0)

P60/KR4/SCLA0/(TxD0)

P03/KR9

P02/KR8/(SCK01)

Note

/(SCL01)

Note

P01/KR7/(SO01)

Note

/(SDA01)

Note

P00/KR6/(SI01)

Note

P22/ANI2

P21/ANI1/AV

REFM

P20/ANI0/AV

REFP

P42/ANI21/SCK01

Note

/SCL01

Note

/TI03/TO03

P41/ANI22/SO01

Note

/SDA01

Note

/TI02/TO02/INTP1

P40/KR0/TOOL0

INDEX MARK

exposed die pad

P122/KR2/X2/EXCLK/(TI02)/(INTP2)

P121/KR3/X1/(TI03)/(INTP3)

P137/INTP0

P125/KR1/SI01

Note

/RESET

P14/ANI20/TO01/INTP3

P13/ANI19/TO00/INTP2

P11/ANI17/SI00/RxD0/SDA00

Note

/TOOLRxD

P12/ANI18/SO00/TxD0/TOOLTxD

P10/ANI16/PCLBUZ0/SCK00/SCL00

Note

P23/ANI3

RL78/G12

(Top View)

Note Provided only in the R5F102 products.

Remarks 1. For pin identification, see 1.5 Pin Identification.

2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection

3. It is recommended to connect an exposed die pad to Vss.

<R>

RL78/G12 1. OUTLINE

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016

Page 9 of 106

1.4.3 30-pin products

 30-pin plastic LSSOP (7.62 mm (300), 0.65 mm pitch)

P20/ANI0/AV

REFP

P01/ANI16/TO00/RxD1

Note

P00/ANI17/TI00/TxD1

Note

P120/ANI19

P40/TOOL0

RESET

P137/INTP0

P122/X2/EXCLK

P121/X1

REGC

P60/SCLA0

P61/SDAA0

P31/TI03/TO03/INTP4/PCLBUZ0

P21/ANI1/AV

REFM

P22/ANI2

P23/ANI3

P147/ANI18

P10/SCK00/SCL00

Note

/(TI07/TO07)

P11/SI00/RxD0/TOOLRxD/SDA00

Note

/(TI06/TO06)

P13/TxD2

Note

/SO20

Note

/(SDAA0)

Note

/(TI04/TO04)

P14/RxD2

Note

/SI20

Note

/SDA20

Note

/(SCLA0)

Note

/(TI03/TO03)

P15/PCLBUZ1/SCK20

Note

/SCL20

Note

/(TI02/TO02)

P12/SO00/TxD0/TOOLTxD/(TI05/TO05)

P16/TI01/TO01/INTP5/(RxD0)

P17/TI02/TO02/(TxD0)

P30/INTP3/SCK11

Note

/SCL11

Note

P50/INTP1/SI11

Note

/SDA11

Note

P51/INTP2/SO11

Note

RL78/G12

(Top View)

Note Provided only in the R5F102 products.

Caution Connect the REGC pin to VSS via capacitor (0.47 to 1



F).

Remarks 1. For pin identification, see 1.5 Pin Identification.

2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection

<R>

RL78/G12 1. OUTLINE

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016

Page 10 of 106

1.5 Pin Identification

ANI0 to ANI3,

ANI16 to ANI22:

Analog input

REGC:

RESET:

Regulator Capacitance

Reset

AVREFM: Analog Reference Voltage Minus

AVREFP: Analog reference voltage plus

RxD0 to RxD2:

SCK00, SCK01, SCK11,

Receive Data

EXCLK: External Clock Input

(Main System Clock)

SCK20:

SCL00, SCL01,

Serial Clock Input/Output

INTP0 to INTP5 Interrupt Request From Peripheral

KR0 to KR9: Key Return

SCL11, SCL20, SCLA0:

SDA00, SDA01, SDA11,

Serial Clock Input/Output

P00 to P03: Port 0 SDA20, SDAA0: Serial Data Input/Output

P10 to P17: Port 1 SI00, SI01, SI11, SI20: Serial Data Input

P20 to P23: Port 2 SO00, SO01, SO11,

P30 to P31: Port 3 SO20: Serial Data Output

P40 to P42: Port 4 TI00 to TI07: Timer Input

P50, P51: Port 5 TO00 to TO07: Timer Output

P60, P61: Port 6 TOOL0: Data Input/Output for Tool

P120 to P122, P125: Port 12

P137: Port 13

TOOLRxD, TOOLTxD: Data Input/Output for External

Device

P147: Port 14 TxD0 to TxD2: Transmit Data

DD: Power supply

SS: Ground

PCLBUZ0, PCLBUZ1: Programmable Clock Output/

Buzzer Output

X1, X2: Crystal Oscillator (Main System

Clock)

RL78/G12 1. OUTLINE

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016

Page 11 of 106

1.6 Block Diagram

1.6.1 20-pin products

PORT 1 P10 to P14

PORT 2 P20 to P23

PORT 4 P40 to P42

PORT 6

PORT 12

CRCNote

PCLBUZ0

P60, P61

P121, P122, P125

RESET

Low Speed

On-chip

oscillator

15 kHz

KR0 to KR5

INTP0 to INTP3

ANI2, ANI3, ANI16 to ANI22

ANI0/AVREFP

ANI1/AVREFM

PORT 13 P137

Multiplier & divider

multiply-

accumulator

On-chip debug

BCD adjustment

IICA0

TOOL0

SCLA0

SDAA0

Power-on

reset/voltage

detector

Clock Generator

Reset Generator

High-Speed

on-chip oscillator

1 to 24 MHz

TOOL

TxD

TOOL

RxD

RL78

CPU

core

Buzzer/clock

output control

Key return

6ch

Interrupt control

4ch

Window watchdog

timer

12-bit Intervaltimer

10-bit A/D converter

11ch

RAM

1.5 KB

Interrupt control

DMANote

2ch

Code flash: 16 KB

Data flash: 2 KBNote

SAU0 (2ch)

UART0

CSI00

CSI01Note

IIC00Note

IIC01Note

TI00/TO00

TAU0 (4ch)

ch00

ch01

ch02

ch03

TI01/TO01

TI02/TO02

TI03/TO03

RxD0

TxD0

SCK00

SI00

SO00

SCK01

SI01

SO01

SCL00

SDA00

SCL01

SDA01

Main OSC

1 to 20 MHz

VDD VSS

X1 X2/EXCLK

Note Provided only in the R5F102 products.

RL78/G12 1. OUTLINE

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016

Page 12 of 106

1.6.2 24-pin products

Code flash: 16 KB

Data flash: 2 KBNote

TAU0 (4ch)

ch01

ch00

Interrupt control

RL78

CPU

core

Low Speed

On-chip

oscillator

15 KHz

DMANote

2ch

RAM

1.5 KB

Poer-on

reset/voltage

detector

High-Speed

On-chip

oscillator

1 to 24 MHz

Clock Generator

Reset Generator

ch02

ch03

UART0

SAU0 (2ch)

CSI00

IICA0

On-chip debug

Multiplier &

divider/

multiply-

accumulator

BCD adjustment

CSI01Note

IIC00Note

IIC01Note

TI00/TO00

TI01/TO01

TI02/TO02

TI03/TO03

RxD0

TxD0

SCK00

SI00

SO00

SCK01

SI01

SO01

SCL00

SDA00

SCL01

SDA01

SCLA0

SDAA0

TOOL0

VDD VSS

Port 0 P00 to P03

P10 to P14

P20 to P23

P40 to P42

P60, P61

P137

PCLBUZ0

KR0 to KR9

INTP0 to INTP3

ANI2, ANI3, ANI16 to ANI22

10-bit

A/D converter

11ch

12-bit Interval timer

Window watchdog

timer

CRCNote

ANI0/AVREFP

ANI1/AVREFM

P121, P122, 125

Port 1

Port 2

Port 4

Port 6

Port 12

Key return

10ch

Interrupt control

4ch

Buzzer/clock

output control

Port 13

RESET

Main OSC

1to 20 MHz

X1 X2/EXCLK

TOOL

TxD

TOOL

RxD

IICA0

Note Provided only in the R5F102 products.

RL78/G12 1. OUTLINE

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016

Page 13 of 106

1.6.3 30-pin products

VOLTAGE

REGULATOR REGC

ANI0/AV

REFP

ANI1/AV

REFM

ANI2, ANI3,

ANI16 to ANI19

TAU (8ch)

TI00

TO00

RxD0

TxD0

RxD2

TxD2

TOOL0

IICA0

On-chip debug

BCD adjustment

SCLA0

SDAA0

SCL20

SDA20

SCK20

SI20

SO20

SCL00

SDA00

SCL11

SDA11

RxD1

TxD1

SCK00

SI00

SO00

SCK11

SI11

SO11

TI01/TO01

TI02/TO02

TI03/TO03

(TI04/TO04)

(TI05/TO05)

(TI06/TO06)

(TI07/TO07)

ch0

ch1

ch2

ch3

ch4

ch5

ch6

ch7

SAU0 (4ch)

SAU0 (2ch)

Note

UART2

CSI20

IIC20

UART0

UART1

Note

CSI00

CSI11

Note

IIC00

Note

IIC11

Note

Low Speed

On-chip

oscillator

15 KHz

P00, P01

P10 to P17

P20 to P23

P30, P31

P40

P50, P51

P60, P61

P120

P121, P122

P137

P147

PCLBUZ0, PCLBUZ1

INTP0 to INTP5

Port 1

Port 0

Port 2

Port 3

Port 4

Port 5

Port 6

Port 12

Port 13

Port 14

Multiplier &

divider/

multiply-

accumulator

Code flash: 16 KB

Data flash: 2 KB

Note

Interrupt control

RL78

CPU

core

DMA

Note

2ch

RAM

2 KB

Poer-on

reset/voltage

detector

High-Speed

On-chip

oscillator

1 to 24 MHz

Clock Generator

Reset Generator

RESET

Main OSC

1 to 20 MHz

X1 X2/EXCLK

TOOL

TxD

TOOL

RxD

10-bit

A/D converter

8ch

12-bit Interval timer

Window watchdog

timer

CRC

Note

Interrupt control

6ch

Buzzer/clock

output control

Note Provided only in the R5F102 products.

Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection

RL78/G12 1. OUTLINE

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016

Page 14 of 106

1.7 Outline of Functions

This outline describes the function at the time when Peripheral I/O redirection register (PIOR) is set to 00H.

(1/2)

20-pin 24-pin 30-pin Item

R5F1026x R5F1036x R5F1027x R5F1037x R5F102Ax R5F103Ax

Code flash memory 2 to 16 KB Note 1 4 to 16 KB

Data flash memory 2 KB  2 KB  2 KB 

RAM 256 B to 1.5 KB 512 B to 1.5 KB 512 B to 2KB

Address space 1 MB

High-speed system clock X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK)

HS (High-speed main) mode : 1 to 20 MHz (VDD = 2.7 to 5.5 V),

HS (High-speed main) mode : 1 to 16 MHz (VDD = 2.4 to 5.5 V),

LS (Low-speed main) mode : 1 to 8 MHz (VDD = 1.8 to 5.5 V)

Main

system

clock

High-speed on-chip

oscillator clock

HS (High-speed main) mode : 1 to 24 MHz (VDD = 2.7 to 5.5 V),

HS (High-speed main) mode : 1 to 16 MHz (VDD = 2.4 to 5.5 V),

LS (Low-speed main) mode : 1 to 8 MHz (VDD = 1.8 to 5.5 V)

Low-speed on-chip oscillator clock 15 kHz (TYP)

General-purpose register (8-bit register  8)  4 banks

0.04167



s (High-speed on-chip oscillator clock: fIH = 24 MHz operation) Minimum instruction execution time

0.05



s (High-speed system clock: fMX = 20 MHz operation)

Instruction set  Data transfer (8/16 bits)

 Adder and subtractor/logical operation (8/16 bits)

 Multiplication (8 bits  8 bits)

 Rotate, barrel shift, and bit manipulation (set, reset, test, and Boolean operation), etc.

Total 18 22 26

CMOS I/O 12

(N-ch O.D. I/O

[VDD withstand voltage]: 4)

(N-ch O.D. I/O

[VDD withstand voltage]: 5)

(N-ch O.D. I/O

[VDD withstand voltage]: 9)

CMOS input 4 4 3

I/O port

N-ch open-drain I/O

(6 V tolerance)

16-bit timer 4 channels 8 channels

Watchdog timer 1 channel

12-bit Interval timer 1 channel

Timer

Timer output 4 channels

(PWM outputs: 3 Note 3)

8 channels

(PWM outputs: 7 Note 3)Note 2

Notes 1. The self-programming function cannot be used in the R5F10266 and R5F10366.

2. The maximum number of channels when PIOR0 is set to 1.

3. The number of PWM outputs varies depending on the setting of channels in use (the number of masters and

slaves). (See 6.9.3 Operation as multiple PWM output function.)

Caution When the flash memory is rewritten via a user program, the code flash area and RAM area are used because

each library is used. When using the library, refer to RL78 Family Flash Self Programming Library Type01

User's Manual and RL78 Family Data Flash Library Type04 User's Manual.

<R>

RL78/G12 1. OUTLINE

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016

Page 15 of 106

(2/2)

20-pin 24-pin 30-pin Item

R5F1026x R5F1036x R5F1027x R5F1037x R5F102Ax R5F103Ax

1 2 Clock output/buzzer output

2.44 kHz to 10 MHz: (Peripheral hardware clock: fMAIN = 20 MHz operation)

8/10-bit resolution A/D converter 11 channels 8 channels

Serial interface [R5F1026x (20-pin), R5F1027x (24-pin)]

 CSI: 2 channels/Simplified I2C: 2 channels/UART: 1 channel

[R5F102Ax (30-pin)]

 CSI: 1 channel/Simplified I2C: 1 channel/UART: 1 channel

[R5F1036x (20-pin), R5F1037x (24-pin)]

 CSI: 1 channel/Simplified I2C: 0 channel/UART: 1 channel

[R5F103Ax (30-pin)]

 CSI: 1 channel/Simplified I2C: 0 channel/UART: 1 channel

2C bus 1 channel

Multiplier and divider/multiply-

accumulator

 16 bits  16 bits = 32 bits (unsigned or signed)

 32 bits  32 bits = 32 bits (unsigned)

 16 bits  16 bits + 32 bits = 32 bits (unsigned or signed)

DMA controller 2 channels  2 channels  2 channels 

Internal 18 16 18 16 26 19

Vectored interrupt

sources External 5 6

Key interrupt 6 10 

Reset  Reset by RESET pin

 Internal reset by watchdog timer

 Internal reset by power-on-reset

 Internal reset by voltage detector

 Internal reset by illegal instruction execution Note

 Internal reset by RAM parity error

 Internal reset by illegal-memory access

Power-on-reset circuit  Power-on-reset: 1.51 V (TYP)

 Power-down-reset: 1.50 V (TYP)

Voltage detector  Rising edge : 1.88 to 4.06 V (12 stages)

 Falling edge : 1.84 to 3.98 V (12 stages)

On-chip debug function Provided

Power supply voltage VDD = 1.8 to 5.5 V

Operating ambient temperature TA = 40 to +85C (A: Consumer applications, D: Industrial applications), TA = 40 to +105C

(G: Industrial applications)

Note The illegal instruction is generated when instruction code FFH is executed.

Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip debug

emulator.

RL78/G12 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C)

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016

Page 16 of 106

2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C)

This chapter describes the following electrical specifications.

Target products A: Consumer applications TA = -40 to +85°C

R5F102xxAxx, R5F103xxAxx

D: Industrial applications TA = -40 to +85C

R5F102xxDxx, R5F103xxDxx

G: Industrial applications when TA = -40 to +105°C products is used in the range of TA = -40 to +85°C

R5F102xxGxx

Cautions 1. The RL78 microcontrollers have an on-chip debug function, which is provided for development and

evaluation. Do not use the on-chip debug function in products designated for mass production, because the

guaranteed number of rewritable times of the flash memory may be exceeded when this function is used,

and product reliability therefore cannot be guaranteed. Renesas Electronics is not liable for problems

occurring when the on-chip debug function is used.

2. The pins mounted depend on the product. Refer to 2.1 Port Functions to 2.2.1 Functions for each product.

<R>

RL78/G12 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C)

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016

Page 17 of 106

2.1 Absolute Maximum Ratings

Absolute Maximum Ratings (TA = 25C)

Parameter Symbols Conditions Ratings Unit

Supply Voltage VDD 0.5 to + 6.5 V

REGC terminal input

voltageNote1

VIREGC REGC 0.3 to +2.8

and 0.3 to VDD + 0.3

Note 2

VI1 Other than P60, P61 0.3 to VDD + 0.3Note 3 V Input Voltage

VI2 P60, P61 (N-ch open drain) 0.3 to 6.5 V

Output Voltage VO 0.3 to VDD + 0.3Note 3 V

Analog input voltage VAI 20-, 24-pin products: ANI0 to ANI3, ANI16 to ANI22

30-pin products: ANI0 to ANI3, ANI16 to ANI19

0.3 to VDD + 0.3

and 0.3 to

AVREF(+)+0.3 Notes 3, 4

Per pin Other than P20 to P23 40 mA

All the terminals other than P20 to P23 170 mA

20-, 24-pin products: P40 to P42

30-pin products: P00, P01, P40, P120

70 mA

IOH1

Total of all pins

20-, 24-pin products: P00 to P03Note 5,

P10 to P14

30-pin products: P10 to P17, P30, P31,

P50, P51, P147

100 mA

Per pin 0.5 mA

Output current, high

IOH2

Total of all pins

P20 to P23

2 mA

Per pin Other than P20 to P23 40 mA

All the terminals other than P20 to P23 170 mA

20-, 24-pin products: P40 to P42

30-pin products: P00, P01, P40, P120

70 mA

IOL1

Total of all pins

20-, 24-pin products: P00 to P03Note 5,

P10 to P14, P60, P61

30-pin products: P10 to P17, P30, P31,

P50, P51, P60, P61, P147

100 mA

Per pin 1 mA

Output current, low

IOL2

Total of all pins

P20 to P23

5 mA

Operating ambient

temperature

TA 40 to +85 C

Storage temperature Tstg 65 to +150 C

Notes 1. 30-pin product only.

2. Connect the REGC pin to VSS via a capacitor (0.47 to 1 F). This value determines the absolute maximum

rating of the REGC pin. Do not use it with voltage applied.

3. Must be 6.5 V or lower.

4. Do not exceed AVREF(+) + 0.3 V in case of A/D conversion target pin.

5. 24-pin products only.

Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter.

That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering

physical damage, and therefore the product must be used under conditions that ensure that the absolute

maximum ratings are not exceeded.

Remarks 1. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port

pins.

2. AVREF(+) : + side reference voltage of the A/D converter.

3. V

SS : Reference voltage

RL78/G12 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C)

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016

Page 18 of 106

2.2 Oscillator Characteristics

2.2.1 X1 oscillator characteristics

(TA = 40 to +85C, 1.8 V  VDD  VDD  5.5 V, VSS = 0 V)

Parameter Resonator Conditions MIN. TYP. MAX. Unit

2.7 V  VDD  5.5 V 1.0 20.0

X1 clock oscillation

frequency (fX)Note

Ceramic resonator /

crystal oscillator 1.8 V  VDD < 2.7 V 1.0 8.0

MHz

Note Indicates only permissible oscillator frequency ranges. Refer to AC Characteristics for instruction execution

time. Request evaluation by the manufacturer of the oscillator circuit mounted on a board to check the

oscillator characteristics.

Caution Since the CPU is started by the high-speed on-chip oscillator clock after a reset release, check the X1 clock

oscillation stabilization time using the oscillation stabilization time counter status register (OSTC) by the user.

Determine the oscillation stabilization time of the OSTC register and the oscillation stabilization time select

Remark When using the X1 oscillator, refer to 5.4 System Clock Oscillator.

2.2.2 On-chip oscillator characteristics

(TA = 40 to +85C, 1.8 V  VDD  5.5 V, VSS = 0 V)

Oscillators Parameters Conditions MIN. TYP. MAX. Unit

High-speed on-chip oscillator

clock frequency Notes 1, 2

fIH 1 24 MHz

TA = 20 to +85C -1.0 +1.0 % R5F102 products

TA = 40 to 20C -1.5

+1.5 %

High-speed on-chip oscillator

clock frequency accuracy

R5F103 products -5.0 +5.0 %

Low-speed on-chip oscillator

clock frequency

fIL 15 kHz

Low-speed on-chip oscillator

clock frequency accuracy

-15 +15 %

Notes 1. High-speed on-chip oscillator frequency is selected by bits 0 to 3 of option byte (000C2H) and bits 0 to 2 of

HOCODIV register.

2. This only indicates the oscillator characteristics. Refer to AC Characteristics for instruction execution time.

RL78/G12 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C)

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016

Page 19 of 106

2.3 DC Characteristics

2.3.1 Pin characteristics

(TA = 40 to +85C, 1.8 V  VDD  5.5 V, VSS = 0 V) (1/4)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

20-, 24-pin products:

Per pin for P00 to P03Note 4,

P10 to P14, P40 to P42

30-pin products:

Per pin for P00, P01, P10 to P17, P30,

P31, P40, P50, P51, P120, P147

10.0

Note 2

4.0 V  VDD  5.5 V 30.0 mA

2.7 V  VDD < 4.0 V 6.0 mA

20-, 24-pin products:

Total of P40 to P42

30-pin products:

Total of P00, P01, P40, P120

(When duty  70% Note 3)

1.8 V  VDD < 2.7 V 4.5 mA

4.0 V  VDD  5.5 V 80.0 mA

2.7 V  VDD < 4.0 V 18.0 mA

20-, 24-pin products:

Total of P00 to P03Note 4, P10 to P14

30-pin products:

Total of P10 to P17, P30, P31,

P50, P51, P147

(When duty  70% Note 3)

1.8 V  VDD < 2.7 V 10.0 mA

IOH1

Total of all pins (When duty  70%Note 3)

100 mA

Per pin for P20 to P23 0.1 mA

Output current, highNote 1

IOH2

Total of all pins 0.4 mA

Notes 1. value of current at which the device operation is guaranteed even if the current flows from the VDD pin to an

output pin.

2. However, do not exceed the total current value.

3. The output current value under conditions where the duty factor  70%.

If duty factor  70%: The output current value can be calculated with the following expression (where n

represents the duty factor as a percentage).

 Total output current of pins = (IOH × 0.7)/(n × 0.01)

<Example> Where n = 80% and IOH = 10.0 mA

Total output current of pins = (10.0 × 0.7)/(80 × 0.01)  8.7 mA

However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A

current higher than the absolute maximum rating must not flow into one pin.

4. 24-pin products only.

Caution P10 to P12 and P41 for 20-pin products, P01, P10 to P12, and P41 for 24-pin products, and P00, P10 to P15,

P17, and P50 for 30-pin products do not output high level in N-ch open-drain mode.

Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port

pins.

RL78/G12 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C)

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016

Page 20 of 106

(TA = 40 to +85C, 1.8 V  VDD  5.5 V, VSS = 0 V) (2/4)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

20-, 24-pin products:

Per pin for P00 to P03Note 4,

P10 to P14, P40 to P42

30-pin products:

Per pin for P00, P01, P10 to P17, P30,

P31, P40, P50, P51, P120, P147

20.0

Note 2

Per pin for P60, P61

15.0

Note 2

4.0 V  VDD  5.5 V 60.0 mA

2.7 V  VDD < 4.0 V 9.0 mA

20-, 24-pin products:

Total of P40 to P42

30-pin products:

Total of P00, P01, P40, P120

(When duty  70% Note 3)

1.8 V  VDD < 2.7 V 1.8 mA

4.0 V  VDD  5.5 V 80.0 mA

2.7 V  VDD < 4.0 V 27.0 mA

20-, 24-pin products:

Total of P00 to P03Note 4,

P10 to P14, P60, P61

30-pin products:

Total of P10 to P17, P30, P31, P50,

P51, P60, P61, P147

(When duty  70% Note 3)

1.8 V  VDD < 2.7 V 5.4 mA

IOL1

Total of all pins (When duty  70%Note 3)

140 mA

Per pin for P20 to P23 0.4 mA

Output current, lowNote 1

IOL2

Total of all pins 1.6 mA

Notes 1. Value of current at which the device operation is guaranteed even if the current flows from an output pin to

the VSS pin.

2. However, do not exceed the total current value.

3. The output current value under conditions where the duty factor  70%.

If duty factor  70%: The output current value can be calculated with the following expression (where n

represents the duty factor as a percentage).

 Total output current of pins = (IOL × 0.7)/(n × 0.01)

<Example> Where n = 80% and IOL = 10.0 mA

Total output current of pins = (10.0 × 0.7)/(80 × 0.01)  8.7 mA

However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A

current higher than the absolute maximum rating must not flow into one pin.

4. 24-pin products only.

Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port

pins.

RL78/G12 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C)

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016

Page 21 of 106

(TA = 40 to +85C, 1.8 V  VDD  5.5 V, VSS = 0 V) (3/4)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

VIH1 Normal input buffer

20-, 24-pin products: P00 to P03Note 2, P10 to P14,

P40 to P42

30-pin products: P00, P01, P10 to P17, P30, P31,

P40, P50, P51, P120, P147

0.8VDD VDD V

4.0 V  VDD  5.5 V 2.2 VDD V

3.3 V  VDD < 4.0 V 2.0 VDD V

VIH2 TTL input buffer

20-, 24-pin products: P10, P11

30-pin products: P01, P10,

P11, P13 to P17

1.8 V  VDD < 3.3 V 1.5 VDD V

VIH3 P20 to P23 0.7VDD VDD V

VIH4 P60, P61 0.7VDD 6.0 V

Input voltage, high

VIH5 P121, P122, P125Note 1, P137, EXCLK, RESET 0.8VDD VDD V

VIL1 Normal input buffer

20-, 24-pin products: P00 to P03Note 2, P10 to P14,

P40 to P42

30-pin products: P00, P01, P10 to P17, P30, P31,

P40, P50, P51, P120, P147

0 0.2VDD V

4.0 V  VDD  5.5 V 0 0.8 V

3.3 V  VDD < 4.0 V 0 0.5 V

VIL2 TTL input buffer

20-, 24-pin products: P10, P11

30-pin products: P01, P10,

P11, P13 to P17

1.8 V  VDD < 3.3 V 0 0.32 V

VIL3 P20 to P23 0 0.3VDD V

VIL4 P60, P61 0 0.3VDD V

Input voltage, low

VIL5 P121, P122, P125Note 1, P137, EXCLK, RESET 0 0.2VDD V

4.0 V  VDD  5.5 V,

IOH1 = 10.0 mA

VDD1.5 V

4.0 V  VDD  5.5 V,

IOH1 = 3.0 mA

VDD0.7 V

2.7 V  VDD  5.5 V,

IOH1 = 2.0 mA

VDD0.6 V

VOH1 20-, 24-pin products:

P00 to P03Note 2, P10 to P14,

P40 to P42

30-pin products:

P00, P01, P10 to P17, P30,

P31, P40, P50, P51, P120,

P147

1.8 V  VDD  5.5 V,

IOH1 = 1.5 mA

VDD0.5 V

Output voltage, high

VOH2 P20 to P23 IOH2 = 100



A VDD0.5 V

Notes 1. 20, 24-pin products only.

2. 24-pin products only.

Caution The maximum value of VIH of pins P10 to P12 and P41 for 20-pin products, P01, P10 to P12, and P41 for 24-

pin products, and P00, P10 to P15, P17, and P50 for 30-pin products is VDD even in N-ch open-drain mode.

High level is not output in the N-ch open-drain mode.

Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port

pins.

RL78/G12 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C)

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016

Page 22 of 106

(TA = 40 to +85C, 1.8 V  VDD  5.5 V, VSS = 0 V) (4/4)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

4.0 V  VDD  5.5 V,

IOL1 = 20.0 mA

1.3 V

4.0 V  VDD  5.5 V,

IOL1 = 8.5 mA

0.7 V

2.7 V  VDD  5.5 V,

IOL1 = 3.0 mA

0.6 V

2.7 V  VDD  5.5 V,

IOL1 = 1.5 mA

0.4 V

VOL1 20-, 24-pin products:

P00 to P03Note, P10 to P14,

P40 to P42

30-pin products: P00, P01,

P10 to P17, P30, P31, P40,

P50, P51, P120, P147

1.8 V  VDD  5.5 V,

IOL1 = 0.6 mA

0.4 V

VOL2 P20 to P23 IOL2 = 400



A 0.4 V

4.0 V  VDD  5.5 V,

IOL1 = 15.0 mA

2.0 V

4.0 V  VDD  5.5 V,

IOL1 = 5.0 mA

0.4 V

2.7 V  VDD  5.5 V,

IOL1 = 3.0 mA

0.4 V

Output voltage, low

VOL3 P60, P61

1.8 V  VDD  5.5 V,

IOL1 = 2.0 mA

0.4 V

ILIH1 Other than P121,

P122

VI = VDD 1



Input port or external

clock input



Input leakage current,

high

ILIH2 P121, P122

(X1, X2/EXCLK)

VI = VDD

When resonator

connected



ILIL1 Other than P121,

P122

VI = VSS 1



Input port or external

clock input

1



Input leakage current,

low

ILIL2 P121, P122

(X1, X2/EXCLK)

VI = VSS

When resonator

connected

10



On-chip pull-up

resistance

RU 20-, 24-pin products:

P00 to P03Note, P10 to P14,

P40 to P42, P125, RESET

30-pin products: P00, P01,

P10 to P17, P30, P31, P40,

P50, P51, P120, P147

VI = VSS, input port 10 20 100 k

Note 24-pin products only.

Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port

pins.

RL78/G12 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C)

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016

Page 23 of 106

2.3.2 Supply current characteristics

(1) 20-, 24-pin products

(TA = 40 to +85C, 1.8 V  VDD  5.5 V, VSS = 0 V) (1/2)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

VDD = 5.0 V 1.5

Basic

operation

VDD = 3.0 V 1.5

VDD = 5.0 V 3.3 5.0

= 24 MHz

Note 3

VDD = 3.0 V 3.3 5.0



VDD = 5.0 V 2.5 3.7

HS(High-speed

main) mode

Note 4

= 16 MHz

Note 3

VDD = 3.0 V 2.5 3.7

VDD = 3.0 V 1.2 1.8

LS(Low-speed

main) mode

Note 4

= 8 MHz

Note 3

VDD = 2.0 V 1.2 1.8

Square wave input 2.8 4.4

= 20 MHz

Note 2

= 5.0 V

Resonator connection 3.0 4.6

Square wave input 2.8 4.4

= 20 MHz

Note 2

= 3.0 V

Resonator connection 3.0 4.6



Square wave input 1.8 2.6

= 10 MHz

Note 2

= 5.0 V

Resonator connection 1.8 2.6



Square wave input 1.8 2.6

HS(High-speed

main) mode

Note4

= 10 MHz

Note 2

= 3.0 V

Resonator connection 1.8 2.6



Square wave input 1.1 1.7

= 8 MHz

Note 2

= 3.0 V

Resonator connection 1.1 1.7



Square wave input 1.1 1.7

Supply

currentNote 1

IDD1 Operating

mode

LS(Low-speed

main) mode

Note 4

= 8 MHz

Note 2

= 2.0 V

Normal

operation

Resonator connection 1.1 1.7



Notes 1. Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is

fixed to VDD or VSS. The values below the MAX. column include the peripheral operation current. However,

not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down

resistors and the current flowing during data flash rewrite.

2. When high-speed on-chip oscillator clock is stopped.

3. When high-speed system clock is stopped

4. Relationship between operation voltage width, operation frequency of CPU and operation mode is as

follows.

HS(High speed main) mode: VDD = 2.7 V to 5.5 V @1 MHz to 24 MHz

DD = 2.4 V to 5.5 V @1 MHz to 16 MHz

LS(Low speed main) mode: VDD = 1.8 V to 5.5 V @1 MHz to 8 MHz

Remarks 1. f

MX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock

frequency)

2. f

IH: high-speed on-chip oscillator clock frequency

3. Temperature condition of the TYP. value is TA = 25C.

RL78/G12 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C)

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016

Page 24 of 106

(1) 20-, 24-pin products

(TA = 40 to +85C, 1.8 V  VDD  5.5 V, VSS = 0 V) (2/2)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

VDD = 5.0 V 440 1210fIH = 24 MHzNote 4

VDD = 3.0 V 440 1210



VDD = 5.0 V 400 950

HS (High-speed

main) mode

Note 6

fIH = 16 MHzNote 4

VDD = 3.0 V 400 950



VDD = 3.0 V 270 542

LS (Low-speed

main) mode

Note 6

fIH = 8 MHzNote 4

VDD = 2.0 V 270 542



Square wave input 280 1000

fMX = 20 MHzNote 3,

VDD = 5.0 V

Resonator connection 450 1170



Square wave input 280 1000

fMX = 20 MHzNote 3,

VDD = 3.0 V Resonator connection 450 1170



Square wave input 190 590

fMX = 10 MHzNote 3,

VDD = 5.0 V Resonator connection 260 660



Square wave input 190 590

HS (High-speed

main) mode

Note 6

fMX = 10 MHzNote 3,

VDD = 3.0 V

Resonator connection 260 660



Square wave input 110 360

fMX = 8 MHzNote 3,

VDD = 3.0 V Resonator connection 150 416



Square wave input 110 360

IDD2 Note 2 HALT

mode

LS (Low-speed

main) mode

Note 6

fMX = 8 MHzNote 3,

VDD = 2.0 V Resonator connection 150 416



TA = 40C 0.19 0.50

TA = +25C 0.24 0.50

TA = +50C 0.32 0.80

TA = +70C 0.48 1.20

Supply

current Note 1

IDD3 Note 5 STOP

mode

TA = +85C 0.74 2.20



Notes 1. Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is

fixed to VDD or VSS. The values below the MAX. column include the peripheral operation current. However,

not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down

resistors and the current flowing during data flash rewrite.

2. During HALT instruction execution by flash memory.

3. When high-speed on-chip oscillator clock is stopped.

4. When high-speed system clock is stopped.

5. Not including the current flowing into the 12-bit interval timer and watchdog timer.

6. Relationship between operation voltage width, operation frequency of CPU and operation mode is as

follows.

HS(High speed main) mode: VDD = 2.7 V to 5.5 V @1 MHz to 24 MHz

VDD = 2.4 V to 5.5 V @1 MHz to 16 MHz

LS(Low speed main) mode: VDD = 1.8 V to 5.5 V @1 MHz to 8 MHz

Remarks 1. f

MX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock

frequency)

2. f

IH: high-speed on-chip oscillator clock frequency

3. Except temperature condition of the TYP. value is TA = 25C, other than STOP mode

RL78/G12 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C)

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016

Page 25 of 106

(2) 30-pin products

(TA = 40 to +85C, 1.8 V  VDD  5.5 V, VSS = 0 V) (1/2)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

VDD = 5.0 V 1.5

Basic

operation

VDD = 3.0 V 1.5

VDD = 5.0 V 3.7 5.5

= 24 MHz

Note 3

VDD = 3.0 V 3.7 5.5



VDD = 5.0 V 2.7 4.0

HS (High-speed

main) mode

Note 4

= 16 MHz

Note 3

VDD = 3.0 V 2.7 4.0

VDD = 3.0 V 1.2 1.8

LS (Low-speed

main) mode

Note 4

= 8 MHz

Note 3

VDD = 2.0 V 1.2 1.8

Square wave input 3.0 4.6

= 20 MHz

Note 2

= 5.0 V

Resonator connection 3.2 4.8

Square wave input 3.0 4.6

= 20 MHz

Note 2

= 3.0 V

Resonator connection 3.2 4.8



Square wave input 1.9 2.7

= 10 MHz

Note 2

= 5.0 V

Resonator connection 1.9 2.7



Square wave input 1.9 2.7

HS (High-speed

main) mode

Note 4

= 10 MHz

Note 2

= 3.0 V

Resonator connection 1.9 2.7



Square wave input 1.1 1.7

= 8 MHz

Note 2

= 3.0 V

Resonator connection 1.1 1.7



Square wave input 1.1 1.7

Supply

current Note 1

IDD1 Operating

mode

LS (Low-speed

main) mode

Note 4

= 8 MHz

Note 2

= 2.0 V

Normal

operation

Resonator connection 1.1 1.7



Notes 1. Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is

fixed to VDD or VSS. The values below the MAX. column include the peripheral operation current. However,

not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down

resistors and the current flowing during data flash rewrite.

2. When high-speed on-chip oscillator clock is stopped.

3. When high-speed system clock is stopped

4. Relationship between operation voltage width, operation frequency of CPU and operation mode is as

follows.

HS(High speed main) mode: VDD = 2.7 V to 5.5 V @1 MHz to 24 MHz

DD = 2.4 V to 5.5 V @1 MHz to 16 MHz

LS(Low speed main) mode: VDD = 1.8 V to 5.5 V @1 MHz to 8 MHz

Remarks 1. f

MX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock

frequency)

2. f

IH: high-speed on-chip oscillator clock frequency

3. Temperature condition of the TYP. value is TA = 25C.

RL78/G12 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C)

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016

Page 26 of 106

(2) 30-pin products

(TA = 40 to +85C, 1.8 V  VDD  5.5 V, VSS = 0 V) (2/2)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

VDD = 5.0 V 440 1280fIH = 24 MHzNote 4

VDD = 3.0 V 440 1280



VDD = 5.0 V 400 1000

HS (High-speed

main) mode

Note 6

fIH = 16 MHzNote 4

VDD = 3.0 V 400 1000



VDD = 3.0 V 260 530

LS (Low-speed

main) mode

Note 6

fIH = 8 MHzNote 4

VDD = 2.0 V 260 530



Square wave input 280 1000

fMX = 20 MHzNote 3,

VDD = 5.0 V

Resonator connection 450 1170



Square wave input 280 1000

fMX = 20 MHzNote 3,

VDD = 3.0 V Resonator connection 450 1170



Square wave input 190 600

fMX = 10 MHzNote 3,

VDD = 5.0 V Resonator connection 260 670



Square wave input 190 600

HS (High-speed

main) mode

Note 6

fMX = 10 MHzNote 3,

VDD = 3.0 V

Resonator connection 260 670



Square wave input 95 330

fMX = 8 MHzNote 3,

VDD = 3.0 V Resonator connection 145 380



Square wave input 95 330

IDD2 Note 2 HALT

mode

LS (Low-speed

main) mode

Note 6

fMX = 8 MHzNote 3

VDD = 2.0 V Resonator connection 145 380



TA = 40C 0.18 0.50

TA = +25C 0.23 0.50

TA = +50C 0.30 1.10

TA = +70C 0.46 1.90

Supply

current Note 1

IDD3Note 5 STOP

mode

TA = +85C 0.75 3.30



Notes 1. Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is

fixed to VDD or VSS. The values below the MAX. column include the peripheral operation current. However,

not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down

resistors and the current flowing during data flash rewrite.

2. During HALT instruction execution by flash memory.

3. When high-speed on-chip oscillator clock is stopped.

4. When high-speed system clock is stopped.

5. Not including the current flowing into the 12-bit interval timer and watchdog timer.

6. Relationship between operation voltage width, operation frequency of CPU and operation mode is as

follows.

HS (High speed main) mode: VDD = 2.7 V to 5.5 V @1 MHz to 24 MHz

VDD = 2.4 V to 5.5 V @1 MHz to 16 MHz

LS (Low speed main) mode: VDD = 1.8 V to 5.5 V @1 MHz to 8 MHz

Remarks 1. f

MX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock

frequency)

2. f

IH: high-speed on-chip oscillator clock frequency

3. Except STOP mode, temperature condition of the TYP. value is TA = 25C.

RL78/G12 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C)

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016

Page 27 of 106

(3) Peripheral functions (Common to all products)

(TA = 40 to +85C, 1.8 V  VDD  5.5 V, VSS = 0 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Low-speed

onchip oscillator

operating current

IFIL Note 1 0.20



12-bit interval

timer operating

current

ITMKA

Notes 1, 2, 3

0.02



Watchdog timer

operating current

IWDT

Notes 1, 2, 4

fIL = 15 kHz 0.22



Normal mode, AVREFP = VDD = 5.0 V 1.30 1.70 mA A/D converter

operating current

IADC Notes 1, 5 When conversion at

maximum speed Low voltage mode, AVREFP = VDD = 3.0 V 0.50 0.70 mA

A/D converter

reference voltage

operating current

IADREF Note 1 75.0



Temperature

sensor operating

current

ITMPS Note 1 75.0



LVD operating

current

ILVD Notes 1, 6 0.08



Self-

programming

operating current

IFSP Notes 1, 8 2.00 12.20 mA

BGO operating

current

IBGO Notes 1, 7 2.00 12.20 mA

The mode is performed Note 9 0.50 0.60 mA ADC operation

The A/D conversion operations are

performed, Low voltage mode,

AVREFP = VDD = 3.0 V

1.20 1.44 mA

SNOOZE

operating current

ISNOZ Note 1

CSI/UART operation 0.70 0.84 mA

Notes 1. Current flowing to the VDD.

2. When high speed on-chip oscillator and high-speed system clock are stopped.

3. Current flowing only to the 12-bit interval timer (excluding the operating current of the low-speed on-chip

oscillator). The current value of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3, and IFIL and ITMKA when

the 12-bit interval timer operates.

4. Current flowing only to the watchdog timer (including the operating current of the low-speed on-chip oscillator).

The current value of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and IWDT when the watchdog timer

operates.

5. Current flowing only to the A/D converter. The current value of the RL78 microcontrollers is the sum of IDD1 or

IDD2 and IADC when the A/D converter operates in an operation mode or the HALT mode.

6. Current flowing only to the LVD circuit. The current value of the RL78 microcontrollers is the sum of IDD1, IDD2 or

IDD3 and ILVD when the LVD circuit operates.

7. Current flowing only during data flash rewrite.

8. Current flowing only during self programming.

9. For shift time to the SNOOZE mode, see 17.3.3 SNOOZE mode.

Remarks 1. fIL: Low-speed on-chip oscillator clock frequency

2. Temperature condition of the TYP. value is TA = 25C

RL78/G12 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C)

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016

Page 28 of 106

2.4 AC Characteristics

(TA = 40 to +85C, 1.8 V  VDD  5.5 V, VSS = 0 V)

Items Symbol Conditions MIN. TYP. MAX. Unit

2.7 V  VDD  5.5 V 0.04167 1





HS (High-

speed main)

mode

2.4 V  VDD  2.7 V 0.0625 1





Main system

clock (f

MAIN

)

operation

LS (Low-

speed main)

mode

1.8 V  VDD  5.5 V 0.125 1



2.7 V  VDD  5.5 V 0.04167 1





HS (High-

speed main)

mode

2.4 V  VDD  2.7 V 0.0625 1





Instruction cycle (minimum

instruction execution time)

TCY

During self

programming

LS (Low-

speed main)

mode

1.8 V  VDD  5.5 V 0.125 1



2.7 V  VDD  5.5 V 1.0 20.0 MHz

2.4 V  VDD  2.7 V 1.0 16.0 MHz

External main system clock

frequency

fEX

1.8 V  VDD  2.4 V 1.0 8.0 MHz

2.7 V  VDD  5.5 V 24 ns

2.4 V  VDD  2.7 V 30 ns

External main system clock

input high-level width, low-

level width

tEXH, tEXL

1.8 V  VDD  2.4 V 60 ns

TI00 to TI07 input high-level

width, low-level width

tTIH, tTIL

1/f

MCK



4.0 V  VDD  5.5 V

12 MHz

2.7 V  VDD  4.0 V

8 MHz

TO00 to TO07 output

frequency

fTO

1.8 V  VDD  2.7 V

4 MHz

4.0 V  VDD  5.5 V

16 MHz

2.7 V  VDD  4.0 V

8 MHz

PCLBUZ0, or PCLBUZ1

output frequency

fPCL

1.8 V  VDD  2.7 V

4 MHz

INTP0 to INTP5 input high-

level width, low-level width

tINTH, tINTL 1



KR0 to KR9 input available

width

tKR 250 ns



RESET low-level width tRSL 10





Remark fMCK: Timer array unit operation clock frequency

(Operation clock to be set by the timer clock select register 0 (TPS0) and the CKS0n bit of timer mode

RL78/G12 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C)

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016

Page 29 of 106

Minimum Instruction Execution Time during Main System Clock Operation

TCY vs VDD (HS (high-speed main) mode)

When the high-speed on-chip oscillator clock is selected

During self programming

When high-speed system clock is selected

Supply voltage V

[V]

1.0

0.1

1.02.03.04.05.06.0

5.52.7

0.01

2.4

0.04167

0.0625

Cycle time TCY [µs]

TCY vs VDD (LS (low-speed main) mode)

1.0

0.1

1.0 2.0 3.0 4.0 5.0 6.0

5.5

0.01

1.8

0.125

Cycle time T

[µs]

Supply voltage V

[V]

When the high-speed on-chip oscillator clock is selected

During self programming

When high-speed system clock is selected

RL78/G12 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C)

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016

Page 30 of 106

AC Timing Test Point

Test points V

External Main System Clock Timing

EXCLK

1/f

EXL

EXH

TI/TO Timing

TI00 to TI07

TIL

TIH

TO00 to TO07

1/f

Interrupt Request Input Timing

INTP0 to INTP5

INTL

INTH

Key Interrupt Input Timing

KR0 to KR9

RESET Input Timing

RESET

RSL

RL78/G12 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C)

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016

Page 31 of 106

2.5 Peripheral Functions Characteristics

AC Timing Test Point

Test points V

2.5.1 Serial array unit

(1) During communication at same potential (UART mode)

(TA = 40 to +85C, 1.8 V  VDD  5.5 V, VSS = 0 V)

HS (high-speed

main) Mode

LS (low-speed

main) Mode

Parameter Symbol Conditions

MIN. MAX. MIN. MAX.

Unit

fMCK/6 fMCK/6 bps Transfer rate

Note 1

Theoretical value of the maximum transfer rate

fCLK = fMCKNote2

4.0 1.3 Mbps

Notes 1. Transfer rate in the SNOOZE mode is 4800 bps only.

2. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are:

HS (high-speed main) mode: 24 MHz (2.7 V VDD 5.5 V)

16 MHz (2.4 V VDD 5.5 V)

LS (low-speed main) mode: 8 MHz (1.8 V VDD 5.5 V)

Caution Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by using port

input mode register g (PIMg) and port output mode register g (POMg).

UART mode connection diagram (during communication at same potential)

RL78

microcontroller

TxDq

RxDq

User's device

UART mode bit width (during communication at same potential) (reference)

TxDq

RxDq

Baud rate error tolerance

High-/Low-bit width

1/Transfer rate

Remarks 1. q: UART number (q = 0 to 2), g: PIM, POM number (g = 0, 1)

2. f

MCK: Serial array unit operation clock frequency

(Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial

mode register mn (SMRmn).

m: Unit number, n: Channel number (mn = 00 to 03, 10, 11))

RL78/G12 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C)

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016

Page 32 of 106

(2) During communication at same potential (CSI mode) (master mode, SCK00... internal clock output,

corresponding CSI00 only)

(TA = 40 to +85C, 2.7 V  VDD  5.5 V, VSS = 0 V)

HS (high-speed main)

Mode

LS (low-speed main)

Mode

Parameter Symbol Conditions

MIN. MAX. MIN. MAX.

Unit

SCK00 cycle time tKCY1 tKCY1  2/fCLK 83.3 250 ns

4.0 V  VDD  5.5 V tKCY1/27 tKCY1/250 ns

SCK00 high-/low-

level width

tKH1,

tKL1 2.7 V  VDD  5.5 V tKCY1/210 tKCY1/250 ns

4.0 V  VDD  5.5 V 23 110 ns

SI00 setup time

(to SCK00) Note 1

tSIK1

2.7 V  VDD  5.5 V 33 110 ns

SI00 hold time

(from SCK00) Note2

tKSI1 10 10 ns

Delay time from

SCK00 to SO00

output Note 3

tKSO1 C = 20 pF Note 4 10 10 ns

Notes 1. When DAP00 = 0 and CKP00 = 0, or DAP00 = 1 and CKP00 = 1. The SI00 setup time becomes “to

SCK00” when DAP00 = 0 and CKP00 = 1, or DAP00 = 1 and CKP00 = 0.

2. When DAP00 = 0 and CKP00 = 0, or DAP00 = 1 and CKP00 = 1. The SI00 hold time becomes “from

SCK00” when DAP00 = 0 and CKP00 = 1, or DAP00 = 1 and CKP00 = 0.

3. When DAP00 = 0 and CKP00 = 0, or DAP00 = 1 and CKP00 = 1. The delay time to SO00 output becomes

“from SCK00” when DAP00 = 0 and CKP00 = 1, or DAP00 = 1 and CKP00 = 0.

4. C is the load capacitance of the SCK00 and SO00 output lines.

Caution Select the normal input buffer for the SI00 pin and the normal output mode for the SO00 and SCK00 pins by

using port input mode register 1 (PIM1) and port output mode register 1 (POM1).

Remarks 1. This specification is valid only when CSI00’s peripheral I/O redirect function is not used.

2. fMCK: Serial array unit operation clock frequency

(Operation clock to be set by the serial clock select register 0 (SPS0) and the CKS00 bit of serial mode

RL78/G12 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C)

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016

Page 33 of 106

(3) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output)

(TA = 40 to +85C, 1.8 V  VDD  5.5 V, VSS = 0 V)

HS (high-speed

main) Mode

LS (low-speed main)

Mode

Parameter Symbol Conditions

MIN. MAX. MIN. MAX.

Unit

2.7 V  VDD  5.5 V 167 500 ns

2.4 V  VDD  5.5 V 250 500 ns

SCKp cycle time tKCY1 tKCY1  4/fCLK

1.8 V  VDD  5.5 V  500 ns

4.0 V  VDD  5.5 V tKCY1/212 tKCY1/250 ns

2.7 V  VDD  5.5 V tKCY1/218 tKCY1/250 ns

2.4 V  VDD  5.5 V tKCY1/238 tKCY1/250 ns

SCKp high-/low-level width tKH1,

tKL1

1.8 V  VDD  5.5 V  tKCY1/250 ns

4.0 V  VDD  5.5 V 44 110 ns

2.7 V  VDD  5.5 V 44 110 ns

2.4 V  VDD  5.5 V 75 110 ns

SIp setup time (to SCKp)

Note 1

tSIK1

1.8 V  VDD  5.5 V  110 ns

SIp hold time

(from SCKp) Note 2

tKSI1 19 19 ns

Delay time from SCKp to

SOp output Note 3

tKSO1 C = 30 pF Note4 25 25 ns

Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to

SCKp” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from

SCKp” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output

becomes “from SCKp” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

4. C is the load capacitance of the SCKp and SOp output lines.

Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp and SCKp pins by

using port input mode register 1 (PIM1) and port output mode registers 0, 1, 4 (POM0, POM1, POM4).

Remarks 1. p: CSI number (p = 00, 01, 11, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0, 1, 3: “1, 3” is

only for the R5F102 products)

2. fMCK: Serial array unit operation clock frequency

(Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode

R5F102 products.))

RL78/G12 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C)

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016

Page 34 of 106

(4) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input)

(TA = 40 to +85C, 1.8 V  VDD  5.5 V, VSS = 0 V)

HS (high-speed

main) Mode

LS (low-speed main)

Mode

Parameter Symbol Conditions

MIN. MAX. MIN. MAX.

Unit

20 MHz  fMCK 8/fMCK  ns 4.0 V  VDD  5.5 V

fMCK  20 MHz 6/fMCK 6/fMCK ns

16 MHz  fMCK 8/fMCK  ns 2.7 V  VDD  5.5 V

fMCK  16 MHz 6/fMCK 6/fMCK ns

2.4 V  VDD  5.5 V 6/fMCK

and 500

6/fMCK

and 500

SCKp cycle time Note4 tKCY2

1.8 V  VDD  5.5 V  6/fMCK

and 750

4.0 V  VDD  5.5 V tKCY2/27 tKCY2/27 ns

2.7 V  VDD  5.5 V tKCY2/28 tKCY2/28 ns

SCKp high-/low-level

width

tKH2,

tKL2

2.4 V  VDD  5.5 V tKCY2/218 tKCY2/218 ns

1.8 V  VDD  5.5 V  tKCY2/218 ns

2.7 V  VDD  5.5 V 1/fMCK +

1/fMCK +

2.4 V  VDD  5.5 V 1/fMCK +

1/fMCK +

SIp setup time

(to SCKp) Note 1

tSIK2

1.8 V  VDD  5.5 V  1/fMCK +

SIp hold time

(from SCKp) Note 2

tKSI2 1/fMCK +

1/fMCK +

2.7 V  VDD  5.5 V 2/fMCK +

2/fMCK +

110

2.4 V  VDD  5.5 V 2/fMCK +

2/fMCK +

110

Delay time from

SCKp to

SOp output Note 3

tKSO2 C = 30 pF Note4

1.8 V  VDD  5.5 V  2/fMCK +

110

Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to

SCKp” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from

SCKp” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output

becomes “from SCKp” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

4. C is the load capacitance of the SOp output lines.

5. Transfer rate in the SNOOZE mode: MAX. 1 Mbps

Caution Select the normal input buffer for the SIp and SCKp pins and the normal output mode for the SOp pin by

using port input mode register 1 (PIM1) and port output mode registers 0, 1, 4 (POM0, POM1, POM4).

RL78/G12 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C)

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016

Page 35 of 106

CSI mode connection diagram (during communication at same potential)

RL78

microcontroller

SCKp

SOp

SCK

User's device

SIp SO

CSI mode serial transfer timing (during communication at same potential)

(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)

SIp

SOp

KCY1, 2

KL1, 2

KH1, 2

SIK1, 2

KSI1, 2

KSO1, 2

SCKp

Input data

Output data

CSI mode serial transfer timing (during communication at same potential)

(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)

SIp

SOp

KCY1, 2

KH1, 2

KL1, 2

SIK1, 2

KSI1, 2

KSO1, 2

SCKp

Input data

Output data

(Remarks are listed on the next page.)

RL78/G12 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C)

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016

Page 36 of 106

Remarks 1. p: CSI number (p = 00, 01, 11, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0, 1, 3: “1, 3” is

only for the R5F102 products.)

2. f

MCK: Serial array unit operation clock frequency

(Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode

R5F102 products.))

(5) During communication at same potential (simplified I2C mode)

(TA = 40 to +85C, 1.8 V  VDD  5.5 V, VSS = 0 V)

HS (high-speed main) Mode

LS (low-speed main) Mode

Parameter Symbol Conditions

MIN. MAX.

Unit

1.8 V  VDD  5.5 V,

Cb = 100 pF, Rb = 3 k

400

Note 1 kHz SCLr clock frequency fSCL

1.8 V  VDD < 2.7 V,

Cb = 100 pF, Rb = 5 k

300

Note 1 kHz

1.8 V  VDD  5.5 V,

Cb = 100 pF, Rb = 3 k

1150 ns

Hold time when SCLr = “L” tLOW

1.8 V  VDD < 2.7 V,

Cb = 100 pF, Rb = 5 k

1550 ns

1.8 V  VDD  5.5 V,

Cb = 100 pF, Rb = 3 k

1150 ns

Hold time when SCLr = “H” tHIGH

1.8 V  VDD < 2.7 V,

Cb = 100 pF, Rb = 5 k

1550 ns

1.8 V  VDD  5.5 V,

Cb = 100 pF, Rb = 3 k

1/fMCK + 145 Note 2 ns Data setup time (reception) tSU:DAT

1.8 V  VDD < 2.7 V,

Cb = 100 pF, Rb = 5 k

1/fMCK + 230 Note 2 ns

1.8 V  VDD  5.5 V,

Cb = 100 pF, Rb = 3 k

0 355 ns

Data hold time (transmission) tHD:DAT

1.8 V  VDD < 2.7 V,

Cb = 100 pF, Rb = 5 k

0 405 ns

Notes 1. The value must also be equal to or less than fMCK/4.

2. Set tSU:DAT so that it will not exceed the hold time when SCLr = "L" or SCLr = "H".

Caution Select the N-ch open drain output (VDD tolerance) mode for SDAr by using port output mode register h

(POMh).

(Remarks are listed on the next page.)

RL78/G12 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C)

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016

Page 37 of 106

Simplified I2C mode connection diagram (during communication at same potential)

RL78

microcontroller

SDAr

SCLr

SDA

SCL

User's device

Simplified I2C mode serial transfer timing (during communication at same potential)

SDAr

tLOW tHIGH

tHD:DAT

SCLr

tSU:DAT

1/fSCL

Remarks 1. Rb []:Communication line (SDAr) pull-up resistance

b [F]: Communication line (SCLr, SDAr) load capacitance

2. r: IIC number (r = 00, 01, 11, 20), h: = POM number (h = 0, 1, 4, 5)

3. f

MCK: Serial array unit operation clock frequency

(Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial

mode register mn (SMRmn). m: Unit number (m = 0, 1), n: Channel number (0, 1, 3))

4. Simplified I2C mode is supported only by the R5F102 products.

RL78/G12 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C)

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016

Page 38 of 106

(6) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode)

(TA = 40 to +85C, 1.8 V  VDD  5.5 V, VSS = 0 V)

HS (high-speed

main) Mode

LS (low-speed

main) Mode

Parameter Symbol Conditions

MIN. MAX. MIN. MAX.

Unit

4.0 V  VDD  5.5 V,

2.7 V  Vb  4.0 V

MCK/6

Note1

MCK/6

Note1

bps

Theoretical value of the maximum

transfer rate

fMCK = fCLK

Note3

4.0 1.3 Mbps

2.7 V  VDD < 4.0 V,

2.3 V  Vb  2.7 V

MCK/6

Note1

MCK/6

Note1

bps

Theoretical value of the maximum

transfer rate

fMCK = fCLK

Note3

4.0 1.3 Mbps

1.8 V  VDD < 3.3 V,

1.6 V  Vb  2.0 V

MCK/6

Notes1, 2

MCK/6

Notes1, 2

bps

Reception

Theoretical value of the maximum

transfer rate

fMCK = fCLK

Note3

4.0 1.3 Mbps

4.0 V  VDD  5.5 V,

2.7 V  Vb  4.0 V

Note4 Note4 bps

Theoretical value of the maximum

transfer rate

Cb = 50 pF, Rb = 1.4 k, Vb = 2.7 V

2.8

Note5

2.8

Note5

Mbps

2.7 V  VDD < 4.0 V,

2.3 V  Vb  2.7 V,

Note6 Note6 bps

Theoretical value of the maximum

transfer rate

Cb = 50 pF, Rb = 2.7 k, Vb = 2.3 V

1.2

Note7

1.2

Note7

Mbps

1.8 V  VDD < 3.3 V,

1.6 V  Vb  2.0 V

Notes

2, 8

Notes

2, 8

bps

Transfer

rate Note4

Transmission

Theoretical value of the maximum

transfer rate

Cb = 50 pF, Rb = 5.5 k, Vb = 1.6 V

0.43

Note9

0.43

Note9

Mbps

Notes 1. Transfer rate in the SNOOZE mode is 4800 bps only.

2. Use it with VDD Vb.

3. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are:

HS (high-speed main) mode: 24 MHz (2.7 V VDD 5.5 V)

16 MHz (2.4 V VDD 5.5 V)

LS (low-speed main) mode: 8 MHz (1.8 V VDD 5.5 V)

4. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid

maximum transfer rate.

Expression for calculating the transfer rate when 4.0 V  VDD  5.5 V and 2.7 V  Vb  4.0 V

Maximum transfer rate = [bps]

{Cb × Rb × ln (1  2.2

Vb)} × 3

Transfer rate  2  {Cb × Rb × ln (1  2.2

Vb)}

Baud rate error (theoretical value) = × 100 [%]

( 1

Transfer rate ) × Number of transferred bits

* This value is the theoretical value of the relative difference between the transmission and reception sides.

RL78/G12 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C)

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016

Page 39 of 106

5. This value as an example is calculated when the conditions described in the “Conditions” column are met.

Refer to Note 4 above to calculate the maximum transfer rate under conditions of the customer.

6. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid

maximum transfer rate.

Expression for calculating the transfer rate when 2.7 V  VDD < 4.0 V and 2.3 V  Vb  2.7 V

Maximum transfer rate =

{Cb × Rb × ln (1  2.0

Vb)} × 3

[bps]

Transfer rate  2  {Cb × Rb × ln (1  2.0

Vb)}

Baud rate error (theoretical value) = × 100 [%]

( 1

Transfer rate ) × Number of transferred bits

* This value is the theoretical value of the relative difference between the transmission and reception sides.

7. This value as an example is calculated when the conditions described in the “Conditions” column are met.

Refer to Note 6 above to calculate the maximum transfer rate under conditions of the customer.

8. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid

maximum transfer rate.

Expression for calculating the transfer rate when 1.8 V  VDD < 3.3 V, 1.6 V  Vb  2.0 V

Maximum transfer rate = [bps]

{Cb × Rb × ln (1  1.5

Vb)} × 3

Transfer rate  2  {Cb × Rb × ln (1  1.5

Vb)}

Baud rate error (theoretical value) = × 100 [%]

( 1

Transfer rate ) × Number of transferred bits

* This value is the theoretical value of the relative difference between the transmission and reception sides.

9. This value as an example is calculated when the conditions described in the “Conditions” column are met.

Refer to Note 8 above to calculate the maximum transfer rate under conditions of the customer.

Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance) mode for the

TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and

VIL, see the DC characteristics with TTL input buffer selected.

RL78/G12 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C)

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016

Page 40 of 106

UART mode connection diagram (during communication at different potential)

RL78

microcontroller

TxDq

RxDq

User's device

UART mode bit width (during communication at different potential) (reference)

TxDq

RxDq

Baud rate error tolerance

High-/Low-bit width

1/Transfer rate

Baud rate error tolerance

High-bit width

Low-bit width

1/Transfer rate

Remarks 1. Rb[]: Communication line (TxDq) pull-up resistance, Cb[F]: Communication line (TxDq) load capacitance,

Vb[V]: Communication line voltage

2. q: UART number (q = 0 to 2), g: PIM and POM number (g = 0, 1)

3. fMCK: Serial array unit operation clock frequency

(Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode

m: Unit number, n: Channel number (mn = 00 to 03, 10, 11))

4. UART0 of the 20- and 24-pin products supports communication at different potential only when the

peripheral I/O redirection function is not used.

RL78/G12 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C)

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016

Page 41 of 106

(7) Communication at different potential (2.5 V, 3 V) (CSI mode) (master mode, SCK00... internal clock output,

corresponding CSI00 only)

(TA = 40 to +85C, 2.7 V  VDD  5.5 V, VSS = 0 V)

HS (high-speed

main) Mode

LS (low-speed

main) Mode

Parameter Symbol Conditions

MIN. MAX. MIN. MAX.

Unit

4.0 V  VDD  5.5 V,

2.7 V  Vb  4.0 V,

Cb = 20 pF, Rb = 1.4 k

200 1150 ns

SCK00 cycle time tKCY1 tKCY1  2/fCLK

2.7 V  VDD < 4.0 V,

2.3 V  Vb  2.7 V,

Cb = 20 pF, Rb = 2.7 k

300 1150 ns

4.0 V  VDD  5.5 V, 2.7 V  Vb  4.0 V,

Cb = 20 pF, Rb = 1.4 k

tKCY1/2 

tKCY1/2

SCK00 high-level width tKH1

2.7 V  VDD < 4.0 V, 2.3 V  Vb  2.7 V,

Cb = 20 pF, Rb = 2.7 k

tKCY1/2 

120

tKCY1/2 

120

4.0 V  VDD  5.5 V, 2.7 V  Vb  4.0 V,

Cb = 20 pF, Rb = 1.4 k

tKCY1/2 

SCK00 low-level width tKL1

2.7 V  VDD < 4.0 V, 2.3 V  Vb  2.7 V,

Cb = 20 pF, Rb = 2.7 k

tKCY1/2 

4.0 V  VDD  5.5 V, 2.7 V  Vb  4.0 V,

Cb = 20 pF, Rb = 1.4 k

58 479 ns

SI00 setup time

(to SCK00) Note 1

tSIK1

2.7 V  VDD < 4.0 V, 2.3 V  Vb  2.7 V,

Cb = 20 pF, Rb = 2.7 k

121 479 ns

4.0 V  VDD  5.5 V, 2.7 V  Vb  4.0 V,

Cb = 20 pF, Rb = 1.4 k

10 10 ns

SI00 hold time

(from SCK00) Note 1

tKSI1

2.7 V  VDD < 4.0 V, 2.3 V  Vb  2.7 V,

Cb = 20 pF, Rb = 2.7 k

10 10 ns

4.0 V  VDD  5.5 V, 2.7 V  Vb  4.0 V,

Cb = 20 pF, Rb = 1.4 k

60 60 ns

Delay time from SCK00

to SO00 output Note 1

tKSO1

2.7 V  VDD < 4.0 V, 2.3 V  Vb  2.7 V,

Cb = 20 pF, Rb = 2.7 k

130 130 ns

4.0 V  VDD  5.5 V, 2.7 V  Vb  4.0 V,

Cb = 20 pF, Rb = 1.4 k

23 110 ns

SI00 setup time

(to SCK00) Note 2

tSIK1

2.7 V  VDD < 4.0 V, 2.3 V  Vb  2.7 V,

Cb = 20 pF, Rb = 2.7 k

33 110 ns

4.0 V  VDD  5.5 V, 2.7 V  Vb  4.0 V,

Cb = 20 pF, Rb = 1.4 k

10 10 ns

SI00 hold time

(from SCK00) Note 2

tKSI1

2.7 V  VDD < 4.0 V, 2.3 V  Vb  2.7 V,

Cb = 20 pF, Rb = 2.7 k

10 10 ns

4.0 V  VDD  5.5 V, 2.7 V  Vb  4.0 V,

Cb = 20 pF, Rb = 1.4 k

10 10 ns

Delay time from SCK00

to SO00 output Note 2

tKSO1

2.7 V  VDD < 4.0 V, 2.3 V  Vb  2.7 V,

Cb = 20 pF, Rb = 2.7 k

10 10 ns

(Notes, Caution, and Remarks are listed on the next page.)

RL78/G12 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C)

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016

Page 42 of 106

Notes 1. When DAP00 = 0 and CKP00 = 0, or DAP00 = 1 and CKP00 = 1

2. When DAP00 = 0 and CKP00 = 1, or DAP00 = 1 and CKP00 = 0.

Caution Select the TTL input buffer for the SI00 pin and the N-ch open drain output (VDD tolerance) mode for the

SO00 pin and SCK00 pin by using port input mode register 1 (PIM1) and port output mode register 1 (POM1).

For VIH and VIL, see the DC characteristics with TTL input buffer selected.

Remarks 1. R

b []:Communication line (SCK00, SO00) pull-up resistance, Cb [F]: Communication line (SCK00, SO00)

load capacitance, Vb [V]: Communication line voltage

2. fMCK: Serial array unit operation clock frequency

(Operation clock to be set by the serial clock select register 0 (SPS0) and the CKS00 bit of serial mode

RL78/G12 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C)

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016

Page 43 of 106

(8) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock

output) (1/3)

(TA = 40 to +85C, 1.8 V  VDD  VDD  5.5 V, VSS = 0 V)

HS (high-speed main)

Mode

LS (low-speed main)

Mode

Parameter Symbol Conditions

MIN. MAX. MIN. MAX.

Unit

4.0 V  VDD  5.5 V,

2.7 V  Vb  4.0 V,

Cb = 30 pF, Rb = 1.4 k

300

1150

2.7 V  VDD < 4.0 V,

2.3 V  Vb  2.7 V,

Cb = 30 pF, Rb = 2.7 k

500 1150

SCKp cycle time tKCY1 tKCY1  4/fCLK

1.8 V  VDD < 3.3 V,

1.6 V  Vb  2.0 V Note,

Cb = 30 pF, Rb = 5.5 k

1150 1150

4.0 V  VDD  5.5 V, 2.7 V  Vb  4.0 V,

Cb = 30 pF, Rb = 1.4 k

tKCY1/2 75 tKCY1/275 ns

2.7 V  VDD < 4.0 V, 2.3 V  Vb  2.7 V,

Cb = 30 pF, Rb = 2.7 k

tKCY1/2 170 tKCY1/2170 ns

SCKp high-level width tKH1

1.8 V  VDD < 3.3 V, 1.6 V  Vb  2.0 V Note,

Cb = 30 pF, Rb = 5.5 k

tKCY1/2 458 tKCY1/2458 ns

4.0 V  VDD  5.5 V, 2.7 V  Vb  4.0 V,

Cb = 30 pF, Rb = 1.4 k

tKCY1/2 12 tKCY1/250 ns

2.7 V  VDD < 4.0 V, 2.3 V  Vb  2.7 V,

Cb = 30 pF, Rb = 2.7 k

tKCY1/2 18 tKCY1/250 ns

SCKp low-level width tKL1

1.8 V  VDD < 3.3 V, 1.6 V  Vb  2.0 V Note,

Cb = 30 pF, Rb = 5.5 k

tKCY1/2 50 tKCY1/250 ns

Note Use it with VDD Vb.

Cautions 1. Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode for the

SOp pin and SCKp pin by using port input mode register 1 (PIM1) and port output mode register 1

(POM1). For VIH and VIL, see the DC characteristics with TTL input buffer selected.

2. CSI01 and CSI11 cannot communicate at different potential.

Remarks 1. R

b []: Communication line (SCKp, SOp) pull-up resistance, Cb [F]: Communication line (SCKp, SOp)

load capacitance, Vb [V]: Communication line voltage

2. p: CSI number (p = 00, 20)

RL78/G12 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C)

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016

Page 44 of 106

(8) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock

output) (2/3)

(TA = 40 to +85C, 1.8 V  VDD  5.5 V, VSS = 0 V)

HS (high-speed

main) Mode

LS (low-speed

main) Mode

Parameter Symbol Conditions

MIN. MAX. MIN. MAX.

Unit

4.0 V  VDD  5.5 V, 2.7 V  Vb  4.0 V,

Cb = 30 pF, Rb = 1.4 k

479 ns

2.7 V  VDD < 4.0 V, 2.3 V  Vb  2.7 V,

Cb = 30 pF, Rb = 2.7 k

177 479 ns

SIp setup time

(to SCKp) Note 1

tSIK1

1.8 V  VDD < 3.3 V, 1.6 V  Vb  2.0 V Note 2,

Cb = 30 pF, Rb = 5.5 k

479 479 ns

4.0 V  VDD  5.5 V, 2.7 V  Vb  4.0 V,

Cb = 30 pF, Rb = 1.4 k

19 19 ns

2.7 V  VDD < 4.0 V, 2.3 V  Vb  2.7 V,

Cb = 30 pF, Rb = 2.7 k

19 19 ns

SIp hold time

(from SCKp) Note 1

tKSI1

1.8 V  VDD < 3.3 V, 1.6 V  Vb  2.0 V Note 2,

Cb = 30 pF, Rb = 5.5 k

19 19 ns

4.0 V  VDD  5.5 V, 2.7 V  Vb  4.0 V,

Cb = 30 pF, Rb = 1.4 k

100 100 ns

2.7 V  VDD < 4.0 V, 2.3 V  Vb  2.7 V,

Cb = 30 pF, Rb = 2.7 k

195 195 ns

Delay time from

SCKp to

SOp output Note 1

tKSO1

1.8 V  VDD < 3.3 V, 1.6 V  Vb  2.0 V Note 2,

Cb = 30 pF, Rb = 5.5 k

483 483 ns

Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.

2. Use it with VDD Vb.

(Cautions and Remarks are listed on the next page.)

RL78/G12 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C)

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016

Page 45 of 106

(8) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock

output) (3/3)

(TA = 40 to +85C, 1.8 V  VDD  5.5 V, VSS = 0 V)

HS (high-speed

main) Mode

LS (low-speed

main) Mode

Parameter Symbol Conditions

MIN. MAX. MIN. MAX.

Unit

4.0 V  VDD  5.5 V, 2.7 V  Vb  4.0 V,

Cb = 30 pF, Rb = 1.4 k

110 ns

2.7 V  VDD < 4.0 V, 2.3 V  Vb  2.7 V,

Cb = 30 pF, Rb = 2.7 k

110 ns

SIp setup time

(to SCKp) Note 1

tSIK1

1.8 V  VDD < 3.3 V, 1.6 V  Vb  2.0 V Note 2,

Cb = 30 pF, Rb = 5.5 k

110 110 ns

4.0 V  VDD  5.5 V, 2.7 V  Vb  4.0 V,

Cb = 30 pF, Rb = 1.4 k

19 19 ns

2.7 V  VDD < 4.0 V, 2.3 V  Vb  2.7 V,

Cb = 30 pF, Rb = 2.7 k

19 19 ns

SIp hold time

(from SCKp) Note 1

tKSI1

1.8 V  VDD < 3.3 V, 1.6 V  Vb  2.0 V Note 2,

Cb = 30 pF, Rb = 5.5 k

19 19 ns

4.0 V  VDD  5.5 V, 2.7 V  Vb  4.0 V,

Cb = 30 pF, Rb = 1.4 k

25 25 ns

2.7 V  VDD < 4.0 V, 2.3 V  Vb  2.7 V,

Cb = 30 pF, Rb = 2.7 k

25 25 ns

Delay time from

SCKp to

SOp output Note 1

tKSO1

1.8 V  VDD < 3.3 V, 1.6 V  Vb  2.0 V Note 2,

Cb = 30 pF, Rb = 5.5 k

25 25 ns

Notes 1. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

2. Use it with VDD Vb.

Cautions 1. Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode for the

SOp pin and SCKp pin by using port input mode register 1 (PIM1) and port output mode register 1

(POM1). For VIH and VIL, see the DC characteristics with TTL input buffer selected.

2. CSI01 and CSI11 cannot communicate at different potential.

Remarks 1. R

b []: Communication line (SCKp, SOp) pull-up resistance, Cb [F]: Communication line (SCKp, SOp)

load capacitance, Vb [V]: Communication line voltage

2. p: CSI number (p = 00, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0)

CSI mode connection diagram (during communication at different potential)

SCKp

SOp

SCK

User's device

SIp SO

RL78

microcontroller

RL78/G12 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C)

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016

Page 46 of 106

CSI mode serial transfer timing (master mode) (during communication at different potential)

(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1)

Input data

Output data

SIp

SOp

KCY1

KL1

KH1

SIK1

KSI1

KSO1

SCKp

CSI mode serial transfer timing (master mode) (during communication at different potential)

(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)

tKCY1

tKL1

tKH1

tSIK1 tKSI1

tKSO1

SIp

SOp

SCKp

Input data

Output data

RL78/G12 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C)

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016

Page 47 of 106

(9) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (slave mode, SCKp... external clock input)

(TA = 40 to +85C, 1.8 V  VDD  5.5 V, VSS = 0 V)

HS (high-speed main)

Mode

LS (low-speed main)

Mode

Parameter Symbol Conditions

MIN. MAX. MIN. MAX.

Unit

20 MHz < fMCK  24 MHz 12/fMCK  ns

8 MHz < fMCK  20 MHz 10/fMCK  ns

4 MHz < fMCK  8 MHz 8/fMCK 16/fMCK ns

4.0 V  VDD  5.5 V,

2.7 V  Vb  4.0 V

fMCK  4 MHz 6/fMCK 10/fMCK ns

20 MHz < fMCK  24 MHz 16/fMCK  ns

16 MHz < fMCK  20 MHz 14/fMCK  ns

8 MHz < fMCK  16 MHz 12/fMCK  ns

4 MHz < fMCK  8 MHz 8/fMCK 16/fMCK ns

2.7 V  VDD < 4.0 V,

2.3 V  Vb  2.7 V

fMCK  4 MHz

6/fMCK 10/fMCK ns

20 MHz < fMCK  24 MHz 36/fMCK  ns

16 MHz < fMCK  20 MHz 32/fMCK  ns

8 MHz < fMCK  16 MHz 26/fMCK  ns

4 MHz < fMCK  8 MHz

16/fMCK 16/fMCK ns

SCKp cycle time Note 1 tKCY2

1.8 V  VDD < 3.3 V,

1.6 V  Vb  2.0 V

Note 2

fMCK  4 MHz

10/fMCK 10/fMCK ns

4.0 V  VDD  5.5 V, 2.7 V  Vb  4.0 V

KCY2/2  12 tKCY2/2  50 ns

2.7 V  VDD < 4.0 V, 2.3 V  Vb  2.7 V

KCY2/2  18 tKCY2/2  50 ns

SCKp high-/low-level

width

tKH2,

tKL2

1.8 V  VDD < 3.3 V, 1.6 V  Vb  2.0 V Note 2

KCY2/2  50 tKCY2/2  50 ns

4.0 V  VDD  5.5 V, 2.7 V  VDD  4.0 V

1/f

MCK

1/fMCK

30 ns

2.7 V  VDD < 4.0 V, 2.3 V  Vb  2.7 V

1/f

MCK

1/fMCK

30 ns

SIp setup time

(to SCKp) Note 3

tSIK2

1.8 V  VDD < 3.3 V, 1.6 V  VDD  2.0 V Note 2

1/f

MCK

+ 30

1/fMCK

30 ns

SIp hold time

(from SCKp) Note 4

tKSI2

1/f

MCK

+ 31

1/fMCK

31 ns

4.0 V  VDD  5.5 V, 2.7 V  Vb  4.0 V,

Cb = 30 pF, Rb = 1.4 k

2/fMCK +

120

2/fMCK

573

2.7 V  VDD < 4.0 V, 2.3 V  Vb  2.7 V,

Cb = 30 pF, Rb = 2.7 k

2/fMCK +

214

2/fMCK

573

Delay time from

SCKp to SOp

output Note 5

tKSO2

1.8 V  VDD < 3.3 V, 1.6 V  Vb  2.0 V Note 2,

Cb = 30 pF, Rb = 5.5 k

2/fMCK +

573

2/fMCK

573

Notes 1. Transfer rate in the SNOOZE mode: MAX. 1 Mbps

2. Use it with VDD Vb.

3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to

SCKp” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from

SCKp” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

5. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output

becomes “from SCKp” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

Cautions 1. Select the TTL input buffer for the SIp and SCKp pins and the N-ch open drain output (VDD tolerance)

mode for the SOp pin by using port input mode register 1 (PIM1) and port output mode register 1 (POM1).

For VIH and VIL, see the DC characteristics with TTL input buffer selected.

2. CSI01 and CSI11 cannot communicate at different potential.

RL78/G12 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C)

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016

Page 48 of 106

CSI mode connection diagram (during communication at different potential)

RL78

microcontroller

SOp

SCK

User's device

SIp SO

SCKp

<Slave>

Remarks 1. Rb []: Communication line (SOp) pull-up resistance, Cb [F]: Communication line (SOp) load capacitance,

Vb [V]: Communication line voltage

2. p: CSI number (p = 00, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0)

3. f

MCK: Serial array unit operation clock frequency

(Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode

CSI mode serial transfer timing (slave mode) (during communication at different potential)

(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)

KCY2

KL2

KH2

SIK2

KSI2

KSO2

SIp

SOp

SCKp

Input data

Output data

RL78/G12 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C)

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016

Page 49 of 106

CSI mode serial transfer timing (slave mode) (during communication at different potential)

(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)

Input data

Output data

SIp

SOp

tKCY2

tKL2

tKH2

tSIK2 tKSI2

tKSO2

SCKp

Remark p: CSI number (p = 00, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0)

RL78/G12 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C)

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016

Page 50 of 106

(10) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I2C mode)

(TA = 40 to +85C, 1.8 V  VDD  5.5 V, VSS = 0 V)

HS (high-speed

main) Mode

LS (low-speed

main) Mode

Parameter Symbol Conditions

MIN. MAX. MIN. MAX.

Unit

4.0 V  VDD  5.5 V, 2.7 V  Vb  4.0 V,

Cb = 100 pF, Rb = 2.8 k

400Note1 300Note1 kHz

2.7 V  VDD < 4.0 V, 2.3 V  Vb  2.7 V,

Cb = 100 pF, Rb = 2.7 k

400Note1 300Note1 kHz

SCLr clock frequency fSCL

1.8 V  VDD < 3.3 V, 1.6 V  Vb  2.0 V,Note2

Cb = 100 pF, Rb = 5.5 k

300Note1 300Note1 kHz

4.0 V  VDD  5.5 V, 2.7 V  Vb  4.0 V,

Cb = 100 pF, Rb = 2.8 k

1150 1550 ns

2.7 V  VDD < 4.0 V, 2.3 V  Vb  2.7 V,

Cb = 100 pF, Rb = 2.7 k

1150 1550 ns

Hold time when SCLr = “L” tLOW

1.8 V  VDD < 3.3 V, 1.6 V  Vb  2.0 V,Note2

Cb = 100 pF, Rb = 5.5 k

1550 1550 ns

4.0 V  VDD  5.5 V, 2.7 V  Vb  4.0 V,

Cb = 100 pF, Rb = 2.8 k

675 610 ns

2.7 V  VDD < 4.0 V, 2.3 V  Vb  2.7 V,

Cb = 100 pF, Rb = 2.7 k

600 610 ns

Hold time when SCLr = “H” tHIGH

1.8 V  VDD < 3.3 V, 1.6 V  Vb  2.0 V,Note2

Cb = 100 pF, Rb = 5.5 k

610 610 ns

4.0 V  VDD  5.5 V, 2.7 V  Vb  4.0 V,

Cb = 100 pF, Rb = 2.8 k

1/fMCK

+ 190

Note3

1/fMCK

+ 190

Note3

2.7 V  VDD < 4.0 V, 2.3 V  Vb  2.7 V,

Cb = 100 pF, Rb = 2.7 k

1/fMCK

+ 190

Note3

1/fMCK

+ 190

Note3

Data setup time (reception) tSU:DAT

1.8 V  VDD < 3.3 V, 1.6 V  Vb  2.0 V,Note2

Cb = 100 pF, Rb = 5.5 k

1/fMCK

+ 190

Note3

1/fMCK

+ 190

Note3

4.0 V  VDD  5.5 V, 2.7 V  Vb  4.0 V,

Cb = 100 pF, Rb = 2.8 k

0 355 0 355 ns

2.7 V  VDD < 4.0 V, 2.3 V  Vb  2.7 V,

Cb = 100 pF, Rb = 2.7 k

0 355 0 355 ns

Data hold time

(transmission)

tHD:DAT

1.8 V  VDD < 3.3 V, 1.6 V  Vb  2.0 V,Note2

Cb = 100 pF, Rb = 5.5 k

0 405 0 405 ns

Notes 1. The value must also be equal to or less than fMCK/4.

2. Use it with VDD Vb.

3. Set tSU:DAT so that it will not exceed the hold time when SCLr = "L" or SCLr = "H".

Cautions 1. Select the TTL input buffer and the N-ch open drain output (VDD tolerance) mode for the SDAr pin and

the N-ch open drain output (VDD tolerance) mode for the SCLr pin by using port input mode register 1

(PIM1) and port output mode register 1 (POM1). For VIH and VIL, see the DC characteristics with TTL

input buffer selected.

2. IIC01 and IIC11 cannot communicate at different potential.

(Remarks are listed on the next page.)

RL78/G12 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C)

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016

Page 51 of 106

Simplified I2C mode connection diagram (during communication at different potential)

SDAr

SCLr

SDA

SCL

User's device

RL78

microcontroller

Simplified I2C mode serial transfer timing (during communication at different potential)

SDAr

LOW

HIGH

HD : DAT

SCLr

SU : DAT

1/f

SCL

Remarks 1. Rb []: Communication line (SDAr, SCLr) pull-up resistance, Cb [F]: Communication line (SDAr, SCLr)

load capacitance, Vb [V]: Communication line voltage

2. r: IIC Number (r = 00, 20)

3. fMCK: Serial array unit operation clock frequency

(Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode

m: Unit number (m = 0,1), n: Channel number (n = 0))

4. Simplified I2C mode is supported only by the R5F102 products.

RL78/G12 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C)

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016

Page 52 of 106

2.5.2 Serial interface IICA

(TA = 40 to +85C, 1.8 V  VDD  5.5 V, VSS = 0 V)

HS (high-speed main) mode

LS (low-speed main) mode

Standard Mode Fast Mode

Parameter Symbol Conditions

MIN. MAX. MIN. MAX.

Unit

Fast mode: fCLK  3.5 MHz 0 400 kHz SCLA0 clock frequency fSCL

Normal mode: fCLK  1 MHz 0 100 kHz

Setup time of restart condition tSU:STA 4.7 0.6



Hold timeNote 1 tHD:STA 4.0 0.6



Hold time when SCLA0 = “L” tLOW 4.7 1.3



Hold time when SCLA0 = “H” tHIGH 4.0 0.6



Data setup time (reception) tSU:DAT 250 100 ns

Data hold time (transmission)Note 2 tHD:DAT 0 3.45 0 0.9



Setup time of stop condition tSU:STO 4.0 0.6



Bus-free time tBUF 4.7 1.3



Notes 1. The first clock pulse is generated after this period when the start/restart condition is detected.

2. The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK

(acknowledge) timing.

Caution Only in the 30-pin products, the values in the above table are applied even when bit 2 (PIOR2) in the

peripheral I/O redirection register (PIOR) is 1. At this time, the pin characteristics (IOH1, IOL1, VOH1, VOL1) must

satisfy the values in the redirect destination.

Remark The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up

resistor) at that time in each mode are as follows.

Normal mode: Cb = 400 pF, Rb = 2.7 k

Fast mode: Cb = 320 pF, Rb = 1.1 k

IICA serial transfer timing

LOW

HIGH

BUF

HD:DAT

SU:DAT

HD:STA

SU:STA

HD:STA

SU:STO

SCLA0

SDAA0

Stop

condition

Start

condition

Restart

condition

Stop

condition

<R>

RL78/G12 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C)

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016

Page 53 of 106

2.6 Analog Characteristics

2.6.1 A/D converter characteristics

Classification of A/D converter characteristics

Reference Voltage Input channel

Reference voltage (+) = AVREFP

Reference voltage () = AVREFM

Reference voltage (+) = VDD

Reference voltage () = VSS

Reference voltage (+) = VBGR

Reference voltage () = AVREFM

ANI0 to ANI3 Refer to 28.6.1 (1).

ANI16 to ANI22 Refer to 28.6.1 (2).

Refer to 28.6.1 (4).

Internal reference voltage

Temperature sensor

output voltage

Refer to 28.6.1 (1).

Refer to 28.6.1 (3).



(1) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage () = AVREFM/ANI1

(ADREFM = 1), target pin: ANI2, ANI3, internal reference voltage, and temperature sensor output voltage

(TA = 40 to +85C, 1.8 V  AVREFP  VDD  5.5 V, VSS = 0 V, Reference voltage (+) = AVREFP, Reference voltage () =

AVREFM = 0 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Resolution RES 8 10 bit

1.2 3.5 LSB Overall errorNote 1 AINL 10-bit resolution

AVREFP = VDD Note 3 1.2 7.0 Note 4 LSB

3.6 V  VDD  5.5 V 2.125 39



2.7 V  VDD  5.5 V 3.1875 39



17 39



10-bit resolution

Target pin: ANI2, ANI3

1.8 V  VDD  5.5 V

57 95



3.6 V  VDD  5.5 V 2.375 39



2.7 V  VDD  5.5 V 3.5625 39



Conversion time tCONV

10-bit resolution

Target pin: Internal

reference voltage, and

temperature sensor

output voltage

(HS (high-speed main)

mode)

2.4 V  VDD  5.5 V 17 39



0.25 %FSRZero-scale errorNotes 1, 2 EZS 10-bit resolution

AVREFP = VDD Note 3 0.50 Note 4 %FSR

0.25 %FSRFull-scale errorNotes 1, 2 EFS 10-bit resolution

AVREFP = VDD Note 3 0.50 Note 4 %FSR

2.5 LSB Integral linearity errorNote 1 ILE 10-bit resolution

AVREFP = VDD Note 3 5.0 Note 4 LSB

1.5 LSB Differential linearity error

Note 1

DLE 10-bit resolution

AVREFP = VDD Note 3 2.0 Note 4 LSB

ANI2, ANI3 0 AVREFP V

Internal reference voltage

(2.4 V  VDD  5.5 V, HS (high-speed main) mode)

VBGR Note 5 V

Analog input voltage VAIN

Temperature sensor output voltage

(2.4 V  VDD  5.5 V, HS (high-speed main) mode)

VTMPS25 Note 5 V

(Notes are listed on the next page.)

RL78/G12 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C)

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016

Page 54 of 106

Notes 1. Excludes quantization error (1/2 LSB).

2. This value is indicated as a ratio (%FSR) to the full-scale value.

3. When AVREFP < VDD, the MAX. values are as follows.

Overall error: Add 1.0 LSB to the MAX. value when AVREFP = VDD.

Zero-scale error/Full-scale error: Add 0.05%FSR to the MAX. value when AVREFP = VDD.

Integral linearity error/ Differential linearity error: Add 0.5 LSB to the MAX. value when AVREFP = VDD.

4. Values when the conversion time is set to 57



s (min.) and 95



s (max.).

5. Refer to 28.6.2 Temperature sensor/internal reference voltage characteristics.

(2) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage () = AVREFM/ANI1

(ADREFM = 1), target pin: ANI16 to ANI22

(TA = 40 to +85C, 1.8 V  AVREFP  VDD  5.5 V, VSS = 0 V, Reference voltage (+) = AVREFP, Reference voltage () =

AVREFM = 0 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Resolution RES 8 10 bit

1.2 5.0 LSB Overall error Note 1 AINL

10-bit resolution

AVREFP = VDD Note 3 1.2 8.5 Note 4 LSB

3.6 V  VDD  5.5 V 2.125 39



2.7 V  VDD  5.5 V 3.1875 39



17 39



Conversion time tCONV 10-bit resolution

Target ANI pin: ANI16 to ANI22

1.8 V  VDD  5.5 V

57 95



0.35 %FSRZero-scale error Notes 1, 2 EZS 10-bit resolution

AVREFP = VDD Note 3 0.60 Note 4 %FSR

0.35 %FSRFull-scale error Notes 1, 2 EFS 10-bit resolution

AVREFP = VDD Note 3 0.60 Note 4 %FSR

3.5 LSB Integral linearity error Note 1 ILE 10-bit resolution

AVREFP = VDD Note 3 6.0 Note 4 LSB

2.0 LSB

Differential linearity

error Note 1

DLE 10-bit resolution

AVREFP = VDD Note 3 2.5 Note 4 LSB

Analog input voltage VAIN ANI16 to ANI22 0 AVREFP

and VDD

Notes 1. Excludes quantization error (1/2 LSB).

2. This value is indicated as a ratio (%FSR) to the full-scale value.

3. When AVREFP  VDD, the MAX. values are as follows.

Overall error: Add 4.0 LSB to the MAX. value when AVREFP = VDD.

Zero-scale error/Full-scale error: Add 0.20%FSR to the MAX. value when AVREFP = VDD.

Integral linearity error/ Differential linearity error: Add 2.0 LSB to the MAX. value when AVREFP = VDD.

4. When the conversion time is set to 57



s (min.) and 95



s (max.).

RL78/G12 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C)

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016

Page 55 of 106

(3) When reference voltage (+) = VDD (ADREFP1 = 0, ADREFP0 = 0), reference voltage () = VSS (ADREFM = 0),

target pin: ANI0 to ANI3, ANI16 to ANI22, internal reference voltage, and temperature sensor output voltage

(TA = 40 to +85C, 1.8 V  VDD  5.5 V, VSS = 0 V, Reference voltage (+) = VDD, Reference voltage () = VSS)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Resolution RES 8 10 bit

1.2 7.0 LSB Overall errorNote 1 AINL 10-bit resolution

1.2 10.5 Note 3 LSB

3.6 V  VDD  5.5 V 2.125 39



2.7 V  VDD  5.5 V 3.1875 39



17 39



Conversion time tCONV 10-bit resolution

Target pin: ANI0 to ANI3,

ANI16 to ANI22 1.8 V  VDD  5.5 V

57 95



3.6 V  VDD  5.5 V 2.375 39



2.7 V  VDD  5.5 V 3.5625 39



Conversion time tCONV 10-bit resolution

Target pin: internal reference

voltage, and temperature

sensor output voltage (HS

(high-speed main) mode)

2.4 V  VDD  5.5 V 17 39



0.60 %FSRZero-scale errorNotes 1, 2 EZS 10-bit resolution

0.85

Note 3

%FSR

0.60 %FSRFull-scale errorNotes 1, 2 EFS 10-bit resolution

0.85

Note 3

%FSR

4.0 LSB Integral linearity errorNote 1 ILE 10-bit resolution

6.5 Note 3 LSB

2.0 LSB Differential linearity error Note 1 DLE 10-bit resolution

2.5 Note 3 LSB

ANI0 to ANI3, ANI16 to ANI22 0 VDD V

Internal reference voltage

(2.4 V  VDD  5.5 V, HS (high-speed main) mode)

VBGR Note 4 V

Analog input voltage VAIN

Temperature sensor output voltage

(2.4 V  VDD  5.5 V, HS (high-speed main) mode)

VTMPS25 Note 4 V

Notes 1. Excludes quantization error (1/2 LSB).

2. This value is indicated as a ratio (%FSR) to the full-scale value.

3. When the conversion time is set to 57



s (min.) and 95



s (max.).

4. Refer to 28.6.2 Temperature sensor/internal reference voltage characteristics.

RL78/G12 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C)

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016

Page 56 of 106

(4) When reference voltage (+) = Internal reference voltage (ADREFP1 = 1, ADREFP0 = 0), reference voltage () =

AVREFM (ADREFM = 1), target pin: ANI0, ANI2, ANI3, and ANI16 to ANI22

(TA = 40 to +85C, 2.4 V  VDD  5.5 V, VSS = 0 V, Reference voltage (+) = VBGR Note 3, Reference voltage () = AVREFM

Note 4= 0 V, HS (high-speed main) mode)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Resolution RES 8 bit

Conversion time tCONV 8-bit resolution 17 39



Zero-scale errorNotes 1, 2 EZS 8-bit resolution 0.60 %FSR

Integral linearity errorNote 1 ILE 8-bit resolution 2.0 LSB

Differential linearity error Note 1 DLE 8-bit resolution 1.0 LSB

Analog input voltage VAIN 0 VBGR Note 3 V

Notes 1. Excludes quantization error (1/2 LSB).

2. This value is indicated as a ratio (%FSR) to the full-scale value.

3. Refer to 28.6.2 Temperature sensor/internal reference voltage characteristics.

4. When reference voltage () = VSS, the MAX. values are as follows.

Zero-scale error: Add 0.35%FSR to the MAX. value when reference voltage () = AVREFM.

Integral linearity error: Add 0.5 LSB to the MAX. value when reference voltage () = AVREFM.

Differential linearity error: Add 0.2 LSB to the MAX. value when reference voltage () = AVREFM.

RL78/G12 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C)

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016

Page 57 of 106

2.6.2 Temperature sensor/internal reference voltage characteristics

(TA = 40 to +85C, 2.4 V  VDD  5.5 V, VSS = 0 V, HS (high-speed main) mode

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Temperature sensor output voltage VTMPS25 Setting ADS register = 80H,

TA = +25C

1.05 V

Internal reference voltage VBGR Setting ADS register = 81H 1.38 1.45 1.50 V

Temperature coefficient FVTMPS Temperature sensor output

voltage that depends on the

temperature

3.6 mV/C

Operation stabilization wait time tAMP 5



2.6.3 POR circuit characteristics

(TA = 40 to +85C, VSS = 0 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

VPOR Power supply rise time 1.47 1.51 1.55 V Detection voltage

VPDR Power supply fall time 1.46 1.50 1.54 V

Minimum pulse width Note TPW 300



Note Minimum time required for a POR reset when VDD exceeds below VPDR. This is also the minimum time required

for a POR reset from when VDD exceeds below 0.7 V to when VDD exceeds VPOR while STOP mode is entered or

the main system clock is stopped through setting bit 0 (HIOSTOP) and bit 7 (MSTOP) in the clock operation

status control register (CSC).

POR

PDR

or 0.7 V

Supply voltage (V

)

RL78/G12 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C)

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016

Page 58 of 106

2.6.4 LVD circuit characteristics

LVD Detection Voltage of Reset Mode and In terrupt Mode

(TA = 40 to +85C, VPDR  VDD  5.5 V, VSS = 0 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Power supply rise time 3.98 4.06 4.14 V VLVD0

Power supply fall time 3.90 3.98 4.06 V

Power supply rise time 3.68 3.75 3.82 V VLVD1

Power supply fall time 3.60 3.67 3.74 V

Power supply rise time 3.07 3.13 3.19 V VLVD2

Power supply fall time 3.00 3.06 3.12 V

Power supply rise time 2.96 3.02 3.08 V VLVD3

Power supply fall time 2.90 2.96 3.02 V

Power supply rise time 2.86 2.92 2.97 V VLVD4

Power supply fall time 2.80 2.86 2.91 V

Power supply rise time 2.76 2.81 2.87 V VLVD5

Power supply fall time 2.70 2.75 2.81 V

Power supply rise time 2.66 2.71 2.76 V VLVD6

Power supply fall time 2.60 2.65 2.70 V

Power supply rise time 2.56 2.61 2.66 V VLVD7

Power supply fall time 2.50 2.55 2.60 V

Power supply rise time 2.45 2.50 2.55 V VLVD8

Power supply fall time 2.40 2.45 2.50 V

Power supply rise time 2.05 2.09 2.13 V VLVD9

Power supply fall time 2.00 2.04 2.08 V

Power supply rise time 1.94 1.98 2.02 V VLVD10

Power supply fall time 1.90 1.94 1.98 V

Power supply rise time 1.84 1.88 1.91 V

Detection supply voltage

VLVD11

Power supply fall time 1.80 1.84 1.87 V

Minimum pulse width tLW 300



Detection delay time 300



RL78/G12 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C)

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016

Page 59 of 106

LVD detection voltage of interrupt & reset mode

(TA = 40 to +85C, VPDR  VDD  5.5 V, VSS = 0 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

VLVDB0 VPOC2, VPOC1, VPOC0 = 0, 0, 1, falling reset voltage 1.80 1.84 1.87 V

Rising reset release voltage 1.94 1.98 2.02 V VLVDB1 LVIS1, LVIS0 = 1, 0

Falling interrupt voltage 1.90 1.94 1.98 V

Rising reset release voltage 2.05 2.09 2.13 V VLVDB2 LVIS1, LVIS0 = 0, 1

Falling interrupt voltage 2.00 2.04 2.08 V

Rising reset release voltage 3.07 3.13 3.19 V VLVDB3

LVIS1, LVIS0 = 0, 0

Falling interrupt voltage 3.00 3.06 3.12 V

VLVDC0 VPOC2, VPOC1, VPOC0 = 0, 1, 0, falling reset voltage 2.40 2.45 2.50 V

Rising reset release voltage 2.56 2.61 2.66 V VLVDC1 LVIS1, LVIS0 = 1, 0

Falling interrupt voltage 2.50 2.55 2.60 V

Rising reset release voltage 2.66 2.71 2.76 V VLVDC2 LVIS1, LVIS0 = 0, 1

Falling interrupt voltage 2.60 2.65 2.70 V

Rising reset release voltage 3.68 3.75 3.82 V VLVDC3

LVIS1, LVIS0 = 0, 0

Falling interrupt voltage 3.60 3.67 3.74 V

VLVDD0 VPOC2, VPOC1, VPOC1 = 0, 1, 1, falling reset voltage 2.70 2.75 2.81 V

Rising reset release voltage 2.86 2.92 2.97 V VLVDD1 LVIS1, LVIS0 = 1, 0

Falling interrupt voltage 2.80 2.86 2.91 V

Rising reset release voltage 2.96 3.02 3.08 V VLVDD2 LVIS1, LVIS0 = 0, 1

Falling interrupt voltage 2.90 2.96 3.02 V

Rising reset release voltage 3.98 4.06 4.14 V

Interrupt and reset

mode

VLVDD3

LVIS1, LVIS0 = 0, 0

Falling interrupt voltage 3.90 3.98 4.06 V

2.6.5 Power supply voltage rising slope characteristics

(TA = 40 to +85C, VSS = 0 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Power supply voltage rising slope SVDD 54 V/ms

Caution Make sure to keep the internal reset state by the LVD circuit or an external reset until VDD reaches the

operating voltage range shown in 28.4 AC Characteristics.

RL78/G12 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C)

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016

Page 60 of 106

2.7 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics

(TA = 40 to +85C, VSS = 0 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Data retention supply voltage VDDDR 1.46

Note 5.5 V

Note This depends on the POR detection voltage. For a falling voltage, data in RAM are retained until the voltage

reaches the level that triggers a POR reset but not once it reaches the level at which a POR reset is generated.

STOP instruction execution

Standby release signal

(interrupt request)

STOP mode

RAM data retention

DDDR

Operation mode

2.8 Flash Memory Programming Characteristics

(TA = 40 to +85C, 1.8 V  VDD  5.5 V, VSS = 0 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

System clock frequency fCLK 1 24 MHz

Code flash memory rewritable times

Notes 1, 2, 3

Retained for 20 years

TA = 85°C

1,000

Retained for 1 year

TA = 25°C

1,000,000

Retained for 5 years

TA = 85°C

100,000

Data flash memory rewritable times

Notes 1, 2, 3

Cerwr

Retained for 20 years

TA = 85°C

10,000

Times

Notes 1. 1 erase + 1 write after the erase is regarded as 1 rewrite. The retaining years are until next rewrite after the

rewrite.

2. When using flash memory programmer and Renesas Electronics self programming library

3. These are the characteristics of the flash memory and the results obtained from reliability testing by

Renesas Electronics Corporation.

<R>

RL78/G12 2. ELECTRICAL SPECIFICATIONS (TA = 40 to +85C)

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016

Page 61 of 106

2.9 Dedicated Flash Memory Programmer Communication (UART)

(TA = 40 to +85C, 1.8 V  VDD  5.5 V, VSS = 0 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Transfer rate During serial programming 115,200 1,000,000 bps

2.10 Timing of Entry to Flash Memory Programming Modes

(TA = 40 to +85C, 1.8 V  VDD  5.5 V, VSS = 0 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Time to complete the communication for the initial

setting after the external reset is released

tSUINIT POR and LVD reset are

released before external

reset release

100 ms

Time to release the external reset after the TOOL0

pin is set to the low level

tSU POR and LVD reset are

released before external

reset release



Time to hold the TOOL0 pin at the low level after

the external reset is released

(excluding the processing time of the firmware to

control the flash memory)

tHD POR and LVD reset are

released before external

reset release

1 ms

RESET

TOOL0

<1> <2> <3>

SUINIT

tHD + software

processing

time 1-byte data for

setting mode

<4>

<1> The low level is input to the TOOL0 pin.

<2> The external reset is released (POR and LVD reset must be released before the external

reset is released.).

<3> The TOOL0 pin is set to the high level.

<4> Setting of the flash memory programming mode by UART reception and complete the baud

rate setting.

Remark t

SUINIT: Communication for the initial setting must be completed within 100 ms after the external reset is released

during this period.

tSU: Time to release the external reset after the TOOL0 pin is set to the low level

tHD: Time to hold the TOOL0 pin at the low level after the external reset is released (excluding the processing

time of the firmware to control the flash memory)

RL78/G12

3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C)

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016

Page 62 of 106

3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = 40 to

+105C)

This chapter describes the following electrical specifications.

Target products G: Industrial applications TA = -40 to +105C

R5F102xxGxx

Cautions 1. The RL78 microcontrollers have an on-chip debug function, which is provided for development and

evaluation. Do not use the on-chip debug function in products designated for mass production, because the

guaranteed number of rewritable times of the flash memory may be exceeded when this function is used,

and product reliability therefore cannot be guaranteed. Renesas Electronics is not liable for problems

occurring when the on-chip debug function is used.

2. The pins mounted depend on the product. Refer to 2.1 Port Functions to 2.2.1 Functions for each product.

3. Please contact Renesas Electronics sales office for derating of operation under TA = +85C to +105C.

Derating is the systematic reduction of load for the sake of improved reliability.

Remark When the RL78 microcontroller is used in the range of TA = -40 to +85 °C, see CHAPTER 28

ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85 °C).

There are following differences between the products "G: Industrial applications (TA = -40 to +105C)" and the products “A:

Consumer applications, and D: Industrial applications”.

Application Parameter

A: Consumer applications,

D: Industrial applications

G: Industrial applications

Operating ambient temperature TA = -40 to +85C TA = -40 to +105C

Operating mode

Operating voltage range

HS (high-speed main) mode:

2.7 V  VDD  5.5 V@1 MHz to 24 MHz

2.4 V  VDD  5.5 V@1 MHz to 16 MHz

LS (low-speed main) mode:

1.8 V  VDD  5.5 V@1 MHz to 8 MHz

HS (high-speed main) mode only:

2.7 V  VDD  5.5 V@1 MHz to 24 MHz

2.4 V  VDD  5.5 V@1 MHz to 16 MHz

High-speed on-chip oscillator clock

accuracy

R5F102 products, 1.8 V  VDD  5.5 V:

1.0%@ TA = -20 to +85C

1.5%@ TA = -40 to -20C

R5F103 products, 1.8 V  VDD  5.5 V:

5.0%@ TA = -40 to +85C

R5F102 products, 2.4 V  VDD  5.5 V:

2.0%@ TA = +85 to +105C

1.0%@ TA = -20 to +85C

1.5%@ TA = -40 to -20C

Serial array unit UART

CSI: fCLK/2 (supporting 12 Mbps), fCLK/4

Simplified I2C communication

UART

CSI: fCLK/4

Simplified I2C communication

Voltage detector Rise detection voltage: 1.88 V to 4.06 V

(12 levels)

Fall detection voltage: 1.84 V to 3.98 V

(12 levels)

Rise detection voltage: 2.61 V to 4.06 V

(8 levels)

Fall detection voltage: 2.55 V to 3.98 V

(8 levels)

Remark The electrical characteristics of the products G: Industrial applications (TA = -40 to +105C) are different from

those of the products “A: Consumer applications, and D: Industrial applications”. For details, refer to 29.1 to

29.10.

<R>

RL78/G12

3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C)

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016

Page 63 of 106

3.1 Absolute Maximum Ratings

Absolute Maximum Ratings (TA = 25C)

Parameter Symbols Conditions Ratings Unit

Supply Voltage VDD 0.5 to + 6.5 V

REGC terminal input

voltageNote1

VIREGC REGC 0.3 to +2.8

and 0.3 to VDD + 0.3

Note 2

VI1 Other than P60, P61 0.3 to VDD + 0.3Note 3 V Input Voltage

VI2 P60, P61 (N-ch open drain) 0.3 to 6.5 V

Output Voltage VO 0.3 to VDD + 0.3Note 3 V

Analog input voltage VAI 20, 24-pin products: ANI0 to ANI3, ANI16 to ANI22

30-pin products: ANI0 to ANI3, ANI16 to ANI19

0.3 to VDD + 0.3

and 0.3 to

AVREF(+)+0.3 Notes 3, 4

Per pin Other than P20 to P23 40 mA

All the terminals other than P20 to P23 170 mA

20-, 24-pin products: P40 to P42

30-pin products: P00, P01, P40, P120

70 mA

IOH1

Total of all pins

20-, 24-pin products: P00 to P03Note 5,

P10 to P14

30-pin products: P10 to P17, P30, P31,

P50, P51, P147

100 mA

Per pin 0.5 mA

Output current, high

IOH2

Total of all pins

P20 to P23

2 mA

Per pin Other than P20 to P23 40 mA

All the terminals other than P20 to P23 170 mA

20-, 24-pin products: P40 to P42

30-pin products: P00, P01, P40, P120

70 mA

IOL1

Total of all pins

20-, 24-pin products: P00 to P03 Note 5,

P10 to P14, P60, P61

30-pin products: P10 to P17, P30, P31,

P50, P51, P60, P61, P147

100 mA

Per pin 1 mA

Output current, low

IOL2

Total of all pins

P20 to P23

5 mA

Operating ambient

temperature

TA 40 to +105 C

Storage temperature Tstg 65 to +150 C

Notes 1. 30-pin product only.

2. Connect the REGC pin to VSS via a capacitor (0.47 to 1 F). This value determines the absolute maximum

rating of the REGC pin. Do not use it with voltage applied.

3. Must be 6.5 V or lower.

4. Do not exceed AVREF(+) + 0.3 V in case of A/D conversion target pin.

5. 24-pin products only.

Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter.

That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering

physical damage, and therefore the product must be used under conditions that ensure that the absolute

maximum ratings are not exceeded.

Remarks 1. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port

pins.

2. AVREF(+) : + side reference voltage of the A/D converter.

3. V

SS : Reference voltage

RL78/G12

3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C)

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016

Page 64 of 106

3.2 Oscillator Characteristics

3.2.1 X1 oscillator characteristics

(TA = 40 to +105C, 2.4 V  VDD  VDD  5.5 V, VSS = 0 V)

Parameter Resonator Conditions MIN. TYP. MAX. Unit

2.7 V  VDD  5.5 V 1.0 20.0

X1 clock oscillation

frequency (fX)Note

Ceramic resonator /

crystal oscillator 2.4 V  VDD < 2.7 V 1.0 8.0

MHz

Note Indicates only permissible oscillator frequency ranges. Refer to AC Characteristics for instruction execution time.

Request evaluation by the manufacturer of the oscillator circuit mounted on a board to check the oscillator

characteristics.

Caution Since the CPU is started by the high-speed on-chip oscillator clock after a reset release, check the X1 clock

oscillation stabilization time using the oscillation stabilization time counter status register (OSTC) by the user.

Determine the oscillation stabilization time of the OSTC register and the oscillation stabilization time select

Remark When using the X1 oscillator, refer to 5.4 System Clock Oscillator.

3.2.2 On-chip oscillator characteristics

(TA = 40 to +105C, 2.4 V  VDD  5.5 V, VSS = 0 V)

Oscillators Parameters Conditions MIN. TYP. MAX. Unit

High-speed on-chip oscillator

clock frequency Notes 1, 2

fIH 1 24 MHz

TA = 20 to +85C -1.0

+1.0 %

TA = 40 to 20C -1.5

+1.5 %

High-speed on-chip oscillator

clock frequency accuracy R5F102 products

TA = +85 to +105C -2.0

+2.0 %

Low-speed on-chip oscillator

clock frequency

fIL 15 kHz

Low-speed on-chip oscillator

clock frequency accuracy

-15 +15 %

Notes 1. High-speed on-chip oscillator frequency is selected by bits 0 to 3 of option byte (000C2H) and bits 0 to 2 of

HOCODIV register.

2. This only indicates the oscillator characteristics. Refer to AC Characteristics for instruction execution time.

RL78/G12

3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C)

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016

Page 65 of 106

3.3 DC Characteristics

3.3.1 Pin characteristics

(TA = 40 to +105C, 2.4 V  VDD  5.5 V, VSS = 0 V) (1/4)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

20-, 24-pin products:

Per pin for P00 to P03Note 4,

P10 to P14, P40 to P42

30-pin products:

Per pin for P00, P01, P10 to P17, P30,

P31, P40, P50, P51, P120, P147

3.0

Note 2

4.0 V  VDD  5.5 V 9.0 mA

2.7 V  VDD < 4.0 V 6.0 mA

20-, 24-pin products:

Total of P40 to P42

30-pin products:

Total of P00, P01, P40, P120

(When duty  70% Note 3)

2.4 V  VDD < 2.7 V 4.5 mA

4.0 V  VDD  5.5 V 27.0 mA

2.7 V  VDD < 4.0 V 18.0 mA

20-, 24-pin products:

Total of P00 to P03Note 4, P10 to P14

30-pin products:

Total of P10 to P17, P30, P31,

P50, P51, P147

(When duty  70% Note 3)

2.4 V  VDD < 2.7 V 10.0 mA

IOH1

Total of all pins (When duty  70%Note 3)

36.0 mA

Per pin for P20 to P23 0.1 mA

Output current, highNote 1

IOH2

Total of all pins 0.4 mA

Notes 1. value of current at which the device operation is guaranteed even if the current flows from the VDD pin to an

output pin.

2. However, do not exceed the total current value.

3. The output current value under conditions where the duty factor  70%.

If duty factor  70%: The output current value can be calculated with the following expression (where n

represents the duty factor as a percentage).

 Total output current of pins = (IOH × 0.7)/(n × 0.01)

<Example> Where n = 80% and IOH = 10.0 mA

Total output current of pins = (10.0 × 0.7)/(80 × 0.01)  8.7 mA

However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A

current higher than the absolute maximum rating must not flow into one pin.

4. 24-pin products only.

Caution P10 to P12 and P41 for 20-pin products, P01, P10 to P12, and P41 for 24-pin products, and P00, P10 to P15,

P17, and P50 for 30-pin products do not output high level in N-ch open-drain mode.

Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port

pins.

RL78/G12

3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C)

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016

Page 66 of 106

(TA = 40 to +105C, 2.4 V  VDD  5.5 V, VSS = 0 V) (2/4)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

20-, 24-pin products:

Per pin for P00 to P03Note 4,

P10 to P14, P40 to P42

30-pin products:

Per pin for P00, P01, P10 to P17, P30,

P31, P40, P50, P51, P120, P147

8.5

Note 2

Per pin for P60, P61

15.0

Note 2

4.0 V  VDD  5.5 V 25.5 mA

2.7 V  VDD < 4.0 V 9.0 mA

20-, 24-pin products:

Total of P40 to P42

30-pin products:

Total of P00, P01, P40, P120

(When duty  70% Note 3)

2.4 V  VDD < 2.7 V 1.8 mA

4.0 V  VDD  5.5 V 40.0 mA

2.7 V  VDD < 4.0 V 27.0 mA

20-, 24-pin products:

Total of P00 to P03Note 4,

P10 to P14, P60, P61

30-pin products:

Total of P10 to P17, P30, P31, P50,

P51, P60, P61, P147

(When duty  70% Note 3)

2.4 V  VDD < 2.7 V 5.4 mA

IOL1

Total of all pins (When duty  70%Note 3)

65.5 mA

Per pin for P20 to P23 0.4 mA

Output current, lowNote 1

IOL2

Total of all pins 1.6 mA

Notes 1. Value of current at which the device operation is guaranteed even if the current flows from an output pin to

the VSS pin.

2. However, do not exceed the total current value.

3. The output current value under conditions where the duty factor  70%.

If duty factor  70%: The output current value can be calculated with the following expression (where n

represents the duty factor as a percentage).

 Total output current of pins = (IOL × 0.7)/(n × 0.01)

<Example> Where n = 80% and IOL = 10.0 mA

Total output current of pins = (10.0 × 0.7)/(80 × 0.01)  8.7 mA

However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A

current higher than the absolute maximum rating must not flow into one pin.

4. 24-pin products only.

Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port

pins.

RL78/G12

3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C)

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016

Page 67 of 106

(TA = 40 to +105C, 2.4 V  VDD  5.5 V, VSS = 0 V) (3/4)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

VIH1 Normal input buffer

20-, 24-pin products: P00 to P03Note 2, P10 to P14,

P40 to P42

30-pin products: P00, P01, P10 to P17, P30, P31,

P40, P50, P51, P120, P147

0.8VDD VDD V

4.0 V  VDD  5.5 V 2.2 VDD V

3.3 V  VDD < 4.0 V 2.0 VDD V

VIH2 TTL input buffer

20-, 24-pin products: P10, P11

30-pin products: P01, P10,

P11, P13 to P17

2.4 V  VDD < 3.3 V 1.5 VDD V

VIH3 Normal input buffer

P20 to P23

0.7VDD VDD V

VIH4 P60, P61 0.7VDD 6.0 V

Input voltage, high

VIH5 P121, P122, P125Note 1, P137, EXCLK, RESET 0.8VDD VDD V

VIL1 Normal input buffer

20-, 24-pin products: P00 to P03Note 2, P10 to P14,

P40 to P42

30-pin products: P00, P01, P10 to P17, P30, P31,

P40, P50, P51, P120, P147

0 0.2VDD V

4.0 V  VDD  5.5 V 0 0.8 V

3.3 V  VDD < 4.0 V 0 0.5 V

VIL2 TTL input buffer

20-, 24-pin products: P10, P11

30-pin products: P01, P10,

P11, P13 to P17

2.4 V  VDD < 3.3 V 0 0.32 V

VIL3 P20 to P23 0 0.3VDD V

VIL4 P60, P61 0 0.3VDD V

Input voltage, low

VIL5 P121, P122, P125Note 1, P137, EXCLK, RESET 0 0.2VDD V

4.0 V  VDD  5.5 V,

IOH1 = 3.0 mA

VDD0.7 V

2.7 V  VDD  5.5 V,

IOH1 = 2.0 mA

VDD0.6 V

VOH1 20-, 24-pin products:

P00 to P03Note 2, P10 to P14,

P40 to P42

30-pin products:

P00, P01, P10 to P17, P30,

P31, P40, P50, P51, P120,

P147

2.4 V  VDD  5.5 V,

IOH1 = 1.5 mA

VDD0.5 V

Output voltage, high

VOH2 P20 to P23 IOH2 = 100



A VDD0.5 V

Notes 1. 20, 24-pin products only.

2. 24-pin products only.

Caution The maximum value of VIH of pins P10 to P12 and P41 for 20-pin products, P01, P10 to P12, and P41 for 24-

pin products, and P00, P10 to P15, P17, and P50 for 30-pin products is VDD even in N-ch open-drain mode.

High level is not output in the N-ch open-drain mode.

Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port

pins.

RL78/G12

3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C)

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016

Page 68 of 106

(TA = 40 to +105C, 2.4 V  VDD  5.5 V, VSS = 0 V) (4/4)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

4.0 V  VDD  5.5 V,

IOL1 = 8.5 mA

0.7 V

2.7 V  VDD  5.5 V,

IOL1 = 3.0 mA

0.6 V

2.7 V  VDD  5.5 V,

IOL1 = 1.5 mA

0.4 V

VOL1 20-, 24-pin products:

P00 to P03Note, P10 to P14,

P40 to P42

30-pin products: P00, P01,

P10 to P17, P30, P31, P40,

P50, P51, P120, P147

2.4 V  VDD  5.5 V,

IOL1 = 0.6 mA

0.4 V

VOL2 P20 to P23 IOL2 = 400



A 0.4 V

4.0 V  VDD  5.5 V,

IOL1 = 15.0 mA

2.0 V

4.0 V  VDD  5.5 V,

IOL1 = 5.0 mA

0.4 V

2.7 V  VDD  5.5 V,

IOL1 = 3.0 mA

0.4 V

Output voltage, low

VOL3 P60, P61

2.4 V  VDD  5.5 V,

IOL1 = 2.0 mA

0.4 V

ILIH1 Other than P121,

P122

VI = VDD 1



Input port or external

clock input



Input leakage current,

high

ILIH2 P121, P122

(X1, X2/EXCLK)

VI = VDD

When resonator

connected



ILIL1 Other than P121,

P122

VI = VSS 1



Input port or external

clock input

1



Input leakage current,

low

ILIL2 P121, P122

(X1, X2/EXCLK)

VI = VSS

When resonator

connected

10



On-chip pull-up

resistance

RU 20-, 24-pin products:

P00 to P03Note, P10 to P14,

P40 to P42, P125, RESET

30-pin products: P00, P01,

P10 to P17, P30, P31, P40,

P50, P51, P120, P147

VI = VSS, input port 10 20 100 k

Note 24-pin products only.

Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port

pins.

RL78/G12

3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C)

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016

Page 69 of 106

3.3.2 Supply current characteristics

(1) 20-, 24-pin products

(TA = 40 to +105C, 2.4 V  VDD  5.5 V, VSS = 0 V) (1/2)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

VDD = 5.0 V 1.5

Basic

operation

VDD = 3.0 V 1.5

VDD = 5.0 V 3.3 5.3

= 24 MHz

Note 3

VDD = 3.0 V 3.3 5.3



VDD = 5.0 V 2.5 3.9

Supply

currentNote 1

IDD1 Operating

mode

= 16 MHz

Note 3

VDD = 3.0 V 2.5 3.9

Square wave input 2.8 4.7

= 20 MHz

Note 2

= 5.0 V

Resonator connection 3.0 4.8

Square wave input 2.8 4.7

= 20 MHz

Note 2

= 3.0 V

Resonator connection 3.0 4.8



Square wave input 1.8 2.8

= 10 MHz

Note 2

= 5.0 V

Resonator connection 1.8 2.8



Square wave input 1.8 2.8

HS (High-speed

main) mode

Note 4

= 10 MHz

Note 2

= 3.0 V

Normal

operation

Resonator connection 1.8 2.8



Notes 1. Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is

fixed to VDD or VSS. The values below the MAX. column include the peripheral operation current. However,

not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down

resistors and the current flowing during data flash rewrite.

2. When high-speed on-chip oscillator clock is stopped.

3. When high-speed system clock is stopped

4. Relationship between operation voltage width, operation frequency of CPU and operation mode is as

follows.

HS(High speed main) mode: VDD = 2.7 V to 5.5 V @1 MHz to 24 MHz

DD = 2.4 V to 5.5 V @1 MHz to 16 MHz

Remarks 1. f

MX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock

frequency)

2. f

IH: high-speed on-chip oscillator clock frequency

3. Temperature condition of the TYP. value is TA = 25C.

RL78/G12

3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C)

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016

Page 70 of 106

(1) 20-, 24-pin products

(TA = 40 to +105C, 2.4 V  VDD  5.5 V, VSS = 0 V) (2/2)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

VDD = 5.0 V 440 2230fIH = 24 MHzNote 4

VDD = 3.0 V 440 2230



VDD = 5.0 V 400 1650fIH = 16 MHzNote 4

VDD = 3.0 V 400 1650



Square wave input 280 1900

fMX = 20 MHzNote 3,

VDD = 5.0 V

Resonator connection 450 2000



Square wave input 280 1900

fMX = 20 MHzNote 3,

VDD = 3.0 V Resonator connection 450 2000



Square wave input 190 1010

fMX = 10 MHzNote 3,

VDD = 5.0 V Resonator connection 260 1090



Square wave input 190 1010

IDD2 Note 2 HALT

mode

HS (High-speed

main) mode

Note 6

fMX = 10 MHzNote 3,

VDD = 3.0 V

Resonator connection 260 1090



TA = 40C 0.19 0.50

TA = +25C 0.24 0.50

TA = +50C 0.32 0.80

TA = +70C 0.48 1.20

TA = +85C 0.74 2.20

Supply

currentNote 1

IDD3 Note 5 STOP

mode

TA = +105C 1.50 10.20



Notes 1. Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is

fixed to VDD or VSS. The values below the MAX. column include the peripheral operation current. However,

not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down

resistors and the current flowing during data flash rewrite.

2. During HALT instruction execution by flash memory.

3. When high-speed on-chip oscillator clock is stopped.

4. When high-speed system clock is stopped.

5. Not including the current flowing into the 12-bit interval timer and watchdog timer.

6. Relationship between operation voltage width, operation frequency of CPU and operation mode is as

follows.

HS (High speed main) mode: VDD = 2.7 V to 5.5 V @1 MHz to 24 MHz

DD = 2.4 V to 5.5 V @1 MHz to 16 MHz

Remarks 1. f

MX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock

frequency)

2. f

IH: high-speed on-chip oscillator clock frequency

3. Except temperature condition of the TYP. value is TA = 25C, other than STOP mode

RL78/G12

3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C)

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016

Page 71 of 106

(2) 30-pin products

(TA = 40 to +105C, 2.4 V  VDD  5.5 V, VSS = 0 V) (1/2)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

VDD = 5.0 V 1.5

Basic

operation

VDD = 3.0 V 1.5

VDD = 5.0 V 3.7 5.8

= 24 MHz

Note 3

VDD = 3.0 V 3.7 5.8



VDD = 5.0 V 2.7 4.2

= 16 MHz

Note 3

VDD = 3.0 V 2.7 4.2

Square wave input 3.0 4.9

= 20 MHz

Note 2

= 5.0 V

Resonator connection 3.2 5.0

Square wave input 3.0 4.9

= 20 MHz

Note 2

= 3.0 V

Resonator connection 3.2 5.0



Square wave input 1.9 2.9

= 10 MHz

Note 2

= 5.0 V

Resonator connection 1.9 2.9



Square wave input 1.9 2.9

Supply

currentNote 1

IDD1 Operating

mode

HS (High-speed

main) mode

Note 4

= 10 MHz

Note 2

= 3.0 V

Normal

operation

Resonator connection 1.9 2.9



Notes 1. Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is

fixed to VDD or VSS. The values below the MAX. column include the peripheral operation current. However,

not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down

resistors and the current flowing during data flash rewrite.

2. When high-speed on-chip oscillator clock is stopped.

3. When high-speed system clock is stopped

4. Relationship between operation voltage width, operation frequency of CPU and operation mode is as

follows.

HS(High speed main) mode: VDD = 2.7 V to 5.5 V @1 MHz to 24 MHz

DD = 2.4 V to 5.5 V @1 MHz to 16 MHz

Remarks 1. f

MX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock

frequency)

2. f

IH: high-speed on-chip oscillator clock frequency

3. Temperature condition of the TYP. value is TA = 25C.

RL78/G12

3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C)

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016

Page 72 of 106

(2) 30-pin products

(TA = 40 to +105C, 2.4 V  VDD  5.5 V, VSS = 0 V) (2/2)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

VDD = 5.0 V 440 2300fIH = 24 MHzNote 4

VDD = 3.0 V 440 2300



VDD = 5.0 V 400 1700fIH = 16 MHzNote 4

VDD = 3.0 V 400 1700



Square wave input 280 1900

fMX = 20 MHzNote 3,

VDD = 5.0 V

Resonator connection 450 2000



Square wave input 280 1900

fMX = 20 MHzNote 3,

VDD = 3.0 V Resonator connection 450 2000



Square wave input 190 1020

fMX = 10 MHzNote 3,

VDD = 5.0 V Resonator connection 260 1100



Square wave input 190 1020

IDD2 Note 2 HALT

mode

HS (High-speed

main) mode

Note 6

fMX = 10 MHzNote 3,

VDD = 3.0 V

Resonator connection 260 1100



TA = 40C 0.18 0.50

TA = +25C 0.23 0.50

TA = +50C 0.30 1.10

TA = +70C 0.46 1.90

TA = +85C 0.75 3.30

Supply

current Note 1

IDD3 Note 5 STOP

mode

TA = +105C 2.94 15.30



Notes 1. Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is

fixed to VDD or VSS. The values below the MAX. column include the peripheral operation current. However,

not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down

resistors and the current flowing during data flash rewrite.

2. During HALT instruction execution by flash memory.

3. When high-speed on-chip oscillator clock is stopped.

4. When high-speed system clock is stopped.

5. Not including the current flowing into the 12-bit interval timer and watchdog timer.

6. Relationship between operation voltage width, operation frequency of CPU and operation mode is as

follows.

HS (High speed main) mode: VDD = 2.7 V to 5.5 V @1 MHz to 24 MHz

DD = 2.4 V to 5.5 V @1 MHz to 16 MHz

Remarks 1. f

MX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock

frequency)

2. f

IH: high-speed on-chip oscillator clock frequency

3. Except STOP mode, temperature condition of the TYP. value is TA = 25C.

RL78/G12

3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C)

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016

Page 73 of 106

(3) Peripheral functions (Common to all products)

(TA = 40 to +105C, 2.4 V  VDD  5.5 V, VSS = 0 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Low-speed onchip

oscillator operating

current

IFIL Note 1 0.20



12-bit interval timer

operating current

ITMKA

Notes 1, 2, 3

0.02



Watchdog timer

operating current

IWDT

Notes 1, 2, 4

fIL = 15 kHz 0.22



Normal mode, AVREFP = VDD = 5.0 V 1.30 1.70 mA A/D converter

operating current

IADC

Notes 1, 5

When conversion

at maximum speed Low voltage mode,

AVREFP = VDD = 3.0 V

0.50 0.70 mA

A/D converter

reference voltage

operating current

IADREF

Note 1

75.0



Temperature sensor

operating current

ITMPS

Note 1

75.0



LVD operating current ILVD

Notes 1, 6

0.08



Self-programming

operating current

IFSP

Notes 1, 8

2.00 12.20 mA

BGO operating

current

IBGO

Notes 1, 7

2.00 12.20 mA

The mode is performed Note 9 0.50 1.10 mA ADC operation

The A/D conversion operations are

performed, Low voltage mode, AVREFP

= VDD = 3.0 V

1.20 2.04 mA

SNOOZE operating

current

ISNOZ

Note 1

CSI/UART operation 0.70 1.54 mA

Notes 1. Current flowing to the VDD.

2. When high speed on-chip oscillator and high-speed system clock are stopped.

3. Current flowing only to the 12-bit interval timer (excluding the operating current of the low-speed on-chip

oscillator). The current value of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3, and IFIL and ITMKA when

the 12-bit interval timer operates.

4. Current flowing only to the watchdog timer (including the operating current of the low-speed on-chip oscillator).

The current value of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and IWDT when the watchdog timer

operates.

5. Current flowing only to the A/D converter. The current value of the RL78 microcontrollers is the sum of IDD1 or

IDD2 and IADC when the A/D converter operates in an operation mode or the HALT mode.

6. Current flowing only to the LVD circuit. The current value of the RL78 microcontrollers is the sum of IDD1, IDD2 or

IDD3 and ILVD when the LVD circuit operates.

7. Current flowing only during data flash rewrite.

8. Current flowing only during self programming.

9. For shift time to the SNOOZE mode, see 17.3.3 SNOOZE mode.

Remarks 1. fIL: Low-speed on-chip oscillator clock frequency

2. Temperature condition of the TYP. value is TA = 25C

RL78/G12

3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C)

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016

Page 74 of 106

3.4 AC Characteristics

(TA = 40 to +105C, 2.4 V  VDD  5.5 V, VSS = 0 V)

Items Symbol Conditions MIN. TYP. MAX. Unit

2.7 V  VDD  5.5 V 0.04167 1





Main system

clock (f

MAIN

)

operation

HS (High-

speed main)

mode

2.4 V  VDD  2.7 V 0.0625 1





2.7 V  VDD  5.5 V 0.04167 1





Instruction cycle (minimum

instruction execution time)

TCY

During self

programming

HS (High-

speed main)

mode

2.4 V  VDD  2.7 V 0.0625 1





2.7 V  VDD  5.5 V 1.0 20.0 MHz

External main system clock

frequency

fEX

2.4 V  VDD  2.7 V 1.0 16.0 MHz

2.7 V  VDD  5.5 V 24 ns

External main system clock

input high-level width, low-

level width

tEXH, tEXL

2.4 V  VDD  2.7 V 30 ns

TI00 to TI07 input high-level

width, low-level width

tTIH, tTIL

1/f

MCK



4.0 V  VDD  5.5 V

12 MHz

2.7 V  VDD  4.0 V

8 MHz

TO00 to TO07 output

frequency

fTO

2.4 V  VDD  2.7 V

4 MHz

4.0 V  VDD  5.5 V

16 MHz

2.7 V  VDD  4.0 V

8 MHz

PCLBUZ0, or PCLBUZ1

output frequency

fPCL

2.4 V  VDD  2.7 V

4 MHz

INTP0 to INTP5 input high-

level width, low-level width

tINTH, tINTL 1



KR0 to KR9 input available

width

tKR 250 ns



RESET low-level width tRSL 10





Remark fMCK: Timer array unit operation clock frequency

(Operation clock to be set by the timer clock select register 0 (TPS0) and the CKS0n bit of timer mode

RL78/G12

3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C)

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016

Page 75 of 106

Minimum Instruction Execution Time during Main System Clock Operation

TCY vs VDD (HS (high-speed main) mode)

When the high-speed on-chip oscillator clock is selected

During self programming

When high-speed system clock is selected

Cycle time T

[µs]

Supply voltage V

[V]

1.0

0.1

1.0 2.0 3.0 4.0 5.0 6.0

5.5

2.7

0.01

2.4

0.04167

0.0625

AC Timing Test Point

Test points V

External Main System Clock Timing

EXCLK

1/f

EXL

EXH

RL78/G12

3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C)

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016

Page 76 of 106

TI/TO Timing

TI00 to TI07

TIL

TIH

TO00 to TO07

1/f

Interrupt Request Input Timing

INTP0 to INTP5

INTL

INTH

Key Interrupt Input Timing

KR0 to KR9

RESET Input Timing

RESET

RSL

RL78/G12

3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C)

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016

Page 77 of 106

3.5 Peripheral Functions Characteristics

AC Timing Test Point

Test points V

3.5.1 Serial array unit

(1) During communication at same potential (UART mode)

(TA = 40 to +105C, 2.4 V  VDD  5.5 V, VSS = 0 V)

HS (high-speed main) Mode Parameter Symbol Conditions

MIN. MAX.

Unit

fMCK/12 bps Transfer rate

Note 1

Theoretical value of the maximum transfer rate

fCLK = fMCKNote2

2.0 Mbps

Notes 1. Transfer rate in the SNOOZE mode is 4800 bps only.

2. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are:

HS (high-speed main) mode: 24 MHz (2.7 V  VDD  5.5 V)

16 MHz (2.4 V  VDD  5.5 V)

Caution Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by using port

input mode register g (PIMg) and port output mode register g (POMg).

UART mode connection diagram (during communication at same potential)

RL78

microcontroller

TxDq

RxDq

User's device

UART mode bit width (during communication at same potential) (reference)

TxDq

RxDq

Baud rate error tolerance

High-/Low-bit width

1/Transfer rate

Remarks 1. q: UART number (q = 0 to 2), g: PIM, POM number (g = 0, 1)

2. f

MCK: Serial array unit operation clock frequency

(Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial

mode register mn (SMRmn).

m: Unit number, n: Channel number (mn = 00 to 03, 10, 11))

RL78/G12

3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C)

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016

Page 78 of 106

(2) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output)

(TA = 40 to +105C, 2.4 V  VDD  5.5 V, VSS = 0 V)

HS (high-speed main) ModeParameter Symbol Conditions

MIN. MAX.

Unit

2.7 V  VDD  5.5 V 334 ns SCKp cycle time tKCY1 tKCY1  4/fCLK

2.4 V  VDD  5.5 V 500 ns

4.0 V  VDD  5.5 V tKCY1/224 ns

2.7 V  VDD  5.5 V tKCY1/236 ns

SCKp high-/low-level width tKH1,

tKL1

2.4 V  VDD  5.5 V tKCY1/276 ns

4.0 V  VDD  5.5 V 66 ns

2.7 V  VDD  5.5 V 66 ns

SIp setup time (to SCKp) Note 1 tSIK1

2.4 V  VDD  5.5 V 113 ns

SIp hold time (from SCKp) Note 2 tKSI1 38 ns

Delay time from SCKp to

SOp output Note 3

tKSO1 C = 30 pF Note4 50 ns