Features
•Programmable Audio Output for Interfacing with Common Audio DAC
– PCM Format Compatible
–I
2S Format Comp atib le
•8-bit MCU C51 Core-based (FMAX = 20 MHz)
•2304 Bytes of Internal RAM
•64K Bytes of Code Memory
– AT89C5132: Flash (100K Write/Erase Cycles)
•4K Bytes of Boot Flash Memory (AT89C5132)
– ISP: Download from USB (standard) or UART (option)
•USB Rev 1.1 Device Controller
– “Full Speed” Data Transmission
•Built-in PLL
•MultiMedia Card® Interface Compatibility
•Atmel DataFlash® SPI Interface Compatibility
•IDE/ATAPI Interface
•2 Channels 10-bit ADC, 8 kHz (8 True Bits)
– Battery Volt age Monitorin g
– Voice Recording Controlled by Software
•Up to 44 Bits of General-purpose I/Os
– 4-bit Interrupt Keyboard Port for a 4 x n Matrix
–SmartMedia
® Software Interface
•Two Standard 16-bit Timer s/Counters
•Hardware Watchdog Timer
•Standard Full Duplex UART with Baud Rate Generator
•Two Wire Master and Slave Modes Controller
•SPI Master and Slave Modes Controller
•Power Management
– Power-on Reset
– Software Programmable MCU Clock
– Idle Mode, Power-down Mode
•Operating Conditions
–3V, ±10%, 25 mA Typical Operating at 25°C
– Temperature Range: -40 °C to +85 °C
•Packages
– TQF P80, PLCC84 (Deve lopm ent Boar d Only)
–Dice
1. Description
The AT89 C51 32 is a mas s st orage dev ice co ntr ol ling data exc han ge be twee n vari ous
Flash modules, HDD and CD-ROM.
The AT89C5132 includes 64K Bytes of Flash memory and allows In-System Program-
ming through an embedded 4K Bytes of Boot Flash Memory.
The AT89C5132 include 2304 Bytes of RAM memory.
The AT89C5132 provides all the necessa ry features for man-machine in terface
including, timers, keyboard por t, serial or parallel in terface (USB, SPI, IDE), ADC
input, I2S output, and all external memory interface (NAND or NOR Flash, SmartMe-
dia , MultiMedia, DataFl ash cards).
2. Typical Applications
• Flash Recorder/Writer
• PDA, Camera, Mobile Phone
• PC Add-on
USB
Microcontroller
with 64K Bytes
Flash Memory
AT89C5132
4173ES–USB–09/07
2 4173ES–USB–09/07
AT89C5132
3. Block Diagram
Figure 3-1. AT89C5132 Block Diagram
Notes: 1. Alternate function of Port 3
2. Alternate function of Port 4
3. Alternate function of Port 1
8-BIT INTERNAL BUS
Clock and PLL
Unit
C51 (X2 CORE)
RAM
2304 Bytes
Flash
Interrupt
Handler Unit
FILT X2X1
MMC
Interface
I/O
MDAT P0 - P5
10-bit A-to-D
Converter
VSS
VDD
Keyboard
Interface
KIN3:0
I2S/PCM
Audio Interface
AVSSAVDD AIN1:0
Ports
INT0 INT1 MOSIMISO
Time r s 0 /1
T1T0
SPI/DataFlash
Controller
MCLK MCMD
SCK
RST
AREF
DSELDCLK SCLKDOUT
64K Bytes
USB
Controller
D+ D-
UART
RXDTXD
IDE
Interface
SS
Watchdog
Flash Boot
4K Bytes
UVSSUVDD
and
BRG
11 11 112222
3
TWI
Controller
SCL SDA
11
3
4173ES–USB–09/07
AT89C5 132
4. Pin Description
Figure 4-1. AT89C5132 80-pin TQFP Package
P0.3/AD3
P0.4/AD4
P0.5/AD5
VSS
VDD
P0.6/AD6
P0.7/AD7
P2.0/A8
P2.1/A9
P3.1/TXD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.0/RXD
1
2
3
4
5
6
7
8
13
11
10
P2.2/A1
0
P2.3/A1
1
P2.4/A1
2
P2.6/A1
4
P2.5/A1
3
P2.7/A1
5
MCLK
MDAT
MCMD
P0.2/AD2
P0.1/AD1
P0.0/AD0
PVSS
VSS
X2
X1
TST
VSS
9
12
14
15
16
P4.3/SS
P4.2/SCK
P4.1/MOSI
P4.0/MISO
VSS
VDD
RST
SCLK
DSEL
DCLK
DOUT
AIN1
AIN0
AREFN
AREFP
AVSS
AVDD
P3.7/RD
P3.6/WR
P3.5/T1
VDD
P1.0/KIN0
P1.1/KIN1
P1.2/KIN2
P1.3/KIN3
P1.4
P1.5
P1.7/SDA
FILT
PVDD
VDD
P1.6/SCL
17
18
19
20
21
22
23
24
25
26
27
28
33
31
30
29
32
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
53
51
50
49
52
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
73
71
70
69
72
74
75
76
77
78
79
80
ALE
ISP
UVDD
UVSS
P5.0
P5.1
P4.7
P4.6
D-
D+
P5.3
P5.2
VSS
VDD
P4.5
P4.4
TQFP80
4 4173ES–USB–09/07
AT89C5132
Figure 4-2. AT89C5132 84-pin PLCC (1)
Note: 1. For developm en t board onl y.
4.1 Signals
All the AT89C5132 signals are detailed by functionality in Table 1 to Table 14.
Table 1. Ports Signal Description
PLCC84
P0.3/AD3
P0.4/AD4
P0.5/AD5
VSS
VDD
P0.6/AD6
P0.7/AD7
P2.0/A8
P2.1/A9
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.2/INT0
65
64
63
62
61
60
59
58
55
56
57
12
13
14
15
16
17
22
20
19
33
34
35
36
37
4
3
2
1
84
83
82
81
80
79
78
NC
P2.3/A11
P2.4/A12
P2.6/A14
P2.5/A13
P2.7/A15
MCLK
MDAT
MCMD
P0.2/AD2
P0.1/AD1
P5.0
PAVSS
VSS
X2
NC
X1
P3.1/TXD
18
21
23
24
25
38
39
40
41
42
69
68
67
66
70
5
6
7
8
9
P4.3/SS
P4.2/SCK
P4.1/MOSI
P4.0/MISO
VSS
VDD
RST
SCLK
DSEL
DCLK
DOUT
AIN1
AIN0
AREFN
AREFP
AVSS
AVDD
VSS
VDD
P3.7/RD
P3.0/RXD
P1.0/KIN0
P1.1/KIN1
P1.2/KIN2
P1.3/KIN3
P1.4
P1.5
P1.7/SDA
FILT
PAVDD
VDD
P1.6/SCL
26
43
TST
P5.2
P0.0/AD0
77
P2.2/A10
54
ALE
ISP
NC
P5.1
P4.7
P4.6
76
75
10
11
28
27
29
30
31
32
UVDD
UVSS
44
45
46
47
48
49
50
51
52
53
74
73
72
71 P4.4
P4.5
VDD
VSS
D-
D+
NC
P5.3
Signal
Name Type Description Alternate
Function
P0.7:0 I/O
Port 0
P0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written
to them float and can be used as high impedance inputs. To avoid any parasitic
current consumption, floating P0 inputs must be polarized t o VDD or VSS.
AD7:0
P1.7:0 I/O Port 1
P1 is an 8-bit bidirectional I/O port with internal pull-ups.
KIN3:0
SCL
SDA
5
4173ES–USB–09/07
AT89C5 132
Table 2. Cloc k Si gna l Desc r ipt ion
Table 3. Timer 0 and Timer 1 Signal Description
P2.7:0 I/O Port 2
P2 is an 8-bit bidirectional I/O port with internal pull-ups. A15:8
P3.7:0 I/O Port 3
P3 is an 8-bit bidirectional I/O port with internal pull-ups.
RXD
TXD
INT0
INT1
T0
T1
WR
RD
P4.7:0 I/O Port 4
P4 is an 8-bit bidirectional I/O port with internal pull-ups.
MISO
MOSI
SCK
SS
P5.3:0 I/O Port 5
P5 is a 4-bit bidirectional I/O port with internal pull-ups. -
Signal
Name Type Description Alternate
Function
X1 I
Input to the on-chip inverting oscillator amplifier
To use the internal oscillator , a crystal/resonator circuit is connected to this pin.
If an external oscillator is used, its output is connected to this pin. X1 is the
clock source for internal timing.
-
X2 O Output of the on-chip inverting oscillator amplifier
To use the internal oscillator , a crystal/resonator circuit is connected to this pin.
If an external oscillator is used, leave X2 unconnected. -
FILT I PLL Low Pass Filter input
FILT receives the RC network of the PLL low pass filter. -
Signal
Name Type Description Alternate
Function
INT0 I
Timer 0 Gate Input
INT0 serves as external run control for timer 0, when selected by GA TE0 bit in
TCON register.
External Interrupt 0
INT0 input sets IE0 in the TCON register . If bit IT0 in this register is set, bit IE0
is set by a falling edge on INT0. If bit IT0 is cleared, bit IE0 is set by a low level
on INT0.
P3.2
INT1 I
Timer 1 Gate Input
INT1 serves as external run control for timer 1, when selected by GA TE1 bit in
TCON register.
External Interrupt 1
INT1 input sets IE1 in the TCON register . If bit IT1 in this register is set, bit IE1
is set by a falling edge on INT1. If bit IT1 is cleared, bit IE1 is set by a low level
on INT1.
P3.3
Signal
Name Type Description Alternate
Function
6 4173ES–USB–09/07
AT89C5132
Table 4. Audio Interface Signal Description
Table 5. USB Controller Signal Description
Table 6. MutiMediaCard Interface Signal Description
T0 I Timer 0 External Clock Input
When timer 0 operates as a counter, a falling edge on the T0 pin increments
the count. P3.4
T1 I Timer 1 External Clock Input
When timer 1 operates as a counter, a falling edge on the T1 pin increments
the count. P3.5
Signal
Name Type Description Alternate
Function
DCLK O DAC Data Bit Clock -
DOUT O DAC Audio Data -
DSEL O DAC Channel Select Signal
DSEL is the sample rate clock output. -
SCLK O DAC System Clock
SCLK is the oversampling clock synchronized to the digital audio data (DOUT)
and the channel selection signal (DSEL). -
Signal
Name Type Description Alternate
Function
D+ I/O USB Positive Data Upstream Port
This pin requires an external 1.5 KΩ pull-up to VDD for full speed operation. -
D- I/O USB Negative Data Upstream Port -
Signal
Name Type Description Alternate
Function
MCLK O MMC Clock outpu t
Data or command clock transfer. -
MCMD I/O
MMC Command line
Bidirectional command channel used for card initialization and data transfer
commands. To avoid any par asitic curr ent consumpt ion, unused MCMD input
must be polarized to VDD or VSS.
-
MDAT I/O MMC Data line
Bidirectional data channel. To avoid any parasitic current consumption, unused
MDAT input must be polarized to VDD or VSS.-
Signal
Name Type Description Alternate
Function
7
4173ES–USB–09/07
AT89C5 132
Table 7. UART Signal Description
Table 8. SPI Controller Signal Description
Table 9. TWI Controller Signal Description
Table 10. A/D Converter Signal Description
Signal
Name Type Description Alternate
Function
RXD I/O Receive Serial Data
RXD sends and receives data in serial I/O mode 0 and receives data in serial
I/O modes 1, 2 and 3. P3.0
TXD O Transmit Serial Data
TXD outputs the shift clock in serial I/O mode 0 and transmits dat a in serial I/O
modes 1, 2 and 3. P3.1
Signal
Name Type Description Alternate
Function
MISO I/O SPI Master Input Slave Output Data Line
When in master mode, MISO receives data from the slave peripheral. When in
slave mode, MISO outputs data to the master controller. P4.0
MOSI I/O SPI Master Output Slave Input Data Line
When in master mode, MOSI outputs data to the slave peripheral. When in
slave mode, MOSI receives data from the master controller. P4.1
SCK I/O SPI Clock Line
When in master mode, SCK outputs clock to the slave peripheral. When in
slave mode, SCK receives clock from the master controller. P4.2
SS ISPI Slave Select Line
When in controlled slave mode, SS enables the slave mode. P4.3
Signal
Name Type Description Alternate
Function
SCL I/O
TWI Serial Clock
When TWI controller is in master mode, SCL outputs the serial clock to the
slave peripherals. When TWI controller is in slave mode, SCL receives clock
from the master controller.
P1.6
SDA I/O TWI Serial Data
SDA is the bidirectional Two Wire data line. P1.7
Signal
Name Type Description Alternate
Function
AIN1:0 I A/D Converter Analog Inputs -
AREFP I Analog Positive Voltage Reference Input -
AREFN I Analog Negative Voltage Reference Input
This pin is internally connected to AVSS. -
8 4173ES–USB–09/07
AT89C5132
Table 11. Keypad Interface Signal Description
Table 12. External Access Signal Desc ription
Table 13. System Signal Description
Signal
Name Type Description Alternate
Function
KIN3:0 I Keypad Input Lines
Holding one of these pins high or low for 24 oscillator periods triggers a
keypad interrupt. P1.3:0
Signal
Name Type Description Alternate
Function
A15:8 I/O Address Lines
Upper address lines for the external bus.
Multiplexed higher address and data lines for the IDE interface. P2.7:0
AD7:0 I/O Address/Data Lines
Multiplexed lower address and data lines for the external memory or the IDE
interface. P0.7:0
ALE O
Address Latch Enable Output
ALE signals the start of an external bus cycle and indicates that valid address
information is available on lines A7:0. An external latch is used to demultiplex
the address from address/data bus.
-
ISP I/O ISP Enable In p ut
This signal must be held to G ND through a pull-down resistor at the falling
reset to force execution of the internal bootloader. -
RD ORead Signal
Read signal asserted during external data memory read operation. P3.7
WR OWrite Signal
Write signal asserted during external data memory write operation. P3.6
Signal
Name Type Description Alternate
Function
RST I
Reset Input
Holding this pin high for 64 oscillator periods while the oscillator is running
resets the device. The Port pins are driven to their reset conditions when a
voltage lower than VIL is applied, whether or not the oscillator is running.
This pin has an internal pull-down resistor which allows the device to be reset
by connecting a capacitor between this pin and VDD.
Asserting RST when the chip is in Idle mode or Power-Down mode returns the
chip to normal operation.
-
TST I Test Input
Test mode entry signal. This pin must be set to VDD.-
9
4173ES–USB–09/07
AT89C5 132
Table 14. Power Signal Description
Signal
Name Type Description Alternate
Function
VDD PWR Digital Supply Voltage
Connect these pins to +3V supply voltage. -
VSS GND Cir c uit Gr ound
Connect these pins to ground. -
AVDD PWR Analog S upply Volta ge
Connect this pin to +3V supply voltage. -
AVSS GND Analog Ground
Connect this pin to ground. -
PVDD PWR PLL Suppl y voltage
Connect this pin to +3V supply voltage. -
PVSS GND PLL Circ uit Ground
Connect this pin to ground. -
UVDD PWR USB Supply Vo ltage
Connect this pin to +3V supply voltage. -
UVSS GND USB Ground
Connect this pin to ground. -
10 4173ES–USB–09/07
AT89C5132
4.2 Internal Pin Structure
Table 15. Detailed Internal Pin Structure
Notes: 1. For information on resistors value, input/output levels, and drive capability, refer to the
Section “DC Characteristics”, page 183.
2. When the Two Wire controller is enabled, P1, P2, and P3 transistors are disabled allowing
pseudo open-drain structure.
3. In Port 2, P1 transistor is continuously driven when outputting a high level bit address (A15:8).
Circuit(1) Type Pins
Input TST
Input/Output RST
Input/Output
P1(2)
P2(3)
P3
P4
P53:0
Input/Output
P0
MCMD
MDAT
ISP
PSEN
Output
ALE
SCLK
DCLK
DOUT
DSEL
MCLK
Input/Output D+
D-
R
TST
VDD
R
RST
VSS
P
VDD
Watchdog Output
P3
VSS
N
P1
VDD VDD
2 osc
Latch Output periods P2
VDD
VSS
N
P
VDD
VSS
N
P
VDD
D+
D-
11
4173ES–USB–09/07
AT89C5 132
5. Address Spaces
The AT8xC5132 derivatives implement four different address spaces:
• Program/Code Memory
• Boot Memory
• Data Memory
• Special Function Registers (SFRs)
5.0.1 Code Memory
The AT89C5132 implements 64K Bytes of on-chip program/code memory in Flash technology.
The Flash memory increases ROM functionality by enabling in-circuit electrical erasure and pro-
gramm ing. Than ks to the inter nal charg e pump, th e high volt age needed f or program ming or
erasing Flash cells is generated on-chip using the standard VDD volta ge. Thus, th e AT89C513 2
can be programmed using only one voltage and allows in application software programming
commonly known as IAP. Hardware programming mode is also available using specific pro-
gramming tools.
5.0.2 Boot Memory
The AT89C51 32 implemen ts 4K Bytes of on-chip boot memory provided in Flash technol ogy.
This boot memory is delivered programmed with a standard bootloader software allowing in sys-
tem programming commonly known as ISP. It also contains some Application Programming
Interfaces routines commonly known as API allowing user to develop his own bootloader.
5.0.3 Data Memory
The AT89C5132 derivatives implement 2304 bytes of on-chip data RAM. This memory is divided
in two separate areas:
• 256 bytes of on-chip RAM memory (standard C51 memory).
• 2048 bytes of on-chip expanded RAM memory (ERAM accessible via MOVX instructions).
12 AT89C5132 4173ES–USB–09/07
Peripherals
The AT8xC5132 peripherals are briefly described in the following sections. For furt her
details on how to interface (hardware and software) to these peripherals, please refer to
the AT8xC5132 complete datasheet.
Clock Generator System The AT8xC5132 internal clocks are extracted from an on-chip PLL fed by an on-chip
oscillator. Four clocks are generated respectively for the C51 core, the audio interface,
and the other peripherals. The C51 and peripheral clocks are derived from the oscillator
clock. The audio interface sample rates are also obtained by dividing the PLL output
clock.
Ports The AT8xC5132 implement five 8-bit ports (P0 to P4) and one 4-bit port (P5). In addition
to performing general-purpose I/Os , some ports are capable of external data memory
operati ons ; othe rs al lo w for alternate func tio ns . Al l I/O Po rts ar e bidir ec tio nal . Eac h P ort
contains a latch, an output driver and an input buffer. Port 0 and Port 2 output drivers
and inp ut buf fers faci litat e exter nal m emor y oper ations. Some Por t 1, Port 3 and Por t 4
pins serve for both general-purpose I/Os and alternate functions.
Timers/Counters The A T8xC513 2 im pleme nt the two gene ral-p urpose, 16- bit T imers /Counte rs of a stan -
dard C51. They are identified as Timer 0, Timer 1, and can independently be configured
each to o per ate in a v arie ty of m ode s a s a Tim er or as a n ev en t Cou nter . W he n op erat -
ing as a Timer, a Timer/Counter runs for a programmed length of time, then issues an
interrupt request. When operating as a Counter, a Timer/Counter counts negative transi-
tions on an external pin. After a preset number of counts, the Counter issues an interrupt
request.
Watchdog Timer The AT8xC5132 implement a hardware Watchdog Timer that automatically resets the
chip if i t is allowed to ti me out. The WDT provide s a means of recove ring from routines
that do not complete successfully due to software or hardware malfunctions.
Audio Output Interface The AT8xC5132 implements an audio output interface allowing the decoded audio bit-
stream to be output in various formats. They are compatible with right and left
justification PCM and I2S formats and the on-chip PLL allows conn ection of almost all
commer ci al audio DAC fami li es availa ble on the mark et.
Universal Serial Bus
Interface The AT8xC5132 implements a full-speed Universal Serial Bus Interface. The USB inter-
face can be used for the following purposes:
• Download of files by supporting the USB mass storage class.
• In-Sy s tem Progr am mi ng by su ppo rting the USB firmware upgrad e class .
MultiMedia Card
Interface The AT8xC5132 im plements a MultiMedia Card (MMC) interface compliant to the V2.2
specification in Multi Media Card mode. The MMC allows storage of files in removable
Flash m emory car ds that can be easi ly plugged o r removed from the applica tion. It can
also be used for In-System Programming.
IDE/ATAPI Interface The AT8xC5132 provide an IDE/ATAPI interface allowing connection of devices such as
CD-ROM reader, CompactFlash™ cards, Hard Disk Drive, etc. It consists of a 16-bit bidi-
rectional bus part of the low-level ANSI ATA/ATAPI specification. It is provided for mass
storage interface but could be used for In-System Programming using CD-ROM.
13
AT89C5132
4173ES–USB–09/07
Serial I/O Interface The AT89C5132 implements a serial port with its own baud rate generator providing one
single synchronous communication mode and three full-duplex Universal Asynchronous
Receiver Transmitter (UART) co mmunication modes. It is provided for the following
purposes:
• In System Programming.
• Remote control of the AT89C5132 by a host.
Serial Peripheral
Interface The AT89C5132 implements a Serial Peripheral Interface (SPI) supporting master and
slave modes. It is provided for the following purposes:
• Remote control of the AT89C5132 by a host.
• In System Programming.
Two-wire Controller The AT89C5132 implements a 2-wire controller supporting the four standard master and
slave modes with multimaster capability. It is provided for the following purposes:
• Connection of slave devices like LCD controller, audio DAC…
• Remote control of the AT89C5132 by a host.
• In System Programming.
A/D Controller The A T89C5 132 im pleme nts a 2 -chan nel 10 -bit ( 8 true bits) a nalog to digi tal con vert er
(ADC). It is provided for the following purposes:
• Batter y mon itoring.
• Voice recording.
• Corded remote control.
14 4173ES–USB–09/07
AT89C5132
6. Electrical Characteristics
6.1 Absolute Maximum Ratings
6.2 DC Characte ristics
6.2.1 Digital Logic
Storage Temperatu re................................... .. -65°C to +150°C
Voltage on any other Pin to VSS .....................................-0.3 to +4.0V
IOL per I/O Pin................................... ............................ .. 5 mA
Power Dissipation............................................................. 1 W
Ambient Temper atu re Under Bias.................... -40°C to +85°C
VDD ....................................................................................... 2.7V to 3.3V
*NOTICE: Stressing the device beyond the “Absolute Maxi-
mum Ratings” may cause permanent damage.
These are stress ratings only. Operation beyond
the “operating conditions” is not recommended
and extended exposure beyond the “Operating
Condi tio ns” ma y affect device reli abi lit y.
Table 1. Digital DC Characteristics
VDD = 2.7 to 3.3V , TA = -40 to +85°C
Symbol Parameter Min Typ(1) Max Units Test Conditions
VIL Input Low Voltage -0.5 0.2·VDD - 0.1 V
VIH1 Input High Voltage (except RST, X1) 0.2·VDD + 1.1 VDD V
VIH2 Input High Voltage (RST, X1) 0.7·VDD(2) VDD + 0.5 V
VOL1
Output Low V oltage
(excep t P0, AL E, MCMD, MDAT, MCLK,
SCLK, DCLK, DSEL, DOUT) 0.45 V IOL= 1.6 mA
VOL2
Output Low V oltage
(P0, ALE, MCMD, MDAT, MCLK, SCLK,
DCLK, DSEL, DOUT) 0.45 V IOL= 3.2 mA
VOH1 Output High Voltage
(P1, P2, P3, P4 and P5) VDD - 0.7 V IOH= -30 μA
VOH2
Output High V oltage
(P0, P2 address mode, ALE, MCMD,
MDAT, MCLK, SCLK, DCLK, DSE L ,
DOUT, D+, D-)
VDD - 0.7 V IOH= -3.2 mA
IIL Logical 0 Input Current (P1, P2, P3, P4
and P5) -50 μA Vin = 0.45 V
15
4173ES–USB–09/07
AT89C5 132
Notes: 1. Typical values are obtained using VDD= 3 V and TA= 25°C. They are not tested and there is no
guarantee on thes e val ues .
2. Flash retention is guaranteed with the same formula for VDD min down to 0V.
3. See Table 154 for typical consumption in player mode.
6.2.2 IDD, IDL and IPD Test Conditions
Figure 6-1. IDD Te st Condition, Activ e Mod e
ILI
Input Leakage Current (P0, ALE, MCMD,
MDAT, MCLK, SCLK, DCLK, DSE L ,
DOUT) 10 μA 0.45< VIN< VDD
ITL Logical 1 to 0 Transition Current
(P1, P2, P3, P4 and P5) -650 μA Vin = 2.0 V
RRST Pull-Down Resistor 50 90 20 0 kΩ
CIO Pin Capacitance 10 pF TA= 25°C
VRET VDD Data Retention Limit 1.8 V
IDD Operating Current (3)
X1 / X2 mod e
6.5 / 10.5
8 / 13.5
9.5 / 17
mA
VDD < 3.3 V
12 MHz
16 MHz
20 MHz
IDL Idle Mode Current (3)
X1 / X2 mod e
5.3 / 8.1
6.4 / 10.3
7.5 / 13
mA
VDD < 3.3 V
12 MHz
16 MHz
20 MHz
IPD Power-Down Mode Current 20 50 0 μAV
RET < VDD < 3.3 V
Table 1. Digital DC Characteristics
VDD = 2.7 to 3.3V , TA = -40 to +85°C
Symbol Parameter Min Typ(1) Max Units Test Conditions
RST
TST
P0
All other pins are unconnected
VDD
VDD VDD IDD
VDD
PVDD
UVDD
AVDD
X2
Clock Signal
VSS
X1
(NC)
VSS
PVSS
UVSS
AVSS
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Figure 6-2. IDL Test Condition, Idle Mode
Figure 6-3. IPD Test Condition, Power-Down Mode
6.2.3 A-to-D Converter
Table 2. A-to-D Converter DC Characteristics
VDD = 2.7 to 3.3V , TA = -40 to +85°C
X2
VDD
Clock Signal
RST
VSS
TST
X1
P0
(NC)
IDL
All other pins are unconnected
VSS
VDD
VSS
VDD
PVDD
UVDD
AVDD
PVSS
UVSS
AVSS
RST
MCMD
P0
All other pins are unconnected
VSS VDD
TST
MDAT
VDD IPD
VDD
PVDD
UVDD
AVDD
X2
VSS
X1
(NC)
VSS
PVSS
UVSS
AVSS
Symbol Parameter Min Typ Max Units Test Conditions
AVDD Analog Supply Voltage 2.7 3.3 V
AIDD Analog Operating Supply Current 600 μAAVDD = 3.3V
AIN1:0 = 0 to AVDD
AIPD Analog Standby Current 2 μAAVDD = 3.3V
ADEN = 0 or PD = 1
AVIN Analog Input Voltage AVSS AVDD V
AVREF
Reference V olt age
AREFN
AREFP
AVSS
2.4 AVDD
V
V
RREF AREF Input Resistance 10 30 kΩTA = 25°C
CIA Analog Input capacitance 10 pF TA = 25°C
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6.2.4 Oscillator and Crystal
6.2.4.1 Schematic
Figure 6-4. Crystal Connection
Note: For operation with most standard crystals, no external components are needed on X1 and X2. It
may be necessary to add external capacitors on X1 and X2 to ground in special cases (max 10
pF). X1 and X2 may not be used to drive other circuits.
6.2.4.2 Parameters Table 3. Oscillator and Crystal Characteristics
VDD = 2.7 to 3.3V , TA = -40 to +85°C
6.2.5 Phase Lock Loop
6.2.5.1 Schematic
Figure 6-5. PLL Filter Connection
VSS
X1
X2
Q
C1
C2
Symbol Parameter Min Typ Max Unit
CX1 Internal Capacitance (X1 - VSS)10pF
CX2 Internal Capacitance (X2 - VSS)10pF
CLEquivalent Load Capacitance (X1 - X2) 5 pF
DL Drive Level 50 μW
F Crystal Frequency 20 MHz
RS Crystal Series Resistance 40 Ω
CS Crystal Shunt Capacitance 6 pF
VSS
FILT
R
C1
C2
VSS
18 4173ES–USB–09/07
AT89C5132
6.2.5.2 Parameters Table 4. PLL Fi lt er Chara cte ris tic s
VDD = 2.7 to 3.3V , TA = -40 to +85°C
6.2.6 USB Connection
6.2.6.1 Schematic
Figure 6-6. USB Connection
6.2.6.2 Parameters Table 16. USB Characteristics
VDD = 3 to 3.3 V, TA = -40 to +85°C
6.2.7 In-system Programming
6.2.7.1 Schematic
Figure 6-7. ISP Pull-down Connection
6.2.7.2 Parameters Table 5. ISP Pul l-D o wn Charac ter isti cs
VDD = 3 to 3.3V , TA = -40 to +85°C
Symbol Parameter Min Typ Max Unit
R Filter Resistor 100 Ω
C1 Filter Capacitance 1 10 nF
C2 Filter Capac itance 2 2.2 nF
D+
D-
VBUS
GND
D+
D-
VSS
To Power
RUSB
RUSB
VDD
Supply RFS
Symbol Parameter Min Typ Max Unit
RUSB USB Termination Resistor 27 Ω
RFS USB Full Speed Resist or 1.5 KΩ
VSS
ISP
RISP
Symbol Parameter Min Typ Max Unit
RISP ISP Pull-Down Resistor 2.2 kΩ
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6.3 AC Characte ristics
6.3.1 External 8-bit Bus Cycles
6.3.1.1 Definition of Symbols
Table 6. External 8-bit Bus Cycles Timing Symbol Definitions
6.3.1.2 Timings
Test conditions: capacitive load on all pins = 50 pF.
Table 7. External 8-bit Bus Cycle – Data Read AC Timings
VDD = 2.7 to 3.3V, TA = -40° to +85°C
Signals Conditions
A Address H High
D Data In L Low
L ALE V Valid
Q Data Out X No Longer Valid
RRD ZFloating
WWR
Symbol Parameter
Variable Clock
Standard Mode Var iable Clock
X2 Mode
UnitMin Max Min Max
TCLCL Clock Period 50 50 ns
TLHLL ALE Pulse Width 2· TCLCL-15 TCLCL-15 ns
TAVLL Address Valid to ALE Low TCLCL-20 0.5·TCLCL-20 ns
TLLAX Address hold after ALE Low TCLCL-20 0.5·TCLCL-20 ns
TLLRL ALE Low to RD Low 3·TCLCL-30 1.5·TCLCL-30 ns
TRLRH RD Pulse Width 6·TCLCL-25 3·TCLCL-25 ns
TRHLH RD high to ALE High TCLCL-20 TCLCL+20 0.5·TCLCL-20 0.5·TCLCL+20 ns
TAVDV Address Valid to Valid Data In 9·TCLCL-65 4.5·TCLCL-65 ns
TAVRL Address Valid to RD Low 4·TCLCL-30 2·TCLCL-30 ns
TRLDV RD Low to Valid Data 5·TCLCL-30 2.5·TCLCL-30 ns
TRLAZ RD Low to Address Float 0 0 ns
TRHDX Data Hold After RD High 0 0 ns
TRHDZ Instruction Float After RD High 2·TCLCL-25 TCLCL-25 ns
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Table 8. External 8-bit Bus Cycle – Data Write AC Timings
VDD = 2.7 to 3.3V, TA = -40° to +85°C
6.3.1.3 Waveforms
Figure 6-8. External 8-bit Bus Cycle – Data Read Waveforms
Symbol Parameter
Variable Clock
Standard Mode Variable C lock
X2 Mode
UnitMin Max Min Max
TCLCL Clock Period 50 50 ns
TLHLL ALE Pulse Width 2·TCLCL-15 TCLCL-15 ns
TAVLL Address Valid to ALE Low TCLCL-20 0.5·TCLCL-20 ns
TLLAX Address hold after ALE Low TCLCL-20 0.5·TCLCL-20 ns
TLLWL ALE Low to WR Low 3·TCLCL-30 1.5·TCLCL-30 ns
TWLWH WR Pulse Width 6·TCLCL-25 3·TCLCL-25 ns
TWHLH WR High to ALE High TCLCL-20 TCLCL+20 0.5·TCLCL-20 0.5·TCLCL+20 ns
TAVWL Address Valid to WR Low 4·TCLCL-30 2·TCLCL-30 ns
TQVWH Data Valid to WR High 7·TCLCL-20 3.5·TCLCL-20 ns
TWHQX Data Hold after WR High TCLCL-15 0.5·TCLCL-15 ns
TAVDV
TLLAX TRHDX
TRHDZ
TAVLL
TAVRL
P2
P0
RD
ALE TLHLL TRLRH
Data In
A15:8
TRLAZ
TLLRL TRHLH
TRLDV
D7:0A7:0
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Figure 6-9. External 8-bit Bus Cycle – Data Write Waveforms
6.3.2 External IDE 16-bit Bus Cycles
6.3.2.1 Definition of Symbols
Table 9. External IDE 16-bit Bus Cycles Timing Symbol Definitions
6.3.2.2 Timings
Test conditions: capacitive load on all pins = 50 pF.
TWHLH
TAVWL
TLLAX TWHQX
P2
P0
WR
ALE TLHLL TWLWH
A15:8
TAVLL TQVWH
D7:0
Data Out
TLLWL
A7:0
Signals Conditions
A Address H High
D Data In L Low
L ALE V Valid
Q Data Out X No Longer Valid
RRD ZFloating
WWR
22 4173ES–USB–09/07
AT89C5132
Table 10. External IDE 16-bit Bus Cycle – Data Read AC Timings
VDD = 2.7 to 3.3V, TA = -40° to +85°C
Table 11. External IDE 16-bit Bus Cycle – Data Write AC Timings
VDD = 2.7 to 3.3V, TA = -40° to +85°C
Symbol Parameter
Variable Clock
Standard Mode Variable C lock
X2 Mode
UnitMin Max Min Max
TCLCL Clock Period 50 50 ns
TLHLL ALE Pulse Width 2·TCLCL-15 TCLCL-15 ns
TAVLL Address Valid to ALE Low TCLCL-20 0.5·TCLCL-20 ns
TLLAX Address hold after ALE Low TCLCL-20 0.5·TCLCL-20 ns
TLLRL ALE Low to RD Low 3·TCLCL-30 1.5·TCLCL-30 ns
TRLRH RD Pulse Width 6·TCLCL-25 3·TCLCL-25 ns
TRHLH RD high to ALE High TCLCL-20 TCLCL+20 0.5·TCLCL-20 0.5·TCLCL+20 ns
TAVDV Address Valid to Valid Data In 9·TCLCL-65 4.5·TCLCL-65 ns
TAVRL Address Valid to RD Low 4·TCLCL-30 2·TCLCL-30 ns
TRLDV RD Low to Valid Data 5·TCLCL-30 2.5·TCLCL-30 ns
TRLAZ RD Low to Address Float 0 0 ns
TRHDX Data Hold After RD High 0 0 ns
TRHDZ Instruction Float After RD High 2·TCLCL-25 TCLCL-25 ns
Symbol Parameter
Variable C lock
Standard Mode Variable C lock
X2 Mode
UnitMin Max Min Max
TCLCL Clock Period 50 50 ns
TLHLL ALE Pulse Wid t h 2· TCLCL-15 TCLCL-15 ns
TAVLL Address Valid to ALE Low TCLCL-20 0.5·TCLCL-20 ns
TLLAX Address hold after ALE Low TCLCL-20 0.5·TCLCL-20 ns
TLLWL ALE Low to WR Low 3·TCLCL-30 1.5·TCLCL-30 ns
TWLWH WR Pulse Width 6·TCLCL-25 3·TCLCL-25 ns
TWHLH WR High to ALE High TCLCL-20 TCLCL+20 0.5·TCLCL-20 0.5·TCLCL+20 ns
TAVWL Address Vali d to WR Low 4·TCLCL-30 2·TCLCL-30 ns
TQVWH Data Valid to WR High 7·TCLCL-20 3.5·TCLCL-20 ns
TWHQX Data Hold after WR High TCLCL-15 0.5·TCLCL-15 ns
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AT89C5 132
6.3.2.3 Waveforms
Figure 6-10. Extern al IDE 16-bi t Bus Cycle – Data Read Wave for ms
Note: D15:8 is written in DAT16H SFR.
Figure 6-11. Extern al IDE 16-bi t Bus Cycle – Data Writ e Wavefor m s
Note: D15:8 is the content of DAT16H SFR.
6.3.3 SPI Interface
6.3.3.1 Definition of Symbols
Table 12. SPI Interface Timing Symbol Definitions
TAVDV
TLLAX TRHDX
TRHDZ
TAVLL
TAVRL
P2
P0
RD
ALE TLHLL TRLRH
Data In
TRLAZ
TLLRL TRHLH
TRLDV
D7:0A7:0
Data In
D15:81A15:8
TWHLH
TAVWL
TLLAX TWHQX
P2
P0
WR
ALE TLHLL TWLWH
TAVLL TQVWH
D7:0
Data Out
TLLWL
A7:0
D15:81
Data Out
A15:8
Signals Conditions
C Clock H High
I Data In L Low
O Data Out V V alid
X No Longer Valid
ZFloating
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AT89C5132
6.3.3.2 Timings Table 13. SPI Interface Master AC Timing
VDD = 2.7 to 3.3V, TA = -40° to +85°C
Notes: 1. Value of this parameter depends on software.
2. Test conditions: capacitive load on all pins = 100 pF
Symbol Parameter Min Max Unit
Slave Mode
TCHCH Clock Period 8 TOSC
TCHCX Clock High Time 3.2 TOSC
TCLCX Clock Low Time 3.2 TOSC
TSLCH, TSLCL SS Low to Clock edge 200 ns
TIVCL, TIVCH Input Data Valid to Clock Edge 100 ns
TCLIX, TCHIX Input Data Hold after Clock Edge 100 ns
TCLOV, TCHOV Output Data Valid after Clock Edge 100 ns
TCLOX, TCHOX Output Data Hold T ime after Clock Edge 0 ns
TCLSH, TCHSH SS High after Clock Edge 0 ns
TIVCL, TIVCH Input Data Valid to Clock Edge 100 ns
TCLIX, TCHIX Input Data Hold after Clock Edge 100 ns
TSLOV SS Low to Output Data Valid 130 ns
TSHOX Output Data Hold after SS High 130 ns
TSHSL SS High to SS Low (1)
TILIH Input Rise Time 2 μs
TIHIL Input Fall Time 2 μs
TOLOH Output Rise Time 100 ns
TOHOL Output Fall Time 100 ns
Master Mode
TCHCH Clock Period 4 TOSC
TCHCX Clock High Time 1.6 TOSC
TCLCX Clock Low Time 1.6 TOSC
TIVCL, TIVCH Input Data Valid to Clock Edge 50 ns
TCLIX, TCHIX Input Data Hold after Clock Edge 50 ns
TCLOV, TCHOV Output Data Valid after Clock Edge 65 ns
TCLOX, TCHOX Output Data Hold T ime after Clock Edge 0 ns
TILIH Input Data Rise T ime 2 μs
TIHIL Input Data Fall Time 2 μs
TOLOH Output Data Rise Time 50 ns
TOHOL Output Data Fall Time 50 ns
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6.3.3.3 Waveforms
Figure 6-12. SPI Slave Waveforms (SSCPHA = 0)
Note: 1. Not Defined but generally the MSB of the character which has just been rece ived.
Figure 6-13. SPI Slave Waveforms (SSCPHA = 1)
Note: 1. Not Defined but generally the LSB of the character which has just been received.
TSLCL
TSLCH
TCHCL
TCLCH
MOSI
(input)
SCK
(SSCPOL = 0)
(input)
SS
(input)
SCK
(SSCPOL = 1)
(input)
MISO
(output)
TCHCH
TCLCX
TCHCX
TIVCL TCLIX
TCHIX
TIVCH
TCHOV
TCLOV TCHOX
TCLOX
MSB IN BIT 6 LSB IN
SLAVE MSB OU T SLAVE LSB OUTBIT 6
TSLOV
1
TSHOX
TSHSL
TCHSH
TCLSH
SI
(input)
SCK
(SSCPOL = 0)
(output)
SS1
(output)
SCK
(SSCPOL = 1)
(output)
SO
(output)
TCHCH
TCLCX
TCHCX
TIVCL TCLIX
TCHIX
TIVCH
TCHOV
TCLOV TCHOX
TCLOX
MSB IN BIT 6 LSB IN
MSB OUTPort Data LSB OUT Port DataBIT 6
TCHCL
TCLCH
26 4173ES–USB–09/07
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Figure 6-14. SPI Master Waveforms (SSCPHA = 0)
Note: 1. SS handled by software using general purpose port pin.
Figure 6-15. SPI Master Waveforms (SSCPHA = 1)
Note: 1. SS handled by software using general purpose port pin.
6.3.4 Two-wire Interface
6.3.4.1 Timings Table 17. TWI Interface AC Timing
TCHCL
TCLCH
MOSI
(input)
SCK
(SSCPOL = 0)
(input)
SS1
(input)
SCK
(SSCPOL = 1)
(input)
MISO
(output)
TCHCH
TCLCX
TCHCX
TIVCL TCLIX
TCHIX
TIVCH
TCLOV
TCHOV TCLOX
TCHOX
MSB IN BI T 6 LSB IN
SLAVE MSB OUT SLAVE LSB OUTBIT 6
TSLOV
1
TSHOX
TSHSL
TCHSH
TCLSH
TSLCL
TSLCH
SI
(input)
SCK
(SSCPOL = 0)
(output)
SS1
(output)
SCK
(SSCPOL = 1)
(output)
SO
(output)
TCHCH
TCLCX
TCHCX
TIVCL TCLIX
TCHIX
TIVCH
TCHOV
TCLOV TCHOX
TCLOX
MSB IN BI T 6 LSB IN
MSB OU TPort Data LSB O U T Port DataBIT 6
TCHCL
TCLCH
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AT89C5 132
VDD = 2.7 to 3.3 V, TA = -40 to +85°C
Notes: 1. At 100 kb it/s. At other bit-rates this value is inversely proportional to the bit-rate of 100 kbit/s.
2. Determined by the external bus-line capacitance and the external bus-line pull-up resistor, this
must be < 1 μs.
3. Spikes on the SDA and SCL lines with a duration of less than 3·TCLCL will be filtered out. Maxi-
mum capacitance on bus-lines SDA and
SCL = 400 p F.
4. TCLCL= TOSC= one oscillator clock period.
6.3.4.2 Waveforms
Figure 6-16. Two Wire Waveforms
Symbol Parameter
INPUT
Min
Max
OUTPUT
Min
Max
THD; STA Start condition hold time 14·TCLCL(4) 4.0 μs(1)
TLOW SCL low time 16·TCLCL(4) 4.7 μs(1)
THIGH SCL high time 14·TCLCL(4) 4. 0 μs(1)
TRC SCL rise time 1 μs-
(2)
TFC SCL fall time 0.3 μs0.3 μs(3)
TSU; DAT1 Data set-up time 250 ns 20·TCLCL(4)- TRD
TSU; DAT2 SDA set-up time (before repeated START condition) 250 ns 1 μs(1)
TSU; DAT3 SDA set-up time (before STOP condition) 250 ns 8·TCLCL(4)
THD; DAT Data hold time 0 ns 8·TCLCL(4) - TFC
TSU; STA Repeated START set-up time 14·TCLCL(4) 4.7 μs(1)
TSU; STO STOP condition set-up time 14·TCLCL(4) 4.0 μs(1)
TBUF Bus free time 14·TCLCL(4) 4.7 μs(1)
TRD SDA rise ti me 1 μs -
(2)
TFD SDA fall time 0.3 μs0.3 μs(3)
Tsu;DAT1
Tsu;STA
Tsu;DAT2
Thd;STA Thigh
Tlow
SDA
(INPUT/OUTPUT) 0.3 VDD
0.7 VDD
Tbuf
Tsu;STO
0.7 VDD
0.3 VDD
Trd
Tfd
Trc Tfc
SCL
(INPUT/OUTPUT)
Thd;DAT
Tsu;DAT3
START or Repeated START condition STA RT condition
STOP condition
Repeated START condition
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6.3.5 MMC Interface
6.3.5.1 Definition of Symbols
Table 14. MMC Interface Timing Symbol Definitions
6.3.5.2 Timings Table 15. MMC Interface AC Timings
VDD = 2.7 to 3.3 V, TA = -40 to +85°C, CL ≤ 100pF (10 cards)
6.3.5.3 Waveforms
Figure 6-17. MMC Input Output Waveforms
Signals Conditions
C Clock H High
D Data In L Low
O Data Out V V alid
X No Longer Valid
Symbol Parameter Min Max Unit
TCHCH Clock Period 50 ns
TCHCX Clock High Time 10 ns
TCLCX Clock Low Time 10 ns
TCLCH Clock Rise Time 10 ns
TCHCL Clock Fall Time 10 ns
TDVCH Input Data Valid to Clock High 3 ns
TCHDX Input Data Hold aft er Clock High 3 ns
TCHOX Output Data Hold after Clock High 5 ns
TOVCH Output Data Valid to Clock High 5 ns
TIVCH
MCLK
MDAT Input
TCHCH TCLCX
TCHCX
TCHCL TCLCH
MCMD Input
TCHIX
TOVCH
MDAT Output
MCMD Output
TCHOX
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6.3.6 Audio Interface
6.3.6.1 Definition of Symbols
Table 16. Audio Interface Timing Symbol Definitions
6.3.6.2 Timings Table 17. Audio Inter face AC timings
VDD = 2.7 to 3.3V, TA = -40 to +85°C, CL ≤ 30pF
Note: 32-bit format with Fs = 48 kHz.
6.3.6.3 Waveforms
Figure 6-18. Audio Interface Waveforms
Signals Conditions
C Clock H High
O Data Out L Low
S Data Select V Valid
X No Longer Valid
Symbol Parameter Min Max Unit
TCHCH Clock Period 325.5(1) ns
TCHCX Clock High Time 30 ns
TCLCX Clock Low Time 30 ns
TCLCH Clock Rise Time 10 ns
TCHCL Clock Fall Time 10 ns
TCLSV Clock Low to Select Valid 10 ns
TCLOV Clock Low to Data Valid 10 ns
DCLK
T
CHCH TCLCX
TCHCX
TCLCH
TCHCL
DSEL
DDAT
Right Left
TCLSV
TCLOV
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6.3.7 Analog to Digital Converter
6.3.7.1 Definition of Symbols
Table 18. Analog to Digital Converter Timing Symbol Definitions
6.3.7.2 Characteristics
Table 18. Analog to Digital Converter AC Characteristics
VDD = 2.7 to 3.3 V, TA = -40 to +85°C
Notes: 1. AVDD= AVREFP= 3.0 V, AVSS= AVREFN= 0 V. ADC is monotonic with no missing code.
2. The differential non-linearity is the difference between the actual step width and the ideal step
width (see Figure 6-20).
3. The integral non-linearity is the peak difference between the center of the actual step and the
ideal transfer curve after appropriate adjustment of gain and offset errors (see Figure 6-20).
4. The offset error is the absolute difference between the straight li ne which fits the actual trans-
fer curve (after removing of gain error), and the straight line which fits the ideal transfer curve
(see Figure 6-20).
5. The gain e rror is th e relat ive di ffe rence in p ercent bet ween the stra ight l ine whic h fit s the actua l
transfer curve (after removing of offset error), and the straight line which fits the ideal transfer
curve (see Figure 6-20).
Signals Conditions
C Clock H High
E Enab le (ADEN bit) L Low
SStart Conversion
(ADSST bit)
Symbol Parameter Min Max Unit
TCLCL Cl ock Period 4 μs
TEHSH Start-up Time 4 μs
TSHSL Conversion Time 11·TCLCL μs
DLe Differential non-
linearity error(1)(2) 1LSB
ILe Integral non-linearity
errorss(1)(3) 2LSB
OSe Offset error(1)(4) 4LSB
Ge Gain error(1)(5) 4LSB
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6.3.7.3 Waveforms
Figure 6-19. Analog-to-Digital Converter Internal Waveforms
Figure 6-20. Analog- to-D igital Converte r Charac ter i stics
ADEN Bit
ADSS T Bit
TEHSH
TSHSL
CLK
TCLCL
1234567 1018 1019 1020 1021 10221023 1024
1
2
3
4
5
6
7
1018
1019
1020
1021
1022
1023
Offset
Error
Code Out
AVIN (LSBideal)
OSe
Offset
Error
OSe
Gain
Error
Ge
Ideal Transfer Curve
1 LSB
(Ideal)
Integral Non-linearity (ILe)
Differential Non-linearity (DLe)
Center of a Step
Exampl e of an Actual Tr ansf er C urve
0
0
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6.3.8 Flash Memory
6.3.8.1 Definition of Symbols
Table 19. Flash Memory Timing Symbol Definitions
6.3.8.2 Timings Table 20. Flash Memory AC Timing
VDD = 2.7 to 3.3V, TA = -40° to +85°C
6.3.8.3 Waveforms
Figure 6-21. Flash Memory – ISP Waveforms
Note: 1. ISP must be driven through a pull-down resistor (see Section “In-system Programming”,
page 18).
Figure 6-22. Flash Memory – Internal Busy Waveforms
6.3.9 External Clock Drive and Logic Level References
6.3.9.1 Definition of Symbols
Table 21. E xter na l Clock Timi ng Sy mbo l Defi niti on s
Signals Conditions
SISP L Low
RRST VValid
B FBUSY flag X No Longer Valid
Symbol Parameter Min Typ Max Unit
TSVRL Input ISP Valid to RST Edge 50 ns
TRLSX Input ISP Hold after RST Edge 50 ns
TBHBL FLASH Internal Busy (Programming) Time 10 ms
NFCY Number of Flash Write Cycles 100K Cycle
TFDR Flash Data Retention Time 10 Year
RST TSVRL
ISP(1)
TRLSX
FBUSY bit TBHBL
Signals Conditions
C Clock H High
L Low
X No Longer Valid
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6.3.9.2 Timings Table 22. External Clock AC Timings
VDD = 2.7 to 3.3V, TA= -40 to +85°C
6.3.9.3 Waveforms
Figure 6-23. External Clock Waveform
Figure 6-24. AC Testing Input/Output Waveforms
Notes: 1. D uring AC te sting, all inputs a re driven at VDD -0.5V for a logic 1 and 0.45V for a logic 0.
2. Timing measurements are made on all outputs at VIH min for a logic 1 and VIL max for a logic 0.
Figure 6-25. Float Waveforms
Note: For ti mi ng purp os es, a port pin is no lo nge r flo ating when a 100 mV change from l oad vo lt age occurs a nd beg ins to flo at w hen a
100 mV change from the loading VOH/VOL level occurs with IOL/IOH = ±20 mA.
Symbol Parameter Min Max Unit
TCLCL Clock Period 50 ns
TCHCX High Time 10 ns
TCLCX Low Time 10 ns
TCLCH Rise Time 3 ns
TCHCL Fall Time 3 ns
TCR Cyclic Ratio in X2 Mode 40 60 %
0.45 V TCLCL
VDD - 0.5 VIH1
VIL
TCHCX
TCLCH
TCHCL
TCLCX
0.45 V
V
DD - 0.5 0.7 VDD
0.3 VDD
VIH min
VIL max
INPUTS OUTPUTS
VLOAD VOH - 0.1V
VOL + 0.1V
VLOAD + 0.1V
VLOAD - 0.1V Timing Reference Points
34 4173ES–USB–09/07
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7. Ordering Information
Note: 1. PLCC84 package only available for development board.
Possible Order Entries(1)
Part Number Memory Size
(Bytes) Supply
Voltage Temperature
Range
Max
Frequency
(MHz) Package Packing Product
Marking
AT89C5132-R OTI L 64K Flash 3V Industrial 40 TQFP80 Tray 895132-IL
AT89C5132- ROTUL 64K Flas h 3V Industrial &
Green 40 TQFP80 Tray 895132-UL
35
4173ES–USB–09/07
AT89C5 132
8. Package Information
8.1 TQFP80
36 4173ES–USB–09/07
AT89C5132
8.2 PLCC84
37
4173ES–USB–09/07
AT89C5 132
9. Datasheet Revision History for AT89C5132
9.1 Changes from 4173A-08/02 to 4173B-03/04
1. Suppression of ROM product version.
2. Suppression of TQFP64 package.
9.2 Cha nges from 4173B-03/0 4 - 4173C - 07/04
1. Add USB connection schematic in USB section.
2. Add USB termination characteristics in DC Characteristics section.
3. Page access mode clarification in Data Memory section.
9.3 Cha nges from 4173C-07/0 4 - 4173D - 01/05
1. Interrupt priority number clarification to match number defined by development tools.
9.4 Changes from to 4317D - 01/05 to 4173E - 09/07
1. Added green product ordering information.
2. Removed ‘Preliminary’ status. Product now fully Industrialised.
Printed on recycled paper.
4173ES–USB–09/07
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