June 1992 Edition 1.0A DATA SHEET MB40730 1-Channel, 10-Bit ASSP Image Processing D/A Converter (60 MSPS) The MB40730 is a low-power consumption, high-speed 10-bit D/A converter. It is characterized by ECL (10KH) compatible digital inputs, an analog output voltage ranging from -2 V to 0 V, and a maximum conversion rate of 60 MHz. It provides reference voltage from a potential divider and band-gap reference, or it can use external reference voltage. The MB40730 D/A converter is suitable for use in high-resolution TVs or VTRs. * Resolution: 10 bits * Conversion characteristics: - Maximum conversion rate: - Linearity error: - Differential linearity error: * Input and output: - Digital input voltage: - Analog output voltage: 60 MHz minimum 0.1% maximum 0.1% maximum Plastic DIP (DIP-20P-M01) 10KH ECL levels 2 Vp-p (-2 V to 0 V) * Reference voltage: - VROUT1: Potential divider circuit (VEEA x 2/5.2) - VROUT2: Band-gap reference circuit (-2 V) * Other characteristics: - Supply voltage: - Power dissipation: -5.2 V single power supply 180 mW (typical value at analog output voltage 2 Vp-p) 140 mW (typical value at analog output voltage 1 Vp-p) * Package and ordering information: - 20-pin plastic DIP, order as MB40730P - 20-pin plastic SOP, order as MB40730PF ABSOLUTE MAXIMUM RATINGS Parameter (V CCA - VCCD = 0 V, TA = +25C Symbol Rating Unit Analog Power Supply Voltage VCCA -7.0 to 0 V Digital Power Supply Voltage VCCD -7.0 to 0 V VEED-VEEA 1.0 V VID 0 to VEE V TSTG -55 to +125 C Power Supply Voltage Difference Digital Signal Input Voltage Storage Temperature Plastic SOP (FPT-20P-M01) -- Note -- Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 1992 by FUJITSU LIMITED and Fujitsu Microelectronics, Inc. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. MB40730 PIN ASSIGNMENT (TOP VIEW) (MSB) (LSB) D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 CLK VCCD VCCA A.OUT VROUT2 VRIN VROUT1 COMP VEEA VEED (DIP-20P-M01) (FPT-20P-M01) PIN FUNCTIONS Pin No. Symbol I/O Description 1 to 10 D1 to D10 I Data signal input pin (D1: MSB, D10: LSB) 20 CLK I Clock signal input pin 19 VCCD - Digital ground pin (0V) 18 VCCA - Analog ground pin (0V) 11 VEED - Digital power pin (-5.2V) 12 VEEA - Analog ground pin (-5.2V) Reference voltage input pin Analog output dynamic range setup pin 15 VRIN I (Connect to pin 14 or 16 to use the built-in reference voltage. When using an external reference voltage, the voltage on this pin must be from -2.20V to -0.70V.) Reference voltage output pin 1 (The output voltage of the potential divider reference is fixed at VEEA x 2/5.2. When this pin is connected to pin 15, the analog output voltage ranges from VEEA x 2/5.2 to 0V.) 14 VROUT1 O 16 VROUT2 O 13 COMP - (Insert a capacitor of 0.1 F or greater between VEEA and COMP for phase compensation.) 17 A.OUT O Analog signal output pin Reference voltage output pin 2 (The output voltage of the band-gap reference is fixed at -2.0V. When the pin is connected to pin 15, the analog output voltage ranges from -2V to 0V.) Phase compensation capacitor pin 2 MB40730 BLOCK DIAGRAM CLK A.OUT (MSB) D1 R D2 R 2R R 2R R 2R R 2R R 2R R 2R R R D3 D4 D5 Input Buffer 10 Masterslave Flip Flop Buffer 10 10 Current Switch D6 D7 D8 D9 D10 (LSB) VCCA VCCD Reference Resistor Amplifier Reference Voltage 1 (Potential Divider Reference) Reference Voltage 2 (Band-gap Reference) VCCA VEED VEEA VROUT1 VROUT2 VRIN COMP 3 MB40730 DIGITAL INPUT EQUIVALENT CIRCUIT VCCD D1 to D10 CLK Threshold voltage = -1.3V VEED ANALOG OUTPUT EQUIVALENT CIRCUIT VCCA RO = 240 A.OUT IO VEEA REFERENCE VOLTAGE OUTPUT EQUIVALENT CIRCUIT VCCA VCCA 4 k VROUT1 6 k VEEA BGR - + VROUT2 RS *Overcurrent-prevention resistor (2 k) for a short to GND. 4 MB40730 TYPICAL CONNECTION EXAMPLE VCC VCC D D1 to D10 DATA Input CLK Input A A. OUT VROUT2 VRIN VROUT1 CLK COMP VEE VEE D 0.01 47 Connect to VROUT1, VROUT2 or External Reference Voltage. 0.1 A 2.2 2.2 47 0.01 -5.2 V RECOMMENDED OPERATING CONDITIONS (VCCA = VCCD = 0V, TA = 20 C to +75 C Standard Values Parameter Power supp y supply voltage Symbol Min. Typ. Max. Unit Analog power supply voltage VEEA -5.46 -5.20 -4.94 V Digital power supply voltage VEED -5.46 -5.20 -4.94 V Power supply voltage difference VEEA-VEED -0.2 - 0.2 V -0.220 -2.00 -0.70 V -20C - - -0.88 V -25C -1.13 - -0.81 V -75C - - -0.735 V -20C -1.95 - - V -25C -1.95 - -1.48 V -75C -1.95 - - V Analog reference voltage Digital input high voltage Digital input low voltage VRIN VIHD VILD Clock frequency tCLK - - 60 MHz Setup time tsu 8 - 60 ns Hold time th 2 - - ns Clock minimum pulse width high tWH 6.5 - - ns Clock minimum pulse width low tWL 6.5 - - ns Phase compensation capacitor CCOMP 0.1 - - F Operating temperature Top 20 - 75 C 5 MB40730 DC CHARACTERISTICS (VEEA=VEED=-5.46 to -4.94V, TA=-20C to +75C) Standard Values Parameter Resolution Linearity error Symbol Conditions Min. Typ. Max. Unit - - - - 10 bit - - 0.1 % - - 0.1 % LE DC accuracy Differential linearity error DLE Digital input current high IIHD - - - 5 A Digital input current low IILD - -0.1 - - A Reference input current IRIN VRIN = -2.000V - - 10 A Reference voltage VROUT1 VEEA = -5.20V VEED = -5.20V -2.100 -2.100 -1.900 V Reference voltage VROUT2 - -2.100 -2.100 -1.900 V - - - 100 - ppm/C Full-scale output voltage VOFS - -20 0 - mV Zero-scale output voltage VOZS VEEA = -5.20V VEED = -5.20V VRIN = -2.000V -2.068 -1.998 -1.928 V Output resistance RO TA = +25C 192 240 288 Power dissipation IEE VEEA = -5.46V VEED = -5.46V VRIN = VROUT1 -59 -34* - mA Potential divider reference Band-gap reference Temperature coefficient VEEA = VEED = -5.20V AC CHARACTERISTICS VEEA= VEED=-5.46 to -4.94V, TA=-20C to +75C) Parameter Symbol Conditions Maximum conversion rate Fs CL = 15 pF Output propagation delay time tpd Output rise time tr Output fall time tf Settling time tset A OUT pin A.OUT terminating resistance i t = 240 Standard Values Unit 60 - - MSPS - 7 - ns - 5 - ns - 5 - ns - 17.5 - ns 6 MB40730 TIMING CHART VIHD tsu th -0.9V Data input -1.3 V VILD -1.7V twH twL VIHD -0.9V -1.3V Clock input -1.7V VILD 1/2LSB VOFS 90% 90% 50% 50% Analog output 10% 10% 1/2LSB VOZS tr tf tsetLH tPLH tsetHL tPHL 7 MB40730 DAC OUTPUT VOLTAGE CHARACTERISTICS Input Output D1 to D10 A.OUT 1023 0 (VCCA) VOFS 0.000V 0.000V VOZS (VRIN) -1.998V -2.000V 1 LSB = 2 mV DAC OUTPUT VOLTAGE FORMULA UNDER IDEAL CONDITIONS A.OUT = VCCA - 1023 - N x (VCCA - VRIN) 1024 (N : Digital input code from 0 to 1023) VOFS = VCCA VOZS = VCCA - 1023 1024 x (VCCA - VRIN) NOTES 1. Preventing Switching Noise To prevent switching noise in the analog output signal, connect noise limiting capacitors to the VEEA and VEED pins as close to the VCCA and VCCD pins as possible. 2. Power Pattern To reduce parasitic impedance, the PC board pattern to the VCCA, VCCD, VEEA and VEED pins should be as wide as possible. 8 MB40730 MB40730 STANDARD CURVES 1. Power Supply Current vs. Ambient Temperature 2. Linearity Error vs. Ambient Temperature VEE = -5.46V VRIN = VROUT1 VEE = -5.20V VRIN = -2.000V 0 0.1 -20 0.08 LE , -40 IEE, Power supply current (mA) -60 Linearity error (%) 0.06 0.04 0.02 -80 0 -100 -25 0 25 50 75 100 -25 TA, Ambient temperature (C) 0 25 50 75 100 TA, Ambient temperature (C) 3. Differential Linearity Error vs. Ambient Temperature 4. Output Resistance vs. Ambient Temperature VEE = -5.20V VRIN = -2.000V 0.1 300 0.08 280 DLE , 0.06 Differential linearity error (%) RO, Output 260 resistance () 0.04 240 0.02 220 0 -25 200 0 25 50 75 TA, Ambient temperature (C) 100 -25 0 25 50 75 100 TA, Ambient temperature (C) Continued on next page 9 MB40730 6. Zero-Scale Output Voltage vs. Ambient Temperature 5. Full-Scale Output Voltage vs. Ambient Temperature VEE = -5.20V VRIN = -2.000V VEE = -5.20V VRIN = -2.000V VCC (Reference) -1.900 -10 -1.950 -20 VOFS, Full-scale output voltage -30 (mV) VOZS, Zero-scale -2.000 output voltage (V) -2.050 -40 -2.100 -50 -25 0 25 50 75 100 -25 TA, Ambient temperature (C) 75 100 VEE = -5.20V -1.900 -1.900 -1.950 -1.950 VROUT1, Reference -2.000 output voltage (V) VROUT2, Reference -2.000 output voltage (V) -2.050 -2.050 -2.100 -2.100 25 50 8. VROUT2 Reference Output Voltage vs. Ambient Temperature VEE = -5.20V 0 25 TA, Ambient temperature (C) 7. VROUT1 Reference Output Voltage vs. Ambient Temperature -25 0 50 75 TA, Ambient temperature (C) 100 -25 0 25 50 75 100 TA, Ambient temperature (C) Continued on next page 10 MB40730 9. VROUT2 Reference Output Voltage vs. Power Supply Voltage 10. Setup Time vs. Ambient Temperature TA = 25 C VEE = -5.20V 10 -1.900 8 -1.950 Reference output voltage VROUT2 (V) -2.000 tsu, Setup time (ns) -2.050 6 4 2 -2.100 0 -6.5 -6.0 -5.5 -5.0 -4.5 -25 -4.0 11. Setup Time vs. Power Supply Voltage 25 50 75 100 12. Hold Time vs. Ambient Temperature TA = 25 C tsu, Setup time (ns) 0 Ta, Ambient temperature (C) VCC, Power supply voltage (V) VEE = -5.20V 10 6 8 4 6 tn, Hold time (ns) 4 2 0 -2 2 -4 0 -6.5 -6.0 -5.5 -5.0 -4.5 VEE, Power supply voltage (V) -4.0 -25 0 25 50 75 100 Ta, Ambient temperature (C) Continued on next page 11 MB40730 13. Hold Time vs. Power Supply Voltage 14. Minimum Clock Pulse Width vs. Ambient Temperature TA = 25 C tn, Hold time (ns) VEE = -5.20V 6 10 4 8 2 twL/twH, Minimum clock pulse width (ns) 0 -2 6 twL 4 twH 2 -4 0 -6.5 -6.0 -5.5 -5.0 -4.5 -25 -4.0 25 50 75 100 16. Rise Time / Fall Time vs. Ambient Temperature 15. Minimum Clock Pulse Width vs. Power Supply Voltage VEE = -5.20V VRIN = -2.000V CL = 15 pF Analog output 240 termination (1V amplitude) TA = 25 C twL/twH, Minimum clock pulse width (ns) 0 TA, Ambient temperature (C) VEE, Power supply voltage (V) 10 10 8 8 6 tr/tf, Rise time and fall time (ns) 4 6 4 twL 2 2 twH 0 0 -6.5 -6.0 -5.5 -5.0 -4.5 VEE, Power supply voltage (V) -4.0 -25 0 25 50 75 100 TA, Ambient temperature (C) Continued on next page 12 MB40730 17. Rise Time / Fall Time vs. Power Supply Voltage 18. Quantization Noise vs. Analog Output Frequency Ta= 25 C VRIN = -2.000V CL = 15 pF Analog output 240 termination (1V amplitude) tr/tf, Rise time and fall time (ns) 10 70 8 60 6 4 50 S/Nq, Quantization noise (dB) 40 2 30 0 fCLK = 15 MHz fCLK = 30 MHz fCLK = 60 MHz 20 -6.5 -6.0 -5.5 -5.0 -4.5 VEE, Power supply voltage (V) -4.0 0 5 10 15 20 25 fOUT, Analog output frequency (MHz) 13 MB40730 PACKAGE DIMENSIONS 20-LEAD PLASTIC DUAL IN-LINE PACKAGE (CASE No.: DIP-20P-M01) 15MAX .970 +.008 (24.64 +0.20 ) -.012 -0.30 INDEX-1 .260.010 (6.600.25) .300(7.62) TYP INDEX-2 .034 +.012 -0 (0.86+0.30 ) -0 .010.002 (0.250.05) .050 +.012 -0 (1.27 +0.30 ) -0 .172(4.36) MAX .118(3.00) MIN .050(1.27) MAX .100(2.54) TYP 1991 FUJITSU LIMITED D20005S-3C .018.003 (0.460.08) .020(0.51) MIN Dimensions in inches (millimeters) 14 MB40730 PACKAGE DIMENSIONS (Continued) 20-LEAD PLASTIC FLAT PACKAGE (CASE No.: FPT-20P-M01) .089(2.25) MAX (MOUNTING HEIGHT) +.010 +0.25 .500 (12.70 ) -.008 -0.20 .002(0.05) MIN (STAND OFF HEIGHT) .307.016 (7.800.40) INDEX +.016 +0.40 .268 (6.80 ) -.008 -0.20 .209.012 (5.300.30) .020.008 (0.500.20) .050(1.27) TYP .018.004 (0.450.10) +.002 +0.05 .006 (0.15 ) -.001 -0.02 .005(0.13) M Details of "A" part "A" .004(0.10) .450(11.43) REF 1991 FUJITSU LIMITED F20003S-5C .008(0.20) .020(0.50) .007(0.18) MAX .027(0.68) MAX Dimensions in inches (millimeters) All Rights Reserved. Circuit diagrams utilizing Fujitsu products are included as a means of illustrating typical semiconductor applications. Complete Information sufficient for construction purposes is not necessarily given. The information contained in this document has been carefully checked and is believed to be reliable. However, Fujitsu assumes no responsibility for inaccuracies. The Information contained in this document does not convey any license under the copyrights, patent rights or trademarks claimed and owned by Fujitsu. Fujitsu reserves the right to change products or specifications without notice. No part of this publication may be copied or reproduced in any form or by any means, or transferred to any third party without prior written consent of Fujitsu. 15