M68HC11EVBU2/D

April 1998

M68HC11EVBU

UNIVERSAL EVALUATION BOARD

USER’S MANUAL

© MOTOROLA Inc. 1990, 1998; All Rights Reserved

Motorola reserves the right to make changes without further notice to any products herein to

improve reliability, function, or design. Motorola does not assume any liability arising out of the

officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs,

damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any

claim of personal injury or death associated with such unintended or unauthorized use, even if

such claim alleges that Motorola was negligent regarding the design or manufacture of the part.

The computer program stored in the Read Only Memory of the device contains material

copyrighted by Motorola Inc., first published 1990, and may be used only under a license such as

the License For Computer Programs (Article 14) contained in Motorola’s Terms and Conditions

of Sale, Rev. 1/79.

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accessible from address location $8000 through $FFFF except where an on-chip resource has

higher priority. The board defaults to normal-expanded mode rather than single-chip mode so

this additional RAM can be used.

For the M68HC11EVBU2 normal configuration, the MC68HC11E9 MCU on-chip ROM

occupies the address space from $D000 through $FFFF. A factory ROM test pattern uses the 4K

from $D000 through $DFFF and the BUFFALO monitor program uses the space from $E000

through $FFFF. The on-chip EEPROM occupies the space from $B600 through $B7FF. The

BUFFALO monitor does not use any of this new RAM so the spaces from $8000 through $B5FF

and $B800 through $CFFF are available to the user.

On the original M68HC11EVBU board a cut-trace short across jumper header J4 holds the

a 74HC00 quad NAND (U8). The latch de-multiplexes the low order addresses from port C of

the MCU. The 74HC00 decodes the select signal for the RAM to map it to the $8000 through

$FFFF area of the memory map. Even though the external 32K RAM is selected when the

internal ROM is accessed, there is no conflict because the MC68HC11E9 ignores the external

data bus during those cycles.

Do not operate the M68HC11EVBU2 board in special expanded test mode with the IRVNE

control bit in the HPRIO register set to 1. This mode is requested when the EVBU2 is reset with

a shorting jumper installed on J3 and no jumper installed on J4. This could cause a data bus fight

between the external RAM data bus drivers and port C during visible internal access cycles. This

conflict could interfere with normal operation.

this looks like the same mapping as the 32K device, you could not store different values at

$8000, $A000, $C000, and $E000 because all of these addresses select the same physical byte in

the 8K RAM. If you leave the cut-trace short intact on J16 and install an 8K device, it would be

mapped at $A000-BFFF and $E000-FFFF (only where A13 and A15 equal 1).

Using Ports B and C as general purpose I/O pins

Remove the RAM (U7) from its socket, and place a jumper across jumper header J4. This makes

the EVBU2 look just like an unmodified M68HC11EVBU. The jumper on J4 cause the board to

reset into single chip mode so ports B and C are general purpose I/O pins rather than being used

as the multiplexed address/data bus.

Using PCbug11