© Semiconductor Components Industries, LLC, 2014
May, 2019 − Rev. 11
1Publication Order Number:
NTD110N02R/D
NTD110N02R, STD110N02R
MOSFET – Power,
N-Channel, DPAK
24 V, 110 A
Features
•Planar HD3e Process for Fast Switching Performance
•Low RDS(on) to Minimize Conduction Loss
•Low Ciss to Minimize Driver Loss
•Low Gate Charge
•Optimized for High Side Switching Requirements in
High−Efficiency DC−DC Converters
•S Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements; AEC−Q101 Qualified and
PPAP Capable
•These Devices are Pb−Free and are RoHS Compliant
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating Symbol Value Unit
Drain−to−Source Voltage VDSS 24 V
Gate−to−Source Voltage − Continuous VGS ±20 V
Thermal Resistance − Junction−to−Case
Total Power Dissipation @ TC = 25°C
Drain Current
− Continuous @ TC = 25°C, Chip
− Continuous @ TC = 25°C
Limited by Package
− Continuous @ TA = 25°C
Limited by Wires
− Single Pulse (tp = 10 ms)
RqJC
PD
ID
ID
ID
ID
1.35
110
110
110
32
110
°C/W
W
A
A
A
A
Thermal Resistance
− Junction−to−Ambient (Note 1)
− Total Power Dissipation @ TA = 25°C
− Drain Current − Continuous @ TA = 25°C
RqJA
PD
ID
52
2.88
17.5
°C/W
W
A
Thermal Resistance
− Junction−to−Ambient (Note 2)
− Total Power Dissipation @ TA = 25°C
− Drain Current − Continuous @ TA = 25°C
RqJA
PD
ID
100
1.5
12.5
°C/W
W
A
Operating and Storage Temperature Range TJ, Tstg −55 to
175
°C
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C
(VDD = 50 Vdc, VGS = 10 Vdc,
IL = 15.5 Apk, L = 1.0 mH, RG = 25 W)
EAS 120 mJ
Maximum Lead Temperature for Soldering
Purposes, (1/8″ from case for 10 s)
TL260 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. When surface mounted to an FR4 board using 0.5 sq in drain pad size.
2. When surface mounted to an FR4 board using the minimum recommended
pad size.
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24 V 4.1 mW @ 10 V
RDS(on) TYP
110 A
ID MAXV(BR)DSS
N−Channel
D
S
G
DPAK
CASE 369AA
(Surface Mount)
STYLE 2
12
3
4
MARKING DIAGRAM
& PIN ASSIGNMENT
1
Gate
3
Source
2
Drain
4
Drain
AYWW
T
110N2G
A = Assembly Location*
Y = Year
WW = Work Week
T110N2 = Device Code
G = Pb−Free Package
See detailed ordering and shipping information on page 5 of
this data sheet.
ORDERING INFORMATION
* The Assembly Location code (A) is front side
optional. In cases where the Assembly Location is
stamped in the package, the front side assembly
code may be blank.
NTD110N02R, STD110N02R
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2
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage (Note 3)
(VGS = 0 V, ID = 250 mA)
Positive Temperature Coefficient
V(BR)DSS
24 28
15
V
mV/°C
Zero Gate Voltage Drain Current
(VDS = 20 V, VGS = 0 V)
(VDS = 20 V, VGS = 0 V, TJ = 125°C)
IDSS
1.5
10
mA
Gate−Body Leakage Current (VGS = ±20 V, VDS = 0 V) IGSS ±100 nA
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage (Note 3)
(VDS = VGS, ID = 250 mA)
Negative Threshold Temperature Coefficient
VGS(th)
1.0 1.5
5.0
2.0
V
mV/°C
Static Drain−to−Source On−Resistance (Note 3)
(VGS = 10 V, ID = 110 A)
(VGS = 4.5 V, ID = 55 A)
(VGS = 10 V, ID = 20 A)
(VGS = 4.5 V, ID = 20 A)
RDS(on)
4.1
5.5
3.9
5.5
4.6
6.2
mW
Forward Transconductance (VDS = 10 V, ID = 15 A) (Note 3) gFS 44 Mhos
DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = 20 V, VGS = 0 V, f = 1.0 MHz)
Ciss 2710 3440 pF
Output Capacitance Coss 1105 1670
Transfer Capacitance Crss 450 640
SWITCHING CHARACTERISTICS (Note 4)
Turn−On Delay Time
(VGS = 10 V, VDD = 10 V,
ID = 40 A, RG = 3.0 W)
td(on) 11 22 ns
Rise Time tr39 80
Turn−Off Delay Time td(off) 27 40
Fall Time tf21 40
Gate Charge
(VGS = 4.5 V, ID = 40 A,
VDS = 10 V) (Note 3)
QT23.6 28 nC
QGS 5.1
QGD 11
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage (IS = 20 A, VGS = 0 V) (Note 3)
(IS = 55 A, VGS = 0 V)
(IS = 20 A, VGS = 0 V, TJ = 125°C)
VSD 0.82
0.99
0.65
1.2 V
Reverse Recovery Time
(IS = 30 A, VGS = 0 V,
dIS/dt = 100 A/ms) (Note 3)
trr 36.5 ns
ta30
tb25
Reverse Recovery Stored Charge Qrr 0.048 mC
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
4. Switching characteristics are independent of operating junction temperatures.
NTD110N02R, STD110N02R
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3
4.2 V
2.0
1.6
1.2
1.4
1.0
0.8
0.6 10
1000
100,000
010
100
42
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
ID, DRAIN CURRENT (AMPS)
0
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics
ID, DRAIN CURRENT (AMPS)
2
0.02
1086
0.01
0
4
Figure 3. On−Resistance versus
Gate−to−Source Voltage
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
ID, DRAIN CURRENT (AMPS)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
Figure 5. On−Resistance Variation with
Temperature
TJ, JUNCTION TEMPERATURE (°C)
Figure 6. Drain−to−Source Leakage Current
versus Voltage
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
RDS(on), DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
IDSS, LEAKAGE (nA)
175
−50 50250−25 75 125100
042
01510 255.0
6
50
25
150
VDS ≥ 10 V
TJ = 25°C
TJ = −55°C
TJ = 175°C
VGS = 4.5 V
175
VGS = 0 V
ID = 55 A
VGS = 10 V
0.03
0.008
0.006
0
0.014
TJ = 175°C
TJ = 100°C
120
0
210
90
30
180
68
0.004
20 1601208040 240
TJ = 25°C
20
100
8
10 V
3.8 V
4.5 V
5 V
6 V
8 V
10,000
ID = 110 A
TJ = 25°C
0.002
0.01
0.012
60 100 220200140 180
VGS = 10 V
1.8
150
75
125
TJ = 25°C
4 V
3.6 V
3.4 V
3.2 V
2.6 V
2.8 V
3 V
2.4 V
60
150
NTD110N02R, STD110N02R
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4
RDS(on) Limit
Thermal Limit
Package Limit
VGS
1000
100
10
1.0
1000
1
5
4
3
2
1
0
120
100
80
60
0
10 10
5000
155020
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
C, CAPACITANCE (pF)
4000
3000
2000
1000
0
5
Qg, TOTAL GATE CHARGE (nC)
Figure 7. Capacitance Variation Figure 8. Gate−to−Source and
Drain−to−Source Voltage versus Total Charge
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 9. Resistive Switching Time Variation
versus Gate Resistance
RG, GATE RESISTANCE (W)
Figure 10. Diode Forward Voltage versus
Current
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
IS, SOURCE CURRENT (AMPS)
t, TIME (ns)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
ID, DRAIN CURRENT (AMPS)
01520105
1 10 100 0.4 0.8 1.21.0
0.1 10 1001.0
ID = 40 A
TJ = 25°C
VGS
VGS = 0 V
VDS = 0 V TJ = 25°C
Crss
Ciss
Coss
Crss
40
20
0.6
Ciss
VGS = 20 V
SINGLE PULSE
TC = 25°C
VDS = 10 V
ID = 55 A
VGS = 10 V
VGS = 0 V
TJ = 25°C
10 ms
1 ms
dc
tr
td(off)
td(on)
tf
VDS
QDS
QT
25
100
20
16
12
8
4
0
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
VDS
QGS
10
NTD110N02R, STD110N02R
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5
0.2
1.0
0.1
0.01
t, TIME (s)
D = 0.5
0.1
0.05
0.02
0.01 Single Pulse
Figure 12. Thermal Response
r(t), EFFECTIVE TRANSIENT THERMAL
RESISTANCE (NORMALIZED)
0.00001 0.0001 0.001 0.01 0.1 1.0 10
ORDERING INFORMATION
Device Package Shipping†
NTD110N02RT4G DPAK
(Pb−Free)
2500 / Tape & Reel
STD110N02RT4G* DPAK
(Pb−Free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*S Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP
Capable.
DPAK (SINGLE GUAGE)
CASE 369AA−01
ISSUE B
DATE 03 JUN 2010
SCALE 1:1
STYLE 1:
PIN 1. BASE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
STYLE 3:
PIN 1. ANODE
2. CATHODE
3. ANODE
4. CATHODE
STYLE 4:
PIN 1. CATHODE
2. ANODE
3. GATE
4. ANODE
STYLE 5:
PIN 1. GATE
2. ANODE
3. CATHODE
4. ANODE
b
D
E
b3
L3
L4
b2
eM
0.005 (0.13) C
c2
A
c
C
Z
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
D0.235 0.245 5.97 6.22
E0.250 0.265 6.35 6.73
A0.086 0.094 2.18 2.38
b0.025 0.035 0.63 0.89
c2 0.018 0.024 0.46 0.61
b2 0.030 0.045 0.76 1.14
c0.018 0.024 0.46 0.61
e0.090 BSC 2.29 BSC
b3 0.180 0.215 4.57 5.46
L4 −−− 0.040 −−− 1.01
L0.055 0.070 1.40 1.78
L3 0.035 0.050 0.89 1.27
Z0.155 −−− 3.93 −−−
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. THERMAL PAD CONTOUR OPTIONAL WITHIN DI-
MENSIONS b3, L3 and Z.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL
NOT EXCEED 0.006 INCHES PER SIDE.
5. DIMENSIONS D AND E ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY.
6. DATUMS A AND B ARE DETERMINED AT DATUM
PLANE H.
12 3
4
STYLE 6:
PIN 1. MT1
2. MT2
3. GATE
4. MT2
STYLE 7:
PIN 1. GATE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
XXXXXX = Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
WW = Work Week
G = Pb−Free Package
YWW
XXX
XXXXXG
XXXXXXG
ALYWW
DiscreteIC
12
3
4
5.80
0.228
2.58
0.102
1.60
0.063
6.20
0.244
3.00
0.118
6.17
0.243
ǒmm
inchesǓ
SCALE 3:1
GENERIC
MARKING DIAGRAM*
*This information is generic. Please refer
to device data sheet for actual part
marking.
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
H0.370 0.410 9.40 10.41
A1 0.000 0.005 0.00 0.13
L1 0.108 REF 2.74 REF
L2 0.020 BSC 0.51 BSC
A1
H
DETAIL A
SEATING
PLANE
A
B
C
L1
L
H
L2 GAUGE
PLANE
DETAIL A
ROTATED 90 CW5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
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DOCUMENT NUMBER:
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DPAK (SINGLE GAUGE)
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