R5F21346CNFP#V0 - Renesas Electronics

To our custo mers,

Old Company Name in Catalogs and Other Documents

On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology

Corporation, and Renesas Electronics Corpor ation took over all the business of both

companies. Therefore, althoug h the old com pany name remains in this docum ent, it is a valid

Renesas Electronics document. W e appreciate your understanding.

Renesas Electronics website: http://www.renesas.com

April 1st, 2010

Renesas Electronics Corporation

Issued by: Renesas Electronics Corporation (http://www.renesas.com)

Send any inquiries to http://www.renesas.com/inquiry.

Notice

1. All information included in this document is current as of the date this document is issued. Such information, however, is

subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please

confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to

additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website.

2. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights

of third parties by or arising from the use of Renesas Electronics products or technical information described in this document.

No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights

of Renesas Electronics or others.

3. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part.

4. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of

semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software,

and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by

you or third parties arising from the use of these circuits, software, or information.

5. When exporting the products or technology described in this document, you should comply with the applicable export control

laws and regulations and follow the procedures required by such laws and regulations. You should not use Renesas

Electronics products or the technology described in this document for any purpose relating to military applications or use by

the military, including but not limited to the development of weapons of mass destruction. Renesas Electronics products and

technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited

under any applicable domestic or foreign laws or regulations.

6. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics

does not warrant that such information is error free. Ren esas E lectronics assumes no liability whatsoever for any da mages

incurred by you resulting from errors in or omissions from the information included herein.

7. Renesas Electronics products are classified acco rding to the following three quality grades: “Standard”, “High Quality”, and

“Specific”. The recommended applications for each Renesas Electronics product depends on the product’s quality grade, as

indicated below. You must check the quality grade of each Renesas Electronics product before using it in a particular

application. You may not use any Renesas Electronics product for any application categorized as “Specific” without the prior

written consent of Renesas Electronics. Further, you may not use any Renesas Electronics product for any application for

which it is not intended without the prior written consent of Renesas Electronics. Renesas Electronics shall not be in any way

liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an

application categorized as “Specific” or for which the product is not intended where you have failed to obtain the prior written

consent of Renesas Electronics. The quality grade of each Renesas Electronics product is “Standard” unless otherwise

expressly specified in a Renesas Electronics data sheets or data books, et c.

“Standard”: Computers; office equipment; communications equipment; test and measurement equipment; audio and visual

equipment; home electro nic app liances; machine tool s; p ersonal electron ic equipment; and indu strial robots .

“High Quality”: Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-

crime systems; safety equipment; and medical equipment not specifically designed for life support.

“Specific”: Aircraft; aerospace equ i pment; submersible repeaters; nu clear reactor control systems; medical equipment or

systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare

interven tion (e.g. excision, et c.), and any oth er applications or purposes that pose a direct th reat to human life.

8. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics,

especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation

characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or

damages arising out of the use of Renesas Electronics products beyond such specified ranges.

9. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have

specific chara cterist ics such as the o ccurren ce of failure at a certai n rate an d malfunct ion s under certai n u se cond ition s. Further,

Renesas Electronics pr oducts are not subject to radiation resi stance design. Please be sure to implement safety measures to

guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a

Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire

control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because

the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system

manufactured by you.

10. Please contact a Renesas Electronics sales office for det ai ls as to enviro nmental matters such as the en vi ronmental

compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable

laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS

Directive. Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with

applicable laws and regulations.

11. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas

Electronics.

12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this

document or Renesas Electronics products, or if you have any other inquiries.

(Note 1) “Renesas Electronics” as us ed in this document means Renesas Electronics Corporation and also includes its majo ri ty-

owned subsidiaries.

(Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.

User’s Manual

R8C/34C Group

Hardware Manual

User’s Manual

Rev.1.00 2010.01

RENESAS MCU

R8C FAMILY / R8C/3x SERIES

All information contained in these materials, including products and product speciﬁcations,

represents information on the product at the time of publication and is subject to change by

Renesas Electronics Corp. without notice. Please review the latest information published by

Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.

website (http://www.renesas.com).

1. This document is provided for reference purposes only so that Renesas customers may select the appropriate

Renesas products for their use. Renesas neither makes warranties or representations with respect to the

accuracy or completeness of the information contained in this document nor grants any license to any

intellectual property rights or any other rights of Renesas or any third party with respect to the information in

this document.

2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising

out of the use of any information in this document, including, but not limited to, product data, diagrams, charts,

programs, algorithms, and application circuit examples.

3. You should not use the products or the technology described in this document for the purpose of military

applications such as the development of weapons of mass destruction or for the purpose of any other military

use. When exporting the products or technology described herein, you should follow the applicable export

control laws and regulations, and procedures required by such laws and regulations.

4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and

application circuit examples, is current as of the date this document is issued. Such information, however, is

subject to change without any prior notice. Before purchasing or using any Renesas products listed in this

document, please confirm the latest product information with a Renesas sales office. Also, please pay regular

and careful attention to additional and different information to be disclosed by Renesas such as that disclosed

through our website. (http://www.renesas.com )

5. Renesas has used reasonable care in compiling the information included in this document, but Renesas

assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information

included in this document.

6. When using or otherwise relying on the information in this document, you should evaluate the information in

light of the total system before deciding about the applicability of such information to the intended application.

Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any

particular application and specifically disclaims any liability arising out of the application and use of the

information in this document or Renesas products.

7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas

products are not designed, manufactured or tested for applications or otherwise in systems the failure or

malfunction of which may cause a direct threat to human life or create a risk of human injury or which require

especially high quality and reliability such as safety systems, or equipment or systems for transportation and

traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication

transmission. If you are considering the use of our products for such purposes, please contact a Renesas

sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above.

8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below:

(1) artificial life support devices or systems

(2) surgical implantations

(3) healthcare intervention (e.g., excision, administration of medication, etc.)

(4) any other purposes that pose a direct threat to human life

Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who

elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas

Technology Corp., its affiliated companies and their officers, directors, and employees against any and all

damages arising out of such applications.

9. You should use the products described herein within the range specified by Renesas, especially with respect

to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation

characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or

damages arising out of the use of Renesas products beyond such specified ranges.

10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific

characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use

conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and

injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for

hardware and software including but not limited to redundancy, fire control and malfunction prevention,

appropriate treatment for aging degradation or any other applicable measures. Among others, since the

evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or

system manufactured by you.

11. In case Renesas products listed in this document are detached from the products to which the Renesas

products are attached or affixed, the risk of accident such as swallowing by infants and small children is very

high. You should implement safety measures so that Renesas products may not be easily detached from your

products. Renesas shall have no liability for damages arising out of such detachment.

12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written

approval from Renesas.

13. Please contact a Renesas sales office if you have any questions regarding the information contained in this

document, Renesas semiconductor products, or if you have any other inquiries.

Notes regarding these materials

General Precautions in the Handling of MPU/MCU Products

The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes

on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under

General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each

other, the description in the body of the manual takes precedence.

1. Handling of Unused Pins

Handle unused pins in accord with the directions given under Handling of Unused Pins in the

manual.

 The input pins of CMOS products are generally in the high-impedance state. In operation

with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the

vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur

due to the false recognition of the pin state as an input signal become possible. Unused

pins should be handled as described under Handling of Unused Pins in the manual.

2. Processing at Power-on

The state of the product is undefined at the moment when power is supplied.

 The states of internal circuits in the LSI are indeterminate and the states of register

settings and pins are undefined at the moment when power is supplied.

In a finished product where the reset signal is applied to the external reset pin, the states

of pins are not guaranteed from the moment when power is supplied until the reset

process is completed.

In a similar way, the states of pins in a product that is reset by an on-chip power-on reset

function are not guaranteed from the moment when power is supplied until the power

reaches the level at which resetting has been specified.

3. Prohibition of Access to Reserved Addresses

Access to reserved addresses is prohibited.

 The reserved addresses are provided for the possible future expansion of functions. Do

not access these addresses; the correct operation of LSI is not guaranteed if they are

accessed.

4. Clock Signals

After applying a reset, only release the reset line after the operating clock signal has become

stable. When switching the clock signal during program execution, wait until the target clock

signal has stabilized.

 When the clock signal is generated with an external resonator (or from an external

oscillator) during a reset, ensure that the reset line is only released after full stabilization of

the clock signal. Moreover, when switching to a clock signal produced with an external

resonator (or by an external oscillator) while program execution is in progress, wait until

the target clock signal is stable.

5. Differences between Products

Before changing from one product to another, i.e. to one with a different part number, confirm

that the change will not lead to problems.

 The characteristics of MPU/MCU in the same group but having different part numbers may

differ because of the differences in internal memory capacity and layout pattern. When

changing to products of different part numbers, implement a system-evaluation test for

each of the products.

How to Use This Manual

1. Purpose and Target Readers

This manual is designed to provide the user with an understanding of the hardware functions and electrical

characteristics of the MCU. It is intended for users designing application systems incorporating the MCU. A basic

knowledge of electric circuits, logical circuits, and MCUs is necessary in order to use this manual.

The manual comprises an overview of the product; descriptions of the CPU, system control functions, peripheral

functions, and electrical characteristics; and usage notes.

Particular attention should be paid to the precautionary notes when using the manual. These notes occur

within the body of the text, at the end of each section, and in the Usage Notes section.

The revision history summarizes the locations of revisions and additions. It does not list all revisions. Refer

to the text of the manual for details.

The following documents app ly to the R8C/34C Group. Make su re to refer to the latest versions of these do cuments.

The newest versions of the documents listed may be obtained from the Renesas Technology Web site.

Document Type Description Document Title Document No.

Shortsheet Hardware overview and electrical characteristics R8C/34C Group

Shortsheet REJ03B0282

Hardware manual Hardware specifications (pin assignments,

memory maps, peripheral function

specifications, electrical characteristics, timing

charts) and operation description

Note: Refer to the applicat ion notes for details on

using peripheral functions.

R8C/34C Group

Hardware Manual This hardware

manual

Software manual Description of CPU instruction set R8C/Tiny Series

Software Manual REJ09B0001

Application note Information on using peripheral functions and

application examples

Sample programs

Information on writing programs in assembly

language and C

Available from Renesas

Technology Web site.

Renesas

technical update Product specifications, updates on documents,

etc.

2. Notation of Numbers and Symbols

The notation conventions for register names, bit names, numbers, and symbols used in this manual are described

below.

(1) Register Names, Bit Names, and Pin Names

Registers, bits, and pins are referred to in the te xt by symbols. The symbol is accompan ied by the word “register,”

“bit,” or “pin” to distinguish the three categories.

Examples the PM03 bit in the PM0 register

P3_5 pin, VCC pin

(2) Notation of Numbers

The indication “b” is appended to numeric values given in binary format. However, nothing is appended to the

values of single bits. The indication “h” is appended to numeric values given in hexadecimal format. Nothing is

appended to numeric values given in decim al format.

Examples Binary: 11b

Hexadecimal: EFA0h

Decimal: 123 4

3. Register Notation

The symbols and terms used in register diagrams are described below.

x.x.x XXX Register (Symbol)

*1 R/W: Read and write.

R: Read only.

W: Write only.

−: Nothing is assigned.

• Reserved bit

Reserved bit. Set to specified value.

• Nothing is assigned.

Nothing is assigned to the bit. As the bit may be used fo r future functions, if necessary, set to 0.

• Do not set to a value.

Operation is not guaranteed when a value is set.

• Function varies according to the operating mode.

The function of the bit varies with the peripheral function mode. Refer to the register diagram for information

on the individual mode s.

Address XXXXh

Bitb7b6b5b4b3b2b1b0

Symbol XXX7 XXX6 XXX5 XXX4 — — XXX1 XXX0

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 XXX0 XXX bit b1 b0

0 0: XXX

0 1: XXX

1 0: Do not set.

1 1: XXX

R/W

b1 XXX1 R/W

b2 — Nothing is assigned. If necessary, set to 0. When read, the content is undefined. —

b3 — Reserved bit Set to 0. R/W

b4 XXX4 XXX bit Function varies according to the operating mode. R/W

b5 XXX5 W

b6 XXX6 R/W

b7 XXX7 XXX bit 0: XXX

1: XXX R

*2 *3

4. List of Abbreviations and Acronyms

All trademarks and registered trademarks are the property of their respective owners.

Abbreviation Full Form

ACIA Asynchronous Communication Interface Adapter

bps bits per second

CRC Cyclic Redundancy Check

DMA Direct Memory Access

DMAC Direct Memory Access Controller

GSM Global System for Mobile Communications

Hi-Z High Impedance

IEBus Inter Equipment Bus

I/O Input/Output

IrDA Infrared Data Association

LSB Least Significant Bit

MSB Most Significant Bit

NC Non-Connection

PLL Phase Locked Loop

PWM Pulse Width Modulation

SIM Subscriber Identity Module

UART Universal Asynchronous Receiver/Transmitter

VCO Voltage Controlled Oscillator

A - 1

SFR Page Reference ........................................................................................................................... B - 1

1. Overview ......................................................................................................................................... 1

1.1 Features ..................................................................................................................................................... 1

1.1.1 Applications .......................................................................................................................................... 1

1.1.2 Specifications ........................................................................................................................................ 2

1.2 Product List ............................................................................................................................................... 4

1.3 Block Diagram .................................................................. ........................................................................ 5

1.4 Pin Assignment .......................................................................................................................................... 6

1.5 Pin Functions ............................................................................................................................................. 9

2. Central Processing Unit (CPU) .............. ... ... ... .... ... ... ... .... ... ... ... .... ... ... ................... .... ... ... ... ... ....... 11

2.1 Data Registers (R0, R1, R2, and R3) ...................................................................................................... 12

2.2 Address Registers (A0 and A1) ............................................................................................................... 12

2.3 Frame Base Register (FB) ....................................................................................................................... 12

2.4 Interrupt Table Register (INTB) .............................................................................................................. 12

2.5 Program Counter (PC) ................ ..................................... ........................................................................ 12

2.6 User Stack Pointer (USP ) and Interrupt Stack Pointer (ISP) .................................................................. 12

2.7 Static Base Register (SB) ............................................. ........................................................................... 12

2.8 Flag Register (FLG) ................................................................................................................................ 12

2.8.1 Carry Flag (C) ..................................................................................................................................... 12

2.8.2 Debug Flag (D) ................................................................................................................................... 12

2.8.3 Zero Flag (Z) ....................................................................................................................................... 12

2.8.4 Sign Flag (S) ....................................................................................................................................... 12

2.8.5 Register Bank Select Flag (B) ............................................................................................................ 12

2.8.6 Overflow Flag (O) .............................................................................................................................. 12

2.8.7 Interrupt Enable Flag (I) ..................................................................................................................... 13

2.8.8 Stack Pointer Select Flag (U) .............................................................................................................. 13

2.8.9 Processor Interrupt Priority Le vel (IPL) ............................................................ ................................. 13

2.8.10 Reserved Bit .................. ...................................................................................................................... 13

3. Memory ......................................................................................................................................... 14

3.1 R8C/34C Group ....................................................................................................................................... 14

4. Special Function Registers (SFRs) ............................................................................................... 15

5. Resets ....... ................ ................ ................ ................ ................ ................ .................................... 27

5.1 Registers .................................................................................................................................................. 29

5.1.1 Processor Mode Register 0 (PM0) .................................................................. .................................... 29

5.1.2 Reset Source Determination Register (RSTFR) ................................................................................. 29

5.1.3 Option Function Select Register (OFS) .............................................................................................. 30

5.1.4 Option Function Select Register 2 (OFS2) ......................................................................................... 31

5.2 Hardware Reset ....................................................................................................................................... 32

5.2.1 When Power Supply is Stable ............................................................................................................. 32

5.2.2 Power On ............................................................................................................................................ 32

5.3 Power-On Reset Function ....................................................................................................................... 34

5.4 Voltage Monitor 0 Reset ......................................................................................................................... 35

5.5 Watchdog Timer Reset ............................................................................................................................ 36

5.6 Software Reset ......................................................................................................................................... 36

Table of Contents

A - 2

5.7 Cold Start-Up/Warm Start-Up Determination Function ......................................................................... 37

5.8 Reset Source Determination Function ..................................................................................................... 37

6. Voltage Detection Circuit .......................... ... .................... ... ... ... .... ... ................... ... .... ... ... ............. 38

6.1 Overview ................................................................................................................................................. 38

6.2 Registers .................................................................................................................................................. 42

6.2.1 Voltage Mon itor Circu it Control Register (CMPA) ........................................................................... 42

6.2.2 Voltage Monitor Circuit Edge Select Register (VCAC) .................................................................... 43

6.2.3 Voltage Detect Register 1 (VCA1) ..................................................................................................... 43

6.2.4 Voltage Detect Register 2 (VCA2) ..................................................................................................... 44

6.2.5 Voltage Detect ion 1 Level Select Regist er (VD1LS) ......................................................................... 45

6.2.6 Voltage Mon itor 0 C ircu it Control Register (VW0C) ........................................................................ 46

6.2.7 Voltage Mon itor 1 C ircu it Control Register (VW1C) ........................................................................ 47

6.2.8 Voltage Mon itor 2 C ircu it Control Register (VW2C) ........................................................................ 48

6.2.9 Option Function Select Register (OFS) .............................................................................................. 49

6.3 VCC Input Voltage .................................................................................................................................. 50

6.3.1 Monitoring Vdet0 ............................. .................................................................................................. 50

6.3.2 Monitoring Vdet1 ............................. .................................................................................................. 50

6.3.3 Monitoring Vdet2 ............................. .................................................................................................. 50

6.4 Voltage Monitor 0 Reset ......................................................................................................................... 51

6.5 Voltage Monitor 1 Interrupt .................................................................................................................... 52

6.6 Voltage Monitor 2 Interrupt .................................................................................................................... 54

7. I/O Ports ........................................................................................................................................ 56

7.1 Functions of I/O Ports ............................................................................................................................. 56

7.2 Effect on Peripheral Functions ................................................................................................................ 57

7.3 Pins Other than I/O Ports .................... ..................................... ................................................................ 57

7.4 Registers .................................................................................................................................................. 73

7.4.1 Port Pi Direct ion Register (PDi) (i = 0 to 4 or 6) ................................................................................ 73

7.4.2 Port Pi Register (Pi) (i = 0 to 4 or 6) ................................................................................................... 74

7.4.3 Timer RA Pin Select Register (TRASR) ............................................................................................ 75

7.4.4 Timer RB/RC Pin Select Register (TRBRCSR) ................................................................................. 75

7.4.5 Timer RC Pin Select Register 0 (TRCPSR0) ..................................................................................... 76

7.4.6 Timer RC Pin Select Register 1 (TRCPSR1) ..................................................................................... 77

7.4.7 Timer RD Pin Select Register 0 (TRDPSR0) ..................................................................................... 78

7.4.8 Timer RD Pin Select Register 1 (TRDPSR1) ..................................................................................... 78

7.4.9 Timer Pin Select Register (TIMSR) .... ...................................................... ......................................... 79

7.4.10 UART0 Pin Select Register (U0SR) ................................................................................................... 80

7.4.11 UART1 Pin Select Register (U1SR) ................................................................................................... 80

7.4.12 UART2 Pin Select Register 0 (U2SR0) .............................................................................................. 81

7.4.13 UART2 Pin Select Register 1 (U2SR1) .............................................................................................. 81

7.4.14 SSU/IIC Pin Select Register (SSUIICSR) .......................................................................................... 82

7.4.15 INT Interrupt Input Pin Sel e ct Register (INTSR) ............................................................................... 83

7.4.16 I/O Function Pin Select Register (PINSR) ......................................................................................... 84

7.4.17 Pull-Up Control Register 0 (PUR0) .................................................................................................... 85

7.4.18 Pull-Up Control Register 1 (PUR1) .................................................................................................... 85

7.4.19 Port P1 Drive Capacity Control Register (P1DRR) ............................................................................ 86

7.4.20 Port P2 Drive Capacity Control Register (P2DRR) ............................................................................ 86

7.4.21 Drive Capacity Control Register 0 (DRR0) ........................................................................................ 87

A - 3

7.4.22 Drive Capacity Control Register 1 (DRR1) ........................................................................................ 88

7.4.23 Input Threshold Control Register 0 (V LT0) ...... ................................................................................. 89

7.4.24 Input Threshold Control Register 1 (V LT1) ...... ................................................................................. 90

7.5 Port Settings .............................................................. .............................................................................. 91

7.6 Unassigned Pin Handling ...................................................................................................................... 111

8. Bus ............... ................ ................ ................ ................ ................. ................ .............................. 112

9. Clock Generation Circuit ............................................................................................................. 114

9.1 Overview ........................................................................................................................... .................... 114

9.2 Registers ................................................................................................................................................ 117

9.2.1 System Clock Contr o l Regi ster 0 (CM0) .......................................................................................... 117

9.2.2 System Clock Contr o l Regi ster 1 (CM1) .......................................................................................... 118

9.2.3 System Clock Contr o l Regi ster 3 (CM3) .......................................................................................... 119

9.2.4 Oscillation Stop Detection Register (OCD) ...................................................................................... 121

9.2.5 High-Speed On-Chip Oscillator Control Register 7 (FRA7) ............................................................ 121

9.2.6 High-Speed On-Chip Oscillator Control Register 0 (FRA0) ............................................................ 122

9.2.7 High-Speed On-Chip Oscillator Control Register 1 (FRA1) ............................................................ 122

9.2.8 High-Speed On-Chip Oscillator Control Register 2 (FRA2) ............................................................ 123

9.2.9 Clock Prescaler Reset Flag (CPSRF) ........... ..................................................................................... 123

9.2.10 High-Speed On-Chip Oscillator Control Register 4 (FRA4) ............................................................ 124

9.2.11 High-Speed On-Chip Oscillator Control Register 5 (FRA5) ............................................................ 124

9.2.12 High-Speed On-Chip Oscillator Control Register 6 (FRA6) ............................................................ 124

9.2.13 High-Speed On-Chip Oscillator Control Register 3 (FRA3) ............................................................ 124

9.2.14 Voltage Detect Register 2 (VCA2) ................................................................. .................................. 125

9.2.15 I/O Function Pin Select Register (PINSR) ....................................................................................... 126

9.3 XIN Clock ....................... ...................................................................................................................... 128

9.4 On-Chip Oscillator Clock ...................................................................................................................... 129

9.4.1 Low-Speed On-Chip Oscill at or Clock .............................................................................................. 129

9.4.2 High- Sp eed On-Chip Oscillator Clock ............................................................................................. 129

9.5 XCIN Clock ........................................................................................................................................... 130

9.6 CPU Clock and Peripheral Function Clock ........................................................................................... 131

9.6.1 System Clock .................................................................................................................................... 131

9.6.2 CPU Clock ..................................................................................... ................................................... 131

9.6.3 Peripheral Function Clock (f1, f2, f4, f8, and f32) ........................................................................... 131

9.6.4 fOCO ................................................................................................................................................. 131

9.6.5 fOCO40M ......................................................................................................................................... 131

9.6.6 fOCO-F ............................................................................................................................ ................. 131

9.6.7 fOCO-S ............................................................................................................................ ................. 132

9.6.8 fOCO128 .......................................................................................................................... ................. 132

9.6.9 fC, fC2, fC4, and fC32 ..................................................................................................... ................. 132

9.6.10 fOCO-WDT ...................................................................................................................................... 132

9.7 Power Control ........................................................................................................................................ 133

9.7.1 Standard Operating Mode ................................................................................................................. 133

9.7.2 Wait Mode .................... .................................. ................................................... ............................... 135

9.7.3 Stop Mode ......................................................................................................................................... 139

9.8 Oscillation Stop Detection Function ............................................................................................. ........ 142

9.8.1 How to Use Oscillation Stop Detection Function ............................................................................. 143

9.9 Notes on Clock Generation Circuit ....................................................................................................... 146

A - 4

9.9.1 Stop Mode ......................................................................................................................................... 146

9.9.2 Wait Mode .................... .................................. ................................................... ............................... 146

9.9.3 Oscillation Stop Detection Function ................................................................................................. 147

9.9.4 Oscillation Circuit Constants .................................................................................................... ........ 147

10. Protection .............. ................. ................ ................ ................ ................ ................ ..................... 148

10.1 Register ................................................................................................................... ............................... 148

10.1.1 Protect Register (PRCR) ................................................................................................................... 148

11. Interrupts ......... ................ ................ ................ ................. ................ ................ ........................... 149

11.1 Overview ............................................................................................................................................... 149

11.1.1 Types of Interrupts ........................................................................................................ .................... 149

11.1.2 Software Interrupts ................................................................................................................... ........ 150

11.1.3 Special Interrupts ............................................................................................................. ................. 151

11.1.4 Peripheral Funct ion Interrupts ............................................................................................... ........... 151

11.1.5 Interrupts and Interrupt Vectors ................................................................................................ ........ 152

11.2 Registers .................................................................................................................... ............................ 154

11.2.1 Interrupt Control Register

(TREIC, S2TIC, S2RIC, KUPIC, ADIC, S0TIC, S0RIC, S1TIC, S1RIC, TRAIC, TRBIC, U2BCNIC,

VCMP1IC, VCMP2IC) .................................................................................................................... 154

11.2.2 In terr upt Control Register (FMRDYIC, TRCIC, TRD0IC, TRD1IC, SSUIC/IICIC) ..................... 155

11.2.3 INTi Interrupt Control Register (INTiIC) (i = 0 to 4) ....................................................................... 156

11.3 Interrupt Control ................... ...................................................... ................................ ........................... 157

11.3.1 I Flag ..................................................................................................................... ............................ 157

11.3.2 IR Bit ........................................................................................................................................... ...... 157

11.3.3 Bits ILVL2 to ILVL0, IPL ...................... .................................................................................. ........ 157

11.3.4 Interrupt Sequence .................................. .................................................................... ...................... 158

11.3.5 Interrupt Response Time ............................ ....................................................................................... 159

11.3.6 IPL Change when Interrupt Request is Acknowledged .................................................................... 159

11.3.7 Saving Registers ......................................................................................................................... ...... 160

11.3.8 Returning from Interrupt Routine ..................................................................................................... 162

11.3.9 Interrupt Priority ....................................................................... ........................................................ 162

11.3.10 Interrupt Priority Level Selection Circuit ......................................................................................... 163

11.4 INT Interrupt ......................................................................................................................................... 164

11.4.1 INTi Interrupt (i = 0 to 4) ............................................................................................................... ... 164

11.4.2 INT Interrupt Input Pin Select Register (IN TS R ) ............................................................................. 164

11.4.3 External Input Enable Register 0 (INTEN) . ..................................................................................... 165

11.4.4 External Input Enable Register 1 (INTEN1) .................................................................................... 165

11.4.5 INT Input Filter Select Register 0 (INTF) ........................................................................................ 166

11.4.6 INT Input Filter Select Register 1 (INTF1) ...................................................................................... 166

11.4.7 INTi Input Filter (i = 0 to 4) ................ .................................................................................... ......... 167

11.5 Key Input Interrupt ................................................................................................................................ 168

11.5.1 Key Input Enable Register 0 (KIEN) ................................................................................................ 169

11.6 A ddress Match Interrupt .............................. ..................................... ................................ ..................... 170

11.6.1 Address Match Interrupt Enable Register i (AIERi) (i = 0 or 1) ...................................................... 171

11.6.2 Address Match Interrupt Register i (RMADi) (i = 0 or 1) ................................................................ 171

11.7 Timer RC Interrupt, Timer RD Interrupt, Synchronous Serial Commun ication Unit Interrupt, I2C bus

Interface Interrupt, and Flash Memory Interrupt (Interrupts with Multiple Interrupt Request Sources)

................................................................................................................................. ............................... 172

A - 5

11.8 Notes on Interrupts ................................................................................................................................ 174

11.8.1 Reading Add ress 00000 h .................................................................................................................. 174

11.8.2 SP Setting ............................................................................................................................ .............. 174

11.8.3 External Interrupt and Key Input Interrupt ....................................................................................... 174

11.8.4 Changing Interrupt Sources ........................................................................................................ ...... 175

11.8.5 Rewriting Interrupt Control Register ..................................................................................... ........... 176

12. ID Code Areas ............................................................................................................................ 177

12.1 Overview ............................................................................................................................................... 177

12.2 Functions ................................................................................................................... ............................ 178

12.3 Forced Erase Function ..................................................................................................................... ...... 179

12.4 Standard Serial I/O Mode Disabled Function ....................................................................................... 179

12.5 Notes on ID Code Areas .................................................................................................................. ...... 180

12.5.1 Setting Example of ID Code Areas ................. ... ..................................... .................................. ........ 180

13. Option Function Select Area ....................................................................................................... 181

13.1 Overview ............................................................................................................................................... 181

13.2 Registers .................................................................................................................... ............................ 182

13.2.1 Option Function Select Register (OFS) ............................................................................................ 182

13.2.2 Option Function Select Register 2 (OFS2) ................................................................................. ...... 183

13.3 Notes on Option Function Select Area ............................................................................................... ... 184

13.3.1 Setting Example of Option Function Select Area ............................................................................. 184

14. Watchdog Timer ....... ... ... .................... ... ... ... .................... ... ... ................... .... ... ... ........................ 185

14.1 Overview ............................................................................................................................................... 185

14.2 Registers .................................................................................................................... ............................ 187

14.2.1 Processor Mode Register 1 (PM1) .................................................................................................... 187

14.2.2 Watchdog Tim e r Reset Register (WD TR) ........................................................................................ 187

14.2.3 Watchdog Tim er Start Register (WDTS) ......................................................................................... 187

14.2.4 Watchdog Timer Control Register (WDTC) .................................................................................... 188

14.2.5 Count Source Protection Mode Register (CSPR) ............................................................................. 188

14.2.6 Option Function Select Register (OFS) ............................................................................................ 189

14.2.7 Option Function Select Register 2 (OFS2) ................................................................................. ...... 190

14.3 Functional Description ............................... ..................................... ................... .................................. 191

14.3.1 Common Items for Multiple Modes ................................................................................................. 191

14.3.2 Count Source Protection Mode Disabled .......................................................................................... 192

14.3.3 Count Source Protection Mode Enabled ........................................................................................ ... 193

15. DTC ............................................................................................................................................ 194

15.1 Overview ............................................................................................................................................... 194

15.2 Registers .................................................................................................................... ............................ 195

15.2.1 DTC Control Register j (DTCCRj) (j = 0 to 23) ............................................................................... 196

15.2.2 DTC Block Size Register j (DTBLSj) (j = 0 to 23) .......................................................................... 196

15.2.3 DTC Transfer Count Register j (DTCCTj) (j = 0 to 23) ................................................................... 197

15.2.4 DTC Transfer Count Reload Register j (DTRLDj) (j = 0 to 23) ...................................................... 197

15.2.5 DTC Source Address Regi st er j (D TSARj) (j = 0 to 23) .................................................................. 197

15.2.6 DTC Destination Address Register j (DTDARj) (j = 0 to 23) .......................................................... 197

15.2.7 DTC Activation Enable Register i (DTCENi) (i = 0 to 6) ................................................................ 198

15.2.8 DTC Activation Control Register (DTCTL) .................................................................................... 199

A - 6

15.3 Function Description .......................................................................................................................... ... 200

15.3.1 Overview ..................................................................................................................................... ...... 200

15.3.2 Activation Sources ........................................................................................................ .................... 200

15.3.3 Control Data Allocation and DTC Vector Table .............................................................................. 202

15.3.4 Normal Mode ......................................................................................................................... ........... 207

15.3.5 Repeat Mode ..................................................................................................................................... 208

15.3.6 Chain Transfers ................................................................................................................................. 209

15.3.7 Interrupt Sources ....................... ...................................................................... .................................. 209

15.3.8 Operation Timings ........................................................................................................... ................. 210

15.3.9 Number of DTC Execution Cycles ................................................................................................... 211

15.3.10 DTC Activation Source Acknowledgement and Interrupt Source Flags .......................................... 212

15.4 Notes on DTC .................................................................................................................... .................... 214

15.4.1 DTC activation source ...................................................................................................................... 214

15.4.2 DTCENi (i = 0 to 6) Registers .......................................................................................................... 214

15.4.3 Peripheral Modules ................................................................................................................ ........... 214

15.4.4 Interrupt Request ................................................................. .............................................................. 214

16. General Overview of Timers ....................................................................................................... 215

17. Timer RA ..................................................................................................................................... 217

17.1 Overview ............................................................................................................................................... 217

17.2 Registers .................................................................................................................... ............................ 218

17.2.1 Timer RA Control Register (TRACR) ......... ..................................................................................... 218

17.2.2 Timer RA I/O Control Register (TRAIOC) ...................................................................................... 218

17.2.3 Timer RA Mode Register (TRAMR) ................................................................................................ 219

17.2.4 Timer RA Prescaler Register (TRAPRE) ......................................................................................... 219

17.2.5 Timer RA Register (TRA) .................................................................................................. .............. 220

17.2.6 Timer RA Pin Select Register (TRASR) .......................................................................................... 220

17.3 Timer Mode ........................................................................................................................................... 221

17.3.1 Timer RA I/O Control Register (TRAIOC) in Timer Mode ............................................................ 221

17.3.2 Timer Write Control during Count Operation .................................................................................. 222

17.4 Pulse Output Mode ................................................................................................................................ 223

17.4.1 Timer RA I/O Control Register (TRAIOC) in Pulse Output Mode ................................................. 224

17.5 Event Counter Mode ....................................................................................................................... ...... 225

17.5.1 Timer RA I/O Control Register (TRAIOC) in Event Counter Mode ............................................... 226

17.6 Pulse Width Measurement Mode .......................................................................................................... 227

17.6.1 Timer RA I/O Control Register (TRAIOC) in Pulse Width Measurement Mode ............................ 228

17.6.2 Operating Example ........................................................................................................................... 229

17.7 Pulse Period Measurement Mode ..................... .................... ..................................... ................. ........... 230

17.7.1 Timer RA I/O Control Register (TRAIOC) in Pulse Period Measurement Mode ........................... 231

17.7.2 Operating Example ........................................................................................................................... 232

17.8 Notes on Timer RA ............................................................................................................................... 233

18. Timer RB ..................................................................................................................................... 234

18.1 Overview ............................................................................................................................................... 234

18.2 Registers .................................................................................................................... ............................ 235

18.2.1 Timer RB Control Register (TRBCR) .............................................................................................. 235

18.2.2 Timer RB One-Shot Control Register (TRBOCR) ........................................................................... 235

18.2.3 Timer RB I/O Control Register (TRBIOC) ...................................................................................... 236

A - 7

18.2.4 Timer RB Mode Register (TRBMR) ................................................................................................ 236

18.2.5 Timer RB Prescaler Register (TRBPRE) ....................................................................................... ... 237

18.2.6 Timer RB Secondary Register (TRBSC) .......................................................................................... 237

18.2.7 Timer RB Primary Register (TRBPR) .............................................................................................. 238

18.2.8 Timer RB/RC Pin Select Register (TRBRCSR) ............................................................................... 238

18.3 Timer Mode ........................................................................................................................................... 239

18.3.1 Timer RB I/O Control Register (TRBIOC) in Timer Mode ...................... ....................................... 239

18.3.2 Timer Write Control during Count Operation .................................................................................. 240

18.4 Programmable Waveform Generation Mode ....................... ................................................................. 242

18.4.1 Timer RB I/O Control Register (TRBIOC) in Programmable Waveform Generation Mode .......... 243

18.4.2 Operating Example ........................................................................................................................... 244

18.5 P rogrammable One-shot Generation Mode ........................................................................................... 245

18.5.1 Timer RB I/O Control Register (TRBIOC) in Programmable One-Shot Generation Mode ............ 246

18.5.2 Operating Example ........................................................................................................................... 247

18.5.3 One-Shot Tri gger Selection ...................................................................................................... ........ 248

18.6 Programmable Wait One-Shot Generation Mode ................................................................................. 249

18.6.1 Timer RB I/O Control Register (TRBIOC) in Programmable Wait One-Shot Generation Mode ... 250

18.6.2 Operating Example ........................................................................................................................... 251

18.7 Notes on Timer RB ........................................................................................................................ ........ 252

18.7.1 Timer Mode ........................................................................................................................ .............. 252

18.7.2 Programmable Waveform Generation Mode ............................................. ....................................... 252

18.7.3 Programmable One-shot Generation Mode ...................................................................................... 253

18.7.4 Programmable Wait One-shot Generation Mode ............................................................................. 253

19. Timer RC .................................................................................................................................... 254

19.1 Overview ............................................................................................................................................... 254

19.2 Registers .................................................................................................................... ............................ 256

19.2.1 Module Standby Control Register (MSTCR) ................................................................................... 257

19.2.2 Timer RC Mode Register (TRCMR) ................................................................................................ 257

19.2.3 Timer RC Control Register 1 (TRCCR1) ......................................................................................... 258

19.2.4 Timer RC Interrupt Enable Register (TRCIER) ......................................................................... ...... 258

19.2.5 Timer RC Status Register (TRCSR) ................................................................................................. 259

19.2.6 Timer RC I/O Control Register 0 (TRCIOR0) ................................................................................. 260

19.2.7 Timer RC I/O Control Register 1 (TRCIOR1) ................................................................................. 260

19.2.8 Timer RC Counter (TRC) ................................................................................................................. 261

19.2.9 Timer RC General Registers A, B, C, and D (TRCGRA, TRCGRB, TRCGRC, TRCGRD) .......... 261

19.2.10 Timer RC Control Register 2 (TRCCR2) ......................................................................................... 262

19.2.11 Timer RC Digital Filter Function Select Register (TRCDF) ............................................................ 262

19.2.12 Timer RC Output Master Enable Register (TRCOER) ............... ..................................................... 263

19.2.13 Timer RC Trigger Control Register (TRCADCR) ........................................................................... 263

19.2.14 Timer RB/RC Pin Select Register (TRBRCSR) ............................................................................... 264

19.2.15 Timer RC Pin Select Register 0 (TRCPSR0) ................................................................................ ... 265

19.2.16 Timer RC Pin Select Register 1 (TRCPSR1) ................................................................................ ... 266

19.3 Common Items for Multiple Modes .................................. ..................................... ............................... 267

19.3.1 Count Source ..................................................................................................................................... 267

19.3.2 Buffer Operation ....................................................................................................................... ........ 268

19.3.3 Digital Filter ........................... ...................................................................... ..................................... 270

19.3.4 Forced Cutoff of Pulse Output .......................................................................................................... 271

19.4 Timer Mode (Input Capture Function) .................................................................................................. 273

A - 8

19.4.1 Timer RC I/O Control Register 0 (TRCIOR0) for Input Capture Fu nction ..................................... 275

19.4.2 Timer RC I/O Control Register 1 (TRCIOR1) for Input Capture Fu nction ..................................... 276

19.4.3 Operating Example ........................................................................................................................ ... 277

19.5 Timer Mode (Output Compare Function) ............................................................................................. 278

19.5.1 Timer RC Control Register 1 (TRCCR1) for Output Compare Function ........................................ 280

19.5.2 Timer RC I/O Control Register 0 (TRCIOR0) for Output Compare Function ................................ 281

19.5.3 Timer RC I/O Control Register 1 (TRCIOR1) for Output Compare Function ................................ 282

19.5.4 Timer RC Control Register 2 (TRCCR2) for Output Compare Function ........................................ 283

19.5.5 Operating Example ........................................................................................................................... 284

19.5.6 Changing Output Pins in Registers TRCGRC and TRCGRD .......................................................... 285

19.6 PWM Mode .................................................................................................... ....................................... 287

19.6.1 Timer RC Control Register 1 (TRCCR1) in PWM Mode ................................................................ 289

19.6.2 Timer RC Control Register 2 (TRCCR2) in PWM Mode ................................................................ 290

19.6.3 Operating Example ........................................................................................................................... 291

19.7 PWM2 Mode ......................................................................................................................................... 293

19.7.1 Timer RC Control Register 1 (TRCCR1) in PWM2 Mode ......... ..................................................... 295

19.7.2 Timer RC Control Register 2 (TRCCR2) in PWM2 Mode ......... ..................................................... 296

19.7.3 Timer RC Digital Filter Function Select Register (TRCDF) in PWM2 Mode ................................. 297

19.7.4 Operating Example ........................................................................................................................... 298

19.8 Timer RC Interrupt ............................................................................................................... ................. 301

19.9 Notes on Timer RC ........................................................................................................................ ........ 302

19.9.1 TRC Register ............................................................................................................ ........................ 302

19.9.2 TRCSR Register ...................... ........................................................................................................ 302

19.9.3 TRCCR1 Register ............................................................................................................................. 302

19.9.4 Count Source Switching ..................................................................................................... .............. 302

19.9.5 Input Capture Function ....................................................................................................... .............. 303

19.9.6 TRCMR Register in PWM2 Mode ................................................................................................ ... 303

19.9.7 Count Source fOCO40M .................................................................................................................. 303

20. Timer RD .................................................................................................................................... 304

20.1 Overview ............................................................................................................................................... 304

20.2 Common Items for Multiple Modes .................................. ..................................... ............................... 306

20.2.1 Count Sources ................................................................................................................................... 306

20.2.2 Buffer Operation ....................................................................................................................... ........ 307

20.2.3 Synchronous Operation ................................................................ ..................................................... 309

20.2.4 Pulse Output Forced Cutoff ................................................................................................... ........... 310

20.3 Input Capture Function .......................................................................................................................... 312

20.3.1 Module Standby Control Register (MSTCR) ................................................................................... 314

20.3.2 Timer RD Control Expansion Register (TRDECR) ........... ................. ............................................. 314

20.3.3 Timer RD Start Register (TRDSTR) in Input Capture Function ...................................................... 315

20.3.4 Timer RD Mode Regist er (TRDMR) in Input Capture Function ...................... ............................... 315

20.3.5 Timer RD PWM Mode Register (TRDPMR) in Input Capture Function ... .................... ................. 316

20.3.6 Timer RD Function Control Register (TRDFCR) in Input Capture Function .................................. 316

20.3.7 Timer RD Digital Filter Function Select Register i (TRDDFi) (i = 0 or 1) in Input Capture Function

.................................................................................................................................. ......................... 317

20.3.8 Timer RD Control Register i (TRDCRi) (i = 0 or 1) in Input Capture Function .............................. 318

20.3.9 Timer RD I/O Control Register Ai (TRDIORAi) (i = 0 or 1) in Input Capture Function ................ 319

20.3.10 Timer RD I/O Control Register Ci (TRDIORCi) (i = 0 or 1) in Input Capture Function ................ 320

20.3.11 Timer RD Status Register i (TRDSRi) (i = 0 or 1) in Input Capture Function .......... ................... ... 321

A - 9

20.3.12 Timer RD Interrupt Enable Register i (TR D IE Ri) (i = 0 or 1) in Input Capture Function ............... 322

20.3.13 Timer RD Counter i (TRDi) (i = 0 or 1) in Input Capture Function ................................................. 322

20.3.14 Timer RD General Registers Ai, Bi, Ci, and Di (TRDGRAi, TRDGRBi, TRDGRCi, TRDGRDi)

(i = 0 or 1) in Input Capture Function ............................................................................................... 323

20.3.15 Timer RD Pin Select Register 0 (TRDPSR0) ................................................................................... 324

20.3.16 Timer RD Pin Select Register 1 (TRDPSR1) ................................................................................... 324

20.3.17 Operating Example ........................................................................................................................... 325

20.3.18 Digital Filter ........................... ...................................................................... ..................................... 326

20.4 O utput Compare Function ............. .................................... .................................................................... 327

20.4.1 Module Standby Control Register (MSTCR) ................................................................................... 329

20.4.2 Timer RD Control Expansion Register (TRDECR) ........... ................. ............................................. 329

20.4.3 Timer RD Trigger Control Register (TRDADCR) ....... .................................................................... 330

20.4.4 Timer RD Start Register (TRDSTR) in Output Compare Function ............... .................................. 331

20.4.5 Timer RD Mode Register (TRDMR) in Output Compare Function ................................................ 332

20.4.6 Timer RD PWM Mode Register (TRDPMR) in Output Compare Function .................................... 333

20.4.7 Timer RD Function Control Register (TRDFCR) in Output Compare Function ............................. 333

20.4.8 Timer RD Output Master Enable Register 1 (TRDOER1) in Output Compare Function ................ 334

20.4.9 Timer RD Output Master Enable Register 2 (TRDOER2) in Output Compare Function ................ 334

20.4.10 Timer RD Output Control Register (TRDOCR) in Output Compare Function ............................... 335

20.4.11 Timer RD Control Register i (T RDCRi) (i = 0 or 1) in Output Compare Function ......................... 336

20.4.12 Timer RD I/O Control Register Ai (TRDIORAi) (i = 0 or 1) in Output Compare Function ........... 337

20.4.13 Timer RD I/O Control Register Ci (TRDIORCi) (i = 0 or 1) in Output Compare Function ............ 338

20.4.14 Timer RD Status Register i (TRDSRi) (i = 0 or 1) in Output Compare Function ............................ 339

20.4.15 Timer RD Interrupt Enable Register i (TR DIE Ri) (i = 0 or 1) in Output Compare Function .......... 340

20.4.16 Timer RD Counter i (TRDi) (i = 0 or 1) in Output Compare Function .................................... ........ 340

20.4.17 Timer RD General Registers Ai, Bi, Ci, and Di (TRDGRAi, TRDGRBi, TRDGRCi, TRDGRDi)

(i = 0 or 1) in Output Compare Function .......................................................................................... 341

20.4.18 Timer RD Pin Select Register 0 (TRDPSR0) ................................................................................... 342

20.4.19 Timer RD Pin Select Register 1 (TRDPSR1) ................................................................................... 342

20.4.20 Operating Example ........................................................................................................................... 343

20.4.21 Changing Output Pins in Registers TRDGRCi (i = 0 or 1) and TRDGRDi ..................................... 344

20.4.22 A/D Trigger Generation ........................................ .................................................................... ........ 346

20.5 PWM Mode ................................................................................... ........................................................ 347

20.5.1 Module Standby Control Register (MSTCR) ................................................................................... 349

20.5.2 Timer RD Control Expansion Register (TRDECR) ........... ................. ............................................. 349

20.5.3 Timer RD Trigger Control Register (TRDADCR) ....... .................................................................... 350

20.5.4 Timer RD Start Register (TRDSTR) in PWM Mode ....................................................................... 351

20.5.5 Timer RD Mode Register (TRDMR) in PWM Mode ............... ........................................................ 351

20.5.6 Timer RD PWM Mode Register (TRDPMR) in PWM Mode .......................................................... 352

20.5.7 Timer RD Function Control Register (TRDFCR) in PWM Mode ................................................... 352

20.5.8 Timer RD Output Master Enable Register 1 (TRDOER1) in PWM Mode ...................................... 353

20.5.9 Timer RD Output Master Enable Register 2 (TRDOER2) in PWM Mode ...................................... 353

20.5.10 Timer RD Output Control Register (TRDOCR) in PWM Mode ...................................................... 354

20.5.11 Timer RD Control Register i (T RD CRi ) (i = 0 or 1) in PWM Mode ............................................... 354

20.5.12 Timer RD Status Register i (TRDSRi) (i = 0 or 1) in PWM Mode .................................................. 355

20.5.13 Timer RD Interrupt Enable Register i (TR D IE Ri) (i = 0 or 1) in PWM Mode ................................ 356

20.5.14 Timer RD PWM Mode Output Level Control Register i (TRDPOCRi) (i = 0 or 1) in PWM Mode

.................................................................................................................................. ......................... 356

20.5.15 Timer RD Counter i (TRDi) (i = 0 or 1) in PWM Mode .................................................................. 357

A - 10

20.5.16 Timer RD General Registers Ai, Bi, Ci, and Di (TRDGRAi, TRDGRBi, TRDGRCi, TRDGRDi)

(i = 0 or 1) in PWM Mode ................................................................................................................ 357

20.5.17 Timer RD Pin Select Register 0 (TRDPSR0) ................................................................................... 358

20.5.18 Timer RD Pin Select Register 1 (TRDPSR1) ................................................................................... 358

20.5.19 Operating Example ........................................................................................................................... 359

20.5.20 A/D Trigger Generation ........................................ .................................................................... ........ 361

20.6 Reset Synchronous PWM Mode ........................................................................................................... 362

20.6.1 Module Standby Control Register (MSTCR) ................................................................................... 364

20.6.2 Timer RD Control Expansion Register (TRDECR) ........... ................. ............................................. 364

20.6.3 Timer RD Trigger Control Register (TRDADCR) ....... .................................................................... 365

20.6.4 Timer RD Start Register (TRDSTR) in Reset Synchronous PWM Mode ................. .. .................... 366

20.6.5 Timer RD Mode Register (TRDMR) in Reset Synchronous PWM Mode .................................... ... 366

20.6.6 Timer RD Function Control Register (TRDFCR) in Reset Synchronous PWM Mode ................... 367

20.6.7 Timer RD Output Master Enable Register 1 (TRDOER1) in Reset Synchronous PWM Mode ...... 368

20.6.8 Timer RD Output Master Enable Register 2 (TRDOER2) in Reset Synchronous PWM Mode ...... 368

20.6.9 Timer RD Control Register 0 (TRDCR0) in Reset Synchronous PWM Mode ................................ 369

20.6.10 Timer RD Status Register i (TRDSRi) (i = 0 or 1) in Reset Synchronous PWM Mode .................. 370

20.6.11 Timer RD Interrupt Enable Register i (TRDIERi) (i = 0 or 1) in Reset Synchronou s PWM Mode 371

20.6.12 Timer RD Counter 0 (TRD0) in Reset Synchronous PWM Mode .............. ..................................... 371

20.6.13 Timer RD General Registers Ai, Bi, Ci, and Di (TRDGRAi, TRDGRBi, TRDGRCi, TRDGRDi)

(i = 0 or 1) in Reset Synchronous PWM Mode ................................................................................ 372

20.6.14 Timer RD Pin Select Register 0 (TRDPSR0) ................................................................................... 373

20.6.15 Timer RD Pin Select Register 1 (TRDPSR1) ................................................................................... 373

20.6.16 Operating Example ........................................................................................................................... 374

20.6.17 A/D Trigger Generation ........................................ .................................................................... ........ 375

20.7 Complementary PWM Mode .......................................................................................................... ...... 376

20.7.1 Module Standby Control Register (MSTCR) ................................................................................... 378

20.7.2 Timer RD Control Expansion Register (TRDECR) ........... ................. ............................................. 378

20.7.3 Timer RD Trigger Control Register (TRDADCR) in Complementary PWM Mode ....................... 379

20.7.4 Timer RD Start Register (TRDSTR) in Complementary PWM Mode ............................................ 380

20.7.5 Timer RD Mode Register (TRDMR) in Complementary PWM Mode ............................................ 380

20.7.6 Timer RD Function Control Register (TRDFCR) in Complementary PWM Mode ........................ 381

20.7.7 Timer RD Output Master Enable Register 1 (TRDOER1) in Complementary PWM Mode ........... 382

20.7.8 Timer RD Output Master Enable Register 2 (TRDOER2) in Complementary PWM Mode ........... 382

20.7.9 Timer RD Control Register i (TRDCRi) (i = 0 or 1) in Complementary PWM Mode .............. ...... 383

20.7.10 Timer RD Status Register i (TRDSRi) (i = 0 or 1) in Complementary PWM Mode ....................... 384

20.7.11 Timer RD Interrupt Enable Register i (TRDIERi) (i = 0 or 1) in Complementary PW M Mode ..... 385

20.7.12 Timer RD Counter 0 (TRD0) in Complementary PWM Mode ........................................................ 386

20.7.13 Timer RD Counter 1 (TRD1) in Complementary PWM Mode ........................................................ 386

20.7.14 Timer RD General Registers Ai, Bi, C1, and Di (TRDGRAi, TRDGRBi, TRDGRC1, TRDGRDi)

(i = 0 or 1) in Complementary PWM Mode ..................................................................................... 387

20.7.15 Timer RD Pin Select Register 0 (TRDPSR0) ................................................................................... 389

20.7.16 Timer RD Pin Select Register 1 (TRDPSR1) ................................................................................... 389

20.7.17 Operating Example ........................................................................................................................... 390

20.7.18 Transfer Timing from Buffer Register .............................................................................................. 392

20.7.19 A/D Trigger Generation ........................................ .................................................................... ........ 392

20.8 PWM3 Mode ......................................................................................................................................... 393

20.8.1 Module Standby Control Register (MSTCR) ................................................................................... 395

20.8.2 Timer RD Control Expansion Register (TRDECR) ........... ................. ............................................. 395

A - 11

20.8.3 Timer RD Trigger Control Register (TRDADCR) ....... .................................................................... 396

20.8.4 Timer RD Start Register (TRDSTR) in PWM3 Mode ............. ........................................................ 397

20.8.5 Timer RD Mode Register (TRDMR) in PWM3 Mode ..................................................................... 397

20.8.6 Timer RD Function Control Register (TRDFCR) in PWM3 Mode ................................................. 398

20.8.7 Timer RD Output Master Enable Register 1 (TRDOER1) in PWM3 Mode .................................... 399

20.8.8 Timer RD Output Master Enable Register 2 (TRDOER2) in PWM3 Mode .................................... 399

20.8.9 Timer RD Output Control Register (TRDOCR) in PWM3 Mode .................................................... 400

20.8.10 Timer RD Control Register 0 (TRDCR0) in PWM3 Mode .............................................................. 401

20.8.11 Timer RD Status Register i (TRDSRi) (i = 0 or 1) in PWM3 Mode ................................................ 402

20.8.12 Timer RD Interrupt Enable Register i (TR D IE Ri) (i = 0 or 1) in PWM3 Mode .............................. 403

20.8.13 Timer RD Counter 0 (TRD0) in PWM3 Mode ................................................................................. 403

20.8.14 Timer RD General Registers Ai, Bi, Ci, and Di (TRDGRAi, TRDGRBi, TRDGRCi, TRDGRDi)

(i = 0 or 1) in PWM3 Mode .............................................................................................................. 404

20.8.15 Timer RD Pin Select Register 0 (TRDPSR0) ................................................................................... 406

20.8.16 Timer RD Pin Select Register 1 (TRDPSR1) ................................................................................... 406

20.8.17 Operating Example ........................................................................................................................... 407

20.8.18 A/D Trigger Generation ........................................ .................................................................... ........ 408

20.9 Timer RD Interrupt ..................................................................................................................... ........... 409

20.10 Notes on Timer RD ................................................................................................................. .............. 410

20.10.1 TRDSTR Register ....................................................................................................................... ...... 410

20.10.2 TRDi Register (i = 0 or 1) ................................................................................................................. 410

20.10.3 TRDSRi Register (i = 0 or 1) ............................................................................................................ 410

20.10.4 TRDCRi Register (i = 0 or 1) ..................................................................................................... ...... 410

20.10.5 Count Source Switch ........................................................................................................................ 411

20.10.6 Input Capture Function ....................................................................................................... .............. 411

20.10.7 Reset Synchronous PWM Mode ............................................................................................... ........ 411

20.10.8 Complementary PWM Mode ............................................................................................................ 412

20.10.9 Count Source fOCO40M ............................................................................................................ ...... 415

21. Timer RE ..................................................................................................................................... 416

21.1 Overview ............................................................................................................................................... 416

21.2 Real-Time Clock Mode ......................................................................................................................... 417

21.2.1 Timer RE Second Data Register (TRE SEC) in Real-Time Clock Mode ................... ...................... 419

21.2.2 Timer RE Minute Data Register (TREMIN) in Real-Time Clock Mode ......................................... 419

21.2.3 Timer RE Hour Data Register (TREHR) in Real-Time Clock Mode ............................................... 420

21.2.4 Timer RE Day of Week Data Register (TREWK) in Real-Time Clock Mode ................................ 420

21.2.5 Timer RE Control Register 1 (TRECR1) in Real-Time Clock Mode .............................................. 421

21.2.6 Timer RE Control Register 2 (TRECR2) in Real-Time Clock Mode .............................................. 422

21.2.7 Timer RE Count Source Select Register (TRECSR) in Real-Time Clock Mode ............................. 423

21.2.8 Timer Pin Select Register (TIMSR) .............................................................................................. ... 423

21.2.9 Operating Example ........................................................................................................................... 424

21.3 O utput Compare Mode ..................................... ...................................................... ................. .............. 425

21.3.1 Timer RE Counter Data Register (TRESEC) in Output Compare Mode .......... ... ............................ 427

21.3.2 Timer RE Compare Data Register (TREMIN) in Output Compare Mode ....................................... 427

21.3.3 Timer RE Control Register 1 (TRECR1) in Output Compare Mode ............................................... 428

21.3.4 Timer RE Control Register 2 (TRECR2) in Output Compare Mode ............................................... 428

21.3.5 Timer RE Count Source Select Register (TRECSR) in Output Compare Mode .............................. 429

21.3.6 Timer Pin Select Register (TIMSR) .............................................................................................. ... 429

21.3.7 Operating Example ........................................................................................................................... 430

A - 12

21.4 Notes on Timer RE .................................................................................................................. .............. 431

21.4.1 Starting and Stopping Count .................................................................................................. ........... 431

21.4.2 Register Setting ................................................................................................................................. 431

21.4.3 Time Reading Procedure of Real-Time Clock Mode ................................................. ...................... 433

22. Serial Interface (UARTi (i = 0 or 1)) ............................................................................................ 434

22.1 Overview ............................................................................................................................................... 434

22.2 Registers .................................................................................................................... ............................ 436

22.2.1 UARTi Transmit/Receive Mode Register (UiM R) (i = 0 or 1) ........................................................ 436

22.2.2 UARTi Bit Rate Register (UiBRG) (i = 0 or 1) ................................................................................ 436

22.2.3 UARTi Transmit Buffer Register (UiTB) (i = 0 or 1) ...................................................................... 437

22.2.4 UARTi Transmit/Receive Control Register 0 (UiC0) (i = 0 or 1) .................................................... 438

22.2.5 UARTi Transmit/Receive Control Register 1 (UiC1) (i = 0 or 1) .................................................... 438

22.2.6 UARTi Receive Buffer Register (UiRB) (i = 0 or 1) ....................................................................... 439

22.2.7 UART0 Pin Select Register (U0SR) ................................................................................................. 440

22.2.8 UART1 Pin Select Register (U1SR) ................................................................................................. 440

22.3 Clock Synchronous Serial I/O Mode ............................................................................................... ...... 441

22.3.1 Measure for Dealing with Communication Errors ........................................................................... 445

22.3.2 Polarity Select Function .................................................................................................................... 446

22.3.3 LSB First/MSB First Select Function ............................................................................................... 446

22.3.4 Continuous Receive Mode ................................................................................................................ 447

22.4 Clock Asynchronous Serial I/O (UART) Mode ......................... ..................................... ...................... 448

22.4.1 Bit Rate .............. ................................................................................................... ............................ 453

22.4.2 Measure for Dealing with Communication Errors ........................................................................... 454

22.5 Notes on Serial Interface (UARTi (i = 0 or 1)) ..................................................................................... 455

23. Serial Interface (UART2) ............................................................................................................ 456

23.1 Overview ............................................................................................................................................... 456

23.2 Registers .................................................................................................................... ............................ 458

23.2.1 UART2 Transmit/Receive Mode Register (U2MR) ......................................................................... 458

23.2.2 UART2 Bit Rate Register (U2BRG) ................................................................................................ 458

23.2.3 UART2 Transmit Buffer Register (U2TB) ....................................................................................... 459

23.2.4 UART2 Transmit/Receive Control Register 0 (U2C0) .................................................................... 460

23.2.5 UART2 Transmit/Receive Control Register 1 (U2C1) .................................................................... 461

23.2.6 UART2 Receive Buffer Register (U2RB) ........................................................................................ 462

23.2.7 UART2 Digital Filter Function Select Register (URXDF) .............................................................. 463

23.2.8 UART2 Special Mode Register 5 (U2SMR5) ..................................... ............................................. 463

23.2.9 UART2 Special Mode Register 4 (U2SMR4) ..................................... ............................................. 464

23.2.10 UART2 Special Mode Register 3 (U2SMR3) .................... ................................................... ........... 464

23.2.11 UART2 Special Mode Register 2 (U2SMR2) .................... ................................................... ........... 465

23.2.12 UART2 Special Mode Register (U2SMR) ................... ................................................... ................. 465

23.2.13 UART2 Pin Select Register 0 (U2SR0) ............................................................................................ 466

23.2.14 UART2 Pin Select Register 1 (U2SR1) ............................................................................................ 466

23.3 Clock Synchronous Serial I/O Mode ............................................................................................... ...... 467

23.3.1 Measure for Dealing with Communication Errors ........................................................................... 471

23.3.2 CLK Polarity Select Function ........................................................................................................ ... 471

23.3.3 LSB First/MSB First Select Function ............................................................................................... 472

23.3.4 Continuous Receive Mode ................................................................................................................ 472

23.3.5 Serial Data Logic Switching Function .............................................................................................. 473

A - 13

23.3.6 CTS/RTS Function ........................................................................................................................... 473

23.4 Clock Asynchronous Serial I/O (UART) Mode ......................... ..................................... ...................... 474

23.4.1 Bit Rate .............. ................................................................................................... ............................ 478

23.4.2 Measure for Dealing with Communication Errors ........................................................................... 479

23.4.3 LSB First/MSB First Select Function ............................................................................................... 479

23.4.4 Serial Data Logic Switching Function .............................................................................................. 480

23.4.5 TXD and RXD I/O Polarity Inverse Function .................................................................................. 480

23.4.6 CTS/RTS Function ........................................................................................................................... 481

23.4.7 RXD2 Digital Filter Select Function ..................................... ..................................... .............. ........ 481

23.5 Special Mode 1 (I2C Mode) .......................................................................................................... ........ 482

23.5.1 Detection of Start and Stop Conditions ............................................................................................ 488

23.5.2 Output of Start and Stop Conditions ................................................................................................. 489

23.5.3 Transfer Clock ....................................................................................................................... ........... 490

23.5.4 SDA Output .............................................................................................................................. ........ 490

23.5.5 SDA Input ......................................................................................................................................... 490

23.5.6 ACK and NACK .................................................................................................................... ........... 490

23.5.7 Initialization of Transmission/Reception .......................................................................................... 491

23.6 Multiprocessor Communication Function ............................................................................................. 492

23.6.1 Multiprocessor Transmission ............................................................................................................ 495

23.6.2 Multiprocessor Reception ................................................................................................................. 496

23.6.3 RXD2 Digital Filter Select Function ..................................... ..................................... .............. ........ 498

23.7 Notes on Serial Interface (UART2) ................................................................................................. ...... 499

23.7.1 Clock Synchronous Serial I/O Mode ................................................................................................ 499

23.7.2 Special Mode 1 (I2C Mode) .............................................................................................................. 500

24. Clock Synchronous Serial Interface .... ... ... ... ............................................................................... 501

24.1 Mode Selection ...................................................................................................................................... 501

25. Synchronous Serial Communication Unit (SSU) ........................................................................ 502

25.1 Overview ............................................................................................................................................... 502

25.2 Registers .................................................................................................................... ............................ 504

25.2.1 Module Standby Control Register (MSTCR) ................................................................................... 504

25.2.2 SSU/IIC Pin Select Register (SSUIICSR) ........................................................................................ 504

25.2.3 SS Bit Counter Register (SSBR) ...................................................................................................... 505

25.2.4 SS Transmit Data Register (SSTDR) ................................................................................................ 505

25.2.5 SS Receive Data Register (SSRDR) ................................................................................................. 506

25.2.6 SS Control Register H (SSCRH) ............... .................................................................................... ... 506

25.2.7 SS Control Register L (SSCRL) ....................................................................................................... 507

25.2.8 SS Mode Register (SSMR) ............................................................................................................... 508

25.2.9 SS Enable Register (SSER) .............................................................................................................. 509

25.2.10 SS Status Register (SSSR) .................................................................................................. .............. 510

25.2.11 SS Mode Register 2 (SSMR2) .......................................................................................................... 511

25.3 Common Items for Multiple Modes .................................. ..................................... ............................... 512

25.3.1 Transfer Clock ....................................................................................................................... ........... 512

25.3.2 SS Shift Register (SSTRSR) ............................................................................................... .............. 514

25.3.3 Interrupt Requests ............... ...................................................... ........................................................ 515

25.3.4 Communication Modes and Pin Functions ....................................................................................... 516

25.4 Clock Synchronous Communication Mode .......................................................................................... 517

25.4.1 In itialization in Clock Synchronous Communication Mode ............................................................ 517

A - 14

25.4.2 Data Transmission ............................................................................................................................ 518

25.4.3 Data Reception .......................................................................................................................... ........ 520

25.5 Operation in 4-Wire Bus Communication Mode .................................................................................. 524

25.5.1 Initialization in 4-Wire Bus Communication Mode ......................................................................... 525

25.5.2 Data Transmission ............................................................................................................................ 526

25.5.3 Data Reception .......................................................................................................................... ........ 528

25.5.4 SCS Pin Control and Arbitration ...................................................................................................... 530

25.6 Notes on Synchronous Serial Communication Unit .............................................................................. 531

26. I2C bus Interface ......................................................................................................................... 532

26.1 Overview ............................................................................................................................................... 532

26.2 Registers .................................................................................................................... ............................ 535

26.2.1 Module Standby Control Register (MSTCR) ................................................................................... 535

26.2.2 SSU/IIC Pin Select Register (SSUIICSR) ........................................................................................ 535

26.2.3 I/O Function Pin Select Register (PINSR) .................................................................................... ... 536

26.2.4 IIC bus Transmit Data Register (ICDRT) ......................................................................................... 537

26.2.5 IIC bus Receive Data Register (ICDRR) .......................................................................................... 537

26.2.6 IIC bus Control Register 1 (ICCR1) ................................................................................................. 538

26.2.7 IIC bus Control Register 2 (ICCR2) ................................................................................................. 539

26.2.8 IIC bus Mode Register (ICMR) .................................................................................................. ...... 540

26.2.9 IIC bus Interrupt Enable Register (ICIER) ....................................................................................... 541

26.2.10 IIC bus Status Register (ICSR) ......................................................................................................... 542

26.2.11 Slave Address Register (SAR) .......................................................................................................... 543

26.2.12 IIC bus Shift Register (ICDRS) ..................................................................................................... ... 543

26.3 Common Items for Multiple Modes .................................. ..................................... ............................... 544

26.3.1 Transfer Clock ....................................................................................................................... ........... 544

26.3.2 SDA Pin Digital Delay Selection ...................................................................................................... 546

26.3.3 Interrupt Requests ............... ...................................................... ........................................................ 547

26.4 I2C bus Interface Mode ......................................................................................................................... 548

26.4.1 I2C bus Format ................................................................................................................................. 548

26.4.2 Master Transmit Operation ............................................................................................................... 549

26.4.3 Master Receive Operation ................................................................................................................ 551

26.4.4 Slave Transmit Operation ................................................................................................................. 554

26.4.5 Slave Receive Operation .................................................................................................. ................. 557

26.5 Clock Synchronous Serial Mode ................. .................... ................................................................ ...... 559

26.5.1 Clock Synchronous Serial Format .................................................................................................... 559

26.5.2 Transmit Operation ................................................................................................................... ........ 560

26.5.3 Receive Operation ............................................................................................................................. 561

26.6 Examples of Register Setting ..................................................................................................... ........... 562

26.7 Noise Canceller ..................................................................................................................................... 566

26.8 Bit Synchronization Circuit ........................................................ .................... ....................................... 567

26.9 Notes on I2C bus Interface .................................................................................................................... 568

27. Hardware LIN ............ ... ... ... .... ... ................... ... .... ................... ... .... ... ................... ... .... ................. 569

27.1 Overview ............................................................................................................................................... 569

27.2 Input/Output Pins ................. ...................................................... ........................................................... 570

27.3 Registers .................................................................................................................... ............................ 571

27.3.1 LIN Control Register 2 (LINCR2) .................................................................................................... 571

27.3.2 LIN Control Register (LINCR) .............................................................................................. ........... 572

A - 15

27.3.3 LIN Status Register (LINST) ...................................................................................................... ...... 572

27.4 Function Description .......................................................................................................................... ... 573

27.4.1 Master Mode ..................................................................................................................................... 573

27.4.2 Slave Mode ...................................................................................................................... ................. 576

27.4.3 Bus Collision Detection Function ..................................................................................................... 580

27.4.4 Hardware LIN End Processing ......................................................................................................... 581

27.5 Interrupt Requests ....................... ...................................................... ..................................................... 582

27.6 Notes on Hardware LIN ....................................................................................................... ................. 583

28. A/D Converter ............................................................................................................................. 584

28.1 Overview ............................................................................................................................................... 584

28.2 Registers .................................................................................................................... ............................ 586

28.2.1 On-Chip Reference Voltage Control Register (OCVREFCR) ......................................................... 586

28.2.2 A/D Register i (ADi) (i = 0 to 7) ........................................................................................ .............. 587

28.2.3 A/D Mode Register (ADMOD) ....................................... ................................................................. 588

28.2.4 A/D Input Select Register (ADINSEL) .................................................. ................................... ....... 589

28.2.5 A/D Control Register 0 (ADCON0) ................................................................................................. 590

28.2.6 A/D Control Register 1 (ADCON1) ................................................................................................. 591

28.3 Common Items for Multiple Modes .................................. ..................................... ............................... 592

28.3.1 Input/Output Pins ........................................................ ...................................................................... 592

28.3.2 A/D Conversion Cycles ....................................................................... ............................................. 592

28.3.3 A/D Conversion Start Condition ................ ................................................................................. ...... 594

28.3.4 A/D Conversion Result ........................ ............................................................................................. 596

28.3.5 Low Current Consumption Function .......................................................................................... ...... 596

28.3.6 Extended Analog Input Pins ............................................................................................................. 596

28.3.7 A/D Open-Circuit Detection Assist Function ................................................................................... 596

28.4 One-Shot Mode ..................................................................................................................................... 598

28.5 Repeat Mode 0 ....................................................................................................................................... 599

28.6 Repeat Mode 1 ....................................................................................................................................... 600

28.7 Single Sweep Mode .................... ................................................................................................... ........ 602

28.8 Repeat Sweep Mode .............................................................................................................................. 604

28.9 Output Impedance of Sensor under A/D Conversion ............................................................................ 606

28.10 Notes on A/D Converter ........................................................................................................................ 607

29. D/A Converter ............................................................................................................................. 608

29.1 Overview ............................................................................................................................................... 608

29.2 Registers .................................................................................................................... ............................ 610

29.2.1 D/Ai Register (DAi) (i = 0 or 1) ..................... .................................................................... .............. 610

29.2.2 D/A Control Register (DACON) ...................................................................................................... 610

30. Comparator B ............................................................................................................................. 611

30.1 Overview ............................................................................................................................................... 611

30.2 Registers .................................................................................................................... ............................ 613

30.2.1 Comparator B Control Register 0 (INTCMP) .................................................................................. 613

30.2.2 External Input Enable Register 0 (INTEN) . ..................................................................................... 613

30.2.3 INT Input Filter Select Register 0 (INTF) ........................................................................................ 614

30.3 Functional Description .................................................................................................................... ...... 615

30.3.1 Comparator Bi Digital Filter (i = 1 or 3) ........... .................................................................... ........... 616

30.4 Comparator B1 and Comparator B3 Interrupts ..................................................................................... 617

A - 16

31. Flash Memory ............................................................................................................................. 618

31.1 Overview ............................................................................................................................................... 618

31.2 Memory Map ................................................................ ................................................ ......................... 619

31.3 Functions to Prevent Flash Memory from being Rewritten .................................................................. 620

31.3.1 ID Code Check Function .................................................................................................................. 620

31.3.2 ROM Code Protect Function ......................................................................................................... ... 621

31.3.3 Option Function Select Register (OFS) ............................................................................................ 621

31.4 CPU Rewrite Mode .......................... ..................................................... .................................. .............. 622

31.4.1 Flash Memory Status Register (FST) ............................................................................................... 623

31.4.2 Flash Memory Cont rol Register 0 (FMR0) .......................................................... ............................ 625

31.4.3 Flash Memory Cont rol Register 1 (FMR1) .......................................................... ............................ 627

31.4.4 Flash Memory Cont rol Register 2 (FMR2) .......................................................... ............................ 629

31.4.5 EW0 Mode ........................................................................................................................................ 631

31.4.6 EW1 Mode ........................................................................................................................................ 631

31.4.7 Suspend Operation ............................................................................................................................ 632

31.4.8 How to Set and Exit Each Mode ....................................................................................................... 633

31.4.9 BGO (BackGround Operation) Function .......................................................................................... 634

31.4.10 Data Protect Function ......................................................................................................... .............. 635

31.4.11 Software Commands ...................................................................................................................... ... 636

31.4.12 Full Status Check .............................................................................................................................. 646

31.5 Standard Serial I/O Mode ................................................................................................................... ... 648

31.5.1 ID Code Check Function .................................................................................................................. 648

31.6 Parallel I/O Mode ............................... ...................................................... .................................. ........... 651

31.6.1 ROM Code Protect Function ......................................................................................................... ... 651

31.7 Notes on Flash Memory ........................................................................................................................ 652

31.7.1 CPU Rewrite Mode .............................. ...................................................... ................................. ...... 652

32. Reducing Power Consumption ................................................................................................... 656

32.1 Overview ............................................................................................................................................... 656

32.2 Key Points and Processing Methods for Reducing Power Consumption ............................................. 656

32.2.1 Voltage Detection Circuit ................................................................................................... .............. 656

32.2.2 Ports ...................................................................................................................... ............................ 656

32.2.3 Clocks ............................................................................................................................................... 656

32.2.4 Wait Mode, Stop Mode ............................................................................................... ...................... 656

32.2.5 Stopping Peripheral Function Clocks ............. ... ............................................................................... 656

32.2.6 Timers ............................................................................................................................................... 656

32.2.7 A/D Converter ............................................................................................................... .................... 656

32.2.8 Clock Synchronous Serial Interface .............................................................................................. ... 656

32.2.9 Reducing Internal Power Consumption ............................................................................................ 657

32.2.10 Stopping Flash Memory ................................................ .................................................. .................. 658

32.2.11 Low-Current-Consumption Read Mode ........................................................................................... 659

33. Electrical Characteristics ............................................................................................................ 661

34. Usage Notes ............................................................................................................................... 688

34.1 Notes on Clock Generation Circuit ....................................................................................................... 688

34.1.1 Stop Mode ..................................................................................................................... .................... 688

34.1.2 Wait Mode ..................................... .................................................................................. ................. 688

34.1.3 Oscillation Stop Detection Function ................................................................................................. 689

A - 17

34.1.4 Oscillation Circuit Constants .............................................................................................. .............. 689

34.2 Notes on Interrupts ................................................................................................................................ 690

34.2.1 Reading Add ress 00000 h .................................................................................................................. 690

34.2.2 SP Setting ............................................................................................................................ .............. 690

34.2.3 External Interrupt and Key Input Interrupt ....................................................................................... 690

34.2.4 Changing Interrupt Sources ........................................................................................................ ...... 691

34.2.5 Rewriting Interrupt Control Register ..................................................................................... ........... 692

34.3 Notes on ID Code Areas .................................................................................................................. ...... 693

34.3.1 Setting Example of ID Code Areas ................. ... ..................................... .................................. ........ 693

34.4 Notes on Option Function Select Area ............................................................................................... ... 693

34.4.1 Setting Example of Option Function Select Area ............................................................................. 693

34.5 Notes on DTC .................................................................................................................... .................... 694

34.5.1 DTC activation source ...................................................................................................................... 694

34.5.2 DTCENi (i = 0 to 6) Registers .......................................................................................................... 694

34.5.3 Peripheral Modules ................................................................................................................ ........... 694

34.5.4 Interrupt Request ................................................................. .............................................................. 694

34.6 Notes on Timer RA ............................................................................................................................... 695

34.7 Notes on Timer RB ........................................................................................................................ ........ 696

34.7.1 Timer Mode ........................................................................................................................ .............. 696

34.7.2 Programmable Waveform Generation Mode ............................................. ....................................... 696

34.7.3 Programmable One-shot Generation Mode ...................................................................................... 697

34.7.4 Programmable Wait One-shot Generation Mode ............................................................................. 697

34.8 Notes on Timer RC ........................................................................................................................ ........ 698

34.8.1 TRC Register ............................................................................................................ ........................ 698

34.8.2 TRCSR Register ...................... ........................................................................................................ 698

34.8.3 TRCCR1 Register ............................................................................................................................. 698

34.8.4 Count Source Switching ..................................................................................................... .............. 698

34.8.5 Input Capture Function ....................................................................................................... .............. 699

34.8.6 TRCMR Register in PWM2 Mode ................................................................................................ ... 699

34.8.7 Count Source fOCO40M .................................................................................................................. 699

34.9 Notes on Timer RD ............................................................................................................................... 700

34.9.1 TRDSTR Register .................................................................................................................. ........... 700

34.9.2 TRDi Register (i = 0 or 1) .............................................................................................................. ... 700

34.9.3 TRDSRi Register (i = 0 or 1) ............................................................................................................ 700

34.9.4 TRDCRi Register (i = 0 or 1) ................................................................................................... ........ 700

34.9.5 Count Source Switch ........................................................................................................................ 701

34.9.6 Input Capture Function ....................................................................................................... .............. 701

34.9.7 Reset Synchronou s PWM Mode ....................................................................................................... 701

34.9.8 Complementary PWM Mode ............................................................................................................ 702

34.9.9 Count Source fOCO40M .................................................................................................................. 705

34.10 Notes on Timer RE ................................................................................................................................ 706

34.10.1 Starting and Stopping Count .................................................................................................. ........... 706

34.10.2 Register Setting ................................................................................................................................. 706

34.10.3 Time Reading Procedure of Real-Time Clock Mode ............................. .......................................... 708

34.11 Notes on Serial Interface (UARTi (i = 0 or 1)) ..................................................................................... 709

34.12 Notes on Serial Interface (UART2) ....................................................................................................... 710

34.12.1 Cloc k Synchronous Serial I/O Mode ................................................................................................ 710

34.12.2 Special Mode 1 (I2C Mode) .............................................................................................................. 711

34.13 Notes on Synchronous Serial Communication Unit .............................................................................. 711

A - 18

34.14 Notes on I2C bus Interface .................................................................................................................... 711

34.15 Notes on Hardware LIN ........................................................................................................................ 711

34.16 Notes on A/D Converter ........................................................................................................................ 711

34.17 Notes on Flash Memory ....................................................................................................... ................. 712

34.17.1 CPU Rewrite Mode ............. ...................................................... .................................................. ...... 712

34.18 Notes on Noise ............................................................................................................. ......................... 716

34.18.1 Inserting a Bypass Capacitor between VCC and VSS Pins as a Countermeasure against Noise and

Latch-up ................................................................................................................................. ........... 716

34.18.2 Countermeasures against Noise Error of Port Control Registers .................................................. ... 716

35. Notes on On-Chip Debugger ...................................................................................................... 717

36. Notes on Emulator Debugger ..................................................................................................... 718

Appendix 1. Package Dimensions ........................................................................................................ 719

Appendix 2. Connection Examples between Serial Writer and On-Chip Debugging Emulator ............ 720

Appendix 3. Example of Oscillation Evaluation Circuit ......................................................................... 721

Index ..................................................................................................................................................... 722

B - 1

Note:

1. The blank regions are reserved. Do not access locations in t hese

regions.

Address Register Symbol Page

0000h

0001h

0002h

0003h

0004h Processor Mode Register 0 PM0 29

0005h Processor Mode Register 1 PM1 187

0006h System Clock Control Regist er 0 CM0 117

0007h System Clock Control Regist er 1 CM1 118

0008h Module Standby Co ntr o l Re gi ste r MSTCR 257, 314,

329, 349,

364, 378,

395, 504,

535

0009h System Clock Control Regist er 3 CM3 119

000Ah Protect Register PRCR 148

000Bh Reset Source Determination Register RSTFR 29

000Ch Oscillation Stop Detection Register OCD 121

000Dh Watchdog Timer Reset Register WDTR 187

000Eh Watchdo g Timer Start Register WDTS 187

000Fh Watchdog Timer Control Register WDTC 188

0010h

0011h

0012h

0013h

0014h

0015h High-Speed On-C hip Oscilla tor Con trol Registe r 7 FRA7 121

0016h

0017h

0018h

0019h

001Ah

001Bh

001Ch Count Source Protection Mode Register CSPR 188

001Dh

001Eh

001Fh

0020h

0021h

0022h

0023h High-Speed On-C hip Oscilla tor Con trol Registe r 0 FRA0 122

0024h High-Speed On-C hip Oscilla tor Con trol Registe r 1 FRA1 122

0025h High-Speed On-C hip Oscilla tor Con trol Registe r 2 FRA2 123

0026h On-Chip Reference Volta ge Control Register OCVREFCR 586

0027h

0028h Clock Prescaler Reset Flag CPSRF 123

0029h High-Speed On-C hip Oscilla tor Con trol Registe r 4 FRA4 124

002Ah High-Speed On- Chip Oscilla tor C ontr ol Registe r 5 FRA5 124

002Bh High-Speed On- Chip Oscilla tor C ontr ol Registe r 6 FRA6 124

002Ch

002Dh

002Eh

002Fh High-Speed On-Chip Oscill ator Contr ol Regi ster 3 FRA3 124

0030h Voltage Monitor Circuit Co ntrol Register CMPA 42

0031h Voltage Monitor Circuit Edge Select Register VCAC 43

0032h

0033h Voltage Detect Register 1 VCA1 43

0034h Voltage Detect Register 2 VCA2 44, 125

0035h

0036h Voltage Detection 1 Level Select Register VD1LS 45

0037h

0038h Voltage Monitor 0 Circuit Control Register VW0C 46

0039h Voltage Monitor 1 Circuit Control Register VW1C 47

003Ah Voltage Monitor 2 Circuit Control Register VW2C 48

003Bh

003Ch

003Dh

003Eh

003Fh

Address Register Symbol Page

0040h

0041h Flash Memory Ready Interrupt Contro l

0042h

0043h

0044h

0045h

0046h INT4 Interrupt Control Register INT4IC 156

0047h Timer RC Interrupt Control Register TRCIC 155

0048h Timer RD0 Interrupt Control Register TRD0IC 155

0049h Timer RD1 Interrupt Control Register TRD1IC 155

004Ah Time r RE Interrupt Control Register TREIC 154

004Bh UART2 Transmit Interru pt Co ntrol Register S2TIC 154

004Ch UART2 Receive Interrupt Control Register S2RIC 154

004Dh Key Input Interrupt Control Register KUPIC 154

004Eh A/D Conversion Interrupt Control Register ADIC 154

004Fh SSU Interrupt Control Register / IIC bus

Interrupt Control Register SSUIC/IICIC 155

0050h

0051h UART0 Transmit Interrupt Co ntrol Register S0TIC 154

0052h UART0 Receive Interrupt Control Register S0RIC 154

0053h UART1 Transmit Interrupt Co ntrol Register S1TIC 154

0054h UART1 Receive Interrupt Control Register S1RIC 154

0055h INT2 Interrupt Control Register INT2IC 156

0056h Timer RA Interrupt Control Register TRAIC 154

0057h

0058h Timer RB Interrupt Control Register TRBIC 154

0059h INT1 Interrupt Control Register INT1IC 156

005Ah INT3 Interrupt Control Register INT3IC 156

005Bh

005Ch

005Dh INT0 Interrupt Control Register INT0IC 156

005Eh UART2 Bus Collision Detection Interrupt

Control Register U2BCNIC 154

005Fh

0060h

0061h

0062h

0063h

0064h

0065h

0066h

0067h

0068h

0069h

006Ah

006Bh

006Ch

006Dh

006Eh

006Fh

0070h

0071h

0072h Voltage Monitor 1 Interrupt Control Register VCMP1IC 154

0073h Voltage Monitor 2 Interrupt Control Register VCMP2IC 154

0074h

0075h

0076h

0077h

0078h

0079h

007Ah

007Bh

007Ch

007Dh

007Eh

007Fh

SFR Page Reference

B - 2

Note:

1. The blank regions are reserved. Do not access locations in t hese

regions.

Address Register Symbol Page

0080h DTC Activat ion Control Register DTCTL 199

0081h

0082h

0083h

0084h

0085h

0086h

0087h

0088h DTC Activation Enable Register 0 DTCEN0 198

0089h DTC Activation Enable Register 1 DTCEN1 198

008Ah DTC Activation Enable Register 2 DTCEN2 198

008Bh DTC Activation Enable Register 3 DTCEN3 198

008Ch DTC Activation Enab le Register 4 DTCEN4 198

008Dh DTC Activation Enab le Register 5 DTCEN5 198

008Eh DTC Activation Enable Register 6 DTCEN6 198

008Fh

0090h

0091h

0092h

0093h

0094h

0095h

0096h

0097h

0098h

0099h

009Ah

009Bh

009Ch

009Dh

009Eh

009Fh

00A0h UART0 Transmit/Receive Mode Register U0MR 436

00A1h UART0 Bit Rate Register U0BRG 436

00A2h UART0 Transmit Buffer Register U0TB 437

00A3h

00A4h UART0 Transmit/Receive Control Register 0 U0C0 438

00A5h UART0 Transmit/Receive Control Register 1 U0C1 438

00A6h UART0 Receive Buffer Register U0RB 439

00A7h

00A8h UART2 Transmit/Receive Mode Register U2MR 458

00A9h UART2 Bit Rate Register U2BRG 458

00AAh UART2 Transmit Buffer Register U2TB 459

00ABh

00ACh UART2 Transmit/Receive Control Register 0 U2C0 460

00ADh UART2 Transmit/Receive Control Register 1 U2C1 461

00AEh UART2 Receive Buffer Registe r U2RB 462

00AFh

00B0h UART2 Dig ital Filter Function Select Register URXDF 463

00B1h

00B2h

00B3h

00B4h

00B5h

00B6h

00B7h

00B8h

00B9h

00BAh

00BBh UART2 Special Mode Register 5 U2SMR5 463

00BCh UART2 Special Mode Register 4 U2SMR4 464

00BDh UART2 Special Mode Register 3 U2SMR3 464

00BEh UART2 Special Mode Register 2 U2SMR2 465

00BFh UART2 Special Mode Register U2SMR 465

Address Register Symbol Page

00C0h A/D Regist e r 0 AD0 587

00C1h

00C2h A/D Regist e r 1 AD1 587

00C3h

00C4h A/D Regist e r 2 AD2 587

00C5h

00C6h A/D Regist e r 3 AD3 587

00C7h

00C8h A/D Regist e r 4 AD4 587

00C9h

00CAh A/D Register 5 AD5 587

00CBh

00CCh A/ D Register 6 AD6 587

00CDh

00CEh A/D Register 7 AD7 587

00CFh

00D0h

00D1h

00D2h

00D3h

00D4h A/D Mode Register ADMOD 588

00D5h A/D Input Select Register ADINSEL 589

00D6h A/D Cont ro l R egi s t e r 0 ADCON0 590

00D7h A/D Cont ro l R egi s t e r 1 ADCON1 591

00D8h D/A0 Register DA0 610

00D9h D/A1 Register DA1 610

00DAh

00DBh

00DCh D/A Co ntrol Register DACON 610

00DDh

00DEh

00DFh

00E0h Port P0 Register P0 74

00E1h Port P1 Register P1 74

00E2h Port P0 Direction Register PD0 73

00E3h Port P1 Direction Register PD1 73

00E4h Port P2 Register P2 74

00E5h Port P3 Register P3 74

00E6h Port P2 Direction Register PD2 73

00E7h Port P3 Direction Register PD3 73

00E8h Port P4 Register P4 74

00E9h

00EAh Port P4 Direction Register PD4 73

00EBh

00ECh Port P6 Register P6 74

00EDh

00EEh Port P6 Direction Register PD6 73

00EFh

00F0h

00F1h

00F2h

00F3h

00F4h

00F5h

00F6h

00F7h

00F8h

00F9h

00FAh

00FBh

00FCh

00FDh

00FEh

00FFh

B - 3

Note:

1. The blank regions are reserved. Do not access locations in t hese

regions.

Address Register Symbol Page

0100h T imer RA Control Register TRACR 218

0101h Timer RA I/O Control Register TRAIOC 218, 221, 224,

226, 228, 231

0102h Timer RA Mode Register TRAMR 219

0103h Timer RA Prescaler Register TRAPRE 219

0104h Timer RA Register TRA 22 0

0105h LIN Control Register 2 LINCR2 571

0106h LIN Control Register LINCR 572

0107h LIN Status Register LINST 572

0108h T imer RB Control Register TRBCR 235

0109h Timer RB One-Shot Control Register TRBOCR 235

010Ah Timer RB I/O Control Register TRBIOC 236, 239, 243,

246, 250

010Bh Timer RB Mode Register TRBMR 236

010Ch Timer RB Prescaler Re gister TRBPRE 237

010Dh Timer RB Secondary Register TRBSC 237

010Eh Timer RB Primary Register TRBPR 238

010Fh

0110h

0111h

0112h

0113h

0114h

0115h

0116h

0117h

0118h Timer RE Second Data Register / Counter

Data Register TRESEC 419, 427

0119h Timer RE Minute Data Register / Compare

Data Register TREMIN 419, 427

011Ah Timer RE Hour Data Register TREHR 420

011Bh Timer RE Day of Week Data Register TREWK 420

011Ch Timer RE Control Register 1 TRECR1 421, 428

011Dh Timer RE Control Register 2 TRECR2 422, 428

011Eh Timer RE Count Source Select Register TRECSR 423, 429

011Fh

0120h Timer RC Mode Regi ster TRCMR 257

0121h T imer RC Control Register 1 TRCCR1 258, 280, 289,

295

0122h Timer RC Interrupt Enable Register TRCIE R 258

0123h Timer RC Status Register TRCSR 259

0124h Timer RC I/O Cont rol Register 0 TRCIO R 0 260, 275, 281

0125h Timer RC I/O Cont rol Register 1 TRCIO R 1 260, 276, 282

0126h Timer RC Counter TRC 261

0127h

0128h Timer RC General Register A TRCGRA 261

0129h

012Ah Timer RC General Register B TRCGRB 261

012Bh

012Ch Timer RC General Register C TRCGRC 261

012Dh

012Eh Timer RC General Register D TRCGRD 261

012Fh

Address Register Symbol Page

0130h Timer RC Control Register 2 TRCCR2 262, 283, 290,

296

0131h Timer RC Digital Filter Function Select

0132h Timer RC Output Master Enable Register TRCOER 263

0133h Timer RC Trigger Control Register TRCADCR 263

0134h

0135h Timer RD Control Expansion Regi ster TRDECR 314, 329, 349,

364, 378, 395

0136h Timer RD Trigger Control Registe r TRDADCR 330, 350, 365,

379, 396

0137h Timer RD Start Register TRDSTR 315, 33 1, 351 ,

366, 380, 397

0138h Timer RD Mode Register TRDMR 315, 332, 351,

366, 380, 397

0139h Timer RD PWM Mode Register TRDPMR 316, 333, 352

013Ah Timer R D Function Control Register TRDFCR 316, 333, 352,

367, 381, 398

013Bh Timer RD Output Master Enable Register 1 TRDOER1 334, 353, 368,

382, 399

013Ch Timer RD Output Master Enable Register 2 TRDOER2 334, 353, 368,

382, 399

013Dh Timer RD Output Control Register TRDOCR 335, 354, 400

013Eh Timer RD Digi tal Filter Function Select

013Fh Timer RD Digital Filter Function Select

0140h Timer RD Control Register 0 TRDCR0 318, 336, 354,

369, 383, 401

0141h Timer RD I/O Control Register A0 TRDIORA0 319, 337

0142h Timer RD I/O Control Register C0 TRDIORC0 320, 338

0143h Timer RD Status Register 0 TRDSR0 321, 339, 355,

370, 384, 402

0144h Timer RD Interrupt Enable Register 0 TRDIER0 322, 340, 356,

371, 385, 403

0145h Timer RD PWM Mode Output Level Control

0146h Timer RD Counter 0 TRD0 322, 340, 357,

371, 386, 403

0147h

0148h Timer RD General Register A0 TRDGRA0 323, 341, 357,

372, 387, 404

0149h

014Ah Timer RD General Regis ter B0 TRDGRB0 323, 341, 357,

372, 387, 404

014Bh

014Ch Timer RD General Register C0 TRDGRC0 323, 341, 357,

372, 404

014Dh

014Eh Timer RD General Register D0 TRDGRD0 323, 341, 357,

372, 387, 404

014Fh

0150h Timer RD Control Register 1 TRDCR1 318, 336, 354,

383

0151h Timer RD I/O Control Register A1 TRDIORA1 319, 337

0152h Timer RD I/O Control Register C1 TRDIORC1 320, 338

0153h Timer RD Status Register 1 TRDSR1 321, 339, 355,

370, 384, 402

0154h Timer RD Interrupt Enable Register 1 TRDIER1 322, 340, 356,

371, 385, 403

0155h Timer RD PWM Mode Output Level Control

0156h Timer RD Counter 1 TRD1 322, 340, 357,

386

0157h

0158h Timer RD General Register A1 TRDGRA1 323, 341, 357,

372, 387, 404

0159h

015Ah Timer RD General Regis ter B1 TRDGRB1 323, 341, 357,

372, 387, 404

015Bh

015Ch Timer RD General Register C1 TRDGRC1 323, 341, 357,

372, 387, 404

015Dh

015Eh Timer RD General Register D1 TRDGRD1 323, 341, 357,

372, 387, 404

015Fh

B - 4

Note:

1. The blank regions are reserved. Do not access locations in t hese

regions.

Address Register Symbol Page

0160h UART1 Transmit/Receive Mode Register U1MR 436

0161h UART1 Bit Rat e Register U1BRG 436

0162h UART1 Transmit Buffer Regist er U1TB 437

0163h

0164h UART1 Transmit/Receive Control Register 0 U1C0 438

0165h UART1 Transmit/Receive Control Register 1 U1C1 438

0166h UART1 Receive Buffer Regi ste r U1RB 439

0167h

0168h

0169h

016Ah

016Bh

016Ch

016Dh

016Eh

016Fh

0170h

0171h

0172h

0173h

0174h

0175h

0176h

0177h

0178h

0179h

017Ah

017Bh

017Ch

017Dh

017Eh

017Fh

0180h Timer RA Pin Select Register TRASR 75, 220

0181h Timer RB/RC Pin Select Register TRBRCSR 75, 238, 264

0182h Timer RC Pin Select Register 0 TRCPSR0 76, 265

0183h Timer RC Pin Select Register 1 TRCPSR1 77, 266

0184h Timer RD Pin Select Register 0 TRDPSR0 78, 324, 342,

358, 373,

389, 406

0185h Timer RD Pin Select Register 1 TRDPSR1 78, 324, 342,

358, 373,

389, 406

0186h Timer Pin Select Register TIMSR 79, 423, 429

0187h

0188h UART0 Pin Sele ct Register U0SR 80, 440

0189h UART1 Pin Sele ct Register U1SR 80, 440

018Ah UART2 Pin Select Register 0 U2SR0 81, 466

018Bh UART2 Pin Select Register 1 U2SR1 81, 466

018Ch SSU/IIC Pin Select Register SSUIICSR 82, 504, 535

018Dh

018Eh INT Interrupt Input Pin Select Register INTSR 83, 164

018Fh I/O Function Pin Select Register PINSR 84, 126, 536

0190h

0191h

0192h

0193h SS Bit Counter Re gister SSBR 505

0194h SS Transmit Data Regist er L / IIC bu s Transmit

Data Register SSTDR /

ICDRT 505, 537

0195h S S Transmit Data Register H SSTDRH

0196h SS Receive Data Register L / IIC bus Receive

Data Register SSRDR /

ICDRR 506, 537

0197h S S Receive Data Register H SSRDRH

0198h SS Control Regi ste r H / IIC bus C ontrol

ICCR1 506, 538

0199h

SS Control Register L / IIC bus Control Register 2

SSCRL /

ICCR2 507, 539

019Ah SS Mode Register / IIC bus Mode Register SSMR /

ICMR 508, 540

019Bh SS Enable Register / IIC bus Int erru pt Ena bl e

ICIER 509, 541

019Ch SS Status Register / IIC bus Status Register

SSSR / ICSR

510, 542

019Dh SS Mode Register 2 / Slave Address Register SSMR2 /

SAR 511, 543

019Eh

019Fh

Address Register Symbol Page

01A0h

01A1h

01A2h

01A3h

01A4h

01A5h

01A6h

01A7h

01A8h

01A9h

01AAh

01ABh

01ACh

01ADh

01AEh

01AFh

01B0h

01B1h

01B2h Flash Memory Status Re gi ste r FST 623

01B3h

01B4h Flash Memory Control Register 0 FMR0 625

01B5h Flash Memory Control Register 1 FMR1 627

01B6h Flash Memory Control Register 2 FMR2 629

01B7h

01B8h

01B9h

01BAh

01BBh

01BCh

01BDh

01BEh

01C0h Address Match Interrupt Register 0 RMAD0 171

01C1h

01C2h

01C3h Address Match Interrupt Enable Register 0 AIER0 171

01C4h Address Match Interrupt Register 1 RMAD1 171

01C5h

01C6h

01C7h Address Match Interrupt Enable Register 1 AIER1 171

01C8h

01C9h

01CAh

01CBh

01CCh

01CDh

01CEh

01CFh

01D0h

01D1h

01D2h

01D3h

01D4h

01D5h

01D6h

01D7h

01D8h

01D9h

01DAh

01DBh

01DCh

01DDh

01DEh

01DFh

B - 5

Note:

1. The blank regions are reserved. Do not access locations in t hese

regions.

Address Register Symbol Page

01E0h Pull-Up Control Register 0 PUR0 85

01E1h Pull-Up Control Register 1 PUR1 85

01E2h

01E3h

01E4h

01E5h

01E6h

01E7h

01E8h

01E9h

01EAh

01EBh

01ECh

01EDh

01EEh

01EFh

01F0h Port P1 Drive Cap acity Control Register P1DRR 86

01F1h Port P2 Drive Cap acity Control Register P2DRR 86

01F2h Drive Capacity Control Registe r 0 DRR0 87

01F3h Drive Capacity Control Registe r 1 DRR1 88

01F4h

01F5h Input Threshold Control Register 0 VLT0 89

01F6h Input Threshold Control Register 1 VLT1 90

01F7h

01F8h Comparator B Control Register 0 INTCMP 613

01F9h

01FAh External Input Enable Register 0 INTEN 165, 613

01FBh External Input Enable Register 1 INTEN1 165

01FCh INT Input Filter Select Register 0 INTF 166, 614

01FDh INT Input Filter Select Register 1 INTF1 166

01FEh Key Input Enable Register 0 KIEN 169

01FFh

2C00h DTC Transfer Vector Area

2C01h DTC Transfer Vector Area

2C02h DTC Transfer Vector Area

2C03h DTC Transfer Vector Area

2C04h DTC Transfer Vector Area

2C05h DTC Transfer Vector Area

2C06h DTC Transfer Vector Area

2C07h DTC Transfer Vector Area

2C08h DTC Transfer Vector Area

2C09h DTC Transfer Vector Area

2C0Ah DTC Transfer Vector Area

: DTC Transfer Vector Area

2C3Ah DTC Transfer Vector Area

2C3Bh DTC Transfer Vector Area

2C3Ch DTC Transfer Vector Area

2C3Dh DTC Transfer Vector Area

2C3Eh DTC Transfer Vector Area

2C3Fh DTC Transfer Vector Area

2C40h DTC Control Data 0 DTCD0

2C41h

2C42h

2C43h

2C44h

2C45h

2C46h

2C47h

2C48h DTC Control Data 1 DTCD1

2C49h

2C4Ah

2C4Bh

2C4Ch

2C4Dh

2C4Eh

2C4Fh

Address Register Symbol Page

2C50h DTC Control Data 2 DTCD2

2C51h

2C52h

2C53h

2C54h

2C55h

2C56h

2C57h

2C58h DTC Control Data 3 DTCD3

2C59h

2C5Ah

2C5Bh

2C5Ch

2C5Dh

2C5Eh

2C5Fh

2C60h DTC Control Data 4 DTCD4

2C61h

2C62h

2C63h

2C64h

2C65h

2C66h

2C67h

2C68h DTC Control Data 5 DTCD5

2C69h

2C6Ah

2C6Bh

2C6Ch

2C6Dh

2C6Eh

2C6Fh

2C70h DTC Control Data 6 DTCD6

2C71h

2C72h

2C73h

2C74h

2C75h

2C76h

2C77h

2C78h DTC Control Data 7 DTCD7

2C79h

2C7Ah

2C7Bh

2C7Ch

2C7Dh

2C7Eh

2C7Fh

2C80h DTC Control Data 8 DTCD8

2C81h

2C82h

2C83h

2C84h

2C85h

2C86h

2C87h

2C88h DTC Control Data 9 DTCD9

2C89h

2C8Ah

2C8Bh

2C8Ch

2C8Dh

2C8Eh

2C8Fh

B - 6

Note:

1. The blank regions are reserved. Do not access locations in t hese

regions.

Address Register Symbol Page

2C90h DTC Control Data 10 DTCD10

2C91h

2C92h

2C93h

2C94h

2C95h

2C96h

2C97h

2C98h DTC Control Data 11 DTCD11

2C99h

2C9Ah

2C9Bh

2C9Ch

2C9Dh

2C9Eh

2C9Fh

2CA0h DTC Control Data 12 DTCD12

2CA1h

2CA2h

2CA3h

2CA4h

2CA5h

2CA6h

2CA7h

2CA8h DTC Control Data 13 DTCD13

2CA9h

2CAAh

2CABh

2CACh

2CADh

2CAEh

2CAFh

2CB0h DTC Control Data 14 DTCD14

2CB1h

2CB2h

2CB3h

2CB4h

2CB5h

2CB6h

2CB7h

2CB8h DTC Control Data 15 DTCD15

2CB9h

2CBAh

2CBBh

2CBCh

2CBDh

2CBEh

2CBFh

2CC0h DTC Control Data 16 DTCD16

2CC1h

2CC2h

2CC3h

2CC4h

2CC5h

2CC6h

2CC7h

2CC8h DTC Control Data 17 DTCD17

2CC9h

2CCAh

2CCBh

2CCCh

2CCDh

2CCEh

2CCFh

Address Register Symbol Page

2CD0h DTC Control Data 18 DTCD18

2CD1h

2CD2h

2CD3h

2CD4h

2CD5h

2CD6h

2CD7h

2CD8h DTC Control Data 19 DTCD19

2CD9h

2CDAh

2CDBh

2CDCh

2CDDh

2CDEh

2CDFh

2CE0h DTC Control Data 20 DTCD20

2CE1h

2CE2h

2CE3h

2CE4h

2CE5h

2CE6h

2CE7h

2CE8h DTC Control Data 21 DTCD21

2CE9h

2CEAh

2CEBh

2CECh

2CEDh

2CEEh

2CEFh

2CF0h DTC Control Data 22 DTCD22

2CF1h

2CF2h

2CF3h

2CF4h

2CF5h

2CF6h

2CF7h

2CF8h DTC Control Data 23 DTCD23

2CF9h

2CFAh

2CFBh

2CFCh

2CFDh

2CFEh

2CFFh

2D00h

2D01h

FFDBh Option Function Select Register 2 OFS2 31, 183, 190

FFFFh Option Function Select Register OFS 30, 49, 182,

189, 621

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 1 of 723

R8C/34C Group

RENESAS MCU

1. Overview

1.1 Features

The R8C/34C Group of single-chip MCUs incorporates the R8C CPU core, employing sophisticated instructions

for a high level of efficiency. With 1 Mbyte of address space, and it is capable of executing instructions at high

speed. In addition, the CPU core boasts a multiplier for high-speed operation processing.

Power consumption is low, and the suppo rted operating modes allow additional pow er control. These MCUs are

designed to maximize EMI/EMS performance.

Integration of many peripheral functions, including multifunction timer and serial interface, reduces the number of

system components.

The R8C/34C Group has data flash (1 KB × 4 blocks) wit h the background operation (BGO) function.

1.1.1 Applications

Electronic household appli a nces, office equi pment, audio equipment , consumer equipment, etc.

REJ09B0586-0100

Rev.1.00

Jan 13, 2010

R8C/34C Group 1. Overview

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 2 of 723

1.1.2 Specifications

Tables 1.1 and 1.2 outline the Specificat ions for R8C/34C Group.

Table 1.1 Specific ations for R8C/34C Group (1)

Item Function Specification

CPU Central processing

unit R8C CPU core

• Number of fundamental instructions: 89

• Minimum instruction execution time:

50 ns (f(XIN) = 20 MHz, VCC = 2.7 to 5.5 V)

200 ns (f(XIN) = 5 MHz, VCC = 1.8 to 5.5 V)

• Multiplier: 16 bits × 16 bits → 32 bits

• Multiply-accumulate instruction: 16 bits × 16 bits + 32 bits → 32 bits

• Operation mode: Single-chip mode (addre s s space: 1 Mbyte)

Memory ROM, RAM, Data

flash Refer to Table 1.3 Product List for R8C/34C Group.

Power Supply

Voltage

Detection

Voltage detection

circuit • Power-on reset

• Voltage detection 3 (d etection level of voltage detection 0 and voltage

detection 1 selectable)

I/O Ports Programmable I/O

ports • Input-only: 1 pin

• CMOS I/O ports: 43, sele ctable pull-up resistor

• High current drive ports: 43

Clock Clock generation

circuits • 4 circuits: XIN clock oscillation circuit,

XCIN clock oscillation circuit (32 kHz),

High-speed on-chip oscillator (with frequency adjustment function),

Low-speed on-chip osci llator

• Oscillation stop detection: XIN clock oscillation stop detection function

• Frequency divider circuit: Dividing selectable 1, 2, 4, 8, and 16

• Low power consumption modes:

Standard operating mode (high-speed clock, low-speed clock, high-speed

on-chip oscillator, low-speed on-chip oscillator), wait mode, stop mode

Real-time clock (timer RE)

Interrupts • Number of interrupt vectors: 69

• External Interru pt: 9 (INT × 5, Key input × 4)

• Priority levels: 7 levels

Watchdog Timer • 14 bits × 1 (with prescaler)

• Reset start selectable

• Low-speed on-chip oscillator for watchdog timer sele ctable

DTC (Data Transfer Controller) • 1 channel

• Activation sources: 33

• Transfer modes: 2 (normal mode, repeat mode)

Timer Timer RA 8 bits × 1 (with 8-bit prescaler)

Timer mode (period timer), pulse output mode (output level inverted every

period), event counter mode, pulse width measurement mode, pulse period

measurement mode

Timer RB 8 bits × 1 (with 8-bit prescaler)

Timer mode (period timer), programmable waveform generation mode (PWM

output), programmable one-shot generation mode, programma ble wait one-

shot generation mode

Timer RC 16 bits × 1 (with 4 capture/compare registers)

Timer mode (input capture function, output compare function), PWM mode

(output 3 pins), PWM2 mode (PWM output pin)

Timer RD 16 bits × 2 (with 4 capture/compare registers)

Timer mode (input capture function, output compare function), PWM mode

(output 6 pins), reset synchronous PWM mode (output three-phase

waveforms (6 pins), sawtooth wave modulation), complementary PWM mode

(output three-phase waveforms (6 pins), triangular wave modulation), PWM3

mode (PWM output 2 pins with fixed period)

Timer RE 8 bits × 1

Real-time clock mode (count seconds, minutes, hours, days of week), output

compare mode

R8C/34C Group 1. Overview

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 3 of 723

Note:

1. Specify the D version if D version functions are to be used.

Table 1.2 Specific ations for R8C/34C Group (2)

Item Function Specification

Serial

Interface UART0, UART1 Clock synchronous serial I/O/UART × 2 channel

UART2 Clock synchronous serial I/O/UART, I2C mode (I2C-bus), multiprocessor

communication function

Synchronous Serial

Communication Unit (SSU) 1 (shared with I2C-bus)

I2C bus 1 (shared with SSU)

LIN Module Hardware LIN: 1 (timer RA, UART0)

A/D Converter 10-bit resolution × 12 channels, includes sample and hold function, with sweep

mode

D/A Converter 8-bit resolution × 2 circuits

Comparator B 2 circuits

Flash Memory • Programming and erasure voltage: VCC = 2.7 to 5.5 V

• Programming and erasure endurance: 10,000 times (data flash)

1,000 times (program ROM)

• Program security: ROM code protect, ID code check

• Debug functions: On-chip deb ug, on-board flash rewrite function

• Background operation (BGO) function

Operating Frequency/Supply

Voltage f(XIN) = 20 MHz (VCC = 2.7 to 5.5 V)

f(XIN) = 5 MHz (VCC = 1.8 to 5.5 V)

Current consumption Typ. 6.5 mA (VCC = 5.0 V, f(XIN) = 20 MHz)

Typ. 3.5 mA (VCC = 3.0 V, f(XIN) = 10 MHz)

Typ. 3.5 µA (VCC = 3.0 V, wait mode (f(XCIN) = 32 kHz))

Typ. 2.0 µA (VCC = 3.0 V, stop mode)

Operating Ambient Temperature -20 to 85°C (N version)

-40 to 85°C (D version) (1)

Package 48-pin LQFP

Package code: PLQP0048KB-A (previous code: 48P6Q-A)

R8C/34C Group 1. Overview

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 4 of 723

1.2 Product List

Table 1.3 lists Prod uct List for R8 C/34C Grou p, and Figure 1.1 shows a Part Number, Memory Size, and Package

of R8C/34C Group.

(D): Under development

Figure 1.1 Part Number, Memory Size, and Package of R8C/34C Group

Table 1.3 Product List for R8C/34C Group Current of Jan. 2010

Part No. ROM Capacity RAM

Capacity Package Type Remarks

P r o g r a m R O M Data flash

R5F21344CNFP 16 Kbytes 1 Kbyte × 4 1.5 Kbytes PLQP0048KB-A N version

R5F21345CNFP 24 Kbytes 1 Kbyte × 4 2 Kbytes PLQP0048KB-A

R5F21346CNFP 32 Kbytes 1 Kbyte × 4 2.5 Kbytes PLQP0048KB-A

R5F21344CDFP (D) 16 Kbytes 1 Kbyte × 4 1.5 Kbytes PLQP0048KB-A D version

R5F21345CDFP (D) 24 Kbytes 1 Kbyte × 4 2 Kbytes PLQP0048KB-A

R5F21346CDFP (D) 32 Kbytes 1 Kbyte × 4 2.5 Kbytes PLQP0048KB-A

Part No. R 5 F 21 34 6 C N FP

Package type:

FP: PLQP0048KB-A (0.5 mm pin-pitch, 7 mm square body)

Classification

N: Operating ambient temperature -20°C to 85°C

D: Operating ambient temperature -40°C to 85°C

ROM capacity

4: 16 KB

5: 24 KB

6: 32 KB

R8C/34C Group

R8C/3x Serie s

Memory type

F: Flash memory

Renesas MCU

Renesas semiconductor

R8C/34C Group 1. Overview

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 5 of 723

1.3 Block Diagram

Figure 1.2 shows a Block Diagram.

Figure 1.2 B lo ck Diag ra m

D/A converter

(8 bits × 2)

R8C CPU core

System clock generation

circuit

XIN-XOUT

High-speed on-chip oscillator

Low-speed on-chip oscillator

XCIN-XCOUT

Memory

ROM (1)

RAM (2)

Multiplier

R0H R0L

R1H R2

R1L

USP

ISP

INTB

FLG

I/O ports

Notes:

1. ROM size varies with MCU type.

2. RAM size varies with MCU type.

Timers

Timer RA (8 bits × 1)

Timer RB (8 bits × 1)

Timer RC (16 bits × 1)

Timer RD (16 bits × 2)

Timer RE (8 bits × 1)

UART or

clock synchronous serial I/O

(8 bits × 3)

I2C bus or SS U

(8 bits × 1)

Peripheral functions

Watchdog timer

(14 bits)

A/D converter

(10 bits × 12 channels)

LIN module

Comparator B

Voltage detection circuit

DTC

Port P6

Low-speed on-chip oscillator

for wa tch d o g time r

5 1

Port P4

Port P3

Port P2

Port P1

Port P0

R8C/34C Group 1. Overview

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 6 of 723

1.4 Pin Assignment

Figure 1.3 shows the Pin Assignment (Top View). Tables 1.4 and 1.5 outline the Pin Name Information by Pin

Number.

Figure 1.3 Pin Assignment (Top View)

36 35 34 33 32 31 30 29

1 34567891011122

P0_7/AN0/DA1(/TRCIOC)

P0_6/AN1/DA0(/TRCIOD)

P0_5/AN2(/TRCIOB)

P0_4/AN3/TREO(/TRCIOB)

P0_3/AN4(/CLK1/TRCIOB)

P0_2/AN5(/RXD1/TRCIOA/TRCTRG)

P0_1/AN6(/TXD1/TRCIOA/TRCTRG)

P0_0/AN7(/TRCIOA/TRCTRG)

P6_4(/RXD1)

P6_3(/TXD1)

P6_2(/CLK1)

P6_1

Notes:

1. Can be assigned to the pin in parentheses by a program.

2. Confirm the pin 1 position on the package by referring to the package dimensions.

28 27 26 25

P3_1(/TRBO)

P2_0(/INT1/TRCIOB/TRDIOA0/TRDCLK)

P2_1(/TRCIOC/TRDIOC0)

P2_2(/TRCIOD/TRDIOB0)

P2_3(/TRDIOD0)

P2_4(/TRDIOA1)

P2_5(/TRDIOB1)

P2_6(/TRDIOC1)

P2_7(/TRDIOD1)

P3_3/IVCMP3/INT3/SCS(/CTS2/RTS2/TRCCLK)

P3_4/IVREF3/SSI(/RXD2/SCL2/TXD2/SDA2/TRCIOC)

P3_5/SCL/SSCK(/CLK2/TRCIOD)

P6_0(/TREO)

P3_0(/TRAO)

P4_2/VREF

MODE

P4_3(/XCIN)

P4_4(/XCOUT)

RESET

P4_7/XOUT

VSS/AVSS

P4_6/XIN

VCC/AVCC

P3_7/SDA/SSO/TRAO(/RXD2/TXD2/SCL2/SDA2)

P1_0/AN8/KI0(/TRCIOD)

P1_1/AN9/KI1(/TRCIOA/TRCTRG)

P1_2/AN10/Kl2(/TRCIOB)

P1_3/AN11/Kl3/TRBO(/TRCIOC)

P1_4(/TRCCLK/TXD0)

P1_5(/INT1/RXD0/TRAIO)

P1_6/IVREF1(/CLK0)

P1_7/IVCMP1/INT1(/TRAIO)

P4_5/ADTRG/INT0(/RXD2/SCL2)

P6_5/INT4(/CLK1/CLK2/TRCIOB)

P6_6/INT2(/TXD2/SDA2/TRCIOC)

P6_7(/INT3/TRCIOD)

R8C/34C Group

PLQP0048KB-A(48P6Q-A)

(top view)

R8C/34C Group 1. Overview

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 7 of 723

Note:

1. Can be assigned to the pin in parentheses by a program.

Table 1.4 Pin Name Information by Pin Number (1)

Number Control Pin Port

I/O Pin Functions fo r Peripheral Modules

Interrupt Timer Serial

Interface SSU I2C

bus

A/D Converter,

D/A Converter,

Comparator B

1P6_0(TREO)

2P3_0(TRAO)

3P4_2 VREF

4MODE

5(XCIN)P4_3

6 (XCOUT) P4_4

7RESET

8XOUTP4_7

9 VSS/AVSS

10 XIN P4_6

11 VCC/AVCC

12 P3_7 TRAO (RXD2/SCL2/

TXD2/SDA2) SSO SDA

13 P3_5 (TRCIOD) (CLK2) SSCK SCL

14 P3_4 (TRCIOC) (RXD2/SCL2/

TXD2/SDA2) SSI IVREF3

15 P3_3 INT3 (TRCCLK) (CTS2/RTS2)SCS IVCMP3

16 P2_7 (TRDIOD1)

17 P2_6 (TRDIOC1)

18 P2_5 (TRDIOB1)

19 P2_4 (TRDIOA1)

20 P2_3 (TRDIOD0)

21 P2_2 (TRCIOD/

TRDIOB0)

22 P2_1 (TRCIOC/

TRDIOC0)

23 P2_0 (INT1)(TRCIOB/

TRDIOA0/

TRDCLK)

24 P3_1 (TRBO)

25 P6_7 (INT3)(TRCIOD)

26 P6_6 INT2 (TRCIOC) (TXD2/SDA2)

27 P6_5 INT4 (TRCIOB) (CLK1/CLK2)

28 P4_5 INT0 (RXD2/SCL2) ADTRG

29 P1_7 INT1 (TRAIO) IVCMP1

30 P1_6 (CLK0) IVREF1

31 P1_5 (INT1)(TRAIO) (RXD0)

32 P1_4 (TRCCLK) (TXD0)

33 P1_3 KI3 TRBO/

(TRCIOC) AN11

34 P1_2 KI2 (TRCIOB) AN10

35 P1_1 KI1 (TRCIOA/

TRCTRG) AN9

R8C/34C Group 1. Overview

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 8 of 723

Note:

1. Can be assigned to the pin in parentheses by a program.

Table 1.5 Pin Name Information by Pin Number (2)

Number Control Pin Port

I/O Pin Functions fo r Peripheral Modules

Interrupt Timer Serial

Interface SSU I2C

bus

A/D Converter,

D/A Converter,

Comparator B

36 P1_0 KI0 (TRCIOD) AN8

37 P0_7 (TRCIOC) AN0/DA1

38 P0_6 (TRCIOD) AN1/DA0

39 P0_5 (TRCIOB) AN2

40 P0_4 TREO

(/TRCIOB) AN3

41 P0_3 (TRCIOB) (CLK1) AN4

42 P0_2 (TRCIOA/

TRCTRG) (RXD1) AN5

43 P0_1 (TRCIOA/

TRCTRG) (TXD1) AN6

44 P0_0 (TRCIOA/

TRCTRG) AN7

45 P6_4 (RXD1)

46 P6_3 (TXD1)

47 P6_2 (CLK1)

48 P6_1

R8C/34C Group 1. Overview

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 9 of 723

1.5 Pin Functions

Tables 1.6 and 1.7 list Pin Functions.

I: Input O: Output I/O: Input and output

Note:

1. Refer to the oscillator manufacturer for oscillation characteristics.

Table 1.6 Pin Functions (1)

Item Pin Name

I/O Type

Description

Power supply input VCC, VSS −Apply 1.8 V to 5.5 V to the VCC pin. Apply 0 V to the VSS pin.

Analog power

supply input AVCC, AVSS −Power supply for the A/D converter.

Connect a capacitor between AVCC and AVSS.

Reset input RESET I Input “L” on this pin resets the MCU.

MODE MOD E I Connect this pin to VCC via a resistor.

XIN clock input XIN I These pi ns are provided for XIN clock generation circuit I/O.

Connect a ceramic resonator or a crystal oscillator between

the XIN and XOUT pins

(1). To use an external clock, input it

to the XOUT pin and leave the XIN pin open.

XIN clock output XOUT I/O

XCIN clock input XCIN I These pins are provided for XCIN clock generation circuit I/O.

Connect a crystal oscillator between the XCIN and XCOUT

pins (1). To use an external clock, input it to the XCIN pin and

leave the XCOUT pin open.

XCIN clock output XCOUT O

INT interrupt input INT0 to INT4 IINT interrupt inpu t pins.

INT0 is timer RB, RC and RD input pin.

Key input interrupt KI0 to KI3 I Key input interrupt inp ut pins

Timer RA TRAIO I/O Timer RA I/O pin

TRAO O Timer RA output pin

Timer RB TRBO O Timer RB output pin

Timer RC TRCCLK I External clock input pin

TRCTRG I External trigger input pin

TRCIOA, TRCIOB,

TRCIOC, TRCIOD I/O Timer RC I/O pins

Timer RD TRDIOA0, TRDIOA1,

TRDIOB0, TRDIOB1,

TRDIOC0, TRDIOC1,

TRDIOD0, TRDIOD1

I/O Timer RD I/O pins

TRDCLK I External clock input pin

Timer RE TREO O Divided clock output pin

Serial interface CLK0, CLK1, CLK2 I/O Transfer clock I/O pins

RXD0, RXD1, RXD2 I Serial data input pins

TXD0, TXD1, TXD2 O Serial data output pins

CTS2 I Transmission control input pin

RTS2 O Reception control output pin

SCL2 I/O I2C mode clock I/O pin

SDA2 I/O I2C mode data I/O pin

I2C bus SCL I/O Clock I/O pin

SDA I/O Data I/O pin

SSU SSI I/O Data I/O pi n

SCS I/O Chip-select signal I/O pin

SSCK I/O Clock I/O pin

SSO I/O Data I/O pi n

R8C/34C Group 1. Overview

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 10 of 723

I: Input O: Output I/O: Input and output

Table 1.7 Pin Functions (2)

Item Pin Name

I/O Type

Description

Reference voltage

input VREF I Reference voltage input pin to A/D converter and D/A

converter

A/D converter AN0 to AN11 I Analog input pins to A/D converter

ADTRG I A/D external trigger input pi n

D/A converter DA0, DA1 O D/A converter output pins

Comparator B IVCMP1, IVCMP3 I Comparator B analog voltage input pins

IVREF1, IVREF3 I Comparator B reference voltage input pins

I/O port P0_0 to P0_7,

P1_0 to P1_7,

P2_0 to P2_7,

P3_0, P3_1,

P3_3 to P3_5, P3_7,

P4_3 to P4_7,

P6_0 to P6_7

I/O CMOS I/O ports. Each port has an I/O select direction

or output individually.

Any port set to input can be set to use a pull-up resistor or not

by a program.

All ports can be used as LED drive ports.

Input port P4_2 I Input-only port

R8C/34C Group 2. Central Processing Unit (CPU)

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 11 of 723

2. Central Processing Unit (CPU)

Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB configure a

Figure 2.1 C PU Registers

b31 b15 b8b7 b0

Data registers (1)

Address registers (1)

R3 R0H (high-order of R0)

INTBHb15b19 b0

INTBL

FB Frame base register (1)

The 4 high order bits of INTB are INTBH and

the 16 low order bits of INTB are INTBL.

Interrupt table register

b19 b0

USP

Program counter

ISP

User stack pointer

Interrupt stack pointer

Static base register

FLG Flag register

Carry flag

Debug flag

Zero flag

Sign flag

Overflow flag

Interrupt enable flag

Stack pointer select flag

Reserved bit

Processor interrupt priority level

Reserved bit

IPL DZSBOIU

b15 b0

b8 b7

Note:

1. These registers comprise a register bank. There are two register banks.

R1H (high-order of R1)

R0L (low-order of R0)

R1L (low-order of R1)

R8C/34C Group 2. Central Processing Unit (CPU)

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 12 of 723

2.1 Data Registers (R0, R1, R2, and R3)

R0 is a 16-bit re gister for transfer, arithmetic, and lo gic operations. The same app lies to R1 to R3. R0 can be split

into high-order bits (R 0H) and low-order bit s (R0L) to be used sep aratel y as 8-bit data regist ers. R1H and R 1L are

analogous to R0H and R0L. R2 can be combined with R0 and used a s a 32-bit data regi ster (R2R0). R3R1 is

analogous to R2R0.

2.2 Address Registers (A0 and A1)

A0 is a 16-bit register for address register indirect addressing and address register relative addressing. It is also

used for transfer, arithmetic, and logic operations. A1 is analogous to A0. A1 can be combined with A0 and as a 32-

bit address register (A1A0).

2.3 Frame Base Register (FB)

FB is a 16-bit register for FB relative addressing.

2.4 Interrupt Table Register (INTB)

INTB is a 20-bit register that indicates the starting address of an interrupt vector table.

2.5 Program Counter (PC)

PC is 20 bits wide and indicates the address of the next instruction to be executed.

2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)

The stack pointers (SP), USP and ISP, are each 16 bits wide. The U flag of FLG is used to switch between

USP and ISP.

2.7 Static Base Register (SB)

SB is a 16-bit register for SB relative addressing.

2.8 Flag Register (FLG)

FLG is an 11-bit register indicating the CPU state.

2.8.1 Carry Flag (C)

The C flag retains carry, borrow, or shift-out bits that have been gen e rated by the arithmetic and logic unit.

2.8.2 Debug Flag (D)

The D flag is for debugging only. Set it to 0.

2.8.3 Zero Flag (Z)

The Z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0.

2.8.4 Sign Flag (S)

The S flag is set to 1 when an arithmetic operation results in a negative valu e; otherwise to 0.

2.8.5 Register Bank Select Flag (B)

2.8.6 Overflow Flag (O)

The O flag is set to 1 when an operation results in an overflow; otherwise to 0.

R8C/34C Group 2. Central Processing Unit (CPU)

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 13 of 723

2.8.7 Interrupt Enable Flag (I)

The I flag enables maskable interrupts.

Interrupts are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0

when an interrupt request is acknowledged.

2.8.8 Stack Pointer Select Flag (U)

ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1.

The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software

interrupt numbers 0 to 31 is executed.

2.8.9 Processor Interrupt Priority Level (IPL)

IPL is 3 bits wide and assigns processor inte rrupt priorit y levels from level 0 to level 7.

If a requested interrupt has higher priority than IPL, the interrupt is enabled.

2.8.10 Reserved Bit

If necessary, set to 0. When read, the content is undefined.

R8C/34C Group 3. Memory

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 14 of 723

3. Memory

3.1 R8C/34C Group

Figure 3.1 is a Memory Map of R8C/34C Group. The R8C/34C Group has a 1-Mbyte address space from addresses

00000h to FFFFFh. The internal ROM (program ROM) is allocated lower addresses, beginning with address

0FFFFh. For example, a 32-Kbyte internal ROM area is allocated addresses 08000h to 0FFFFh.

The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. The starting address of each interrupt

routine is stored here.

The internal ROM (data flash) is allocated addresses 03000h to 03FFFh.

The internal RAM is allocated higher addresses, beginning with address 00400h. For example, a 2.5-Kbyte internal

RAM area is allocated addresses 00400h to 00DFFh. The internal RAM is used not only for data storage but also as

a stack area when a subroutine is called or when an interrupt request is acknowledged.

Special function registers (SFRs) are allocated addresses 00000h to 002FFh and 02C00h to 02FFFh. Peripheral

function control registers are allocated here. All unallocated spaces within the SFRs are reserved and cannot be

accessed by users.

Figure 3.1 Memory Map of R8C/34C Group

0FFFFh

0FFDCh

Notes:

1. Data flash indicates block A (1 Kbyte), block B (1 Kbyte), block C (1 Kbyte), and block D (1 Kbyte).

2. The blank areas are reserved and c annot be accessed by users.

FFFFFh

0FFFFh

0YYYYh

0XXXXh

00400h

002FFh

00000h

Internal ROM

(program ROM)

Internal RAM

SFR

(Refer to 4. Special

Function Registers

(SFRs))

02FFFh

02C00h SFR

(Refer t o 4. Special Functi on

Registers (SFRs))

ZZZZZh

Internal ROM

(program ROM)

03FFFh

03000h Internal ROM

(data flash) (1)

0FFD8h

Reserved area

Undefined instruction

Overflow

BRK instru c tio n

Address match

Single step

Watchdog timer, oscillation stop detection, voltage monitor

Address break

(Reserved)

Reset

Part Number

R5F21344CNFP, R5F21344CDFP

R5F21345CNFP, R5F21345CDFP

R5F21346CNFP, R5F21346CDFP

Internal ROM Internal RAM

Size Address 0YYYYh Size Address 0XXXXh

Address ZZZZZh

16 Kbytes

24 Kbytes

32 Kbytes

0C000h

0A000h

08000h

1.5 Kbytes

2 Kbytes

2.5 Kbytes

009FFh

00BFFh

00DFFh

−

R8C/34C Group 4. Special Function Registers (SFRs)

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 15 of 723

4. Special Function Registers (SFRs)

An SFR (special function register) is a control register for a peripheral function. Tables 4.1 to 4.12 list the special

function registers. Table 4.13 lists the ID Code Areas and Option Function Select Area.

Table 4.1 SFR Information (1 ) (1)

X: Undefined

Notes:

1. The blank areas are reserved and cannot be accessed by users.

2. The CWR bit in the RSTFR register is set to 0 after power-on and voltage monitor 0 reset. Hardware reset, software reset, or watchdog timer

reset does not affect this bit.

3. The CSPROINI bit in the OFS register is set to 0.

4. The LVDAS bit in the OFS register is set to 1.

5. The LVDAS bit in the OFS register is set to 0.

Address Register Symbol After Reset

0000h

0001h

0002h

0003h

0004h Processor Mode Register 0 PM0 00h

0005h Processor Mode Register 1 PM1 00h

0006h System Clock Control Register 0 CM0 00101000b

0007h System Clock Control Register 1 CM1 00100000b

0008h Module Standby Control Register MSTCR 00h

0009h System Clock Control Register 3 CM3 00h

000Ah Protect Register PRCR 00h

000Bh Reset Source Determination Register RSTFR 0XXXXXXXb (2)

000Ch Oscillation Stop Detection Register OCD 00000100b

000Dh Watchdog Timer Reset Register WDTR XXh

000Eh Watchdog Timer Start Register WDTS XXh

000Fh Watchdog Timer Control Register WDTC 00111111b

0010h

0011h

0012h

0013h

0014h

0015h High-Speed On-Chip Oscillat or Control Register 7 FRA7 When shipping

0016h

0017h

0018h

0019h

001Ah

001Bh

001Ch Count Source Protection Mode Register CSPR 00h

10000000b (3)

001Dh

001Eh

001Fh

0020h

0021h

0022h

0023h High-Speed On-Chip Oscillator Control Register 0 FRA0 00h

0024h High-Speed On-Chip Oscillat or Control Register 1 FRA1 When shipping

0025h High-Speed On-Chip Oscillator Control Register 2 FRA2 00h

0026h On-Chip Reference Voltage Control Register OCVREFCR 00h

0027h

0028h Clock Prescaler Reset Flag CPSRF 00h

0029h High-Speed On-Chip Oscillat or Control Register 4 FRA4 When shipping

002Ah High-Speed On-Chip Oscillator Control Register 5 FRA5 When shipping

002Bh High-Speed On-Chip Oscillator Control Register 6 FRA6 When shipping

002Ch

002Dh

002Eh

002Fh High-Speed On-Chip Oscillator Control Register 3 FRA3 When shipping

0030h Voltage Monitor Circuit Control Register CMPA 00h

0031h Voltage Monitor Circuit Edge Select Register VCAC 00h

0032h

0033h Voltage Detect Register 1 VCA1 00001000b

0034h Voltage Detect Register 2 VCA2 00h (4)

00100000b (5)

0035h

0036h Voltage Detection 1 Level Select Register VD1LS 00000111b

0037h

0038h Voltage Monitor 0 Circuit Control Register VW0C 1100X010b (4)

1100X011b (5)

0039h Voltage Monitor 1 Circuit Control Register VW1C 10001010b

R8C/34C Group 4. Special Function Registers (SFRs)

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 16 of 723

Table 4.2 SFR Information (2 ) (1)

X: Undefined

Notes:

1. The blank areas are reserved and cannot be accessed by users.

2. Selectable by the IICSEL bit in the SSUIICSR register.

Address Register Symbol After Reset

003Ah Voltage Monitor 2 Circuit Control Register VW2C 10000010b

003Bh

003Ch

003Dh

003Eh

003Fh

0040h

0041h Flash Memory Ready Interrupt Control Register FMRDYIC XXXXX000b

0042h

0043h

0044h

0045h

0046h INT4 Interrupt Control Register INT4IC XX00X000b

0047h Timer RC Interrupt Control Register TRCIC XXXXX000b

0048h Timer RD0 Interrupt Control Register TRD0IC XXXXX000b

0049h Timer RD1 Interrupt Control Register TRD1IC XXXXX000b

004Ah Timer RE Interrupt Control Register TREIC XXXXX000b

004Bh UART2 Transmit Interrupt Control Register S2TIC XXXXX000b

004Ch UART2 Receive Interrupt Control Register S2RIC XXXXX000b

004Dh Key Input Interrupt Control Register KUPIC XXXXX000b

004Eh A/D Conversion Interrupt Control Register ADIC XXXXX000b

004Fh SSU Interrupt Control Register / IIC bus Interrupt Control Register (2) SSUIC / IICIC XXXXX000b

0050h

0051h UART0 Transmit Interrupt Control Register S0TIC XXXXX000b

0052h UART0 Receive Interrupt Control Register S0RIC XXXXX000b

0053h UART1 Transmit Interrupt Control Register S1TIC XXXXX000b

0054h UART1 Receive Interrupt Control Register S1RIC XXXXX000b

0055h INT2 Interrupt Control Register INT2IC XX00X000b

0056h Timer RA Interrupt Control Register TRAIC XXXXX000b

0057h

0058h Timer RB Interrupt Control Register TRBIC XXXXX000b

0059h INT1 Interrupt Control Register INT1IC XX00X000b

005Ah INT3 Interrupt Control Register INT3IC XX00X000b

005Bh

005Ch

005Dh INT0 Interrupt Control Register INT0IC XX00X000b

005Eh UART2 Bus Collision Detection Interrupt Control Register U2BCNIC XXXXX000b

005Fh

0060h

0061h

0062h

0063h

0064h

0065h

0066h

0067h

0068h

0069h

006Ah

006Bh

006Ch

006Dh

006Eh

006Fh

0070h

0071h

0072h Voltage Monitor 1 Interrupt Control Register VCMP1IC XXXXX000b

0073h Voltage Monitor 2 Interrupt Control Register VCMP2IC XXXXX000b

0074h

0075h

0076h

0077h

0078h

0079h

007Ah

007Bh

007Ch

007Dh

007Eh

007Fh

R8C/34C Group 4. Special Function Registers (SFRs)

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 17 of 723

Table 4.3 SFR Information (3 ) (1)

X: Undefined

Note:

1. The blank areas are reserved and cannot be accessed by users.

Address Register Symbol After Reset

0080h DTC Activation Control Register DTCTL 00h

0081h

0082h

0083h

0084h

0085h

0086h

0087h

0088h DTC Activation Enable Register 0 DTCEN0 00h

0089h DTC Activation Enable Register 1 DTCEN1 00h

008Ah DTC Activation Enable Register 2 DTCEN2 00h

008Bh DTC Activation Enable Register 3 DTCEN3 00h

008Ch DTC Activation Enable Register 4 DTCEN4 00h

008Dh DTC Activation Enable Register 5 DTCEN5 00h

008Eh DTC Activation Enable Register 6 DTCEN6 00h

008Fh

0090h

0091h

0092h

0093h

0094h

0095h

0096h

0097h

0098h

0099h

009Ah

009Bh

009Ch

009Dh

009Eh

009Fh

00A0h UART0 Transmit/Receive Mode Register U0MR 00h

00A1h UART0 Bit Rate Register U0BRG XXh

00A2h UART0 Transmit Buffer Register U0TB XXh

00A3h XXh

00A4h UART0 Transmit/Receive Control Register 0 U0C0 00001000b

00A5h UART0 Transmit/Receive Control Register 1 U0C1 00000010b

00A6h UART0 Receive Buffer Register U0RB XXh

00A7h XXh

00A8h UART2 Transmit/Receive Mode Register U2MR 00h

00A9h UART2 Bit Rate Register U2BRG XXh

00AAh UART2 Transmit Buffer Register U2TB XXh

00ABh XXh

00ACh UART2 Transmit /Receive Control Register 0 U2C0 00001000b

00ADh UART2 Transmit /Receive Control Register 1 U2C1 00000010b

00AEh UART2 Receive Buffer Register U2RB XXh

00AFh XXh

00B0h UART2 Digital Filter Function Select Register URXDF 00h

00B1h

00B2h

00B3h

00B4h

00B5h

00B6h

00B7h

00B8h

00B9h

00BAh

00BBh UART2 Special Mode Register 5 U2SMR5 00 h

00BCh UART2 Special Mode Register 4 U2SMR4 00h

00BDh UART2 Special Mode Register 3 U2SMR3 000X0X0Xb

00BEh UART2 Special Mode Register 2 U2SMR2 X0000000b

00BFh UART2 Special Mode Register U2SMR X0000000b

R8C/34C Group 4. Special Function Registers (SFRs)

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 18 of 723

Table 4.4 SFR Information (4) (1)

X: Undefined

Note:

1. The blank areas are reserved and cannot be accessed by users.

Address Register Symbol After Reset

00C0h A/D Register 0 AD0 XXh

000000XXb00C1h

00C2h A/D Register 1 AD1 XXh

00C3h 000000XXb

00C4h A/D Register 2 AD2 XXh

00C5h 000000XXb

00C6h A/D Register 3 AD3 XXh

00C7h 000000XXb

00C8h A/D Register 4 AD4 XXh

00C9h 000000XXb

00CAh A/D Register 5 AD5 XXh

00CBh 000000XXb

00CCh A/D Register 6 AD6 XXh

00CDh 000000XXb

00CEh A/D Register 7 AD7 XXh

00CFh 000000XXb

00D0h

00D1h

00D2h

00D3h

00D4h A/D Mode Register ADMOD 00h

00D5h A/D Input Select Register ADINSEL 11000000b

00D6h A/D Control Register 0 ADCON0 00h

00D7h A/D Control Register 1 ADCON1 00h

00D8h D/A0 Register DA0 00h

00D9h D/A1 Register DA1 00h

00DAh

00DBh

00DCh D/A Control Register DACON 00h

00DDh

00DEh

00DFh

00E0h Port P0 Register P0 XXh

00E1h Port P1 Register P1 XXh

00E2h Port P0 Direction Register PD0 00h

00E3h Port P1 Direction Register PD1 00h

00E4h Port P2 Register P2 XXh

00E5h Port P3 Register P3 XXh

00E6h Port P2 Direction Register PD2 00h

00E7h Port P3 Direction Register PD3 00h

00E8h Port P4 Register P4 XXh

00E9h

00EAh Port P4 Direction Reg i ster PD4 00h

00EBh

00ECh Port P6 Register P6 XXh

00EDh

00EEh Port P6 Direction Reg i ster PD6 00h

00EFh

00F0h

00F1h

00F2h

00F3h

00F4h

00F5h

00F6h

00F7h

00F8h

00F9h

00FAh

00FBh

00FCh

00FDh

00FEh

00FFh

R8C/34C Group 4. Special Function Registers (SFRs)

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 19 of 723

Table 4.5 SFR Information (5 ) (1)

Note:

1. The blank areas are reserved and cannot be accessed by users.

Address Register Symbol After Reset

0100h Timer RA Control Register TRACR 00h

0101h Timer RA I/O Control Register TRAIOC 00 h

0102h Timer RA Mode Register TRAMR 00h

0103h Timer RA Prescaler Register TRAPRE FFh

0104h Timer RA Register TRA FFh

0105h LIN Control Register 2 LINCR2 00h

0106h LIN Control Register LINCR 00h

0107h LIN Status Register LINST 00h

0108h Timer RB Control Register TRBCR 00h

0109h Timer RB One-Shot Control Register TRBOCR 00h

010Ah Timer RB I/O Control Register TRBIOC 00 h

010Bh Timer RB Mode Register TRBMR 00h

010Ch Timer RB Prescaler Register TRBPRE FFh

010Dh Timer RB Secondary Register TRBSC FFh

010Eh Timer RB Primary Register TRBPR FFh

010Fh

0110h

0111h

0112h

0113h

0114h

0115h

0116h

0117h

0118h Timer RE Second Data Register / Counter Data Register TRESEC 00h

0119h Timer RE Minute Data Register / Compare Data Register TREMIN 00h

011Ah Timer RE Hour Data Register TREHR 00h

011Bh Timer RE Day of Week Data Register TREWK 00h

011Ch Timer RE Control Register 1 TRECR1 00h

011Dh Timer RE Control Register 2 TRECR2 00h

011Eh Timer RE Count Source Select Register TRECSR 00001000b

011Fh

0120h Timer RC Mode Register TRCMR 01001000b

0121h Timer RC Control Register 1 TRCCR1 00h

0122h Timer RC Interrupt Enable Register TRCIER 01110000b

0123h Timer RC Status Register TRCSR 01110000b

0124h Timer RC I/O Control Register 0 TRCIOR0 10001000b

0125h Timer RC I/O Control Register 1 TRCIOR1 10001000b

0126h Timer RC Counter TRC 00h

0127h 00h

0128h Timer RC General Register A TRCGRA FFh

0129h FFh

012Ah Timer RC General Register B TRCGRB FFh

012Bh FFh

012Ch Timer RC General Register C TRCGRC FFh

012Dh FFh

012Eh Timer RC General Register D TRCGRD FFh

012Fh FFh

0130h Timer RC Control Register 2 TRCCR2 000110 00b

0131h Timer RC Digital Filter Function Select Register TRCDF 00h

0132h Timer RC Output Master Enable Register TRCOER 01111111b

0133h Timer RC Trigger Control Register TRCADCR 00h

0134h

0135h Timer RD Control Expansion Register TRDECR 00h

0136h Timer RD Trigger Control Register TRDADCR 00h

0137h Timer RD Start Register TRDSTR 11111100b

0138h Timer RD Mode Register TRDMR 00001110b

0139h Timer RD PWM Mode Register TRDPMR 10001000b

013Ah Timer RD Function Control Register TRDFCR 10000000b

013Bh Timer RD Output Master Enable Register 1 TRDOER1 FFh

013Ch Timer RD Output Master Enable Register 2 TRDOER2 01111111b

013Dh Timer RD Output Control Register TRDOCR 00h

013Eh Timer RD Digital Filter Function Select Register 0 TRDDF0 00h

013Fh Timer RD Digital Filter Function Select Register 1 TRDDF1 00h

R8C/34C Group 4. Special Function Registers (SFRs)

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 20 of 723

Table 4.6 SFR Information (6 ) (1)

X: Undefined

Note:

1. The blank areas are reserved and cannot be accessed by users.

Address Register Symbol After Reset

0140h Timer RD Control Register 0 TRDCR0 00h

0141h Timer RD I/O Control Register A0 TRDIORA0 10001000b

0142h Timer RD I/O Control Register C0 TRDIORC0 10001000b

0143h Timer RD Status Register 0 TRDSR0 11100000b

0144h Timer RD Interrupt Enable Register 0 TRDIER0 11100000b

0145h Timer RD PWM Mode Output Level Control Register 0 TRDPOCR0 11111000b

0146h Timer RD Counter 0 TRD0 00h

0147h 00h

0148h Timer RD General Register A0 TRDGRA0 FFh

0149h FFh

014Ah Timer RD General Register B0 TRDGRB0 FFh

014Bh FFh

014Ch Timer RD General Register C0 TRDGRC0 FFh

014Dh FFh

014Eh Timer RD General Register D0 TRDGRD0 FFh

014Fh FFh

0150h Timer RD Control Register 1 TRDCR1 00h

0151h Timer RD I/O Control Register A1 TRDIORA1 10001000b

0152h Timer RD I/O Control Register C1 TRDIORC1 10001000b

0153h Timer RD Status Register 1 TRDSR1 11000000b

0154h Timer RD Interrupt Enable Register 1 TRDIER1 11100000b

0155h Timer RD PWM Mode Output Level Control Register 1 TRDPOCR1 11111000b

0156h Timer RD Counter 1 TRD1 00h

0157h 00h

0158h Timer RD General Register A1 TRDGRA1 FFh

0159h FFh

015Ah Timer RD General Register B1 TRDGRB1 FFh

015Bh FFh

015Ch Timer RD General Register C1 TRDGRC1 FFh

015Dh FFh

015Eh Timer RD General Register D1 TRDGRD1 FFh

015Fh FFh

0160h UART1 Transmit/Receive Mode Register U1MR 00h

0161h UART1 Bit Rate Register U1BRG XXh

0162h UART1 Transmit Buffer Register U1TB XXh

0163h XXh

0164h UART1 Transmit/Receive Control Register 0 U1C0 00001000b

0165h UART1 Transmit/Receive Control Register 1 U1C1 00000010b

0166h UART1 Receive Buffer Register U1RB XXh

0167h XXh

0168h

0169h

016Ah

016Bh

016Ch

016Dh

016Eh

016Fh

0170h

0171h

0172h

0173h

0174h

0175h

0176h

0177h

0178h

0179h

017Ah

017Bh

017Ch

017Dh

017Eh

017Fh

R8C/34C Group 4. Special Function Registers (SFRs)

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 21 of 723

Table 4.7 SFR Information (7) (1)

X: Undefined

Notes:

1. The blank areas are reserved and cannot be accessed by users.

2. Selectable by the IICSEL bit in the SSUIICSR register.

Address Register Symbol After Reset

0180h Timer RA Pin Select Register TRASR 00h

0181h Timer RB/RC Pin Select Register TRBRCSR 00h

0182h Timer RC Pin Select Register 0 TRCPSR0 00h

0183h Timer RC Pin Select Register 1 TRCPSR1 00h

0184h Timer RD Pin Select Register 0 TRDPSR0 00h

0185h Timer RD Pin Select Register 1 TRDPSR1 00h

0186h Timer Pin Select Register TIMSR 00h

0187h

0188h UART0 Pin Select Register U0SR 00h

0189h UART1 Pin Select Register U1SR 00h

018Ah UART2 Pin Select Register 0 U2SR0 00h

018Bh UART2 Pin Select Register 1 U2SR1 00h

018Ch SSU/IIC Pin Select Register SSUIICSR 00h

018Dh

018Eh INT Interrupt Input Pin Select Register INTSR 00h

018Fh I/O Function Pin Select Register PINSR 00h

0190h

0191h

0192h

0193h SS Bit Counter Register SSBR 11111000b

0194h SS Transmit Data Register L / IIC bus Transmit Data Register (2) SSTDR / ICDRT FFh

0195h SS Transmit Data Register H (2) SSTDRH FFh

0196h SS Receive Data Register L / IIC bus Receive Data Register (2) SSRDR / ICDRR FFh

0197h SS Receive Data Register H (2) SSRDRH FFh

0198h SS Control Register H / IIC bus Control Register 1 (2) SSCRH / ICCR1 00h

0199h SS Control Register L / IIC bus Control Register 2 (2) SSCRL / ICCR2 01111101b

019Ah SS Mode Register / IIC bus Mode Register (2) SSMR / ICMR 00010000b / 00011000b

019Bh SS Enable Register / IIC bus Interrupt Enable Register (2) SSER / ICIER 00h

019Ch SS Status Register / IIC bus Status Register (2) S SSR / ICSR 00h / 0000X000b

019Dh SS Mode Register 2 / Slave Address Register (2) SSMR2 / SAR 00h

019Eh

019Fh

01A0h

01A1h

01A2h

01A3h

01A4h

01A5h

01A6h

01A7h

01A8h

01A9h

01AAh

01ABh

01ACh

01ADh

01AEh

01AFh

01B0h

01B1h

01B2h Flash Memory Status Register FST 10000X00b

01B3h

01B4h Flash Memory Control Register 0 FMR0 00h

01B5h Flash Memory Control Register 1 FMR1 00h

01B6h Flash Memory Control Register 2 FMR2 00h

01B7h

01B8h

01B9h

01BAh

01BBh

01BCh

01BDh

01BEh

01BFh

R8C/34C Group 4. Special Function Registers (SFRs)

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 22 of 723

Table 4.8 SFR Information (8) (1)

X: Undefined

Note:

1. The blank areas are reserved and cannot be accessed by users.

Address Register Symbol After Reset

01C0h Address Match Interrupt Register 0 RMAD0 XXh

01C1h XXh

01C2h 0000XXXXb

01C3h Address Match Interrupt Enable Register 0 AIER0 00h

01C4h Address Match Interrupt Register 1 RMAD1 XXh

01C5h XXh

01C6h 0000XXXXb

01C7h Address Match Interrupt Enable Register 1 AIER1 00h

01C8h

01C9h

01CAh

01CBh

01CCh

01CDh

01CEh

01CFh

01D0h

01D1h

01D2h

01D3h

01D4h

01D5h

01D6h

01D7h

01D8h

01D9h

01DAh

01DBh

01DCh

01DDh

01DEh

01DFh

01E0h Pull-Up Control Register 0 PUR0 00h

01E1h Pull-Up Control Register 1 PUR1 00h

01E2h

01E3h

01E4h

01E5h

01E6h

01E7h

01E8h

01E9h

01EAh

01EBh

01ECh

01EDh

01EEh

01EFh

01F0h Port P1 Drive Capacity Control Register P1DRR 00h

01F1h Port P2 Drive Capacity Control Register P2DRR 00h

01F2h Drive Capacity Control Register 0 DRR0 00h

01F3h Drive Capacity Control Register 1 DRR1 00h

01F4h

01F5h Input Threshold Contr ol Register 0 VLT0 00h

01F6h Input Threshold Contr ol Register 1 VLT1 00h

01F7h

01F8h Comparator B Control Register 0 INTCMP 00h

01F9h

01FAh External Input Enable Register 0 INTEN 00h

01FBh External Input Enable Register 1 INTEN1 00h

01FCh INT Input Filter Select Register 0 INTF 00h

01FDh INT Input Filter Select Register 1 INTF1 00h

01FEh Key Input Enable Register 0 KIEN 00h

01FFh

R8C/34C Group 4. Special Function Registers (SFRs)

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 23 of 723

Table 4.9 SFR Information (9 ) (1)

X: Undefined

Note:

1. The blank areas are reserved and cannot be accessed by users.

Address Register Symbol After Reset

2C00h DTC Transfer Vector Area XXh

2C01h DTC Transfer Vector Area XXh

2C02h DTC Transfer Vector Area XXh

2C03h DTC Transfer Vector Area XXh

2C04h DTC Transfer Vector Area XXh

2C05h DTC Transfer Vector Area XXh

2C06h DTC Transfer Vector Area XXh

2C07h DTC Transfer Vector Area XXh

2C08h DTC Transfer Vector Area XXh

2C09h DTC Transfer Vector Area XXh

2C0Ah DTC Transfer Vector Area XXh

: DTC Transfer Vector Area XXh

2C3Ah DTC Transfer Vector Area XXh

2C3Bh DTC Transfer Vector Area XXh

2C3Ch DTC Transfer Vector Area XXh

2C3Dh DTC Transfer Vector Area XXh

2C3Eh DTC Transfer Vector Area XXh

2C3Fh DTC Transfer Vector Area XXh

2C40h DTC Control Data 0 DTCD0 XXh

2C41h XXh

2C42h XXh

2C43h XXh

2C44h XXh

2C45h XXh

2C46h XXh

2C47h XXh

2C48h DTC Control Data 1 DTCD1 XXh

2C49h XXh

2C4Ah XXh

2C4Bh XXh

2C4Ch XXh

2C4Dh XXh

2C4Eh XXh

2C4Fh XXh

2C50h DTC Control Data 2 DTCD2 XXh

2C51h XXh

2C52h XXh

2C53h XXh

2C54h XXh

2C55h XXh

2C56h XXh

2C57h XXh

2C58h DTC Control Data 3 DTCD3 XXh

2C59h XXh

2C5Ah XXh

2C5Bh XXh

2C5Ch XXh

2C5Dh XXh

2C5Eh XXh

2C5Fh XXh

2C60h DTC Control Data 4 DTCD4 XXh

2C61h XXh

2C62h XXh

2C63h XXh

2C64h XXh

2C65h XXh

2C66h XXh

2C67h XXh

2C68h DTC Control Data 5 DTCD5 XXh

2C69h XXh

2C6Ah XXh

2C6Bh XXh

2C6Ch XXh

2C6Dh XXh

2C6Eh XXh

2C6Fh XXh

R8C/34C Group 4. Special Function Registers (SFRs)

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 24 of 723

Table 4.10 SFR Information (10) (1)

X: Undefined

Note:

1. The blank areas are reserved and cannot be accessed by users.

Address Register Symbol After Reset

2C70h DTC Control Data 6 DTCD6 XXh

2C71h XXh

2C72h XXh

2C73h XXh

2C74h XXh

2C75h XXh

2C76h XXh

2C77h XXh

2C78h DTC Control Data 7 DTCD7 XXh

2C79h XXh

2C7Ah XXh

2C7Bh XXh

2C7Ch XXh

2C7Dh XXh

2C7Eh XXh

2C7Fh XXh

2C80h DTC Control Data 8 DTCD8 XXh

2C81h XXh

2C82h XXh

2C83h XXh

2C84h XXh

2C85h XXh

2C86h XXh

2C87h XXh

2C88h DTC Control Data 9 DTCD9 XXh

2C89h XXh

2C8Ah XXh

2C8Bh XXh

2C8Ch XXh

2C8Dh XXh

2C8Eh XXh

2C8Fh XXh

2C90h DTC Control Data 10 DTCD10 XXh

2C91h XXh

2C92h XXh

2C93h XXh

2C94h XXh

2C95h XXh

2C96h XXh

2C97h XXh

2C98h DTC Control Data 11 DTCD11 XXh

2C99h XXh

2C9Ah XXh

2C9Bh XXh

2C9Ch XXh

2C9Dh XXh

2C9Eh XXh

2C9Fh XXh

2CA0h DTC Control Data 12 DTCD12 XXh

2CA1h XXh

2CA2h XXh

2CA3h XXh

2CA4h XXh

2CA5h XXh

2CA6h XXh

2CA7h XXh

2CA8h DTC Control Data 13 DTCD13 XXh

2CA9h XXh

2CAAh XXh

2CABh XXh

2CACh XXh

2CADh XXh

2CAEh XXh

2CAFh XXh

R8C/34C Group 4. Special Function Registers (SFRs)

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 25 of 723

Table 4.11 SFR Information (11) (1)

X: Undefined

Note:

1. The blank areas are reserved and cannot be accessed by users.

Address Register Symbol After Reset

2CB0h DTC Control Data 14 DTCD14 XXh

2CB1h XXh

2CB2h XXh

2CB3h XXh

2CB4h XXh

2CB5h XXh

2CB6h XXh

2CB7h XXh

2CB8h DTC Control Data 15 DTCD15 XXh

2CB9h XXh

2CBAh XXh

2CBBh XXh

2CBCh XXh

2CBDh XXh

2CBEh XXh

2CBFh XXh

2CC0h DTC Control Data 16 DTCD16 XXh

2CC1h XXh

2CC2h XXh

2CC3h XXh

2CC4h XXh

2CC5h XXh

2CC6h XXh

2CC7h XXh

2CC8h DTC Control Data 17 DTCD17 XXh

2CC9h XXh

2CCAh XXh

2CCBh XXh

2CCCh XXh

2CCDh XXh

2CCEh XXh

2CCFh XXh

2CD0h DTC Control Data 18 DTCD18 XXh

2CD1h XXh

2CD2h XXh

2CD3h XXh

2CD4h XXh

2CD5h XXh

2CD6h XXh

2CD7h XXh

2CD8h DTC Control Data 19 DTCD19 XXh

2CD9h XXh

2CDAh XXh

2CDBh XXh

2CDCh XXh

2CDDh XXh

2CDEh XXh

2CDFh XXh

2CE0h DTC Control Data 20 DTCD20 XXh

2CE1h XXh

2CE2h XXh

2CE3h XXh

2CE4h XXh

2CE5h XXh

2CE6h XXh

2CE7h XXh

2CE8h DTC Control Data 21 DTCD21 XXh

2CE9h XXh

2CEAh XXh

2CEBh XXh

2CECh XXh

2CEDh XXh

2CEEh XXh

2CEFh XXh

R8C/34C Group 4. Special Function Registers (SFRs)

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 26 of 723

Table 4.12 SFR Information (12) (1)

X: Undefined

Note:

1. The blank areas are reserved and cannot be accessed by users.

Table 4.13 ID Code Areas and Option Function Select Area

Notes:

1. The option function select area is allocated in the flash memory, not i n the SFRs. Set appropriate values as ROM data by a program.

Do not write additions to t he option function select area. If the block includi ng the option functio n select area is erased, the optio n function select

area is set to FFh.

When blank products are shipped, the option function select area is set to FFh. It is set to the written value after written by the user.

When factory-programming pr oducts are shipped, the value of the option function select area is the value programmed by the user.

2. The ID code areas are allocated in the flash memory, not in the SFRs. Set appropriate values as ROM data by a program.

Do not write additions to the ID code areas. If the block including the ID code areas is erased, t he ID code areas are set to FFh.

When blank products are sh ipped, the ID code areas are set to FFh. They are set to the written value after written by the user.

When factory-programming pr oducts are shipped, the value of the ID code areas is the value programmed by the user.

Address Register Symbol After Reset

2CF0h DTC Control Data 22 DTCD22 XXh

2CF1h XXh

2CF2h XXh

2CF3h XXh

2CF4h XXh

2CF5h XXh

2CF6h XXh

2CF7h XXh

2CF8h DTC Control Data 23 DTCD23 XXh

2CF9h XXh

2CFAh XXh

2CFBh XXh

2CFCh XXh

2CFDh XXh

2CFEh XXh

2CFFh XXh

2D00h

2FFFh

Address Area Name Symbol After Reset

FFDBh Option Function Select Register 2 OFS2 (Note 1)

FFDFh ID1 (Note 2)

FFE3h ID2 (Note 2)

FFEBh ID3 (Note 2)

FFEFh ID4 (Note 2)

FFF3h ID5 (Note 2)

FFF7h ID6 (Note 2)

FFFBh ID7 (Note 2)

FFFFh Option Function Select Register OFS (Note 1)

R8C/34C Group 5. Resets

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 27 of 723

5. Resets

The following resets are implement ed: hardware reset, power-on reset, volt age monitor 0 reset, wat chdog timer reset,

and software reset.

Table 5.1 lists the Reset Names and Sources. Figure 5.1 shows a Block Diagram of Reset Circuit .

Figure 5.1 B lo ck Diagra m of Rese t Circ ui t

Table 5.1 Reset Names and Sources

Reset Name Source

Hardware reset Input voltage of RESET pin is held “L”

Power-on reset VCC rises

Voltage monitor 0 reset VCC falls (monitor voltage: Vdet0)

Watchdog timer reset Underflow of watchdog timer

Software reset Write 1 to PM03 bit in PM0 register

RESET

Power-on reset

circuit

Voltage

detection

circuit

Watchdog

timer

CPU

Pin, CPU, and SFR (1)

VCC

Hardware reset

Power-on reset

Voltage monitor 0 reset

Watchdog timer

reset

Software reset

Note:

1. The CWR bit in the RST F R register is set to 0 (cold start-up) after power-on or

voltage monitor 0 r eset. This bit rema ins unchanged at a hardware reset,

software reset, or watchdog timer reset.

R8C/34C Group 5. Resets

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 28 of 723

Table 5.2 lists the Pin Functions while RESET Pin Level is “L”, Figure 5.2 shows the CPU Register Status after Reset,

Figure 5.3 shows the Reset Sequence.

Figure 5.2 CPU Register Status after Reset

Figure 5.3 R eset Sequence

Table 5.2 Pin Functions while RESET Pin Level is “L”

Pin Name Pin Function

P0 to P2, P6 Input port

P3_0 and P3_1, P3_3 to P3_5, P3_7 Input port

P4_2 to P4_7 Input port

b19 b0

Interrupt table register (INTB)

Program counter (PC)

User stack pointer (USP)

Interrupt stack pointer (ISP)

Static base register (SB)

Content of addresses 0FFFEh to 0FFFCh

Flag register (FLG)

IPL DZSBOIU

b15 b0

b8 b7

b15 b0

0000h

Data register (R0)

Data register (R1)

Data register (R2)

Data register (R3)

Address register (A0)

Address register (A1)

Frame base register (FB)

00000h

0000h

Start time of flash memory

(CPU clock × 148 cycles)

0FFFCh 0FFFEh

0FFFDh Content of reset vector

CPU clock

Address

(internal address

signal)

Notes:

1. Hardware reset.

2. When the “L” input width to the RESET pin is set to fOCO-S clock × 32 cycles or more, setting the RESET pin to “H” also sets the internal

reset signal to “H” at the same time.

CPU clock × 28 cycles

fOCO-S clock × 32 cycles (2)

fOCO-S

Internal reset

signal

RESET pin

10 µs or more are needed (1)

R8C/34C Group 5. Resets

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 29 of 723

5.1 Registers

5.1.1 Processor Mode Register 0 (PM0)

Set the PRC1 bit in the PRCR register to 1 (write enabled) before rewriting the PM0 register.

5.1.2 Reset Source Determination Register (RSTFR)

Notes:

1. The CWR bit is set to 0 (cold start-up) after power-on or voltage monitor 0 reset. This bit remains unchanged at a

hardware reset, software reset, or watchdog timer reset.

2. If 1 is written to the CWR bit by a program, it is set to 1. (Writing 0 does not affect this bit.)

3. When the VW0C0 bit in the VW0C register is set to 0 (voltage monitor 0 reset disabled), the CWR bit value is

undefined.

Address 0004h

Bitb7b6b5b4b3b2b1b0

Symbol————PM03———

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 — Reserved bits Set to 0. R/W

b1 —

b2 —

b3 PM03 Software reset bit The MCU is reset when this bit is set to 1. When

read, the content is 0. R/W

b4 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b5 —

b6 —

b7 —

Address 000Bh

Bitb7b6b5b4b3b2b1b0

Symbol — — — — WDR SWR HWR CWR

After Reset0XXXXXXX(Note 1)

Bit Symbol Bit Name Function R/W

b0 CWR Cold start-up/warm start-up

determine flag (2, 3) 0: Cold start-up

1: Warm start-up R/W

b1 HWR Hardware reset detect flag 0: Not detected

1: Detected R

b2 SWR Software reset detect flag 0: Not detected

1: Detected R

b3 WDR Watchdog timer reset detect flag 0: Not detected

1: Detected R

b4 — Reserved bits When read, the content is undefi ned. R

b5 —

b6 —

b7 — Reserved bit Set to 0. R/W

R8C/34C Group 5. Resets

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 30 of 723

5.1.3 Option Function Select Register (OFS)

Notes:

1. The OFS register is allocated in the flash memory, not in the SFRs. Set appropriate values as ROM data by a

program.

Do not write addi tions to the OFS regi ster. If the block includi ng the OFS register is er ased, the OFS register is

set to FFh.

When blank products are shipped, the OFS reg ister is set to FFh. It is set to the written value after written by the

user.

When factory-programming products are shi pped, th e valu e o f the OF S regi ster is th e val ue pr ogrammed by the

user.

2. The same level of the vo ltage detection 0 leve l selected by bi ts VDSEL0 and VDESL1 is se t in both functi ons of

voltage monitor 0 reset and power-on reset.

3. To use power-on reset and voltage monitor 0 reset, set the LVDAS bit to 0 (voltage monitor 0 reset enabled after

reset).

For a setting example of the OFS register, ref e r to 13.3.1 Setting Example of Option Function Select Area.

LVDAS Bit (Voltage Detection 0 Circuit Start Bit)

The Vdet0 voltage to be monitored by the voltage detection 0 circuit is selected by bits VDSEL0 and VDSEL1.

Address 0FFFFh

Bitb7 b6b5b4b3b2b1b0

Symbol CSPROINI LVDAS VDSEL1 VDSEL0 ROMCP1 ROMCR — WDTON

After Reset User Setting Value (1)

Bit Symbol Bit Name Function R/W

b0 WDTON Watchdog timer start select bit 0: Watchdog timer automatically starts after reset

1: Watchdog timer is stopped after reset R/W

b1 — Reserved bit Set to 1. R/W

b2 ROMCR ROM code protect disable bit 0: ROM code protect disabled

1: ROMCP1 bit enabled R/W

b3 ROMCP1 ROM code protect bi t 0: ROM code protect enabled

1: ROM code protect disabled R/W

b4 VDSEL0 Voltage detection 0 level select bit (2) b5 b4

0 0: 3.80 V selected (Vdet0_3)

0 1: 2.85 V selected (Vdet0_2)

1 0: 2.35 V selected (Vdet0_1)

1 1: 1.90 V selected (Vdet0_0)

R/W

b5 VDSEL1 R/W

b6 LVDAS Voltage detection 0 circuit start bit (3) 0: Voltage monitor 0 reset enabled after reset

1: Voltage monitor 0 reset disabled after reset R/W

b7 CSPROINI Count source protection mode

after reset select bit 0: Count source protect mode enabled after reset

1: Count source protect mode disabled after reset R/W

R8C/34C Group 5. Resets

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 31 of 723

5.1.4 Option Function Select Register 2 (OFS2)

Note:

1. The OFS2 register is allocated in the flash memory, not in the SFRs. Set appropriate values as ROM data by a

program.

Do not write additions to the OF S2 register. If the block including the OFS2 register is erased, the OFS2 register

is set to FFh.

When blank products are shipped, the OFS2 register is set to FFh. It is set to the written value after written by the

user.

When factory-programming products are shipped, the value of the OFS2 register is the value programmed by the

user.

For a setting example of the OFS2 register, refer to 13.3.1 Setting Example of Option Function Select Area.

Bits WDTRCS0 and WDTRCS1

(Watchdog Timer Refresh Acknowledgement Period Set Bit)

Assuming that the period from when the watchdog timer starts counting until it underflows is 100%, the refresh

acknowledgement period for the watchdog ti mer can be selected.

For details, refer to 14.3.1.1 Refresh Acknowledgement Period.

Address 0FFDBh

Bitb7b6b5b4b3b2b1b0

Symbol — — — — WDTRCS1 WDTRCS0 WDTUFS1 WDTUFS0

After Reset User Setting Value (1)

Bit Symbol Bit Name Function R/W

b0 WDTUFS0 Watchdog timer un derflow period set bit b1 b0

0 0: 03FFh

0 1: 0FFFh

1 0: 1FFFh

1 1: 3FFFh

R/W

b1 WDTUFS1 R/W

b2 WDTRCS0 Watchdog timer refresh acknowledgement peri od

set bit b3 b2

0 0: 25%

0 1: 50%

1 0: 75%

1 1: 100%

R/W

b3 WDTRCS1 R/W

b4 — Reserved bits Set to 1. R/W

b5 —

b6 —

b7 —

R8C/34C Group 5. Resets

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 32 of 723

5.2 Hardware Reset

A reset is applied using the RESET pin. When an “L” signal is applied to the RESET pin while the suppl y voltage

meets the recommended operating co nditio ns, pin s, CPU, and SFRs ar e all reset (refer to Table 5.2 Pin Functi ons

while RESET Pin Level is “L”, Figure 5.2 CPU Register Status after Reset, and Table 4.1 to Table 4.12 SFR

Information).

When the input level applied to the RESET pin changes from “L” to “H”, a program is executed beginning with the

address indicated by the reset vector. After reset, the low-speed on-chip oscillator clock with no division is

automatically selected as the CPU clock.

Refer to 4. Special Function Registers (SFRs) for the states of the SFRs after reset.

The internal RAM is not reset. If the RESET pin is pulled “L” while writing to the internal RAM is in progress, the

contents of internal RAM will be undefined.

Figure 5.4 shows a n Example of Hardware Reset Circuit and O peration and Figure 5.5 shows an Example of

Hardware Reset Circuit (Usage Example of External Supply Voltage Detection Circuit) and Operation.

5.2.1 When Power Supply is Stable

(1) Apply “L” to the RESET pin.

(2) Wait for 10 µs.

(3) Apply “H” to the RESET pin.

5.2.2 Power On

(1) Apply “L” to the RESET pin.

(2) Let the supply voltage increase until it meets th e recommend e d operating conditions.

(3) Wait for td(P-R) or more to allow the internal power supply to stabilize (refer to 33. Electrical

Characteristics).

(4) Wait for 10 µs.

(5) Apply “H” to the RESET pin.

R8C/34C Group 5. Resets

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 33 of 723

Figure 5.4 Example of Hardware Reset Circuit and Operation

Figure 5.5 Ex a m p le of Hard wa re Re se t Circuit (Usage Example of Exte rn al Suppl y Vol tag e

Detection Circuit) and Operation

RESET

VCC VCC

RESET

1.8 V

0 V 0.2 VCC or below

td(P-R) + 10 µs or more

0 V

Note:

1. Refer to 33. Electrical Characteristics.

RESET VCC VCC

RESET

1.8 V

0 V

5 V

Example when

VCC = 5 V

Supply vo ltage

detection circuit

Note:

1. Refer to 33. Elect rical Charac te rist ics.

td(P-R) + 10 µs or more

R8C/34C Group 5. Resets

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 34 of 723

5.3 Power-On Reset Function

When the RESET pin is connected to the VCC pin via a pull-up resistor, and the VCC pin voltage level rises, the

power-on reset function is enabled and the MCU resets its pins, CPU, and SFR. When a capacitor is connected to

the RESET pin, too, always keep the voltage to the RESET pin 0.8VCC or more.

When the input voltage to the VCC pin reaches the Vdet0 level or above, the low-speed on-chip oscillator clock

starts counting. When the low-speed on-chip oscillator clock count reaches 32, the internal reset signal is held “H”

and the MCU enters the reset sequence (refer to Figure 5.3). The low-speed on-chip oscillator clock with no

division is automati cally selected as the CPU clock after reset.

Refer to 4. Special Function Registers (SFRs) for the states of the SFR after power-on reset.

To use the power-on reset function, enable voltage monitor 0 reset by setting the LVDAS bit in the OFS regi st er to

Figure 5.6 shows an Example of Power-On Reset Circuit and Operation.

Figure 5.6 Example of Power-On Reset Circuit and Operation

RESET

VCC

4.7 kΩ

(reference)

Notes:

1. Vdet0 indicat es the voltage detectio n level of the voltage detecti on 0 circuit. Refer to

6. Voltage Detecti on Circuit for details.

2. tw(por) indicates the duration the external pow er VCC must be held below the valid

voltage (0.5 V) to enable a power-on reset. When t urni ng on the power after it falls

with volt age monitor 0 reset di sabled, maintain tw(por) for 1 ms or more.

3. To use the power-on reset functi on, enable voltage monitor 0 reset by setting the

LVDAS bit in the OFS register to 0.

Vdet0 (1)

0.5V

Internal

reset signal

tw(por) (2)

fOCO-S × 32

External

Power VCC

R8C/34C Group 5. Resets

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 35 of 723

5.4 Voltage Monitor 0 Reset

A reset is applied using the on-chip voltage detection 0 circuit. The voltage detection 0 circuit monitors the input

voltage to the VCC pin. The vo ltage to m onitor is Vd et0. To use voltage m onitor 0 reset , set the LV DAS bit in the

OFS register to 0 (voltage monitor 0 reset enabled after reset). The Vdet0 voltage detection level can be changed by

the settings of bits VDSEL0 to VDSEL1 in th e OFS register.

When the input voltage to the VCC pin reaches the Vdet0 level or below, the pins, CPU, and SFR are reset.

When the input voltage to the VCC pin reaches the Vdet0 level or above, the low-speed on-chip oscillator clock

start counting. When the low-speed on-chip oscillator clock count reaches 32, the internal reset signal is held “H”

and the MCU enters the reset sequence (refer to Figure 5.3). The low-speed on-chip oscillator clock with no

division is automati cally selected as the CPU clock after reset.

To use the power-on reset function, enable voltage monitor 0 reset by setting the LVDAS bit in the OFS regi st er to

Bits VDSEL0 to VDSEL1 and LVDAS cannot be changed by a program. To set these bits, write values to b4 to b6

of address 0FFFFh using a flash programmer.

Refer to 5.1.3 Option Function Select Register (OFS) for details of the OFS register.

Refer to 4. Special Function Registers (SFRs) for the status of the SFR after voltage monitor 0 reset.

The internal RAM is not reset. When the input voltage to the VCC pin reaches the Vdet0 level or below while

writing to the internal RAM is in progress, the contents of internal RAM are undefined.

Refer to 6. Voltage Detection Circuit for details of voltage monitor 0 reset.

Figure 5.7 shows an Example of Voltag e Monito r 0 Reset Circuit and Operation.

Figure 5.7 Example of Voltage Monitor 0 Reset Circuit and Operation

Internal reset signal

Voltage detection 0

circuit response time

fOCO-S × 32

Vdet0

0.5V

Notes:

1. Vdet0 indicates the voltage det ection level of the voltage detection 0 circui t. Refer to 6. Voltage

Detection Circuit for details.

2. To use the power-on reset function, enabl e voltage monitor 0 reset by setting the LVDAS bit in

the OFS register to 0.

External

Power VCC

R8C/34C Group 5. Resets

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 36 of 723

5.5 Watchdog Timer Reset

When the PM12 bit in the PM1 register is set to 1 (reset when watchdog timer underflows), the MCU resets its pins,

CPU, and SFR if the watchd og timer underflows. Then t he program beginning with t he address indicated by the

reset vector is executed. After reset, the low-speed on-chip oscillator clock with no division is automatically

selected as the CPU clock.

Refer to 4. Special Function Registers (SFRs) for the states of the SFRs after watchdog timer reset.

The internal RAM is not reset. When the watchdog timer underflows while writing to the internal RAM is in

progress, the contents of internal RAM are undefined.

The underflow peri od and refresh acknowledge period for th e watchdog timer can be set by bits WDTUFS0 to

WDTUFS1 and bits WDTRCS0 to WDTRCS1 in the OFS2 register, respectively.

Refer to 14. Watchdog Timer for details of the watchdog timer.

5.6 Software Reset

When the PM03 bit in the PM0 register is set to 1 (MCU reset), the MCU resets its pins, CPU, and SFR. The

program beginning with the address indicated by the reset vector is executed. After reset, the low-speed on-chip

oscillator clock with no division is automatically selected for the CPU clock.

Refer to 4. Special Function Registers (SFRs) for the states of the SFRs after software reset.

The internal RAM is not reset.

R8C/34C Group 5. Resets

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 37 of 723

5.7 Cold Start-Up/Warm Start-Up Determination Function

The cold start-up/warm start-up determ ination function uses the C WR bit in the R STFR register to determine cold

start-up (reset process) at power-on and warm start-up (reset process) when a reset occurred during operation.

The CWR bit is set to 0 (cold start-up) at power-on and also set to 0 at a voltage monitor 0 reset. If 1 is written to

the CWR bit by a program, it is set to 1. This bit remains unchanged at a hardware reset, software reset, or

watchdog timer reset.

The cold start-up/warm stat-up determination function uses voltage monitor 0 reset.

Figure 5.8 shows an Operating Examp le of Cold Start-Up/Warm Star t- Up Function

Figure 5.8 Operating Example of Cold Start-Up/Warm Start-Up Function

5.8 Reset Source Determination Function

The RSTFR register can be used to detect whether a hardware reset, software reset, or watchdog timer reset has

occurred.

If a hardware reset occurs, the HWR bit is set to 1 (detected). If a software reset occurs, the SWR bit is set to 1

(detected). If a watchdog timer reset occurs, the WDR bit is set to 1 (detected).

Set to 1 by

a program.

Vdet0

CWR bit in RSTFR register

Voltage monitor 0 reset

VCC

Set to 1 by

a program.

R8C/34C Group 6. Voltage Detection Circuit

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 38 of 723

6. Voltage Detection Circuit

The voltage detection circuit monitors the voltage input to th e VCC pin. This circuit can be used to monitor the VCC

input voltage by a program.

6.1 Overview

The detection voltage of voltage detection 0 can be selected among four levels using the OFS register.

The detection voltage of voltage detection 1 can be selected among 16 levels using the VD1LS register.

The voltage monitor 0 reset, and voltage monitor 1 interrupt and voltage monitor 2 interrupt can also be used.

Table 6.1 Voltage Detection Circuit Specifications

Item Voltage Monitor 0 Voltage Monitor 1 Voltage Monitor 2

VCC

monitor Voltage to

monitor Vdet0 Vdet1 Vdet2

Detection

target Whether passing through

Vdet0 by falling Whether passing through

Vdet1 by rising or falling Whether passing through

Vdet2 by rising or falling

Detection

voltage Selectable among

4 levels using the OFS

Selectable among

16 levels using the VD1LS

The fixed level

Monitor None The VW1C3 bit in

the VW1C register The VCA13 bit in

theVCA1register

Whether VCC is higher or

lower than Vdet1 Whether VCC is higher or

lower than Vdet2

Process at

voltage

detection

Reset Voltage monitor 0 reset None None

Reset at Vdet0 > VCC;

CPU operation restarts

at VCC > Vdet0

Interrupts None Voltage monitor 1 interrupt Vo ltage monitor 2 interrupt

Non-maskable or maskable

selectable Non-maskable or maska ble

selectable

Interrupt request at:

Vdet1 > VCC

and/or

VCC > Vdet1

Interrupt request at:

Vdet2 > VCC

and/or

VCC > Vdet2

Digital filter Switching

enable/disable No digital filter function Supported Supported

Sampling

time — (fOCO-S divided by n) × 2

n: 1, 2, 4, and 8 (fOCO-S divided by n) × 2

n: 1, 2, 4, and 8

R8C/34C Group 6. Voltage Detection Circuit

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 39 of 723

Figure 6.1 Voltage Detection Circuit Block Diagram

VCA13: Bit in VCA1 register

VCA25, VCA26, VCA27: Bits in VCA2 regi ster

VW1C3: Bit in VW1C register

VD1S0 to VD1S3: Bits in VD1LS register

VDSEL0, VDSEL1: Bits in OFS register

VCA27

≥ Vdet0

VCA25

VCA26

VCC

Volt age detection 1 signal

VCA13 bit

Voltage detection 0 signal

Voltage detection 2 signal

≥ Vdet1

Internal

reference

voltage VCA1 register

VW1C 3 bit

VW1C register

Level

Selection

Circuit

(16 levels)

VD1S3 to VD1S0

≥ Vdet2

Level

Selection

Circuit

(4 levels)

VDSEL1 to VDSEL0

R8C/34C Group 6. Voltage Detection Circuit

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 40 of 723

Figure 6.2 B lock Diagram of Voltage Monitor 0 Reset Generation Circuit

Figure 6.3 B lock Diagram of Voltage Monitor 1 Interrupt Generation Circuit

Voltage de tec t i on 0 circu it

VCA25

VCC

Internal reference voltage

When VCA25 bit is set to 0 (disabled),

voltage detecti on 0 si gnal is dri ven hi gh.

Voltage

detection 0

signal

VW0C0

Voltage monitor 0 reset generation circuit

VW0C0: Bit in VW0C register

VCA25: Bit in VCA2 register

VDSEL0, VDSEL1: Bits in OFS regist er

Voltage monitor 0

reset signal

Level selectio n

VDSEL1

to VDSEL0

1/2 1/2 1/2

Voltage detectio n 1 circuit

VCA26

VW1C3

When VCA26 bit is set to 0 (disabled),

voltage detection 1 signal is driven high.

Voltage

detection 1

signal

fOCO-S

VW1F1 to VW1F0

= 00b

= 01b

= 10b

= 11b VW1C2 bit is set to 0 (not detected) by writing 0 by a program.

When VCA26 bit is set to 0 (voltage detection 1 circuit disabled),

VW1C2 bit is set to 0.

VW1C2

IRQ1SEL Maskable

interrupt signal

Voltage monitor 1 int errupt generation circuit

VW1C0 to VW1C3, VW1F0, VW1F1, VW1C7: Bits in VW1C register

VCA26: Bits in VCA2 register

VD1S0 to VD1S3: Bits in VD1LS register

COMPSEL, IRQ1SEL: Bits in CMPA register

VCAC1: Bit in VCAC register

COMPSEL

VD1S3

to VD1S0

VCC VW1C1 = 0

VW1C1 = 1

Digital filter

Edge

selection

circuit

VW1C0

VCAC1

VW1C7

Internal reference voltage

Level

selection

Non-maskable

interrupt signal

Voltage monitor 1

interrupt signal

Watchdog timer

interrupt signal

R8C/34C Group 6. Voltage Detection Circuit

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 41 of 723

Figure 6.4 B lock Diagram of Voltage Monitor 2 Interrupt Generation Circuit

1/2 1/2 1/2

Voltage detection 2 circuit

VCA27

VCA13

When VCA27 bit is set to 0 (disabled),

voltage detection 2 signal is driven high.

Voltage

detection 2

signal

fOCO-S

VW2F1 to VW2F0

= 00b

= 01b

= 10b

= 11b VW2C2 bit is set to 0 (not detected) by writing 0 by a program.

When VCA27 bit is set to 0 (voltage detection 2 circuit disabled),

VW2C2 bit is set to 0.

VW2C2

VW2C3

Watchdog timer block

Watchdog timer underflow signal

VW2C3 bit is set to 0 (not detected)

by writing 0 by a program.

COMPSEL

IRQ2SEL Maskable

interrupt signal

Non-maskable

interrupt signal

Voltage monitor 2

interrupt signal

Watchdog timer

interrupt signal

Voltag e mo ni tor 2 interr upt generation circui t

VW2C0 to VW2C3, VW2F0, VW2F1, VW2C7: Bits in VW2C

VCA13: Bit in VCA1 register

VCA27: Bits in VCA2 r e gister

COMPSEL, IRQ2SEL: Bits in CMPA register

VCAC2: Bit in VCAC register

VW2C1 = 0

VW2C1 = 1

Digital filter

Edge

selection

circuit

VW2C0

VCAC2

VW2C7

Internal reference voltage

VCC Level

change

R8C/34C Group 6. Voltage Detection Circuit

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 42 of 723

6.2 Registers

6.2.1 Voltage Monitor Circuit Control Register (CMPA)

Notes:

1. When the VW1C0 bit in the VW1C register is set to 1 (enabled), do not set bits IRQ1SEL and COMPSEL

simultaneously (with one instruction).

2. When the VW2C0 bit in the VW2C register is set to 1 (enabled), do not set bits IRQ2SEL and COMPSEL

simultaneously (with one instruction).

Address 0030h

Bitb7b6b5b4b3b2b1b0

Symbol COMPSEL — IRQ2SEL IRQ1SEL — — — —

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 — Reserved bits Set to 0. R/W

b1 —

b2 —

b3 —

b4 IRQ1SEL Voltage monitor 1 interrupt type

select bit (1) 0: Non-maskable interrupt

1: Maskable interrupt R/W

b5 IRQ2SEL Voltage monitor 2 interrupt type

select bit (2) 0: Non-maskable interrupt

1: Maskable interrupt R/W

b6 — Reserved bit Set to 0. R/W

b7 COMPSEL Voltage monitor interrupt type

selection enable bit (1 , 2) 0: Bits IRQ1SEL and IRQ2SEL disabled

1: Bits IRQ1SEL and IRQ2SEL enabled R/W

R8C/34C Group 6. Voltage Detection Circuit

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 43 of 723

6.2.2 Voltage Monitor Circuit Edge Select Register (VCAC)

Notes:

1. When the VCAC1 bit is set to 0 (one edg e), the VW1C7 bit in th e VW1C register is enabl ed. Set the VW1C7 bit

after setting the VCAC1 bit to 0.

2. When the VCAC2 bit is set to 0 (one edg e), the VW2C7 bit in th e VW2C register is enabl ed. Set the VW2C7 bit

after setting the VCAC2 bit to 0.

6.2.3 Voltage Detect Register 1 (VCA1)

Note:

1. When the VCA27 bit in the VCA2 register is set to 1 (voltage detection 2 circuit enabled), the VCA13 bit is

enabled.

When the VCA27 bi t in th e VC A2 re gi st er i s set to 0 (vol tage detection 2 circuit disabled), the VCA13 bit is set to

1 (VCC ≥ Vdet2).

Address 0031h

Bitb7b6b5b4b3b2b1b0

Symbol — — — — — VCAC2 VCAC1 —

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b1 VCAC1 Voltage monitor 1 circuit edge select bit (1) 0: One edge

1: Both edges R/W

b2 VCAC2 Voltage monitor 2 circuit edge select bit (2) 0: One edge

1: Both edges R/W

b3 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b4 —

b5 —

b6 —

b7 —

Address 0033h

Bitb7b6b5b4b3b2b1b0

Symbol————VCA13———

After Reset00001000

Bit Symbol Bit Name Function R/W

b0 — Reserved bits Set to 0. R/W

b1 —

b2 —

b3 VCA13 Voltage detection 2 signal monitor flag (1) 0: VCC < Vdet2

1: VCC ≥ Vdet2

or voltage detection 2 circuit disabled

b4 — Reserved bits Set to 0. R/W

b5 —

b6 —

b7 —

R8C/34C Group 6. Voltage Detection Circuit

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 44 of 723

6.2.4 Voltage Detect Register 2 (VCA2)

Notes:

1. Use the VCA20 bit only whe n the MCU enters wait mode. To set the VCA20 bi t, follow the procedure shown in

Figure 9.3 Procedure for Reducing Internal Power Consumption Using VCA20 bit.

2. When the VCA20 bit is set to 1 (low consumption enabled), do not set the CM10 bit in the CM1 register to 1 (stop

mode).

3. When writing to the VCA25 bit, set a value after reset.

4. To use the voltage detection 1 interrupt or the VW1C3 bit in the VW1C register, set the VCA26 bit to 1.

After the VCA26 bit is set to 1 from 0, allow td(E-A) to elapse before the voltage detection 1 circuit starts

operation.

5. To use the voltage detection 2 interrupt or the VCA13 bit in the VCA1 register, set the VCA27 bit to 1.

After the VCA27 bit is set to 1 from 0, allow td(E-A) to elapse before the voltage detection 2 circuit starts

operation.

Set the PRC3 bit in the PRCR register to 1 (write enabled) before rewriting the VCA2 register.

Address 0034h

Bitb7b6b5b4b3b2b1b0

Symbol VCA27 VCA26 VCA25 — — — — VCA20

After Reset00000000

The above applies when the LVDAS bit in the OFS registe r is set to 1.

After Reset00100000

The above applies when the LVDAS bit in the OFS registe r is set to 0.

Bit Symbol Bit Name Function R/W

b0 VCA20 Internal power low consumption

enable bit (1) 0: Low consumption disabled

1: Low consumption enabled (2) R/W

b1 — Reserved bits Set to 0. R/W

b2 —

b3 —

b4 —

b5 VCA25 Voltage detection 0 enable bit (3) 0: Voltage detection 0 circuit disabled

1: Voltage detection 0 circuit enabled R/W

b6 VCA26 Voltage detection 1 enable bit (4) 0: Voltage detection 1 circuit disabled

1: Voltage detection 1 circuit enabled R/W

b7 VCA27 Voltage detection 2 enable bit (5) 0: Voltage detection 2 circuit disabled

1: Voltage detection 2 circuit enabled R/W

R8C/34C Group 6. Voltage Detection Circuit

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 45 of 723

6.2.5 Voltage Detection 1 Level Select Register (VD1LS)

Set the PRC3 bit in the PRCR register to 1 (write enabled) before rewriting the VD1LS register.

Address 0036h

Bitb7b6b5b4b3b2b1b0

Symbol————VD1S3VD1S2VD1S1VD1S0

After Reset00000111

Bit Symbol Bit Name Function R/W

b0 VD1S0 Vol tage detection 1 level select bit

(Reference voltage when the voltage falls) b3 b2 b1 b0

0 0 0 0: 2.20 V (Vdet1_0)

0 0 0 1: 2.35 V (Vdet1_1)

0 0 1 0: 2.50 V (Vdet1_2)

0 0 1 1: 2.65 V (Vdet1_3)

0 1 0 0: 2.80 V (Vdet1_4)

0 1 0 1: 2.95 V (Vdet1_5)

0 1 1 0: 3.10 V (Vdet1_6)

0 1 1 1: 3.25 V (Vdet1_7)

1 0 0 0: 3.40 V (Vdet1_8)

1 0 0 1: 3.55 V (Vdet1_9)

1 0 1 0: 3.70 V (Vdet1_A)

1 0 1 1: 3.85 V (Vdet1_B)

1 1 0 0: 4.00 V (Vdet1_C)

1 1 0 1: 4.15 V (Vdet1_D)

1 1 1 0: 4.30 V (Vdet1_E)

1 1 1 1: 4.45 V (Vdet1_F)

R/W

b1 VD1S1 R/W

b2 VD1S2 R/W

b3 VD1S3 R/W

b4 — Reserved bits Set to 0. R/W

b5 —

b6 —

b7 —

R8C/34C Group 6. Voltage Detection Circuit

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 46 of 723

6.2.6 Voltage Monitor 0 Circuit Control Register (VW0C)

Note:

1. The VW0C0 bit is enabled when the VCA25 bit in the VCA2 register is set to 1 (voltage detection 0 circuit

enabled). When writing to the VW0C0 bit, set a value after reset.

Set the PRC3 bit in the PRCR register to 1 (write enabled) before writing the VW0C register.

Address 0038h

Bitb7b6b5b4b3b2b1b0

Symbol———————VW0C0

After Reset1100X010

The above applies when the LVDAS bit in the OFS registe r is set to 1.

After Reset1100X011

The above applies when the LVDAS bit in the OFS registe r is set to 0.

Bit Symbol Bit Name Function R/W

b0 VW0C0 Voltage monitor 0 reset enable bit (1) 0: Disabled

1: Enabled R/W

b1 — Reserved bit Set to 1. R/W

b2 — Reserved bit Set to 0. R/W

b3 — Reserved bit When read, the content is undefined. R

b4 — Reserved bits Set to 0. R/W

b5 —

b6 — Reserved bits Set to 1. R/W

b7 —

R8C/34C Group 6. Voltage Detection Circuit

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 47 of 723

6.2.7 Voltage Monitor 1 Circuit Control Register (VW1C)

Notes:

1. The VW1C0 is enabled when the VCA26 bit in the VCA2 register is set to 1 (voltage detection 1 circuit enabled).

Set the VW1C0 bit to 0 (disabled) when the VCA26 bit is set to 0 (voltage detection 1 circuit disabled).

To set the VW0C0 bit to 1 (enabled), follow the procedure shown in Table 6.2 Procedure for Setting Bits

Associated with Voltage Monitor 1 Interrupt.

2. When using the digital filter (whil e the VW1C1 bi t is 0), set th e CM14 bit i n the CM1 registe r to 0 (low-speed on-

chip oscillator on).

To use the voltage monitor 1 interrupt to exit stop mode, set the VW1C1 bit in the VW1C register to 1 (digital filter

disabled).

3. Bits VW1C2 and VW1C3 are enabled when the VCA26 bit in the VCA2 regi ster is set to 1 (voltage detection 1

circuit enabled).

4. Set the VW1C2 bit to 0 by a program. When 0 is written by a program, this bit is set to 0 (and remains unchanged

even if 1 is written to it).

5. The VW1C7 bit is enabled when the VCAC1 bit in the VCAC register is set to 0 (one edge). After setting the

VCAC1 bit to 0, set the VW1C7 bit.

6. When the VW1C0 bit is set to 1 (enabled), do not set the VW1C1 bit and bits VW1F1 and VW1F0 simultaneously

(with one instruction).

Set the PRC3 bit in the PRCR register to 1 (write enabled) before writing the VW1C register.

Rewriting the VW1C register may set the VW1C2 bit to 1. Set the VW1C2 bit to 0 after rewriting the VW1C

Address 0039h

Bitb7b6b5b4b3b2b1b0

Symbol VW1C7 — VW1F1 VW1F0 VW1C3 VW1C2 VW1C1 VW1C0

After Reset10001010

Bit Symbol Bit Name Function R/W

b0 VW1C0 Voltage monitor 1 interrupt enable bit (1) 0: Disabled

1: Enabled R/W

b1 VW1C1 Voltage monitor 1 digital filter

disable mode select bit (2, 6) 0: Digital filter enabled mode

(digital filter circuit enabled)

1: Digital filter disable mode

(digital filter circuit disabled)

R/W

b2 VW1C2 Voltage change detection flag (3, 4) 0: Not detected

1: Vdet1 passing detected R/W

b3 VW1C3 Voltage detection 1 signal mo nitor flag (3) 0: VCC < Vdet1

1: VCC ≥ Vdet1

or voltage detection 1 circuit disabled

b4 VW1F0 Sampling clock select bit (6) b5 b4

0 0: fOCO-S divided by 1

0 1: fOCO-S divided by 2

1 0: fOCO-S divided by 4

1 1: fOCO-S divided by 8

R/W

b5 VW1F1 R/W

b6 — Reserved bit Set to 0. R/W

b7 VW1C7 Voltage monitor 1 int err up t

generation condition select bit (5) 0: When VCC reach es Vdet1 or above.

1: When VCC reaches Vdet1 or below. R/W

R8C/34C Group 6. Voltage Detection Circuit

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 48 of 723

6.2.8 Voltage Monitor 2 Circuit Control Register (VW2C)

Notes:

1. The VW2C0 is enabled when the VCA27 bit in the VCA2 register is set to 1 (voltage detection 2 circuit enabled).

Set the VW2C0 bit to 0 (disabled) when the VCA27 bit is set to 0 (voltage detection 2 circuit disabled).

To set the VW2C0 bit to 1 (enabled), follow the procedure shown in Table 6.3 Procedure for Setting Bits

Associated with Voltage Monitor 2 Interrupt.

2. When using the digital filter (whil e the VW2C1 bi t is 0), set th e CM14 bit i n the CM1 registe r to 0 (low-speed on-

chip oscillator on).

To use the voltage monitor 2 interrupt to exit stop mode, set the VW2C1 bit in the VW2C register to 1 (digital filter

disabled).

3. The VW2C2 bit is enabled when the VCA27 bit in the VCA2 register is set to 1 (voltage detection 2 circuit

enabled).

4. Set this bit to 0 by a program. When 0 is written by a program, this bit is set to 0 (and remains unchanged even if

1 is written to it).

5. The VW2C7 bit is enabled when the VCAC2 bit in the VCAC register is set to 0 (one edge). After setting the

VCAC2 bit to 0, set the VW2C7 bit.

6. When the VW2C0 bit is set to 1 (enabled), do not set the VW2C1 bit and bits VW2F1 and VW2F0 simultaneously

(with one instruction).

Set the PRC3 bit in the PRCR register to 1 (write enabled) before rewriting the VW2C register.

Rewriting the VW2C register may set the VW2C2 bit to 1. After rewriting this register, set the VW2C2 bit to 0.

Address 003Ah

Bitb7b6b5b4b3b2b1b0

Symbol VW2C7 — VW2F1 VW2F0 VW2C3 VW2C2 VW2C1 VW2C0

After Reset10000010

Bit Symbol Bit Name Function R/W

b0 VW2C0 Voltage monitor 2 interrupt enable bit (1) 0: Disabled

1: Enabled R/W

b1 VW2C1 Voltage monitor 2 digital filter

disable mode select bit (2, 6) 0: Digital filter enable mode

(digital filter circuit enabled)

1: Digital filter disable mode

(digital filter circuit disabled)

R/W

b2 VW2C2 Voltage change detection flag (3, 4) 0: Not detected

1: Vdet2 passing detected R/W

b3 VW2C3 WDT detection monitor flag (4) 0: Not detected

1: Detected R/W

b4 VW2F0 Sampling clock select bit (6) b5 b4

0 0: fOCO-S divided by 1

0 1: fOCO-S divided by 2

1 0: fOCO-S divided by 4

1 1: fOCO-S divided by 8

R/W

b5 VW2F1 R/W

b6 — Reserved bit Set to 0. R/W

b7 VW2C7 Voltage monitor 2 interrupt

generation condition select bit (5) 0: When VCC reaches Vdet2 or above.

1: When VCC reaches Vdet2 or below. R/W

R8C/34C Group 6. Voltage Detection Circuit

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 49 of 723

6.2.9 Option Function Select Register (OFS)

Notes:

1. The OFS register is allocated in the flash memory, not in the SFRs. Set appropriate values as ROM data by a

program.

Do not write addi tions to the OFS regi ster. If the block includi ng the OFS register is er ased, the OFS register is

set to FFh.

When blank products are shipped, the OFS reg ister is set to FFh. It is set to the written value after written by the

user.

When factory-programming products are shi pped, th e valu e o f the OF S regi ster is th e val ue pr ogrammed by the

user.

2. The same level of the vo ltage detection 0 leve l selected by bi ts VDSEL0 and VDESL1 is se t in both functi ons of

voltage monitor 0 reset and power-on reset.

3. To use power-on reset and voltage monitor 0 reset, set the LVDAS bit to 0 (voltage monitor 0 reset enabled after

reset).

For a setting example of the OFS register, ref e r to 13.3.1 Setting Example of Option Function Select Area.

LVDAS Bit (Voltage Detection 0 Circuit Start Bit)

The Vdet0 voltage to be monitored by the voltage detection 0 circuit is selected by bits VDSEL0 and VDSEL1.

Address 0FFFFh

Bitb7 b6b5b4b3b2b1b0

Symbol CSPROINI LVDAS VDSEL1 VDSEL0 ROMCP1 ROMCR — WDTON

After Reset User Setting Value (1)

Bit Symbol Bit Name Function R/W

b0 WDTON Watchdog timer start select bit 0: Watchdog timer automatically starts after reset

1: Watchdog timer is stopped after reset R/W

b1 — Reserved bit Set to 1. R/W

b2 ROMCR ROM code protect disable bit 0: ROM code protect disabled

1: ROMCP1 bit enabled R/W

b3 ROMCP1 ROM code protect bi t 0: ROM code protect enabled

1: ROM code protect disabled R/W

b4 VDSEL0 Voltage detection 0 level select bit (2) b5 b4

0 0: 3.80 V selected (Vdet0_3)

0 1: 2.85 V selected (Vdet0_2)

1 0: 2.35 V selected (Vdet0_1)

1 1: 1.90 V selected (Vdet0_0)

R/W

b5 VDSEL1 R/W

b6 LVDAS Voltage detection 0 circuit start bit (3) 0: Voltage monitor 0 reset enabled after reset

1: Voltage monitor 0 reset disabled after reset R/W

b7 CSPROINI Count source protection mode

after reset select bit 0: Count source protect mode enabled after reset

1: Count source protect mode disabled after reset R/W

R8C/34C Group 6. Voltage Detection Circuit

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 50 of 723

6.3 VCC Input Voltage

6.3.1 Monitoring Vdet0

Vdet0 cannot be monitored.

6.3.2 Monitoring Vdet1

Once the following settings are made, the comparison result of voltage monitor 1 can be monitored by the

VW1C3 bit in the VW1C register after td(E-A) has elapsed (refer to 33. Electrical Characteristics).

(1) Set bits VD1S3 to VD1S0 in the VD1LS register (voltage detection 1 detection voltage).

(2) Set the VCA26 bit in the VCA2 register to 1 (voltage detectio n 1 circuit enabled).

6.3.3 Monitoring Vdet2

Once the following settings are made, the comparison result of voltage monitor 2 can be monitored by the

VCA13 bit in the VCA1 register after td(E-A) has elapsed (r efer to 33. Electrical Characteristics).

• Set the VCA27 bit in the VCA2 register to 1 (voltage detection 2 circuit enabled).

R8C/34C Group 6. Voltage Detection Circuit

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 51 of 723

6.4 Voltage Monitor 0 Reset

To use voltage monitor 0 reset, set the LVDAS bit in the OFS register to 0 (voltage monitor 0 reset enabled after

reset).

Figure 6.5 shows an Operating Ex ample of Voltage Monitor 0 Reset.

Figure 6.5 Operating Example of Voltage Monitor 0 Reset

Vdet0

VCC

When the internal reset signal is driven low, the pins, CPU, and SFRs are initialized.

When the internal reset signal level changes from low to high,

a program is executed beginning with the address indicated by the reset vector.

Refer to 4. Special Function Registers (SFRs) for the states of the SFRs after reset.

Internal reset signal

fOCO-S × 32

R8C/34C Group 6. Voltage Detection Circuit

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 52 of 723

6.5 Voltage Monitor 1 Interrupt

Table 6.2 lists the Procedure for Setting Bits Associated with Voltage Monitor 1 Interrupt. Figure 6.6 shows an

Operating Example of Voltage Monitor 1 Interrupt.

To use the voltage monitor 1 interrupt to exit stop mode, set the VW1C1 bit in the VW1C register to 1 (digital filter

disabled).

Notes:

When the VW1C0 bit is set to 0, st eps 4 and 5 ca n be executed simultan eously (with one instruction) .

When the VW1C0 bit is set to 0, st eps 6 and 7 ca n be executed simultan eously (with one instruction) .

3. When making the setting while the voltage monitor 1 interrupt is disabled (the VW1C0 bit in the

VW1C register is 0 and the VCA26 b i t in th e VCA2 r eg ister is 0), no interr upt reque st is gene rated if

VCC < Vdet1 (or VCC > Vdet1) is detected before enabling the voltage monitor 1 interrupt in step

12. If VCC < Vdet1 (or VCC > Vdet1) is detected between step 10 and step 12, the VW1C2 bit is set

to 1. Read the VW1C2 bit after step 12. If this bit is read as 1, perform the processing to be executed

when the above state is detected.

Table 6.2 Procedure for Set ting Bits Associated with Voltage Monitor 1 Interrupt

Step When Using Digital Filter When Using No Digital Filter

1Select the voltage detection 1 detection voltage by bi ts VD1S3 to VD1S0 in the VD1LS

2 Set the VCA26 bit in the VCA2 register to 1 (voltage detection 1 circuit enabled).

3 Wait for td(E-A).

4 Set the COMPSEL bit in the CMPA register to 1.

5 (1) Select the interrupt type by the IRQ1SEL in the CMPA register.

6Select the sampling cl ock of the digital filter by

bits VW1F0 and VW1F1 in the VW1C register. Set the VW1C1 bit in the VW1C register to 1

(digital filter disabled).

7 (2) Set the VW1C1 bit in the VW1C register to 0

(digital filter enabled). −

8Select the interrupt request timing by the VCAC1 bit in the VCAC register and

the VW1C7 bit in the VW1C register.

9 Set the VW1C2 bit in the VW1C register to 0.

10 Set the CM14 bit in the CM1 register to 0

(low-speed on-chip oscillator on) −

11 Wait for 2 cycles of the sampling clock of

the digital filter − (No wait time required)

12 (3) Set the VW1C0 bit in the VW1C register to 1 (voltage monitor 1 interrupt enabled)

R8C/34C Group 6. Voltage Detection Circuit

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 53 of 723

Figure 6.6 Operating Example of Voltage Monitor 1 Interr upt

Vdet1

VW1C3 bit

VCC

The above applies when:

• VCA26 bit in VCA2 register = 1 (voltage detection 1 circuit enabled)

• VW1C0 bit in VW1C register = 1 (voltage monitor 1 interrupt enabled)

Note:

1. If voltage monitor 0 reset is not used, set the power supply to VCC ≥ 1.8 V.

1.8 V (1)

Sampling clock of

digital filter × 2 cy cl es

VW1C2 bit

VW1C1 bit is set to 1

(digital filter disabled),

VCAC1 bit is set to 0

(one edge),

and

VW1C7 bit is set to 0

(when VCC reaches Vdet1

or above)

VW1C1, VW1C2, VW1C3, VW 1C7: Bits in VW1C register

VCAC1: Bit in VCAC register

Sampling clock of

digital filter × 2 cycles

Set to 0 by a program.

Voltage monitor 1

interrupt request

Voltage monitor 1

interrupt request

Set to 0 when an interrupt request

is acknowledged.

VW1C2 bit

Voltage monitor 1

interrupt request

VW1C1 bit is set to 0

(digital filter enabled)

and

VCAC1 bit is set to 1

(both edges)

VW1C2 bit

Set to 0 when an interrupt request

is acknowledged.

Set to 0 by a program.

Voltage monitor 1

interrupt request

VW1C1 bit is set to 0

(digital filter enabled),

VCAC1 bit is set to 0

(one edge),

and

VW1C7 bit is set to 0

(when VCC reaches Vdet1

or above)

VW1C2 bit

Voltage monitor 1

interrupt request

VW1C1 bit is set to 0

(digital filter enabled),

VCAC1 bit is set to 0

(one edge),

and

VW1C7 bit is set to 1

(when VCC reaches Vdet1

or below)

Set to 0 by a program.

VW1C2 bit

Voltage monitor 1

interrupt request

VW1C1 bit is set to 1

(digital filter disabled)

and

VCAC1 bit is set to 1

(both edges)

Set to 0 by a program.

Set to 0 when an interrupt request

is acknowledged.

Set to 0 by a program.

Set to 0 when an interrupt request

is acknowledged.

Set to 0 by a program.

VW1C1 bit is set to 1

(digital filter disabled),

VCAC1 bit is set to 0

(one edge),

and

VW1C7 bit is set to 1

(when VCC reaches Vdet1

or below)

Set to 0 when an interrupt request

is acknowledged.

Set to 0 when an interrupt request

is acknowledged.

R8C/34C Group 6. Voltage Detection Circuit

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 54 of 723

6.6 Voltage Monitor 2 Interrupt

Table 6.3 lists the Procedure for Setting Bits Associated with Voltage Monitor 2 Interrupt. Figure 6.7 shows an

Operating Example of Voltage Monitor 2 Interrupt.

To use the voltage monitor 2 interrupt to exit stop mode, set the VW2C1 bit in the VW2C register to 1 (digital filter

disabled).

Notes:

When the VW2C0 bit is set to 0, st eps 3 and 4 ca n be executed simultan eously (with one instruction) .

When the VW2C0 bit is set to 0, st eps 5 and 6 ca n be executed simultan eously (with one instruction) .

3. When making the setting while the voltage monitor 2 interrupt is disabled (the VW2 C0 bit in the

VW2C register is 0 and the VCA27 b i t in th e VCA2 r eg ister is 0), no interr upt reque st is gene rated if

VCC < Vdet2 (or VCC > Vdet2) is detected before enabling the voltage monitor 2 interrupt in step

11. If VCC < Vdet2 (or VCC > Vdet2) is detected between step 9 and step 11, the VW2C2 bit is set

to 1. Read the VW2C2 bit after step 11. If this bit is read as 1, perform the processing to be executed

when the above state is detected.

Table 6.3 Procedure for Set ting Bits Associated with Voltage Monitor 2 Interrupt

Step When Using Digital Filter When Using No Digital Filter

1 Set the VCA27 bit in the VCA2 register to 1 (voltage detection 2 circuit enabled).

2 Wait for td(E-A).

3 Set the COMPSEL bit in the CMPA register to 1.

4 (1) Select the interrupt type by the IRQ2SEL in the CMPA register.

5Select the sampling clock of the digital filter by

bits VW2F0 and VW2F1 in the VW2C register. Set the VW2C1 bit in the VW2C register to 1

(digital filter disabled).

6 (2) Set the VW2C1 bit in the VW2C register to 0

(digital filter enabled). −

7Select the interrupt request timing by the VCAC2 bit in the VCAC register and

the VW2C7 bit in the VW2C register.

8 Set the VW2C2 bit in the VW2C register to 0.

9Set the CM14 bit in the CM1 register to 0

(low-speed on-chip oscillator on). −

10 Wait for 2 cycles of the sampling clock of

the digital filter. − (No wait time required)

11 (3) Set the VW2C0 bit in the VW2C register to 1 (voltage monitor 2 interrupt enabled).

R8C/34C Group 6. Voltage Detection Circuit

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 55 of 723

Figure 6.7 Operating Example of Voltage Monitor 2 Interr upt

Vdet2

VCA13 bit

VCC

The above applies when:

• VCA27 bit in VCA2 register = 1 (voltage detection 2 circuit enabled)

• VW2C0 bit in VW2C register = 1 (voltage monitor 2 interrupt enabled)

Note:

1. If voltage monitor 0 reset is not used, set the power supply to VCC ≥ 1.8 V.

1.8 V (1)

Sampling clock of

digital fi lter × 2 cycles

VW2C2 bit

VW2C1 bit is set to 1

(digital filter disabled),

VCAC2 bit is set to 0

(one edge),

and

VW2C7 bit is set to 0

(when VCC reaches

Vdet2 or above)

VCA13: Bit in VCA1 re gister

VW2C1, VW2C2, VW2C7: Bi ts in VW2C register

VCAC2: Bit in VCAC register

Sampling clock of

digital fi lter × 2 cycles

Set to 0 by a program.

Voltage monitor 2

interrupt request

Voltage monitor 2

interrupt request

Set to 0 when an inte rrupt request

is acknowledged.

VW2C2 bit

Voltage monitor 2

interrupt request

VW2C1 bit is set to 0

(digital filter enabled)

and

VCAC2 bit is set to 1

(both edges)

VW2C2 bit

Set to 0 when an interrupt request

is acknowledged.

Set to 0 by a program.

Voltage monitor 2

interrupt request

VW2C1 bit is set to 0

(digital f ilter enabled),

VCAC2 bit is set to 0

(one edge),

and

VW2C7 bit is set to 0

(when VCC reaches

Vdet2 or above)

VW2C2 bit

Voltage monitor 2

interrupt request

VW2C1 bit is set to 0

(digital f ilter enabled),

VCAC2 bit is set to 0

(one edge),

and

VW2C7 bit is set to 1

(when VCC reaches

Vdet2 or below)

Set to 0 by a program .

VW2C2 bit

Voltage monitor 2

interrupt request

VW2C1 bit is set to 1

(digital filter disabled)

and

VCAC2 bit is set to 1

(both edges)

Set to 0 by a program.

Set to 0 when an interrupt request

is acknowledged.

Set to 0 by a program.

Set to 0 when an interrupt request

is acknowledged.

Set to 0 by a program.

VW2C1 bit is set to 1

(digital filter disabled),

VCAC2 bit is set to 0

(one edge),

and

VW2C7 bit is set to 1

(when VCC reaches

Vdet2 or below)

Set to 0 when an interrupt request

is acknowledged.

Set to 0 when an inte rrupt request

is acknowledged.

R8C/34C Group 7. I/O Ports

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 56 of 723

7. I/O Ports

There are 43 I/O ports P0 to P2, P3_0 and P3_1, P3_3 to P3_5, P3_7, P4_3 to P4_7, P6, and P6 (P4_3 and P4_4 can be

used as I/O ports if the X CIN clock oscillation circ uit is not used. P4_6 and P4_ 7 can be used as I/O ports if the XIN

clock oscillation circuit is not used.).

If the A/D converter and the D/A converter are not used, P4_2 can be used as an input -only port.

Table 7.1 lists an Overview of I/ O Po rts.

Notes:

1. In input mode, whether an inte rnal pull-up resistor is connected or not can be selected by registers PUR0 and

PUR1.

2. Whether the drive capacity of the out put transisto r is set to low or high can be selected using re gisters P1DRR

and P2DRR.

3. Whether the drive capaci ty of the output transistor is set to low or high can be selected using registers DRR0

and DRR1.

4. The input threshold value can be selected among three voltage levels (0.35 VCC, 0.50 VCC, and 0.70 VCC)

using registers VLT0 and VLT1.

5. When the XCIN clock oscillation circuit is not used, these ports can be used as an I/O ports.

6. When the XIN clock oscillation circu it is not used, these ports can be used as I/O ports.

7. When the A/D converter and the D/A conve rter are not used, this port can be used as an input-only ports.

7.1 Functions of I/O Ports

The PDi_j (j = 0 to 7) bit in the PDi (i = 0 to 4 or 6) register controls I/O of the ports P0 to P2, P3_0 and P3_1, P3_3

to P3_5, P3_7, P4_3 to P4_7, and P6. The Pi register consists of a port latch to hold output data and a circuit to read

pin states.

Figures 7.1 to 7.15 show the Configurations of I/O Ports. Tab le 7.2 lists the Functions of I/O Ports.

i = 0 to 4 or 6, j = 0 to 7

Note:

1. Nothing is assigned to bits PD4_0 to PD4_2. Also, bits PD3_2 and PD3_6 are reserved bits.

Table 7.1 Overview of I/O Ports

Ports I/O Type of Output I/O Setting Internal Pull-Up

Resister Drive Capacity

Switch Input Level Switch

P0, P6 I/O CMOS3 state Set in 1-bit units Set in 4-bit units (1) Set in 4-bit units (3) Set in 8-bit units (4)

P1, P2 I/O CMOS3 state Set in 1-bit units Set in 4-bit units (1) Set in 1-bit units (2) Set in 8-bit units (4)

P3_0 and

P3_1, P3_3 to

P3_5, P3_7

I/O CMOS3 state Set in 1-bit un i t s Set in 3-bit units (1) Set in 3-bit units (3) Set in 6-bit units (4)

P4_3 (5) I/O CMOS3 state Set in 1-bit units Set in 1-bit units (1) Set in 1-bit units (3)

P4_4 (5), P4_5,

P4_6 (6),

P4_7 (6)

I/O CMOS3 state Set in 1-bit un i t s Set in 4-bit units (1) Set in 4-bit units (3)

P4_2 (7) I (No output

function) None None None

Table 7.2 Functions of I/O Ports

Operation When

Accessing

Pi Register

Value of PDi_j Bit in PDi Register (1)

When PDi_j Bit is Set to 0 (Input Mode) When PDi_j Bit is Set to 1 (Output Mode)

Read Read the pin input level. Read the port latch.

Write Write to the port latch. Write to the po rt latch . The value written to

the port latch is output from the pin.

R8C/34C Group 7. I/O Ports

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 57 of 723

7.2 Effect on Peripheral Functions

I/O ports function as I/O ports for peripheral functions (refer to Table 1.4 Pin Name Information by Pin Number

(1) and Table 1.5 Pin Name Information by Pin Number (2)).

Table 7.3 lists the Setting of PDi_j Bit when Functioning as I/O Ports for Peripheral Functions (i = 0 to 4 or 6, j = 0

to 7).

Refer to the description of each function for information on how to set peripheral functions.

7.3 Pins Other than I/O Ports

Figure 7.16 shows the Configuration of I/O Pins.

Table 7.3 Setting of PDi_j Bit when Functioning as I/O Ports for Peripheral Functions

(i = 0 to 4 or 6, j = 0 to 7)

I/O of Peripheral Function PDi_j Bit Settings for Shared Pin Function

Input Set this bit to 0 (input mode).

Output This bit can be set to either 0 or 1 (output regardless of the port setting).

R8C/34C Group 7. I/O Ports

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 58 of 723

Figure 7.1 C onfiguration of I/O Ports (1)

Pin select register

P0_0 to P0_5

Drive capacity selection

(Note 1)

Input to individual peripheral function

Analog input of A/D converter

Pin select register

P0_6 and P0_7

Drive capacity selection

(Note 1)

Input to individual peripheral function

Analog input of A/D converter

Analog output of D/A converter D/A co nverter

output enable

Note:

1. symbolizes a parasitic diode.

Ensure the input voltage to each port does not exceed VCC.

Port latch

Data bus

Pull-up selection

Output f r om in dividual

peripheral function

Drive capacity selection

Direction

Input level

switch function

Pin select

Port latch

Data bus

Pull-up selection

Output f r om in dividual

peripheral function

Drive capacity selection

Direction

Input level

switch function

Pin select

Output from individual

peripheral function enabled

IOINSEL

IOINSEL: Bit in PINSR register

Output from individual

peripheral function enabled

IOINSEL

R8C/34C Group 7. I/O Ports

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 59 of 723

Figure 7.2 C onfiguration of I/O Ports (2)

Pin select register

P1_0 to P1_3

Drive capacity selection

Input to individual peripheral function

Analog input of A/D converter

Note:

1. symbolizes a parasitic diode.

Ensure the input voltage to each port does not exceed VCC.

(Note 1)

Port latch

Data bus

Pull-up selection

Output from individual

peripheral function

Drive capacity selection

Direction

Input level

switch function

Pin select

IOINSEL: Bit in PINSR register

IOINSEL

O u tp ut from ind ivid u a l

peripheral function enabled

R8C/34C Group 7. I/O Ports

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 60 of 723

Figure 7.3 C onfiguration of I/O Ports (3)

Pin select register

P1_5 Drive capacity selection

Drive capacity selection

Input to individual

peripheral function

Input to external interrupt Digital

filter

Pin select register

P1_4

Drive capacity selection

Input to individual peripheral function

(Note 1)

Note:

1. symbolizes a parasitic diode.

Ensure the input voltage to each port does not exceed VCC.

Port latch

Data bus

Pull-up selection

Output f r o m individual

peripheral f u nct io n

Drive capacity selection

Direction

Input level

switch function

Pin sele ct

Port latch

Data bus

Pull-up selection

Output f r o m individual

peripheral f u nct io n

Direction

Input level

switch function

Pin sele ct

IOINSEL

Output from individual

peripheral function enabled

IOINSEL

Output from individual

peripheral function enabled

IOINSEL: Bit in PINSR register

R8C/34C Group 7. I/O Ports

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 61 of 723

Figure 7.4 C onfiguration of I/O Ports (4)

Pin select register

P1_7 Drive capacity selection

Drive capacity selection

Input to individual

peripheral function

Input to external interrupt Digital

filter

Analog input of

comparator B

Pin select register

Drive capacity selection

Input to individual peripheral function

Analog input of comparator B

P1_6

(Note 1)

Note:

1. symbolizes a parasitic diode.

Ensure the input voltage to each port does not exceed VCC.

Port latch

Data bus

Pull-up selection

Output from individual

peripheral function

Direction

Input level

switch function

Pin select

Port latch

Data bus

Pull-up selection

Output from individual

peripheral function

Direction

Input level

switch function

IOINSEL: Bit in PINSR register

IOINSEL

O u tp ut from ind ivid u a l

peripheral function enabled

Pin select

O u tp ut from ind ivid u a l

peripheral function enabled

R8C/34C Group 7. I/O Ports

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 62 of 723

Figure 7.5 C onfiguration of I/O Ports (5)

Pin select register

P2_0 Drive capacity selection

Drive capacity selection

Input to individual

peripheral function

Input to external interrupt Digital

filter

(Note 1)

Note:

1. symbolizes a parasitic diode.

Ensure the input voltage to each port does not exceed VCC.

Port latch

Data bus

Pull-up selection

Output f r om individu al

peripheral f u nct io n

Direction

Input level

switch function

Pin sele ct

Pin select register

P2_1 to P2_7 Drive capacity selection

Drive capacity selection

Input to individual peripheral function

(Note 1)

Port latch

Data bus

Pull-up selection

Output f r om individu al

peripheral f u nct io n

Direction

Input level

switch function

IOINSEL

Output from individual

peripheral function enabled

IOINSEL

Output from individual

peripheral function enabled

Pin sele ct

IOINSEL: Bit in PINSR register

R8C/34C Group 7. I/O Ports

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 63 of 723

Figure 7.6 C onfiguration of I/O Ports (6)

Drive capacity selection

P3_0 and P3_1

(Note 1)

Note:

1. symbolizes a parasitic diode.

Ensure the input voltage to each port does not exceed VCC.

Port latch

Data bus

Pull-up selection

Output f r om individu al

peripheral f u nct io n

Direction

Input level

switch function

Pin sele ct

IOINSEL

IOINSEL: Bit in PINSR register

Output from individual

peripheral function enabled

R8C/34C Group 7. I/O Ports

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 64 of 723

Figure 7.7 C onfiguration of I/O Ports (7)

Pin select register

P3_3

Drive capacity selection

Input to individual

peripheral function

Input to external interrupt Digital

filter

Analog input of

comparator B

Pin select register

Drive capacity selection

Input to individual peripheral function

Analog input of comparator B

P3_4

(Note 1)

Note:

1. symbolizes a parasitic diode.

Ensure the input voltage to each port does not exceed VCC.

Port latch

Data bus

Pull-up selection

Output f r om in dividual

peripheral function

Direction

Input level

switch function

Pin select

Port latch

Data bus

Pull-up selection

Output f r om in dividual

peripheral function

Direction

Input level

switch function

Pin select

Drive capacity selection

IOINSEL

Output from individual

peripheral function enabled

IOINSEL: Bit in PINSR register

Output from individual

peripheral function enabled

R8C/34C Group 7. I/O Ports

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 65 of 723

Figure 7.8 C onfiguration of I/O Ports (8)

Pin select register

P3_5

Drive capacity selection

Input to individual peripheral function

(Note 1)

Note:

1. symbolizes a parasitic diode.

Ensure the input voltage to each port does not exceed VCC.

Port latch

Data bus

Pull-up selection

Output from individual

peripheral function

Direction

Input level

switch function

Pin select

Drive capacity selection

IOINSEL

O u tp ut from ind ivid u a l

peripheral function enabled

IOINSEL: Bit in PINSR register

R8C/34C Group 7. I/O Ports

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 66 of 723

Figure 7.9 C onfiguration of I/O Ports (9)

Note:

1. symbolizes a parasitic diode.

Ensure the input voltage to each port does not exceed VCC.

Pin select register

P3_7 Drive capacity selection

Drive capacity selection

Input to individual

peripheral function

(Note 1)

Port latch

Data bus

Pull-up selection

Output from individual

peripheral function

Direction

Input level

switch function

IOINSEL

IOINSEL: Bit in PINSR register

O u tp ut from ind ivid u a l

peripheral function enabled

Pin select

R8C/34C Group 7. I/O Ports

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 67 of 723

Figure 7.10 Configuration of I/O Ports (10)

CM03, CM04: Bits in CM0 register

CM12: Bit in CM1 register

XCSEL: Bit in PINSR register

IOINSEL: Bit in PINSR register

P4_2/VREF

Data bus Input level

switch function

Port latch

Data bus

Pull-up selection

Drive capacity selection

Direction

Input level

switch function

P4_3/XCIN

Port latch

Data bus

Pull-up selection

Drive capacity selection

Direction

Input level

switch function

P4_4/XCOUT

CM12

RfXCIN

CM04, XCSEL

CM03

XCIN

oscillation

circuit

Note:

1. symbolizes a parasitic diode.

Ensure the input voltage to each port does not exceed VCC.

(Note 1)

IOINSEL

R8C/34C Group 7. I/O Ports

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 68 of 723

Figure 7.11 Configuration of I/O Ports (11)

Pin select register

P4_5 Drive capacity selection

Drive capacity selection

(Note 1)

Input to individual

peripheral function

Input to external interrupt

A/D trigger input Digital

filter

Note:

1. symbolizes a parasitic diode.

Ensure the input voltage to each port does not exceed V CC.

Port latch

Data bus

Pull-up selection

Output f r om in dividual

peripheral function

Direction

Input level

switch function

IOINSEL

IOINSEL: Bit in PINSR register

Output from individual

peripheral function enabled

Pin sele ct

R8C/34C Group 7. I/O Ports

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 69 of 723

Figure 7.12 Configuration of I/O Ports (12)

Note:

1. symbolizes a parasitic diode.

Ensure the input voltage to each port does not exceed VCC.

CM05: Bits in CM0 register

CM11, CM13: Bits in CM1 register

IOINSEL: Bit in PINSR register

CM05

CM11

CM13

RfXIN

XIN

oscillation

circuit

Port latch

Data bus

Pull-up selection

Drive capacity selection

Direction

Input level

switch function

P4_6/XIN

Port latch

Data bus

Pull-up selection

Drive capacity selection

Direction

Input level

switch function

P4_7/XOUT

(Note 1)

IOINSEL

R8C/34C Group 7. I/O Ports

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 70 of 723

Figure 7.13 Configuration of I/O Ports (13)

Drive capacity selection

P6_0 and P6_3

(Note 1)

Note:

1. symbolizes a parasitic diode.

Ensure the input voltage to each port does not exc eed VCC.

Port latch

Data bus

Pull-up selection

Drive capacity selection

Direction

Input level

switch function

P6_1

(Note 1)

Port latch

Data bus

Pull-up selection

Output f r o m individual

peripheral f u nct io n

Direction

Input level

switch function

IOINSEL

IOINSEL: Bit in PINSR register

Output from individual

peripheral function enabled

Pin sele ct

IOINSEL

R8C/34C Group 7. I/O Ports

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 71 of 723

Figure 7.14 Configuration of I/O Ports (14)

Pin select register

P6_2

Drive capacity selection

Input to individual peripheral function

(Note 1)

Note:

1. symbolizes a parasitic diode.

Ensure the input voltage to each port does not exceed VCC.

Port latch

Data bus

Pull-up selection

Pin select register

P6_4 Drive capacity selection

Drive capacity selection

Direction

Input to individual peripheral function

Input level

switch function

(Note 1)

Port latch

Data bus

Pull-up selection

Output f r o m individual

peripheral f u nct io n

Drive capacity selection

Direction

Input level

switch function

IOINSEL

IOINSEL: Bit in PINSR register

Output from individual

peripheral function enabled

Pin sele ct

IOINSEL

R8C/34C Group 7. I/O Ports

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 72 of 723

Figure 7.15 Configuration of I/O Ports (15)

Figure 7.16 Configuration of I/O Pins

Pin select register

P6_5 to P6_7 Drive capacity selection

Drive capacity selection

Input to individual

peripheral function

Input to external interrupt Digital

filter

(Note 1)

Note:

1. symbolizes a parasitic diode.

Ensure the input voltage to each port does not exceed VCC.

Port latch

Data bus

Pull-up selection

Output f r o m in dividual

peripheral function

Direction

Input level

switch function

IOINSEL

IOINSEL: Bit in PINSR register

Output from individual

peripheral function enabled

Pin sele ct

MODE

RESET

(Note 1)

Note:

1. symbolizes a parasitic diode.

Ensure the input voltage t o each port does not exceed VCC.

MODE signal input

RESET signal input

R8C/34C Group 7. I/O Ports

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 73 of 723

7.4 Registers

7.4.1 Port Pi Direction Register (PDi) (i = 0 to 4 or 6)

Notes:

1. Write to the PD0 register with the next instruction after t hat used to set the PRC2 bit in the PRCR register to 1

(write enabled).

2. Bits PD3_2 and PD3_6 in the PD3 register are rese rve d bi ts. If it is nece ssary to set bits PD3_2 and PD3_6, set

to 0. When read, the content is undefined.

3. Bits PD4_0 to PD4_2 in the PD4 register are unavailable on this MCU. If it is necessary to set bits PD4_0 to

PD4_2 set to 0. When read, the content is 0.

The PDi register selects whether I/O ports are used for input or output. Each bit in the PDi register corresponds

to one port.

Address 00E2h (PD0 (1)), 00E3h (PD1), 00E6h (PD2), 00E7h (PD3 (2)), 00EAh (PD4 (3)), 00EEh (PD6),

Bitb7b6b5b4b3b2b1b0

Symbol PDi_7 PDi_6 PDi_5 PDi_4 PDi_3 PDi_2 PDi_1 PDi_0

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 PDi_0 Port Pi_0 direction bit 0: Input mode (functions as an input port)

1: Output mode (functions as an output port) R/W

b1 PDi_1 Port Pi_1 direction bit R/W

b2 PDi_2 Port Pi_2 direction bit R/W

b3 PDi_3 Port Pi_3 direction bit R/W

b4 PDi_4 Port Pi_4 direction bit R/W

b5 PDi_5 Port Pi_5 direction bit R/W

b6 PDi_6 Port Pi_6 direction bit R/W

b7 PDi_7 Port Pi_7 direction bit R/W

R8C/34C Group 7. I/O Ports

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 74 of 723

7.4.2 Port Pi Register (Pi) (i = 0 to 4 or 6)

Notes:

1. Bits P3_2 and P3_6 in the P3 register are reserved bits. If it is necessary to set bits P3_2 and P3_6, set to 0.

When read, the content is undefined.

2. Bits P4_0 and P4_ 1 in the P4 register are unavailable on this MCU. If i t is necessary to set bits P4_ 0 and P4_1

set to 0. When read, the content is 0.

Data input and output to and from external devices are accomplished by reading and writing to the Pi register.

The Pi register consists of a port latch to retain output data and a circuit to read the pin status. The value written

in the port latch is output from the pin. Each bit in th e Pi register correspo nds to one po rt.

Pi_j Bit (i = 0 to 4 or 6, j = 0 to 7) (Port Pi_j Bit)

The pin level of any I/O port which is set to input mode can be read by reading the corresponding bit in this

corresponding bit in this register.

Address 00E0h(P0), 00E1h(P1), 00E4h(P2), 00E5h(P3 (1)), 00E8h(P4 (2)), 00ECh(P6),

Bitb7b6b5b4b3b2b1b0

Symbol Pi_7 Pi_6 Pi_5 Pi_4 Pi_3 Pi_2 Pi_1 Pi_0

After ResetXXXXXXXX

Bit Symbol Bit Name Function R/W

b0 Pi_0 Port Pi_0 bit 0: “L” level

1: “H” level R/W

b1 Pi_1 Port Pi_1 bit R/W

b2 Pi_2 Port Pi_2 bit R/W

b3 Pi_3 Port Pi_3 bit R/W

b4 Pi_4 Port Pi_4 bit R/W

b5 Pi_5 Port Pi_5 bit R/W

b6 Pi_6 Port Pi_6 bit R/W

b7 Pi_7 Port Pi_7 bit R/W

R8C/34C Group 7. I/O Ports

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 75 of 723

7.4.3 Timer RA Pin Select Register (TRASR)

The TRASR register selects which pin is assigned to the timer RA I/O. To use the I/O pin for timer RA, set this

Set the TRASR register before setting the timer RA associated registers. Also, do not change the setting value

in this register during timer RA operation.

7.4.4 Timer RB/RC Pin Select Register (TRBRCSR)

The TRBRCSR register selects which pin is assigned to the timer RB and timer RC I/O. To use the I/O pin for

timer RB and timer RC, set this register.

Set the TRBOSEL0 bit before setting the timer RB associated registers. Set bits TRCCLKSEL0 and

TRCCLKSEL1 before setting the timer RC associated registers. Also, do not change the setting values of the

TRBOSEL0 bit during timer RB operation. Do not change the setting values of bits TRCCLKSEL0 and

TRCCLKSEL1 during timer RC operation.

Address 0180h

Bitb7b6b5 b4 b3 b2 b1 b0

Symbol — — — — TRAOSEL0 — TRAIOSEL1 TRAIOSEL0

After Reset000 0 0 0 0 0

Bit Symbol Bit Name Function R/W

b0 TRAIOSEL0 TRAIO pin select bit b1 b0

0 0: TRAIO pin not used

0 1: P1_7 assigned

1 0: P1_5 assigned

1 1: Do not set.

R/W

b1 TRAIOSEL1 R/W

b2 — Reserved bit Set to 0. R/W

b3 TRAOSEL0 TRAO pin select bit 0: P3_7 assigned

1: P3_0 assigned R/W

b4 — Reserved bit Set to 0. R/W

b5 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b6 —

b7 —

Address 0181h

Bitb7b6 b5 b4 b3b2b1 b0

Symbol — — TRCCLKSEL1 TRCCLKSEL0 — — — TRBOSEL0

After Reset000 00000

Bit Symbol Bit Name Function R/W

b0 TRBOSEL0 TRBO pin select bit 0: P1_3 assigned

1: P3_1 assigned R/W

b1 — R eserved bit Set to 0. R/W

b2 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b3 —

b4 TRCCLKSEL0 TRCCLK pin select bit b5 b4

0 0: TRCCLK pin not used

0 1: P1_4 assigned

1 0: P3_3 assigned

1 1: Do not set.

R/W

b5 TRCCLKSEL1 R/W

b6 — R eserved bit Set to 0. R/W

b7 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

R8C/34C Group 7. I/O Ports

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 76 of 723

7.4.5 Timer RC Pin Select Register 0 (TRCPSR0)

The TRCPSR0 register selects which pin is assigned to the timer RC I/O. To use the I/O pin for timer RC, set

this register.

Set the TRCPSR0 register before setting the timer RC associated registers. Also, do not change the setting value

in this register during timer RC operation.

Address 0182h

Bitb7b6 b5 b4b3b2 b1 b0

Symbol —

TRCIOBSEL2 TRCIOBSEL1 TRCIOBSEL0 — TRCIOASEL2 TRCIOASEL1 TRCIOASEL0

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 TRCIOASEL0 TRCIOA/TRCTRG pin select bit b2 b1 b0

0 0 0: TRCIOA/TRCTRG pin not used

0 0 1: P1_1 assigned

0 1 0: P0_0 assigned

0 1 1: P0_1 assigned

1 0 0: P0_2 assigned

Other than above: Do not set.

R/W

b1 TRCIOASEL1 R/W

b2 TRCIOASEL2 R/W

b3 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b4 TRCIOBSEL0 TRCIOB pin select bit b6 b5 b4

0 0 0: TRCIOB pin not used

0 0 1: P1_2 assigned

0 1 0: P0_3 assigned

0 1 1: P0_4 assigned

1 0 0: P0_5 assigned

1 0 1: P2_0 assigned

1 1 0: P6_5 assigned

Other than above: Do not set.

R/W

b5 TRCIOBSEL1 R/W

b6 TRCIOBSEL2 R/W

b7 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

R8C/34C Group 7. I/O Ports

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 77 of 723

7.4.6 Timer RC Pin Select Register 1 (TRCPSR1)

The TRCPSR1 register selects which pin is assigned to the timer RC I/O. To use the I/O pin for timer RC, set

this register.

Set the TRCPSR1 register before setting the timer RC associated registers. Also, do not change the setting value

in this register during timer RC operation.

Address 0183h

Bitb7b6 b5 b4b3b2 b1 b0

Symbol

— TRCIODSEL2 TRCIODSEL1 TRCIODSEL0 — TRCIOCSEL2 TRCIOCSEL1 TRCIOCSEL0

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 TRCIOCSEL0 TRCIOC pin select bit b2 b1 b0

0 0 0: TRCIOC pin not used

0 0 1: P1_3 assigned

0 1 0: P3_4 assigned

0 1 1: P0_7 assigned

1 0 0: P2_1 assigned

1 0 1: P6_6 assigned

Other than above: Do not set.

R/W

b1 TRCIOCSEL1 R/W

b2 TRCIOCSEL2 R/W

b3 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b4 TRCIODSEL0 TRCIOD pin select bit b6 b5 b4

0 0 0: TRCIOD pin not used

0 0 1: P1_0 assigned

0 1 0: P3_5 assigned

0 1 1: P0_6 assigned

1 0 0: P2_2 assigned

1 0 1: P6_7 assigned

Other than above: Do not set.

R/W

b5 TRCIODSEL1 R/W

b6 TRCIODSEL2 R/W

b7 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

R8C/34C Group 7. I/O Ports

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 78 of 723

7.4.7 Timer RD Pin Select Register 0 (TRDPSR0)

The TRDPSR0 register selects which pin is assigned to the timer RD I/O. To use the I/O pin for timer RD, set

this register.

Set the TRDPSR0 register before setting the timer RD associated registers. Also, do not change the setting

value in this register during timer RD operation.

7.4.8 Timer RD Pin Select Register 1 (TRDPSR1)

The TRDPSR1 register selects which pin is assigned to the timer RD I/O. To use the I/O pin for timer RD, set

this register.

Set the TRDPSR1 register before setting the timer RD associated registers. Also, do not change the setting

value in this register during timer RD operation.

Address 0184h

Bitb7b6b5b4b3b2b1b0

Symbol — TRDIOD0SEL0 TRDIOC0SEL1 TRDIOC0SEL0 TRDIOB0SEL1 TRDIOB0SEL0 — TRDIOA0SEL0

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 TRDIOA0SEL0 TRDIOA0/TRDCLK pin select bit 0: TRDIOA0/TRDCLK pin not used

1: P2_0 assigned R/W

b1 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b2 TRDIOB0SEL0 TRDIOB0 pin select bit b3 b2

0 0: TRDIOB0 pin not used

0 1: Do not set.

1 0: P2_2 assigned

1 1: Do not set.

R/W

b3 TRDIOB0SEL1 R/W

b4 TRDIOC0SEL0 TRDIOC0 pin select bit b5 b4

0 0: TRDIOC0 pin not used

0 1: Do not set.

1 0: P2_1 assigned

1 1: Do not set.

R/W

b5 TRDIOC0SEL1 R/W

b6 TRDIOD0SEL0 TRDIOD0 pin select bit 0: TRDIOD0 pin not used

1: P2_3 assigned R/W

b7 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

Address 0185h

Bitb7b6b5b4b3b2b1b0

Symbol — TRDIOD1SEL0 — TRDIOC1SEL0 — TRDIOB1SEL0 — TRDIOA1SEL0

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 TRDIOA1SEL0 TRDIOA1 pin select bit 0: TRDIOA1 pin not used

1: P2_4 assigned R/W

b1 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b2 TRDIOB1SEL0 TRDIOB1 pin select bit 0: TRDIOB1 pin not used

1: P2_5 assigned R/W

b3 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b4 TRDIOC1SEL0 TRDIOC1 pin select bit 0: TRDIOC1 pin not used

1: P2_6 assigned R/W

b5 — Reserved bit Set to 0. R/W

b6 TRDIOD1SEL0 TRDIOD1 pin select bit 0: TRDIOD1 pin not used

1: P2_7 assigned R/W

b7 — Reserved bit Set to 0. R/W

R8C/34C Group 7. I/O Ports

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 79 of 723

7.4.9 Timer Pin Select Register (TIMSR)

The TIMSR register selects which pin is assigned to the timer RE output. To use the output pin for timer RE, set

this register.

Set the TIMSR register before setting the timer RE associated registers. Also, do not change the setting value in

this register during timer RE operation.

Address 0186h

Bitb7b6b5b4b3b2b1 b0

Symbol———————TREOSEL0

After Reset0000000 0

Bit Symbol Bit Name Function R/W

b0 TREOSEL0 TREO pin select bit 0: P0_4 assigned

1: P6_0 assigned R/W

b1 — N othing is assigned. If necessary, set to 0. When read, the content is 0. —

b2 —

b3 —

b4 —

b5 —

b6 —

b7 —

R8C/34C Group 7. I/O Ports

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 80 of 723

7.4.10 UART0 Pin Select Register (U0SR)

The U0SR register selects which pin is assigned to the UART0 I/O. To use the I/O pin for UART0, set this

Set the U0SR register before setting the UART0 associated registers. Also, do not change the setting value in

this register during UART0 operation.

7.4.11 UART1 Pin Select Register (U1SR)

The U1SR register selects which pin is assigned to the UART1 I/O. To use the I/O pin for UART1, set this

Set the U1SR register before setting the UART1 associated registers. Also, do not change the setting value in

this register during UART1 operation.

Address 0188h

Bitb7b6b5b4b3b2b1b0

Symbol — — — CLK0SEL0 — RXD0SEL0 — TXD0SEL0

After Reset000 0 0 0 0 0

Bit Symbol Bit Name Function R/W

b0 TXD0SEL0 TXD0 pin sel ect bit 0: TXD0 pin not used

1: P1_4 assigned R/W

b1 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b2 RXD0SEL0 RXD0 pin select bit 0: RXD0 pin not used

1: P1_5 assigned R/W

b3 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b4 CLK0SEL0 CLK0 pin select bit 0: CLK0 pin not used

1: P1_6 assigned R/W

b5 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b6 —

b7 —

Address 0189h

Bitb7b6b5b4b3b2b1b0

Symbol — — CLK1SEL1 CLK1SEL0 RXD1SEL1 RXD1SEL0 TXD1SEL1 TXD1SEL0

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 TXD1SEL0 TXD1 pin select bit b1 b0

0 0: TXD1 pin not used

0 1: P0_1 assigned

1 0: P6_3 assigned

1 1: Do not set.

R/W

b1 TXD1SEL1 R/W

b2 RXD1SEL0 RXD1 pin select bit b3 b2

0 0: RXD1 pin not used

0 1: P0_2 assigned

1 0: P6_4 assigned

1 1: Do not set.

R/W

b3 RXD1SEL1 R/W

b4 CLK1SEL0 CLK1 pin select bit b5 b4

0 0: CLK1 pin not used

0 1: P0_3 assigned

1 0: P6_2 assigned

1 1: P6_5 assigned

R/W

b5 CLK1SEL1 R/W

b6 — N othing is assigned. If necessary, set to 0. When read, the content is 0. —

b7 —

R8C/34C Group 7. I/O Ports

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 81 of 723

7.4.12 UART2 Pin Select Register 0 (U2SR0)

The U2SR0 register selects wh ich pin is assigned to the UART2 I/O. To use the I/O pin fo r UART2, set this

Set the U2SR0 register before setting the UART2 associated registers. Also, do not change the setting value in

this register during UART2 operation.

7.4.13 UART2 Pin Select Register 1 (U2SR1)

The U2SR1 register selects wh ich pin is assigned to the UART2 I/O. To use the I/O pin fo r UART2, set this

Set the U2SR1 register before setting the UART2 associated registers. Also, do not change the setting value in

this register during UART2 operation.

Address 018Ah

Bitb7b6b5 b4b3b2 b1 b0

Symbol — — RXD2SEL1 RXD2SEL0 — TXD2SEL2 TXD2SEL1 TXD2SEL0

After Reset000 000 0 0

Bit Symbol Bit Name Function R/W

b0 TXD2SEL0 TXD2/SDA2 pin select bit b2 b1 b0

0 0 0: TXD2/SDA2 pin not used

0 0 1: P3_7 assigned

0 1 0: P3_4 assigned

0 1 1: Do not set.

1 0 0: Do not set.

1 0 1: P6_6 assigned

1 1 0: Do not set.

1 1 1: Do not set.

R/W

b1 TXD2SEL1 R/W

b2 TXD2SEL2 R/W

b3 — N othing is assigned. If necessary, set to 0. When read, the content is 0. —

b4 RXD2SEL0 RXD2/SCL2 pin select bit b5 b4

0 0: RXD2/SCL2 pin not used

0 1: P3_4 assigned

1 0: P3_7 assigned

1 1: P4_5 assigned

R/W

b5 RXD2SEL1 R/W

b6 — Reserved bit Set to 0. R/W

b7 — N othing is assigned. If necessary, set to 0. When read, the content is 0. —

Address 018Bh

Bitb7b6b5 b4 b3b2 b1 b0

Symbol — — — CTS2SEL0 — — CLK2SEL1 CLK2SEL0

After Reset000 0 00 0 0

Bit Symbol Bit Name Function R/W

b0 CLK2SEL0 CLK2 pin select bit b1 b0

0 0: CLK2 pin not used

0 1: P3_5 assigned

1 0: Do not set.

1 1: P6_5 assigned

R/W

b1 CLK2SEL1 R/W

b2 — N othing is assigned. If necessary, set to 0. When read, the content is 0. —

b3 —

b4 CTS2SEL0 CTS2/RTS2 pin select bit 0: CTS2/RTS2 pin not used

1: P3_3 assigned R/W

b5 — Reserved bit Set to 0. R/W

b6 — N othing is assigned. If necessary, set to 0. When read, the content is 0. —

b7 —

R8C/34C Group 7. I/O Ports

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 82 of 723

7.4.14 SSU/IIC Pin Select Register (SSUIICSR)

Address 018Ch

Bitb7b6b5b4b3b2b1b0

Symbol———————IICSEL

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 IICSEL SSU/I2C bus switch bit 0: SSU fu nction selected

1: I2C bus function selected R/W

b1 — Reserved bit Set to 0. R/W

b2 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b3 —

b4 — Reserved bits Set to 0. R/W

b5 —

b6 —

b7 —

R8C/34C Group 7. I/O Ports

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 83 of 723

7.4.15 INT Interrupt Input Pin Select Register (INTSR)

The INTSR register selects which pin is assigned to the INTi (i = 1 or 3) input. To use INTi, set this register.

Set the INTSR register before setting the INTi associated registers. Also, do not change the setting values in this

Address 018Eh

Bitb7b6b5b4b3b2b1b0

Symbol INT3SEL1 INT3SEL0 — — — INT1SEL1 INT1SEL0 —

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b1 INT1SEL0 INT1 pin select bit b3 b2 b1

0 0: P1_7 assigned

0 1: P1_5 assigned

1 0: P2_0 assigned

1 1: Do not set.

R/W

b2 INT1SEL1 R/W

b3 — Reserved bits Set to 0. R/W

b4 —

b5 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b6 INT3SEL0 INT3 pin select bit b7 b6

0 0: P3_3 assigned

0 1: Do not set.

1 0: P6_7 assigned

1 1: Do not set.

R/W

b7 INT3SEL1 R/W

R8C/34C Group 7. I/O Ports

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 84 of 723

7.4.16 I/O Function Pin Select Register (PINSR)

XCSEL Bit (XCIN/XCOUT pin connect bit)

The XCSEL bit is used to connect XCIN and XCOUT to P4_3 and P4_4, respectively. When this bit is set to 1,

XCIN is connected to P4_3 and XCOUT is connected to P4_4. For how to set XCIN and XCOUT, refer to 9.

Clock Generation Circuit.

IOINSEL Bit (I/O port input function select bit)

The IOINSEL bit is used to select the pin level of an I/O port when the PDi_j (j = 0 to 7) bit in the PDi (i = 0 to

4 or 6) register is set to 1 (output mode). When this bit is set to 1, the I/O port input function reads the pin input

level regardless of the PDi register.

Table 7.4 lists I/O Port Values Read by Usin g IOINSEL Bit. The IOINSEL bit can be used to change the input

function of all I/O ports except P4_2.

Address 018Fh

Bitb7 b6 b5 b4b3b2b1b0

Symbol SDADLY1 SDADLY0 IICTCHALF IICTCTWI IOINSEL — — XCSEL

After Reset0 0 0 00000

Bit Symbol Bit Name Function R/W

b0 XCSEL XCIN/XCOUT pin connect bit 0: XCIN not connected to P4_3, XCOUT not

connected to P4_4

1: XCIN connected to P4_3, XCOUT connected to

P4_4

R/W

b1 — Reserved bit Se t to 0. R/W

b2 — N othing is assigned. If necessary, set to 0. When read, the content is 0. —

b3 IOINSEL I/O port input function select bit 0: The I/O port input function depends on the PDi (i =

0 to 4 or 6) register.

When the PDi_j (j = 0 to 7) bit in the PDi register is

set to 0 (input mode), the pin input level is read.

When the PDi_j bit in the PDi regi ster is set to 1

(output mode), the port latch is read.

1: The I/O port input function reads the pin input level

regardless of the PDi register.

R/W

b4 IICTCTWI I2C double transfer rate select bit 0: Transfer rate is the same as the value set with bits

CKS0 to CKS3 in the ICCR1 register

1: Transfer rate is twice the value set with bits CKS0

to CKS3 in the ICCR1 register

R/W

b5 IICTCHALF I2C half transfer rate select bit 0: Transfer rate is the same as the value set with bits

CKS0 to CKS3 in the ICCR1 register

1: Transfer rate is half the value set with bits CKS0 to

CKS3 in the ICCR1 register

R/W

b6 SDADLY0 SDA digital delay select bit b7 b6

0 0: Digital delay of 3 × f1 cycles

0 1: Digital delay of 11 × f1 cycles

1 0: Digital delay of 19 × f1 cycles

1 1: Do not set.

R/W

b7 SDADLY1 R/W

Table 7.4 I/O Port Values Read by Using IOINSEL Bit

PDi_j bit in PDi register 0 (input mode) 1 (output mode)

IOINSEL bit 0 1 0 1

I/O port values read Pin input level Port latch value Pin input level

R8C/34C Group 7. I/O Ports

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 85 of 723

7.4.17 Pull-Up Control Register 0 (PUR0)

Note:

1. When this bit is set to 1 (pulled up), th e pin whose port direction bit is set to 0 (input mode) is pulled up.

For pins used as input, the setting values in the PUR0 register are valid.

7.4.18 Pull-Up Control Register 1 (PUR1)

Note:

1. When this bit is set to 1 (pulled up), th e pin whose port direction bit is set to 0 (input mode) is pulled up.

For pins used as input, the setting values in the PUR1 register are valid.

Address 01E0h

Bitb7b6b5b4b3b2b1b0

Symbol PU07 PU06 PU05 PU04 PU03 PU02 PU01 PU00

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 PU00 P0_0 to P0_3 pull-up 0: Not pulled up

1: Pulled up (1) R/W

b1 PU01 P0_4 to P0_7 pull-up R/W

b2 PU02 P1_0 to P1_3 pull-up R/W

b3 PU03 P1_4 to P1_7 pull-up R/W

b4 PU04 P2_0 to P2_3 pull-up R/W

b5 PU05 P2_4 to P2_7 pull-up R/W

b6 PU06 P3_0, P3_1, and P3_3 pull-up R/W

b7 PU07 P3_4, P3_5, and P3_7 pull-up R/W

Address 01E1h

Bitb7b6b5b4b3b2b1b0

Symbol — — PU15 PU14 — — PU11 PU10

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 PU10 P4_3 pull-up 0: Not pulled up

1: Pulled up (1) R/W

b1 PU11 P4_4 to P4_7 pull-up R/W

b2 — Reserved bits Set to 0. R/W

b3 —

b4 PU14 P6_0 to P6_3 pull-up 0: Not pulled up

1: Pulled up (1) R/W

b5 PU15 P6_4 to P6_7 pull-up R/W

b6 — Nothing is assigned. If necessary, set to 0. When read, the content is undefined. —

b7 —

R8C/34C Group 7. I/O Ports

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 86 of 723

7.4.19 Port P1 Drive Capacity Control Register (P1DRR)

Note:

1. Both “H” and “L” output are set to high drive capacity.

The P1DRR register selects whether the drive capacity of the P1 output transistor is set to low or high.

The P1DRRi bit (i = 0 to 7) is used to sel ect whether the drive capacity of the output transistor is set to low or

high for each pin.

For pins used as output, the setting values in the P1DRR register are valid.

7.4.20 Port P2 Drive Capacity Control Register (P2DRR)

Note:

1. Both “H” and “L” output are set to high drive capacity.

The P2DRR register selects whether the drive capacity of the P2 output transist or is set to low or high. The

P2DRRi bit (i = 0 to 7) is used to select whether the drive capacity of the output tran sistor is set to low or high

for each pin.

For pins used as output, the setting values in the P2DRR register are valid.

Address 01F0h

Bitb7b6b5b4b3b2b1b0

Symbol P1DRR7 P1DRR6 P1DRR5 P1DRR4 P1DRR3 P1DRR2 P1DRR1 P1DRR0

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 P1DRR0 P1_0 drive capacity 0: Low

1: High (1) R/W

b1 P1DRR1 P1_1 drive capacity R/W

b2 P1DRR2 P1_2 drive capacity R/W

b3 P1DRR3 P1_3 drive capacity R/W

b4 P1DRR4 P1_4 drive capacity R/W

b5 P1DRR5 P1_5 drive capacity R/W

b6 P1DRR6 P1_6 drive capacity R/W

b7 P1DRR7 P1_7 drive capacity R/W

Address 01F1h

Bitb7b6b5b4b3b2b1b0

Symbol P2DRR7 P2DRR6 P2DRR5 P2DRR4 P2DRR3 P2DRR2 P2DRR1 P2DRR0

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 P2DRR0 P2_0 drive capacity 0: Low

1: High (1) R/W

b1 P2DRR1 P2_1 drive capacity R/W

b2 P2DRR2 P2_2 drive capacity R/W

b3 P2DRR3 P2_3 drive capacity R/W

b4 P2DRR4 P2_4 drive capacity R/W

b5 P2DRR5 P2_5 drive capacity R/W

b6 P2DRR6 P2_6 drive capacity R/W

b7 P2DRR7 P2_7 drive capacity R/W

R8C/34C Group 7. I/O Ports

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 87 of 723

7.4.21 Drive Capacity Control Register 0 (DRR0)

Note:

1. Both “H” and “L” output are set to high drive capacity.

For pins used as output, the setting values in the DRR0 register are valid.

DRR00 Bit (P0_0 to P0_3 drive capacity)

The DRR00 bit selects whether the drive capacity of the P0_0 to P0_3 output transistors is set to low or high.

This bit is used to select whether the drive capacity of the output transisto rs is set to low or high for four pins.

DRR01 Bit (P0_4 to P0_7 drive capacity)

The DRR01 bit selects whether the drive capacity of the P0_4 to P0_7 output transistors is set to low or high.

This bit is used to select whether the drive capacity of the output transisto rs is set to low or high for four pins.

DRR06 Bit (P3_0, P3_1, and P3_3 drive capacity)

The DRR06 bit selects whether the drive capacity of the P3_0, P3_1, and P3_3 output transistors is set to low or

high. This bit is used to select whether the drive capacity o f the o utp ut tran sistors is set to low or hi gh for t hree

pins.

DRR07 Bit (P3_4, P3_5, and P3_7 drive capacity)

The DRR07 bit selects whether the drive capacity of the P3_4, P3_5, and P3_7 output transistors is set to low or

high. This bit is used to select whether the drive capacity o f the o utp ut tran sistors is set to low or hi gh for t hree

pins.

Address 01F2h

Bitb7b6b5b4b3b2b1b0

Symbol DRR07 DRR06 — — — — DRR01 DRR00

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 DRR00 P0_0 to P0_3 drive capacity 0: Low

1: High (1) R/W

b1 DRR01 P0_4 to P0_7 drive capacity R/W

b2 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b3 —

b4 —

b5 —

b6 DRR06 P3_0, P3_1, and P3_3 drive capacity 0: Low

1: High (1) R/W

b7 DRR07 P3_4, P3_5, and P3_7 drive capacity R/W

R8C/34C Group 7. I/O Ports

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 88 of 723

7.4.22 Drive Capacity Control Register 1 (DRR1)

Note:

1. Both “H” and “L” output are set to high drive capacity.

For pins used as output, the setting values in the DRR1 register are valid.

DRR10 Bit (P4_3 drive capacity)

The DRR10 bit selects whether the drive capacity of the P4_3 output transistor is set to low or high. This bit is

used to select whether the drive capacity of the output transistor is set to low or high for one pin.

DRR11 Bit (P4_4 to P4_7 drive capacity)

The DRR11 bit selects whether the drive capacity of the P4_4 to P4_7 output transistors is set to low or high.

This bit is used to select whether the drive capacity of the output transisto rs is set to low or high for four pins.

DRR14 Bit (P6_0 to P6_3 drive capacity)

The DRR14 bit selects whether the drive capacity of the P6_0 and P6_3 output transistors is set to low or h igh.

This bit is used to select whether the drive capacity of the output transistors is set to low or high for fo ur pins.

DRR15 Bit (P6_4 to P6_7 drive capacity)

The DRR15 bit selects whether the drive capacity of the P6_4 and P6_7 output transistors is set to low or h igh.

This bit is used to select whether the drive capacity of the output transistors is set to low or high for fo ur pins.

Address 01F3h

Bitb7b6b5b4b3b2b1b0

Symbol — — DRR15 DRR14 — — DRR11 DRR10

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 DRR10 P4_3 drive capacity 0: Low

1: High (1) R/W

b1 DRR11 P4_4 to P4_7 drive capacity R/W

b2 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b3 — Reserved bit Set to 0. R/W

b4 DRR14 P6_0 to P6_3 drive capacity 0: Low

1: High (1) R/W

b5 DRR15 P6_4 to P6_7 drive capacity R/W

b6 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b7 —

R8C/34C Group 7. I/O Ports

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 89 of 723

7.4.23 Input Threshold Control Register 0 (VLT0)

The VLT0 register selects the voltage level of the input threshold values for ports P0 to P3. Bits VLT00 to

VLT07 are used to select the input threshold values among three voltage levels (0.35 VCC, 0.50 VCC, and 0.70

VCC) for every eight pins.

Address 01F5h

Bitb7b6b5b4b3b2b1b0

Symbol VLT07 VLT06 VLT05 VLT04 VLT03 VLT02 VLT01 VLT00

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 VLT00 P0 input level select bit b1 b0

0 0: 0.50 × VCC

0 1: 0.35 × VCC

1 0: 0.70 × VCC

1 1: Do not set.

R/W

b1 VLT01 R/W

b2 VLT02 P1 input level select bit b3 b2

0 0: 0.50 × VCC

0 1: 0.35 × VCC

1 0: 0.70 × VCC

1 1: Do not set.

R/W

b3 VLT03 R/W

b4 VLT04 P2 input level select bit b5 b4

0 0: 0.50 × VCC

0 1: 0.35 × VCC

1 0: 0.70 × VCC

1 1: Do not set.

R/W

b5 VLT05 R/W

b6 VLT06 P3 input level select bit b7 b6

0 0: 0.50 × VCC

0 1: 0.35 × VCC

1 0: 0.70 × VCC

1 1: Do not set.

R/W

b7 VLT07 R/W

R8C/34C Group 7. I/O Ports

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 90 of 723

7.4.24 Input Threshold Control Register 1 (VLT1)

The VLT1 register selects the voltage level of the input threshold values for ports P4_2 to P4_7, and P6. Bits

VLT10 and VLT11, VLT14 and VLT15 are used to select the input threshold values among three voltage levels

(0.35 VCC, 0.50 VCC, and 0.70 VCC).

Address 01F6h

Bitb7b6b5b4b3b2b1b0

Symbol — — VLT15 VLT14 — — VLT11 VLT10

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 VLT10 P4_2 to P4_7 input level select bit b1 b0

0 0: 0.50 × VCC

0 1: 0.35 × VCC

1 0: 0.70 × VCC

1 1: Do not set.

R/W

b1 VLT11 R/W

b2 — Reserved bits Set to 0. R/W

b3 —

b4 VLT14 P6 input level select bit b5 b4

0 0: 0.50 × VCC

0 1: 0.35 × VCC

1 0: 0.70 × VCC

1 1: Do not set.

R/W

b5 VLT15 R/W

b6 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b7 —

R8C/34C Group 7. I/O Ports

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 91 of 723

7.5 Port Settings

Tables 7.5 to 7.61 list the port settings.

X: 0 or 1

Notes:

1. Pulled up by setting the PU00 bit in the PUR0 register to 1.

2. Output drive capacity high by setting the DRR00 bit in the DRR0 register to 1.

X: 0 or 1

Notes:

1. Pulled up by setting the PU00 bit in the PUR0 register to 1.

2. Output drive capacity high by setting the DRR00 bit in the DRR0 register to 1.

3. N-channel open-drain output by setting the NCH bit in the U1C0 register to 1.

X: 0 or 1

Notes:

1. Pulled up by setting the PU00 bit in the PUR0 register to 1.

2. Output drive capacity high by setting the DRR00 bit in the DRR0 register to 1.

Table 7.5 Port P0_0/AN7/TRCIOA/TRCTRG

Bit PD0_0 CH ADGSEL TRCIOASEL —

21010210

Setting

Value

0 XXXXXOther than 010b X Input port (1)

1 XXXXXOther than 010b X Output port (2)

0 11100Other than 010b X A/D converter input (AN7) (1)

0 XXXXX010 Refer to Table 7.50

TRCIOA Pin Setting TRCIOA input (1)

X XXXXX010 Refer to Table 7.50

TRCIOA Pin Setting TRCIOA output (2)

Table 7.6 Port P0_1/AN6/TXD1/TRCIOA/TRCTRG

Bit PD0_1 CH ADGSEL TXD1SEL SMD TRCIOASEL —

21010 1 0210210

Setting

Value

0 XXX X X Other

than 01b XXX Other than

011b XInput port (1)

1 XXX X X Other

than 01b XXX Other than

011b XOutput port (2)

011000Other

than 01b XXX Other than

011b X

A/D conv erter in put (AN6 )

(1)

X XXX X X 0 1

001

XXX X TXD1 output (2, 3)

0 XXX X X Other

than 01b XXX011Refer to Table 7.50

TRCIOA Pin Setting TRCIOA input (1)

X XXX X X Other

than 01b XXX011Refer to Table 7.50

TRCIOA Pin Setting TRCIOA output (2)

Table 7.7 Port P0_2/AN5/RXD1/TRCIOA/TRCTRG

Bit PD0_2 CH ADGSEL RXD1SEL TRCIOASEL —

210 1 0 1 0 2 1 0

Setting

Value

0 X X X X X X X Other than 100b X Input port (1)

1 X X X X X X X Other than 100b X Output port (2)

0 1 0 1 0 0 Other than 01b Other than 100b X A/D converter input (AN5) (1)

0 X X X X X 0 1 Other than 100b X RXD1 input (1)

0XXXXXX X100

Refer to Table 7.50

TRCIOA Pin Setting TRCIOA input (1)

XXXXXXX X 100

Refer to Table 7.50

TRCIOA Pin Setting TRCIOA output (2)

R8C/34C Group 7. I/O Ports

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 92 of 723

X: 0 or 1

Notes:

1. Pulled up by setting the PU00 bit in the PUR0 register to 1.

2. Output drive capacity high by setting the DRR00 bit in the DRR0 register to 1.

X: 0 or 1

Notes:

1. Pulled up by setting the PU01 bit in the PUR0 register to 1.

2. Output drive capacity high by setting the DRR01 bit in the DRR0 register to 1.

X: 0 or 1

Notes:

1. Pulled up by setting the PU01 bit in the PUR0 register to 1.

2. Output drive capacity high by setting the DRR01 bit in the DRR0 register to 1.

Table 7.8 Port P0_3/AN4/CLK1/TRCIOB

Bit PD0_3 CH ADGSEL CLK1SEL SMD CKDIR TRCIOBSEL —

210 1 0 1 0 210 2 1 0

Setting

Value

0XXXXX Other

than 01b XXX X Other than

010b XInput port (1)

1XXXXX Other

than 01b XXX X Other than

010b XOutput port (2)

010000 Other

than 01b XXX X Other than

010b XA/D converter input

(AN4) (1)

0 XXX X X 0 1 XXX 1 X X X X CLK1 (external clock)

input (1)

X XXX X X 0 1 001 0 X X X X CLK1 (internal clock)

output (2)

0XXXXX Other

than 01b XXX X 0 1 0 Refer to Table 7.51

TRCIOB Pin Setting TRCIOB input (1)

XXXXXX Other

than 01b XXX X 0 1 0 Refer to Table 7.51

TRCIOB Pin Setting TRCIOB output (2)

Table 7.9 Port P0_4/AN3/TREO/TRCIOB

Bit PD0_4 CH ADGSEL TREOSEL0 TOENA

TRCIOBSEL

—

210 1 0 2 1 0

Setting

Value

0 X X X X X Other than 01b Other than

011b XInput port (1)

1 X X X X X Other than 01b Other than

011b XOutput port (2)

0 0 1 1 0 0 Other than 01b Other than

011b X

A/D conv erter in put (AN3 )

(1)

X XXX X X 0 1 Other than

011b XTREO output (2)

0 XXX X X X X 0 1 1 Refer to Table 7.51

TRCIOB Pin Setting TRCIOB input (1)

X XXX X X X X 0 1 1 Refer to Table 7.51

TRCIOB Pin Setting TRCIOB output (2)

Table 7.10 Port P0_5/AN2/TRCIOB

Bit PD0_5 CH ADGSEL TRCIOBSEL —

21010210

Setting

Value

0 XXXXXOther than 100b X Input port (1)

1 XXXXXOther than 100b X Output port (2)

0 01000Other than 100b X A/D converter input (AN2) (1)

0 XXXXX100 Refer to Table 7.51

TRCIOB Pin Setti ng TRCIOB input (1)

X XXXXX100 Refer to Table 7.51

TRCIOB Pin Setti ng TRCIOB output (2)

R8C/34C Group 7. I/O Ports

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 93 of 723

X: 0 or 1

Notes:

1. Pulled up by setting the PU01 bit in the PUR0 register to 1.

2. Output drive capacity high by setting the DRR01 bit in the DRR0 register to 1.

X: 0 or 1

Notes:

1. Pulled up by setting the PU01 bit in the PUR0 register to 1.

2. Output drive capacity high by setting the DRR01 bit in the DRR0 register to 1.

X: 0 or 1

Notes:

1. Pulled up by setting the PU02 bit in the PUR0 register to 1.

2. Output drive capacity high by setting the P1DRR0 bit in the P1DRR register to 1.

Table 7.11 Port P0_6/AN1/DA0/TRCIOD

Bit PD0_6 CH ADGSEL DA0E TRCIODSEL —

210 1 0 2 1 0

Setting

Value

0 X X X X X 0 Other than 011b X Input port (1)

1 X X X X X 0 Other than 011b X Output port (2)

0 0 0 1 0 0 0 Other than 011b X A/D converter input (AN1) (1)

0 X X X X X 1 Other than 011b X D/A converter output (DA0) (1)

0XXXXX 0 011

Refer to Table 7.53

TRCIOD Pin Setting TRCIOD input (1)

XXXXXX 0 011

Refer to Table 7.53

TRCIOD Pin Setting TRCIOD output (2)

Table 7.12 Port P0_7/AN0/DA1/TRCIOC

Bit PD0_7 CH ADGSEL DA1E TRCIOCSEL —

21010 210

Setting

Value

0 X X X X X 0 Other than 011b X Input port (1)

1 X X X X X 0 Other than 011b X Output port (2)

0 0 0 0 0 0 0 Other than 011b X A/D converter input (AN0) (1)

0 X X X X X 1 Other than 011b X D/A converter output (DA1) (1)

0 XXXXX 0 011

Refer to Table 7.52

TRCIOC Pin Setti ng TRCIOC input (1)

X XXXXX 0 011

Refer to Table 7.52

TRCIOC Pin Setti ng TRCIOC output (2)

Table 7.13 Port P1_0/KI0/AN8/TRCIOD

Bit PD1_0 KI0EN CH ADGSEL TRCIODSEL —

21010210

Setting

Value

0 X X X X X X Other than 001b X Input port (1)

1 X X X X X X Other than 001b X Output port (2)

0 1 X X X X X Other than 001b X KI0 input (1)

0 0 0 0 0 0 1 Other than 001b X

A/D converter input (AN8)

(1)

0XXXXXX001

Refer to Table 7.53

TRCIOD Pin Setti ng TRCIOD input (1)

XXXXXXX001

Refer to Table 7.53

TRCIOD Pin Setti ng TRCIOD output (2)

R8C/34C Group 7. I/O Ports

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 94 of 723

X: 0 or 1

Notes:

1. Pulled up by setting the PU02 bit in the PUR0 register to 1.

2. Output drive capacity high by setting the P1DRR1 bit in the P1DRR register to 1.

X: 0 or 1

Notes:

1. Pulled up by setting the PU02 bit in the PUR0 register to 1.

2. Output drive capacity high by setting the P1DRR2 bit in the P1DRR register to 1.

Table 7.14 Port P1_1/KI1/AN9/TRCIOA/TRCTRG

Bit PD1_1 KI1EN CH ADGSEL TRCIOASEL —

21010210

Setting

Value

0 X X X X X X Other than 001b X Input port (1)

1 X X X X X X Other than 001b X Output port (2)

0 1 X X X X X Other than 001b X KI1 input (1)

0 0 0 0 1 0 1 Other than 001b X

A/D converter input (AN9)

(1)

0 X XXXXX001Refer to Table 7.50

TRCIOA Pin Setti ng TRCIOA input (1)

X X XXXXX001Refer to Table 7.50

TRCIOA Pin Setti ng TRCIOA output (2)

Table 7.15 Port P1_2/KI2/AN10/TRCIOB

Bit PD1_2 KI2EN CH ADGSEL TRCIOBSEL —

21010210

Setting

Value

0 X X X X X X Other than 001b X Input port (1)

1 X X X X X X Other than 001b X Output port (2)

0 1 X X X X X Other than 001b X KI2 input (1)

0 0 0 1 0 0 1 Other than 001b X

A/D converter input (AN10)

(1)

0 X XXXXX001Refer to Table 7.51

TRCIOB Pin Setti ng TRCIOB input (1)

X X XXXXX001Refer to Table 7.51

TRCIOB Pin Setti ng TRCIOB output (2)

R8C/34C Group 7. I/O Ports

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 95 of 723

X: 0 or 1

Notes:

1. Pulled up by setting the PU02 bit in the PUR0 register to 1.

2. Output drive capacity high by setting the P1DRR3 bit in the P1DRR register to 1.

X: 0 or 1

Notes:

1. Pulled up by setting the PU03 bit in the PUR0 register to 1.

2. Output drive capacity high by setting the P1DRR4 bit in the P1DRR register to 1.

3. N-channel open-drain output by setting the NCH bit in the U0C0 register to 1.

Table 7.16 Port P1_3/KI3/AN11/TRCIOC

Bit PD1_3 KI3EN CH

ADGSEL

TRBOSEL0 TRCIOCSEL ——

21010 210

Setting

Value

0 X XXXXX 1Other than

001b

XXInput port (1)

XOther than TRBO

usage conditions

1 X XXXXX 1Other than

001b

XXOutput port (2)

XOther than TRBO

usage conditions

0 1 XXXXX 1Other than

001b

XXKI3 input (1)

XOther than TRBO

usage conditions

0 0 01101 1Other than

001b

XXA/D converter

input (AN11) (1)

XOther than TRBO

usage conditions

X X XXXXX 0 XXXRe fe r to Table

7.49 TRBO Pin

Setting XTRBO output (2)

0 X XXXXX 1001 XRefer to Table

7.52 TRCIOC

Pin Setting TRCIOC input (1)

XOther than TRBO

usage conditions

X X XXXXX 1001 XRefer to Table

7.52 TRCIOC

Pin Setting TRCIOC output (2)

XOther than TRBO

usage conditions

Table 7.17 Port P1_4/TXD0/TRCCLK

Bit PD1_4 TXD0SEL0 SMD TRCCLKSEL TCK

21010210

Setting

Value

0 0 XXXXXXXX

Input port (1)

1 0 XXXXXXXX

Output port (2)

001

XXXXX

TXD0 output (2, 3)

0 0 XXX01101

TRCCLK input (1)

R8C/34C Group 7. I/O Ports

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 96 of 723

X: 0 or 1

Notes:

1. Pulled up by setting the PU03 bit in the PUR0 register to 1.

2. Output drive capacity high by setting the P1DRR5 bit in the P1DRR register to 1.

X: 0 or 1

Notes:

1. Pulled up by setting the PU03 bit in the PUR0 register to 1.

2. Output drive capacity high by setting the P1DRR6 bit in the P1DRR register to 1.

X: 0 or 1

Notes:

1. Pulled up by setting the PU03 bit in the PUR0 register to 1.

2. Output drive capacity high by setting the P1DRR7 bit in the P1DRR register to 1.

Table 7.18 Port P1_5/RXD0/TRAIO/INT1

Bit PD1_5 RXD0SEL0 TRAIOSEL TOPCR TMOD INT1SEL INT1EN INT1CP0

1 0 210210

Setting

Value

0 X Other than 10b X X X XXXX X X Input port (1)

1 X Other than 10b X X X XXXX X X Output port (2)

0 1 Other than 10b X X X XXXX X X RXD0 input (1)

0X100

Other than

000b, 001b XXX X X TRAIO input (1)

0 X Other than 10b X X X X 0 0 1 1 0 INT1 input (1)

0X100

Other than

000b, 001b 001 1 0 TRAIO/INT1

input (1)

X X 1 0 0 001XXX X X TRAIO pulse

output (2)

01100

Master mode:

000b

Slave mode:

011b

XXX X X TRAIO/RXD0

input (Hardware

LIN)

0 1 1 0 0 001 1 0 TRAIO/RXD0/

INT1 input

(Hardware LIN)

Table 7.19 Port P1_6/CLK0/IVREF1

Bit PD1_6 CLK0SEL0 SMD CKDIR INT1CP0

210

Setting

Value

0 0 XXX X XInput port (1)

1 0 XXX X XOutput port (2)

0 1 XXX 1 XCLK0 (exter nal clock) input (1)

X10010X

CLK0 (internal clock) output (2)

0 0 X X X X 1 Comparator B1 reference voltage input (IVREF1)

Table 7.20 Port P1_7/INT1/TRAIO/IVCMP1

Bit PD1_7 TRAIOSEL TOPCR TMOD INT1SEL INT1EN INT1CP0

1 0 21010

Setting

Value

0 Other than 01b X X XXXX X X Input port (1)

1 Other than 01b X X XXXX X X Output port (2)

001 0Other than

000b, 001b XX X X TRAIO input (1)

0 Other than 01b X X X X 0 0 1 0 INT1 input (1)

001 0Other than

000b, 001b 00 1 0 TRAIO/INT1 input (1)

X 0 1 0 001XX X X TRAIO pulse output (2)

0 Other than 01b X X XXXX 1 1 Comparator B1 input (IVCMP1)

R8C/34C Group 7. I/O Ports

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 97 of 723

X: 0 or 1

Notes:

1. Pulled up by setting the PU04 bit in the PUR0 register to 1.

2. Output drive capacity high by setting the P2DRR0 bit in the P2DRR register to 1.

X: 0 or 1

Notes:

1. Pulled up by setting the PU04 bit in the PUR0 register to 1.

2. Output drive capacity high by setting the P2DRR1 bit in the P2DRR register to 1.

Table 7.21 Port P2_0/TRDIOA0/TRDCLK/INT1/TRCIOB

Setting Timer RD

Setting Function

Bit PD2_0 TRDIOA0SEL0 INT1SEL INT1EN INT1CP

0TRCIOBSEL ——

10 210

Setting

Value

00XXXX

Other than

101b XX

Input port

(1)

10XXXX

Other than

101b XX

Output

port (2)

01XXXX

Other than

101b XRefer to Table

7.54 TRDIOA0

Pin Setting

TRDIOA0

input (1)

X1XXXX

Other than

101b XRefer to Table

7.54 TRDIOA0

Pin Setting

TRDIOA0

output (2)

001010

Other than

101b XX

INT1 input

(1)

0 X XX X X 101

Refer to Table

7.51 TRCIOB

Pin Setting XTRCIOB

input (1)

X X XX X X 101

Refer to Table

7.51 TRCIOB

Pin Setting XTRCIOB

output (2)

Table 7.22 Port P2_1/TRDIOC0/TRCIOC

Bit PD2_1 TRDIOC0SEL TRCIOCSEL ——

10210

Setting

Value

0 Other than 10b Other than 100b X X Input port (1)

1 Other than 10b Other than 100b X X Output port (2)

0 1 0 Other than 100b X Refer to Table 7.56

TRDIOC0 Pin Setting TRDIOC0 input (1)

X 1 0 Other than 100b X Refer to Table 7.56

TRDIOC0 Pin Setting TRDIOC0 output (2)

0XX100

Refer to Table 7.52

TRCIOC Pin Setting XTRCIOC input (1)

XXX100

Refer to Table 7.52

TRCIOC Pin Setting XTRCIOC output (2)

R8C/34C Group 7. I/O Ports

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 98 of 723

X: 0 or 1

Notes:

1. Pulled up by setting the PU04 bit in the PUR0 register to 1.

2. Output drive capacity high by setting the P2DRR2 bit in the P2DRR register to 1.

X: 0 or 1

Notes:

1. Pulled up by setting the PU04 bit in the PUR0 register to 1.

2. Output drive capacity high by setting the P2DRR3 bit in the P2DRR register to 1.

X: 0 or 1

Notes:

1. Pulled up by setting the PU05 bit in the PUR0 register to 1.

2. Output drive capacity high by setting the P2DRR4 bit in the P2DRR register to 1.

X: 0 or 1

Notes:

1. Pulled up by setting the PU05 bit in the PUR0 register to 1.

2. Output drive capacity high by setting the P2DRR5 bit in the P2DRR register to 1.

Table 7.23 Port P2_2/TRDIOB0/TRCIOD

Bit PD2_2 TRDIOB0SEL TRCIODSEL ——

10210

Setting

Value

0 Other than 10b Other than 100b X X Input port (1)

1 Other than 10b Other than 100b X X Output port (2)

0 1 0 Other than 100b X Refer to Table 7.55

TRDIOB0 Pin

Setting TRDIOB0 input (1)

X 1 0 O ther than 100b X Refer to Table 7.55

TRDIOB0 Pin

Setting TRDIOB0 output (2)

0XX100

Refer to Table 7.53

TRCIOD Pin

Setting XTRCIOD input (1)

XXX100

Refer to Table 7.53

TRCIOD Pin

Setting XTRCIOD output (2)

Table 7.24 Port P2_3/TRDIOD0

Bit PD2_3 TRDIOD0SEL0 —

Setting

Value

00 X Input port (1)

10 X Output port (2)

0 1 Refer to Table 7.57 TRDIOD0 Pin Setting TRDIOD0 input (1)

X 1 Refer to Table 7.57 TRDIOD0 Pin Setting TRDIOD0 output (2)

Table 7.25 Port P2_4/TRDIOA1

Bit PD2_4 TRDIOA1SEL0 —

Setting

Value

00 X Input port (1)

10 X Output port (2)

0 1 Refer to Table 7.58 TRDIOA1 Pin Setting TRDIOA1 input (1)

X 1 Refer to Table 7.58 TRDIOA1 Pin Setting TRDIOA1 output (2)

Table 7.26 Port P2_5/TRDIOB1

Bit PD2_5 TRDIOB1SEL0 —

Setting

Value

00 X Input port (1)

10 X Output port (2)

0 1 Refer to Table 7.59 TRDIOB1 Pin Setting TRDIOB1 input (1)

X 1 Refer to Table 7.59 TRDIOB1 Pin Setting TRDIOB1 output (2)

R8C/34C Group 7. I/O Ports

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 99 of 723

X: 0 or 1

Notes:

1. Pulled up by setting the PU05 bit in the PUR0 register to 1.

2. Output drive capacity high by setting the P2DRR6 bit in the P2DRR register to 1.

X: 0 or 1

Notes:

1. Pulled up by setting the PU05 bit in the PUR0 register to 1.

2. Output drive capacity high by setting the P2DRR7 bit in the P2DRR register to 1.

X: 0 or 1

Notes:

1. Pulled up by setting the PU06 bit in the PUR0 register to 1.

2. Output drive capacity high by setting the DRR06 bit in the DRR0 register to 1.

X: 0 or 1

Notes:

1. Pulled up by setting the PU06 bit in the PUR0 register to 1.

2. Output drive capacity high by setting the DRR06 bit in the DRR0 register to 1.

Table 7.27 Port P2_6/TRDIOC1

Bit PD2_6 TRDIOC1SEL0 —

Setting

Value

00 X Input port (1)

10 X Output port (2)

0 1 Refer to Table 7.60 TRDIOC1 Pin Setting TRDIOC1 input (1)

X 1 Refer to Table 7.60 TRDIOC1 Pin Setting TRDIOC1 output (2)

Table 7.28 Port P2_7/TRDIOD1

Bit PD2_7 TRDIOD1SEL0 —

Setting

Value

00 X Input port (1)

10 X Output port (2)

0 1 Refer to Table 7.61 TRDIOD1 Pin Setting TRDIOD1 input (1)

X 1 Refer to Table 7.61 TRDIOD1 Pin Setting TRDIOD1 output (2)

Table 7.29 Port P3_0/TRAO

Bit PD3_0 TRAOSEL0 TOENA

Setting

Value

00X

Input port (1)

10X

Output port (2)

X11

TRAO output (2)

Table 7.30 Port P3_1/TRBO

Bit PD3_1 TRBOSEL0 —

Setting

Value

00 X Input port (1)

10 X Output port (2)

X 1 Refer to Table 7.49 TRBO Pin Setting TRBO output (2)

R8C/34C Group 7. I/O Ports

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 100 of 723

X: 0 or 1

Notes:

1. Pulled up by setting the PU06 bit in the PUR0 register to 1.

2. Output drive capacity high by setting the DRR06 bit in the DRR0 register to 1.

3. N-channel open-drain output by setting the CSOS bit in the SSMR2 register to 1 (N-channel open-drain output).

X: 0 or 1

Notes:

1. Pulled up by setting the PU07 bit in the PUR0 register to 1.

2. Output drive capacity high by setting the DRR07 bit in the DRR0 register to 1.

3. N-channel open-drain output by setting the SOOS bit in the SSMR2 register to 1 (N-channel open-drain output) and setting the BIDE bit in the

SSMR2 register to 0 (standard mode).

4. N-channel open-drain output by setting the NCH bit in the U2C0 register to 1.

Table 7.31 Port P3_3/INT3/TRCCLK/SCS/CTS2/RTS2/IVCMP3

Bit PD3_3 CSS INT3SEL INT3EN TRCCLKSEL TCK CTS2SEL0 SMD CRS CRD INT3CP0

10 1 0 1 0 210 210

Setting

Value

0 0 0 X X X X X XXX 0 XXX X X X Input port (1)

1 0 0 X X X X X XXX 0 XXX X X X Output port (2)

0 0 0 0 0 1 X X XXX 0 XXX X X 0 INT3 input (1)

0 00 X X X 1 0 101 0 XXX X X X TRCCLK input (1)

X 0 1 X X X X X XXX X X X X X SCS input (1)

X10X X X X X XXX X X X X X SCS output (2, 3)

0 0 0 X X X X X XXX 1 Other than

000b 00 XCTS2 input (1)

X 0 0 X X X X X XXX 1 Other than

000b 10 XRTS2 output (2)

0 0 0 X X 1 Other than 10 b X X X 0 X X X X X 1 Comparator B3

input (IVCMP3)

Table 7.32 Port P3_4/TRCIOC/SSI/RXD2/SCL2/TXD2/SDA2/IVREF3

Synchronous Serial

Communication Unit

(Refer to Table 25.4

Association between

Communication

Modes and I/O Pins.)

TRCPSR1 U2SR0 U2MR U2SMR

INTCMP

Timer RC

Setting Function

Bit PD3_4 IICSEL SSI output

control SSI input

control

TRCIOC

SEL RXD2

SEL TXD2

SEL SMD IICM INT3

CP0 —

21010210210

Setting

Value

0X 0 0

Other than

010b

Other

than

01b

Other than

010b XXX X X X Input port (1)

1X 0 0

Other than

010b

Other

than

01b

Other than

010b XXX X X X Output port (2)

0X 0 0010

Other

than

01b

Other than

010b XXX X X Refer to Table

7.52 TRCIOC

Pin Setting

TRCIOC

input (1)

XX 0 0010

Other

than

01b

Other than

010b XXX X X Refer to Table

7.52 TRCIOC

Pin Setting

TRCIOC

output (2)

X 0 0 1 XXXXXXXXXXX X X X SSI input (1)

X 0 1 0 XXXXXXXXXXX X X X SSI outpu t (2, 3)

0X 0 0

Other than

010b 01

Other than

010b XXX X X X RXD2

input (1)

0X 0 0XXX01

Other than

010b 010 1 X X SCL2 input/

output (2, 4)

X X 0 0 XXXXX010

001

XX XTXD2

output (2, 4)

0 X 0 0 XXXXX010010 1 X X SDA2 input/

output (2, 4)

0X 0 0

Other than

010b

Other

than

01b

Other than

010b XXX X 1 X

Comparator B3

reference

voltage input

(IVREF3)

R8C/34C Group 7. I/O Ports

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 101 of 723

X: 0 or 1

Notes:

1. Pulled up by setting the PU07 bit in the PUR0 register to 1.

2. Output drive capacity high by setting the DRR07 bit in the DRR0 register to 1.

3. N-channel open-drain output by setting the SCKOS bit in the SSMR2 register to 1 (N-channel open-drain output).

4. N-channel open-drain output by setting the NODC bit in the U2SMR3 register to 1.

Table 7.33 Port P3_5/SCL/SSCK/TRCIOD/CLK2

Synchronous Serial

Communication Unit (Refer to

Table 25.4 Association

between Co m m un ication

Modes and I/O Pins

TRCPSR1 U2SR1 U2MR Timer RC

Setting Function

Bit PD3_5 IICSEL ICE SSCK output

control SSCK input

control TRCIODSEL CLK2SEL SMD CKDIR —

210 1 0210

Setting

Value

00X 0 0Other than

010b Other than

01b XXX X X Input port (1)

10 X X

10X 0 0Other than

010b Other than

01b XXX X X Output port (2)

10 X X

X 1 1 X X XXX X XXXX X X SCL input/output (2)

X 0 X 0 1 XXX X XXXX X X SSCK input (1)

X 0 X 1 0 XXX X XXXX X X SSCK output (2, 3)

00X 0 0010

Other than

01b XXX X Refer to Table

7.53 TRCIOD

Pin Setting TRCIOD input (1)

10 X X

X0X 0 0010

Other than

01b XXX X Refer to Table

7.53 TRCIOD

Pin Setting TRCIOD output (2)

10 X X

00X 0 0

XXX 0 1XXX 1 X CLK2 input (2)

10 X X

X0X 0 0

XXX 0 1001 0 X CLK2 output (2, 4)

10 X X

R8C/34C Group 7. I/O Ports

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 102 of 723

X: 0 or 1

Notes:

1. Pulled up by setting the PU07 bit in the PUR0 register to 1.

2. Output drive capacity high by setting the DRR07 bit in the DRR0 register to 1.

3. N-channel open-drain output by setting the SOOS bi t in the SSMR2 register to 1 (N-channel open-drain output).

4. N-channel open-drain output by setting the NCH bit in the U2C0 register to 1.

Table 7.34 Port P3_7/SSO/TXD2/SDA2/RXD2/SCL2/TRAO/SDA

Synchronous Serial

Communication Unit

(Refer to

Table 25.4

Association between

Communication

Modes and I/O Pins

U2SR0 U2MR U2SMR TRASR TRAIOC

Function

Bit PD3_7 IICSEL ICE SSO

output

control

SSO

input

control

RXD2SEL

TXD2SEL SMD IICM TRAOSEL0 TOENA

1 0 210210 0

Setting

Value

010X X

Other

than 10b Other than

001b X X X X Other than 01b Input port (1)

0X0 0

110X X

Other

than 10b Other than

001b X X X X Other than 01b Output port (2)

0X0 0

X 1 1 X X X X XXXXXX X X X SDA

input/output (2)

X 0 X 0 1 X X XXXXXX X X X SSO input (1)

X 0 X 1 0 X X XXXXXX X X X SSO output (2, 3)

010X X

Other than

001b X X X X Other than 01b RXD2 input (1)

0X0 0

010X X

Other than

001b 010 1 X X SCL2 input/

output (2, 4)

0X0 0

X10X X

XX001

001

XX X

TXD2

output (2, 4)

0X0 0 1

010X X

X X 001010 1 X X SDA2 input/

output (2, 4)

0X0 0

X10X X

Other

than 10b Other than

001b XXX X 0 1 TRAO output (2)

0X0 0

R8C/34C Group 7. I/O Ports

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 103 of 723

X: 0 or 1

Notes:

1. Pulled up by setting the PU10 bit in the PUR1 register to 1.

2. Output drive capacity high by setting the DRR10 bit in the DRR1 register to 1.

3. When the XCIN clock is used, set the PU10 bit in the PUR1 register to 0 (not pulled up).

X: 0 or 1

Notes:

1. Pulled up by setting the PU11 bit in the PUR1 register to 1.

2. Output drive capacity high by setting the DRR11 bit in the DRR1 register to 1.

3. Since the XCIN-XCOUT oscillation buffer operates with internal step-down power, the XCOUT output level cannot be used as

the CMOS level signal directly.

4. When the XCIN clock is used, set the PU11 bit in the PUR1 register to 0 (not pulled up).

Table 7.35 Port P4_2/VREF

Bit ADSTBY DA0E DA1E

Setting

Value 0 0 0 Input port

Other than 000b Input port/VREF input

Table 7.36 Port P4_3/XCIN

Bit PD4_3 XCSEL CM03 CM04 CM10 CM12 Oscillation

buffer Feedback

resistor

Setting

Value

00XXXX OFF OFF

Input port (1)

10XXXX OFF OFF

Output port (2)

0ON ON

XCIN-XCOUT oscillation

(on-chip feedback resistor enabled) (3)

1ONOFF

XCIN-XCOUT oscillation

(on-chip feedback resistor disabled) (3)

10OFF ON

XCIN-XCOUT oscillation stop

(on-chip feedback resistor enabled)

1OFFOFF

XCIN-XCOUT oscillation stop

(on-chip feedback resistor disabled)

XXXX1XOFFOFF

XCIN-XCOUT oscillation stop

(STOP mode)

Table 7.37 Port P4_4/XCOUT

Bit PD4_4 XCSEL CM03 CM04 CM10 CM12 Oscillation

buffer Feedback

resistor

Setting

Value

00XXXX OFF OFF

Input port (1)

10XXXX OFF OFF

Output port (2)

0ON ON

XCIN-XCOUT oscillation

(on-chip feedback resistor enabled)

(

)

1ONOFF

XCIN-XCOUT oscillation

(on-chip feedback resistor disabled)

(

)

10OFF ON

XCIN-XCOUT oscillation stop

(on-chip feedback resistor enabled)

1OFFOFF

XCIN-XCOUT oscillation stop

(on-chip feedback resistor disabled)

XXXX1XOFFOFF

XCIN-XCOUT oscillation stop

(STOP mode)

R8C/34C Group 7. I/O Ports

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 104 of 723

X: 0 or 1

Notes:

1. Pulled up by setting the PU11 bit in the PUR1 register to 1.

2. Output drive capacity high by setting the DRR11 bit in the DRR1 register to 1.

3. N-channel open-drain output by setting the NCH bit in the U2C0 register to 1.

X: 0 or 1

Notes:

1. Pulled up by setting the PU11 bit in the PUR1 register to 1.

2. Output drive capacity high by setting the DRR11 bit in the DRR1 register to 1.

X: 0 or 1

Notes:

1. Pulled up by setting the PU11 bit in the PUR1 register to 1.

2. Output drive capacity high by setting the DRR11 bit in the DRR1 register to 1.

3. Since the XCIN-XCOUT oscillation buffer operates with internal step-down power, the XCOUT output level cannot be used as the CMOS level

signal directly.

Table 7.38 Port P4_5/INT0/RXD2/SCL2/ADTRG

Bit PD4_5 INT0EN RXD2SEL SMD IICM ADCAP

1 0 210 1 0

Setting

Value

0 X Other than 11b X X X X X X Input port (1)

1 X Other than 11b X X X X X X Output port (2)

0 1 Other than 11b X X X X X X INT0 input (1)

0 X 1 1 XXX X X X

RXD2 input (1)

0 X 1 1 010 1 X X

SCL2 input/output (2, 3)

0 1 Other than 11b X X X X 1 1 ADTRG input (1)

Table 7.39 Port P4_6/XIN

Bit PD4_6 XCSEL CM03 CM04 CM05 CM10 CM11 CM12 CM13 Oscillation

buffer Feedback

resistor

Setting

Value

00X0X0XX0 OFF OFF

Input port (1)

10X0X0XX0 OFF OFF

Output port (2)

XXXX

ON ON XIN-XOUT oscillation

(on-chip feedback resistor enabled)

1ONOFF

XIN-XOUT oscillation

(on-chip feedback resistor disabled)

10OFFON

XIN-XOUT oscillation stop

(on-chip feedback resistor enabled)

1OFFOFF

XIN-XOUT oscillation stop

(on-chip feedback resistor disabled)

X X X X 1 X X X OFF OFF Oscillation stop (STOP mode)

Table 7.40 Port P4_7/XOUT

Bit PD4_7 XCSEL CM03 CM04 CM05 CM10 CM11 CM12 CM13 Oscillation

buffer Feedback

resistor

Setting

Value

00X0X0XX0 OFF OFF

Input port (1)

10X0X0XX0 OFF OFF

Output port (2)

XXXX

ON ON XIN-XOUT oscillation

(on-chip feedback resistor enabled)

1ONOFF

XIN-XOUT oscillation

(on-chip feedback resistor disabled)

10OFFON

XIN-XOUT oscillation stop

(on-chip feedback resistor enabled)

1OFFOFF

XIN-XOUT oscillation stop

(on-chip feedback resistor disabled)

X X X X 1 X X X OFF OFF Oscillation stop (STOP mode)

R8C/34C Group 7. I/O Ports

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 105 of 723

X: 0 or 1

Notes:

1. Pulled up by setting the PU14 bit in the PUR1 register to 1.

2. Output drive capacity high by setting the DRR14 bit in the DRR1 register to 1.

Notes:

1. Pulled up by setting the PU14 bit in the PUR1 register to 1.

2. Output drive capacity high by setting the DRR14 bit in the DRR1 register to 1.

X: 0 or 1

Notes:

1. Pulled up by setting the PU14 bit in the PUR1 register to 1.

2. Output drive capacity high by setting the DRR14 bit in the DRR1 register to 1.

X: 0 or 1

Notes:

1. Pulled up by setting the PU14 bit in the PUR1 register to 1.

2. Output drive capacity high by setting the DRR14 bit in the DRR1 register to 1.

3. N-channel open-drain output by setting the NCH bit in the U1C0 register to 1.

Table 7.41 Port P6_0/TREO

Bit PD6_0 TREOSEL0 TOENA

Setting

Value

0 Other than 11b Input port (1)

1 Other than 11b Output port (2)

X11

TREO output (2)

Table 7.42 Port P6_1

Bit PD6_1

Setting

Value 0Input port (1)

1Output port (2)

Table 7.43 Port P6_2/CLK1

Bit PD6_2 CLK1SEL1 CLK1SEL0 SMD2 SMD1 SMD0 CKDIR

Setting

Value

0 Other than 10b X X X X Input port (1)

1 Other than 10b X X X X Output port (2)

0 1 0 XXX1

CLK1 (external clock) input (1)

X1 0 0010

CLK1 (internal clock) output (2)

Table 7.44 Port P6_3/TXD1

Bit PD6_3 TXD1SEL1 TXD1SEL0 SMD2 SMD1 SMD0

Setting

Value

0 Other than 10b X X X Input port (1)

1 Other than 10b X X X Output port (2)

X10

001

TXD1 output (2, 3)

R8C/34C Group 7. I/O Ports

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 106 of 723

X: 0 or 1

Notes:

1. Pulled up by setting the PU15 bit in the PUR1 register to 1.

2. Output drive capacity high by setting the DRR15 bit in the DRR1 register to 1.

X: 0 or 1

Notes:

1. Pulled up by setting the PU15 bit in the PUR1 register to 1.

2. Output drive capacity high by setting the DRR15 bit in the DRR1 register to 1.

3. N-channel open-drain output by setting the NODC bit in the U2SMR3 register to 1.

Table 7.45 Port P6_4/RXD1

Bit PD6_4 RXD1SEL1 RXD1SEL0

Setting

Value

0XX

Input port (1)

1XX

Output port (2)

010

RXD1 output (1)

Table 7.46 Port P6_5/INT4/CLK2/CLK1/TRCIOB

Bit PD6_5 INT4EN CLK2SEL SMD CKDIR CLK1SEL SMD CKDIR TRCIOBSEL —

1 0 210 1 0 210 2 1 0

Setting

Value

Other than

11b XXX X Other than

110b XInput port (1)

Other than

11b XXX X Other than

110b XOutput port (2)

Other than

11b XXX X Other than

110b XINT4 input (1)

0 X 1 1 XXX 1 Other than

11b XXX X XXX X CLK2 (external clock)

input (1)

X X 1 1 001 0 Other than

11b XXX X XXX X CLK2 (internal clock)

output (2, 3)

0 X X X XXX X 1 1 XXX 1 X X X X CLK1 (external clock)

input (1)

X X X X XXX X 1 1 001 0 X X X X CLK1 (internal clock)

output (2)

Other than

11b XXX X Other than

11b XXX X 110

Refer to Table 7.51

TRCIOB Pi n Setting TRCIOB input (1)

Other than

11b XXX X Other than

11b XXX X 110

Refer to Table 7.51

TRCIOB Pi n Setting TRCIOB output (2)

R8C/34C Group 7. I/O Ports

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 107 of 723

X: 0 or 1

Notes:

1. Pulled up by setting the PU15 bit in the PUR1 register to 1.

2. Output drive capacity high by setting the DRR15 bit in the DRR1 register to 1.

3. N-channel open-drain output by setting the NCH bit in the U2C0 register to 1.

X: 0 or 1

Notes:

1. Pulled up by setting the PU15 bit in the PUR1 register to 1.

2. Output drive capacity high by setting the DRR15 bit in the DRR1 register to 1.

Table 7.47 Port P6_6/INT2/TXD2/SDA2/TRCIOC

Bit PD6_6 INT2EN TXD2SEL SMD IICM TRCIOCSEL —

210210 210

Setting

Value

Other than

101b XXX X Other than

101b XInput port (1)

Other than

101b XXX X Other than

101b XOutput port (2)

Other than

101b XXX X Other than

101b XINT2 input (1)

XX101

001

XXXX X TXD2 output (2, 3)

0 X 101010 1 XXX X

SDA2 input/output

(2, 3)

Other than

101b XXX X 101Refer to Table 7.52

TRCIOC Pin Setting TRCIOC input (1)

Other than

101b XXX X 101Refer to Table 7.52

TRCIOC Pin Setting TRCIOC output (2)

Table 7.48 Port P6_7/INT3/TRCIOD

Bit PD6_7 INT3SEL INT3EN INT3CP0 TRCIODSEL —

10 210

Setting

Value

0 X X X X Other than 101b X Input port (1)

1 X X X X Other than 101b X Output port (2)

0 1 0 1 0 Other than 101b X INT3 input (1)

0 XX X X 101 Refer to Table 7.53

TRCIOD Pin Setting TRCIOD input (1)

XXXX X101

Refer to Table 7.53

TRCIOD Pin Setting TRCIOD output (2)

R8C/34C Group 7. I/O Ports

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 108 of 723

X: 0 or 1

Table 7.49 TRBO Pin Setting

Bit TOCNT TMOD1 TMOD0

Setting

Value

0 0 1 Programmable waveform generation mode (pulse output)

1 0 1 Programmable waveform generation mode (programmable output)

0 1 0 Programmable one-shot generation mode

0 1 1 Programmable wait one-shot generation mode

Table 7.50 TRCIOA Pin Setting

Bit EA PWM2 IOA2 IOA1 IOA0 TCEG1 TCEG0

Setting

Value

01001XX

Timer waveform output

(output compare function)

01 1 X X X X Timer mode (input capture function)

10XXX01

PWM2 mode TRCTRG input

Table 7.51 TRCIOB Pin Setting

Bit EB PWM2 PWMB IOB2 IOB1 IOB0

Setting

Value

0 0 X X X X PWM2 mode waveform output

0 1 1 X X X PWM mode waveform output

010001

Timer waveform output (output compare

function)

01 0 1 X X Timer mode (input capture function)

Table 7.52 TRCIOC Pin Setting

Bit EC PWM2 PWMC IOC2 IOC1 IOC0

Setting

Value

0 1 1 X X X PWM mode waveform output

0 10001

Timer waveform output (output compare

function)

01 0 1 X X Timer mode (input capture function)

Table 7.53 TRCIOD Pin Setting

Bit ED PWM2 PWMD IOD2 IOD1 IOD0

Setting

Value

0 1 1 X X X PWM mode waveform output

0 10001

Timer waveform output (output compare

function)

01 0 1 X X Timer mode (input capture function)

R8C/34C Group 7. I/O Ports

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 109 of 723

X: 0 or 1

Table 7.54 TRDIOA0 Pin Setting

Bit EA0 CMD1 CMD0 STCLK PWM3 IOA2 IOA1 IOA0

Setting

Value

X 0 0 0 1 1 X X Timer mode (input capture function)

X XX11000External clock input (TRDCLK)

0 0 0 0 0 X X X PWM3 mode waveform output

0 0001001

Timer mode waveform output (output

compare function)

Table 7.55 TRDIOB0 Pin Setting

Bit EB0 CMD1 CMD0 PWM3 PWMB0 IOB2 IOB1 IOB0

Setting

Value

X 0 0 1 0 1 X X Timer mode (input capture function)

0X X XXX

Complementary PWM mode waveform

output

0 01X X XXX

Reset synchronous PWM mode waveform

output

0 0 0 0 X X X X PWM3 mode waveform output

0 0 0 1 1 X X X PWM mode waveform output

000100

Timer mode waveform output (output

compare function)

Table 7.56 TRDIOC0 Pin Setting

Bit EC0 CMD1 CMD0 PWM3 PWMC0 IOC2 IOC1 IOC0

Setting

Value

X 0 0 1 0 1 X X Timer mode (input capture function)

0X X XXX

Complementary PWM mode waveform

output

0 01X X XXX

Reset synchronous PWM mode

waveform output

0 0 0 1 1 X X X PWM mode waveform output

000100

Timer mode waveform output (output

compare function)

Table 7.57 TRDIOD0 Pin Setting

Bit ED0 CMD1 CMD0 PWM3 PWMD0 IOD2 IOD1 IOD0

Setting

Value

X 0 0 1 0 1 X X Timer mode (input capture function)

0X X XXX

Complementary PWM mode waveform

output

0 01X X XXX

Reset synchronous PWM mode

waveform output

0 0 0 1 1 X X X PWM mode waveform output

000100

Timer mode waveform output (output

compare function)

R8C/34C Group 7. I/O Ports

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 110 of 723

X: 0 or 1

Table 7.58 TRDIOA1 Pin Setting

Bit EA1 CMD1 CMD0 PWM3 IOA2 IOA1 IOA0

Setting

Value

X 0 0 1 1 X X Timer mode (input capture function)

0X X X X Complementary PWM mode waveform output

0 0 1 X X X X Reset synchronous PWM mode waveform output

00010

Timer mode waveform output

(output compare function)

Table 7.59 TRDIOB1 Pin Setting

Bit EB1 CMD1 CMD0 PWM3 PWMB1 IOB2 IOB1 IOB0

Setting

Value

X 0 0 1 0 1 X X Timer mode (input capture function)

0X X XXX

Complementary PWM mode waveform

output

0 01X X XXX

Reset synchronous PWM mode

waveform output

0 0 0 1 1 X X X PWM mode waveform output

000100

Timer mode waveform output (output

compare function)

Table 7.60 TRDIOC1 Pin Setting

Bit EC1 CMD1 CMD0 PWM3 PWMC1 IOC2 IOC1 IOC0

Setting

Value

X 0 0 1 0 1 X X Timer mode (input capture function)

0XXXXX

Complementary PWM mode waveform

output

0 01XXXXX

Reset synchronous PWM mode

waveform output

0 0 0 1 1 X X X PWM mode waveform output

0 00100

Timer mode waveform output (output

compare function)

Table 7.61 TRDIOD1 Pin Setting

Bit ED1 CMD1 CMD0 PWM3 PWMD1 IOD2 IOD1 IOD0

Setting

Value

X 0 0 1 0 1 X X Timer mode (input capture function)

0X X XXX

Complementary PWM mode waveform

output

0 01X X XXX

Reset synchronous PWM mode

waveform output

0 0 0 1 1 X X X PWM mode waveform output

000100

Timer mode waveform output

(output compare function)

R8C/34C Group 7. I/O Ports

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 111 of 723

7.6 Unassigned Pin Handling

Table 7.62 lists Unassigned Pin Handling.

Notes:

1. If these ports are set to output mod e and left ope n, they remain in input mode until they are switched

to output mode by a program. The voltage level of these pins may be undefined and the power

current may increase while the ports remain in input mode.

The content of the direction registers may change due to noise or program runaway caused by

noise. In order to enhance program reliability, the program should periodically repeat the setting of

the direction registers.

2. Connect these unassigned pins to the MCU using the shortest wire length (2 cm or less) possible.

3. When the power-on reset function is in use.

Figure 7.17 Unassigned Pin Handling

Table 7.62 Unassigned Pin Handling

Pin Name Connection

Ports P0 to P2, P3_0 and P3_1,

P3_3 to P3_5, P3_7, P4_3 to

P4_7, P6

• After setting to input mode, connect each pin to VSS via a resistor

(pull-down) or co nn ec t ea ch pin to VCC via a re sist or (pull-up). (2)

• After setting to output mode, leave these pins ope n. (1, 2)

Port P4_2/VREF Connect to VCC

RESET (3) Connect to VCC via a pull-up resistor (2)

Note:

1. When the power-on reset function is in use.

MCU

Port P0 to P2,

P3_0 and P3_1,

P3_3 to P3_5, P3_7,

P4_3 to P4_7, P6

(Input mode )

(Input mode)

(Output mode)

Open

RESET (1)

Port P4_2/VREF

R8C/34C Group 8. Bus

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 112 of 723

8. Bus

The bus cycles differ when accessing ROM, RAM, DTC vector area, DTC control data and when accessing SFR.

Table 8.1 lists Bus Cycles by Access Area of R8C/34C Group.

ROM, RAM, DTC vector area, DTC control data and SFR are connected to the CPU by an 8-bit bus. When accessing

in word (16-bit) units, these areas are accessed twice in 8-bit units.

Table 8.2 shows Access Units and Bus Operati ons.

Table 8.2 Access Units and Bus Operations

Table 8.1 Bus Cycles by Access Area of R8C/34C Group

Access Area Bus Cycle

SFR/Data flash 2 cycles of CPU clock

Program ROM/RAM 1 cycle of CPU clock

Area SFR, Data flash

Even address

Byte acce ss

ROM (program ROM), RAM,

DTC vector area, DTC control data

Odd address

Byte acce ss

Even address

Word access

Odd address

Word access

CPU clock

Data Data Data

Even Even

Address

CPU clock

Data

Address

CPU clock

Data

Address

CPU clock

Data

Address

CPU clock

Data

Address

CPU clock

Data

Address

CPU clock

Data

Address

CPU clock

Data

Address

Data Data

Odd Odd

Data

Even Even + 1

Data

Odd Odd + 1

Data

Even Even + 1

Data

Odd Odd + 1

Data

R8C/34C Group 8. Bus

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 113 of 723

However, only the followin g SFRs are connected with the 16-bit bus:

Interrupts: Each interrupt control register

Timer RC: Registers TRC, TRCGRA, TRCGRB, TRCGRC, and TRCGRD

Timer RD: Registers TRDi (i = 0, 1), TRDGRAi, TRDGRBi, TRDGRCi, and TRDGRDi

SSU: Registers SSTDR, SSTDRH, SSRDR, and SSRDRH

UART2: Registers U2MR, U2BRG, U2TB, U2C0, U2C1, U2RB, U2SMR5, U2SMR4, U2SMR3, U2SMR2,

and U2SMR

A/D converter: Registers AD0, AD1, AD2, AD3, AD4, AD5 , AD6, AD7, ADMOD, ADINSEL, ADCON0,

and ADCON1

D/A converter: Registers DA0 and DA1

Address match interrupt: Registers RMAD0, AIER0, RMAD1, and AIER1

Therefore, they are accessed once in 16-bit units. The bus operation is the same as “Area: SFR, Data flash, Even

address Byte Access” in Table 8.2 Access Units and Bus Operations, and 16-bit data is accessed at a time.

R8C/34C Group 9. Clock Generation Circuit

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 114 of 723

9. Clock Generation Circuit

The following five circuits are incorporated in the clock generation circui t:

• XIN clock oscillation circuit

• XCIN clock oscillation circuit

• Low-speed on-chip oscill ator

• High-speed on-chip oscillator

• Low-speed on-chip oscill ator for watchdog timer

9.1 Overview

Table 9.1 lists the Specification Overview of Clock Generation Circuit. Figure 9.1 shows a Clock Generation

Circuit, Figure 9.2 shows a Peripheral Function Clock and Figure 9.3 shows a Procedure for Reducing Internal

Power Consumption Using VCA2 0 bit.

Notes:

1. These pins can be used as P4_6 and P4_7 when using the XCIN clock oscillation circuit or on-chip oscillato r

clock as the CPU clock while the XIN clock oscillation circuit is not used.

2. These pins can be used as P4_3 and P4_4 when using the XIN clock oscillation circuit or on-chip oscillator

clock as the CPU clock while the XCIN clock oscillation circuit is not used.

3. To input an external clock, set the CM05 bit in the CM0 register to 1 (XIN clock stops), the CM11 bit in the CM1

4. The clock frequency is automatically set to up to 20 MHz by a divider when using the high-speed on-chip

oscillator as the CPU clock source.

This applies when the CSPROINI bit in the OFS register is set to 1 (count source protection mode disabled after reset).

This applies when the CSPROINI bit in the OFS register is set to 0 (count source protection mode enabled after reset).

Table 9.1 Specification Overview of Clock Generation Circuit

Item XIN Clock

Oscillation Circuit XCIN Clock

Oscillation Circuit

On-Chip Oscillator Low-Speed On-

Chip Oscillator for

Watchdog Timer

High-Speed

On-Chip Oscillator Low-Speed

On-Chip Oscillator

Applications • CPU clock

source

• Peripheral

function clock

source

• CPU clock

source

• Peripheral

function clock

source

• CPU clock

source

• Peripheral

function clock

source

• CPU and

peripheral function

clock source when

XIN clock stops

oscillating

• CPU clock

source

• Peripheral

function clock

source

• CPU and

peripheral function

clock source when

XIN clock stops

oscillating

• Watchdog timer

clock source

Clock frequency 0 to 20 MHz 32.7 68 kHz

Approx. 40 MHz

(4) Approx. 125 kHz Approx. 125 kHz

Connectable

oscillator •Ceramic

resonator

• Crystal

oscillator

• Crystal

oscillator −−−

Oscillator

connect pins XIN, XOUT (1) XCIN, XCOUT (2) − (1) − (1) −

Oscillation stop,

restart function Usable Usable Usable Usable Usable

Oscillator status

after reset Stop Stop Stop Oscillate Stop (5)

Oscillate (6)

Others Externally

generated clock

can be input (3)

• Externally

generated clock

can be input

•On-chip

feedback resistor

Rf (connected/

not connected

selectable)

−−−

R8C/34C Group 9. Clock Generation Circuit

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 115 of 723

Figure 9.1 Clock Generation Circuit

1/2 1/2 1/2 1/2 1/2

Charge/discharge

circuit Oscillation stop detection

Interrupt generation circuit

FRA00 High-speed

on-chip oscillator

FRA01 = 1

FRA01 = 0

CM14

OCD2 = 0

OCD2 = 1

Divider

Oscillation stop detection

XIN clock

XOUT

CM02

WAIT instruction

CM10 = 1 (stop m ode)

CM06 = 0

CM17 to CM16 = 11b

CM06 = 1

CM06 = 0

CM17 to

CM16 = 10b

CM06 = 0

CM17 to CM16 = 01b

CM06 = 0

CM17 to CM16 = 00b Detail of di vider

Oscillation Stop Detection Circuit

Pulse generat ion c irc uit

for cloc k ed ge dete ct ion

and charge/ disc har ge

control

XIN clock

Forcible discharge when OC D0 = 0

Watchdog timer interrupt

OCD1

OCD2 bit switch signal

CM14 bit switch signal

Oscillation stop detection,

Watchdog timer,

Voltage monitor 1 interrupt,

Voltage monitor 2 interrupt

CM02, CM03, CM04, CM05, CM06, CM07: Bits in CM0 register

CM10, CM13, CM14, CM16, CM17: Bits in CM1 register

CM30: Bit in CM 3 r egist er

OCD0, OCD1, OCD2: Bits in OC D register

FRA00, FRA01, FRA03: Bits in FRA0 register

CSPRO: Bit i n CSP R regi ster

FRA2 register

fOCO (On-chip osci l lator clock)

fOCO-S

System clock

Low-speed

on-chip oscillator

FRA1 register, FRA3 register

Frequency adjustable

Divider

Power-on reset circuit

Voltage detection circuit

Voltage monitor 1 int err upt

Divider

(1/128)

1/81/2

CPU clock

f32

fOCO40M

fC4

fC32

fOCO-F

fOCO

fOCO128

fOCO-S

Peripheral

function

clock

1/2

fC2

fOCO-WDT

Low-speed on-chip oscillator

for watchdog timer

CSPRO

CM30

CM13

CM05

XIN

CM13

CM04

CM03

XCIN

CM04

XCOUT

Voltage monitor 2 int err upt

FRA03 = 1

FRA03 = 0

CM07 = 0

CM07 = 1

RESET

Power-on reset

Software reset

Voltage monito r 0 reset

Interrupt request

R8C/34C Group 9. Clock Generation Circuit

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 116 of 723

Figure 9.2 Peripheral Function Clock

UART0

A/D converter

Timer RDTimer RBTimer RA

INT0 SSU /

I2C bus

Watchdog

timer

UART1Timer RE

CPU clock

f32

fOCO40M

fOCO-F

fC4

fC32

fOCO128

Timer RC UART2

fOCO-WDT

fOCO

CPU

fC2

R8C/34C Group 9. Clock Generation Circuit

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 117 of 723

9.2 Registers

9.2.1 System Clock Control Register 0 (CM0)

Notes:

1. The CM05 bit stops the XIN clock when the hi gh-speed on-chip oscillator mode or low-speed on-chip o scillator

mode is selected. This bit cannot be used to detect whether the XIN clock has stopped. To stop the XIN clock,

set the bits in the following order:

(a) Set bits OCD1 to OCD0 in the OCD register to 00b.

(b) Set the OCD2 bit to 1 (on-chip oscillator clock selecte d).

2. During external clock input, only the clock oscillation buffer stops and clock input is acknowledged.

3. Only when the CM05 bi t is set to 1 (XIN clock stops) and the CM13 bit in the CM1 re gister is set to 0 (P4_6 and

P4_7), P4_6 and P4_7 can be used as I/O ports.

4. When the MCU enters stop mode, the CM06 bit is set to 1 (divide-by-8 mode).

5. The CM04 bit can be set to 1 by a program but cannot be set to 0.

6. To use the XCIN clock, set the CM04 bit to 1 and the XCSEL bit in the PINSR register to 1. Also, set ports P4_3

and P4_4 as input ports without pull-up.

7. Set the CM07 bit to 1 (XCIN clock) from 0 after setting the CM04 bit to 1 (XCIN-XCOUT pin) and allowing XCIN

clock oscillation to stabilize.

Set the PRC0 bit in the PRCR register to 1 (write enabled) before rewriting the CM0 register.

Address 0006h

Bitb7b6b5b4b3b2b1b0

Symbol CM07 CM06 CM05 CM04 CM03 CM02 — —

After Reset00101000

Bit Symbol Bit Name Function R/W

b0 — Reserved bits Set to 0. R/W

b1 —

b2 CM02 Wait mode peripheral function clock

stop bit 0: Peripheral func tion clock does not stop in wait mode

1: Peripheral function clock stops in wait mode R/W

b3 CM03 XCIN clock stop bit 0: XCIN clock oscillates

1: XCIN clock stops R/W

b4 CM04 Port/XCIN-XCOUT switch bit (5) 0: I/O ports P4_3 and P4_4

1: XCIN-XCOUT pin (6) R/W

b5 CM05 XIN clock (XIN-XOUT) stop bit (1, 3) 0: XIN clock oscillates

1: XIN clock stops (2) R/W

b6 CM06 CPU clock division select bit 0 (4) 0: Bits CM16 and CM17 in CM1 register enabled

1: Divide-by-8 mode R/W

b7 CM07 XIN, XCIN clock select bit (7) 0: XIN clock

1: XCIN clock R/W

R8C/34C Group 9. Clock Generation Circuit

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 118 of 723

9.2.2 System Clock Control Register 1 (CM1)

Notes:

1. When the CM06 bit is set to 0 (bits CM16 and CM17 enabled), bits CM16 and CM17 are enabled.

2. If the CM10 bit is set to 1 (stop mode), the on-chip feedback resistor is disabled.

3. When the OCD2 bit is set to 0 (XIN clock selected), the CM14 bit can be set to 1 (low-speed on-chip oscillator

off). When the OCD2 bit is set to 1 (on-chip oscillator clock selected), the CM14 bit is set to 0 (low-speed on-chip

oscillator on). It remains unchanged even if 1 is written to it.

4. To use the voltage monitor 1 interrupt or voltage monitor 2 interrupt (when the digital filter is used), set the CM14

bit to 0 (low-speed on-chip oscillator on).

5. Once the CM13 bit is set to 1 by a program, it cannot be set to 0.

6. Do not set the CM10 bit to 1 (stop mode) when the VCA20 bit in the VCA2 register to 1 (low consumption

enabled).

Set the PRC0 bit in the PRCR register to 1 (write enabled) before rewriting the CM1 register.

Address 0007h

Bitb7b6b5b4b3b2b1b0

Symbol CM17 CM16 — CM14 CM13 CM12 CM11 CM10

After Reset00100000

Bit Symbol Bit Name Function R/W

b0 CM10 All clock stop control bit (2, 6) 0: Clock oscillates

1: All clocks stop (stop mode) R/W

b1 CM11 XIN-XOUT on-chip feedback resistor

select bit 0: On-chip feedback resistor enabled

1: On-chip feedback resistor disabled R/W

b2 CM12 XCIN-XCOUT on-chip feedback

resistor select bit 0: On-chip feedback resistor enabled

1: On-chip feedback resistor disabled R/W

b3 CM13 Port/XIN-XOUT switch bit (5) 0: I/O ports P4_6 and P4_7

1: XIN-XOUT pin R/W

b4 CM14 Low-speed on-chip oscillator stop bit

(3, 4) 0: Low-speed on-chip oscillator on

1: Low-speed on-chip oscillator off R/W

b5 — Reserved bit Set to 1. R/W

b6 CM16 CPU clock division select bit 1 (1) b7 b6

0 0: No division mode

0 1: Divide-by-2 mode

1 0: Divide-by-4 mode

1 1: Divide-by-16 mode

R/W

b7 CM17 R/W

R8C/34C Group 9. Clock Generation Circuit

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 119 of 723

9.2.3 System Clock Control Register 3 (CM3)

Notes:

1. When the MCU exits wait mode by a peripheral function interrupt, the CM30 bit is set to 0 (other than wait mode).

2. Set the CM35 bit to 0 in stop mode. When the MCU enters wait mode, if the CM35 bit is set to 1 (no division), the

CM06 bit in the CM0 register is set to 0 (bits CM16 and CM17 enabled) and bits CM17 and CM16 in the CM1

3. When bits CM37 and CM36 are set to 10b (high-speed on-chip oscillator clock selected), the following will be set

when the MCU exits wait mode or stop mode.

• OCD2 bit in OCD register = 1 (on-chip oscillator selected)

• FRA00 bit in FRA0 register = 1 (high-speed on-chip oscillator on)

• FRA01 bit in FRA0 register = 1 (high-speed on-chip oscillator selected)

4. When bits CM37 and CM36 are set to 11b (XIN clock selected), the following will be set when the MCU exits wait

mode or stop mode.

• OM05 bit in OM0 register = 1 (XIN clock oscillates)

• OM13 bit in OM1 register = 1 (XIN-XOUT pin)

• OCD2 bit in OC D reg ist er = 0 (XIN clock selected)

When the MCU enters wait mode while the CM05 bit in the CM0 register is 1 (XIN clock stops), if the XIN clock is

selected as the CPU clock when exiting wait mode, set the CM06 bit to 1 (divide-by-8 mode) and the CM35 bit to

However, if an externally gene rated clock is used as the XIN clock, do not set bits CM37 to CM36 to 11b (XIN

clock selected).

Set the PRC0 bit in the PRCR register to 1 (write enabled) before rewriting the CM3 register.

Address 0009h

Bitb7b6b5b4b3b2b1b0

Symbol CM37 CM36 CM35 — — — — CM30

After Reset00000000

Bit Symbol Bi t Name Function R/W

b0 CM30 Wait control bit (1) 0: Other than wait mode

1: MCU enters wait mode R/W

b1 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b2 —

b3 — Reserved bits Set to 0. R/W

b4 —

b5 CM35 CPU clock division when exiting

wait mode select bit (2) 0: Following settings are enabled:

CM06 bit in CM0 register

Bits CM16 and CM17 in CM1 register

1: No division

R/W

b6 CM36 System clock when exiting wait

mode or stop mode select bit b7 b6

0 0: MCU exits with the CPU clock immediately

before entering wait or stop mode.

0 1: Do not set.

1 0: High-speed on-chip oscillator clock selected (3)

1 1: XIN clock select ed (4)

R/W

b7 CM37 R/W

R8C/34C Group 9. Clock Generation Circuit

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 120 of 723

CM30 bit (Wait Control Bit)

When the CM30 bit is set to 1 (MCU enters wait mode), the CPU clock stops (wait mode). Since the XIN clock,

XCIN clock, and the on-chip oscillator clock do not stop, the peripheral functions using these clocks continue

operating. To set the CM30 bit to 1, set the I flag to 0 (maskable interrupt disab led).

The MCU exits wait mode by a reset or peripheral function interrupt. When the MCU exits wait mode by a

peripheral function interrupt, it resumes executing the instruction immediately after the instruction to set the

CM30 bit to 1.

When the MCU enters wait mode with the WAIT instruction, make sure to set the I flag to 1 (maskable interrupt

enabled). With this setting, interrupt handling is performed by the CPU when the MCU exits wait mode.

R8C/34C Group 9. Clock Generation Circuit

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 121 of 723

9.2.4 Oscillation Stop Detection Register (OCD)

Notes:

1. Set bits OCD1 to OCD0 to 00b before the MCU enters stop mode, high-speed on-chi p oscillator mode, or low-

speed on-chip oscillator mode (XIN clock stops).

2. If the OCD2 bit is set to 1 (on-chip oscillator clock selected), the CM14 bit is set to 0 (low-speed on-chip oscillator

on).

3. The OCD2 bit is automatically set to 1 (on-chip oscillator clock selected) if XIN clock oscillation stop is detected

while bits OCD1 to OCD0 are set to 11b. If the OCD3 bit is set to 1 (XIN clock stops), the OCD2 bit remains

unchanged even when set to 0 (XIN clock selected).

4. The OCD3 bit is enabled when the OC D0 bit is set to 1 (oscillation stop detection function enable d).

5. The OCD3 bit remains 0 (XIN clock oscillates) if bits OCD1 to OCD0 are set to 00b.

6. Refer to Figure 9.10 Procedure for Switching Clock Source from Low-Speed On-Chip Oscillator to XIN

Clock for the switching procedure when the XIN clock re-oscillates after detecting oscillation stop.

Set the PRC0 bit in the PRCR register to 1 (write enabled) before rewriting the OCD register.

9.2.5 High-Speed On-Chip Oscillator Control Register 7 (FRA7)

Address 000Ch

Bitb7b6b5b4b3b2b1b0

Symbol — — — — OCD3 OCD2 OCD1 OCD0

After Reset00000100

Bit Symbol Bit Name Function R/W

b0 OCD0 Oscillation stop detection enable bit (6) 0: Oscillation stop detection function disabled (1)

1: Oscillation stop detection function enabled R/W

b1 OCD1 Oscillati on stop detection interrupt

enable bit 0: Disabled (1)

1: Enabled R/W

b2 OCD2 System clock select bit (3) 0: XIN clock selected (6)

1: On-chip oscillator clock selected (2) R/W

b3 OCD3 Clock monitor bit (4, 5) 0: XIN clock oscillates

1: XIN clock stops R

b4 — Reserved bits Set to 0. R/W

b5 —

b6 —

b7 —

Address 0015h

Bitb7b6b5b4b3b2b1b0

Symbol————————

After Reset When shipping

Bit Function R/W

b7-b0 32 MHz frequency correction data is stored.

The frequency can be adjusted by transferring this value to the FRA3 register and by

transferring the correction value in the FRA6 register to the FRA1 register.

R8C/34C Group 9. Clock Generation Circuit

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 122 of 723

9.2.6 High-Speed On-Chip Oscillator Control Register 0 (FRA0)

Notes:

1. Change the FRA01 bit in the following conditions.

• FRA00 = 1 (high-speed on-chip oscillator on)

• The CM14 bit in the CM1 register = 0 (low-speed on-chip oscillator on)

• Bits FRA22 to FRA20 in the FRA2 register:

All division mode can be set when VCC = 2.7 V to 5.5 V 000b to 111b

Divide ratio of 8 or more when VCC = 1.8 V to 5.5 V 110b to 111b (divide-by-8 or more)

2. When setting the FRA01 bit to 0 (low-speed on-chip oscillator selected), do not set the FRA00 bit to 0 (high-

speed on-chip oscillator off) at the same time. Set the FRA00 bit to 0 after setting the FRA01 bit to 0.

Set the PRC0 bit in the PRCR register to 1 (write enabled) before rewriting the FRA0 register.

9.2.7 High-Speed On-Chip Oscillator Control Register 1 (FRA1)

Set the PRC0 bit in the PRCR register to 1 (write enabled) before rewriting the FRA1 register.

Also, rewrite the FRA1 register when the FRA00 bit in the FRA0 register is set 0 (high-speed on-chip oscillator

off).

Address 0023h

Bitb7b6b5b4b3b2b1b0

Symbol — — — — FRA03 — FRA01 FRA00

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 FRA00 High-speed on-chip oscillator enable bit 0: High-speed on-chip oscillator off

1: High-speed on-chip oscillator on R/W

b1 FRA01 High-speed on-chip oscillator select bit (1) 0: Low-speed on-chip oscillator selected (2)

1: High-speed on-chip oscillator selected R/W

b2 — Reserved bit Set to 0. R/W

b3 FRA03 fOCO128 clock select bit 0: fOCO-S divided by 128 selected

1: fOCO-F divided by 128 selected R/W

b4 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b5 —

b6 —

b7 —

Address 0024h

Bitb7b6b5b4b3b2b1b0

Symbol————————

After Reset When shipping

Bit Function R/W

b7-b0 The frequency of th e high-speed on-chip oscillator can be adjusted by settin g as follows:

40 MHz: FRA1 = value after reset, FRA3 = value after reset

36.864 MHz: Tran sfer the value in the FRA4 register to the FRA1 registe r an d the value in

the FRA5 register to the FRA3 register.

32 MHz: Transfer the value in the FRA6 register to the FRA1 register and th e value in

the FRA7 register to the FRA3 register.

R/W

R8C/34C Group 9. Clock Generation Circuit

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 123 of 723

9.2.8 High-Speed On-Chip Oscillator Control Register 2 (FRA2)

Set the PRC0 bit in the PRCR register to 1 (write enabled) before rewriting the FRA2 register.

9.2.9 Clock Prescaler Reset Flag (CPSRF)

Address 0025h

Bitb7b6b5b4b3b2b1b0

Symbol — — — — — FRA22 FRA21 FRA20

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 FRA20 High-speed on-chip oscillato r frequency

switching bit Division selection

These bits select the division ratio for the high-

speed on-chip oscillator cl ock.

b2 b1 b0

0 0 0: Divide-by-2 mode

0 0 1: Divide-by-3 mode

0 1 0: Divide-by-4 mode

0 1 1: Divide-by-5 mode

1 0 0: Divide-by-6 mode

1 0 1: Divide-by-7 mode

1 1 0: Divide-by-8 mode

1 1 1: Divide-by-9 mode

R/W

b1 FRA21 R/W

b2 FRA22 R/W

b3 — Reserved bits Set to 0. R/W

b4 —

b5 —

b6 —

b7 —

Address 0028h

Bitb7b6b5b4b3b2b1b0

SymbolCPSR———————

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 — Reserved bits Set to 0. R/W

b1 —

b2 —

b3 —

b4 —

b5 —

b6 —

b7 CPSR Clock prescaler reset flag Setting this bit to 1 initializes the clock prescaler.

(When read, the content is 0.) R/W

R8C/34C Group 9. Clock Generation Circuit

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 124 of 723

9.2.10 High-Speed On-Chip Oscillator Control Register 4 (FRA4)

9.2.11 High-Speed On-Chip Oscillator Control Register 5 (FRA5)

9.2.12 High-Speed On-Chip Oscillator Control Register 6 (FRA6)

9.2.13 High-Speed On-Chip Oscillator Control Register 3 (FRA3)

Set the PRC0 bit in the PRCR register to 1 (write enabled) before rewriting the FRA3 register.

Also, rewrite the FRA3 register when the FRA00 bit in the FRA0 register is set 0 (high-speed on-chip oscillator

off).

Address 0029h

Bitb7b6b5b4b3b2b1b0

Symbol————————

After Reset When shipping

Bit Function R/W

b7-b0 36.864 MHz frequency correction data is stored.

The frequency can be adjusted by transferring this value to the FRA1 register and by

transferring the correction value in the FRA5 register to the FRA3 register.

Address 002Ah

Bitb7b6b5b4b3b2b1b0

Symbol————————

After Reset When shipping

Bit Function R/W

b7-b0 36.864 MHz frequency correction data is stored.

The frequency can be adjusted by transferring this value to the FRA3 register and by

transferring the correction value in the FRA4 register to the FRA1 register.

Address 002Bh

Bitb7b6b5b4b3b2b1b0

Symbol————————

After Reset When shipping

Bit Function R/W

b7-b0 32 MHz frequency correction data is stored.

The frequency can be adjusted by transferring this value to the FRA1 register and by

transferring the correction value in the FRA7 register to the FRA3 register.

Address 002Fh

Bitb7b6b5b4b3b2b1b0

Symbol————————

After Reset When shipping

Bit Function R/W

b7-b0 The frequency of th e high-speed on-chip oscillator can be adjusted by settin g as follows:

40 MHz: FRA1 = value after reset, FRA3 = value after reset

36.864 MHz: Tran sfer the value in the FRA4 register to the FRA1 registe r an d the value in

the FRA5 register to the FRA3 register.

32 MHz: Transfer the value in the FRA6 register to the FRA1 register and th e value in

the FRA7 register to the FRA3 register.

R/W

R8C/34C Group 9. Clock Generation Circuit

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 125 of 723

9.2.14 Voltage Detect Register 2 (VCA2)

Notes:

1. Use the VCA20 bit only whe n the MCU enters wait mode. To set the VCA20 bi t, follow the procedure shown in

Figure 9.3 Procedure for Reducing Internal Power Consumption Using VCA20 bit.

2. When the VCA20 bit is set to 1 (low consumption enabled), do not set the CM10 bit in the CM1 register to 1 (stop

mode).

3. When writing to the VCA25 bit, set a value after reset.

4. To use the voltage detection 1 interrupt or the VW1C3 bit in the VW1C register, set the VCA26 bit to 1.

After the VCA26 bit is set to 1 from 0, allow td(E-A) to elapse before the voltage detection 1 circuit starts

operation.

5. To use the voltage detection 2 interrupt or the VCA13 bit in the VCA1 register, set the VCA27 bit to 1.

After the VCA27 bit is set to 1 from 0, allow td(E-A) to elapse before the voltage detection 2 circuit starts

operation.

Set the PRC3 bit in the PRCR register to 1 (write enabled) before rewriting the VCA2 register.

Address 0034h

Bitb7b6b5b4b3b2b1b0

Symbol VCA27 VCA26 VCA25 — — — — VCA20

After Reset00000000

The above applies when the LVDAS bit in the OFS registe r is set to 1.

After Reset00100000

The above applies when the LVDAS bit in the OFS registe r is set to 0.

Bit Symbol Bit Name Function R/W

b0 VCA20 Internal power low consumption

enable bit (1) 0: Low consumption disabled

1: Low consumption enabled (2) R/W

b1 — Reserved bits Set to 0. R/W

b2 —

b3 —

b4 —

b5 VCA25 Voltage detection 0 enable bit (3) 0: Voltage detection 0 circuit disabled

1: Voltage detection 0 circuit enabled R/W

b6 VCA26 Voltage detection 1 enable bit (4) 0: Voltage detection 1 circuit disabled

1: Voltage detection 1 circuit enabled R/W

b7 VCA27 Voltage detection 2 enable bit (5) 0: Voltage detection 2 circuit disabled

1: Voltage detection 2 circuit enabled R/W

R8C/34C Group 9. Clock Generation Circuit

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 126 of 723

9.2.15 I/O Function Pin Select Register (PINSR)

XCSEL Bit (XCIN/XCOUT pin connect bit)

The XCSEL bit is used to connect XCIN and XCOUT to P4_3 and P4_4, respectively. When this bit is set to 1,

XCIN is connected to P4_3 and XCOUT is connected to P4_4. For how to set XCIN and XCOUT, refer to 9.

Clock Generation Circuit.

IOINSEL Bit (I/O port input function select bit)

The IOINSEL bit is used to select the pin level of an I/O port when the PDi_j (j = 0 to 7) bit in the PDi (i = 0 to

4 or 6) register is set to 1 (output mode). When this bit is set to 1, the I/O port input function reads the pin input

level regardless of the PDi register.

Table 9.2 lists I/O Port Values Read by Usin g IOINSEL Bit. The IOINSEL bit can be used to change the input

function of all I/O ports except P4_2.

Address 018Fh

Bitb7 b6 b5 b4b3b2b1b0

Symbol SDADLY1 SDADLY0 IICTCHALF IICTCTWI IOINSEL — — XCSEL

After Reset0 0 0 00000

Bit Symbol Bit Name Function R/W

b0 XCSEL XCIN/XCOUT pin connect bit 0: XCIN not connected to P4_3, XCOUT not

connected to P4_4

1: XCIN connected to P4_3, XCOUT connected to

P4_4

R/W

b1 — Reserved bit Se t to 0. R/W

b2 — N othing is assigned. If necessary, set to 0. When read, the content is 0. —

b3 IOINSEL I/O port input function select bit 0: The I/O port input function depends on the PDi (i =

0 to 4 or 6) register.

When the PDi_j (j = 0 to 7) bit in the PDi register is

set to 0 (input mode), the pin input level is read.

When the PDi_j bit in the PDi regi ster is set to 1

(output mode), the port latch is read.

1: The I/O port input function reads the pin input level

regardless of the PDi register.

R/W

b4 IICTCTWI I2C double transfer rate select bit 0: Transfer rate is the same as the value set with bits

CKS0 to CKS3 in the ICCR1 register

1: Transfer rate is twice the value set with bits CKS0

to CKS3 in the ICCR1 register

R/W

b5 IICTCHALF I2C half transfer rate select bit 0: Transfer rate is the same as the value set with bits

CKS0 to CKS3 in the ICCR1 register

1: Transfer rate is half the value set with bits CKS0 to

CKS3 in the ICCR1 register

R/W

b6 SDADLY0 SDA digital delay select bit b7 b6

0 0: Digital delay of 3 × f1 cycles

0 1: Digital delay of 11 × f1 cycles

1 0: Digital delay of 19 × f1 cycles

1 1: Do not set.

R/W

b7 SDADLY1 R/W

Table 9.2 I/O Port Values Read by Using IOINSEL Bit

PDi_j bit in PDi register 0 (input mode) 1 (output mode)

IOINSEL bit 0 1 0 1

I/O port values read Pin input level Port latch value Pin input level

R8C/34C Group 9. Clock Generation Circuit

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 127 of 723

Figure 9.3 Procedure for Reducing Internal Power Consumption Using VCA20 bit

Notes:

1. Execute this routine to handle all interrupts generated in wait mode.

However, this does not apply if it is not necessary to start the high-speed clock or high-speed on-chip oscillator during the interrupt routine.

2. Do not set the VCA20 bit to 0 with the instruction immediately after setting the VCA20 bit to 1. Also, do not do the opposite.

3. When the VCA20 bit is set to 1, do not set the CM10 bit to 1 (stop mode).

4. When the MCU enters wait mode, follow 9.7.2 Wait Mode.

Procedure for enabling reduced internal

power consumption using VCA20 bit

Enter low-speed clock mode or

low-speed on-chip oscillator mode

Stop XIN clock and

high-speed on-chip oscillator clock

VCA20 ← 1

(internal power low consumption enabled) (2, 3)

Enter wait mode (4)

VCA20 ← 0

(internal power low consumption disabled) (2)

Start XIN clock or

high-speed on-chip oscillator clock

(Wait until XIN clock or high-speed on-chip

oscillator clock oscillation stabilizes)

Enter high-speed clock mode or

high-speed on-chip oscillator mode

In interrupt routine

VCA20 ← 0

(internal power low consumption disabled) (2)

(This is automatically set when exiting wait mode)

Start XIN clock

or high-speed on-chip oscillator clock

Enter high-speed clock mode or

high-speed on-chip oscillator mode

Enter low-speed clock mode or

low-speed on-chip oscillator mode

Exit wait mode by interrupt

Stop XIN clock and

high-speed on-chip oscillator clock

VCA20 ← 1

(internal power low consumption enabled) (2, 3)

Interrupt handling completed

Step (1)

Step (2)

Step (3)

Step (4)

Step (5)

Step (6)

Step (7)

Step (8)

Step (5)

Step (6)

Step (7)

Step (8)

(Wait until XIN clock or high-speed on-chip

oscillator clock oscillation stabilizes)

Step (1)

Step (2)

Step (3)

If it is necessary to start

the high-speed clock or

high-speed on-chip oscillator

during the interrupt routine,

execute steps (6) to (7)

in the routine.

If the high-speed clock or

high-speed on-chip oscillator

starts during the interrupt

routine, execute steps (1) to

(3) at the end of the routine.

(Note 1)

Interrupt handling

VCA20: Bit in VCA2 register

R8C/34C Group 9. Clock Generation Circuit

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 128 of 723

The clocks generated by the clock generation circuits are described below.

9.3 XIN Clock

The XIN clock is supplied by the XIN clock oscillation circuit. This clock is used as the clock source for the CPU

and peripheral function clocks. The X IN clock oscillation circuit is configured by connecting a resonator between

pins XIN and XOUT. The XIN clock oscillation circuit includes an on-chip feedback resistor, which is

disconnected from the oscillation circuit in stop mode in order to reduce the amount of power consumed by the

chip. The XIN clock oscillation circuit may also be configured by feeding an externally generated clock to the

XOUT pin.

Figure 9.4 shows Examples of XIN Clock Connection Circuit.

During and after a reset, the XIN clock stops.

After setting the CM13 bit in the CM1 register to 1 (XIN-XOUT pin), the XIN clock starts oscillating when the

CM05 bit in the CM0 regist er is set to 0 (XIN clock oscillat es). After the XIN clock oscillati on stabilizes, th e XIN

clock is used as the CPU clock source when the OCD2 bit in the OCD register is set to 0 (XIN clock selected).

The power consu mption can be reduced by setting the CM0 5 bit in the CM0 reg ister to 1 (XIN clock stops) i f the

OCD2 bit is set to 1 (on-chip oscillator clock selected).

When an externally generated clock is input to the XOUT pin , the XIN clock does not stop even if the CM05 bit is

set to 1. If necessary, use an external circuit to stop the clock.

In stop mode, all clocks including the XIN clock stop. Refer to 9.7 Power Control for detai ls.

Figure 9.4 Examples of XIN Clock Connection Circuit

XIN XOUT

MCU

(on-chip feedback resistor)

Rd (1)

COUTCIN

XIN XOUT

MCU

(on-chip feedback resistor)

Externally generated clock

VCC

VSS

Notes:

1. Insert a damping resistor if required. The resistance will vary depending on the oscillator and

the oscillation drive capacity settings. Use the values recommended by the oscillator manufacturer.

If the oscillator manufacturer's datasheet specifies that a feedback resistor be added to the chip

externally, insert a feedback resistor between XIN and XOUT following the instructions.

2. Insert a damping resistor if required to prevent an overshoot from occurring.

Open

Ceramic resonator external circuit External clock input circuit

Rf (1)

• When CM05 bit in CM0 register

is set to 0 (XIN clock oscillates)

and CM13 bit in CM1 register is

set to 1 (XIN-XOUT pin)

• When CM05 bit in CM0 register

is set to 1 (XIN clock stops),

CM11 bit in CM1 register is set

to 1 (internal feedback resistor

disabled), and the CM13 bit is

set to 1 (XIN-XOUT pin)

(2)

R8C/34C Group 9. Clock Generation Circuit

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 129 of 723

9.4 On-Chip Oscillator Clock

The on-chip oscillator clock is supplied by the on-chip oscillator (high-speed on-chip oscillator or low-speed on-

chip oscillator). This clock is selected by the FRA01 bit in the FRA0 register.

9.4.1 Low-Speed On-Chip Oscillator Clock

The clock generated by the low-speed on-chip oscillator is used as the clock source for the CPU clock,

peripheral function clock, fOCO, fOCO-S, and fOCO128.

After a reset, the on-chip oscillator clock generated by the low-speed on-chip oscillator divided by 1 (no

division) is selected as the CPU clock.

If the XIN clock stops oscil lating when bits OC D1 to OCD0 in the OCD register are set to 11b, the low-speed

on-chip oscillator automatically starts operating and supplies the necessary clock for the MCU.

The frequency of the low-speed on-chip oscillator var ies depending on the supply voltage and the operating

ambient temperature. Application products must be designed with sufficient margin to allow for frequency

changes.

9.4.2 High-Speed On-Chip Oscillator Clock

The clock generated by the high-speed on-chip oscillator is used as the clock source for the CPU clock,

peripheral function clock, fOCO, fO CO-F, fOCO40M, and fOCO128.

To use the high-sp eed on-chip oscilla tor clock as the clock source for the CPU clock, peripheral clock, fOCO,

and fOCO-F, set bits FRA20 to FRA22 in the FRA2 regist er as foll ows:

•All divisio n mode can be set when VCC = 2.7 V to 5. 5 V 000b to 111b

•Divide ratio of 8 or more when VCC = 1.8 V to 5.5 V 110b to 111b (divide by 8 or more)

After a reset, the on-chip oscillator clock generated by the high-speed on-chip oscillator stops. Oscillation is

started by setting the FRA 00 bit in the FRA0 register to 1 (high-speed on-chip oscillator on).

Frequency correction data is stored in registers FRA4 to FRA7.

To adjust the frequency of the high-speed on-chip oscillator clock to 36.864 MHz, first transfer the correction

value in the FRA4 register to the FRA1 register and the correction value in the FRA5 register to the FRA3

0% when the serial interface is used in UART mode (refer to Table 22.8 and Table 23.8 Bit Rate Setting

Example in UART Mode).

To adjust the frequency of the high-speed on-chip oscillator clock to 32 MHz, first transfer the correction value

in the FRA6 register to the FRA 1 register and the correction value in the FRA7 register to the FRA3 register

before using the values.

R8C/34C Group 9. Clock Generation Circuit

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 130 of 723

9.5 XCIN Clock

The XCIN clock is suppl ied by the XCIN clock oscilla tion circuit. This cl ock is used as the clock source fo r the

CPU and peripheral function clocks. The XCIN clock oscillation circuit is configured by connecting a resonator

between the XCIN an d XCOUT pins. The XC IN clock oscillation circuit includes an on-chip a feedback resistor,

which is disconnected from the oscillation circuit in stop mode in order to reduce the amount of power consumed

by the chip. The XCIN clock oscillation circuit may also be configured by feeding an externally generated clock to

the XCIN pin.

Figure 9.5 shows Examples of XCIN Clock Connection Circuits.

During and after a reset, the XCIN clock stops.

After setting the XCSEL bit in the PINSR register to 1 (XCIN connected to P4_3, XCOUT connected to P4_4) and

the CM04 bit in the CM0 register to 1 (XCIN-XCOUT pin), th e XCIN clock starts oscillating wh en the CM03 bit

in the CM0 register is set to 0 (XCIN clock oscillates). After the XCIN clock oscillation stabilizes, the XCIN clock

is used as the CPU clock source when the CM07 bit in the CM0 register is set to 1 (XCIN clock). To input an

externally generated clock to the XCIN pin, also set the CM04 bit in the CM0 register to 1 (XCIN-XCOUT pin).

Leave the XCOUT pin open at this time.

This MCU has an on-chip feedback resistor, which can be disabled/enabled by the CM12 bit in the CM1 register.

In stop mode, all clocks including the XCIN clock stop. Refer to 9.7 Power Control for details.

Figure 9.5 Examples of XCIN Clock Connection Circuit s

XCIN XCOUT

MCU

(on-chip feedback resistor)

Rd (1)

COUTCIN

XCIN XCOUT

MCU

(on-chip feedback resistor)

Externally generated clock

VCC

VSS

Note:

1. Insert a damping resistor and feedback resistor if required. The resistance will vary depending on

the osc illator and the oscill a t io n driv e ca pa c i ty setting. Use the va l ue rec om me n de d by t h e os cillator

manufacturer.

When the oscillation drive capacity is set to low, check that oscillation is stable. If the oscillator

manufacturer's datasheet specifies that a feedback resistor be added to the chip ex ternally ,

insert a feedback resistor between XCIN and XCOUT following the instructions.

Open

External crystal oscillator circuit External clock input circuit

Rf (1)

• When CM03 bit in CM0 register is set

to 0 (XCIN clock oscillates) a nd CM04

bit is set to 1 (XCIN-XCOUT pin)

• When CM03 bit in CM0 register is set

to 1 (XCIN clock stops) and CM04 bit

is set to 1 (XCIN-XCOUT pin)

R8C/34C Group 9. Clock Generation Circuit

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 131 of 723

9.6 CPU Clock and Peripheral Function Clock

There are a CPU clock to operate the CPU and a peripheral function clock to operate the peripheral functions. Refer

to Figure 9.1 Clock Generation Circuit.

9.6.1 System Clock

The system clock is the clock source for the CPU and peripheral function clocks. The XIN clock, the XCIN

clock, or the on-chip oscillator clock can be selected.

9.6.2 CPU Clock

The CPU clock is an operating clock for the CPU and the watchdog timer.

The system clock divided by 1 (no division), 2, 4, 8, or 16 is used as the CPU clock. Use the CM06 bit in the

CM0 register and bits CM16 and CM17 in the CM1 register to select the value of the division.

Also, use the XCIN clock while the XCIN clock oscillation stabilizes.

After a reset, the low-speed on-chip oscillator clock divided by 1 (no division) is used as the CPU clock.

When the MCU enters stop mode, the CM06 bit is set to 1 (divide-by-8 mode). To enter stop mode, set the

CM35 bit in the CM3 register to 0 (settings of CM06 in CM0 register and bits CM16 and CM1 7 in CM1

9.6.3 Peripheral Function Clock (f1, f2, f4, f8, and f32)

The peripheral function clock is an operat ing clo c k for the peri pheral functions.

The fi (i = 1, 2, 4, 8, and 32) clock is generated by the sy stem clock divided by i. It is used for timers RA, RB,

RC, RD, RE, the serial interface, and the A/D converter.

If the MCU enters wait mode after the CM02 bit in the CM0 register is set to 1 (peripheral function clock stops

in wait mode), th e fi clo c k st op s.

9.6.4 fOCO

fOCO is an operating clock for the peripheral functions.

This clock runs at the same frequency as the on-chip oscillator c lock and can be used as the source for timer

RA.

In wait mode, the fOCO clock does not stop.

9.6.5 fOCO40M

fOCO40M is used as the count source for timers RC and RD.

This clock is generated by the high-speed on-chip oscillator and supplied by setting the FRA00 bit to 1.

In wait mode, the fOCO40M clock does no t stop.

This clock can be used with supply voltage VCC = 2.7 to 5.5 V.

9.6.6 fOCO-F

fOCO-F is used as the count source for timers RC, RD and the A/D converter.

fOCO-F is a clock generated by the h igh-speed on-chip oscilla t or and divided by i (i = 2, 3, 4, 5, 6, 7, 8, and 9;

divide ratio selected by the FRA2 register). This clock is su ppl ied by setting the FRA00 bit to 1.

In wait mode, the fOCO-F clock does not stop.

R8C/34C Group 9. Clock Generation Circuit

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 132 of 723

9.6.7 fOCO-S

fOCO-S is an operating clock for the voltage detection circuit.

This clock is generated by the low-speed on-chip oscillator and supplied by setting the CM14 bit to 0 (lo w-

speed on-chip oscillator on).

In wait mode, the fOCO-S clock does not stop.

9.6.8 fOCO128

fOCO128 is a clock generated by dividin g fOCO-S or fOCO -F by 12 8. When the FRA03 bit is set to 0, fOCO-

S divided by 128 is selected. When this bit is set to 1, fOCO-F divided by 128 is selected.

fOCO128 is configured as the capture sign al used in the TRCGRA register for timer RC and timer RD0 for

timer RD.

9.6.9 fC, fC2, fC4, and fC32

fC, fC2, fC4, and fC32 are used for timers RA, RD, RE, and the serial interface.

Use theses clocks while the XCIN clock oscillation stabilizes.

9.6.10 fOCO-WDT

fOCO-WDT is an operating clock for the watchdo g tim er.

This clock is generat ed by the low-spe ed on-chip oscillat or for the watchdog timer an d supplied by se tting the

CSPRO bit in the CSPR register to 1 (count source protect mode enabled).

In count source protection mode for the watchdog timer, the fOCO-WDT clock does not stop.

R8C/34C Group 9. Clock Generation Circuit

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 133 of 723

9.7 Power Control

There are three power control modes. All modes other than wait mode and stop mode are referred to as standard

operating mode.

9.7.1 Standard Operating Mode

Standard operating mode is further separated into fo u r modes.

In standard operating mode, the CPU an d peripheral function clocks are su pplied to operate the CPU and the

peripheral functions. Power consumption control is enabled by controlling the CPU clock frequency. The

higher the CPU clock frequency, the more processing power increases. The lower the CPU clock frequency, the

more power consumption decreases. If unnecessary oscillator circuits stop, power consumption is further

reduced.

Before the clock sources for the CPU clock can be switched over, the new clock source needs to be oscillating

and stable. Allow sufficient wait time in a program until oscillation stabilizes before switching the clock.

−: Indicates that either 0 or 1 can be set.

Table 9.3 Settings and Modes of Clock Associated Bits

Modes

OCD

OCD2 CM17,

CM16 CM14 CM13 CM07 CM06 CM05 CM04 CM03 FRA01 FRA00

High-speed

clock mode No division 0 00b −1000−− − −

Divide-by-2 0 01b −1000−− − −

Divide-by-4 0 10b −1000−− − −

Divide-by-8 0 −−1010−− − −

Divide-by-16 0 11b −1000−− − −

Low-speed

clock mode No division −00b −−10−10 −−

Divide-by-2 −01b −−10−10 −−

Divide-by-4 −10b −−10−10 −−

Divide-by-8 − −−−11−10 −−

Divide-by-16 −11b −−10−10 −−

High-speed

on-chip

oscillator

mode

No division 1 00b −−00−−− 11

Divide-by-2 1 01b −−00−−− 11

Divide-by-4 1 10b −−00−−− 11

Divide-by-8 1 −−−01−−− 11

Divide-by-16 1 11b −−00−−− 11

Low-speed

on-chip

oscillator

mode

No division 1 00b 0 −00−−− 0−

Divide-by-2 1 01b 0 −00−−− 0−

Divide-by-4 1 10b 0 −00−−− 0−

Divide-by-8 1 −0−01−−− 0−

Divide-by-16 1 11b 0 −00−−− 0−

R8C/34C Group 9. Clock Generation Circuit

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 134 of 723

9.7.1.1 High-Speed Clock Mode

The XIN clock divided by 1 (no d ivision), 2, 4, 8, or 16 is used as the CPU clock. If the CM14 bit is set to 0

(low-speed on-chip oscillator on) or the FRA00 bit in the FRA0 register is set to 1 (high-speed on-chip

oscillator on), fOCO can be used for timer RA.

Also, if the FRA00 bit is set to 1, fOCO40M can be used for timer RC and timer RD.

If the CM14 bit is set to 0 (low-speed on-chip oscillator on), fOCO-S can be used for the voltage detection

circuit.

9.7.1.2 Low-Speed Clock Mode

The XCIN clock divided by 1 (no division), 2, 4, 8, or 16 is used as the CPU clock.

In this mode, low consumption operation is enabled by stopping the XIN clock and the high-speed on-chip

oscillator, and by setting the FMR27 bit in the FMR2 register to 1 (low-current-consumption read mode

enabled). When the CPU clock is set to the XCIN clock divided by 1 (no division), 2, 4, or 8, low-current-

consumption read mode can be used. However, do not use low-current-consumption read mode when the

frequency of the selected CPU clock is 3 kHz or be low. After setting the divi de ratio of the C PU clock, set the

FMR27 bit to 1.

Also, if the FRA00 bit is set to 1, fOCO40M can be used for timer RC and timer RD.

If the CM14 bit is set to 0 (low-speed on-chip oscillator on), fOCO-S can be used for the voltage detection

circuit.

To enter wait mode from low-speed clock mode, lower consum ption current in wait mode is enabled by setti ng

the VCA20 bit in the VCA2 register to 1 (internal power low cons ump tion enabled).

To reduce the power consump tion, refer to 32. Reducing Power Consumption.

9.7.1.3 High-Speed On-Chip Oscillator Mode

The high-speed on-chip oscillator is used as the on-chip osci llator clock when the FRA00 bit in the FRA0

chip oscillator divided by 1 (no division), 2, 4, 8, or 16 is used as the CPU clock. If the FRA00 bit is set to 1,

fOCO40M can be used for timer RC and timer RD.

Also, if the CM14 bit is set to 0 (low-speed on-chip oscillator on), fOCO-S can be used for the voltage detection

circuit.

9.7.1.4 Low-Speed On-Chip Oscillator Mode

If the CM14 bit in the CM1 register is set to 0 (low-speed on-chip oscillator on) and the FRA01 bit in the FRA0

chip oscillator clock divided by 1 (no division), 2, 4, 8 or 16 is used as the CPU clock. The on-chip oscillator

clock is also the clock source for the peripheral function clocks. If the FRA00 bit is set to 1, fOCO40M can be

used for timer RC and timer RD.

Also, if the CM14 bit is set to 0 (low-speed on-chip oscillator on), fOCO-S can be used for the voltage detection

circuit.

In this mode, low consumption operation is enabled by stopping the XIN clock and the high-speed on-chip

oscillator, and by setting the FMR27 bit in the FMR2 register to 1 (low-current-consumption read mode

enabled). When the CPU clock is set to the low-speed on-chip oscillator clock divided by 4, 8, or 16, low-

current-consumption read mode can be used. After set ting the d ivide ratio of the CPU clock, set the FMR27 bit

to 1.

To enter wait mode from low-speed clock mode, lower consum ption current in wait mode is enabled by setti ng

the VCA20 bit in the VCA2 register to 1 (internal power low cons ump tion enabled).

To reduce the power consump tion, refer to 32. Reducing Power Consumption.

R8C/34C Group 9. Clock Generation Circuit

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 135 of 723

9.7.2 Wait Mode

Since the CPU clock st ops in wait mode, the CPU op erating with the CPU cl ock and the w atchdog t imer when

count source protection mode is disabled stop. Since the XIN clock, XCIN clock, and on-chip oscillator clock

do not stop, the peripheral functions using these clock s con tin ue operating.

9.7.2.1 Peripheral Function Clock Stop Function

If the CM02 bit is set to 1 (peripheral function clock stops in wait mode), the f1 , f2, f4, f 8, and f32 clocks st op

in wait mode. This reduces power consumption.

9.7.2.2 Entering Wait Mode

The MCU enters wait mode by executing the WAIT instruction or setting the CM30 bit in the CM3 register to 1

(MCU enters wait mode).

When the OCD2 bit in the OCD register is set to 1 (on-chip oscillator selected as system clock), set the OCD1

bit in the OCD register to 0 (oscillation stop detection interrupt disabled) before executing the WAIT

instruction or setting the CM30 bit in the CM3 register to 1(MCU enters wait mode).

If the MCU enters wa it mode while the OCD1 bit is set to 1 (osci llation stop detection interru pt enabled),

current consumption is not reduced because the CPU clock does not stop.

Enter wait mode after settin g the FMR27 bit to 0 (low-current-co nsumption read mode disabled). Do not ent er

wait mode while the FMR27 bit is 1 (low-current-consump tion read mode enabled).

9.7.2.3 Pin Status in Wait Mode

The I/O port retains the status immediately before the MCU enters wait mode.

R8C/34C Group 9. Clock Generation Circuit

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 136 of 723

9.7.2.4 Exiting Wait Mode

The MCU exits wait mode by a reset or peripheral function interrupt.

The peripheral function interrupts are affected by the CM02 bit. When the CM02 bit is set to 0 (peripheral

function clock does not stop in wait mode), the peripheral function interrupts other than A/D conversion

interrupts can be used to ex it wait mode. When th e CM02 bit is set to 1 (peripheral function clock stops in wait

mode), the peripheral fu nctions using the peripheral function clo ck stop and the peripheral function s operating

with external signals or the on-chip oscillator clock can be used to exit wait mode.

Table 9.4 lists Interrupts to Exit Wait Mode and Usage Conditions.

Table 9.4 Interrupts to Exit Wait Mode and Usage Conditions

Interrupt CM02 = 0 CM02 = 1

Serial interface interrupt Usable when operating with internal

or external clock Usable when operating with external

clock

Synchronous serial

communication unit inte rrupt/

I2C bus interface inter ru pt

Usable in all modes (Do not use)

Key input interrupt Usable Usable

A/D conversion interrupt (Do not use) (Do not use)

Timer RA interrupt Usable in all modes Usable if ther e is no filter in even t

counter mode.

Usable by selecting fOCO, fC, or

fC32 as count source.

Timer RB interrupt Usable in all modes (D o not use)

Timer RC interrupt Usable in all modes (Do not use)

Timer RD interrupt Usable in all modes Usable by selecting fOCO40M or

fC2 as count source

Timer RE interrupt Usable in all modes Usable when operating in real time

clock mode

INT interrupt Usable Usable (INT0 to INT4 can be used if

there is no filter.)

Voltage monitor 1 interrupt Usable Usable

Voltage monitor 2 interrupt Usable Usable

Oscillation stop detection

interrupt Usable (Do not use)

R8C/34C Group 9. Clock Generation Circuit

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 137 of 723

Figure 9.6 shows the Time from Wait Mode to First Instruction Execution following Exit after CM30 Bit in

CM3 Register is Set to 1 (MCU Enters Wait Mode).

To use a peripheral function interrupt to exi t wait mode, set up the following before setting the CM30 bit to 1.

(1) Set the I flag to 0 (maskable interrupt disabled).

(2) Set the interrupt priority level in bits ILVL2 to ILVL0 in the interrupt control registers of the peripheral

function interrupts to be used for exiting wait mode. Set bits ILVL 2 to ILVL0 of the pe ripheral function

interrupts that are not to be used for exiting wait mode to 000b (interrupt disabled).

(3) Operate the peripheral function to be used for exiting wait mode.

When the MCU exits by a peripheral function interrupt, the time (number of cycles) between interrupt request

generation and interrupt routine execut ion is determ in ed by the sett ings of the FMSTP bit in the FMR 0 regist er

and the VCA20 bit in the VCA2 register, as shown in Figure 9.6.

The clock set by bits CM35, CM36, an d CM37 in the CM3 register is used as the CPU clock when the MCU

exits wait mode by a peripheral function interrupt. At this time, the CM06 bit in the CM0 register and bits

CM16 and CM17 in the CM1 register automatically change.

Figure 9.6 Time from Wait Mode to First Instruction Execution following Exit after CM30 Bit in

CM3 Register is Set to 1 (MCU Enters Wait Mode)

Wait mode

Interrupt request generation

Flash memory

activation sequence

CPU clock

restart sequence

Internal power

stabilization time

100 µs (max.)

0 µs

100 µs (max.)

0 µs

(internal power

low consumption disabled)

(internal power

low consumption enabled)

(internal power

low consumption enabled)

(internal power

low consumption disabled

FMSTP Bit

(flash memory

operates)

(flash memory

stops)

FMR0 Register VCA2 Register

100 µs (max.)

Time until

Flash Memory

Activation ( T1)

Period of system clock

× 1 cycle + 60 µs

(max.)

Period of system clock

× 1 cycle

Period of CPU clock

× 2 cycles

Same as above

Time until

CPU Clock

Supply (T2)

Internal Power

Stabilization Time

(T0)

VCA20 Bit

The total of T0 to

T2 is the time

from wait mode to

first instruction

execution

following exit.

Remarks

R8C/34C Group 9. Clock Generation Circuit

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 138 of 723

Figure 9.7 shows the Time from Wait Mode to Interrupt Routine Execution after WAIT instruction is Executed.

To use a peripheral function interrupt to exit wait mode, set up the following before executing the WAIT

instruction.

(1) Set the interrupt priority level in bits ILVL2 to ILVL0 of the peri pheral function interrupts to be used for

exiting stop mode. Set bits ILVL2 to ILVL0 of the peripheral function inte rrupts th at are not to be used for

exiting stop mode to 000 b (interrupt disabled).

(2) Set the I flag to 1.

(3) Operate the peripheral function to be used for exiting stop mode.

When the MCU exits by a peripheral function interrupt, the time (number of cycles) between interrupt request

generation and interrupt routine execut ion is determ in ed by the sett ings of the FMSTP bit in the FMR 0 regist er

and the VCA20 bit in the VCA2 register, as shown in Figure 9.7.

The clock set by bits CM35, CM36, an d CM37 in the CM3 register is used as the CPU clock when the MCU

exits wait mode by a peripheral function interrupt. At this time, the CM06 bit in the CM0 register and bits

CM16 and CM17 in the CM1 register automatically change.

Figure 9.7 Time from Wait Mode to Interrupt Routine Exe cution after WAIT instruction is

Executed

Wait mode

Interrupt request generation

Flash memory

activation sequence

CPU clock

restart sequence

Internal power

stabilization time

100 µs (max.)

0 µs

100 µs (max.)

0 µs

(internal p ower

low consumption disabled)

(internal p ower

low consumption enabled)

(internal p ower

low consumption enabled)

(internal p ower

low consumption disabled

FMSTP Bit

(flash memory

operates)

(flash memory

stops)

FMR0 Register VCA2 Register

100 µs (max.)

Time until

Flash Memory

Activation ( T1)

Period of system clock

× 1 cycle + 60 µs

(max.)

Period of system clock

× 1 cycle

Period of CPU clock

× 2 cycles

Same as above

Time until

CPU Clock

Supply (T2)

Internal Power

Stabilizati on Time

(T0)

Time for

Interrupt

Sequence (T3)

Period of CPU c lock

× 20 cycles

Same as above

VCA20 Bit

The total of T0

to T3 is the time

from wait mode t o

interrupt rout ine

execution.

Remarks

Interrupt sequence

R8C/34C Group 9. Clock Generation Circuit

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 139 of 723

9.7.3 Stop Mode

Since all oscillator circuits except fOCO-WDT stop in stop mode, the CPU and peripheral fu nction cl ocks st op

and the CPU and the peripheral functions operating with these clocks also stop. The least power required to

operate the MCU is in stop mode. If the voltage applied to the VCC pin is VRAM or more, the contents of

internal RAM is retained.

The peripheral functions clocked by external signals conti nue operating.

Table 9.5 lists Interrupts to Exit Stop Mode and Usage Condition s.

9.7.3.1 Entering Stop Mode

The MCU enters stop mode when the CM10 bit in the CM1 register is set to 1 (all clocks stop). At the same

time, the CM06 bit in the CM0 register is set to 1 (divide-by-8 mode).

To use stop mode, set the following before the MCU enters stop mode:

•Bits OCD1 to OCD0 in the OCD register = 00b

•CM35 bit in CM3 register = 0 (settings of CM06 bit in CM0 register and bits CM16 and CM17 in CM1

Enter stop mode after setting the FMR27 bit to 0 (low-current-consumption read mode d isabled). Do not enter

stop mode while the FMR27 bit is 1 (low-current-con sumption read mode enabled).

9.7.3.2 Pin Status in Stop Mode

The I/O port retains the status before the MCU enters stop mode.

However, when the CM13 bit in the CM 1 register is set to 1 (XIN-XOUT pin), the XOUT(P4_7) pin is held

“H”. When the CM13 bit is set to 0 (input ports P4_6 and P4_7), the P4_7(XOUT pin) is held in an input status.

Table 9.5 Interrupts to Exit Stop Mode and Usage Conditions

Interrupt Usage Conditions

Key input interrupt Usable

INT0 to INT4 interrupt Usable if there is no filter

Timer RA interrupt Usable if there is no filter when external pulse is counted in event counter

mode

Serial interface interrupt When external clock selected

Voltage monitor 1 interrupt Usable in digital filter disabled m ode (VW1 C1 b it in VW1C re gister is set to 1)

Voltage monitor 2 interrupt Usable in digital filter disabled m ode (VW2 C1 b it in VW2C re gister is set to 1)

R8C/34C Group 9. Clock Generation Circuit

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 140 of 723

9.7.3.3 Exiting Stop Mode

The MCU exits stop mode by a reset or peripheral function interrupt.

Figure 9.8 shows the Time from Stop Mode to Interrupt Routine Execution.

To use a peripheral function interrupt to exi t stop mode, set up the following before setting the CM10 bit to 1.

(1) Set the interrupt priority level in bits ILVL2 to ILVL0 of the peri pheral function interrupts to be used for

exiting stop mode. Set bits ILVL2 to ILVL0 of the peripheral function inte rrupts th at are not to be used for

exiting stop mode to 000 b (interrupt disabled).

(2) Set the I flag to 1.

(3) Operate the peripheral function to be used for exiting stop mode.

When the MCU exits stop mode by a peripheral function interrupt, the interrupt sequence is executed when

an interrupt request is generated and the CPU clock supply starts.

The clock used immediately before stop mode divided by 8 is used as the CPU clock when t he MCU exits stop

mode by a peripheral function interrupt. To enter stop mode, set the CM35 bit in the CM3 register to 0 (settings

of CM06 bit in CM0 register and bits CM16 and CM17 in CM1 register enabled)

Figure 9.8 Time from Stop Mode to Interrupt Routine Execution

100 µs (max.)

FMSTP Bit

(flash memory operates)

(flash memory stops)

FMR0 Register

Period of system clock

× 1 cycle + 60 µs

(max.)

Period of system clock

× 1 cycle

Period of CPU clock

× 2 cycles

Same as above

Time until

CPU Clock

Supply (T3)

Interrupt request generation

Internal Power

Stabilization Time (T0)

Time until

Flash Memory

Activation ( T2)

100 ms (max. )

Stop mode Internal power

stabilizat ion time Oscillation time of CPU clock

source used immediately

before stop mode

T4T2

Interrupt sequence

Flash memory

activation sequence

CPU clock

restart sequence

Time for

Interrupt

Sequence (T4)

Period of CPU c lock

× 20 cycles The total of T0

to T4 is the time

from wait mode t o

interrupt rout ine

execution.

Remarks

Same as above

100 µs (max.)

R8C/34C Group 9. Clock Generation Circuit

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 141 of 723

Figure 9.9 shows the State Transitions in Power Control Mode.

Figure 9.9 State Transitions in Power Control Mode

CM10 = 1

CPU operation stops

Stop mode

State Transitions in Power Control Mode

Reset

Wait mode

Low-speed on-chip oscillator mode

CM07 = 0

CM14 = 0

OCD2 = 1

FRA01 = 0

High-speed on-chip osci llator mode

CM07 = 0

OCD2 = 1

FRA00 = 1

FRA01 = 1

High-speed clock mode

CM05 = 0

CM07 = 0

CM13 = 1

OCD2 = 0

Standard operating mode

CM14 = 0

OCD2 = 1

FRA01 = 0

CM05 = 0

CM13 = 1

OCD2 = 0

CM05 = 0

CM13 = 1

OCD2 = 0

OCD2 = 1

FRA00 = 1

FRA01 = 1

FRA00 = 1

FRA01 = 1

CM14 = 0

FRA01 = 0

All oscillators stop

(except fOCO-WDT)

InterruptWAIT instructionInterrupt

CM03, CM04, C M 05 , CM07: Bits in CM0 register

CM13, CM14: Bits in CM1 register

OCD2: Bit in OCD register

FRA00, FRA01: Bits in FRA0 register

Low-speed clock mode

CM04 = 1

CM07 = 1

CM03 = 0

CM07 = 0

CM14 = 0

OCD2 = 1

FRA01 = 0

CM03 = 0

CM04 = 1

CM07 = 1

CM07 = 0

OCD2 = 1

FRA00 = 1

FRA01 = 1

CM03 = 0

CM04 = 1

CM07 = 1

CM03 = 0

CM04 = 1

CM07 = 1

CM05 = 0

CM07 = 0

CM13 = 1

OCD2 = 0

R8C/34C Group 9. Clock Generation Circuit

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 142 of 723

9.8 Oscillation Stop Detection Function

The oscillation stop detection function detects the stop of the XIN clock oscillating circuit.

The oscillation stop detection function can be enabled and disabled by the OCD0 bit in the OCD register.

Table 9.6 lists the Specifications of Oscillation Stop Detection Function.

When the XIN clock is the CPU clock source and bits OCD1 to OCD0 are set to 11b, the MCU is placed in the

following state if the XIN clock stops.

•OCD2 bit in OCD register = 1 (on-chip oscillator clock selected)

•OCD3 bit in OCD register = 1 (XIN clock stops)

•CM14 bit in CM1 register = 0 (low-speed on-chip oscillator oscillates)

•Oscillation stop detection interrupt request is generated

Table 9.6 Specifications of Oscillation Stop Detection Function

Item Specification

Oscillation stop detection clock and

frequency bandwidth f(XIN) ≥ 2 MHz

Enabled condition for oscillation stop

detection function Bits OCD1 to OCD0 set to 11b

Operation at oscillation stop detection Oscillation stop detection interrupt generated

R8C/34C Group 9. Clock Generation Circuit

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 143 of 723

9.8.1 How to Use Oscillation Stop Detection Function

•The oscillation stop detection interrupt shares a vector with the voltage monitor 1 interrupt, the voltage

monitor 2 interr upt, and the watchdog timer inter rupt. To use the oscillation stop detection int errupt and

watchdog timer interrupt, the interrupt source needs to be determined.

Table 9.7 lists the Determination of Interrupt Sources for Oscillation Stop Detection, Watchdog Timer,

Voltage Monitor 1, or Voltage Monitor 2 Interrupt. Figure 9.11 shows an Example of Determining Interrupt

Sources for Oscillation Stop Detection, Watchdog Timer, Voltage Monitor 1, or Voltage Monito r 2 Interrupt.

•When the XIN clock restarts after oscillation stop, switch the XIN clock to the clock source for the CPU clock

and the peripheral functions by a program .

Figure 9.10 shows the Procedure for Switching Clock Source from Low-Speed On-Chip Oscillator to XIN

Clock.

•To enter wait mode while the oscillation stop detection function is used, set the CM02 bit to 0 (peripheral

function clock does no t stop in wait mode).

•Since the oscillation stop detection function is a function for cases where the XIN clock is stopped by an

external cause, set bits OCD1 to OCD0 to 00b to stop or start the XIN clock by a program (select stop mode or

change the CM05 bit).

•This function cannot be used when the XIN clock frequency is below 2 M Hz. In this case, set bits OCD1 to

OCD0 to 00b.

•To use the low-speed on-chip oscillator clock as the clock source for the CPU clock and the peripheral

functions after detecting the oscillation stop, set the FRA01 bit i n the FRA0 register to 0 (low-speed on-ch ip

oscillator selected) and bits OCD1 to OCD0 to 11b.

To use the high-speed on-chip oscillator clock as the clock source for the CPU clock and the peripheral

functions after detecting the oscillation stop, first set the FRA00 bit to 1 (high-speed on-chip oscillator

oscillates) and the FRA01 bit to 1 (high-speed on-chip oscillator selected). Then set bits OCD1 to OCD0 to

11b.

R8C/34C Group 9. Clock Generation Circuit

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 144 of 723

Figure 9.10 Procedure for Switching Clock Source from Low-Speed On-Chip Oscillator to XIN

Clock

Table 9.7 Determination of Interrupt Sources for Oscillation Stop Detection, Watchdog Timer,

Voltage Monitor 1, or Voltage Monitor 2 Interrupt

Generated Interrupt Source Bit Indicating Interrupt Source

Oscillation stop detection

((a) or (b)) (a) OCD3 bit in OCD register = 1

(b) OCD1 to OCD0 bits in OCD register = 11b and OCD2 bit = 1

Watchdog timer VW2C3 bit in VW2C register = 1

Voltage monitor 1 VW1C2 bit in VW1C register = 1

Voltage monitor 2 VW2C2 bit in VW2C register = 1

OCD3 to OCD0: Bits in OCD registe r

Switch to XIN clock

Check several times

whether OCD3 bit is set to 0

(XIN clock oscillates)

Set bits OCD1 to OCD0 to 00b

Set OCD2 bit to 0

(XIN clock selected)

End

YES

R8C/34C Group 9. Clock Generation Circuit

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 145 of 723

Figure 9.11 Example of Determining Interrupt Sources for Oscillation Stop Detection, Watchdog

Timer, Voltage Monitor 1, or Voltage Monitor 2 Interrupt

Determinat i on of

Interrupt sources

OCD3 = 1?

(XIN cl ock stops)

OCD1 = 1

(oscillation stop detection

interrupt enabled) and OCD2 = 1

(on-chip oscillator clock

selected a s system clock) ?

VW2C3 = 1?

(watchdog timer underflow)

VW2C2 = 1?

(Vdet2 passed)

To oscillation stop detection

interrupt rout i ne To volt age m oni to r 1

interrupt rou t i ne

To voltage monitor 2

interrupt routi ne

To watchdog tim er

interrupt routi ne

YES

Note:

1. This disables multiple oscillation stop detection interrupts.

OCD1 to OCD3: Bits in OCD register

VW2C2, VW2C3: Bits in VW2C register

Set OC D1 bit to 0

(oscillation stop detection

interrupt disabled ) (1)

R8C/34C Group 9. Clock Generation Circuit

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 146 of 723

9.9 Notes on Clock Generation Circuit

9.9.1 Stop Mode

To enter stop mode, set the FMR01 bit in the FMR0 register to 0 (CPU r ewrite mode disabled) and then the

CM10 bit in the CM1 register to 1 (stop mode). An instruction queue pre-reads 4 bytes from the instr uction

which sets the CM10 bit to 1 (stop mode) and the program stops.

Insert at least four NOP i nstructio ns foll owing t he JMP.B in st ruction after the instruction whi ch sets the C M10

bit to 1.

• Program example to enter stop mode

BCLR 1,FMR 0 ; CPU rewrite mode disabled

BCLR 7, FMR2 ; Low-current-consump tion read mode

disabled

BSET 0,PRCR ; Writing to CM1 register enabled

FSET I ; Interrupt enabled

BSET 0,CM1 ; Stop mode

JMP.B LABEL_001

LABEL_001:

NOP

9.9.2 Wait Mode

To enter wait mode by settin g the CM30 bit to 1, set the FMR01 bit in the FMR0 regi ster to 0 (CPU rewrite

mode disabled) before setting the CM30 bit to 1.

To enter wait mode with the WAIT instruction, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode

disabled) and then execute the WAIT instruction. An instruction queue pre-reads 4 bytes from the instruction to

set the CM30 bit to 1 (MCU enters wait mode) or the WAIT instruction, and then the program stops. Insert at

least four NOP instructions after the instruction to set the CM30 bit to 1 (MCU ent ers wait m ode) or the WAIT

instruction.

• Program example to execute the WAIT instruction

BCLR 1,FMR 0 ; CPU rewrite mode disabled

BCLR 7, FMR2 ; Low-current-consump tion read mode

disabled

FSET I ; Interrupt enabled

WAIT ; Wait mode

NOP

• Program example to ex ecute the instruction to set the CM30 bit to 1

BCLR 1, FMR0 ; CPU rewrite mode disabled

BCLR 7, FMR2 ; Low-current-consump tion read mode

disabled

BSET 0, PRCR ; Writing to CM3 register enabled

FCLR I ; Interrup t disabled

BSET 0, CM3 ; Wait mode

NOP

BCLR 0, PRCR ; Writing to CM3 register disabled

FSET I ; Interrupt enabled

R8C/34C Group 9. Clock Generation Circuit

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 147 of 723

9.9.3 Oscillation Stop Detection Function

Since the oscillation stop detection function cannot be used if the XIN clock frequency is below 2 MHz, set bits

OCD1 to OCD0 to 00b.

9.9.4 Oscillation Circuit Constants

Consult the oscillator manufacturer to determine the optimal oscillation circuit constants for the user system.

To use the MCU with supply voltage below VCC = 2.7 V, it is recommended to set the CM11 bit in the CM1

R8C/34C Group 10. Protection

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 148 of 723

10. Protection

The protection function protects important registers from bein g easily overwritten if a program runs ou t of control.

The registers protected by the PRCR register are as follows:

• Registers protected by PRC0 bit: Registers CM0, CM1, CM3, OCD, FRA0, FRA1, FRA2, and FRA3

• Registers protected by PRC1 bit: Registers PM0 and PM1

• Registers protected by PRC2 bit: PD0 register

• Registers protected by PRC3 bit: Registers OCVREFCR, VCA2, VD1LS, VW0C, VW1C, and VW2C

10.1 Register

10.1.1 Protect Register (PRCR)

Notes:

1. The PRC2 bit is set to 0 after setting it to 1 (write enabled) and writing to the SFR area. Change the register

protected by the PRC2 bit with the next instruction after that used to set the PRC2 bit to 1. Do not allow interrupts

or DTC activation between the instruction to set to the PRC2 bit to 1 and the next instruction.

2. Bits PRC0, PRC1, and PRC3 are not set to 0 even after setting them to 1 (write enabled) a nd writing to the SFR

areas. Set these bits to 0 by a program.

Address 000Ah

Bitb7b6b5b4b3b2b1b0

Symbol — — — — PRC3 PRC2 PRC1 PRC0

After Reset00000000

Bit Symbol Bit Name F unction R/W

b0 PRC0 Protect bit 0 Enables writing to registers CM0, CM1, CM3, OCD, FRA0,

FRA1, FRA2, and FRA3.

0: Write disabled

1: Write enabled (2)

R/W

b1 PRC1 Protect bit 1 Enables writing to registers PM0 and PM1.

0: Write disabled

1: Write enabled (2)

R/W

b2 PRC2 Protect bit 2 Enables writing to the PD0 register.

0: Write disabled

1: Write enabled (1)

R/W

b3 PRC3 Protect bit 3 Enables writing to registers OCVREFCR, VCA2, VD1LS,

VW0C, VW1C, and VW2C.

0: Write disabled

1: Write enabled (2)

R/W

b4 — Reserved bits Set to 0. R/W

b5 —

b6 —

b7 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

R8C/34C Group 11. Interrupts

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 149 of 723

11. Interrupts

11.1 Overview

11.1.1 Types of Interrupts

Figure 11.1 shows the Types of Interrupts.

Figure 11.1 Types of Interrupts

•Maskable interrupts: These interrupts are enabled or disabled by th e interrupt enable flag (I flag).

The interrupt priority can be changed based on the interrupt priority level.

•Non-maskable interrupts: These interrupts are not enabled or disabled by the interrupt enable flag (I flag).

The interrupt priority cannot be changed based on the interrupt priority level.

Interrupts

(non-maskable interrupts)

Hardware

Software

(non-maskable interrupts)

(maskable interrupts)

Special

Peripheral function (1)

Undefined instruction (UND instruction)

Overflow (INTO instruction)

BRK instruction

INT instruction

Watchdog timer

Oscillation stop detection

Voltage monitor 1 (3)

Voltage monitor 2 (3)

Single step (2)

Address break (2)

Address match

Notes:

1. Peripheral function interrupts are generated by the peripheral functions in the MCU.

2. Do not use these interrupts. This is provided exclusively for use by development tools.

3. A non-maskable or maskable interrupt can be selected by bits IRQ1 SEL and IRQ2SEL in the CMPA regist er.

R8C/34C Group 11. Interrupts

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 150 of 723

11.1.2 Software Interrupts

A software interrupt is generated when an instructio n is executed. Software interrupts are non-maskable.

11.1.2.1 Undefined Instruction Interrupt

An undefined instruction interrupt is gene rated when the UND instruction is executed.

11.1.2.2 Overflow Interrupt

An overflow interrupt is generated when the O flag is set to 1 (arithmetic operation overflow) and the INTO

instruction is executed. Instructions that set the O flag are as follows:

ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, and SUB.

11.1.2.3 BRK Interrupt

A BRK interrupt is generated when the BRK instruction is executed.

11.1.2.4 INT Instruction Interrupt

An INT instruction interrupt is generated when the INT instruction is executed. Software interrupt numbers 0 to

63 can be specified with the INT instruction. Because some software interrupt numbers are assigned to

peripheral function interrupts, the same interrupt routine as for peripheral function interrupts can be executed by

executing the INT instruction.

For software interrupt numb ers 0 to 31, the U flag is saved on the st ack during instruction execution and the U

flag is set to 0 (ISP selected) before the interrupt sequence is executed. The U flag is restored from the stack

when returning from the interrupt ro utine. For software interrupt numbers 32 to 63, the U flag does not change

state during instruction execution, and the selected SP is used.

R8C/34C Group 11. Interrupts

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 151 of 723

11.1.3 Special Interrupts

Special interru pts are non-maskable.

11.1.3.1 Watchdog Timer Interrupt

A watchdog timer interrupt is generated by the watchdog timer. For details, refer to 14. Watchdog Timer.

11.1.3.2 Oscillation Stop Detection Interrupt

An oscillation stop detectio n interrupt is generated by th e oscillation stop detection function. For details of the

oscillation stop detection function, refer to 9. Clock Generation Circuit.

11.1.3.3 Voltage Monitor 1 Interrupt

A voltage monitor 1 in terrupt is generated by the voltage detection circ uit. A non-maskable or maskable

interrupt can be selected by IRQ1SEL bit in the CMPA register. For details of the voltage detection circuit,

refer to 6. Voltage Detection Circuit.

11.1.3.4 Voltage Monitor 2 Interrupt

A voltage monitor 2 in terrupt is generated by the voltage detection circ uit. A non-maskable or maskable

interrupt can be selected by IRQ2SEL bit in the CMPA register. For details of the voltage detection circuit,

refer to 6. Voltage Detection Circuit.

11.1.3.5 Single-Step Interrupt, and Address Break Interrupt

Do not use these interrupts. They are provided exclu sively for use by devel opment tools.

11.1.3.6 Address Match Interrupt

An address match interrupt is generated immediately before executing an instruction that is stored at an address

indicated by registers RMAD0 to RMAD1 if the AIER00 bit in the AIER0 register or the AIER10 bit in the

AIER1 register is set to 1 (address match interrupt enabled).

For details of the address match int e rr upt, refer to 11.6 Address Match Interrupt.

11.1.4 Peripheral Function Interrupts

A peripheral function interrupt is ge nerat ed by a peripheral function in the MCU. Peripheral function interrupts

are maskable. Refer to Table 11.2 Relocatable Vector Tables for sources of the corresponding peripheral

function interrupt. For details of peripheral functions, refer to the descriptions of individual peripheral

functions.

R8C/34C Group 11. Interrupts

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 152 of 723

11.1.5 Interrupts and Interrupt Vectors

There are 4 bytes in each vector. Set the starting address of an interrupt routine in each interrupt vector. When

an interrupt request is acknowledged, the CPU branches to the address set in the corresponding interrupt vector.

Figure 11.2 sh ow s an In terrupt Vector.

Figure 11.2 Interrupt Vector

11.1.5.1 Fixed Vector Tables

The fixed vector tables are allocated addresses 0FFDCh to 0FFFFh.

Table 11.1 lists the Fixed Vector Tab les. The vector addresses (H) of fixed vectors are used by the ID code

check function. For details, refer to 31.3 Functions to Prevent Flash Memory from being Rewritten.

Note:

1. Do not use these interrupts. They are provided exclusively for use by development tools.

Table 11.1 Fixed Vector Tables

Interrupt Source Vector Addresses

Address (L) to (H) Remarks Reference

Undefined instruction

0FFDCh to 0FFDFh

Interrupt with

UND instruction R8C/Tiny Series

Software Manual

Overflow 0FFE0h to 0FFE3h Interrupt with

INTO instruction

BRK instruction 0FFE4h to 0FFE7h

If the content of address

0FFE7h is FFh, program

execution starts from

the address shown by

the vector in the

relocatable vector table.

Address match 0FFE8h to 0FFEBh 11.6 Add re ss Match

Interrupt

Single step (1) 0FFECh to 0FFEFh

Watchdog timer,

Oscillation stop detection,

Voltage moni to r 1,

Voltage monitor 2

0FFF0h to 0FFF3h 14. Watchdog Timer

9. Clock Generation Cir cuit

6. Voltage D ete ction Circuit

Address break (1) 0FFF4h to 0FFF7h

(Reserved) 0FFF8h to 0FFFBh

Reset 0FFFCh to 0FFFFh 5. Resets

Vector address (L)

Vector address (H)

MSB LSB

Low-order address

Middle-order address

High-order address0 0 0 0

0 0 0 0 0 0 0 0

R8C/34C Group 11. Interrupts

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 153 of 723

11.1.5.2 Relocatable Vector Tables

The relocatable vector tables occupy 256 bytes beginning from the starting address set in the INTB register.

Table 11.2 lists the Relocatable Vector Tables.

Notes:

1. These addresses are relative to those in the INTB register.

2. Selectable by the IICSEL bit in the SSUIICSR register.

3. These interrupts are no t disabled by the I flag.

Table 11.2 Relocatable Vector Tables

Interrupt Source Vector Addresses (1)

Address (L) to Address (H)

Software

Interrupt

Number

Interrupt Control

Reference

BRK instruction (3) +0 to +3 (0000h to 0003h) 0 −R8C/Tiny Series

Software Manual

Flash memory ready +4 to +7 (0004h to 0007h) 1 FMRDYIC 31. Flash Memory

(Reserved) 2 to 5 −−

INT4 +24 to +27 (0018h to 001Bh) 6 INT4IC 11.4 INT Interrupt

Timer RC +28 to +31 (001Ch to 001Fh) 7 TRCIC 19. Timer RC

Timer RD0 +32 to +35 (0020h to 0023h) 8 TRD0IC 20. Timer RD

Timer RD1 +36 to +39 (0024h to 0027h) 9 TRD1IC

Timer RE +40 to +43 (0028 h to 002Bh) 10 TREIC 21. Timer RE

UART2 transmit/NACK2 +44 to +47 (002Ch to 002Fh) 11 S2TIC 23. Serial Interface

(UART2)

UART2 receive/ACK2 +48 to +51 (0030h to 0033h) 12 S2RIC

Key input +52 to +55 (0034h to 0037h) 13 KUPIC 11.5 Key Input Interrupt

A/D conversion +56 to +59 (0038 h to 003Bh) 14 ADIC 28. A/D Converter

Synchronous serial

communication unit / I2C

bus interface (2)

+60 to +63 (003Ch to 003Fh) 15 SSUIC/IICIC

25. Synchronous Serial

Communication Unit

(SSU),

26. I2C bus Interface

(Reserved) 16 −−

UART0 transmit +68 to +71 (0044h to 0047h) 17 S0TIC 22. Serial Interface

(UARTi (i = 0 or 1))

UART0 receive +72 to +75 (0048h to 004Bh) 18 S0RIC

UART1 transmit +76 to +79 (004Ch to 004Fh) 19 S1TIC

UART1 receive +80 to +83 (0050h to 0053h) 20 S1RIC

INT2 +84 to +87 (0054h to 0057h) 21 INT2IC 11.4 INT Inte rrupt

Timer RA +88 to +91 (0058 h to 005Bh) 22 TRAIC 17. Timer RA

(Reserved) 23 −−

Timer RB +96 to +99 (0060 h to 0063h) 24 TRBIC 18. Timer RB

INT1 +100 to +103 (0064h to 0067h) 25 INT1IC 11.4 INT Interrupt

INT3 +104 to +107 (0068h to 006Bh) 26 INT3IC

(Reserved) 27 −−

(Reserved) 28 −−

INT0 +116 to +119 (0074h to 0077h) 29 INT0IC 11.4 INT Interrupt

UART2 bus collision detection

+120 to +123 (0078h to 007Bh) 30 U2BCNIC 23. Serial Interface

(UART2)

(Reserved) 31 −−

Software (3) +128 to +131 (0080h to 0083h) to

+164 to +167 (00A4h to 00A7h) 32 to 41 −R8C/Tiny Series

Software Manual

(Reserved) 42 to 49 −−

Voltage monitor 1 +200 to +203 (00C8h to 00CBh) 50 VCMP1IC 6. Voltage Detection

Circuit

Voltage monitor 2 +204 to +207 (00CCh to 00CFh) 51 VCMP2IC

(Reserved) 52 to 55 −−

Software (3) +224 to +227 (00E0h to 00E3h) to

+252 to +255 (00FCh to 00FFh) 56 to 63 −R8C/Tiny Series

Software Manual

R8C/34C Group 11. Interrupts

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 154 of 723

11.2 Registers

11.2.1 Interrupt Control Register

(TREIC, S2TIC, S2RIC, KUPIC, ADIC, S0TIC, S0RIC, S1TIC, S1RIC, TRAIC,

TRBIC, U2BCNIC, VCMP1IC, VCMP2IC)

Note:

1. Only 0 can be wri tten to the IR bit. Do not write 1 to this bit.

Rewrite the interrupt control register when an interrupt request corresponding to the register is not generated.

Refer to 11.8.5 Rewriting Interrupt Control Register.

Address 004Ah (TREIC), 004Bh (S2TIC), 004Ch (S2RIC), 004Dh (KUPIC), 004Eh (ADIC),

0051h (S0TIC), 0052h (S0RIC), 0053h (S1TIC), 0054h (S1RIC), 0056h (TRAIC),

0058h (TRBIC), 005Eh (U2BCNIC), 0072h (VCMP1IC), 0073h (VCMP2IC),

Bitb7b6b5b4b3b2b1b0

Symbol — — — — IR ILVL2 ILVL1 ILVL0

After ResetXXXXX000

Bit Symbol Bit Name Function R/W

b0 ILVL0 Interrupt priority level select bit b2 b1 b0

0 0 0: Level 0 (interrupt disabled)

0 0 1: Level 1

0 1 0: Level 2

0 1 1: Level 3

1 0 0: Level 4

1 0 1: Level 5

1 1 0: Level 6

1 1 1: Level 7

R/W

b1 ILVL1 R/W

b2 ILVL2 R/W

b3 IR Interrupt request bit 0: No interrupt requested

1: Interrupt requested R/W

(1)

b4 — Nothing is assigned. If necessary, set to 0.

When read, the content is undefined. —

b5 —

b6 —

b7 —

R8C/34C Group 11. Interrupts

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 155 of 723

11.2.2 Interrupt Control Register (FMRDYIC, TRCIC, TRD0IC, TRD1IC, SSUIC/IICIC)

Note:

1. Selectable by the IICSEL bit in the SSUIICSR register.

Rewrite the interrupt control register when an interrupt request corresponding to the register is not generated.

Refer to 11.8.5 Rewriting Interrupt Control Register.

Address 0041h (FMRDYIC), 0047h (TRCIC), 0048h (TRD0IC), 0049h (TRD1IC), 004Fh (SSUIC/IICIC (1))

Bitb7b6b5b4b3b2b1b0

Symbol — — — — IR ILVL2 ILVL1 ILVL0

After ResetXXXXX000

Bit Symbol Bit Name Function R/W

b0 ILVL0 Interrupt priority level select bit b2 b1 b0

0 0 0: Level 0 (interrupt disabled)

0 0 1: Level 1

0 1 0: Level 2

0 1 1: Level 3

1 0 0: Level 4

1 0 1: Level 5

1 1 0: Level 6

1 1 1: Level 7

R/W

b1 ILVL1 R/W

b2 ILVL2 R/W

b3 IR Interrupt request bit 0: No interrupt requested

1: Interrupt requested R

b4 — Nothing is assigned. If necessary, set to 0.

When read, the content is undefined. —

b5 —

b6 —

b7 —

R8C/34C Group 11. Interrupts

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 156 of 723

11.2.3 INTi Interrupt Control Register (INTiIC) (i = 0 to 4)

Notes:

1. Only 0 can be wri tten to the IR bit. (Do not wri te 1 to this bit.)

2. If the INTiPL bit in the INTEN register is set to 1 (both edges), set the POL bit to 0 (falling edge selected).

3. The IR bit may be set to 1 (interrupt requested) when the POL bit is rewritten. Refer to 11.8.4 Changing

Interrupt Sources.

Rewrite the interrupt control register when an interrupt request corresponding to the register is not generated.

Refer to 11.8.5 Rewriting Interrupt Control Register.

Address 0046h (INT4IC), 005 5h (INT2IC), 0059h (INT1IC), 005Ah (INT3IC),

005Dh (INT 0IC)

Bitb7b6b5b4b3b2b1b0

Symbol — — — POL IR ILVL2 ILVL1 ILVL0

After Reset X X 0 0 X 0 0 0

Bit Symbol Bit Name Function R/W

b0 ILVL0 Interrupt priority level select bit b2 b1 b0

0 0 0: Level 0 (interrupt disabled)

0 0 1: Level 1

0 1 0: Level 2

0 1 1: Level 3

1 0 0: Level 4

1 0 1: Level 5

1 1 0: Level 6

1 1 1: Level 7

R/W

b1 ILVL1 R/W

b2 ILVL2 R/W

b3 IR Interrupt request bit 0: No interrupt requested

1: Interrupt requested R/W

(1)

b4 POL Polarity switch bit (3) 0: Falling edge selected

1: Rising edge selected (2) R/W

b5 — Reserved bit Set to 0. R/W

b6 — Nothing is assigned. If necessary, set to 0.

When read, the content is undefined. —

b7 —

R8C/34C Group 11. Interrupts

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 157 of 723

11.3 Interrupt Control

The following describes enabling and disabling maskable interrupts and setting the acknowledgement priority. This

description does not apply to non -maskable interrupts.

Use the I flag in the FLG register, IPL, and bits ILVL2 to ILVL0 in the corresponding interru pt control register to

enable or disable a maskable interrupt. Whether an interrupt is requested or not is indicated by the IR bit in the

corresponding interrupt control register.

11.3.1 I Flag

The I flag enables or disables maskable interrupts. Setting the I flag to 1 (enabl ed) enables maskable interrupt s.

Setting the I flag to 0 (disabled) disables all maskable interrupts.

11.3.2 IR Bit

The IR bit is set t o 1 (interru pt requested) when an interrupt request is generated. After the interrupt request is

acknowledged and the CPU bran ches to the corresponding interrupt vector, the IR bi t is set to 0 (no interrupt

requested).

The IR bit can be set to 0 by a program. Do not write 1 to this bit.

However, the IR bit operations of the timer RC interrupt, the timer RD interrupt, the synchronous serial

communication unit interrupt the I2C bus interface interrupt, and the flash memory interrupt are different. Refer

to 11.7 Timer RC Interrupt, Timer RD Interrupt, Synchronous Serial Communication Unit Interrupt,

I2C bus Interface Interrupt, and Flash Memory Interrupt (Interrupts with Multiple Interrupt Request

Sources).

11.3.3 Bits ILVL2 to ILVL0, IPL

Interrupt priority levels can be set using bits ILVL2 to ILVL0.

Table 11.3 lists the Settings of Interrupt Priority Levels and Table 11.4 lists the Interrupt Priority Levels

Enabled by IPL.

The following are the conditions when an interrupt is acknowledged:

•I flag = 1

•IR bit = 1

•Interrupt priority level > IPL

The I flag, IR bit, bits ILVL2 to ILVL0, and IPL are independent of each other. They do not affect one another.

Table 11.3 Settings of Interrupt Priority

Levels

Bits ILVL2 to ILVL0 Interrupt Priority Level Priority

000b Level 0 (interrupt disabled) −

001b Level 1 Low

010b Level 2

011b Level 3

100b Level 4

101b Level 5

110b Level 6

111b Level 7 High

Table 11.4 Interrupt Priority Levels Enabled by

IPL

IPL Enabled Interrupt Priority Level

000b Interrupt level 1 and above

001b Interrupt level 2 and above

010b Interrupt level 3 and above

011b Interrupt level 4 and above

100b Interrupt level 5 and above

101b Interrupt level 6 and above

110b Interrupt level 7 and above

111b All maskable interrupts are disabled

R8C/34C Group 11. Interrupts

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 158 of 723

11.3.4 Interrupt Sequence

The following describes an interrupt sequence which is performed from when an interrupt request is

acknowledged until the interrupt routine is executed.

When an interrupt request is generated while an instruction is being executed, the CPU det ermines it s interrupt

priority level after the instruction is completed. The CPU starts the interrupt sequence from the following cycle.

However, for the SMOVB, SMOVF, SSTR, or RMPA instruction, if an interrupt request is generated while the

instruction is being executed, the MCU su spends the instruction to start the inter rupt sequence. The interrup t

sequence is performed as indicated below.

Figure 11.3 shows the Time Required for Executing Interrupt Sequence.

(1) The CPU obtains interrupt information (interrupt number and interrupt request level) by reading address

00000h. The IR bit for the corresponding interrupt is set to 0 (no interrupt requested). (2)

(2) The FLG register is saved to a temporary register (1) in the CPU immediately before entering the interru pt

sequence.

(3) The I, D and U flags in the FLG register are set as follows:

The I flag is set to 0 (interrupts disabled).

The D flag is set to 0 (single-step interrupt disabled).

The U flag is set to 0 (ISP selected).

However, the U flag does not chan ge state if an INT instruction for software interrupt number 32 to 63 is

executed.

(4) The CPU internal temporary register (1) is saved on the stack.

(5) The PC is saved on the stack.

(6) The interrupt priority level of the acknowledged interrupt is set in the IPL.

(7) The starting address of the interrupt routine set in the interrupt vector is stored in the PC.

After the inte rrupt sequence is compl eted, instructions are executed from the starting address of the interrupt

routine.

Figure 11.3 Time Required for Executing Interrupt Sequence

Notes:

1. These registers cannot be accessed by the user.

2. Refer to 11.7 Timer RC Interrupt, Timer RD Interrupt, Synchronous Serial Communication Unit

Interrupt, I2C bus Interface Interrupt, and Flash Memory Interrupt (Interrupts with Multiple

Interrupt Request Sources) for the IR bit operations of the timer RC Interrupt, timer RD Interrupt,

Synchronous Serial Comm unication unit Interrupt, and the I 2C bus Interface Interrupt.

1234567891011 12 13 14 15 16 17 18 19 20

CPU Clock

Address Bus

Data B us

Address

0000h Undefined

Undefined

Interrupt

information

SP-2 SP-1 SP-4 SP-3 VEC VEC+1 VEC+2 PC

SP-2

contents SP-1

contents SP-4

contents SP-3

contents VEC

contents VEC+1

contents VEC+2

contents

Note:

The indeterminate state depen ds on the instruction queue buffer.

A read cycle occurs when the instruction queue buffer is ready to acknow ledge instructions.

R8C/34C Group 11. Interrupts

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 159 of 723

11.3.5 Interrupt Response Time

Figure 11.4 shows the Int errupt Response Time. The interrupt response time is the period from when an

interrupt request is generated until the first instruction in the interrupt routine is executed. The interrupt

response time includes the period from when an interrupt request is generated until the currently executing

instruction is completed (refer to (a) in Figure 11.4) and the period required for executing the interrupt sequence

(20 cycles, refer to (b) in Figu re 11.4) .

Figure 11.4 Interrupt Response Time

11.3.6 IPL Change when Interrupt Request is Acknowledged

When a maskable interrupt request is acknowledged, the interrupt priority level of t he acknowle dged interrupt

is set in the IPL.

When a software interrupt or special interrupt request is acknowledged, the level listed in Table 11.5 is set in

the IPL.

Table 11.5 lists the IPL Value When Software or Special Interrup t is Acknowledged.

Table 11.5 IPL Value When Software or Special Interrupt is Acknowledged

Interrupt Source without Interrupt Priority Level Value Set in IPL

Watchdog timer, oscillation stop detection, voltage monitor 1, voltage monitor

2, address break 7

Software, address match, single-step Not changed

Interrupt request ge neration Interrupt request acknowledgement

Instruction Interrupt sequence Instructio n in

interr upt routine

Time

(a) 20 cycles (b)

Interrupt response time

(a) The period from when an interrupt request is generated until the currently executing instruction is completed.

The length of time varies depending on the instruction being executed. The DIVX instruction requires

the longest time, 30 cycles (no wait states if the divisor is a register).

(b) 21 cycles for address match and single-step interrupts.

R8C/34C Group 11. Interrupts

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 160 of 723

11.3.7 Saving Registers

In the interrupt sequence, the FLG register and PC are saved on the stack.

After an extended 16 bits, 4 high-order bits in the PC and 4 high-order (IPL) and 8 low-order bits in the FLG

Figure 11.5 shows the Stack State Before and After Acknowledgement of Interrupt Request.

The other necessary registers should be saved by a program at the beginning of the interrupt routine. The

PUSHM instruction can save several registers in the register bank being currently used (1) with a single

instruction.

Note:

1. Selectable from registers R0, R1, R2, R 3, A0, A1, SB, and FB.

Figure 11.5 Stack State Before and After Acknowledgement of Interrupt Request

Stack

[SP]

SP value before

interrupt request

acknowledgement (1)

Previous stack contents

LSBMSB

Address

Previous stack contents

m−4

m−3

m−2

m−1

m+1

Stack state before interrupt request acknowledgement

[SP]

New SP value (1)

Previous stack contents

LSBMSB

Previous stack contents

m+1

Stack state after interrupt request acknowledgement

PCL

PCM

FLGL

FLGH PCH

m−4

m−3

m−2

m−1

Stack

Address

PCL : 8 low-order bits of PC

PCM : 8 middle-order bits of PC

PCH : 4 high-order bits of PC

FLGL : 8 low-order bits of F LG

FLGH : 4 high-order bits of FLG

Note:

1.When an INT instruction for software numbers 32 to 63 has been executed,

this SP is indicated by the U flag. Otherwise it is ISP.

R8C/34C Group 11. Interrupts

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 161 of 723

The register saving operation, wh ich is performed as part o f the interrupt sequence, saved in 8 bits at a time in

four steps.

Figure 11.6 shows the Register Saving Operation.

Figure 11.6 Register Saving Operation

Stack

Completed saving registers

in four operations

Address

[SP]−5

[SP]

PCL

PCM

FLGL

FLGH PCH

(3)

(4)

(1)

(2)

Saved, 8 bits at a time

Sequence in which registers are saved

Note:

1.[SP] indicates the SP initial value when an interrupt request is acknowledged.

After registers are saved, the SP content is [SP] minus 4.

When an INT instruction for software numbers 32 to 63 has been executed,

this SP is indicated by the U flag. Otherwise it is ISP.

[SP]−4

[SP]−3

[SP]−2

[SP]−1PCL : 8 low-order bits of PC

PCM : 8 middle-order bits of PC

PCH : 4 high-order bits of PC

FLGL : 8 low-order bits of FLG

FLGH : 4 high-order bits of FLG

R8C/34C Group 11. Interrupts

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 162 of 723

11.3.8 Returning from Interrupt Routine

When the REIT instruction is executed at the end of an interrupt routine, the FLG register and PC, which have

been saved on the stack, are automatically restored. The program, that was running before the interrup t request

was acknowledged, starts running again.

Registers saved by a program in an interrupt routine should be saved using the POPM instruction or a similar

instruction before executing the REIT instructi on .

11.3.9 Interrupt Priority

If two or more interrupt requests are generated while a single instruction is being executed, the interrupt with

the higher priority is acknowledged.

Set bits ILVL2 to ILVL0 to select any priori ty level for maskable interrupts (peripheral function). However, if

two or more maskable interrupts have the same priority level, their interrupt priority is resolved by hardware,

with the higher priority interrupts acknowledged.

The priority of watchdog time r and other special interrupts is set by hardware.

Figure 11.7 shows the Hardware Interrupt Priority.

Software interrupts are not affected by the interrupt priority. If an instruction is executed, the MCU executes the

interrupt routine.

Figure 11.7 Hardware Interrupt Priority

Address break

Watchdog timer

Oscillation stop detec tion

Voltage monitor 1

Voltage monitor 2

Peripheral function

Single step

Address match

High

Low

Reset

R8C/34C Group 11. Interrupts

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 163 of 723

11.3.10 Interrupt Priority Level Selection Circuit

The interrupt priority lev e l selection circuit is used to select the highest priority in terrupt .

Figure 11.8 shows the Interrupt Priority Level Selection Circuit.

Figure 11.8 Interrupt Priority Level Selection Circuit

INT1

Timer RC

A/D conversion

UART0 transmit

SSU / I2C bus (1)

Key input

Timer RD1

Lowest

Highest

Peripheral function interrupt priority

(if the priority levels are same)

Interrupt request level

selection output signal

Interrupt request

acknowledgement

I flag

Address match

Watchdog timer

Oscillation stop detection

Voltage monitor 1

Note:

1. Selectable by the IICSEL bit in the SSUIICSR register.

Timer RD0

UART1 transmit

UART2 receive/ACK2

Timer RE

Flash memory ready

Timer RB

INT4

UART1 receive

Voltage monitor 2

INT2

Priority level of interrupts Level 0 (init ial value)

Voltage monitor 2

Voltage monitor 1

UART2 bus collision detection

Timer RA

INT0

UART0 receive

UART2 transmit/NACK2

INT3

IPL

R8C/34C Group 11. Interrupts

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 164 of 723

11.4 INT Interrupt

11.4.1 INTi Interrupt (i = 0 to 4)

The INTi interrupt is generated by an INTi input. To use the INTi interrupt, set the INTiEN bit in the INTEN

bit in the INTiIC register. The input pins used as the INT1 to INT3 input can be selected.

Also, inputs can be passed through a digital filter with three different sampling clocks.

The INT0 pin is shared with t he pulse output forced cutoff i nput of timer RC , and the ext ernal trigger inpu t of

timer RB. The INT2 pin is shared with the event input enabled of timer RA.

Table 11.6 lists the Pin Configurat ion of INT Interrupt.

11.4.2 INT Interrupt Input Pin Select Register (INTSR)

The INTSR register selects which pin is assigned to the INTi (i = 1 or 3) input. To use INTi, set this register.

Set the INTSR register before setting the INTi associated registers. Also, do not change the setting values in this

Table 11.6 Pin Configuration of INT Inte rrupt

Pin Name Assigned Pin I/O Function

INT0 P4_5 Input INT0 interrupt input, timer RB external

trigger input, timer RC pulse output forced

cutoff input

INT1 P1_5, P1_7, or P2_0 Input INT1 interrupt input

INT2 P6_6 Input INT2 interrupt input, timer RA event in put

enabled

INT3 P3_3 or P6_7 Input INT3 interrupt input

INT4 P6_5 Input INT4 interrupt input

Address 018Eh

Bitb7b6b5b4b3b2b1b0

Symbol INT3SEL1 INT3SEL0 — — — INT1SEL1 INT1SEL0 —

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b1 INT1SEL0 INT1 pin select bit b3 b2 b1

0 0: P1_7 assigned

0 1: P1_5 assigned

1 0: P2_0 assigned

1 1: Do not set.

R/W

b2 INT1SEL1 R/W

b3 — Reserved bits Set to 0. R/W

b4 —

b5 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b6 INT3SEL0 INT3 pin select bit b7 b6

0 0: P3_3 assigned

0 1: Do not set.

1 0: P6_7 assigned

1 1: Do not set.

R/W

b7 INT3SEL1 R/W

R8C/34C Group 11. Interrupts

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 165 of 723

11.4.3 External Input Enable Register 0 (INTEN)

Notes:

1. To set the INTiPL bit (i = 0 to 3) to 1 (both edges), set the POL bit in the INTiIC register to 0 (falling edge

selected).

2. The IR bit in the INTiIC register may be set to 1 (interrupt reque sted) if the INTEN register is rewritten. Refer to

11.8.4 Changing Interrupt Sources.

11.4.4 External Input Enable Register 1 (INTEN1)

Notes:

1. To set the INT4PL bit to 1 (both edges), set the POL bit in the INT4IC register to 0 (falling edge selected).

2. The IR bit in the INT4IC register may be set to 1 (interrupt requested) if the INTEN1 register is rewritten. Refer to

11.8.4 Changing Interrupt Sources.

Address 01FAh

Bitb7b6b5b4b3b2b1b0

Symbol INT3PL INT3EN INT2PL INT2EN INT1PL INT1EN INT0PL INT0EN

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 INT0EN INT0 input enable bit 0: Disabled

1: Enabled R/W

b1 INT0PL INT0 input polarity select bit (1, 2) 0: One edge

1: Both edges R/W

b2 INT1EN INT1 input enable bit 0: Disabled

1: Enabled R/W

b3 INT1PL INT1 input polarity select bit (1, 2) 0: One edge

1: Both edges R/W

b4 INT2EN INT2 input enable bit 0: Disabled

1: Enabled R/W

b5 INT2PL INT2 input polarity select bit (1, 2) 0: One edge

1: Both edges R/W

b6 INT3EN INT3 input enable bit 0: Disabled

1: Enabled R/W

b7 INT3PL INT3 input polarity select bit (1, 2) 0: One edge

1: Both edges R/W

Address 01FBh

Bitb7b6b5b4b3b2b1b0

Symbol——————INT4PLINT4EN

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 INT4EN INT4 input enable bit 0: Disabled

1: Enabled R/W

b1 INT4PL INT4 input polarity select bit(1, 2) 0: One edge

1: Both edges R/W

b2 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b3 —

b4 —

b5 —

b6 —

b7 —

R8C/34C Group 11. Interrupts

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 166 of 723

11.4.5 INT Input Filter Select Register 0 (INTF)

11.4.6 INT Input Filter Select Register 1 (INTF1)

Address 01FCh

Bitb7b6b5b4b3b2b1b0

Symbol INT3F1 INT3F0 INT2F1 INT2F0 INT1F1 INT1F0 INT0F1 INT0F0

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 INT0F0 INT0 input filter select bit b1 b0

0 0: No filter

0 1: Filter with f1 sampling

1 0: Filter with f8 sampling

1 1: Filter with f32 sampling

R/W

b1 INT0F1 R/W

b2 INT1F0 INT1 input filter select bit b3 b2

0 0: No filter

0 1: Filter with f1 sampling

1 0: Filter with f8 sampling

1 1: Filter with f32 sampling

R/W

b3 INT1F1 R/W

b4 INT2F0 INT2 input filter select bit b5 b4

0 0: No filter

0 1: Filter with f1 sampling

1 0: Filter with f8 sampling

1 1: Filter with f32 sampling

R/W

b5 INT2F1 R/W

b6 INT3F0 INT3 input filter select bit b7 b6

0 0: No filter

0 1: Filter with f1 sampling

1 0: Filter with f8 sampling

1 1: Filter with f32 sampling

R/W

b7 INT3F1 R/W

Address 01FDh

Bitb7b6b5b4b3b2b1b0

Symbol——————INT4F1INT4F0

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 INT4F0 INT4 input filter select bit b1 b0

0 0: No filter

0 1: Filter with f1 samp l ing

1 0: Filter with f8 samp l ing

1 1: Filter with f3 2 samp li n g

R/W

b1 INT4F1 R/W

b2 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b3 —

b4 —

b5 —

b6 —

b7 —

R8C/34C Group 11. Interrupts

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 167 of 723

11.4.7 INTi Input Filter (i = 0 to 4)

The INTi input contains a digital filter. The sampling clock is selected using bits INTiF1 and INTiF0 in

registers INTF and I NTF1. The INTi level is sampled every sampling clock cycle and if the sampled input level

matches three times, the IR bit in the INTiIC register is set to 1 (interrupt requested).

Figure 11.9 shows the INTi Input Filter Configuration. Figure 11.10 shows an Operating Example of INTi Input

Filter.

Figure 11.9 INTi Input Filter Configuration

Figure 11.10 Operating Example of INTi Input Filter

INTiF0, INTiF1: Bits in registers INTF, INTF1

INTiEN, INTiPL: Bits in registers INTEN, INTEN1

i = 0 to 4

= 01b

INTi

Port direction

Sampling clock

Digital filter

(input level

matches

3 times)

INTi interrupt

= 10b

= 11b

f32

INTiF1 to INTiF0

INTiEN

Other than

INTiF1 to INTiF0

= 00b

= 00b INTiPL = 0

INTiPL = 1

Note:

1. INT0: Port P4_5 direction register

INT1: Port P1_5 direction register when P1_5 pin used

Port P1_7 direction register when P1_7 pin used

Port P2_0 direction register when P2_0 pin used

when P6_6 pin used

INT3: Port P3_3 direction register when P3_3 pin used

Port P6_7 direction register when P6_7 pin used

INT4: Port P6_5 direction register

Both edges

detection

circuit

INTi input

Sampling

timing

IR bit in

INTiIC register

Set to 0 by a program.

Note:

1. This is an operating example when bits INTiF1 to INTiF0 in registers INTF and INTF1 are set to 01b, 10b, or 11b

(digital filter enabled).

i = 0 to 4

R8C/34C Group 11. Interrupts

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 168 of 723

11.5 Key Input In terrupt

A key input interrupt request is generated by one of the input edges of pins K10 to K13. The key input interrupt can

be used as a key-on wake-up function to exit wait or stop mode.

The KIiEN (i = 0 to 3) bit in the KIEN register is be used to select whether or not the pins are used as the KIi input.

The KIiPL bit in the KIEN register is also be used to select the input polarity.

When inputting “L” to the KIi pin, which sets the KIiPL bit to 0 (falling edge), the input to the other pins K10 to

K13 is not detected as interrupts. When inputting “H” to the KIi pin, which sets the KIiPL bit to 1 (rising edge), the

input to the other pins K10 to K1 3 is not also detected as interrupts.

Figure 11.11 shows a Block Diagram of Key Input Interrupt. Table 11.7 lists the Pin Configuration of Key Input

Interrupt.

Figure 11.11 Block Diagram of Key Input Interrupt

Table 11.7 Pin Configuration of Key Input Interru pt

Pin Name I/O Functio n

KI0 Input KI0 interrupt input

KI1 Input KI1 interrupt input

KI2 Input KI2 interrupt input

KI3 Input KI3 interrupt input

KI3

Pull-up

transistor

KI2

Pull-up

transistor

KI3PL = 0

KI3PL = 1

PD1_3 bit

KI3EN bit

PU02 bit in PUR0 regist er

PD1_3 bit in PD1 register KUPIC register

Interrupt control circuit Key input

interrupt reques t

KI2PL = 0

KI2PL = 1

PD1_2 bit

KI2EN bit

KI1

Pull-up

transistor KI1PL = 0

KI1PL = 1

PD1_1 bit

KI1EN bit

KI0

Pull-up

transistor KI0PL = 0

KI0PL = 1

PD1_0 bit

KI0EN bit KI0EN, KI1EN, KI2EN, KI3EN,

KI0PL, KI1PL, KI2PL, KI3PL: Bits in KIEN register

PD1_0, PD1_1, PD1_2, PD1_3: Bits in PD1 registe r

R8C/34C Group 11. Interrupts

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 169 of 723

11.5.1 Key Input Enable Register 0 (KIEN)

The IR bit in the KUPIC register may be set to 1 (interrupt requested) when the KIEN register is rewritten.

Refer to 11.8.4 Changing Interrupt Sources.

Address 01FEh

Bitb7b6b5b4b3b2b1b0

Symbol KI3PL KI3EN KI2PL KI2EN KI1PL KI1EN KI0PL KI0EN

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 KI0EN KI0 input enable bit 0: Disabled

1: Enabled R/W

b1 KI0PL KI0 input polarity select bit 0: Falling edge

1: Rising edge R/W

b2 KI1EN KI1 input enable bit 0: Disabled

1: Enabled R/W

b3 KI1PL KI1 input polarity select bit 0: Falling edge

1: Rising edge R/W

b4 KI2EN KI2 input enable bit 0: Disabled

1: Enabled R/W

b5 KI2PL KI2 input polarity select bit 0: Falling edge

1: Rising edge R/W

b6 KI3EN KI3 input enable bit 0: Disabled

1: Enabled R/W

b7 KI3PL KI3 input polarity select bit 0: Falling edge

1: Rising edge R/W

R8C/34C Group 11. Interrupts

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 170 of 723

11.6 Address Match Interrupt

An address ma tch interrupt reques t is generated imme diately before execution of the instruction at the address

indicated by the RMADi reg ister (i = 0 or 1). This in terrupt is used as a break function by the debugger. When the

on-chip debugger is used, d o not set an address match interru pt (registers AIER0, AIER1, RMAD0, and RMAD1,

and fixed vector tables) in the user system.

Set the starting address of any in stru ction in the RMA Di regi ster (i = 0 or 1 ). The AIERi0 b it in th e AIERi regi ster

can be used to select enable or disable the interrupt. The address match interrupt is not affected by the I flag and

IPL.

The PC value (refer to 11.3.7 Saving Registers) which is saved on the stack when an address match interrupt

request is acknowledged varies d epending on the instru ction at the address indicated by the RMADi regist er. (The

appropriate return address is not saved on the stack.) When returnin g from the address match interrupt , fol low one

of the following means:

•Rewrite the contents of the stack and use the REIT instruction to return.

•Use an instruction such as POP to restore the stack to its previous state before the interrupt request was

acknowledged. Then use a jump instruction to ret urn .

Table 11.8 lists the PC Value Saved on Stack When Address Match In terrupt Request is Acknowledged.

Notes:

1. Refer to 11.3.7 Saving Registers.

2. Operation code: Refer to the R8C/Tiny Series Software Manual (REJ09B0001).

Chapter 4. Instruction Code/Number of Cycles contains diagrams showing

operation code below each syntax. Operation code is shown in the bold frame in

the diagrams.

Table 11.8 PC Value Saved on Stack When Address Match Interrupt Request is Acknowledged

Address Indicated by RMADi Register (i = 0 or 1) PC Value Saved (1)

• Instruction with 2-byte operation code (2)

• Instruction with 1-byte operation code (2)

ADD.B:S #IMM8,dest SUB.B:S #IMM8,dest AND.B:S #IMM8,dest

OR.B:S #IMM8,dest MOV.B:S #IMM8,dest STZ #IMM8,dest

STNZ #IMM8,dest STZX #IMM81,#IMM82,dest

CMP.B:S #IMM8,dest PUSHM src POPM dest

JMPS #IMM8 JSRS #IMM8

MOV.B:S #IMM,dest (however, dest = A0 o r A1)

Address indicated by

RMADi register + 2

Instructions other than above Address indicated by

RMADi register + 1

Table 11.9

Correspondence Between Address Match Interrupt Sources and Associated Registers

Address Match Interrupt Source Address Match Interrupt Enable Bit Address Match Interrupt Register

Address match interrupt 0 AIER00 RMAD0

Address match interrupt 1 AIER10 RMAD1

R8C/34C Group 11. Interrupts

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 171 of 723

11.6.1 Address Match Interrupt Enable Register i (AIERi) (i = 0 or 1)

11.6.2 Address Match Interrupt Register i (RMADi) (i = 0 or 1)

Address 01C3h (AIER0), 01C7h (AIER1)

Bitb7b6b5b4b3b2b1b0

Symbol———————AIER00AIER0 register

After Reset00000000

Symbol———————AIER10AIER1 register

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 AIERi0 Address match interrupt i enable bit 0: Disabled

1: Enabled R/W

b1 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b2 —

b3 —

b4 —

b5 —

b6 —

b7 —

Address 01C2h to 01C0h (RMAD 0), 01C6h to 01C4h (RMAD1)

Bitb7b6b5b4b3b2b1b0

Symbol————————

After ResetXXXXXXXX

Bit b15 b14 b13 b12 b11 b10 b9 b8

Symbol————————

After ResetXXXXXXXX

Bit b23 b22 b21 b20 b19 b18 b17 b16

Symbol————————

After Reset0000XXXX

Bit Symbol Function Setting Range R/W

b19 to b0 — Address setting register for address match interrupt 00000h to FFFFFh R/W

b20 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b21 —

b22 —

b23 —

R8C/34C Group 11. Interrupts

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 172 of 723

11.7 Timer RC Interrupt, Timer RD Interrupt, Synchronous Serial Communication

Unit Interrupt, I2C bus Interface Interrupt, and Flash Memory Interrupt

(Interrupts with Multiple Interrupt Request Sources)

The timer RC interrupt, timer RD (timer RD0) interrupt, timer RD (timer RD1) interrupt, synchronous serial

communication u nit interrupt, I2C bus interface interrupt, and flash memory interrupt each have multiple interrupt

request sources. An interrupt request is generated by the logical OR of several interrupt request s ources and is

reflected in the IR bit in the corresponding interrupt control register. Therefore, each of these peripheral functions

has its own interrupt request source status register (status register) and interrupt request source enable register

(enable register) to control the generation of interrupt requests (change of the IR bit in the interrupt control

Serial Communication Unit Interrupt, I2C bus Interface Interrupt, and Flash Memory Interrupt and Figure 11.12

shows a Block Diagram of Timer RD Interrupt.

Figure 11.12 B lock Diagram of Timer RD Interrupt

Table 11.10 Registers Associated with Timer RC Interrupt , Timer RD Interrupt, Synchronous Serial

Communication Unit In terrupt , I

C bus Interface Interrupt, and Flas h Memo ry Interrup t

Peripheral Function

Name

Status Register of

Interrupt Request Source

Enable Register of

Interrupt Request

Source

Interrupt Control

Timer RC

TRCSR

TRCIER TRCIC

Timer RD Timer RD0 TRDSR0 TRDIER0 TRD0IC

Timer RD1 TRDSR1 TRDIER1 TRD1IC

Synchronous serial

communication unit SSSR SSER SSUIC

I2C bus interface ICSR ICIER IICIC

Flash memory RDYSTI RDYSTIE FMRDYIC

BSYAEI BSYAEIE

CMDERIE

Timer RDi

interrupt request

(IR bit in TRDiIC register)

IMFA bit

IMIEA bit

IMFB bit

IMIEB bit

IMFC bit

IMIEC bit

IMFD bit

IMIED bit

UDF bit

OVF bit

OVIE bit

i = 0 or 1

IMFA, IMFB, IMFC, IMFD, OVF, UDF: Bits in TRDSRi register

IMIEA, IMIEB, IMIEC, IMIED, OVIE: Bits in TRDIERi register

Timer RDi

R8C/34C Group 11. Interrupts

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 173 of 723

As with other m askable interrupts, the timer RC interrupt, timer RD (timer RD 0) interrupt, timer R D (timer RD1)

interrupt, synchronous serial communication un it interrupt, I2C bus interface interrupt, and flash memory interrupt

are controlled by the combination of the I flag, IR bit, bits ILVL0 to ILVL2, and IPL. However, since ea ch

interrupt source is generated by a combination of multiple interrupt request sources, the following differences from

other maskable interrupts apply:

•When bits in the enable register are set to 1 and the corresponding bi ts in the stat us register are set to 1 (interru pt

enabled), the IR bit in the interrupt contro l register is set to 1 (interrupt requested).

•When either bits in the status register or the corresponding bits in the enable register, or both are set to 0, th e IR

bit is set to 0 (no interrupt requested).

That is, even if the interrupt is not acknowledged after the IR bit is set to 1, the interrupt request will not be

retained.

Also, the IR bit is not set to 0 even if 0 is written to this bit.

•Individual bits in the status register are not automatically set to 0 even if the interrupt is acknowledged.

The IR bit is also not automatically set to 0 when the interrupt is acknowledged.

Set individual bits in t he status register to 0 in the interrup t routine. Refer to the status regist er figure for how to

set individual bits in the status register to 0.

•When multiple bits in the enable register are set to 1 and other request sources are generated after the IR bit is set

to 1, the IR bit remains 1.

•When multiple bits in the enable register are set to 1, use the status register to determine which request source

causes an interrupt.

Refer to chapters of the individual peripheral functions (19. Timer RC, 20. Timer RD, 25. Synchronous Serial

Communication Unit (SSU), 26. I2C bus Interface, and 31. Flas h Memory) for the status register and enable

For the interrupt control register, refer to 11.3 Interrupt Control.

R8C/34C Group 11. Interrupts

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 174 of 723

11.8 Notes on Interrupts

11.8.1 Reading Address 00000h

Do not read address 0000 0h by a program. When a maskable interrupt requ est is acknowledged, the CPU reads

interrupt information (interrupt number and interrupt request level) from 00000h in the interrupt sequence. At

this time, the IR bit for the acknowledged interrupt is set to 0.

If address 00000h is read by a program, the IR bit for the interrupt which has the highest priority among the

enabled interrupts is set to 0. This may cause the interrupt to be canceled, or an unexpected interrupt to be

generated.

11.8.2 SP Setting

Set a value in the SP before an interrupt is acknowledged. The SP is set to 0000h after a reset. If an interrupt is

acknowledged before setting a value in the SP, the pro gram may run out of control.

11.8.3 External Interrupt and Key Input Interrupt

Either the “L” level width or “H” level width shown in the Electrical Characteristics is required for the signal

input to pins INT0 to INT4 and pins KI0 to KI3, regardless of the CPU clock.

For details, refer t o Table 33.22 (VCC = 5V), Table 33.28 (VCC = 3V), Table 33 .34 (V CC = 2.2V) External

Interrupt INTi (i = 0 to 4) Input, Key Input Interrupt KIi (i = 0 to 3).

R8C/34C Group 11. Interrupts

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 175 of 723

11.8.4 Changing Interrupt Sources

The IR bit in the interrupt control register may be set to 1 (interrupt requested) when the interrupt source

changes. To use an interrupt, set the IR bit to 0 (no interrupt requested) after changing interrupt sources.

Changing interrupt sources as referred to here includes all factors that change the source, polarity, or timing of

the interrupt assigned to a software interrupt number. Therefore, if a mode change of a peripheral function

involves the source, polarity , or timing of an interrupt, set the IR bit t o 0 (no interrupt requ ested) after makin g

these changes. Refer to the descriptions of the individual peripheral functi ons for related interrupts.

Figure 11.13 shows a Procedure Example for Changing Inte rrupt Sources.

Figure 11.13 Procedure Example for Changing Interrupt Sources

Notes:

1. The above settings m ust be executed individually. Do not execute two or more settings

simultaneously (using one instruction).

2. To prevent interrupt requests from being generated, disable the peripheral function

before changing the interrupt source. In this case, use the I flag if all m ask able

interrupts can be disabled.

If all maskable interrupts cannot be disabled, use bits ILVL0 to ILVL2 for the interrupt

whose so urce is to be changed.

3. To change the interrupt source to the input with the digital filter used, wait for three or

more cycles of the sampling clock of the digital filter before setting the IR bit to 0 (no

interrupt request). Refer to 1 1 .8 .5 Re writ in g In te r rupt Co n t ro l Regist e r for th e

instructions to use and related notes.

Interrupt source change

Disable interrupts (2, 3)

Set the IR bit to 0 (no interrupt request)

using the MOV instruction (3)

Change interrupt sources

(including mode of peripheral function)

Enable interrupts (2, 3 )

Change completed

IR bit: The interrupt control register bit for the interrupt w hose source is to be changed

R8C/34C Group 11. Interrupts

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 176 of 723

11.8.5 Rewriting Interrupt Control Register

(a) The contents of the interrupt control register can be rewritten only while no interrupt requests

corresponding to th at register are generated. If an interrupt request may be generated, disable the interrupt

before rewriting the contents of the interrupt control register.

(b) When rewriting the contents of the interrupt control register after disabling the interrupt, be careful to

choose appropriate instructions.

Changing any bit other than the IR bit

If an interrupt requ est corresponding to the register is generated while execut ing the instruction, the IR bit

may not be set to 1 (interrupt requested), and the interrupt may be ignored. If this causes a problem, use one

of the following instructio ns to rewrite th e contents of the register: AND, OR, BCLR, and BSET.

Changing the IR bit

Depending on the instruction used, th e IR bit may not be set to 0 (no interrupt requested).

Use the MOV instruction to set the IR bit to 0.

(b) regarding rew rit ing the contents of interrupt con trol registers using the sample programs.

Examples 1 to 3 sho ws how to prevent the I flag from b eing set to 1 (interrupts en abled) before the cont ents of

the interrupt control register are rewritten for the effects of the internal bus and the instruction queue buffer.

Example 1: Use the NOP instructions to pause program until the interrupt control register is rewritten

INT_SWITCH1:

FCLR I ; Disable interrupts

AND.B #00H,0056H ; Set the TRAIC register to 00h

NOP ;

NOP

FSET I ; Enable interrupts

Example 2: Use a dummy read to delay the FSET instruction

INT_SWITCH2:

FCLR I ; Disable interrupts

AND.B #00H,0056H ; Set the TRAIC register to 00h

MOV.W MEM,R0 ; Dummy read

FSET I ; Enable interrupts

Example 3: Use the POPC instruction to change the I flag

INT_SWITCH3:

PUSHC FLG

FCLR I ; Disable interrupts

AND.B #00H,0056H ; Set the TRAIC register to 00h

POPC FLG ; Enable interrupts

R8C/34C Group 12. ID Code Areas

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 177 of 723

12. ID Code Areas

The ID code areas are used to implement a function that prevents the flash memory from being rewritten in standard

serial I/O mode. This functio n prevents the flash memory from being read, rewritten, or erased.

12.1 Overview

The ID code areas are assigned to 0FFDFh, 0FFE3h, 0FFEBh, 0FFEFh, 0FFF3h, 0FFF7h, and 0FFFBh of the

respective vector highest-order addresses of the fixed vector table. Fi gure 12.1 sh ows the ID Code Areas.

Figure 12.1 ID Code Areas

4 bytes

Address

Watchdog timer, oscillation stop detection,

voltage monitor 1, voltage monitor 2

(Reserved)

Undefined instruction vector

Overflow vector

BRK instruction vector

Address match vector

Single step vector

Address break vector

Reset vector

ID code areas

ID1

ID2

ID3

ID4

ID5

ID6

ID7

OFS

0FFDFh to 0FFDCh

0FFE3h to 0FFE0h

0FFE7h to 0FFE4h

0FFEBh to 0FFE8h

0FFEFh to 0FFECh

0FFF3h to 0FFF0h

0FFF7h to 0FFF4h

0FFFBh to 0FFF8h

0FFFFh to 0FFFCh

R8C/34C Group 12. ID Code Areas

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 178 of 723

12.2 Functions

The ID code areas are used in standard serial I/O mode. Unless 3 bytes (addresses 0FFFCh to 0FFFEh) of the reset

vector are set to FFFFFFh, the ID codes stored in the ID code areas and the ID codes sent from the serial

programmer or the on-chip debugging emulator are checked to see if they match. If the ID codes match, the

commands sent from the serial programmer or the on-chip debugging emulator are acknowledged. If the ID codes

do not match, the commands are not acknowledged. To use the serial programmer or th e on-chip debugging

emulator, first write predetermined ID codes to the ID code areas.

If 3 bytes (addresses 0FFFCh to 0FFFEh) of the reset vector are set to FFFFFFh, the ID codes are not checked and

all commands are accepted.

The ID code areas are allocate d in the flash memory, not in the SFRs. Set appropriate values as ROM data by a

program.

The character sequence of the ASCII codes “ALeRASE” is the reserved word used for the forced erase function.

The character sequence of the ASCII codes “Protect” is the reserved word used for the standard serial I/O mode

disabled function. Table 12.1 shows the ID Code Reserved Word. The reserved word is a set of reserved characters

when all the addresses and data in the ID code storage addresses sequentially match Table 12.1. When the forced

erase function or standard serial I/O mode disabled function is not used, us e another character sequence of the

ASCII codes.

Table 12.1 ID Code Reserved Word

Note:

1. Reserve word:A set of characters when all the addresses and data in the ID code storage addresses

sequentially match Table 12.1.

ID Code Storage Ad dr ess lD Code Reserved Word (ASCII) (1)

ALeRASE Protect

0FFDFh ID1 41h (upper-case “A”) 50h (upper-case “P”)

0FFE3h ID2 4Ch (upper-case “L”) 72h (lower-case “r”)

0FFEBh ID3 65h (lower-case “e”) 6Fh (lower-case “o”)

0FFEFh ID4 52h (upper-case “R”) 74h (lower-case “t”)

0FFF3h ID5 41h (upper-case “A”) 65h (lower-case “e”)

0FFF7h ID6 53h (upper-case “S”) 63h (lower-case “c”)

0FFFBh ID7 45h (upper-case “E”) 74h (lower-case “t”)

R8C/34C Group 12. ID Code Areas

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 179 of 723

12.3 Forced Erase Function

This function is used in standard serial I/O mode. When the ID codes sent from the serial programmer or the on-

chip debugging emulator are “ALeRASE” in ASCII code, the content of the user ROM area will be erased at once.

However, if the contents of the ID code addresses are set to other than “ALeRASE” (other than Table 12.1 ID

Code Reserved Word) when the ROMCR bit in the OFS register is set to 1 and the ROMCP1 bit is set to 0 (ROM

code protect enabled), forced erasure is not executed and the ID codes are checked with the ID code check function.

Table 12.2 lists the Conditions and Operations of Forced Erase Function.

Also, when the contents of the ID code addresses are set to “ALeRASE” in ASCII code, if the ID codes sent from

the serial programmer or the on-chip debugging emu lator are “ALeRASE”, the content of the user ROM area will

be erased. If the ID codes sent from the serial programmer are other than “ALeRASE”, the ID codes do not match

and no command is acknowledged, thus the user ROM area remains protected.

Note:

1. For “Protect”, refer to 12.4 Standard Serial I/O Mode Disabled Fu nction.

12.4 Standard Serial I/O Mode Disabled Function

This function is used in standard serial I/O mode. When the I/D codes in the ID code storage addresses are set to the

reserved character sequence of the ASCII codes “Protect” (refer to Table 12.1 ID Code Reserved Word),

communication with the serial programmer or the on-chip debugging emulator is not performed. This does not

allow the flash memory to be read, rewritten, or erased using the serial programmer or the on-chip debugging

emulator.

Also, if the ID codes are also set to the reserved character sequence of the ASCII codes “Protect” when the

ROMCR bit in the OFS register is set to 1 and the ROMCP1 bit is set to 0 (ROM code protect enabled), ROM code

protection ca nnot be disabled usin g the serial programmer or the o n-chip debugging emulator. Thi s prevents the

flash memory from being read, rewritten, or erased using the serial programmer, the on-chip debugging emulator,

or parallel programmer.

Table 12.2 Conditions and Operations of Forced Erase Function

Condition

Operation

ID code from serial

programmer or the

on-chip debugging

emulator

ID code in

ID code storage

address

Bits ROMCP1 and

ROMCR

in OFS register

ALeRASE ALeRASE –

All erasure of user ROM

area (forced erase function)

Other than ALeRASE

(1) Other than 01b

(ROM code protect disabled)

01b

(ROM code protect enabled)

ID code check

(ID code check function)

Other than ALeRASE ALeRASE – ID code check

(ID code check function.

No ID code match.)

Other than ALeRASE

(1) – ID code check

(ID code check function)

R8C/34C Group 12. ID Code Areas

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 180 of 723

12.5 Notes on ID Code Areas

12.5.1 Setting Example of ID Code Areas

The ID code areas are allocated in the flash memory, not in the SFRs. Set appropriate values as ROM data by a

program. The following shows a setting example.

•To set 55h in all of the ID code areas

.org 00FFDCH

.lword dummy | (55000000h) ; UND

.lword dummy | (55000000h) ; INTO

.lword dummy ; BREAK

.lword dummy | (55000000h) ; ADDRESS MATCH

.lword dummy | (55000000h) ; SET SINGLE STEP

.lword dummy | (55000000h) ; WDT

.lword dummy | (55000000h) ; ADDRESS BREAK

.lword dummy | (55000000h) ; RESERVE

(Programming form ats vary depending on the compiler. Check the compiler manual.)

R8C/34C Group 13. Option Function Select Area

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 181 of 723

13. Option Function Select Area

13.1 Overview

The option function select area is used to selec t the MCU st ate after a reset, the f unction to p revent re writing in

parallel I/O mode, or the w atchdog timer operation. Th e reset vector highest-order-address, 0FFFFh and 0FFDBh,

are assigned as the option function sel ect area. Figure 13.1 shows the Option Function Select Area.

Figure 13.1 Option Function Select Area

Address

0FFDBh to 0FFD8h OFS2

Option function select area

4 bytes

0FFFFh t o 0FFFCh OFS Reset vector

Reserved area

R8C/34C Group 13. Option Function Select Area

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 182 of 723

13.2 Registers

Registers OFS and OFS2 are used to select the MCU state after a reset, the function to prevent rewriting in parallel

I/O mode, or the watchdog tim er operation.

13.2.1 Option Function Select Register (OFS)

Notes:

1. The OFS register is allocated in the flash memory, not in the SFRs. Set appropriate values as ROM data by a

program.

Do not write addi tions to the OFS regi ster. If the block includi ng the OFS register is er ased, the OFS register is

set to FFh.

When blank products are shipped, the OFS reg ister is set to FFh. It is set to the written value after written by the

user.

When factory-programming products are shi pped, th e valu e o f the OF S regi ster is th e val ue pr ogrammed by the

user.

2. The same level of the vo ltage detection 0 leve l selected by bi ts VDSEL0 and VDESL1 is se t in both functi ons of

voltage monitor 0 reset and power-on reset.

3. To use power-on reset and voltage monitor 0 reset, set the LVDAS bit to 0 (voltage monitor 0 reset enabled after

reset).

For a setting example of the OFS register, ref e r to 13.3.1 Setting Example of Option Function Select Area.

LVDAS Bit (Voltage Detection 0 Circuit Start Bit)

The Vdet0 voltage to be monitored by the voltage detection 0 circuit is selected by bits VDSEL0 and VDSEL1.

Address 0FFFFh

Bitb7 b6b5b4b3b2b1b0

Symbol CSPROINI LVDAS VDSEL1 VDSEL0 ROMCP1 ROMCR — WDTON

After Reset User Setting Value (1)

Bit Symbol Bit Name Function R/W

b0 WDTON Watchdog timer start select bit 0: Watchdog timer automatically starts after reset

1: Watchdog timer is stopped after reset R/W

b1 — Reserved bit Set to 1. R/W

b2 ROMCR ROM code protect disable bit 0: ROM code protect disabled

1: ROMCP1 bit enabled R/W

b3 ROMCP1 ROM code protect bi t 0: ROM code protect enabled

1: ROM code protect disabled R/W

b4 VDSEL0 Voltage detection 0 level select bit (2) b5 b4

0 0: 3.80 V selected (Vdet0_3)

0 1: 2.85 V selected (Vdet0_2)

1 0: 2.35 V selected (Vdet0_1)

1 1: 1.90 V selected (Vdet0_0)

R/W

b5 VDSEL1 R/W

b6 LVDAS Voltage detection 0 circuit start bit (3) 0: Voltage monitor 0 reset enabled after reset

1: Voltage monitor 0 reset disabled after reset R/W

b7 CSPROINI Count source protection mode

after reset select bit 0: Count source protect mode enabled after reset

1: Count source protect mode disabled after reset R/W

R8C/34C Group 13. Option Function Select Area

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 183 of 723

13.2.2 Option Function Select Register 2 (OFS2)

Note:

1. The OFS2 register is allocated in the flash memory, not in the SFRs. Set appropriate values as ROM data by a

program.

Do not write additions to the OF S2 register. If the block including the OFS2 register is erased, the OFS2 register

is set to FFh.

When blank products are shipped, the OFS2 register is set to FFh. It is set to the written value after written by the

user.

When factory-programming products are shipped, the value of the OFS2 register is the value programmed by the

user.

For a setting example of the OFS2 register, refer to 13.3.1 Setting Example of Option Function Select Area.

Bits WDTRCS0 and WDTRCS1

(Watchdog Timer Refresh Acknowledgement Period Set Bit)

Assuming that the period from when the watchdog timer starts counting until it underflows is 100%, the refresh

acknowledgement period for the watchdog ti mer can be selected.

For details, refer to 14.3.1.1 Refresh Acknowledgement Period.

Address 0FFDBh

Bitb7b6b5b4b3b2b1b0

Symbol — — — — WDTRCS1 WDTRCS0 WDTUFS1 WDTUFS0

After Reset User Setting Value (1)

Bit Symbol Bit Name Function R/W

b0 WDTUFS0 Watchdog timer un derflow period set bit b1 b0

0 0: 03FFh

0 1: 0FFFh

1 0: 1FFFh

1 1: 3FFFh

R/W

b1 WDTUFS1 R/W

b2 WDTRCS0 Watchdog timer refresh acknowledgement peri od

set bit b3 b2

0 0: 25%

0 1: 50%

1 0: 75%

1 1: 100%

R/W

b3 WDTRCS1 R/W

b4 — Reserved bits Set to 1. R/W

b5 —

b6 —

b7 —

R8C/34C Group 13. Option Function Select Area

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 184 of 723

13.3 Notes on Option Function Select Area

13.3.1 Setting Example of Option Function Select Area

The option function select area is allocated in the flash memory, not in the SFRs. Set appropriate values as

ROM data by a program. The following shows a setting example.

•To set FFh in the OFS register

.org 00FFFCH

.lword reset | (0FF000000h) ; RESET

(Programming form ats vary depending on the compiler. Check the compiler manual.)

•To set FFh in the OFS2 register

.org 00FFDBH

.byte 0FFh

(Programming form ats vary depending on the compiler. Check the compiler manual.)

R8C/34C Group 14. Watchdog Timer

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 185 of 723

14. Watchdog Timer

The watchdog timer is a function that detects when a program is out of control. Use of the watchdog timer is

recommended to improve the reliability of the system.

14.1 Overview

The watchdog timer contains a 14-bit counter and allows selection of count source protection mode enable or

disable.

Table 14.1 lists the Watchdog Timer Specifications.

Refer to 5.5 Watchdog Timer Reset for details of the watchdog timer reset.

Figure 14.1 shows a Watchdog Timer Block Diagram.

Note:

1. Write the WDTR register during the count opera tion of the watchdog timer.

Table 14.1 Watchdog Timer Specifications

Item Count Source Protection Mode

Disabled Count Source Protection Mode

Enabled

Count source CPU clock Low-speed on-chip oscillator clock

for the watchdog timer

Count operation Decrement

Count start condition Either of the following can be selected:

• After a reset, count starts automatically

• Count starts by writing to the WDTS register

Count stop condition Stop mode, wait mode None

Watchdog timer

initialization conditions • Reset

• Write 00h and then FFh to the WDTR register (with acknowledgement period

setting) (1)

• Underflow

Operations at und erf lo w Watchdo g tim er inte rr up t

or watchdog timer reset Watchdog timer reset

Selectable func tion s • Division ratio of the pr es ca ler

Selected by the WDTC7 bit in the WDTC register or the CM07 bit in

the CM0 register.

• Count source protection mode

Whether count source protection mode is enabled or disabled after a reset

can be selected by the CSPROINI bit in the OFS register (flash memory).

If count source protection mode is d isabled after a reset, it can be enabled o r

disabled by the CSPRO bit in the CSPR register (program).

• Start or stop of the watchdog timer after a reset

Selected by the WDTON bit in the OFS register (flash memory).

• Initial value of the watchdog timer

Selectable by bits WDTUFS0 and WDTUFS1 in the OFS2 register.

• Refresh acknowledgement period for the watchdog timer

Selectable by bits WDTRCS0 and WDTRCS1 in the OFS2 register.

R8C/34C Group 14. Watchdog Timer

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 186 of 723

Figure 14.1 Watchdog Timer Block Diagram

1/128

1/2 Watchdog timer

CPU clock

Bits WDTRCS0 and WDTRCS1

CM07 = 1 (Note 1) PM12 = 1

Watchdog

timer reset

PM12 = 0

Watchdog timer

interrupt request

Prescaler

CSPRO = 0

CSPRO = 1

CSPRO: Bit in CSPR register

WDTC7: Bit in WDTC register

PM12: Bit in PM1 register

CM07: Bit in CM0 register

WDTUFS0, WDTUFS1, WDTRCS0, WDTRC S1: Bits in OFS2 register

Note:

1. A value set by bits WDTUFS0 and WDTUFS1 is set in the watchdog timer (value when shipping: 3FFFh).

Internal reset signal

(“L” active)

1/16

CM07 = 0,

WDTC7 = 0

CM07 = 0,

WDTC7 = 1

Low-speed on-chip oscillator

for watchdog timer

Oscillation starts

when CSPRO = 1

Refresh period

control circuit

Write to WDTR register

R8C/34C Group 14. Watchdog Timer

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 187 of 723

14.2 Registers

14.2.1 Processor Mode Register 1 (PM1)

Note:

1. The PM12 bit is set to 1 when 1 is written by a program (and remains unchanged even if 0 is written to it).

This bit is automatically set to 1 when the CSPRO bit in the CSPR register is set to 1 (count source protection

mode enabled).

Set the PRC1 bit in the PRCR register to 1 (write enabled) before rewriting the PM1 register.

14.2.2 Watchdog Timer Reset Register (WDTR)

Note:

1. Write the WDTR register during the count operation of the watchd og timer.

14.2.3 Watchdog Timer Start Register (WDTS)

Address 0005h

Bitb7b6b5b4b3b2b1b0

Symbol—————PM12——

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 — Reserved bits Set to 0. R/W

b1 —

b2 PM12 WDT interrupt/reset switch bit 0: Watchdog timer interrupt

1: Watchdog timer reset (1) R/W

b3 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b4 —

b5 —

b6 —

b7 — Reserved bit Set to 0. R/W

Address 000Dh

Bitb7b6b5b4b3b2b1b0

Symbol————————

After ResetXXXXXXXX

Bit Function R/W

b7 to b0 Writing 00h and then FFh to this register initializes the watchdog timer.

The initial value of the watchdog timer is specified by bits WDTUFS0 and WDTUF1 in the OFS2

Address 000Eh

Bitb7b6b5b4b3b2b1b0

Symbol————————

After ResetXXXXXXXX

Bit Function R/W

b7 to b0 A write instruction to this register starts the watchdog timer. W

R8C/34C Group 14. Watchdog Timer

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 188 of 723

14.2.4 Watchdog Timer Control Register (WDTC)

14.2.5 Count Source Protection Mode Register (CSPR)

Note:

1. To set the CSPRO bit to 1, write 0 and then 1 to it. Th is bit cannot be set to 0 by a program. Disable interrupts

and DTC activation between writing 0 and writing 1.

Address 000Fh

Bitb7b6b5b4b3b2b1b0

SymbolWDTC7———————

After Reset00111111

Bit Symbol Bit Name Function R/W

b0 — The following bits of the watchdog timer can be read.

When bits WDTUFS1 to WDTUFS0 in the OFS2 register are

00b (03FFh): b5 to b0

01b (0FFFh): b7 to b2

10b (1FFFh): b8 to b3

11b (3FFFh): b9 to b4

b1 — R

b2 — R

b3 — R

b4 — R

b5 — R

b6 — Reserved bit When read, the content is 0. R

b7 WDTC7 Prescaler sele ct bit 0: Divided-by-16

1: Divided-by-128 R/W

Address 001Ch

Bitb7b6b5b4b3b2b1b0

SymbolCSPRO———————

After Reset00000000

The above applies when the CSPR OINI bit in the OFS register is set to 1.

After Reset10000000

The above applies when the CSPR OINI bit in the OFS register is set to 0.

Bit Symbol Bit Name Function R/W

b0 — Reserved bits Set to 0. R/W

b1 —

b2 —

b3 —

b4 —

b5 —

b6 —

b7 CSPRO Count source protection mode select bit (1) 0: Count source protection mode disabled

1: Count source protection mode enabled R/W

R8C/34C Group 14. Watchdog Timer

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 189 of 723

14.2.6 Option Function Select Register (OFS)

Notes:

1. The OFS register is allocated in the flash memory, not in the SFRs. Set appropriate values as ROM data by a

program.

Do not write addi tions to the OFS regi ster. If the block includi ng the OFS register is er ased, the OFS register is

set to FFh.

When blank products are shipped, the OFS reg ister is set to FFh. It is set to the written value after written by the

user.

When factory-programming products are shi pped, th e valu e o f the OF S regi ster is th e val ue pr ogrammed by the

user.

2. The same level of the vo ltage detection 0 leve l selected by bi ts VDSEL0 and VDESL1 is se t in both functi ons of

voltage monitor 0 reset and power-on reset.

3. To use power-on reset and voltage monitor 0 reset, set the LVDAS bit to 0 (voltage monitor 0 reset enabled after

reset).

For a setting example of the OFS register, ref e r to 13.3.1 Setting Example of Option Function Select Area.

LVDAS Bit (Voltage Detection 0 Circuit Start Bit)

The Vdet0 voltage to be monitored by the voltage detection 0 circuit is selected by bits VDSEL0 and VDSEL1.

Address 0FFFFh

Bitb7 b6b5b4b3b2b1b0

Symbol CSPROINI LVDAS VDSEL1 VDSEL0 ROMCP1 ROMCR — WDTON

After Reset User Setting Value (1)

Bit Symbol Bit Name Function R/W

b0 WDTON Watchdog timer start select bit 0: Watchdog timer automatically starts after reset

1: Watchdog timer is stopped after reset R/W

b1 — Reserved bit Set to 1. R/W

b2 ROMCR ROM code protect disable bit 0: ROM code protect disabled

1: ROMCP1 bit enabled R/W

b3 ROMCP1 ROM code protect bi t 0: ROM code protect enabled

1: ROM code protect disabled R/W

b4 VDSEL0 Voltage detection 0 level select bit (2) b5 b4

0 0: 3.80 V selected (Vdet0_3)

0 1: 2.85 V selected (Vdet0_2)

1 0: 2.35 V selected (Vdet0_1)

1 1: 1.90 V selected (Vdet0_0)

R/W

b5 VDSEL1 R/W

b6 LVDAS Voltage detection 0 circuit start bit (3) 0: Voltage monitor 0 reset enabled after reset

1: Voltage monitor 0 reset disabled after reset R/W

b7 CSPROINI Count source protection mode

after reset select bit 0: Count source protect mode enabled after reset

1: Count source protect mode disabled after reset R/W

R8C/34C Group 14. Watchdog Timer

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 190 of 723

14.2.7 Option Function Select Register 2 (OFS2)

Note:

1. The OFS2 register is allocated in the flash memory, not in the SFRs. Set appropriate values as ROM data by a

program.

Do not write additions to the OF S2 register. If the block including the OFS2 register is erased, the OFS2 register

is set to FFh.

When blank products are shipped, the OFS2 register is set to FFh. It is set to the written value after written by the

user.

When factory-programming products are shipped, the value of the OFS2 register is the value programmed by the

user.

For a setting example of the OFS2 register, refer to 13.3.1 Setting Example of Option Function Select Area.

Bits WDTRCS0 and WDTRCS1

(Watchdog Timer Refresh Acknowledgement Period Set Bit)

Assuming that the period from when the watchdog timer starts counting until it underflows is 100%, the refresh

acknowledgement period for the watchdog ti mer can be selected.

For details, refer to 14.3.1.1 Refresh Acknowledgement Period.

Address 0FFDBh

Bitb7b6b5b4b3b2b1b0

Symbol — — — — WDTRCS1 WDTRCS0 WDTUFS1 WDTUFS0

After Reset User Setting Value (1)

Bit Symbol Bit Name Function R/W

b0 WDTUFS0 Watchdog timer un derflow period set bit b1 b0

0 0: 03FFh

0 1: 0FFFh

1 0: 1FFFh

1 1: 3FFFh

R/W

b1 WDTUFS1 R/W

b2 WDTRCS0 Watchdog timer refresh acknowledgement peri od

set bit b3 b2

0 0: 25%

0 1: 50%

1 0: 75%

1 1: 100%

R/W

b3 WDTRCS1 R/W

b4 — Reserved bits Set to 1. R/W

b5 —

b6 —

b7 —

R8C/34C Group 14. Watchdog Timer

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 191 of 723

14.3 Functional Description

14.3.1 Common Items for Multiple Modes

14.3.1.1 Refresh Acknowledgement Period

The period for acknowledging refreshment operation to the watchdog timer (write to the WDTR register) can

be selected by bits WDTRCS0 and WDTRCS1 in the OFS2 register. Figure 14.2 shows the Refresh

Acknowledgement Period for Watchdog Timer.

Assuming that the period from when the watchdog timer starts counting until it underflows is 100%, a refresh

operation executed during the refresh acknowledgement period is acknowledged. Any refresh operation

executed during the period other than the ab ove is processed as an incorrect write, and a watchdog timer

interrupt or watchdog timer reset (selectable by the PM1 2 bit in the PM1 register) is generated.

Do not execute any refresh operation while the count operation of the watchdog timer is stopped.

Figure 14.2 Refresh Acknowledgement Period for Watchdog Timer

Count starts

Note:

1. A watchdog timer interrupt or watchdog timer reset is generated.

Watchdog timer period

Underflow

Refresh can be acknowledged

Processed as incorrect write (1) Refresh can be

acknowledged

Processed as

inc orrec t write (1)

Processed as incorrect write (1)

25% 50% 75% 100%

Refresh acknowledge period

100% (WDTRCS1 to WDTRCS0 = 11b)

75% (WDTRCS1 to WDTRCS0 = 10b)

50% (WDTRCS1 to WDTRCS0 = 01b)

25% (WDTRCS1 to WDTRCS0 = 00b)

WDTRCS0, WDTRCS1: Bits in OFS2 register

R8C/34C Group 14. Watchdog Timer

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 192 of 723

14.3.2 Count Source Protection Mode Disabled

The count source for the watchdog timer is the CPU clock when count source protection m ode is disabled.

Table 14.2 lists the Watchdog Timer Specifications (Count Source Protection Mode Di sabled).

Notes:

1. The watchdog timer is initialized when 00h and then FFh is written to the WDTR register. The

prescaler is initialized after a reset. This may cause some errors due to the prescaler during the

watchdog timer period.

2. The WDTON bit cannot be changed by a program . To set this bit, write 0 to bit 0 o f add ress 0 FFFFh

with a flash programmer.

3. Write the WDTR register during the count opera tion of the watchdog timer.

Table 14.2 Watchdog Timer Specifications (Count Source Protection Mode Disabled)

Item Specification

Count source CPU clock

Count operation Decrement

Period

Division ratio of prescaler (n) × count value of watchdog timer (m)

(1)

CPU clock

n: 16 or 128 (selected by the WDTC7 bit in the WDTC register), or

2 when selecting the low-speed clock (CM07 bit in CM0 register = 1)

m: Value set by bits WDTUFS0 and WDTUFS1 in the OFS2 register

Example:

The period is approximately 13.1 ms when:

- The CPU clock frequency is set to 20 MHz.

- The prescaler is divided by 16.

- Bits WDTUFS1 to WDTUFS0 are set to 11b (3FFFh).

Watchdog timer

initialization conditions • Reset

• Write 00h and then FFh to the WDTR register. (3)

• Underflow

Count start conditions The operation of the watchdog timer after a reset is selected by

the WDTON bit (2) in the OFS register (address 0FFFFh).

• When the WDTON bit is set to 1 (watchdog timer is stopped after reset).

The watchdog timer and prescaler are stopped after a reset and

start counting when the WDTS register is written to.

• When the WDTON bit is set to 0 (watchdog timer starts automatically after

reset).

The watchdog timer and prescaler start counting automatically after a reset.

Count stop condition Stop mode, wait mode (Count resumes from the retained value after exiting.)

Operations at underflow • When the PM12 bit in the PM1 register is set to 0.

Watchdog timer interrupt

• When the PM12 bit in the PM1 register is set to 1.

Watchdog timer reset (refer to 5.5 Watchdog Timer Reset)

R8C/34C Group 14. Watchdog Timer

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 193 of 723

14.3.3 Count Source Protection Mode Enabled

The count source for the watchdog tim er is the low-speed on-chip oscillator clock for the watchdog timer when

count source protection mode is enabled. If the CPU clock stops when a program is out of control, the clock can

still be supplied to the watchdog timer.

Table 14.3 lists the Watchdog Timer Specifications (Count Source Protection Mode Enable d).

Notes:

1. The WDTON bit cannot be changed by a program . To set this bit, write 0 to bit 0 o f add ress 0 FFFFh

with a flash programmer.

2. Even if 0 is written to the CSPROINI bit in the OFS register, the CSPRO bit is set to 1. The

CSPROINI bit cannot be changed by a program. To set this bit, write 0 to bit 7 of address 0FFFFh

with a flash programmer.

3. Write the WDTR register during the count opera tion of the watchdog timer.

Table 14.3 Watchdog Timer Specifications (Count Source Protection Mode Enabled)

Item Specification

Count source Low-speed on-chip oscillator clock

Count operation Decrement

Period Count value of watchdog timer (m)

Low-speed on-chip oscillator clock for the watchdog timer

m: Value set by bits WDTUFS0 and WDTUFS1 in the OFS2 register

Example:

The period is approximately 8.2 ms when:

- The on-chip oscillator clock for the watchdog timer is set to 125 kHz.

- Bits WDTUFS1 to WDTUFS0 are set to 00b (03FFh).

Watchdog timer

initialization conditions •Reset

• Write 00h and then FFh to the WDTR register (3)

• Underflow

Count start conditions The operation of the watchdog timer after a reset is selected by

the WDTON bit (1) in the OFS register (address 0FFFFh).

• When the WDTON bit is set to 1 (watchdog timer is stopped after reset).

The watchdog timer and prescaler are stopped after a reset and

start counting when the WDTS register is written to.

• When the WDTON bit is set to 0 (watchdog timer starts automatically after

reset).

The watchdog timer and prescaler start counting automatically after a reset.

Count stop condition None (Count does not sto p even in wait mode and stop mode once it starts.)

Operation at underflow Watchdog timer reset (Refer to 5.5 Watchdog Timer Reset.)

Registers, bits • When the CSPPRO bit in the CSPR register is set to 1 (count source

protection mode enabled) (2), the following are set automatically:

- The low-speed on-chip oscillator for the watchdog timer is on.

- The PM12 bit in the PM1 register is set to 1 (watchdog timer r eset when the

watchdog timer underflows).

R8C/34C Group 15. DTC

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 194 of 723

15. DTC

The DTC (data transfer controller) is a function that transfers data between the SFR and on-chip memory without using

the CPU. This chip incorporates one DTC channel. The DTC is activated by a peripheral function interrup t to perform

data transfers. The DTC and CPU use the same bus, and the DTC takes pri or ity over the CPU in using the bus.

To control DTC data transfers, cont rol data comprised of a transfer source address, a transfer destination address, and

operating modes are allocated in the DTC con trol data area. Each time the DTC is acti vated, the DTC reads co ntrol

data to perform data transfers.

15.1 Overview

Table 15.1 shows the DTC Specific at ions.

i = 0 to 6, j = 0 to 23

Table 15.1 DTC Specifications

Item Specification

Activation sources 33 sources

Allocatable control data 24 sets

Address space which can be transferred 64 Kbytes (00000h to 0FFFFh)

Maximum number of transfer

times Normal mode 256 times

Repeat mode 255 times

Maximum size of block to be

transferred Normal mode 256 bytes

Repeat mode 255 bytes

Unit of transfers Byte

Transfer mode Normal mode Transfers end on completion of the transfer causing the DTCCTj

Repeat mode On completion of the transfer causing the DTCCTj register value to

change from 1 to 0, the repeat area address is initiali zed and the

DTRLDj register value is reloaded to the DTCCTj register to continue

transfers.

Address control Normal mode Fixed or incremented

Repeat mode Addresses of the area not selected as the repeat area are fixed or

incremented.

Priority of activation sources Refer to Table 15.5 DTC Activa t ion Sourc e s and DTC Vector

Addresses.

Interrupt request Normal mode When the data transfer causing the DTCCTj register value to change

from 1 to 0 is performed, the activation source interrupt request is

generated for the CPU, and interrupt handling is performed on

completion of the data transfer.

Repeat mode When the data transfer causing the DTCCTj register value to change

from 1 to 0 is performed while the RPTINT bit in the DTCCRj register

is 1 (interrupt generation enabled), the activation source interrupt

request is generated for the CPU, and interrupt handling is performed

on completion of the transfer.

Transfer start When bits DTCENi0 to DTCENi7 in the DTCENi registers are 1

(activation enabled), data transfer is started each time the

corresponding DTC activation sources are generated.

Transfer stop Normal mode • When bits DTCENi0 to DTCENi7 are set to 0 (activation disabled).

• When the data transfer causing the DTCCTj register value to

change from 1 to 0 is completed.

Repeat mode • When bits DTCENi0 to DTCENi7 are set to 0 (activation disabled).

• When the data transfer causing the DTCCTj register value to

change from 1 to 0 is completed while the RPTINT bit is 1 (interrupt

generati on enabled).

R8C/34C Group 15. DTC

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 195 of 723

Figure 15.1 DTC Block Diagram

15.2 Registers

When the DTC is activated, control data (DTCCRj, DTBLSj, DTCCTj, DTRLDj, DTSARj, and DTDARj, j = 0 to

23) allocated in the control data area is read, and then transferred to the control registers (DTCCR, DTBLS,

DTCCT, DTRLD, DTSAR, and DTDAR) in the DTC. On completion of the DTC data transfer, the contents of the

DTC control registers are written back to the control data area.

Each DTCCR, DTBLS, DTCCT, DTRLD, DTSAR, and DTDAR register cannot be directly read or written to.

DTCCRj, DTBLSj, DTCCTj, DTRLDj, DTSARj, and DTDARj are allocated as control data at addresses from

2C40h to 2CFFh in the DTC control data area, and can be directly accessed.

Also, registers DTCTL and DTCENi (i = 0 to 6) can be directly accessed.

DTCEN0

DTCEN6

Interrupt controller

Peripheral interrupt request

Control circuit

DTCCR

DTBLS

DTCCT

DTRLD

DTSAR

DTDAR

DTC activation

request

Peripheral interr upt

request

Internal bus

CPU

Bus interface

ROM

RAM

Peripheral

functions

DTCCR: DTC control register

DTBLS: DTC block size register

DTCCT: DTC transfer count register

DTRLD: DTC transfer count reload register

DTSAR: DTC source address register

DTDAR: DTC destination address register

DTCTL: DTC activation control register

DTCEN0 to DTCEN6:

DTC activation enable registers 0 to 6

Peripheral bus

DTCTL

R8C/34C Group 15. DTC

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 196 of 723

15.2.1 DTC Control Register j (DTCCRj) (j = 0 to 23)

Notes:

1. This bit is valid when the MODE bi t is 1 (repeat mode).

2. Settings of bits SAMOD and DAMOD are invalid fo r the repeat area.

3. Set the CHNE bit in the DTCCR23 register to 0 (chain transfers disabled).

15.2.2 DTC Block Size Register j (DTBLSj) (j = 0 to 23)

Note:

1. When the DTBLS register is set to 00h, the block size is 256 bytes.

Address Refer to Table 15.4 Control Data Allocation Addresses.

Bitb7b6b5b4b3b2b1b0

Symbol — — RPTINT CHNE DAMOD SAMOD RPTSEL MODE

After ResetXXXXXXXX

Bit Symbol Bit Name Function R/W

b0 MODE Transfer mode select bit 0: Normal mode

1: Repeat mode R/W

b1 RPTSEL Repeat area select bit (1) 0: Transfer destination is the repeat area.

1: Transfer source is the repeat area. R/W

b2 SAMOD Source address control bit (2) 0: Fixed

1: Incremented R/W

b3 DAMOD Destination address control bit (2) 0: Fixed

1: Incremented R/W

b4 CHNE Chain transfer enable bit (3) 0: Chain transfers disabled

1: Chain transfers enabled R/W

b5 RPTINT Repeat mode interrupt enable bit (1) 0: Interrupt generation disabled

1: Interrupt generation enabled R/W

b6 — Reserved bits Set to 0. R/W

b7 —

Address Refer to Table 15.4 Control Data Allocation Addresses.

Bitb7b6b5b4b3b2b1 b0

Symbol——————— —

After ResetXXXXXXX X

Bit Function Setting Range R/W

b7 to b0 These bits specify the size of the data block to be transferred by one

activation. 00h to FFh (1) R/W

R8C/34C Group 15. DTC

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 197 of 723

15.2.3 DTC Transfer Count Register j (DTCCTj) (j = 0 to 23)

Note:

1. When the DTCCT register is set to 00h, th e number of transfer times is 256. Each time the DTC is activated, the

DTCCT register is decremented by 1.

15.2.4 DTC Transfer Count Reload Register j (DTRLDj) (j = 0 to 23)

Note:

1. Set the initial value for the DTCCT regi ster.

15.2.5 DTC Source Address Register j (DTSARj) (j = 0 to 23)

15.2.6 DTC Destination Address Register j (DTDARj) (j = 0 to 23)

Address Refer to Table 15.4 Control Data Allocation Addresses.

Bitb7b6b5b4b3b2b1b0

Symbol————————

After ResetXXXXXXXX

Bit Function Setting Range R/W

b7 to b0 These bits specify the number of times of DTC data transfe r s. 00h to FFh (1) R/W

Address Refer to Table 15.4 Control Data Allocation Addresses.

Bitb7b6b5b4b3b2b1b0

Symbol————————

After ResetXXXXXXXX

Bit Function Setting Range R/W

b7 to b0 This register value is reloaded to the DTCCT register in repeat mode. 00h to FFh (1) R/W

Address Refer to Table 15.4 Control Data Allocation Addresses.

Bitb7b6b5b4b3b2b1b0

Symbol————————

After ResetXXXXXXXX

Bit b15 b14 b13 b12 b11 b10 b9 b8

Symbol————————

After ResetXXXXXXXX

Bit Function Setting Range R/W

b15 to b0 These bits specify a transfer source address for data transfer. 0000h to FFFFh R/W

Address Refer to Table 15.4 Control Data Allocation Addresses.

Bitb7b6b5b4b3b2b1b0

Symbol————————

After ResetXXXXXXXX

Bit b15 b14 b13 b12 b11 b10 b9 b8

Symbol————————

After ResetXXXXXXXX

Bit Function Setting Range R/W

b15 to b0 These bits specify a transfer destination address for data transfer. 0000h to FFFFh R/W

R8C/34C Group 15. DTC

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 198 of 723

15.2.7 DTC Activation Enable Register i (DTCENi) (i = 0 to 6)

i = 0 to 6

Note:

1. For the operation of this bit, refer to 15.3.7 Interrupt Sources.

The DTCENi registers enable/disable DTC activation by interru pt sources. Tabl e 15.2 show s Correspondences

between Bits DTCENi0 to DTCENi7 (i = 0 to 6) and Interrupt Sources.

Address 0088h (DTCEN0), 0089h (DTCEN1), 008Ah (DTCEN2), 008Bh (DTCEN3), 008Ch (DTCEN4),

008Dh (DTCEN5), 008Eh (DTCEN6)

Bitb7b6b5b4b3b2b1b0

Symbol DTCENi7 DTCENi6 DTCENi5 DTCENi4 DTCENi3 DTCENi2 DTCENi1 DTCENi0

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 DTCENi0 DTC activation enable bit (1) 0: Activation disabled

1: Activation enabled R/W

b1 DTCENi1 R/W

b2 DTCENi2 R/W

b3 DTCENi3 R/W

b4 DTCENi4 R/W

b5 DTCENi5 R/W

b6 DTCENi6 R/W

b7 DTCENi7 R/W

Table 15.2 Correspondences be tween Bits DTCENi0 to DTCENi7 (i = 0 to 6) and Interrupt

Sources

Bit DTCENi6

Bit DTCENi5

Bit DTCENi4

Bit DTCENi3

Bit DTCENi2

Bit DTCENi1

Bit DTCENi0

Bit

DTCEN0 INT0 INT1 INT2 INT3 INT4 ———

DTCEN1 Key input A/D

conversion UART0

reception UART0

transmission UART1

reception UART1

transmission UART2

reception UART2

transmission

DTCEN2 SSU/I2C bus

receive data

full

SSU/I2C bus

transmit

data empty

Voltage

Monitor 2 Voltage

Monitor 1 ——

Timer RC

input-

capture/

compare-

match A

Timer RC

input-

capture/

compare-

match B

DTCEN3

Timer RC

input-

capture/

compare-

match C

Timer RC

input-

capture/

compare-

match D

Timer RD0

input-

capture/

compare-

match A

Timer RD0

input-

capture/

compare-

match B

Timer RD0

input-

capture/

compare-

match C

Timer RD0

input-

capture/

compare-

match D

Timer RD1

input-

capture/

compare-

match A

Timer RD1

input-

capture/

compare-

match B

DTCEN4

Timer RD1

input-

capture/

compare-

match C

Timer RD1

input-

capture/

compare-

match D

——————

DTCEN5 ——

Timer RE —————

DTCEN6 —Timer RA —Timer RB Flash ready

status ———

R8C/34C Group 15. DTC

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 199 of 723

15.2.8 DTC Activation Control Register (DTCTL)

Note:

1. This bit is set to 0 when the read result is 1 and 0 is written to the same bit. This bit remains

unchanged even if the read result is 0 and 0 is written to the same bit. This bit remains unchanged if

1 is written to it.

The DTCTL register controls DTC activation when a non-maskable interrupt (an interrupt by the watchdog

timer, oscillation stop detection, voltage monitor 1, or voltage monitor 2) is generated.

NMIF Bit (Non-Maskable Interrupt Generation Bit)

The NMIF bit is set to 1 when a watchdog timer interrupt, an oscillation stop detection interrupt, a voltage

monitor 1 interrupt, or a voltage monit or 2 interrupt is generated.

When the NMIF bit is 1, the DTC is not activated even if the interrupt which enables DTC activation is

generated. If the NMIF bit is changed to 1 during DTC transfer, the transfer is continued un til it is completed.

When an interrupt source is the watchdog timer, wait for the following cycles before writing 0 to the NMIF bit:

If the WDTC7 bit in the W DTC register is set to 0 (divi de-by-16 using the prescaler), wait for 16 cycles of the

CPU clock after the interrupt source is generated.

If the WDTC7 bit is set to 1 (divide-by-128 using the prescaler), wait for 128 cycles of the CPU clock after the

interrupt source is generated.

When an interrupt source is oscillation stop detecti on, set to the OCD1 bi t in the OCD register to 0 (oscillation

stop detection interrupt disabl ed) before writing 0 to the NMIF bit.

Address 0080h

Bitb7b6b5b4b3b2b1b0

Symbol——————NMIF—

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 — Reserved bit Set to 0. R/W

b1 NMIF Non-maskable interrupt generation

bit (1) 0: Non-maskable interrupts not generated

1: Non-maskable interrupts generated R/W

b2 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b3 —

b4 —

b5 —

b6 —

b7 —

R8C/34C Group 15. DTC

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 200 of 723

15.3 Function Description

15.3.1 Overview

When the DTC is activated, control data is read from the DTC control data area to perform data transfers and

control data after data transfer is written back to the DTC control data area. Twenty-four sets of control data can

be stored in the DTC control data area, which allows 24 types of data transfers to be performed.

There are two transfer modes: normal mode and repeat mode. When the CHNE bit in the DTCCRj (j = 0 to 23)

performed by one activation source (chain transfers).

A transfer source address is specified by t he 16-bit register DTSARj, an d a transfer destination address is

specified by the 16-bit register DTDARj. The values in the registers DTSARj and DTDARj are separately fixed

or incremented according to the control data on completion of the data transfer.

15.3.2 Activation Sources

The DTC is activated by an interrupt source. Figure 15.2 is a Block Diagram Showing Control of DTC

Activation Sources.

The interrupt sources to activate the DTC are selected with the DTCENi (i = 0 to 6) registers.

The DTC sets 0 (activation disabled) to the corresponding bit among bits DTCENi0 to DTCENi7 in the

DTCENi register during operation when the setting of data transfer (the first transfer in chain transfers) is either

of the following:

• Transfer causing the DTCCTj (j = 0 to 23) register value to change to 0 in normal mode

• Transfer causing the DTCCTj register value to change to 0 while the RPTINT bit in the DTCCRj register is 1

(interrupt generation enabled) in repeat mode

If the data transfer setting is not either of the above and the activation source is an interrupt source for timer RC,

timer RD, or the flash memory, the DTC sets 0 to the interrupt source flag corresponding to the activation

source during operation.

Table 15.3 shows the DTC Activation Sources and Interrupt Source Flags for Setting to 0 during DTC

Operation.

If multiple activation sources are simultaneously generated , the DTC activation will be performed according to

the DTC activation source priority.

If multiple activation sources are simultaneously generated on completion of DTC operation, the next transfer

will be performed according to the priority.

DTC activation is not affected by the I flag or interrupt control regist er, unlike with interrupt request o perat ion.

Therefore, even if interrupt requests cannot be acknowledged because interrupts are disabled, DTC activation

requests can be acknowledged. The IR bit in the interrupt control register does not change even when an

interrupt source to enable DTC activation is generated.

Figure 15.2 Block Diagram Showing Control of DTC Activation Sources

Interrupt c ontroller

Select interrupt source or

DTC activation source

DTCENi

Clear control

Peripheral function 1

Peripheral function 2

(timer RC, timer RD,

flash memory)

DTC

Interrupt request

Peripheral interrupt

request

Peripheral interrupt

request

DTC acti v at i o n

request

Select DTC activation or

interrupt generation.

Set the bit among bits DTCENi0 to

DTCENi7 (i = 0 to 6) to 0.

Set the interrupt source flag

in the status register t o 0.

R8C/34C Group 15. DTC

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 201 of 723

Table 15.3 DTC Activation Sources and Interrupt Source Flags for Sett ing to 0 during DTC

Operation

DTC activation source generation Interrupt Source Fla g for Setting to 0

Timer RC input-capture/compare-match A IMFA bit in TRCSR re gister

Timer RC input-capture/compare-match B IMFB bit in TRCSR re gister

Timer RC input-capture/compare-match C IMFC bit in TRCSR register

Timer RC input-capture/compare-match D IMFD bit in TRCSR register

Timer RD0 input-capture/compar e-match A IMFA bit in TRDSR0 register

Timer RD0 input-capture/compar e-match B IMFB bit in TRDSR0 register

Timer RD0 input-capture/compare-match C IMFC bit in TRDSR0 register

Timer RD0 input-capture/compare-match D IMFD bit in TRDSR0 register

Timer RD1 input-capture/compar e-match A IMFA bit in TRDSR1 register

Timer RD1 input-capture/compar e-match B IMFB bit in TRDSR1 register

Timer RD1 input-capture/compare-match C IMFC bit in TRDSR1 register

Timer RD1 input-capture/compare-match D IMFD bit in TRDSR1 register

Flash ready status RDYSTI bit in FST reg ist er

R8C/34C Group 15. DTC

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 202 of 723

15.3.3 Control Data Allocation and DTC Vector Table

Control data is allocated in the order: Registers DTCCRj, DTBLSj, DTCCTj, DTRLDj, DTSARj, and DTDARj

(j = 0 to 23). Table 15.4 shows the Control Data Allocation Addresses.

j = 0 to 23

Table 15.4 Control Data Allocation Addresses

Symbol Control

Data No. Address DTCCRj

DTSARj

(Lower

8 Bits)

DTSARj

(Higher

8 Bits)

DTDARj

(Lower

8 Bits)

DTDARj

(Higher

8 Bits)

DTCD0 Control

Data 0 2C40h to

2C47h 2C40h 2C41h 2C42h 2C43h 2C44h 2C45h 2C46h 2C47h

DTCD1 Control

Data 1 2C48h to

2C4Fh 2C48h 2C49h 2C4Ah 2C4Bh 2C4Ch 2C4Dh 2C4Eh 2C4Fh

DTCD2 Control

Data 2 2C50h to

2C57h 2C50h 2C51h 2C52h 2C53h 2C54h 2C55h 2C56h 2C57h

DTCD3 Control

Data 3 2C58h to

2C5Fh 2C58h 2C59h 2C5Ah 2C5Bh 2C5Ch 2C5Dh 2C5Eh 2C5Fh

DTCD4 Control

Data 4 2C60h to

2C67h 2C60h 2C61h 2C62h 2C63h 2C64h 2C65h 2C66h 2C67h

DTCD5 Control

Data 5 2C68h to

2C6Fh 2C68h 2C69h 2C6Ah 2C6Bh 2C6Ch 2C6Dh 2C6Eh 2C6Fh

DTCD6 Control

Data 6 2C70h to

2C77h 2C70h 2C71h 2C72h 2C73h 2C74h 2C75h 2C76h 2C77h

DTCD7 Control

Data 7 2C78h to

2C7Fh 2C78h 2C79h 2C7Ah 2C7Bh 2C7Ch 2C7Dh 2C7Eh 2C7Fh

DTCD8 Control

Data 8 2C80h to

2C87h 2C80h 2C81h 2C82h 2C83h 2C84h 2C85h 2C86h 2C87h

DTCD9 Control

Data 9 2C88h to

2C8Fh 2C88h 2C89h 2C8Ah 2C8Bh 2C8Ch 2C8Dh 2C8Eh 2C8Fh

DTCD10 Control

Data 10 2C90h to

2C97h 2C90h 2C91h 2C92h 2C93h 2C94h 2C95h 2C96h 2C97h

DTCD11 Control

Data 11 2C98h to

2C9Fh 2C98h 2C99h 2C9Ah 2C9Bh 2C9Ch 2C9Dh 2C9Eh 2C9Fh

DTCD12 Control

Data 12 2CA0h to

2CA7h 2CA0h 2CA1h 2CA2h 2CA3h 2CA4h 2CA5h 2CA6h 2CA7h

DTCD13 Control

Data 13 2CA8h to

2CAFh 2CA8h 2CA9h 2CAAh 2CABh 2CACh 2CADh 2CAEh 2CAFh

DTCD14 Control

Data 14 2CB0h to

2CB7h 2CB0h 2CB1h 2CB2h 2CB3h 2CB4h 2CB5h 2CB6h 2CB7h

DTCD15 Control

Data 15 2CB8h to

2CBFh 2CB8h 2CB9h 2CBAh 2CBBh 2CBCh 2CBDh 2CBEh 2CBFh

DTCD16 Control

Data 16 2CC0h to

2CC7h 2CC0h 2CC1h 2CC2h 2CC3h 2CC4h 2CC5h 2CC6h 2CC7h

DTCD17 Control

Data 17 2CC8h to

2CCFh 2CC8h 2CC9h 2CCAh 2CCBh 2CCCh 2CCDh 2CCEh 2CCFh

DTCD18 Control

Data 18 2CD0h to

2CD7h 2CD0h 2CD1h 2CD2h 2CD3h 2CD4h 2CD5h 2CD6h 2CD7h

DTCD19 Control

Data 19 2CD8h to

2CDFh 2CD8h 2CD9h 2CDAh 2CDBh 2CDCh 2CDDh 2CDEh 2CDFh

DTCD20 Control

Data 20 2CE0h to

2CE7h 2CE0h 2CE1h 2CE2h 2CE3h 2CE4h 2CE5h 2CE6h 2CE7h

DTCD21 Control

Data 21 2CE8h to

2CEFh 2CE8h 2CE9h 2CEAh 2CEBh 2CECh 2CEDh 2CEEh 2CEFh

DTCD22 Control

Data 22 2CF0h to

2CF7h 2CF0h 2CF1h 2CF2h 2CF3h 2CF4h 2CF5h 2CF6h 2CF7h

DTCD23 Control

Data 23 2CF8h to

2CFFh 2CF8h 2CF9h 2CFAh 2CFBh 2CFCh 2CFDh 2CFEh 2CFFh

R8C/34C Group 15. DTC

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 203 of 723

When the DTC is activated, one control data is selected according to the data read from the vector table which

has been assigned to each activation source, and the selected control data is read fr om the DTC control data

area.

Table 15.5 shows the DTC Activation Sources and DTC Vector Addresses. A one-byte vector table area is

assigned to each activation source and one value from 00000000b to 00010111b (control data numbers in Table

15.4) is stored in each area to select one of the 24 control data sets.

Figures 15.3 to 15.7 show the DTC Internal Operation Flowchart.

Table 15.5 DTC Activation Sources and DTC Vector Addresses

Interrupt Request Source Interrupt Name Source No. DTC Vector Address Priority

External input INT0 0 2C00h High

INT1 1 2C01h

INT2 2 2C02h

INT3 3 2C03h

INT4 4 2C04h

Key input Key input 8 2C08h

A/D A/D conversion 9 2C09h

UART0 U ART0 reception 10 2C0Ah

UART0 transmission 11 2C0Bh

UART1 U ART1 reception 12 2C0Ch

UART1 transmission 13 2C0Dh

UART2 U ART2 reception 14 2C0Eh

UART2 transmission 15 2C0Fh

SSU/I2C bus Receive data full 16 2C10h

Transmit data empty 17 2C 11h

Voltage detection circuit Voltage monitor 2 18 2C12h

Voltage monito r 1 19 2C13h

Timer RC Input-capture/compare-match A 22 2C16h

Input-capture/compare-match B 23 2C17h

Input-capture/compare-match C 24 2C18h

Input-capture/compare-match D 25 2C19h

Timer RD0 Inp ut-capture/compare-match A 26 2C1Ah

Input-capture/compare-match B 27 2C1Bh

Input-capture/compare-match C 28 2C1Ch

Input-capture/compare-match D 29 2C1Dh

Timer RD1 Inp ut-capture/compare-match A 30 2C1Eh

Input-capture/compare-match B 31 2C1Fh

Input-capture/compare-match C 32 2C20h

Input-capture/compare-match D 33 2C21h

Timer RE Timer RE 42 2C2Ah

Timer RA Timer RA 49 2C31h

Timer RB Timer RB 51 2C33h

Flash memory Flash ready status 52 2C34h Low

R8C/34C Group 15. DTC

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 204 of 723

Figure 15.3 DTC Internal Operation Flowchart When DTC Activation Source is not SSU/I2C bus,

Timer RC, Timer RD, or Flash Memory Interrupt Source

Figure 15.4 DTC Internal Ope ratio n Flowchar t When DTC Act ivation Sourc e is Timer RC or T imer

RD Interrupt Source

DTC activation source

generation

NMIF = 1?

Read DTC vector

Read control data

Transfer data

Write back control data

CHNE=1?

Branch 1

0 is written to the bit among bi ts DTCENi0 to DTCENi7 and an interrupt request is generated

when transfer is either of the following:

- Transf er c a using the DTCCTj (j = 0 to 23) r eg i s ter value to ch an ge from 1 to 0 in no rmal mode

- Transfer causing the DTCCTj register value to change from 1 to 0 while the RPTINT bit is 1 in

repeat mode

Yes

DTCENi0 to DTCENi7: Bits in DTCENi (i = 0 to 6) registers

RPTINT, CHNE: Bits in DTCCRj registers

NMIF: Bit in DTCTL register

Branch 1

End

Yes

Read control data

Transfer data

Write back control data

CHNE=1?

Write 0 to the bit among

DTCENi0 to DTCE N i7

Generate an interrupt request

for the CPU

Transfer data

Write back control data

CHNE=1? Yes

Interrupt handling

Read control data

Transfer data

Write back control data

CHNE=1? Yes

DTC activation source

generation

NMIF = 1?

Read DTC vector

Read control data

Write 0 to the interrupt source

flag in the status register

Transfer data

Branch 1

0 is written to the bit among bits DTCENi0 to DTCENi7 and an interrupt request is generated

when transfer is either of the following:

- Transfer causing the DTCCTj (j = 0 to 23) register value to change from 1 to 0 in normal mode

- Transfer causing the DTCCTj register value to change from 1 to 0 while the RPTINT bit is 1 in

repeat mode

Yes

DTCENi0 to DTCENi7: Bits in DTCENi (i = 0 to 6) registers

RPTINT, CHNE: Bits in DTCCRj registers

NMIF: Bit in DTCTL register

Branch 1

Yes

Read control dat a

Transfer data

Write back control data

CHNE=1?

Write 0 to the bit among

DTCENi0 to DTCENi7

Generate an interrupt request

for the CPU

Transfer data

Write back control data

CHNE=1? Yes

Interrupt handling

Read control data

Transfer data

Write back control data

CHNE=1? Yes

CHNE=1?

End

Yes

Write back control data

R8C/34C Group 15. DTC

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 205 of 723

Figure 15.5 DTC Internal Operation Flowchart When DTC Activation Source is SSU/I2C bus

Receive Da ta Full

Figure 15.6 DTC Internal Operation Flowchart When DTC Activation Source is SSU/I2C bus

Transmit Data Empty

DTC activation source generation

NMIF = 1?

Read DTC vector

Read control data

Transfer data

(Reading the receive data register

sets the RDRF bit to 0 ) (1)

Write back control data

CHNE=1?

Branch 1

0 is written to the bit among bits DTCENi0 to DTCENi7 and an interrupt request is generated

when transfer is either of the following:

- Transfer causing the DTCCTj (j = 0 to 23) register value to change from 1 to 0 in normal mode

- Transfe r c au s ing the DTCCTj re gi st e r value to change fr om 1 to 0 while the R P T I N T bit is 1 in

repeat mode

Yes

DTCENi0 to DTCENi7: Bits in DTCENi (i = 0 to 6) registers

RPTINT, CHNE: Bits in DTCCRj registers

NMIF: Bit in DTCTL register

RDRF: Bit in SSSR/ICSR register

Branch 1

End

Yes

Read control data

Transfer data

(Reading the receive data register

sets th e RD RF bit to 0) (1)

Write back control data

CHNE=1?

Write 0 to the bit among

DTCENi0 to DTCENi7

Generate an interrupt request

for the CPU

Transfer data

(Reading the receive data register

does not set the RDRF bit to 0)

Write back control data

CHNE=1? Yes

Interrupt handling

Read control data

Transfer data

(Reading the receive data register

does not set the RDRF bit to 0)

Write back control data

CHNE=1? Yes

Note:

1. When the DTC activation source is SSU/I2C bus receive data full, the DTC does not set the RDRF bit in the SSSR register/the ICSR register to 0.

Instead, reading the receive data register during DTC data transfer sets the RDRF bit to 0.

DTC activation source generation

NMIF = 1?

Read DTC vector

Read control data

Transfer data

(writing the transmit data register

sets the TDRE bit to 0) (1)

Write back control data

CHNE=1?

Branch 1

0 is written to the bit among bits DTCENi0 to DTCENi7 when transfer is either of the following:

- Transfer causing the DTCCTj (j = 0 to 23) register value to change from 1 to 0 in normal mode

- Transfer causing the DTCCTj register value to change from 1 to 0 while the RPTINT bit is 1 in

repeat m od e

Yes

DTCENi0 to DTCENi7: Bits in DTCENi (i = 0 to 6) registers

RPTINT, CHNE: Bits in DTCCRj registers

NMIF: Bit in DTCTL register

TDRE: Bit in SSSR/ICSR register

Branch 1

End

Yes

Read control data

Transfer data

(writing the transmit data register

sets the TDRE bit to 0) (1)

Write back control data

CHNE=1?

Write 0 to the bit among

DTCENi0 to DTCENi7

Transfer data

(writing the transmit data register

sets the TDRE bit to 0) (1)

Write back control data

CHNE=1? Yes

Read control data

Transfer data

(writing the transmit data register

sets the TDRE bit to 0) (1)

Write back control data

CHNE=1? Yes

Note:

1. When the DTC activation source is SSU/I2C bus transmit data empty, the DTC does not set the TDRE bit in the SSSR register/the ICSR register to 0.

Instead, writing data to the transmit data register during DTC data transfer sets the TDRE bit to 0.

R8C/34C Group 15. DTC

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 206 of 723

Figure 15.7 DTC Internal Operation Flowchart When DTC Ac tivation Source is Flash ready status

DTC activation source

generation

NMIF = 1?

Read DTC vector

Read control data

Write 0 to the interrupt source

flag in the status register

Transfer data

Branch 1

0 is writ t en to the bit among bits DT CENi0 to DTCENi7 when t r an sfer is eith er of the follow ing:

- Transfer causing the DTCCTj (j = 0 to 23) register value to change from 1 to 0 in normal mode

- Transfer causing the DTCCTj register value to change from 1 to 0 while the RPTINT bit is 1 in

repeat mode

Yes

DTCENi0 to DTCENi7: Bits in DTCENi (i = 0 to 6) registers

RPTINT, CHNE: Bits in DTCCRj registers

NMIF: Bit in DTCTL register

Branch 1

Yes

Read control dat a

Transfer data

Write back control data

CHNE=1?

Write 0 to the bit among

DTCENi0 to DTCENi7

Write 0 to the interrupt source

flag in t h e status reg i s t e r

Transfer data

Write back control data

CHNE=1? Yes

Read control data

Transfer data

Write back control data

CHNE=1? Yes

CHNE=1?

End

Yes

Write back control data

R8C/34C Group 15. DTC

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 207 of 723

15.3.4 Normal Mode

One to 256 bytes of data are transferred by one activation. The number of transfer times can be 1 to 256. When

the data transfer causing the DTCCTj ( j = 0 to 23) register value to change to 0 is performed, an in terrupt

request for the CPU is generated during DTC operation.

Table 15.6 shows Register Functions in Normal Mode.

Figure 15.8 show s Dat a Transfers in Normal Mode.

j =0 to 23

Figure 15.8 Data Tran sf ers in Normal Mo de

Table 15.6 Register Functions in Normal Mode

DTC block size register j DTBLSj Size of the data block to be transferred by one activation

DTC transfer count register j DTCCTj Number of times of data transfers

DTC transfer count reload

DTC source address register j DTSARj Data transfer source address

DTC destination address

SRC Transfer DST

Transfer source Transfer destination

Size of the data block to be transferred

by one activation (N bytes)

DTBLSj = N

DTSARj = SRC

DTDARj = DST

j = 0 to 23

Bits b3 to b0 in

DTCCR register

00X0b

01X0b

10X0b

11X0b

Source address

control

Fixed

Incremented

Fixed

Incremented

Destination address

control

Fixed

Incremented

Source address

after transfer

SRC

SRC+N

SRC

SRC+N

Destination address

after transfer

DST

DST+N

X: 0 or 1

R8C/34C Group 15. DTC

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 208 of 723

15.3.5 Repeat Mode

One to 255 bytes of data are transferred by one activation. Either of the transfer source or destination should be

specified as the repeat area. The number of transfer times can be 1 to 255. On completion of the specified

number of transfer times, the DTCCTj (i =0 to 23) register and the address specified for the repeat area are

initialized to continue transfers. When the data transfer causing the DTCCTj register value to change to 0 is

performed while the RPTINT bit in the DTCCRj register is 1 (interrupt generation enabled), an interrupt request

for the CPU is generated during DTC operation.

The lower 8 bits of the initial value for the repeat area address must be 00h. The size of data to be transferred

must be set to 255 bytes or less before the specified number of transfer times is completed.

Table 15.7 shows Register Functions in Repeat Mode.

Figure 15.9 shows Data Transfers in Repeat Mode.

j =0 to 23

Figure 15.9 Data Transfers in Repeat Mode

Table 15.7 Register Functions in Repeat Mode

DTC block size register j DTBLSj Size of the data block to be transferred by one activation

DTC transfer count register j DTCCTj Number of times of data transfers

DTC transfer count reload register j DTRLDj This register value is reloaded to the DTCCT register. (Data

transfer count is initialize d.)

DTC source address register j DTSARj Data transfer source address

DTC destination address register j DTDARj Data transfer destination address

SRC Transfer DST

Transfer source Transfer destination

Size of the data block to be transferred by

one activation (N bytes)

DTBLSj = N

DTCCTj ≠ 1

DTSARj = SRC

DTDARj = DST

j = 0 to 23

Bits b3 to b0 in

DTCCR register

0X11b

1X11b

X001b

X101b

Source address

control

Repeat area

Fixed

Incremented

Destination address

control

Fixed

Incremented

Repeat area

Source address

after transfer

SRC+N

SRC

SRC+N

Destination address

after transfer

DST

DST+N

DTCCTj register = 1

SRC0/DST0

…

Repeat area

Bits b3 to b0 in

DTCCR register

0X11b

1X11b

X001b

X101b

Source address

control

Repeat area

Fixed

Incremented

Destination address

control

Fixed

Incremented

Repeat area

Source address

after transfer

SRC0

SRC

SRC+N

Destination address

after transfer

DST

DST+N

DST0

SRC/DST

Address of the repeat area is initialized

after a transfer.

DTBLSj = N

DTCCTj = 1

DTSARj = SRC

DTDARj = DST

j = 0 to 23

SRC0: Initial source address value

DST0: Initial destination address value

X: 0 or 1

DTCCTj register ≠ 1

R8C/34C Group 15. DTC

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 209 of 723

15.3.6 Chain Transfers

When the CHNE bit in the DTCCRj (j = 0 to 22) register is 1 (chain transfers enabled), mult iple data transfers

can be continuously performed by one activation source. Figure 15.10 shows a Flow of Chain Transfers.

When the DTC is activated, one control data is selected according to the data read from the DTC vector address

corresponding to the activation source, and the selected control data is read from the DTC control data area.

When the CHNE bit for the control data is 1 (chain transfers enabled), the next control data immediately

following the current control data is read and transferred after the current transfer is com pleted. This op eration

is repeated until the data transfer with the con trol data for w hich t he CHNE bit is 0 (ch ain transfers disabled ) is

completed.

Set the CHNE bit in the DTCCR23 register to 0 (chain transfers disabled).

Figure 15.1 0 Flow of Ch ai n T ran sf ers

15.3.7 Interrupt Sources

When the data transfer causing the DTCCTj (j = 0 to 23) register value to change to 0 is performed in normal

mode, and when the data transfer causing the DTCCTj register value to change to 0 is performed while the

RPTINT bit in the DTCCRj register is 1 (interrupt generation enabled) in repeat mode, the interrupt request

corresponding to the activation source is generated for the CPU during D TC operation. H owever, no i nterrupt

request is generated for t he CPU when the activation source is SSU/I2C bus transmit data empty or flash ready

status.

Interrupt requests for the CPU are affected by the I flag or interrupt control register. In chain transfers, whether

the interrupt request is generated or not is determined either by the number of transfer times specified for the

first type of the transfer or the RPTINT bit. W hen an interrupt requ est is generated fo r the CPU, the bit among

bits DTCENi0 to DTCENi7 in the DTCENi (i = 0 to 6) registers corresponding to the activation source are set

to 0 (activation disabled).

DTC activation source

generation

Read DTC vector

Read control data 1

Transfer data

Write back control data 1

Read control data 2

Data transfer

Write back control data 2

End of DTC transfers

Control data 1

CHNE = 1

Control data 2

CHNE = 0

DTC control data area

CHNE: Bit i n DTC CRj register

R8C/34C Group 15. DTC

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 210 of 723

15.3.8 Operation Timings

The DTC requires five clock cycles to read control data allocated in the DTC cont rol d ata area. The number of

clock cycles required to write back control data differs depending on the control data settings.

Figure 15.11 shows an Example of DTC Operation Timings and Figure 15.12 shows an Example of DTC

Operation Timings in Chain Transfers.

Table 15.8 shows the Specifications of Control Data Write-Back Operation.

Figure 15.11 Example of DTC Operation Timings

Figure 15.12 Example of DTC Operation Timings in Chain Transfers

j = 0 to 23

X: 0 or 1

Table 15.8 Specifications of Control Data Write-Back Operation

Bits b3 to b0

in DTCCR

Operating

Mode

Address Control Control Data to be Written Back Number of

Clock

Cycles

Source Destination DTCCTj

00X0b

Normal

mode

Fixed Fixed Written back Written back Not written

back Not written

back 1

01X0b Incremented Fixed Written back Written back Written back Not written

back 2

10X0b Fixed Incremented Written back Written back Not written

back Written back 2

11X0b Incremented Incremented Written back Written back Written back Written back 3

0X11b

Repeat

mode

Repeat area Fixed Written back Written back Written back Not written

back 2

1X11b Incremented Written back Written back Written back Written back 3

X001b Fixed Repeat area Written back Written back Not written

back Written back 2

X101b Incremented Written back Written back Written back Written back 3

Used by CPU Used by CPU

Read cont rol data Transfer data Write back co ntrol data

CPU cl ock

Address Read Write

Read vector

Used by CPU Read Write Used by CPU

Read control data Transfer data Write back control data Read control data Transfer data Write back control data

CPU clock

Address Read Write

Read vector

R8C/34C Group 15. DTC

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 211 of 723

15.3.9 Number of DTC Execution Cycles

Table 15.9 shows the Operations Following DTC Activation and Required Number of Cycles for each

operation.

Table 15.10 shows the Number of Clock Cycles Required for Data Transfers.

Notes:

1. For the number of clock cycles required for data read/write, refer to Table 15.10 Number of Clock

Cycles Required for Data Transfers.

2. For the number of clock cycles required for control data write-back, refer to Table 15.8

Specifications of Control Data Write-Back Operation.

Data is transferred as described below, when the DTBLSj (j = 0 to 23) register = N,

(1) When N = 2n (even), two-byte transfers are performed n times.

(2) When N = 2n + 1 (odd), two-byte transfers are performed n times followed by one time of one-byte

transfer.

From Tables 15.9 and 15.10, the total number of required execution cycles can be obtained by the following

formula:

Number of required execution cycles = 1 + Σ[formula A] + 2

Σ: Sum of the cycles for the number of transfer times p erformed by one activation source ([the number of

transfer times for which CHNE is set to 1] + 1)

(1) For N = 2n (even)

Formula A = J + n • SK2 + n • SL2

(2) For N = 2n+1 (odd)

Formula A = J + n • SK2 + 1 • SK1 + n • SL2 + 1 • SL1

J: Number of c ycl es re q uire d to rea d c ont rol d ata (5 cycl es ) + nu m ber o f cy c les re qui red to write b a ck c ont rol d a ta

To read data from or write data to the register that to be accessed in 16-bit units, set an even value of 2 or grea ter

to the DTBLSj (j = 0 to 23) register.

The DTC performs accesses in 16-bit units.

Table 15.9 Operations Following DTC Activation and Required Number of Cycles

Vector Read Control Data Data Read Data Write Internal Operation

Read Write-back

1 5 (Note 2) (Note 1) (Note 1) 1

Table 15.10 Number of Clock Cycles Required for Data Trans fers

Operation Unit of

Transfers

Internal

RAM

(During DTC Transfers)

Internal ROM

(Program ROM)

Internal

ROM

(Data flash)

SFR

(Word Access) SFR

(Byte

Access)

SFR

(DTC control data area)

Even

Address Odd

Address Even

Address Odd

Address Even

Address Odd

Address

Data read 1-byte SK1 1 1 2 2 2 1

2-byte SK2 1 2 2 4 2 4 4 1 2

Data write 1-byte SL1 1—— 221

2-byte SL2 12 ——

24412

R8C/34C Group 15. DTC

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 212 of 723

15.3.10 DTC Activation Source Acknowledgement and Interrupt Source Flags

15.3.10.1 Interrupt Sources Except for Flash Memory, Timer RC, Timer RD, and

Synchronous Serial Communication Unit (SSU)/I2C bus

When the DTC activation source is an interrupt source except for the flash memory, timer RC, timer RD, or the

synchronous serial communication unit/I2C bus, the same DTC activation source cannot be acknowledged for 8

to 12 cycles of the CPU clock after the interrupt source is generated. If an interrupt source is generated when a

software command is executed, the same DTC activation source cannot be acknowledged for 9 to 16 cycles of

the CPU clock. If a DTC activation source is generated during DTC operation and acknowledged, the same

DTC activation source cannot be acknowledged for 8 to 12 cycles of the CPU clock on completion of the DTC

transfer immediately before the DTC is activated by the source. When a software command is executed on

completion of the DTC transfer immediately before the DTC is activated, the same DTC activation source

cannot be acknowledged for 16 cycles of the CPU clock.

15.3.10.2 Flash Memory

When the DTC activation source is flash ready status, even if a flash ready status interrupt request is generated,

it is not acknowle dged as the DTC activation source after the RDYSTI bit in the FST register is set to 1 (flash

ready status interrupt request) and be fore the DTC sets the RDYSTI bit to 0 (no flash ready status interrupt

request). If a flash ready status interrupt req uest is generated after the D TC sets the RDYSTI bit to 0, t he DTC

acknowledges it as the activation source. 8 to 12 cycles of the CPU clock are required after the RDYSTI bit is

set to 1 and before the DTC sets the interrupt request flag to 0. If a flash ready status interrupt is generated when

a software command is executed, 9 to 16 cycles of the CPU clock are requir ed before the DTC sets the interrupt

source flag to 0. If a flash ready status interrupt request is generated during DTC operation and acknowledged

as the DTC activation source, the RDYSTI bit is set to 0 after 8 to 12 cycles of the CPU clock on completion of

the DTC transfer immediately before the DTC is activated by the source. When a software command is

executed on completion of the DTC transfer immediately before the DTC is activated, the RDYSTI bit is set to

0 after 16 cycles of the CPU clock.

15.3.10.3 Timer RC, Timer RD

When the DTC activation source is an interrupt source for timer RC or timer RD, even if an input

capture/compare match in individual timers occurs, it is not acknowledged as the DTC activation source after

the interrupt source flag is set to 1 and before the DTC sets the flag to 0. If an input capture/compare match

occurs after the DTC sets the interrupt source flag to 0, the DTC acknowledges it as the activation source. 8 to

12 cycles of the CPU clock plu s 0.5 to 1.5 cycles of the timer operating clock are required after the interrupt

source flag is set to 1 and before the DTC sets the flag to 0. If the interrupt request flag is set to 1 when a

software com mand is executed , 9 to 16 cycles of the CPU clock pl us 0.5 to 1.5 cyc les of the time r operating

clock are required before the DTC sets the interrupt source flag to 0. If individual DTC activation sources are

generated for timer RC and timer RD during DTC o peration and acknowledged , the interrupt source flag is set

to 0 after 8 to 12 cycles of the CPU clock plus 0.5 to 1.5 cycles of the timer operating clock on completion of

the DTC transfer immediately before the DTC is activated by the source. When a software command is

executed on completion of the D TC transfer immediately before the DTC is activated, the interrupt source flag

is set to 0 after 16 cycles of the CPU clock plus 0.5 to 1.5 cycles of the timer operating clock.

R8C/34C Group 15. DTC

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 213 of 723

15.3.10.4 SSU/I2C bus Receive Data Full

When the DTC activation source is SSU/I2C bus receive data full, read the SSRDR register/the ICDRR register

using a data transfer. The RDRF bit in the SSSR register/the ICSR register is set to 0 (no data in

SSRDR/ICDRR register) by reading the SSRDR register/ the ICDRR register. If an interrupt source for receive

data full is subsequently gene rated, the DTC acknowledges it as the activation source.

15.3.10.5 SSU/I2C bus Transmit Data Empty

When the DTC activation source is SSU/I2C bus transmit data empty, write to the SSTDR register/the ICDRT

transferred from registers SSTDR/ICDRT to SSTRSR/ICDRS) by writing to th e SSTDR register/the I CDRT

the activation source.

R8C/34C Group 15. DTC

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 214 of 723

15.4 Notes on DTC

15.4.1 DTC activation source

• Do not generate any DTC activation sources before entering wait mode or during wait mode.

• Do not generate any DTC activation sources before entering stop mode or during stop mode.

15.4.2 DTCENi (i = 0 to 6) Registers

• Modify bits DTCENi0 to DTCENi7 only while an interrupt request corresponding to the bit is not generated.

• When the interrupt source flag in the status register for the peripheral function is 1, do not modify the

corresponding activation source bit among bits DT CENi0 to DTCENi7.

• Do not access the DTCENi registers using DTC transfers.

15.4.3 Peripheral Modules

• Do not set the status register bit for the peripheral function to 0 using a DTC transfer.

• When the DTC activation source is SSU/I2C bus receive data full, read the SSRDR register/the ICDRR

The RDRF bit in the SSSR register/the ICSR register is set to 0 (no data in SSRDR/ICDRR register) by

reading the SSRDR register/t he ICDRR register.

However, the RDRF bit is not set to 0 by reading the SSRDR register/the ICDRR register when the DTC data

transfer setting is either of the following:

- Transfer causing the DTCCTj (j = 0 to 23) register value to change from 1 to 0 in normal mod e

- Transfer causing the DTCCRj register value to change from 1 to 0 while the RPTINT bit in the DTCCRj

• When the DTC activation source is SSU/I 2C bus transmit data empty, write to the SSTDR register/the ICDRT

transferred from registers SSTDR/ICDRT to SSTRSR/ICDRS) by writing to the SSTDR register/the ICDRT

15.4.4 Interrupt Request

No interrupt is generated for the CPU during DTC operation in any of the following cases:

- When the DTC activation source is SSU/I2C transmit data empty or flash ready status

- When performing the data transfer causing the DTCCTj (j = 0 to 23) register value to change to 0 in normal

mode

- When performing the data transfer causing the DTCCRj register value to change to 0 while the RPTINT bit in

the DTCCRj register is 1 (in terrupt generation enabled) in repeat mode

R8C/34C Group 16. General Overview of Timers

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 215 of 723

16. General Overview of Timers

The MCU has two 8-bit timers with 8-bit prescalers, three 16-bit timers, and a timer with a 4-bit counter and an 8-bit

counter. The two 8-bit timers with 8-bit prescalers are timer RA and timer RB. These timers contain a reload register to

store the default value of the counter. The one 16-bit timer is timer RC, and the two 16-bit timers are timer RD, and

have input capture and output compare functions. The 4-bit and 8-bit counters are timer RE, and has an output compare

function. All the timers operate independently.

Table 16.1 lists Functional Comparison of Timers.

R8C/34C Group 16. General Overview of Timers

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 216 of 723

Notes:

1. Rectangular waves are output in these modes. Since the waves are inverted at each overflow, the “H” and “L” level widths of

the pulses are the same.

2. The underflow interrupt can be set to timer RD1.

Table 16.1 Functional Comparison of Timers

Item Timer RA Timer RB Timer RC Timer RD Timer RE

Configuration 8-bit timer with

8-bit prescaler

(with reload

8-bit timer with 8-

bit prescaler

(with reload

16-bit timer (with

input capture and

output compare)

16-bit timer × 2 (with

input capture and

output compare)

4-bit counter

8-bit counter

Count Decrement Decrement Increment Increment/Decrement Increment

Count sources • f1

•f2

•f8

•fOCO

•fC32

•fC

•f1

•f2

•f8

•Timer RA

underflow

•f1

•f2

•f4

•f8

•f32

• fOCO40M

• fOCO-F

• TRCCLK

•f1

•f2

•f4

•f8

•f32

•fC2

• fOCO40M

• fOCO-F

• TRDCLK

•f4

•f8

•f32

•fC4

Function Count of the

internal count

source

Timer mode Timer mode Timer mode (output

compare function) Timer mode (output

compare function) —

Count of the

external count

source

Event counter

mode — Timer mode (output

compare function) Timer mode (output

compare function) —

External pulse

width/period

measurement

Pulse width

measurement

mode, pulse

period

measurement

mode

— Timer mode (input

capture function;

4 pins)

Timer mode (input

compare function; 2 × 4

pins)

—

PWM output Pulse output

mode (1), Event

counter mode (1)

Programmable

waveform

generation mode

Timer mode (output

compare function;

4 pins) (1),

PWM mode (3 pins),

PWM2 mode (1 pin)

Timer mode (output

compare function; 2

× 4

pins)

(1),

PWM mode

(2 × 3 pins),

PWM3 mode

(1 × 2 pins)

Output

compare

mode (1)

One-shot

waveform output — Programmable

one-shot

generation mode,

Programmable

wait one-shot

generation mode

PWM mode (3 pins)

PWM mode

(2 × 3 pins)

—

Three-phase

waveforms

output

— — — Reset synchronous

PWM mode (2 × 3 pins,

Sawtooth wave

modulation),

Complementary PWM

mode

(2 × 3 pins,

triangular

wave modulation, dead

time)

—

Timer Timer mode

(only fC32

count)

— — — Real-time clock

mode

Input pin TRAIO,

INT2 INT0 INT0, TRCCLK,

TRCTRG, TRCIOA,

TRCIOB, TRCIOC,

TRCIOD

INT0, TRDCLK,

TRDIOA0, TRDIOA1,

TRDIOB0, TRDIOB1,

TRDIOC0, TRDIOC1,

TRDIOD0, TRDIOD1

—

Output pin TRAO,

TRAIO TRBO TRCIOA,

TRCIOB, TRCIOC,

TRCIOD

TRDIOA0, TRDIOA1,

TRDIOB0, TRDIOB1,

TRDIOC0, TRDIOC1,

TRDIOD0, TRDIOD1

TREO

Related interrupt Timer RA

interrupt,

INT2 interrupt

Timer RB

interrupt,

INT0 interrupt

Compare match/

input capture A to D

interrupt,

Overflow interrupt,

INT0 interrupt

Compare match/input

capture A0 to D0

interrupt,

Compare match/input

capture A1 to D1

interrupt,

Overflow interrupt,

Underflow interrupt (2),

INT0 interrupt

Timer RE

interrupt

Timer stop Provided Provided Provided Provided Provided

R8C/34C Group 17. Timer RA

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 217 of 723

17. Timer RA

Timer RA is an 8-bit timer with an 8-bit prescaler.

17.1 Overview

The prescaler and timer each consist of a reload register and counter. The reload register and counter are allocated

at the same address, and can be accessed when accessing registers TRAPRE and TRA (refer to Tables 17.2 to 17.6

the Specifications of Each Mode).

The count source for t im er RA is the operating clock that regulates the timing of timer operations such as counting

and reloading.

Figure 17.1 shows a Timer RA Block Diagram. Table 17.1 lists Pin Configurati on of Timer RA.

Timer RA contains the following five operating modes:

• Timer mode: The timer counts the internal count source.

• Pulse output mode: The timer counts the internal count source and outputs pulses which invert the

polarity by underflow of the timer.

• Event counter mode: The tim er counts external pu lses.

• Pulse width measurement mode: The timer measures the pulse width of an external pulse.

• Pulse period measurement mode: The timer measures the pulse period of an external pulse.

Figure 17.1 Timer RA Block Diagram

Table 17.1 Pin Configuration of Timer RA

Pin Name Assigned Pin I/O Function

TRAIO P1_5 or P1_7 I/O Function differs according to the mode.

Refer to descriptions of individual modes

for details

TRAO P3_0 or P3_7 Output

Counter

Reload

TRAPRE register

(prescaler)

Data bus

Timer RA interrupt

Write to TRAMR register

Write 1 to TSTOP bit

TCSTF, TSTOP: TRACR register

TEDGSEL, TOPCR, TOENA, TIPF1, TIPF0, TIOGT1, TIOGT0: TRAIOC register

TMOD2 to TMOD0, TCK2 to TCK0, TCKCUT: TRAMR register

Toggle

flip-flop

QCLR

TOENA bit

TRAO pin (2)

TCSTF

bit

TMOD2 to TMOD0

= 011b or 100b

Counter

Reload

TRA register

(timer)

Count control

circle

TMOD2 to TMOD0 = 001b

TOPCR bit

Underflow signal

Measurement

completion signal

TEDGSEL = 1

TEDGSEL = 0

Notes:

1. Bits TRAIOSEL0 and TRAIOSEL1 in the TRASR register are used to select which pin is assigned.

2. Bit TRAOSEL0 in the TRASR register is used to select which pin is assigned.

3. The POL bit in the INT2IC register is used to select the INT2 level when the event input is enabled.

TRAIO pin (1)

TCK2 to TCK0 bit

TMOD2 to TMOD0

= other than 010b

TMOD2 to TMOD0

= 010b

Polarity

switching

Digital

filter

TIPF1 to TIPF0 bits

= 01b

= 10b

= 11b

f32

TIPF1 to TIPF0 bits

= other than

000b

= 00b

= 000b

= 001b

= 011b

= 010b

fOCO

= 100b

fC32

TIOGT1 to TIOGT0 bits

= 01b

= 10b

Event input enabled at INT2 level (3)

Event input always enabled = 00b

Event enabled for “L” period of

TRCIOD (timer RC output)

= 110b

TCKCUT

bit

R8C/34C Group 17. Timer RA

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 218 of 723

17.2 Registers

17.2.1 Timer RA Control Register (TRACR)

Notes:

1. Refer to 17.8 Notes on Timer RA for precautions regarding bits TSTART and TCSTF.

2. When the TSTOP bit is set to 1, bits TSTART and TCST F and registers TR APRE and TRA are set to the values

after a reset.

3. Bits TEDGF and TUNDF can be se t to 0 by writing 0 to these bits by a program. However, their value remains

unchanged when 1 is written.

4. Set to 0 in timer mode, pulse output mode, and event counter mode.

In pulse width measurement mode and pulse period measurement mode, use the MOV instruction to set the

TRACR register. If it is necessary to avoid changing the values of bits TEDGF and TUNDF, write 1 to them.

17.2.2 Timer RA I/O Control Register (TRAIOC)

Address 0100h

Bitb7b6b5b4b3b2b1b0

Symbol — — TUNDF TEDGF — TSTOP TCSTF TSTART

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 TSTART Timer RA count start bit (1) 0: Count stops

1: Count starts R/W

b1 TCSTF Timer RA count status flag (1) 0: Count stops

1: During count R

b2 TSTOP Timer RA count forcible stop bit (2) When this bit is set to 1, the count is forcibly stopped.

When read, its content is 0. R/W

b3 — Nothing is assig ned. If necessary, set to 0. When read, the content is 0. —

b4 TEDGF Active edge judgment flag (3, 4) 0: Active edge not received

1: Active edge received (end of measurement period) R/W

b5 TUNDF Timer RA underflow flag (3, 4) 0: No underflow

1: Underflow R/W

b6 — Nothing is assig ned. If necessary, set to 0. When read, the content is 0. —

b7 —

Address 0101h

Bitb7b6b5b4b3b2b1 b0

Symbol TIOGT1 TIOGT0 TIPF1 TIPF0 TIOSEL TOENA TOPCR TEDGSEL

After Reset0000000 0

Bit Symbol Bit Name Function R/W

b0 TEDGSEL TRAIO polarity switch bit Function varies according to the operating mode. R/W

b1 TOPCR TRAIO output control bit R/W

b2 TOENA TRAO output enable bi t R/W

b3 TIOSEL Hardware LIN function select bit R/W

b4 TIPF0 TRAIO input filter select bit R/W

b5 TIPF1 R/W

b6 TIOGT0 TRAIO event input control bit R/W

b7 TIOGT1 R/W

R8C/34C Group 17. Timer RA

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 219 of 723

17.2.3 Timer RA Mode Register (TRAMR)

When both the TSTART and TCSTF bits in the TRACR register are set to 0 (count stops), rewrite this register.

17.2.4 Timer RA Prescaler Register (TRAPRE)

Note:

1. When th e TST OP bi t in the TRACR registe r is set to 1, the TRAPRE register is set to FFh.

Address 0102h

Bitb7b6b5b4b3b2b1b0

Symbol TCKCUT TCK2 TCK1 TCK0 — TMOD2 TMOD1 TMOD0

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 TMOD0 Timer RA operati ng mode select bit b2 b1 b0

0 0 0: Timer mode

0 0 1: Pulse output mode

0 1 0: Event counter mode

0 1 1: Pulse width measurement mode

1 0 0: Pulse period measurement mode

1 0 1: Do not set.

1 1 0: Do not set.

1 1 1: Do not set.

R/W

b1 TMOD1 R/W

b2 TMOD2 R/W

b3 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b4 TCK0 Timer RA count source select bit b6 b5 b4

0 0 0: f1

0 0 1: f8

0 1 0: fOCO

0 1 1: f2

1 0 0: fC32

1 0 1: Do not set.

1 1 0: fC

1 1 1: Do not set.

R/W

b5 TCK1 R/W

b6 TCK2 R/W

b7 TCKCUT Timer RA count source cutoff bit 0: Provides count source

1: Cuts off count source R/W

Address 0103h

Bitb7b6b5b4b3b2b1b0

Symbol————————

After Reset11111111(Note 1)

Bit Mode Function Setting Range R/W

b7 to b0 Timer mode Counts an internal count so urce 00h to FFh R/W

Pulse output mode 00h to FFh R/W

Event counter mode Counts an external count source 00h to FFh R/W

Pulse width measurement mode Measure pulse width of input pulses from

external (counts internal count source) 00h to FFh R/W

Pulse period measurement mode Measure pulse period of input pulses from

external (counts internal count source) 00h to FFh R/W

R8C/34C Group 17. Timer RA

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 220 of 723

17.2.5 Timer RA Register (TRA)

Note:

1. When th e TST OP bi t in the TRACR registe r is set to 1, the TRAPRE register is set to FFh.

17.2.6 Timer RA Pin Select Register (TRASR)

The TRASR register selects which pin is assigned to the timer RA I/O. To use the I/O pin for timer RA, set this

Set the TRASR register before setting the timer RA associated registers. Also, do not change the setting value

in this register during timer RA operation.

Address 0104h

Bitb7b6b5b4b3b2b1b0

Symbol————————

After Reset11111111(Note 1)

Bit Mode Function Setting Range R/W

b7 to b0 All modes Counts on underflow of TRAPRE register 00h to FFh R/W

Address 0180h

Bitb7b6b5 b4 b3 b2 b1 b0

Symbol — — — — TRAOSEL0 — TRAIOSEL1 TRAIOSEL0

After Reset000 0 0 0 0 0

Bit Symbol Bit Name Function R/W

b0 TRAIOSEL0 TRAIO pin se lect bit b1 b0

0 0: TRAIO pin not used

0 1: P1_7 assigned

1 0: P1_5 assigned

1 1: Do not set.

R/W

b1 TRAIOSEL1 R/W

b2 — Reserved bit Set to 0. R/W

b3 TRAOSEL0 TRAO pin select bit 0: P3_7 assigned

1: P3_0 assigned R/W

b4 — Reserved bit Set to 0. R/W

b5 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b6 —

b7 —

R8C/34C Group 17. Timer RA

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 221 of 723

17.3 Timer Mode

In this mode, the timer counts an internally generated count source (refer to Table 17.2 Timer Mode

Specifications).

17.3.1 Timer RA I/O Control Register (TRAIOC) in Timer Mode

Table 17.2 Timer Mode Specifications

Item Specification

Count sources f1, f2, f8, fOCO, fC32, fC

Count operations • Decrement

• When the timer underflows, the contents of the reload register are reloaded

and the count is continued.

Divide ratio 1/(n+1)(m+1)

n: Value set in TRAPRE register, m: Value set in TRA register

Count start condition 1 (count starts) is written to the TSTART bit in the TRACR register.

Count stop conditions • 0 (count stops) is written to the TSTART bit in the TRACR register.

• 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register.

Interrupt request

generation timing When timer RA u nderflows [timer RA interrupt].

TRAIO pin function Programmable I/O port

TRAO pin function Programmable I/O port

Read from timer The count value can be read by reading registers TRA and TRAPRE.

Write to timer • When registers TRAPRE and TRA are written while the count is stopped,

values are written to both the relo ad register and counter.

• When r egisters TRAPRE and TRA are written during the count, values are

written to the reload register and counter (refer to 17.3.2 Timer Write Control

during Count Operation).

Address 0101h

Bitb7b6b5b4b3b2b1 b0

Symbol TIOGT1 TIOGT0 TIPF1 TIPF0 — TOENA TOPCR TEDGSEL

After Reset0000000 0

Bit Symbol Bit Name Function R/W

b0 TEDGSEL TRAIO polarity switch bit Set to 0 in timer mode. R/W

b1 TOPCR TRAIO output control bit R/W

b2 TOENA TRAO output enable bi t R/W

b3 — Reserved bit Set to 0. R/W

b4 TIPF0 TRAIO input filter select bit Set to 0 in timer mode. R/W

b5 TIPF1 R/W

b6 TIOGT0 TRAIO event input control bit R/W

b7 TIOGT1 R/W

R8C/34C Group 17. Timer RA

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 222 of 723

17.3.2 Timer Write Control during Count Operation

Timer RA has a prescaler and a timer (which counts the prescale r underflows). The prescaler and timer each

consist of a reload register and a counter. When writing to the prescaler or timer, values are written to both the

reload register and counter.

However, values are transferred from the reload regist er to the count er of the prescal er in synchronizatio n with

the count source. In addition, values are transferred from the reload register to the counter of the timer in

synchronization with prescaler underflows. Therefore, if the prescaler or timer is written to when count

operation is in progress, the counter value is not updated immediately after the WR ITE instruction is executed.

Figure 17.2 shows an Operating Example of Timer RA when Counter Value is Rewritten during Count

Operation.

Figure 17.2 Operating Example of Timer RA when Counter Value is Rewritten during Count

Operation

Count source

Reload register of

timer RA prescaler

IR bit in TRAIC

Counter of

timer RA prescaler

Reload register of

timer RA

Counter of timer RA

Set 01h to the TRAPRE register and 25h to

the TRA register by a program.

After writing, the reload register is

written to at the first count source.

Reload at

second count

source Reload at

underflow

After writing, the reload register is

written to at the first underflow.

Reload at the second underflow

The IR bit remains unchanged until underflow is

generated by a new value.

05h 04h 01h 00h 01h 00h 01h 00h 01h 00h06h

New value (01h)Previous value

New value (25h)Previous value

03h 24h02h 25h

The above applies under the following conditions.

Both bits TSTART and TCSTF in the TRACR register are set to 1 (during count).

R8C/34C Group 17. Timer RA

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 223 of 723

17.4 Pulse Output Mode

In pulse output mode, the internally gen erated count source is counted, and a pulse with in verted polarity is output

from the TRAIO pin each time the timer underflows (refer to Table 17.3 Pu ls e Output Mode Specifications).

Note:

1. The level of the output pulse becomes the level when the pulse output starts when the TRAMR

Table 17.3 Pulse Output Mode Specifications

Item Specification

Count sources f1, f2, f8, fOCO, fC32, fC

Count operations • Decrement

• When the timer underflows, the contents in the reload register is reloa ded and

the count is continued.

Divide ratio 1/(n+1)(m+1)

n: Value set in TRAPRE register, m: Value set in TRA register

Count start conditio n 1 (count starts) is written to the TSTA R T bit in the TR ACR re gis te r.

Count stop conditions • 0 (count stops) is written to the TSTART bit in the TRACR register.

• 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register.

Interrupt request

generation timing When timer RA underflows [timer RA interrupt].

TRAIO pin function Pulse output, programmable output port

TRAO pin function Programmable I/O port or inverted output of TRAIO

Read from timer The count value can be rea d by reading registers TRA and TRAPRE.

Write to timer • When registers TRAPRE and TRA are written while the count is stopped , values

are written to both the reload r egister and counter.

• When registers TRAPRE and TRA are written during the count, values are

written to the reload register and counter (refer to 17.3.2 Timer Write Control

during Count Operation).

Selectable func tion s • TRAIO signal polarity switch function

The level when the pulse output starts is selected by the TEDGSEL bit in the

TRAIOC register. (1)

• TRAO output function

Pulses inverted from the TRAIO output p olarity can be output from the TRAO pin

(selectable by the TOENA bit in the TRAIOC register).

• Pulse output stop function

Output from the TRAIO pi n is stopped by th e TOPCR bit in the TRAIOC register.

•TRAIO pin select function

P1_5 or P1_7 is selected by bits TRAIOSEL0 to TRAIOSEL1 in the TRASR

• TRAO pin sele ct function

P3_0 or P3_7 is selected by the TRAOSEL0 bit in the TRASR register.

R8C/34C Group 17. Timer RA

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 224 of 723

17.4.1 Timer RA I/O Control Register (TRAIOC) in Pulse Output Mode

Address 0101h

Bitb7b6b5b4b3b2b1 b0

Symbol TIOGT1 TIOGT0 TIPF1 TIPF0 — TOENA TOPCR TEDGSEL

After Reset0000000 0

Bit Symbol Bit Name Function R/W

b0 TEDGSEL TRAIO polarity switch bit 0: TRAIO output starts at “H”

1: TRAIO output starts at “L” R/W

b1 TOPCR TRAIO output control bit 0: TRAIO output

1: Port P1_5 or P1_7 R/W

b2 TOENA TRAO output enable bit 0: Port P3_0 or P3_7

1: TRAO output (inverted TRAIO output from the

port P3_0 or P3_7)

R/W

b3 — Reserved bit Set to 0. R/W

b4 TIPF0 TRAIO input filter select bit Set to 0 in pulse output mode. R /W

b5 TIPF1 R/W

b6 TIOGT0 TRAIO event input control bit R/W

b7 TIOGT1 R/W

R8C/34C Group 17. Timer RA

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 225 of 723

17.5 Event Counter Mode

In event counter mode, external signal inputs to the TRAIO pin are counted (refer to Table 17.4 Event Counter

Mode Specifications).

Note:

1. The level of the output pulse becomes the level when the pulse output starts when the TRAMR

Table 17.4 Event Counter Mode Specifications

Item Specification

Count source External signal which is input to TRAIO pin (active edge selectable by a program)

Count operations • Decrement

• When the timer underflows, the contents of the reload register are reloaded and

the count is continued.

Divide ratio 1/(n+1)(m+1)

n: setting value of TRAPRE register, m: setting value of TRA register

Count start condition 1 (count starts) is written to the TSTART bit in the TRACR register.

Count stop conditions • 0 (count stops) is written to the TSTART bit in the TRACR register.

• 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register.

Interrupt request

generation timing When timer RA underflows [timer RA interrupt].

TRAIO pin function Count source input

TRAO pin function Programmable I/O port or pulse output (1)

Read from timer The count value can be rea d by reading registers TRA and TRAPRE.

Write to timer • When registers TRAPRE and TRA are written while the count is stopped, values

are written to both the reload register and counter.

• When registers TRAPRE and TRA are written during the count, values are

written to the reload register and coun ter (refer to 17.3.2 Timer Write Control

during Count Operation).

Selectable func tion s • TRAIO input polarity switch function

The active edge of the count source is selected by the TEDGSEL bit in the

TRAIOC register.

• Count source input pin select function

P1_5 or P1_7 is selected by bits TRAIOSEL0 to TRAIOSEL1 in the TRASR

• Pulse output fu nction

Pulses of inverted polarity can be output from the TRAO pin each time the timer

underflows (selectable by the TOENA bit in the TRAIOC register). (1)

• TRAO pin select function

P3_0 or P3_7 is selected by the TRAOSEL0 bit in the TRASR register .

• Digital filter function

Whether enabling or disabling the digital filter and the sampling frequency is

selected by bits TIPF0 and TIPF1 in the TRAIOC register.

• Event input control function

The enabled period for the event input to the TRAIO pin is selected by b i ts

TIOGT0 and TIOGT1 in the TRAIOC register.

R8C/34C Group 17. Timer RA

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 226 of 723

17.5.1 Timer RA I/O Control Register (TRAIOC) in Event Counter Mode

Notes:

1. When the same value from the TRAIO pin is sample d three times continuously, the input is determined.

2. Make the following settings to use event input enabled at INT2 level:

• Set the INT2EN bit in the INTEN register to 1 (INT2 input enabled) and the INT2PL bit to 0 (one edge).

• Set the INT2 polarity by the POL bit in the INT2IC register.

When the POL bit is set 0 (falling edge selected), the event input for the INT2 high-level period is enabled.

When the POL bit is set 1 (rising edge selected), the event input for the INT2 low-level period is enabled.

• Set the PDi_j (j = 2 or 6) bit in the PDi (i = 3 or 6) register for the port assigned as the INT2 pin to 0 (input

mode).

• Select the INT2 digital filter by bits INT2F1 to INT2F0 in the INTF register.

The IR bit in the INT2IC register is set to 1 (interrupt req uested) in accordance with the setting of the POL bit in

the INT2IC register and the INT2PL bit in the INTEN register and a change in th e INT2 pin input (refer to 11.8

Notes on Interrupts).

For details on interrupts, refer to 11. Interrupts.

Address 0101h

Bitb7b6b5b4b3b2b1 b0

Symbol TIOGT1 TIOGT0 TIPF1 TIPF0 — TOENA TOPCR TEDGSEL

After Reset0000000 0

Bit Symbol Bit Name Function R/W

b0 TEDGSEL TRAIO polarity switch bit 0: Starts counting at rising edge of the TRAIO input

and TRAO starts output at “L”

1: Starts counting at falling edge of the TRAIO input

and TRAO starts output at “H”

R/W

b1 TOPCR TRAIO output control bit Set to 0 in event counte r mode. R/W

b2 TOENA TRAO output enable bit 0: Port P3_0 or P3_7

1: TRAO output R/W

b3 — Reserved bit Set to 0. R/W

b4 TIPF0 TRAIO input filter select bit (1) b5 b4

0 0: No filter

0 1: Filter with f1 sampling

1 0: Filter with f8 sampling

1 1: Filter with f32 sampling

R/W

b5 TIPF1 R/W

b6 TIOGT0 TRAIO event input control bit b7 b6

0 0: Event input always enabled

0 1: Event input enabled at INT2 level (2)

1 0: Event input enabled for “L” period of TRCIOD

(timer RC output)

1 1: Do not set.

R/W

b7 TIOGT1 R/W

R8C/34C Group 17. Timer RA

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 227 of 723

17.6 Pulse Width Measurement Mode

In pulse width measurement mode, the pulse width of an external signal input to the TRAIO pin is measured (refer

to Table 17.5 Pulse Width Measurement Mode Specifications).

Figure 17.3 shows an Operating Example of Pulse Width Measurement Mode.

Table 17.5 Pulse Width Measurement Mode Specifications

Item Specification

Count sources f1, f2, f8, fOCO, fC32, fC

Count operations • Decrement

• Continuou sly counts the selected signal only wh en measurement pulse is “H”

level, or conversely only “L” level.

• When the timer underflows, the contents of the reload register are reloaded

and the count is continued.

Count start condition 1 (count starts) is written to the TSTART bit in the TRACR register.

Count stop conditions •0 (count stops) is written to the TSTART bit in the TRACR register.

• 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register.

Interrupt request

generation timing • When timer RA und erflows [timer RA interrupt].

• Rising or falling of the TRAIO input (end of measurement period) [tim er RA

interrupt]

TRAIO pin function Measured pulse input

TRAO pin function Programmable I/O port

Read from timer The count value can be read by reading registers TRA and TRAPRE.

Write to timer • When registers TRAPRE and TRA are written while the count is stopped,

values are written to both the reload register and counter.

• When registers TRAPRE and TRA are written during the count, values a re

written to the reload register and coun ter (refer to 17.3.2 Timer Write

Control during Count Operation).

Selectable func tion s • Measurement level setting

The “H” level or “L” level period is selected by the TEDGSEL bit in the

TRAIOC register.

• Measured pulse input pin select function

P1_5 or P1_7 is selected by bits TRAIOSEL0 to TRAIOSEL1 in the TRASR

• Digital filter function

Whether enabling or disabling the digital filter and the sampling frequency is

selected by bits TIPF0 and TIPF1 in the TRAIOC register.

R8C/34C Group 17. Timer RA

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 228 of 723

17.6.1 Timer RA I/O Control Register (TRAIOC) in Pulse Width Measurement

Mode

Note:

1. When the same value from the TRAIO pin is sample d three times continuously, the input is determined.

Address 0101h

Bitb7b6b5b4b3b2b1 b0

Symbol TIOGT1 TIOGT0 TIPF1 TIPF0 — TOENA TOPCR TEDGSEL

After Reset0000000 0

Bit Symbol Bit Name Function R/W

b0 TEDGSEL TRAIO polarity switch bit 0: TRAIO input starts at “L”

1: TRAIO input starts at “H” R/W

b1 TOPCR TRAIO output control bit Set to 0 in pulse width measurement mode. R/W

b2 TOENA TRAO output enable bi t R/W

b3 — Reserved bit Set to 0. R/W

b4 TIPF0 TRAIO input filter select bit (1) b5 b4

0 0: No filter

0 1: Filter with f1 sampling

1 0: Filter with f8 sampling

1 1: Filter with f32 sampling

R/W

b5 TIPF1 R/W

b6 TIOGT0 TRAIO event input control bit Set to 0 in pulse width measuremen t mode. R/W

b7 TIOGT1 R/W

R8C/34C Group 17. Timer RA

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 229 of 723

17.6.2 Operating Example

Figure 17.3 Operating Example of Pulse Width Measurement Mode

FFFFh

0000h

Content of counter (hex)

n = high level: the contents of TRA register, low level: the contents of TRAPRE register

Count start

Count stop

Underflow

Period

TSTART bit in

TRACR register

Measured pulse

(TRAIO pin input)

TEDGF bit in

TRACR register

TUNDF bit in

TRACR register

• “H” level width of measured pulse is measured. (TEDGSEL = 1)

• TRAPRE = FFh

Set to 1 by program

IR bit in TRAIC

Set to 0 by program

Count stop

Count start

Set to 0 when interrupt request is acknowledged, or set by program

Count start

Set to 0 by program

The above applies under the following conditions.

R8C/34C Group 17. Timer RA

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 230 of 723

17.7 Pulse Period Measurement Mode

In pulse period measurement mode, the pulse period of an external signal input to the TRAIO pin is measured

(refer to Table 17.6 Pulse Period Measurement Mode Specifications).

Figure 17.4 shows an Operating Example of Pulse Period Measurement Mode.

Note:

1. Input a pulse with a period longer than twice the timer RA prescaler period. Input a pulse with a

longer “H” and “L” width than the timer RA prescaler period. If a pulse with a shorter period is input

to the TRAIO pin, the input may be ignored.

Table 17.6 Pulse Period Measurement Mode Specifications

Item Specification

Count sources f1, f2, f8, fOCO, fC32, fC

Count operations • Decrement

• After the active edge of the measured pulse is input, the contents of the r ead-

out buffer are re tained at the first underflow of timer RA pre scaler. Then timer

RA reloads the contents in the reload register at the second und erflow of

timer RA prescaler and continues counting.

Count start conditio n 1 (count starts) is writte n t o the TST ART bit in the TRACR register.

Count stop conditions • 0 (count stops) is written to TSTART bit in the TRACR register.

• 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register.

Interrupt request

generation timing • When timer RA underflows or reloads [timer RA interrupt].

• Rising or falling of the TRAIO input (end of measurement period) [timer RA

interrupt]

TRAIO pin function Measured pulse input (1)

TRAO pin function Programmable I/O p ort

Read from timer The count value can be read by reading registers TRA and TRAPRE.

Write to timer • When registers TRAPRE and TRA are written while the count is stopped,

values are written to both the reload register and counter.

• When registers TRAPRE and TRA are written during the count, values are

written to the reload register and counter (refer to 17.3.2 Timer Write

Control during Count Operation).

Selectable func tion s • Measurement period selection

The measurement period of the inpu t pulse is selected by the TEDGSEL in

the TRAIOC register.

• Measured pulse input pin select function

P1_5 or P1_7 is selected by bits TRAIOSEL0 to TRAIOSEL1 in the TRASR

• Digital filter function

Whether enabling or disablin g the digital filter and the sampling frequency is

selected by bits TIPF0 and TIPF1 in the TRAIOC register.

R8C/34C Group 17. Timer RA

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 231 of 723

17.7.1 Timer RA I/O Control Register (TRAIOC) in Pulse Period Measurement

Mode

Note:

1. When the same value from the TRAIO pin is sample d three times continuously, the input is determined.

Address 0101h

Bitb7b6b5b4b3b2b1 b0

Symbol TIOGT1 TIOGT0 TIPF1 TIPF0 — TOENA TOPCR TEDGSEL

After Reset0000000 0

Bit Symbol Bit Name Function R/W

b0 TEDGSEL TRAIO polarity switch bit 0: Measures measurement pulse from one rising

edge to next rising edge

1: Measures measurement pulse from one falling

edge to next falling edge

R/W

b1 TOPCR TRAIO output control bit Set to 0 in pulse period measurement mode. R/W

b2 TOENA TRAO output enable bi t R/W

b3 — Reserved bit Set to 0. R/W

b4 TIPF0 TRAIO input filter select bit (1) b5 b4

0 0: No filter

0 1: Filter with f1 sampling

1 0: Filter with f8 sampling

1 1: Filter with f3 2 sampling

R/W

b5 TIPF1 R/W

b6 TIOGT0 TRAIO event input control bit Set to 0 in pulse period measurement mode. R/W

b7 TIOGT1 R/W

R8C/34C Group 17. Timer RA

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 232 of 723

17.7.2 Operating Example

Figure 17.4 Operating Example of Pulse Period Me asurement Mode

Underflow signal of

timer RA prescaler

Notes:

1. The contents of the read-out buffer can be read by reading the TRA register in pulse period measurement m ode.

2. After an active edge of the measured pulse is input, the TEDGF bit in the TRACR register is set to 1 (active edge received) when the

timer RA prescaler underflows for the second time.

3. The TRA register should be read before t he next active edge is input after the TEDGF bit is set to 1 (active edge received).

The contents in the read-out buffer are retained until the TRA register is read. If the TRA register is not read before the next active edge

is input, the measured result of the previous period is retained.

4. To set to 0 by a program, use a MOV instruction to write 0 to the TEDGF bit in the TRACR register. At the same time, write 1 to the

TUNDF bit in the TRACR register.

5. To set to 0 by a program, use a M OV instruction to write 0 to the TUNDF bit. At the same time, write 1 to the TEDGF bit.

6. Bits TUNDF and TEDGF are both s et to 1 if timer RA und erflows and reloads on an active edge simultaneously.

0Eh 0Dh 0Fh 0Eh 0Dh 0Ch 0Bh 0Ah 09h 0Fh 0Eh 0Dh 01h 00h 0Fh 0Eh0Fh

0Dh

0Fh 0Bh 0Ah 0Dh 01h 00h 0Fh 0Eh09h

TSTART bit in

TRACR register

TEDGF bit in

TRACR register

Measurement pulse

(TRAIO pin input)

Contents of TRA

Contents of read-out

buffer (1)

IR bit in TRAIC

TUNDF bit in

TRACR register

Set to 1 by program

Count st art

TRA reloaded

TRA read (3)

Retained

Set to 0 by program

Conditions: The period from one rising edge to the next rising edge of the measured pulse is measured (TEDGSEL = 0) with

the default value of the TRA register as 0Fh.

0Eh

TRA reloaded

Retained

Set to 0 when interrupt request is acknowledged, or set by program

Set to 0 by program

Underflow

(Note 2) (Note 2)

(Note 4) (Note 6)

(Note 5)

R8C/34C Group 17. Timer RA

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 233 of 723

17.8 Notes on Timer RA

• Timer RA stops countin g after a reset. Set the values in the timer RA and timer RA prescalers before the count

starts.

• Even if the prescaler and timer RA are read out in 16-bit units, these registers are read 1 byte at a time by the

MCU. Consequently, the timer value may be updated during the period when these two registers are being read.

• In pulse width measurement mode and pulse period measurement mode, bits TEDGF and TUNDF in the TRACR

written. When using the READ-MODIFY-WRITE instruction for the TRACR register, the TEDGF or TUNDF

bit may be set to 0 alt hough these bits are set to 1 while the i nstruction is being executed. In this case, w rite 1 to

the TEDGF or TUNDF bit which is not supposed to be set to 0 with the MOV instruction.

• When changing to pulse period measurement mode from another mode, the contents of bits TEDGF and TUNDF

are undefined. Write 0 to bits TEDGF and TUNDF before the count starts.

• The TEDGF bit may be set to 1 by the first timer RA prescaler underflow generated after the count starts.

• When using the pulse period measurement mode, leave two or more periods of the timer RA prescaler

immediately after the count starts, then set the TEDGF bit to 0.

• The TCSTF bit retains 0 (count stops) for 0 to 1 cycle of the count source after setting the TSTART bit to 1 (count

starts) while the count is stopped.

During this time, do not access registers associated with timer RA (1) other than the TCSTF bit. Timer RA starts

counting at the first valid edge of the coun t source after the TCSTF bit is set to 1 (during count).

The TCSTF bit remains 1 for 0 to 1 cycle of the count source after setting the TSTART bit to 0 (count stops)

while the count is in progress. Timer RA counting is stopped when the TCSTF bit is set to 0.

During this time, do not access registers associated with timer RA (1) other than the TCSTF bit.

Note:

1. Registers associated with timer RA: TRACR, TRAIOC, TRAMR, TRAPRE, and TRA.

• When the TRAPRE register is continuously written during count operation (TCSTF bit is set to 1), allow three or

more cycles of the count source clock for each write interval.

• When the TRA register is continuously written during count operation (TCSTF bit is set to 1), allow three or

more cycles of the prescaler underflow for each write interval.

R8C/34C Group 18. Timer RB

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 234 of 723

18. Timer RB

Timer RB is an 8-bit timer with an 8-bit prescaler.

18.1 Overview

The prescaler and timer each consist of a reload register and counter (refer to Tables 18.2 to 18.5 the

Specifications of Each Mode). Timer RB has timer RB primary and timer RB secondary as reload registers.

The count source for timer RB is the operating clock that regulates the timing of timer operations such as counting

and reloading.

Figure 18.1 shows a Timer RB Block Diagram. Table 18.1 lists Pin Configuration of Timer RB.

Timer RB has four operation modes listed as follows:

• Timer mode: The timer counts an internal count source (peripheral

function clock or timer RA underflows ).

• Programmable waveform generation mode: The timer outputs pulses of a given width successively.

• Programmable one-shot generation mode: The timer ou tpu ts a one-shot pulse.

• Programmable wait one-shot generation mode: The timer outputs a delayed one-shot pulse.

Figure 18.1 Timer RB Block Diagram

Table 18.1 Pin Configuration of Timer RB

Pin Name Assigned Pin I/O Function

TRBO P1_3 or P3_1 Output

Pulse output (Programmable waveform

generation mode, Programmable one-shot

generation mode, Programmable wait one-

shot generation mode)

INT0PL bit

= 00b

= 01b

= 11b

= 10b

Timer RA underflow

Bits TCK1 to TCK0

TSTART bit

TRBPRE register

(prescaler)

Timer RB interrupt

INT0 interrupt

Write 1 to TSTOP bit

Toggle

flip-flop

QCLR

TOPL = 1

TOPL = 0P1_3 bit in P1 regist er or

P3_1 bit in P3 regist er

f2 TMOD1 to TMOD0 bits

= 10b or 11b

TOSSTF bit

Polarity

select

INOSEG bit

Input polarity

selected to be one

edge or both edges

Digital filter

INT0 pin

INT0EN bit

Bits TMOD1 to TMOD0

= 01b, 10b, 11b

Counter

Reload

Counter (timer RB)

Reload

TRBPR

Data bus

TRBSC

TCKCUT bit

INOSTG bit

TSTART, TCSTF: Bits in TRBCR register

TOSSTF: Bit in TRBOCR register

TOPL, TOCNT, INOSTG, INOSEG: Bits in TRBIOC register

TMOD1 to TMOD0, TCK1 to TCK0, TCKCUT: Bits in TRBMR register

(Timer)

TOCNT = 0

TOCNT = 1

Bits TMOD1 to TMOD0

= 01b, 10b, 11b

TRBO pin (1)

Note:

1. The TRBOSEL0 bit in the T RBRCSR r egister is u sed to select which pin is assigned.

R8C/34C Group 18. Timer RB

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 235 of 723

18.2 Registers

18.2.1 Timer RB Control Register (TRBCR)

Notes:

1. Refer to 18.7 Notes on Timer RB for precautions regarding bits TSTART, TCSTF and TSTOP.

2. When the TSTOP bit is set to 1, registers TRBPRE, TRBSC, TRBPR, and bits TSTART and TCSTF, and the

TOSSTF bit in the TRBOCR register are set to values after a reset.

3. Indicates that count operation is in progress in timer mod e or programmable waveform mod e. In programmable

one-shot generat ion mode or programmable wait on e-shot generation mode , indicates that a one-shot pulse

trigger has been acknowledged.

18.2.2 Timer RB One-Shot Control Register (TRBOCR)

Note:

1. When 1 is set to th e TST OP bi t in the TRBCR register, the TOSSTF bit is set to 0.

This register is enabled when bits TMOD1 to TMOD0 in the TRBMR register is set to 10b (programmable one-

shot generation mode) or 11b (programmable wait one-shot generation mode).

Address 0108h

Bitb7b6b5b4b3b2b1b0

Symbol — — — — — TSTOP TCSTF TSTART

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 TSTART Timer RB count start bit (1) 0: Count stops

1: Count starts R/W

b1 TCSTF Timer RB count status flag (1) 0: Count stops

1: During count (3) R

b2 TSTOP Timer RB count forcible stop bit (1, 2) When this bit is set to 1, the count is forcibly

stopped. When read, the content is 0. R/W

b3 — Nothing is assig ned. If necessary, set to 0. When read, the content is 0. —

b4 —

b5 —

b6 —

b7 —

Address 0109h

Bitb7b6b5b4b3b2b1b0

Symbol — — — — — TOSSTF TOSSP TOSST

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 TOSST Timer RB one-shot start bit When this bit is set to 1, one-shot trigger

generated. When read, its content is 0. R/W

b1 TOSSP Timer RB one-sho t sto p bit When this bit is set to 1, counting of one-shot

pulses (including programmable wait one-shot

pulses) stops. When read, the content is 0.

R/W

b2 TOSSTF Timer RB one-shot status flag (1) 0: One-shot stopped

1: One-shot operating (Including wait period) R

b3 — Nothing is assig ned. If necessary, set to 0. When read, the content is 0. —

b4 —

b5 —

b6 —

b7 —

R8C/34C Group 18. Timer RB

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 236 of 723

18.2.3 Timer RB I/O Control Register (TRBIOC)

18.2.4 Timer RB Mode Register (TRBMR)

Notes:

1. Change bits TMOD1 and TMOD0; TCK1 and TCK0; and TCKCUT when both the TSTART and TCSTF bits in the

TRBCR register set to 0 (count stops).

2. The TWRC bit can be set to either 0 or 1 in timer mode. In programmable waveform generation mode,

programmable one-shot generation mode, or programmable wait one-shot generation mode, the TWRC bit must

be set to 1 (write to reload register only).

3. To use the underflow signal of timer RA as the count source for timer RB, set timer RA in timer mode, pulse

output mode, or event count mode.

Address 010Ah

Bitb7b6b5b4b3b2b1b0

Symbol — — — — INOSEG INOSTG TOCNT TOPL

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 TOPL Timer RB output level select bit Function varies according to the operating mode. R/W

b1 TOCNT Timer RB output switch bit R/W

b2 INOSTG One-shot trigger control bit R/W

b3 INOSEG One-shot trigger polarity select bit R/W

b4 — Nothing is assig ned. If necessary, set to 0. When read, the content is 0. —

b5 —

b6 —

b7 —

Address 010Bh

Bitb7b6b5b4b3b2b1b0

Symbol TCKCUT — TCK1 TCK0 TWRC — TMOD1 TMOD0

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 TMOD0 Timer RB operating mode select bit (1) b1 b0

0 0: Timer mode

0 1: Programmable waveform ge neration mode

1 0: Programmable one-shot generation mode

1 1: Programmable wait one-shot generation

mode

R/W

b1 TMOD1 R/W

b2 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b3 TWRC Timer RB write control bit (2) 0: Write to reload register and counter

1: Write to reload register only R/W

b4 TCK0 Timer RB count source select bit (1) b5 b4

0 0: f1

0 1: f8

1 0: Timer RA underflow (3)

1 1: f2

R/W

b5 TCK1 R/W

b6 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b7 TCKCUT Timer RB count source cutoff bit (1) 0: Provides count source

1: Cuts off count source R/W

R8C/34C Group 18. Timer RB

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 237 of 723

18.2.5 Timer RB Prescaler Register (TRBPRE)

When the TSTOP bit in the TRBCR register is set to 1, the TRBPRE register is set to FFh.

18.2.6 Timer RB Secondary Register (TRBSC)

Notes:

1. The values of registers TRBPR and TRBSC are reloaded to the counter alterna tely and counted.

2. The count value can be read out by reading the TRBPR register even when the secondary period is being

counted.

When the TSTOP bit in the TRBCR register is set to 1, the TRBSC register is set to FFh.

To write to the TRBSC register, perform the following steps.

(1) Write the value to the TRBSC register.

(2) Write the value to the TRBPR register. (If the value does not change, write the same value second time.)

Address 010Ch

Bitb7b6b5b4b3b2b1b0

Symbol————————

After Reset11111111

Bit Mode Function Setting Range R/W

b7 to b0 Timer mode Counts an internal count source or

timer RA underflows 00h to FFh R/W

Programmable wavefo rm generation

mode 00h to FFh R/W

Programmable one-shot generation

mode 00h to FFh R/W

Programmable wait one-shot

generation mode 00h to FFh R/W

Address 010Dh

Bitb7b6b5b4b3b2b1b0

Symbol————————

After Reset11111111

Bit Mode Function Setting Range R/W

b7 to b0 Timer mode Disabled 00h to FFh —

Programmable wavefo rm generation

mode Counts timer RB prescaler underflows (1) 00h to FFh W (2)

Programmable one-shot generation

mode Disabled 00h to FFh —

Programmable wait one-shot

generation mode Counts time r RB prescaler unde rflows

(one-shot width is counted) 00h to FFh W (2)

R8C/34C Group 18. Timer RB

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 238 of 723

18.2.7 Timer RB Primary Register (TRBPR)

Note:

1. The values of registers TRBPR and TRBSC are reloaded to the counter alterna tely and counted.

When the TSTOP bit in the TRBCR register is set to 1, the TRBPR register is set to FFh.

18.2.8 Timer RB/RC Pin Select Register (TRBRCSR)

The TRBRCSR register selects which pin is assigned to the timer RB and timer RC I/O. To use the I/O pin for

timer RB and timer RC, set this register.

Set the TRBOSEL0 bit before setting the timer RB associated registers. Set bits TRCCLKSEL0 and

TRCCLKSEL1 before setting the timer RC associated registers. Also, do not change the setting values of the

TRBOSEL0 bit during timer RB operation. Do not change the setting values of bits TRCCLKSEL0 and

TRCCLKSEL1 during timer RC operation.

Address 010Eh

Bitb7b6b5b4b3b2b1b0

Symbol————————

After Reset11111111

Bit Mode Function Setting Range R/W

b7 to b0 Timer mode Counts timer RB prescaler underflows 00h to FFh R/W

Programmable wavefo rm generation

mode Counts timer RB prescaler underflows (1) 00h to FFh R/W

Programmable one-shot generation

mode Counts timer RB prescaler underflows

(one-shot width is counted) 00h to FFh R/W

Programmable wait one-shot

generation mode Counts time r RB prescaler unde rflows

(wait period width is counted) 00h to FFh R/W

Address 0181h

Bitb7b6 b5 b4 b3b2b1 b0

Symbol — — TRCCLKSEL1 TRCCLKSEL0 — — — TRBOSEL0

After Reset000 00000

Bit Symbol Bit Name Function R/W

b0 TRBOSEL0 TRBO pin select bit 0: P1_3 assigned

1: P3_1 assigned R/W

b1 — R eserved bit Set to 0. R/W

b2 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b3 —

b4 TRCCLKSEL0 TRCCL K pin select bit b5 b4

0 0: TRCCLK pin not used

0 1: P1_4 assigned

1 0: P3_3 assigned

1 1: Do not set.

R/W

b5 TRCCLKSEL1 R/W

b6 — R eserved bit Set to 0. R/W

b7 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

R8C/34C Group 18. Timer RB

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 239 of 723

18.3 Timer Mode

In timer mode, a count source which is internally generated or timer RA underflows are counted (refer to Table

18.2 Timer Mode Specifications). Registers TRBOCR and TRBSC are not used in timer mode.

18.3.1 Timer RB I/O Control Register (TRBIOC) in Timer Mode

Table 18.2 Timer Mode Specifications

Item Specification

Count sources f1, f2, f8, timer RA underflow

Count operations • Decrement

• When the timer underflows, it reloads the reload register contents before the

count continues (whe n timer RB u nderflows, the contents of timer RB primary

reload register is reloaded ).

Divide ratio 1/(n+1)(m+1)

n: setting value in TRBPRE register, m: setting value in TRBPR register

Count start condition 1 (count starts) is written to the TSTART bit in the TRBCR register.

Count stop conditions • 0 (count stops) is written to the TSTART bit in the TRBCR register.

• 1 (count forcibly stop) is written to the TSTOP bit in the TRBCR register.

Interrupt request

generation timing When timer RB underflows [timer RB interrupt].

TRBO pin function Programmable I/O port

INT0 pin function Programmable I/O port or INT0 interrupt input

Read from timer The coun t value ca n be rea d out by rea ding re gisters TRBPR and TRBPRE.

Write to timer •When registers TRBPRE and TRBPR are written while the count is stopped,

values are written to both the r eload register and counter.

• When re gisters TRBPRE and TRBPR are written to while count operation is in

progress:

If the TWRC bit in the TRBMR register is set to 0, the value is written to both

the reload register and the counter.

If the TWRC bit is set to 1, the value is written to the reload register only.

(Refer to 18.3.2 Timer Write Control during Count Operation.)

Address 010Ah

Bitb7b6b5b4b3b2b1b0

Symbol————INOSEGINOSTGTOCNTTOPL

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 TOPL Timer RB output level select bit Set to 0 in timer mode. R/W

b1 TOCNT Timer RB output switch bit R/W

b2 INOSTG One-shot trigger control bit R/W

b3 INOSEG One-shot trigger polarity select bit R/W

b4 — Nothing is assig ned. If necessary, set to 0. When read, the content is 0. —

b5 —

b6 —

b7 —

R8C/34C Group 18. Timer RB

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 240 of 723

18.3.2 Timer Write Control during Count Operation

Timer RB has a presca ler and a timer (which counts the prescaler underflows ). The prescaler and timer each

consist of a reload register and a counter. In timer mode, the TWRC bit in the TRBMR register can be used to

select whether writing to the prescaler or timer during count operation is performed to both the reload register

and counter or only to the reload regist er.

However, values are transferred from the reload regist er to the count er of the prescal er in synchronizatio n with

the count source. In addition, values are transferred from the reload register to the counter of the timer in

synchronization with prescaler underflows. Therefore, even if the TWRC bit is set for writing to both the reload

addition, if the TWRC bit is set for writing to the reload register only, the synchronization of the writing will be

shifted if the prescaler value changes. Figure 18.2 shows an Operating Example of Timer RB when Counter

Value is Rewritten during Count Operation.

R8C/34C Group 18. Timer RB

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 241 of 723

Figure 18.2 Operating Example of Timer RB when Counter Value is Rewritten during Count

Operation

Count source

Reloads register of

timer RB prescaler

IR bit in TRBIC

Counter of

timer RB prescaler

Reloads register of

timer RB

Counter of t im e r RB

Set 01h to the T R BP R E reg is ter and 25h to

the TRBPR register by a program.

After writing, the reload register is

written with the first count source.

Reloa d with

the second

count source

Reload on

underflow

After writing, the reload register is

written on th e fi rst underflow.

Reload on the second

underflow

The IR bit remains unchang ed until underfl o w

is generate d by a ne w v al ue.

When the TWRC bit is set to 0 (write to reload register and counter)

Count source

Reloads register of

timer RB prescaler

IR bit in TRBIC

Counter of

timer RB prescaler

Reloads register of

timer RB

Counter of timer RB

Set 01h to th e TR B PRE re gi st er and 25h t o

the TRBPR regist er by a program.

After wri ting, the r el oad register i s

written with the first count source.

Reload on

underflow

After writing, the reload register is

writte n on t h e first underflow.

Reload on

underflow

Only the pre scaler values are updated,

extending the durati o n until timer RB underflow.

When the TWRC bit is set to 1 (write to reload register only)

05h 04h 03h 02h 01h 00h 01h 00h 01h 00h06h 01h 00h 01h

03h 00h02h 01h 25h

New value (25h)Previous valu e

New value (01h)Previous value

05h 04h 01h 00h 01h 00h 01h 00h 01h 00h06h

New value (25h)Previous value

03h 24h02h 25h

The above applies under the following conditions.

Both bits TSTART and TCSTF in the TRBCR register are set to 1 (During count).

R8C/34C Group 18. Timer RB

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 242 of 723

18.4 Programmable Waveform Generation Mode

In programmable waveform generation mode, the signal output from the TRBO pin is inverted each time the

counter underflows, while the values in registers TRBPR and TRBSC are counted alternately (refer to Table 18.3

Programmable Waveform Generation Mode Specifications). Counting starts by counting the setting value in the

TRBPR register. The TRBOCR register is unused in this mode.

Figure 18.3 shows an Operating Example of Timer RB in Prog ram mable Waveform Generation Mode.

Notes:

1. Even when counting the secondary period, the TRBPR register may be read.

2. The set values are reflected in the waveform output beginning with the following primary period after writing to

the TRBPR register.

3. The value written to the TOCNT bit is enabled by the following.

• When counting starts.

• When a timer RB interrupt request is generated.

The contents after the TOCNT bit is changed are reflected from the output of the following primary period.

Table 18.3 Programmable Waveform Generation Mode Specifications

Item Specification

Count sources f1, f2, f8, timer RA underflow

Count operations • Decrement

• When the timer underflows, it reloads the contents of the primary reload and secondary

reload registers alternately before the count continues.

Width and period of

output waveform Primary period: (n+1)(m+1)/fi

Secondary period: (n+1)(p+1)/fi

Period: (n+1){(m+1)+(p+1)}/fi

fi: Count source frequency

n: Value set in TRBPRE register m: Value set in TRBPR register

p: Value set in TRBSC register

Count start condition 1 (count start) is written to the TSTA RT bit in the TRBCR register.

Count stop conditions • 0 (count stop) is written to the TSTART bit in the TRBCR register.

• 1 (count forcibly stop) is written to the TSTOP bit in the TRBCR register.

Interrupt req uest

generation timing In half a cycle of the count source, after timer RB underflows during the secondary period

(at the same time as the TRBO output change) [timer RB interrupt]

TRBO pin function Programmable output port or pulse output

INT0 pin function Programmable I/O port or INT0 interrupt input

Read from timer The count value can be read out by reading registers TRBPR and TRBPRE (1).

Write to timer • When registers TRBPRE, TRBSC, and TRBPR are written while the count is stopped,

values are written to both the reload register and counter.

• When registers TRBPRE, TRBSC, and TR BPR are written to during count operation,

values are written to the reload registers only. (2)

Selectable functions • Output le vel select function

The output level during primary and secondary periods is selected by the TOPL bit in the

TRBIOC register.

• TRBO pin output switch function

Timer RB pulse output or P3_1 (P1_3) latch output is selected by the TOCNT bit in the

TRBIOC register. (3)

R8C/34C Group 18. Timer RB

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 243 of 723

18.4.1 Timer RB I/O Control Register (TRBIOC) in Programmable Waveform

Generation Mode

Address 010Ah

Bitb7b6b5b4b3b2b1b0

Symbol————INOSEGINOSTGTOCNTTOPL

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 TOPL Timer RB output level select bit 0: Outputs “H” for primary period

Outputs “L” for secondary period

Outputs “L” when the timer is stopped

1: Outputs “L” for primary period

Outputs “H” for secondary period

Outputs “H” when the timer is stopped

R/W

b1 TOCNT Timer RB output switch bit 0: Outputs timer RB waveform

1: Outputs value in P3_1 (P1_3) port register R/W

b2 INOSTG One-shot trigger control bit Set to 0 in programmable waveform generation

mode. R/W

b3 INOSEG One-shot trigger polarity select bit R/W

b4 — Nothing is assig ned. If necessary, set to 0. When read, the content is 0. —

b5 —

b6 —

b7 —

R8C/34C Group 18. Timer RB

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 244 of 723

18.4.2 Operating Example

Figure 18.3 Operating Example of Timer RB in Programmable Waveform Generation Mode

IR bit in TRBIC

Count source

Timer RB prescaler

underflow signal

Cou nter of timer RB

TRBO pin output

TOPL bit in TRBIO

Set to 1 by program

Set to 0 when interrupt

request is acknowledged,

or set by program.

The above applies under the following conditions.

TSTART bit in TRBCR

01h 00h 02h

Timer RB secondary reloads Timer RB primary reloads

Set to 0 by program

TRBPRE = 01h, TRBPR = 01h, TRBSC = 02h

TRBIOC register TOCNT = 0 (timer RB waveform is output from the TRBO pin)

02h 01h 00h 01h 00h

Primary period Primary periodSecondary period

Waveform

output starts Waveform output inverted Waveform output starts

Initial output is the same level

as during secondary period.

R8C/34C Group 18. Timer RB

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 245 of 723

18.5 Programmable One-shot Generation Mode

In programmable one-shot generation mode, a one-shot pu lse is output from the TRBO pin by a program or an

external t rigger input (in put to the INT0 pin) (refer to Table 18.4 Programmable One-Shot Generation Mode

Specifications). When a trigger is generated, the timer starts operati ng from the p oint on ly once for a gi ven peri od

equal to the set value in the TRBPR register. The TRBSC register is not used in this mode.

Figure 18.4 shows an Operating Example of Programmable One-Shot Generation Mode.

Note:

1. The set value is reflected at the following one-shot pulse after writing to the TRBPR register.

Table 18.4 Programmable One-Shot Generation Mode Specifications

Item Specification

Count sources f1, f2, f8, timer RA underflow

Count operations • Decrement the setting value in the TRBPR register

• When the timer underflows, it reloads the contents of the reload register before

the count completes and th e TOSSTF bit is set to 0 (one-shot stops).

• When the count stops, the timer reloads the contents of the reload register

before it stops.

One-shot pulse

output time (n+1)(m+1)/fi

fi: Count source frequency,

n: Setting value in TRBPRE register, m: Setting value in TRBPR register

Count start conditions • The TSTART bit in the TRBCR register is set to 1 (count starts) an d the ne xt

trigger is generated

• Set the TOSST b i t in the TRBOCR register to 1 (one-shot starts)

• Input trigger to the INT0 pin

Count stop conditions • When reloading completes after timer RB underflows during primary period

• When the TOSSP bit in the TRBOCR register is set to 1 (one-shot stops)

• When th e TSTART bit in the TRBCR register is set to 0 (stops counting)

• When the TSTOP bit in the TRBCR register is set to 1 (forcibly stops counting)

Interrupt request

generation timing In half a cycle of the count source, after the tim er underflows (at the same time as

the TRBO output ends) [timer RB interrupt]

TRBO pin function Pulse output

INT0 pin functions •When the INOSTG bit in the TRBIOC register is set to 0 (INT0 one-shot trigg e r

disabled): programmable I/O port or INT0 interrupt input

• When th e INOSTG bit in the TRBIOC register is set to 1 (INT0 one-shot trigg e r

enabled): external trigger (INT0 interrupt input)

Read from timer The count value can be read out by reading registers TRBPR and TRBPRE.

Write to timer • When registers TRBPRE and TRBPR are written while the count is stopped,

values are written to both the reload register and counter.

• When registers TRBPRE and TRBPR are written during the count, values are

written to the reload register only (the data is transferred to the counter at the

following reload) (1).

Selectable func tion s • Output level select function

The output level of the on e- sh ot pulse waveform is selected by the TO PL bit in

the TRBIOC register.

• One-shot trigger select function

Refer to 18.5.3 One-Shot Trigger Selection.

R8C/34C Group 18. Timer RB

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 246 of 723

18.5.1 Timer RB I/O Control Register (TRBIOC) in Programmable One-Shot

Generation Mode

Note:

1. Refer to 18.5.3 One-Shot Trigger Selection.

Address 010Ah

Bitb7b6b5b4b3b2b1b0

Symbol————INOSEGINOSTGTOCNTTOPL

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 TOPL Timer RB output level select bit 0: Outputs one-shot pulse “H”

Outputs “L” when the timer is stopped

1: Outputs one-shot pulse “L”

Outputs “H” when the timer is stopped

R/W

b1 TOCNT Timer RB output switch bit Set to 0 in programmable one-shot generation

mode. R/W

b2 INOSTG One-shot trigger control bit (1) 0: INT0 pin on e-shot trigger disabled

1: INT0 pin one-shot trigger enabled R/W

b3 INOSEG One-shot trigger polarity select bit (1) 0: Falling edge trigger

1: Rising edge trigger R/W

b4 — Nothing is assig ned. If necessary, set to 0. When read, the content is 0. —

b5 —

b6 —

b7 —

R8C/34C Group 18. Timer RB

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 247 of 723

18.5.2 Operating Example

Figure 18.4 Operating Example of Programmable One-Shot Generation Mode

TOSSTF bit in TRBOCR

INT0 pin input

IR bit in TRBIC

Count source

Timer RB prescaler

underflow signal

Counter of timer RB

TRBIO pin output

TOPL bit in

TRBIOC register

Set to 1 by program

Set to 1 by setting 1 to

TOSST bit in TRBOCR

Set to 0 when interrupt request is

acknowledged, or set by program

The above applies under the following conditions.

TSTART bit in TRBCR

01h 00h 01h 00h 01h

Count starts Ti mer RB primary reloads Count starts Timer RB primary reloads

Set to 0 by program

Waveform output start s Waveform output ends Waveform output starts Waveform output ends

Set to 0 when

counting ends Set to 1 by INT0 pin

input trigger

TRBPRE = 01h, TRBPR = 01h

TRBIOC register TOPL = 0, TOCNT = 0

INOSTG = 1 (INT0 one-shot trigger enabled)

INOSEG = 1 (edge trigger at rising edge)

R8C/34C Group 18. Timer RB

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 248 of 723

18.5.3 One-Shot Trigger Selection

In programmable one-shot generation mode and programmable wait one-shot generation mode, operation starts

when a one-shot trigger is generated while the TCSTF bit in the TRBCR register is set to 1 (count starts).

A one-shot trigger can be generated by either of the following causes:

• 1 is written to the TOSST bit in the TRBOCR register by a program.

• Trigger input from the IN T0 pin.

When a one-shot trigger occurs, the TOSSTF bit in the TRBOCR register is set to 1 (one-shot operation in

progress) after one or two cycles of the count source have elapsed. Then, in programmable one-shot gen erati on

mode, count operation begins and one-shot waveform output starts. (In programmable wait one-shot generation

mode, count operat ion starts for the wait period.) If a one-shot trigger occurs w hile the TOSSTF bit i s set to 1,

no retriggering occurs.

To use trigger input from the INT0 pin, input the trigger after making the following settings:

• Set the PD4_5 bit in the PD4 register to 0 (input port).

• Select the INT0 digital filter with bits INT0F1 and INT0F0 in the INTF register.

• Select both edges or one edge with t he INT0PL bit in INTEN register. If one edge is selected, further select

falling or rising edge with the INOSEG bit in TRBIOC register.

• Set the INT0EN bit in the INTEN register to 1 (enabled).

• After completing the above, set the INOSTG bit in the TRBIOC register to 1 (INT0 pin one-shot trigger

enabled).

Note the following points with regard to generating interrupt requests by trigger input from the INT0 pin.

• Processing to handle the interrupts is required. Refer to 11. Interrupts, for details.

• If one edge is selected, use the POL bit i n the INT0IC register to select falling or rising ed ge. (The INOSEG

bit in the TRBIOC register does not affect INT0 interrupts).

• If a one-shot trigger occurs while the TOSSTF bit is set to 1, timer RB operation is not affected, but the value

of the IR bit in the INT0IC register changes.

R8C/34C Group 18. Timer RB

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 249 of 723

18.6 Programmable Wait One-Shot Generation Mode

In programmable wait one-shot generation mode, a one-shot pulse is output from the TRBO pin by a program or an

external trigger input (input to the INT0 pin) (refer to Table 1 8.5 Prog rammable Wait One-Shot Generation Mode

Specifications). When a trig ger is ge nerated from t hat point, the t imer outputs a pulse onl y once for a g iven length

of time equal to the setti ng value in the TRBSC register after wa iti ng for a given length of time equal to the setting

value in the TRBPR register.

Figure 18.5 shows an Operating Example of Program m able Wait One-Shot Generation Mode.

Note:

1. The set value is reflected at the following one-shot pulse after writing to registers TRBSC and TRBPR.

Table 18.5 Programmable Wait One-Shot Generation Mode Specifications

Item Specification

Count sources f1, f2, f8, timer RA underflow

Count operations • Decrement the timer RB primary setting value.

• When a count of the timer RB primary underflows, the timer reloads the contents of

timer RB secondary before the count continues.

• When a count of the timer RB secondary underflows, the timer reloads the contents

of timer RB primary before the count completes and the TOSSTF bit is set to 0

(one-shot stops).

• When the count stops, the timer reloads the contents of the reload register before it

stops.

Wait time (n+1)(m+1)/fi

fi: Count source frequency

n: Value set in the TRBPRE register, m Value set in the TRBPR register

One-shot pulse output time (n+1)(p+1)/fi

fi: Count source frequency

n: Value set in the TRBPRE register, p: Value set in the TRBSC register

Count start conditions • The TSTART bit in the TRBCR register is set to 1 (count starts) and the next trigger

is generated.

• Set the TOSST bit in the TRBOCR register to 1 (one-shot starts).

• Inpu t trigger to the INT0 pin

Count stop conditions

• When reloading completes after timer RB underflows during secondary period.

• When the TOSSP bit in the TRBOCR register is set to 1 (one-shot stops).

• When the T ST A RT bit in the TRBCR register is set to 0 (starts counting).

• When the TSTOP bi t in the TRBCR register is set to 1 (forcibly stops counting).

Interrupt request generation

timing In half a cycle of the count source after timer RB underflows during secondary period

(complete at the same time as waveform output from the TRBO pin) [timer RB

interrupt].

TRBO pin function Pulse output

INT0 pin functions • When the INOSTG bit in the TRBIOC register is set to 0 (INT0 one-shot trigger

disabled): programmable I/O port or INT0 interrupt input

• When the INOSTG bit in the TR BIOC register is set to 1 (INT0 one-shot trigger

enabled): external trigger (INT0 interrupt input)

Read from timer The count value can be read out by reading registers TRBPR and TRBPRE.

Write to timer • When registers TRBPRE, TRBSC, and TRBPR are written while the count stops,

values are written to both the reload register and counter.

• When reg isters TRBPRE, TRBSC, and TRBPR are written to during count

operation, values are written to the reload registers onl y. (1)

Selectable functions • Output level select function

The output level of the one-shot pulse waveform is selected by the TOPL bit in the

TRBIOC register.

• One-shot trigger select function

Refer to 18.5.3 One-Shot Trigger Selection.

R8C/34C Group 18. Timer RB

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 250 of 723

18.6.1 Timer RB I/O Control Register (TRBIOC) in Programmable Wait One-Shot

Generation Mode

Note:

1. Refer to 18.5.3 One-Shot Trigger Selection.

Address 010Ah

Bitb7b6b5b4b3b2b1b0

Symbol————INOSEGINOSTGTOCNTTOPL

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 TOPL Timer RB output level select bit 0: Outputs one-shot pulse “H”

Outputs “L” when the timer stops or during wait

1: Outputs one-shot pulse “L”

Outputs “H” when the timer stops or during wait

R/W

b1 TOCNT Timer RB output switch bit Set to 0 in programmable wait one-shot generation

mode. R/W

b2 INOSTG One-shot trigger control bit (1) 0: INT0 pin one-shot trigger disabled

1: INT0 pin one-shot trigger enabled R/W

b3 INOSEG One-shot trigger polarity select bit (1) 0: Falling edge trigger

1: Rising edge trigger R/W

b4 — Nothing is assig ned. If necessary, set to 0. When read, the content is 0. —

b5 —

b6 —

b7 —

R8C/34C Group 18. Timer RB

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 251 of 723

18.6.2 Operating Example

Figure 18.5 Operating Example of Programmable Wait One-Shot Generation Mode

TOSSTF bit in TRBOCR

INT0 pi n input

IR bit in TRBIC

Count source

Timer RB prescaler

underflow signal

Counter of timer RB

TRBIO pi n output

TOPL bit in

TRBIOC register

Set to 1 by program

Set to 1 by setting 1 to TOSST bit in TRBOCR

Set to 0 when interrupt request is

acknowledged, or set by program.

The above applies under the following conditions.

TSTART bit in TRBCR

01h 00h 00h 01h

Count starts Timer RB secondary reloads Timer RB primary reloads

Set to 0 by program

Wait starts Waveform output starts Waveform output ends

Set to 0 when

counting ends

TRBPRE = 01h, TRBPR = 01h, TRBSC = 04h

INOSTG = 1 (INT0 one-shot trigger enabled)

INOSEG = 1 (edge trigger at rising edge)

04h 03h 02h 01h

Wait

(primary peri od ) One-shot pulse

(secondary period)

R8C/34C Group 18. Timer RB

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 252 of 723

18.7 Notes on Timer RB

•Timer RB stops counting after a reset. Set the values in the timer RB and timer RB prescalers before the count

starts.

•Even if the prescaler and timer RB is read out in 16-bit units, these registers are read 1 byte at a time by the MCU.

Consequently, the timer value may be updated during the period when these two registers are being read.

•In programmable one-shot generation mode and programm able wait one-shot generation mode , when setting the

TSTART bit in the TRBCR reg ister to 0 (stops counting ) or setting the TOSSP bit in th e TRBOCR register to 1

(stops one-shot), th e timer reloads the value of reload register and stops. Therefore, in programmable one-shot

generation mode and programmable wait one-shot generation mode, read the timer count value before the timer

stops.

•The TCSTF bit remains 0 (count stops) for 1 to 2 cycles of the count source after setting the TSTART bit to 1

(count starts) while the count is stopped.

During this time, do not access registers associated with timer RB (1) other than the TCSTF bit. Timer RB starts

counting at the first valid edge of the coun t source after the TCSTF bit is set to 1 (during count).

The TCSTF bit remains 1 for 1 to 2 cycles of the count source after s etting the TSTART bi t to 0 (count stops)

while the count is in progress. Timer RB counting is stopped when the TCSTF bit is set to 0.

During this time, do not access registers associated with timer RB (1) other than the TCSTF bit.

Note:

1. Registers associated with timer RB: TRBCR, TRBOCR, TRBIOC, TRBMR, TRBPRE, TRBSC, and

TRBPR.

•If the TSTOP bit in the TRBCR register is set to 1 during timer operation, timer RB stops immediately.

•If 1 is written to the TOSST or TOSSP bit in the TRBOCR register, the value of the TOSSTF bit changes after

one or two cycles of the count sou rce have elapsed. If the TOSSP bit is written t o 1 during the period between

when the TOSST bit is written to 1 and when the TOSSTF bit is set to 1, the TOSSTF bit may be set to either 0 or

1 depending on the co ntent state. Likewise, if t he TOSST bit is written to 1 du ring the period between when the

TOSSP bit is written to 1 and when the TOSSTF bit is set to 0, the TOSSTF bit may be set to either 0 or 1.

•To use the underflow signal of timer RA as the count source for timer RB, set timer RA in timer mode, pulse

output mode, or event count mode.

18.7.1 Timer Mode

To write to registers TRBPRE and TRBPR during count operation (TCSTF bit in the TRBCR register is set to

1), note the following points:

•When the TRBPRE register is written continuou sly, allow three or more cycles of the count source for each

write interval.

•When the TRBPR register is written continuously, al low three or more cycles of the prescaler underflow for

each write interval.

18.7.2 Programmable Waveform Generation Mode

To write to registers TRBPRE and TRBPR during count operation (TCSTF bit in the TRBCR register is set to

1), note the following points:

•When the TRBPRE register is written continuou sly, allow three or more cycles of the count source for each

write interval.

•When the TRBPR register is written continuously, al low three or more cycles of the prescaler underflow for

each write interval.

R8C/34C Group 18. Timer RB

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 253 of 723

18.7.3 Programmable One-shot Generation Mode

To write to registers TRBPRE and TRBPR during count operation (TCSTF bit in the TRBCR register is set to

1), note the following points:

•When the TRBPRE register is written continuously during count operation (TCSTF bit is set to 1), allow three

or more cycles of the count source for each write interval.

•When the TRBPR regi ster is written cont inuously durin g count operat ion (TCSTF bit is set to 1), allow t hree

or more cycles of the prescaler underflow for each write interval.

18.7.4 Programmable Wait One-shot Generation Mode

To write to registers TRBPRE and TRBPR during count operation (TCSTF bit in the TRBCR register is set to

1), note the following points:

•When the TRBPRE register is written continuou sly, allow three or more cycles of the count source for each

write interval.

•When the TRBPR register is written continuously, al low three or more cycles of the prescaler underflow for

each write interval.

R8C/34C Group 19. Timer RC

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 254 of 723

19. Timer RC

Timer RC is a 16-bit timer with fo ur I/O pins.

19.1 Overview

Timer RC uses either f1, fOCO40M or fOCO-F as its operation clock. Table 19.1 lists the Timer RC Operation

Clock.

Table 19.2 lists the Pin Configuration of Timer RC, and Figure 19.1 shows a Timer RC Block Diagram.

Timer RC has three modes.

• Timer mode

- Input capture function The counter value is captured to a register, using an ex ternal signal as the trigge r.

- Output compare function Matches between the counter and register values are detected. (Pin output state

changes when a match is detected.)

The following two modes use the output compare function.

• PWM mode Pulses of a given width are output continuously.

• PWM2 mode A one-shot waveform or PWM waveform is output following the trigger afte r the

wait time has elapsed.

Input capture function, output compare function, and PWM mode settings may be specified independently for each

pin.

In PWM2 mode waveforms are output based on a combination of the counter or the regist er.

Table 19.1 Timer RC Operation Clock

Condition Timer RC Operation Clock

Count source is f1, f2, f4, f8, f32, or TRCCLK input (bits TCK2 to TCK0 in

TRCCR1 register are set to a value fr om 000b to 101b) f1

Count source is fOCO40M (bits TCK2 to TCK0 in TRCCR1 register are set

to 110b) fOCO40M

Count source is fOCO-F (bits TCK2 to TCK0 in TRCCR1 register are set to

111b) fOCO-F

R8C/34C Group 19. Timer RC

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 255 of 723

Figure 19.1 Timer RC Block Diagram

Table 19.2 Pin Configuration of Timer RC

Pin Name Assigned Pin I/O Function

TRCIOA P0_0, P0_1, P0_2, or P1_1 I/O Function differs according to th e mode.

Refer to descriptions of individual modes

for details

TRCIOB P0_3, P0_4, P0_5, P1_2, P2_0, or

P6_5

TRCIOC P0_7, P1_3, P2_1, P3_4, or P6 _6

TRCIOD P0_6, P1_0, P2_2, P3_5, or P6 _7

TRCCLK P1_4 or P3_3 Input External clock input

TRCTRG P0_0, P0_1, P0_2, or P1_1 Input PWM2 mode external trigger input

TRCMR register

Data bus

TRCCR1 register

TRCIER register

TRCSR register

TRCIOR0 register

TRC register

TRCGRA register

TRCGRB register

TRCGRC register

TRCGRD register

TRCCR2 register

TRCDF register

TRCOER register

Timer RC con trol circ u it

INT0

TRCCLK

Count source

select circuit

f1, f2 , f 4, f8, f32,

fOCO40M , fOCO - F

Time r RC in te rru p t

request

TRCIOR1 register TRCIOB

TRCIOC

TRCIOD

TRCIOA/TRCTRG

TRCADCR register

R8C/34C Group 19. Timer RC

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 256 of 723

19.2 Registers

Table 19.3 lists the Registers Associated with Timer RC.

−: Invalid

Table 19.3 Registers Associated with Timer RC

Address Symbol

Mode

Related Information

Timer

PWM PWM2

Input

Capture

Function

Output

Compare

Function

0008h MSTCR Valid Valid Valid Valid 19.2.1 Module Standby Control Register (MSTCR)

0120h TRCMR Valid Valid Valid Vali d 19.2.2 Timer RC Mode Registe r (TR CMR)

0121h TRCCR1 Valid Valid Valid Valid Timer RC control register 1

19.2.3 Timer RC Control Register 1 (TRCCR1)

19.5.1 Timer RC Control Register 1 (TRCCR1) for

Output Compare Function

19.6.1 Timer RC Control Register 1 (TRCCR1) in

PWM Mode

19.7.1 Timer RC Control Register 1 (TRCCR1) in

PWM2 Mode

0122h TRCIER Valid Valid Valid Valid 19 .2 .4 Timer RC Interrupt Enable Register (TRCIER)

0123h TRCSR Valid Valid Valid Valid 19.2.5 Timer RC Status Register (TRCSR)

0124h

TRCIOR0

Valid Valid −−Timer RC I/O control register 0, timer RC I/O control

19.2.6 Timer RC I/O Control Register 0 (TRCIOR0)

19.2.7 Timer RC I/O Control Register 1 (TRCIOR1)

19.4.1 Timer RC I/O Control Register 0 (TRCIOR0)

for Input Capture Function

19.4.2 Timer RC I/O Control Register 1 (TRCIOR1)

for Input Capture Function

19.5.2 Timer RC I/O Control Register 0 (TRCIOR0)

for Output Compare Function

19.5.3 Timer RC I/O Control Register 1 (TRCIOR1)

for Output Compare Function

0125h

TRCIOR1

0126h

0127h TRC Valid Valid Valid Valid 19.2.8 Timer RC Counter (TRC )

0128h

0129h TRCGRA Valid Valid Valid Valid 19.2.9 Timer RC General Registers A, B, C, and D

(TRCGRA, TRCGRB, TRCGRC, TRCGRD)

012Ah

012Bh TRCGRB

012Ch

012Dh TRCGRC

012Eh

012Fh TRCGRD

0130h TRCCR2 −Valid Valid Valid 19.2.10 Timer RC Control Register 2 (TRCCR2)

0131h TRCDF Valid −−Valid 19.2.11 Timer RC Digita l Filter Function Select

0132h TRCOER −Valid Valid Valid 19.2.12 Timer RC Ou tput Master Enable Register

(TRCOER)

0133h

TRCADCR

−Valid Valid Valid 19 .2 .13 Timer RC Trigger Control Register

(TRCADCR)

0181h

TRBRCSR

Valid Valid Valid Valid 19.2.14 Timer RB/RC Pin Select Register

(TRBRCSR)

0182h

TRCPSR0

Valid Valid Valid Valid 19.2.15 Timer RC Pin Select Register 0 (TRCPSR0)

0183h

TRCPSR1

Valid Valid Valid Valid 19.2.16 Timer RC Pin Select Register 1 (TRCPSR1)

R8C/34C Group 19. Timer RC

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 257 of 723

19.2.1 Module Standby Control Register (MSTCR)

Notes:

1. When the MSTIIC bit is set to 1 (standby), any access to the SSU or the I2C bus associated registers (addresses

0193h to 019Dh) is disabled.

2. When the MSTTRD bi t is set to 1 (stand by), any acce ss to the ti mer RD associated regi sters (addresse s 0135h

to 015Fh) is disabled.

3. To set the MSTTRD bit to 1 (standby), set bits TCK2 to TCK0 in the TRDCRi (i = 0 or 1) register to 000b (f1).

4. When the MSTTRC bi t is set to 1 (stand by), any acce ss to the time r RC associated registers (addresses 0120h

to 0133h) is disabled.

19.2.2 Timer RC Mode Register (TRCMR)

Notes:

1. These bits are enabled when the PWM2 bit is set to 1 (timer mode or PWM mode).

2. Set the BFC bit to 0 (genera l register) in PWM2 mode.

For notes on PWM2 mode, refer to 19.9.6 TRCMR Register in PWM2 Mode.

Address 0008h

Bitb7b6b5b4b3b2b1b0

Symbol — — MSTTRC MSTTRD MSTIIC — — —

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b1 —

b2 —

b3 MSTIIC SSU, I2C bus standby bit 0: Active

1: Standby (1) R/W

b4 MSTTRD Timer RD standby bit 0: Active

1: Standby (2, 3) R/W

b5 MSTTRC Timer RC standby bit 0: Active

1: Standby (4) R/W

b6 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b7 —

Address 0120h

Bitb7b6b5b4b3b2b1b0

Symbol TSTART — BFD BFC PWM2 PWMD PWMC PWMB

After Reset01001000

Bit Symbol Bit Name Function R/W

b0 PWMB PWM mode of TRCIOB select bit (1) 0: Timer mode

1: PWM mode R/W

b1 PWMC PWM mode of TRCIOC select bit (1) 0: Timer mode

1: PWM mode R/W

b2 PWMD PWM mode of TRCIOD select bit (1) 0: Timer mode

1: PWM mode R/W

b3 PWM2 PWM2 mode select bit 0: PWM 2 mode

1: Timer mode or PWM mode R/W

b4 BFC TRCGRC register function select bit (2) 0: Genera l register

1: Buffer register of TRCGRA register R/W

b5 BFD TRCGRD register fu nction select bit 0: General register

1: Buffer register of TRCGRB register R/W

b6 — Nothing is assig ned. If necessary, set to 0. When read, the content is 1. —

b7 TSTART TRC count star t bit 0: Count stops

1: Count starts R/W

R8C/34C Group 19. Timer RC

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 258 of 723

19.2.3 Timer RC Control Register 1 (TRCCR1)

Notes:

1. Set to these bits when the TSTART bit in t he TRCMR register is set to 0 (count stops).

2. To select fOCO-F, set it to the clock frequency higher than the CPU clock frequency.

19.2.4 Timer RC Interrupt Enable Register (TRCIER)

Address 0121h

Bitb7b6b5b4b3b2b1b0

Symbol CCLR TCK2 TCK1 TCK0 TOD TOC TOB TOA

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 TOA TRCIOA output level select bit (1) Function varies according to the operating mode

(function). R/W

b1 TOB TRCIOB output level select bit (1) R/W

b2 TOC TRCIOC output level select bit (1) R/W

b3 TOD TRCIOD output level select bit (1) R/W

b4 TCK0 Count source select bit (1) b6 b5 b4

0 0 0: f1

0 0 1: f2

0 1 0: f4

0 1 1: f8

1 0 0: f32

1 0 1: TRCCLK input rising edge

1 1 0: fOCO40M

1 1 1: fOCO-F (2)

R/W

b5 TCK1 R/W

b6 TCK2 R/W

b7 CCLR TRC counter clear select bit 0: Disable clear (free-running operation)

1: Clear TRC counter by input capture or by compare

match in TRCGRA

R/W

Address 0122h

Bitb7b6b5b4b3b2b1b0

Symbol OVIE — — — IMIED IMIEC IMIEB IMIEA

After Reset01110000

Bit Symbol Bit Name Function R/W

b0 IMIEA Input capture / compare match interrupt

enable bit A 0: Disable interrupt (IMIA) by the IMFA bit

1: Enable interrupt (IMIA) by the IMFA bit R/W

b1 IMIEB Input capture / compare match interrupt

enable bit B 0: Disable interrupt (IMIB) by the IMFB bit

1: Enable interrupt (IMIB) by the IMFB bit R/W

b2 IMIEC Inp ut capture / compare match interrupt

enable bit C 0: Disable interrupt (IMIC) by the IMFC bit

1: Enable interrupt (IMIC) by the IMFC bit R/W

b3 IMIED Inp ut capture / compare match interrupt

enable bit D 0: Disable interrupt (IMID) by the IMFD bit

1: Enable interrupt (IMID) by the IMFD bit R/W

b4 — Nothing is assig ned. If necessary, set to 0. When read, the content is 1. —

b5 —

b6 —

b7 OVIE Overflow interrupt enable bit 0: Disable interrupt (OVI) by the OVF bit

1: Enable interrupt (OVI) by the OVF bit R/W

R8C/34C Group 19. Timer RC

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 259 of 723

19.2.5 Timer RC Status Register (TRCSR)

Note:

1. The writing results are as follows:

•This bit is set to 0 when the read result is 1 and 0 is written to the same bit.

•This bit remains uncha nged even if the read result is 0 and 0 is written to the same bit. (This bit remains 1 even

if it is set to 1 from 0 after reading, and writing 0.)

•This bit remains unchanged if 1 is written to it.

Notes:

1. Edge selected by bits IOj1 to IOj0 (j = A, B, C, or D).

2. Includes the condition that bits BFC and BFD are set to 1 (buffer registers of registers TRCGRA and TRCGRB).

Address 0123h

Bitb7b6b5b4b3b2b1b0

Symbol OVF — — — IMFD IMFC IMFB IMFA

After Reset01110000

Bit Symbol Bit Name Function R/W

b0 IMFA Input capture / compare match flag A [Source for setting this bit to 0]

Write 0 after read (1).

[Source for setting thi s bit to 1]

Refer to Table 19.4 Sou rce for Setting Bit of

Each Flag to 1.

R/W

b1 IMFB Input capture / compare match flag B R/W

b2 IMFC Input capture / compare match flag C R/W

b3 IMFD Input capture / compare match flag D R/W

b4 — Nothing is assig ned. If necessary, set to 0. When read, the content is 1. —

b5 —

b6 —

b7 OVF Overflow flag [Source for setting this bit to 0]

Write 0 after read (1).

[Source for setting thi s bit to 1]

Refer to Table 19.4 Sou rce for Setting Bit of

Each Flag to 1.

R/W

Table 19.4 Source for Setting Bit of Each Flag to 1

Bit Symbol Timer Mode PWM Mode PWM2 Mode

Input capture Function Output Compare Function

IMFA TRCIOA pin input edge (1) When the values of the registers TRC and TRCGRA match.

IMFB TRCIOB pin input edge (1) When the values of the registers TRC and TRCGRB match.

IMFC TRCIOC pin input edge (1) When the values of the registers TRC and TRCGRC ma tch. (2)

IMFD TRCIOD pin input edge (1) When the values of the registers TRC and TRCGRD ma tch. (2)

OVF When the TRC register overflows.

R8C/34C Group 19. Timer RC

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 260 of 723

19.2.6 Timer RC I/O Control Register 0 (TRCIOR0)

Notes:

1. When the BFC bit in the TRCMR register is set to 1 (buffer register of TRCGRA register), set the IOC2 bit in the

TRCIOR1 register to the same value as the IOA2 bit in the TRCIOR0 register.

2. When the BFD bit in the TRCMR register is set to 1 (buffer register of TRCGRB register), set the IOD2 bit in the

TRCIOR1 register to the same value as the IOB2 bit in the TRCIOR0 register.

3. The IOA 3 bi t i s ena b l ed wh e n th e IOA2 bit is set to 1 (input capture function).

The TRCIOR0 register is enabled in timer mode. It is disabled in modes PWM and PWM2.

19.2.7 Timer RC I/O Control Register 1 (TRCIOR1)

Notes:

1. When the BFC bit in the TRCMR register is set to 1 (buffer register of TRCGRA register), set the IOC2 bit in the

TRCIOR1 register to the same value as the IOA2 bit in the TRCIOR0 register.

2. When the BFD bit in the TRCMR register is set to 1 (buffer register of TRCGRB register), set the IOD2 bit in the

TRCIOR1 register to the same value as the IOB2 bit in the TRCIOR0 register.

The TRCIOR1 register is enabled in timer mode. It is disabled in modes PWM and PWM2.

Address 0124h

Bitb7b6b5b4b3b2b1b0

Symbol— IOB2IOB1IOB0IOA3IOA2IOA1IOA0

After Reset10001000

Bit Symbol Bit Name Function R/W

b0 IOA0 TRCGRA control bit Function varies according to the operating mode

(function). R/W

b1 IOA1 R/W

b2 IOA2 TRCGRA mode select bit (1) 0: Output compare function

1: Input capture function R/W

b3 IOA3 TRCGRA input capture input switch

bit (3) 0: fOCO128 signal

1: TRCIOA pin input R/W

b4 IOB0 TRCGRB control bit Function varies according to the operating mode

(function). R/W

b5 IOB1 R/W

b6 IOB2 TRCGRB mode select bit (2) 0: Output compare function

1: Input capture function R/W

b7 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. —

Address 0125h

Bitb7b6b5b4b3b2b1b0

Symbol IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0

After Reset10001000

Bit Symbol Bit Name Function R/W

b0 IOC0 TRCGRC control bit Function varies according to the operating mode

(function). R/W

b1 IOC1 R/W

b2 IOC2 TRCGRC mode select bit (1) 0: Output compare function

1: Input capture function R/W

b3 IOC3 TRCGRC register function select bit 0: TRCIOA output register

1: General register or buffer register R/W

b4 IOD0 TRCGRD control bit Function varies according to the operating mode

(function). R/W

b5 IOD1 R/W

b6 IOD2 TRCGRD mode select bit (2) 0: Output compare function

1: Input capture function R/W

b7 IOD3 TRCGRD register function select bit 0: TRCIOB output register

1: General register or buffer register R/W

R8C/34C Group 19. Timer RC

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 261 of 723

19.2.8 Timer RC Counter (TRC)

Access the TRC register in 16-bit units. Do not access it in 8-bit units.

19.2.9 Timer RC General Registers A, B, C, and D (TRCGRA, TRCGRB, TRCGRC,

TRCGRD)

Access registers TRCGRA to TRCGRD in 16-bit units. Do not access them in 8-bit units.

Address 0127h to 0126h

Bitb7b6b5b4b3b2b1b0

Symbol————————

After Reset00000000

Bit b15 b14 b13 b12 b11 b10 b9 b8

Symbol————————

After Reset00000000

Bit Function Setting Range R/W

b15 to b0 Count a count source. Cou nt operation is incremented.

When an overflow occurs, the OVF bit in the TRCSR register is set to 1. 0000h to FFFFh R/W

Address 0129h to 0128h (TRCGRA), 012Bh to 012Ah (TRCGRB), 012Dh to 012Ch (TRCGRC),

012Fh to 012Eh (TRCGRD)

Bitb7b6b5b4b3b2b1b0

Symbol————————

After Reset11111111

Bit b15 b14 b13 b12 b11 b10 b9 b8

Symbol————————

After Reset11111111

Bit Function R/W

b15 to b0 Function varies according to the operating mode. R/W

R8C/34C Group 19. Timer RC

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 262 of 723

19.2.10 Timer RC Control Register 2 (TRCCR2)

Notes:

1. Enabled when in PWM mode.

2. Enabled when in output compare function, PWM mode, or PWM2 mode. For notes on PWM2 mode, refer to

19.9.6 TRCMR Register in PWM2 Mode.

3. Enabled when in PWM2 mode.

19.2.11 Timer RC Digital Filter Function Select Register (TRCDF)

Notes:

1. These bits are enabled for the input capture function.

2. These bits are enabled when in PWM2 mode and bits TCEG1 to TCEG0 in the TRCCR2 register are set to 01b,

10b, or 11b (TRCTRG trigger input enabled).

Address 0130h

Bitb7b6b5b4b3b2b1b0

Symbol TCEG1 TCEG0 CSEL — — POLD POLC POLB

After Reset00011000

Bit Symbol Bit Name Function R/W

b0 POLB PWM mode output level control

bit B (1) 0: TRCIOB output level selected as “L” active

1: TRCIOB output level selected as “H” active R/W

b1 POLC PWM mode output level control

bit C (1) 0: TRCIOC output level selected as “L” active

1: TRCIOC output level selected as “H” active R/W

b2 POLD PWM mode output level control

bit D (1) 0: TRCIOD output level selected as “L” active

1: TRCIOD output level selected as “H” active R/W

b3 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. —

b4 —

b5 CSEL TRC count operation select bit (2) 0: Count continues at compare match with the

TRCGRA register

1: Count stops at compare match with the TRCGRA

R/W

b6 TCEG0 TRCTRG input edge select bit (3) b7 b6

0 0: Disable the trigger input from the TRCTRG pin

0 1: Rising edge selected

1 0: Falling edge selected

1 1: Both edges selected

R/W

b7 TCEG1 R/W

Address 0131h

Bitb7b6b5b4b3b2b1b0

Symbol DFCK1 DFCK0 — DFTRG DFD DFC DFB DFA

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 DFA TRCIOA pin digital filter function select bit (1) 0: Function is not used

1: Function is used R/W

b1 DFB TRCIOB pin digital filter function select bit (1) R/W

b2 DFC TRCIOC pin digital filter function select bit (1) R/W

b3 DFD TRCIOD pin digital filter function select bit (1) R/W

b4 DFTRG TRCTRG pin digital filter function select bit (2) R/W

b5 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b6 DFCK0 Clock select bits for digital filter function (1, 2) b7 b6

0 0: f32

0 1: f8

1 0: f1

1 1: Count source (clock selected by bits

TCK2 to TCK0 in the TRCCR1

R/W

b7 DFCK1 R/W

R8C/34C Group 19. Timer RC

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 263 of 723

19.2.12 Timer RC Output Master Enable Register (TRCOER)

Note:

1. These bits are disabled for input pins set to the input capture function.

19.2.13 Timer RC Trigger Control Register (TRCADCR)

Address 0132h

Bitb7b6b5b4b3b2b1b0

Symbol PTO — — — ED EC EB EA

After Reset01111111

Bit Symbol Bit Name Function R/W

b0 EA TRCIOA output disable bit (1) 0: Enable output

1: Disable output (The TRCIOA pin is used as a

programmable I/O port.)

R/W

b1 EB TRCIOB output disable bit (1) 0: Enable output

1: Disable output (The TRCIOB pin is used as a

programmable I/O port.)

R/W

b2 EC TRCIOC output disable bit (1) 0: Enable output

1: Disable output (The TRCIOC pin is used as a

programmable I/O port.)

R/W

b3 ED TRCIOD output disable bit (1) 0: Enable output

1: Disable output (The TRCIOD pin is used as a

programmable I/O port.)

R/W

b4 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. —

b5 —

b6 —

b7 PTO INT0 of pulse output forced cutoff

signal input enabled bit 0: Pulse output forced cutoff input disabled

1: Pulse output forced cutoff input enabled

(Bits EA, EB, EC, and ED are set to 1 (disable

output) when “L” is applied to the INT0 pin)

R/W

Address 0133h

Bitb7b6b5b4 b3 b2 b1 b0

Symbol — — — — ADTRGDE ADTRGCE ADTRGBE ADTRGAE

After Reset0000 0 0 0 0

Bit Symbol Bit Name Function R/W

b0 ADTRGAE A/D trigger A enable bit 0: A/D trigger disabled

1: A/D trigger generated at compare match with

registers TRC and TRCGRA

R/W

b1 ADTRGBE A/D trigger B enable bit 0: A/D trigger disabled

1: A/D trigger generated at compare match with

registers TRC and TRCGRB

R/W

b2 ADTRGCE A /D trigger C enab le bit 0: A/D trigger disabled

1: A/D trigger generated at compare match with

registers TRC and TRCGRC

R/W

b3 ADTRGDE A /D trigger D enab le bit 0: A/D trigger disabled

1: A/D trigger generated at compare match with

registers TRC and TRCGRD

R/W

b4 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b5 —

b6 —

b7 —

R8C/34C Group 19. Timer RC

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 264 of 723

19.2.14 Timer RB/RC Pin Select Register (TRBRCSR)

The TRBRCSR register selects which pin is assigned to the timer RB and timer RC I/O. To use the I/O pin for

timer RB and timer RC, set this register.

Set the TRBOSEL0 bit before setting the timer RB associated registers. Set bits TRCCLKSEL0 and

TRCCLKSEL1 before setting the timer RC associated registers. Also, do not change the setting values of the

TRBOSEL0 bit during timer RB operation. Do not change the setting values of bits TRCCLKSEL0 and

TRCCLKSEL1 during timer RC operation.

Address 0181h

Bitb7b6 b5 b4 b3b2b1 b0

Symbol — — TRCCLKSEL1 TRCCLKSEL0 — — — TRBOSEL0

After Reset000 00000

Bit Symbol Bit Name Function R/W

b0 TRBOSEL0 TRBO pin select bit 0: P1_3 assigned

1: P3_1 assigned R/W

b1 — R eserved bit Set to 0. R/W

b2 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b3 —

b4 TRCCLKSEL0 TRCCL K pin select bit b5 b4

0 0: TRCCLK pin not used

0 1: P1_4 assigned

1 0: P3_3 assigned

1 1: Do not set.

R/W

b5 TRCCLKSEL1 R/W

b6 — R eserved bit Set to 0. R/W

b7 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

R8C/34C Group 19. Timer RC

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 265 of 723

19.2.15 Timer RC Pin Select Register 0 (TRCPSR0)

The TRCPSR0 register selects which pin is assigned to the timer RC I/O. To use the I/O pin for timer RC, set

this register.

Set the TRCPSR0 register before setting the timer RC associated registers. Also, do not change the setting value

in this register during timer RC operation.

Address 0182h

Bitb7b6 b5 b4b3b2 b1 b0

Symbol —

TRCIOBSEL2 TRCIOBSEL1 TRCIOBSEL0 — TRCIOASEL2 TRCIOASEL1 TRCIOASEL0

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 TRCIOASEL0 TRCIOA/TRCTRG pin select bit b2 b1 b0

0 0 0: TRCIOA/TRCTRG pin not used

0 0 1: P1_1 assigned

0 1 0: P0_0 assigned

0 1 1: P0_1 assigned

1 0 0: P0_2 assigned

Other than above: Do not set.

R/W

b1 TRCIOASEL1 R/W

b2 TRCIOASEL2 R/W

b3 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b4 TRCIOBSEL0 TRCIOB pin select bit b6 b5 b4

0 0 0: TRCIOB pin not used

0 0 1: P1_2 assigned

0 1 0: P0_3 assigned

0 1 1: P0_4 assigned

1 0 0: P0_5 assigned

1 0 1: P2_0 assigned

1 1 0: P6_5 assigned

Other than above: Do not set.

R/W

b5 TRCIOBSEL1 R/W

b6 TRCIOBSEL2 R/W

b7 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

R8C/34C Group 19. Timer RC

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 266 of 723

19.2.16 Timer RC Pin Select Register 1 (TRCPSR1)

The TRCPSR1 register selects which pin is assigned to the timer RC I/O. To use the I/O pin for timer RC, set

this register.

Set the TRCPSR1 register before setting the timer RC associated registers. Also, do not change the setting value

in this register during timer RC operation.

Address 0183h

Bitb7b6 b5 b4b3b2 b1 b0

Symbol

— TRCIODSEL2 TRCIODSEL1 TRCIODSEL0 — TRCIOCSEL2 TRCIOCSEL1 TRCIOCSEL0

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 TRCIOCSEL0 TRCIOC pin select bit b2 b1 b0

0 0 0: TRCIOC pin not used

0 0 1: P1_3 assigned

0 1 0: P3_4 assigned

0 1 1: P0_7 assigned

1 0 0: P2_1 assigned

1 0 1: P6_6 assigned

Other than above: Do not set.

R/W

b1 TRCIOCSEL1 R/W

b2 TRCIOCSEL2 R/W

b3 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b4 TRCIODSEL0 TRCIOD pin select bit b6 b5 b4

0 0 0: TRCIOD pin not used

0 0 1: P1_0 assigned

0 1 0: P3_5 assigned

0 1 1: P0_6 assigned

1 0 0: P2_2 assigned

1 0 1: P6_7 assigned

Other than above: Do not set.

R/W

b5 TRCIODSEL1 R/W

b6 TRCIODSEL2 R/W

b7 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

R8C/34C Group 19. Timer RC

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 267 of 723

19.3 Common Items for Multiple Modes

19.3.1 Count Source

The method of selecting the count source is common to all modes.

Table 19.5 lists the Count Source Selection, and Figure 19.2 shows a Count Source Block Diagram.

Figure 19.2 Count Source Block Diagram

The pulse width of the external clock input to the TRCCLK pin should be three cycles or more of the timer RC

operation clock (refer to Table 19.1 Timer RC Operation Clock).

To select fOCO40M or fOCO-F as the count source, set the FRA00 bit in the FRA0 register set to 1 (high-speed

on-chip oscillator on), and then set bits TCK2 to TCK0 in the TRCCR1 register to 110b (fOCO40M) or 111b

(fOCO-F).

Table 19.5 Count Source Selection

Count Source Selection Method

f1, f2, f4, f8, f32 Count source selected using bits TCK2 to TCK0 in TRCCR1 register

fOCO40M

fOCO-F FRA00 bit in FRA0 register set to 1 (high-speed on-chip oscillator on)

Bits TCK2 to TCK0 in TRCCR1 register are set to 110b (fOCO40M)

Bits TCK2 to TCK0 in TRCCR1 register are set to 111b (fOCO-F)

External signal input

to TRCCLK pin Bits TCK2 to TCK0 in TRCCR1 register are set to 101b (count source is rising edge

of external clock) and the corresponding dire ction bit in the corresponding dire ction

TCK2 to TCK0

TRC regist e r

TCK2 to TCK0: Bits in TRCCR1 register

f32

= 001b

= 010b

= 011b

= 000b

= 110b

= 100b

Count source

TRCCLK = 101b

fOCO40M

= 111b

fOCO-F

R8C/34C Group 19. Timer RC

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 268 of 723

19.3.2 Buffer Operation

Bits BFC and BFD in the TRCM R register are used to select the TR CGRC or TRCGRD register as the buffer

• Buffer register for TRCGRA register: TRCGRC register

• Buffer register for TRCGRB register: TRCGRD register

Buffer operation differs depending on the mod e.

Table 19.6 lists the Buffer Operation in Each Mode, Figure 19.3 shows the Buffer Operation for Input Capture

Function, and Figure 19.4 shows the Buffer Op erati on for Output Compare Function.

Figure 19.3 Buffer Operation for Input Capture Function

Table 19.6 Buffer Operation in Each Mode

Function, Mode Transfer Timing Transfer Destination Register

Input capture function Input capture signal input Contents of TRCGRA (TRCG RB)

Output compare function Compare match between TRC

Contents of buffer register are

transferre d to TRCGRA (TRCGRB)

PWM mode

PWM2 mode • Compare match between TRC

• TRCTRG pin trigger input

Contents of buffer register (TRCGRD)

are transferred to TRCGRB register

Transfer

n-1 n+1

TRCIOA input

TRC register

The above applies under the following conditions:

• The BFC bit in the TRCMR register is set to 1 (the TRCGRC register functions as the buffer register for the TRCGRA register).

• Bits IOA2 to IOA0 in the TRCIOR0 register are set to 100b (input capture at the rising edge).

Transfer

TRCGRC

TRCIOA input

(input capture signal)

TRCGRA reg i ster

TRCGRC register

(buffer)

R8C/34C Group 19. Timer RC

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 269 of 723

Figure 19.4 Buffer Operation for Output Compare Function

Make the following settings in timer mod e .

• To use the TRCGRC register as the buffer register for the TRCGRA register:

Set the IOC2 bit in the TRCIOR1 register to the same value as the IOA2 bit in the TRCIOR0 register.

• To use the TRCGRD register as the buffer register for the TRCGRB register:

Set the IOD2 bit in the TRCIOR1 register to the same value as the IOB2 bit in the TRCIOR0 register.

The output compare function, PWM mode, or PWM2 mode, and the TRCGRC or TRCGRD register is

functionin g as a buffer register, the IMFC b it or IMFD bit in the TRCSR re gister is set to 1 when a compare

match with the TRC register occurs.

The input capture function and the TRCGRC register or TRCGRD register is functioning as a buffer register,

the IMFC bit or IMFD bit in the TRCSR register is set to 1 at the input edge of a signal input to the TRCIOC pin

or TRCIOD pin.

mnTRCGRA register

m-1 m+1

TRC register

The above applies under the following conditions:

• The BFC bit in the TRCMR register is set to 1 (the TRCGRC register functions as the buffer register for the TRCGRA register).

• Bits IOA2 to IOA0 in the TRCIOR0 register are set to 001b (“L” output by compare match).

Transfer

TRCGRC register

(buffer)

TRCIOA output

TRCGRC

Compare match s ignal

R8C/34C Group 19. Timer RC

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 270 of 723

19.3.3 Digital Filter

The input to TRCTRG or TRCIOj (j = A, B, C, or D) is sampled, and the level is considered to be determined

when three matches occur. The digital filter function and sampling clock are selected using the TRCDF register.

Figure 19.5 shows a Digital Filter Block Diagram.

Figure 19.5 Digital Filter Block Diagram

Latch

Match detect

circuit Edge detect

circuit

DFj (or DFTRG)

Sampling clock

IOA2 to IOA0

IOB2 to IOB0

IOC2 to IOC0

IOD2 to IOD0

(or TCEG1 to TCEG0)

DFCK1 to DFCK0

TRCIOj input signal

(or TRCTRG input

signal)

Clock cycle selected by

TCK2 to TCK0

(or DFCK1 to DFCK0)

Sampling clock

TRCIOj in put signal

(or TRCTRG input signal)

Input signa l after passing

through digital filter

If fewer than three matches occur,

the matches are tr eated as noise

and no transmissi on is performed.

Maximum signal transmission

delay is five sampli ng clock

pulses.

Three matches occur and a

signal change is confi r m ed.

f32

j = A, B, C, or D

TCK0 to TCK2: Bit s in TRCCR1 register

DFTRG, DFC K0 t o DFCK1, DFj: Bits in T RCDF register

IOA0 to IOA2, IOB0 to IOB2: Bits in TRCIOR0 register

IOC0 to IOC2, IOD0 to IOD2: Bits in TRCIOR1 register

TCEG1 to TCEG0: Bits in TRCCR2 register

Latch

Timer RC operation clock

f1 or fOCO40M

Count source

= 00b

= 01b

= 10b

= 11b

TCK2 to TCK0

= 001b

= 010b

= 011b

= 000b

= 100b

= 101b

f32

TRCCLK

fOCO40M = 110b

fOCO-F = 111b

R8C/34C Group 19. Timer RC

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 271 of 723

19.3.4 Forced Cutoff of Pulse Output

When using the timer mode’s output compare function, the PWM mode, or the PWM2 mode, pulse output from

the TRCIOj (j = A, B, C, or D) output pin can be forcibly cut off and the TRCIOj pin set to function as a

programmable I/O port by means of input to the INT0 pin.

A pin used for output by the timer mode’s output compare function, the PWM mode, or the PWM2 mode can be

set to function as the timer RC output pin by setting the Ej bit in the TRCOER register to 0 (timer RC output

enabled). If “L” is input to the INT0 pin while the PTO bit in the TRCOER register is set to 1 (pulse output

forced cuto ff signal input IN T0 enabled), bits EA, EB, EC, and ED in the TRCOER register are all set to 1

(timer RC output disabled, TRCIOj outp ut pin functions as the programmable I/O port). When one or two

cycles of the timer RC operation clock after “L” input to the INT0 pin (refer to Table 19.1 Timer RC

Operation Clock) has elapsed, the TRCIOj output pin becomes a programmable I/O port.

Make the following settings to use this function:

• Set the pin state following forced cutoff of pulse output (high impedance (input), “L” output, or “H” output).

(Refer to 7. I/O Ports.)

• Set the INT0EN bit in the INTEN register to 1 (INT0 inpu t enab led) and th e INT0 PL b it to 0 (one edge), and

set the POL bit in the INT0IC register to 0 (falling edge selected).

• Set the PD4_5 bit in the PD4 register to 0 (input mode).

• Select the INT0 digital filter by bits INT0F1 to INT0F0 in the INTF register.

• Set the PTO bit in the TRCOER register to 1 (pulse output forced cutoff signal inpu t INT0 enabled).

The IR bit in the INT0IC register is set to 1 (interrupt request) in accordance with the setting of the POL bit in

the INT0IC register and the INT0PL bit in the INTEN register and a change in the INT0 pin input (refer to 11.8

Notes on Int er r upts).

For details on interrupts, refer to 11. Interrupts.

R8C/34C Group 19. Timer RC

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 272 of 723

Figure 19.6 Forced Cutoff of Pulse Output

INT0 input TRCIOA

PTO bit

EA bit

write value

TRCIOB

EB bit

write value

TRCIOC

EC bit

write value

TRCIOD

ED bit

write value

EA, EB, EC, ED, PTO: Bits in TRCOER register

Timer RC

output data

Port P1_1

output data

Port P1_1

input data

Timer RC

output data

Port P1_2

output data

Port P1_2

input data

Timer RC

output data

Port P3_4

output data

Port P3_4

input data

Timer RC

output data

Port P3_5

output data

Port P3_5

input data

R8C/34C Group 19. Timer RC

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 273 of 723

19.4 Timer Mode (Input Capture Function)

This function measures the width or period of an external signal. An external signal input to the TRCIOj (j = A, B,

C, or D) pin acts as a trigger for tr ansferring the contents of the TRC register (counter) to the TRCGRj register

(input capture). The input capture function, or any other mode or function, can be selected for each individual pin.

The TRCGRA register can also select fOCO128 signal as input-capture trigger input.

Table 19.7 lists the Specifications of Input Capture Function, Figure 19.7 shows a Block Diagram of Input Capture

Function, Table 19.8 lists the Functions of TRCGRj Register when Using In put Capture Fu nction, and Figure 19.8

shows an Operating Example of Input Capture Function.

j = A, B, C, or D

Table 19.7 Specifications of Input Capture Function

Item Specification

Count source f1, f2, f4, f8, f32, fOCO40M, fOCO-F

External signal (rising edge) input to TRCCLK pin

Count operation Increment

Count period •

The CCLR bit in the TRCCR1 regis ter is set to 0 (free running operation):

1/fk × 65,536

fk: Count source frequency

• The CCLR bit in the TRCCR1 register is set to 1 (TRC register set to

0000h at TRCGRA compare match):

1/fk × (n + 1)

n: TRCGRA register setting value

Count start condition 1 (count starts) is written to the TSTART bit in the TRCMR register.

Count stop conditio n 0 (count stops) is written to the TSTA R T bit in the TRCM R re gist er .

The TRC register retains a value before count stops.

Interrupt request generation

timing • Input capture (valid edge of TRCIOj input or fOCO128 signal edge)

• The TRC register overflows.

TRCIOA, TRCIO B , TR CIO C ,

and TRCIOD pin functions Programmable I/O port or input capture input (selectable individually for

each pin)

INT0 pin function Programmable I/O port or INT0 interrupt input

Read from timer The count value can be read by reading TRC register.

Write to timer The TRC register can be written to.

Selectable functions • Input capture input pin selection

One or more of pins TRCIOA, TRCIOB, TRCIOC, and TRCIOD

• Input capture input valid edge selection

Rising edge, falling edge, or both risin g and falling edges

• Buffer operation (Refer to 1 9 .3. 2 Bu ff er Op era tion .)

• Digital filter (Refer to 19.3.3 Digital Filter.)

• Timing for setting the TRC register to 0000h

Overflow or input capture

• Input-capture trigger selected

fOCO128 can be selected for input-capture trigger inp ut of the

TRCGRA register.

R8C/34C Group 19. Timer RC

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 274 of 723

Figure 19.7 Block Diagram of Input Capture Function

IOA3: Bit in TRCIOR0 register

Notes:

1. The BFC bi t in the TRCM R register is set t o 1 (TRC GRC regi s t er functions as the buffer register for the TRCGRA register)

2. The BFD bi t in the TRCM R register is set t o 1 (TRC GRD regi s t er functions as the buffer register for the TRCGRB register)

3. The trigger input of the TRCGRA register can select the TRCIOA pin input or fOCO128 signal.

TRCGRA

Input capture signal

TRCGRC

TRCGRB

TRCGRD

TRCIOB

(Note 1)

(Note 2)

TRCIOC

TRCIOD

Input capture signal

Divided

by 128 IOA3 = 0

IOA3 = 1

fOCO-S or

fOCO-F fOCO128

TRCIOA Edge

selection

Edge

selection

Edge

selection

Edge

selection

(Note 3)

R8C/34C Group 19. Timer RC

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 275 of 723

19.4.1 Timer RC I/O Control Register 0 (TRCIOR0) for Input Capture Function

Notes:

1. When the BFC bit in the TRCMR register is set to 1 (buffer register of TRCGRA register), set the IOC2 bit in the

TRCIOR1 register to the same value as the IOA2 bit in the TRCIOR0 register.

2. When the BFD bit in the TRCMR register is set to 1 (buffer register of TRCGRB register), set the IOD2 bit in the

TRCIOR1 register to the same value as the IOB2 bit in the TRCIOR0 register.

3. The IOA 3 bi t i s ena b l ed wh e n th e IOA2 bit is set to 1 (input capture function).

Address 0124h

Bitb7b6b5b4b3b2b1b0

Symbol— IOB2IOB1IOB0IOA3IOA2IOA1IOA0

After Reset10001000

Bit Symbol Bit Name Function R/W

b0 IOA0 TRCGRA control bit b1 b0

0 0: Input capture to the TRCGRA register at the

rising edge

0 1: Input capture to the TRCGRA register at the

falling edge

1 0: Input capture to the TRCGRA register at both

edges

1 1: Do not set.

R/W

b1 IOA1 R/W

b2 IOA2 TRCGRA mode select bit (1) Set to 1 (input capture) in the input capture function. R/W

b3 IOA3 TRCGRA input capture input switch

bit (3) 0: fOCO128 signal

1: TRCIOA pin input R/W

b4 IOB0 TRCGRB control bit b5 b4

0 0: Input capture to the TRCGRB register at the

rising edge

0 1: Input capture to the TRCGRB register at the

falling edge

1 0: Input capture to the TRCGRB register at both

edges

1 1: Do not set.

R/W

b5 IOB1 R/W

b6 IOB2 TRCGRB mode select bit (2) Set to 1 (input capture) in the input capture function. R/W

b7 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. —

R8C/34C Group 19. Timer RC

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 276 of 723

19.4.2 Timer RC I/O Control Register 1 (TRCIOR1) for Input Capture Function

Notes:

1. When the BFC bit in the TRCMR register is set to 1 (buffer register of TRCGRA register), set the IOC2 bit in the

TRCIOR1 register to the same value as the IOA2 bit in the TRCIOR0 register.

2. When the BFD bit in the TRCMR register is set to 1 (buffer register of TRCGRB register), set the IOD2 bit in the

TRCIOR1 register to the same value as the IOB2 bit in the TRCIOR0 register.

j = A, B, C, or D

BFC, BFD: Bits in TRCMR register

Address 0125h

Bitb7b6b5b4b3b2b1b0

Symbol IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0

After Reset10001000

Bit Symbol Bit Name Function R/W

b0 IOC0 TRCGRC control bit b1 b0

0 0: Input capt ure to the TRCGRC regist er at the rising

edge

0 1: Input capture to the TRCGRC register at the

falling edge

1 0: Input capture to the TRCGRC register at both

edges

1 1: Do not set.

R/W

b1 IOC1 R/W

b2 IOC2 TRCGRC mode select bit (1) Set to 1 (input capture) in the input capture function. R/W

b3 IOC3 TRCGRC register function select

bit Set to 1. R/W

b4 IOD0 TRCGRD control bit b5 b4

0 0: Input capt ure to the TRCGRD regist er at the rising

edge

0 1: Input capture to the TRCGRD register at the

falling edge

1 0: Input capture to the TRCGRD register at both

edges

1 1: Do not set.

R/W

b5 IOD1 R/W

b6 IOD2 TRCGRD mode select bit (2) Set to 1 (input capture) in the input capture function. R/W

b7 IOD3 TRCGRD register function select

bit Set to 1. R/W

Table 19.8 Functions of TRCGRj Register when Using Input Capture Function

Input Pin

TRCGRA −General register. Can be used to read the TRC register value

at input capture. TRCIOA

TRCGRB TRCIOB

TRCGRC BFC = 0 General register. Can be used to read the TRC register value

at input capture. TRCIOC

TRCGRD BFD = 0 TRCIOD

TRCGRC BFC = 1 Buffer registers. Can be used to hold transferred value from

the general register. (Refer to 19.3.2 Buff er Op era ti on.) TRCIOA

TRCGRD BFD = 1 TRCIOB

R8C/34C Group 19. Timer RC

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 277 of 723

19.4.3 Operating Example

Figure 19.8 Operating Example of Input Capture Func tion

TRC register

count value

TSTART bit in

TRCMR register

TRCGRA register

TRCIOA input

TRCGRC register

IMFA bit in

TRCSR register

OVF bit in

TRCSR register

TRCCLK input

count source

The above applies under the following conditions:

• The CCLR bit in the TRCCR1 register is set to 1 (Clear TRC counter by input capture).

• Bits TCK2 to TCK0 in the TRCCR1 register are set to 101b (the count source is TRCCLK input).

• Bits IOA2 to IOA0 in the TRCI ORA reg is ter are set to 101b (inp ut c apture at the fall in g ed g e of t he TR CI OA inp ut ).

• The BFC bit in the TRCMR register is set to 1 (the TRCGRC register functions as the buffer register for the TRCGRA register).

Set to 0 by a program

Transfer

FFFFh

0009h

0006h

65536

0000h

0009h0006h

0006h

Transfer

R8C/34C Group 19. Timer RC

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 278 of 723

19.5 Timer Mode (Output Compare Function)

This function detects when the contents of the TRC register (counter) and the TRCGRj register (j = A, B, C, or D)

match (compare match). When a match occurs a signal is o utput from the TRCIOj pin at a given level. The output

compare function, or other mode or function, can be selected for each individual pin.

Table 19.9 lists the Specifications of Output Compare Function, Figure 19.9 shows a Block Diagram of Output

Compare Function, Table 19.10 lists the Functions of TRCGRj Re gister when Using Output Compare Function,

and Figure 19.10 shows an Operating Exam ple of Output Compare Function.

j = A, B, C, or D

Table 19.9 Specifications of Output Compare Function

Item Specification

Count source f1, f2, f4, f8, f32, fOCO40M, fOCO-F

External signal (rising edge) input to TRCCLK pin

Count operation Increment

Count period • T he CCLR bit in the TRCCR1 register is set to 0 (free running operation):

1/fk × 65,536

fk: Count source frequency

• The CCLR bit in th e TRCCR1 register is set to 1 (TRC register set to 0000h at

TRCGRA compare match):

1/fk × (n + 1)

n: TRCGRA register setting value

Waveform output timing Compare match

Count start condition 1 (count starts) is written to the TSTART bit in th e TRCMR register.

Count stop condition • When the CSEL bit in the TRCCR2 register is set to 0 (count continues after

compare match with TRCGRA).

0 (count stops) is written to the TSTART bit in the TR CMR register.

The output compare output pin retains output level before count stops, the TRC

• When the CSEL bit in the TRCCR2 register is set to 1 (count stops at compare

match with TRCGRA register).

The count stops at the compare match wi th the TRCGRA register. The output

compare output pin retains the level after the output is changed by the compare

match.

Interrupt request generation

timing • Compare match (contents of registers TRC and TRCGRj match)

• The TRC register overflows.

TRCIOA, TRCIOB, TRCIOC, and

TRCIOD pin functions Programmable I/O port or output compare output (Selectable individually for

each pin)

INT0 pin function Programmable I/O port, pulse output forced cutoff signal input, or INT0 interrupt

input

Read from timer The count value can be read by reading the TRC register.

Write to timer The TRC register can be writt e n to .

Selectable functions • Output compare ou tput pin selection

One or more of pins TRCIOA, TRCIOB, TRCIOC, and TRCIOD

• Compare match output level selection

“L” output, “H” output, or toggl e output

• Ini tial output level selection

Sets output level for period from count start to compare match

• Timing for setting the TRC register to 0000h

Overflow or compare match with the TRCGRA register

• Buffer operation (Refer to 19.3.2 Buffer Operation.)

• Pulse output forced cutoff signal input (Refer to 19.3.4 Forced Cutoff of Pulse

Output.)

• Can be use d as an internal timer by disabling timer RC output

• Changing output pins for reg isters TRCGRC and TRCGRD

TRCGRC can be used for output control of th e TRCIOA pin and TRCGRD can

be used for output control of the TRCIOB pin.

• A/D trigger ge neration

R8C/34C Group 19. Timer RC

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 279 of 723

Figure 19.9 Block Diagram of Output Compare Function

TRCIOA Output

control Comparator TRCGRA

TRC

TRCIOC TRCGRC

TRCIOB TRCGRB

TRCIOD TRCGRD

Output

control

Output

control

Output

control

Compare match signal

Comparator

R8C/34C Group 19. Timer RC

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 280 of 723

19.5.1 Timer RC Control Register 1 (TRCCR1) for Output Compare Function

Notes:

1. Set to these bits when the TSTART bit in t he TRCMR register is set to 0 (count stops).

2. If the pin function is set for waveform output (refer to 7.5 Port Settings), the initial output level is output when the

TRCCR1 register is set.

3. To select fOCO-F, set it to the clock frequency higher than the CPU clock frequency.

j = A, B, C, or D

BFC, BFD: Bits in TRCMR register

Address 0121h

Bitb7b6b5b4b3b2b1b0

Symbol CCLR TCK2 TCK1 TCK0 TOD TOC TOB TOA

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 TOA TRCIOA output level select bit (1, 2) 0: Initial output “L”

1: Initial output “H” R/W

b1 TOB TRCIOB output level select bit (1, 2) R/W

b2 TOC TRCIOC output level select bit (1, 2) R/W

b3 TOD TRCIOD output level select bit (1, 2) R/W

b4 TCK0 Count source select bit (1) b6 b5 b4

0 0 0: f1

0 0 1: f2

0 1 0: f4

0 1 1: f8

1 0 0: f32

1 0 1: TRCCLK input rising edge

1 1 0: fOCO40M

1 1 1: fOCO-F (3)

R/W

b5 TCK1 R/W

b6 TCK2 R/W

b7 CCLR TRC counter clear select bit 0 : Disable clear (free-running operation)

1: Clear by compare match in the TRCGRA register R/W

Table 19.10 Functions of TRCGRj Register when Using Output Compare Function

Output Pin

TRCGRA −General register. Write a compare value to one of these

registers. TRCIOA

TRCGRB TRCIOB

TRCGRC BFC = 0 General register. Write a compare value to one of these

registers. TRCIOC

TRCGRD BFD = 0 TRCIOD

TRCGRC BFC = 1 Buffer register. Write the next compare value to one of

these registers. (Refer to 19.3.2 Buffer Operation.) TRCIOA

TRCGRD BFD = 1 TRCIOB

R8C/34C Group 19. Timer RC

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 281 of 723

19.5.2 Timer RC I/O Control Register 0 (TRCIOR0) for Output Compare Function

Notes:

1. When the BFC bit in the TRCMR register is set to 1 (buffer register of TRCGRA register), set the IOC2 bit in

theTRCIOR1 register to the same value as the IOA2 bit in the TRCIOR0 register.

2. When the BFD bit in the TRCMR register is set to 1 (buffer register of TRCGRB register), set the IOD2 bit in the

TRCIOR1 register to the same value as the IOB2 bit in the TRCIOR0 register.

Address 0124h

Bitb7b6b5b4b3b2b1b0

Symbol— IOB2IOB1IOB0IOA3IOA2IOA1IOA0

After Reset10001000

Bit Symbol Bit Name Function R/W

b0 IOA0 TRCGRA control bit b1 b0

0 0: Disable pin output by compare match (TRCIOA pin

functions as the programmable I/O port)

0 1: “L” output by compare match in the TRCGRA

1 0: “H” output by compare match in the TRCGRA

1 1: Toggle output by compare match in the TRCGRA

R/W

b1 IOA1 R/W

b2 IOA2 TRCGRA mode select bit (1) Set to 0 (output compare) in the output compare

function. R/W

b3 IOA3 TRCGRA input capture input

switch bit Set to 1. R/W

b4 IOB0 TRCGRB control bit b5 b4

0 0: Disable pin output by compare match (TRCIOB pin

functions as the programmable I/O port)

0 1: “L” output by compare match in the TRCGRB

1 0: “H” output by compare match in the TRCGRB

1 1: Toggle output by compare match in the TRCGRB

R/W

b5 IOB1 R/W

b6 IOB2 TRCGRB mode select bit (2) Set to 0 (output compare) in the output compare

function. R/W

b7 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. —

R8C/34C Group 19. Timer RC

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 282 of 723

19.5.3 Timer RC I/O Control Register 1 (TRCIOR1) for Output Compare Function

Notes:

1. When the BFC bit in the TRCMR register is set to 1 (buffer register of TRCGRA register), set the IOC2 bit in

theTRCIOR1 register to the same value as the IOA2 bit in the TRCIOR0 register.

2. When the BFD bit in the TRCMR register is set to 1 (buffer register of TRCGRB register), set the IOD2 bit in

theTRCIOR1 register to the same value as the IOB2 bit in the TRCIOR0 register.

Address 0125h

Bitb7b6b5b4b3b2b1b0

Symbol IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0

After Reset10001000

Bit Symbol Bit Name Function R/W

b0 IOC0 TRCGRC control bit b1 b0

0 0: Disable pin output by compare match

0 1: “L” output by compare match in the TRCGRC

1 0: “H” output by compare match in the TRCGRC

1 1: Toggle output by compare match in the TRCGRC

R/W

b1 IOC1 R/W

b2 IOC2 TRCGRC mode select bit (1) Set to 0 (output compare) in the outp ut compare

function. R/W

b3 IOC3 TRCGRC register function select

bit 0: TRCIOA output register

1: General register or buffer register R/W

b4 IOD0 TRCGRD control bit b5 b4

0 0: Disable pin output by compare match

0 1: “L” output by compare match in the TRCGRD

1 0: “H” output by compare match in the TRCGRD

1 1: Toggle output by compare match in the TRCGRD

R/W

b5 IOD1 R/W

b6 IOD2 TRCGRD mode select bit (2) Set to 0 (output compare) in the outp ut compare

function. R/W

b7 IOD3 TRCGRD register function select

bit 0: TRCIOB output register

1: General register or buffer register R/W

R8C/34C Group 19. Timer RC

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 283 of 723

19.5.4 Timer RC Control Register 2 (TRCCR2) for Output Compare Function

Notes:

1. Enabled when in PWM mode.

2. Enabled when in the output compare function , PWM mod e, or PW M2 mod e. For notes on PWM2 mode , refer to

19.9.6 TRCMR Register in PWM2 Mode.

3. Enabled when in PWM2 mode.

Address 0130h

Bitb7b6b5b4b3b2b1b0

Symbol TCEG1 TCEG0 CSEL — — POLD POLC POLB

After Reset00011000

Bit Symbol Bit Name Function R/W

b0 POLB PWM mode output level control

bit B (1) 0: TRCIOB output level selected as “L” active

1: TRCIOB output level selected as “H” active R/W

b1 POLC PWM mode output level control

bit C (1) 0: TRCIOC output level selected as “L” active

1: TRCIOC output level selected as “H” active R/W

b2 POLD PWM mode output level control

bit D (1) 0: TRCIOD output level selected as “L” active

1: TRCIOD output level selected as “H” active R/W

b3 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. —

b4 —

b5 CSEL TRC count operation select bit (2) 0: Count continues at compare match with the

TRCGRA register

1: Count stops at compare match with the TRCGRA

R/W

b6 TCEG0 TRCTRG input edge select bit (3) b7 b6

0 0: Disable the trigger input from the TRCTRG pin

0 1: Rising edge selected

1 0: Falling edge selected

1 1: Both edges selected

R/W

b7 TCEG1 R/W

R8C/34C Group 19. Timer RC

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 284 of 723

19.5.5 Operating Example

Figure 19.10 Operating Example of Output Compare Functio n

Output level held

TRC register value

Count source

m+1 m+1

TSTART bit in

TRCMR register

TRCIOA output

IMFA bit in

TRCSR register

n+1

TRCIOB output “H” output by

compare match

Set to 0 by a program

IMFB bit in

TRCSR register

Initial output “L”

TRCIOC output

Set to 0 by a program

IMFC bit in

TRCSR register

Initial output “H”

“L” output by compare match

P+1

m: TRCGRA register setting value

n: TRCGRB register setting value

p: TRCGRC register setting value

The above applies under the following conditions:

Count

restarts

Count

stops

Output level held

Set to 0 by a program

• Bits BFC and BFD in the TRCMR register are set to 0 (TRCGRC and TRCGRD do not operate as buffers).

• Bits EA, EB, and EC in the TRCOER register are set to 0 (output from TRCIOA, TRCIOB, and TRCIOC enabled).

• The CCLR bit in the TRCCR1 register is set to 1 (set the TRC register to 0000h by TRCGRA compare match).

• In the TRCCR1 register, bits TOA and TOB are set to 0 (“L” initial output until compare match) and the TOC bit is set to 1 (“H” initial output until

compa re match).

• Bits IOA2 to IOA0 in the TRCIOR0 register are set to 011b (TRCIOA output inverted at TRCGRA compare match).

• Bits IOB2 to IOB0 in the TRCIOR0 register are set to 010b (“H” TRCIOB output at TRCGRB compare match).

• Bits IOC2 to IOC2 in the TRCIOR1 register are set to 001b (“L” TRCIOC output at TRCGRC compare match).

• The CSEL bit in the TRCCR2 register is set to 0 (TRC count continues after TRCGRA compare match).

Output level held

Output inverted by

compare match

R8C/34C Group 19. Timer RC

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 285 of 723

19.5.6 Changing Output Pins in Registers TRCGRC and TRCGRD

The TRCGRC register can be used for output control of the TRCIOA pin, and the TRCGRD register can be

used for output control of the TRCIOB pin. Therefore, each pin output can be controlle d as follows:

• TRCIOA output is controlled by the values in registers TRCGRA and TRCGRC.

• TRCIOB output is controlled by the values in regist ers TRCGRB and TRCGRD.

Change output pins in registers TRCGRC and TRCGRD as follows:

• Set the IOC3 bit in the TRCIOR1 register to 0 (TRCIOA output register) and set the IOD3 bit to 0

(TRCIOB output register).

• Set bits BFC and BFD in the TRCMR register to 0 (general register).

• Set different values in registers TRCGRC and TRCGRA. Also, set different values in registers TRCGRD

and TRCGRB.

Figure 19.12 shows an Operating Example When TRCGRC Register is Used for Output Control of TRCIOA

Pin and TRCGRD Register is Used for Output Control of TRCIOB Pin.

Figure 19.11 Changing Output Pins in Registers TRCGRC and TRCGRD

TRCIOA Output

control Comparator TRCGRA

TRC

TRCIOC Output

control Comparator TRCGRC

Compare match signal

TRCIOB Output

control Comparator TRCGRB

TRCIOD Output

control Comparator TRCGRD

Compare match signal

IOC3 = 0 in

TRCIOR1 register

IOC3 = 1

IOD3 = 0 in

TRCIOR1 register

IOD3 = 1

R8C/34C Group 19. Timer RC

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 286 of 723

Figure 19.12 Operating Example When TRCGRC Register is Used for Output Control of TRCIOA

Pin and TRCGRD Register is Used for Output Control of TRCIOB Pin

Set to 0 by a programSet to 0 by a program

Value in TRC register

Count source

TRCIOA output

FFFFh

TRCIOB output

m: Value set in TRCGRA register

n: Value set in TRCGRC register

p: Value set in TRCGRB register

q: Value set in TRCGRD register

The above applies under the following conditions:

• Bits BFC and BFD in the TRCMR register are set to 0 (registers TRCGRC and TRCGRD are not used as buffer register).

• Bits EA and EB in the TRCOER register are set to 0 (e na ble T R CIOA and TRCIO B pin ou tpu ts).

• The CCLR bit in the TRC CR 1 re gist er are se t to 1 (set t he TRC register to 000 0h b y compare match in th e TR CG RA re gist er).

• Bits TOA and TOB in the TRCCR1 register are set to 0 (initial output “L” to compare match).

• Bits IOA2 to IOA0 in the TRCIOR0 register are set to 011b (TRCIOA output inverted at TRCGRA register compare match).

• Bits IOB2 to IOB0 in the TRCIOR0 register are set to 011b (TRCIOB output inverted at TRCGRB register compare match).

• Bits IOC2 to IOC0 in the TRCIOR1 register are set to 011b (TRCIOA output inverted at TRCGRC register compare match).

• The IOC3 bit in the TRCIOR1 register are set to 0 (TRCIOA output register).

• Bits IOD2 to IOD0 in the TRCIOR1 register are set to 011b (TRCIOB output inverted at TRCGRD register compare match).

• The IOD3 bit in the TRCIOR1 register are set to 0 (TRCIOB output register).

• The CSEL bit in th e T RC CR 2 re gist er are se t to 0 (T RC co ntin ue s cou n ting aft er compare mat ch).

m+1

n+1

0000h

m-n

p+1

p-qq+1

IMFA bit in

TRCSR register

IMFC bit in

TRCSR register

Set to 0 by a program

Output inverted by compare match

Initial output “L”

IMFB bit in

TRCSR register

IMFD bit in

TRCSR register

Initial output “L”

Set to 0 by a program

Output inverted by compare match

R8C/34C Group 19. Timer RC

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 287 of 723

19.6 PWM Mode

This mode outputs PWM waveforms. A maximum of three PWM waveforms with the same period are output.

The PWM mode, or the timer mode, can be selected for each individual pin. (However, since the TRCGRA register

is used when using any pin for the PWM mode, the TRCGRA register cannot be used for the timer mode.)

Table 19.11 lists the Specifications of PWM Mode, Figure 19.13 shows a PWM Mode Block Diagram, Table 19.12

lists the Functions of TRCGRh Register in PWM Mode, and Figures 19.14 and 19.15 show Operating Examples of

PWM Mode.

j = B, C, or D

h = A, B, C, or D

Table 19.11 Specifications of PWM Mode

Item Specification

Count source f1, f2, f4, f8, f32, fOCO40M, fOCO-F

External signal (rising edge) input to TRCCLK pin

Count operation Increment

PWM waveform PWM period: 1/fk × (m + 1)

Active level width: 1/fk × (m - n)

Inactive width: 1/fk × (n + 1)

fk: Count source frequency

m: TRCGRA register setting value

n: TRCGRj register setting value

Count start condition 1 (count starts) is written to the TSTART bit in the TRCMR register.

Count stop condition • When the CSEL bit in the TRCCR2 register is set to 0 (count continues

after compar e ma tc h with TRCG RA) .

0 (count stops) is written to the TSTART bit in the TRCMR register.

PWM output pin retains output level before count stops, TRC register

retains value before count stops.

• When the CSEL bit in the TRCCR2 register is set to 1 (count stops at

compare match with TRCGRA register).

The count stops at the compare match with the TRCGRA register. The

PWM output pin retains the level after the output is changed by the

compare match.

Interrupt request generation

timing • Compare match (contents of registers TRC and TRCGRh match)

• The TRC register overflows.

TRCIOA pin function Programmable I/O port

TRCIOB, TRCIO C , an d

TRCIOD pin functions Programmable I/O port or PWM output (selectable individually for each

pin)

INT0 pin function Programmable I/O port, pulse output forced cutoff signal input, or INT0

interrupt input

Read from timer The cou n t valu e ca n be rea d by rea ding the TRC register.

Write to timer The TRC register can be written to.

Selectable functions • One to thr ee pins selectable as PWM output pins

One or more of pins TRCIOB, TRCIOC, and TRCIOD

• Active level selectable for each pin

• Initial level selectable for each pin

• Buffer operation (Refer to 19.3.2 Buffer Operation.)

• Pulse output forced cutoff signal input (Refer to 19.3.4 Forced Cutoff

of Pulse Output.)

• A/D trigger generation

m+1

n+1 m-n (“L” is active level)

R8C/34C Group 19. Timer RC

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 288 of 723

Figure 19.13 PWM Mode Block Diagram

TRCIOB

Output

control

Comparator TRCGRA

TRC

Compare match signal

TRCGRB

TRCIOC

TRCGRC

TRCGRD

TRCIOD

Notes:

1. The BFC bit in the TRCMR register is set to 1 (TRCGRC register functions as the buffer register for the TRCGRA register)

2. The BFD bit in the TRCMR register is set to 1 (TRCGRD register functions as the buffer register for the TRCGRB register)

(Note 1)

(Note 2)

Compare match signal

Comparator

R8C/34C Group 19. Timer RC

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 289 of 723

19.6.1 Timer RC Control Register 1 (TRCCR1) in PWM Mode

Notes:

1. Set to these bits when the TSTART bit in t he TRCMR register is set to 0 (count stops).

2. If the pin function is set for waveform output (refer to 7.5 Port Settings), the initial output level is output when the

TRCCR1 register is set.

3. To select fOCO-F, set it to the clock frequency higher than the CPU clock frequency.

Address 0121h

Bitb7b6b5b4b3b2b1b0

Symbol CCLR TCK2 TCK1 TCK0 TOD TOC TOB TOA

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 TOA TRCIOA output level select bit (1) Disabled in PWM mode R/W

b1 TOB TRCIOB output level select bit (1, 2) 0: Initial output selected as non-active level

1: Initial output selected as active level R/W

b2 TOC TRCIOC output level select bit (1, 2) R/W

b3 TOD TRCIOD output level select bit (1, 2) R/W

b4 TCK0 Count source select bit (1) b6 b5 b4

0 0 0: f1

0 0 1: f2

0 1 0: f4

0 1 1: f8

1 0 0: f32

1 0 1: TRCCLK input rising edge

1 1 0: fOCO40M

1 1 1: fOCO-F (3)

R/W

b5 TCK1 R/W

b6 TCK2 R/W

b7 CCLR TRC counter clear select bit 0: Disable clear (free-running operation)

1: Clear by compare match in the TRCGRA register R/W

R8C/34C Group 19. Timer RC

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 290 of 723

19.6.2 Timer RC Control Register 2 (TRCCR2) in PWM Mode

Notes:

1. Enabled when in PWM mode.

2. Enabled when in output compare function, PWM mode, or PWM2 mode. For notes on PWM2 mode, refer to

19.9.6 TRCMR Register in PWM2 Mode.

3. Enabled when in PWM2 mode.

h = A, B, C, or D

BFC, BFD: Bits in TRCMR register

Note:

1. The output level does not chan ge even when a compare match occurs if the TRCGRA register value (PWM

period) is the same as the TRCGRB, TRCGRC, or TRCGRD register value.

Address 0130h

Bitb7b6b5b4b3b2b1b0

Symbol TCEG1 TCEG0 CSEL — — POLD POLC POLB

After Reset00011000

Bit Symbol Bit Name Function R/W

b0 POLB PWM mode output level control

bit B (1) 0: TRCIOB output level selected as “L” active

1: TRCIOB output level selected as “H” active R/W

b1 POLC PWM mode output level control

bit C (1) 0: TRCIOC output level selected as “L” active

1: TRCIOC output level selected as “H” active R/W

b2 POLD PWM mode output level control

bit D (1) 0: TRCIOD output level selected as “L” active

1: TRCIOD output level selected as “H” active R/W

b3 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. —

b4 —

b5 CSEL TRC count operation select bit (2) 0: Count continues at compa r e match with the

TRCGRA register

1: Count stops at compare match with the TRCGRA

R/W

b6 TCEG0 TRCTRG input edge select bit (3) b7 b6

0 0: Disable the trigger input from the TRCTRG pin

0 1: Rising edge selected

1 0: Falling edge selected

1 1: Both edges selected

R/W

b7 TCEG1 R/W

Table 19.12 Functions of TRCGRh Register in PWM Mode

TRCGRA −General register. Set the PWM period. −

TRCGRB −General register. Set the PWM output change point. TRCIOB

TRCGRC BFC = 0 General register. Set the PWM output change point. TRCIOC

TRCGRD BFD = 0 TRCIOD

TRCGRC BFC = 1 Buffer register. Set the next PWM period. (Refer to 19.3.2 Buffer

Operation.) −

TRCGRD BFD = 1 Buffer register. Set the next PWM output change point. (Refer to

19.3.2 Buffer Operation.) TRCIOB

R8C/34C Group 19. Timer RC

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 291 of 723

19.6.3 Operating Example

Figure 19.14 Operating Example of PWM Mode

TRCIOC output

TRCIOD output

m: TRCGRA register setting value

n: TRCGRB register setting value

p: TRCGRC register setting value

q: TRCGRD register setting value

TRCIOB output

IMF A b i t in

TRCSR register

IMF B b it in

TRCSR register

IMFC bit in

TRCSR register

IMFD bit in

TRCSR register

The above applies under the following conditions:

• Bits BFC and BFD in the TRCMR register are set to 0 (registers TRCGRC and TRCGRD do not operate as buffers).

• Bits EB, EC, and ED in the TRCOER register are set to 0 (output from TRCIOB, TRCIO C, and TRCIOD enabled).

• Bits TOB and TOC in the TRCCR1 register are set to 0 (inactive level), the TOD bit is set to 1 (active level).

• The POLB bit in the TRCCR2 register is set to 1 (“H” active), bits POLC and POLD are set to 0 (“L” active).

Value in TRC register

Count source

m+1

n+1

m-n

p+1 m-p

m-qq+1

Inac tive le ve l “L”

Active level “H”

Inac tive le ve l “H”

Active level “L”

Set to 0 by a program Set to 0 by a program

Initial out put “L”

to compare match

Initial output “H”

to compare match

Initia l o u tput “L”

to compare match

R8C/34C Group 19. Timer RC

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 292 of 723

Figure 19.15 Operating Example of PWM Mode (Duty 0% and Duty 100%)

Rewritten by

a program

TRC register value

m: TRCG RA register setting value

Set to 0 by a program

Rewritten by a program

0000h

Duty 0%

TRCGRB register

IMFA bit in

TRCSR register

IMFB bit in

TRCSR register

TSTART bit in

TRCMR register

TRCIOB output

p (p>m)n

TRC register value

0000h

TRCGRB register

IMFA bit in

TRCSR register

IMFB bit in

TRCSR register

TSTART bit in

TRCMR register

TRCIOB output

pn m

The above applies under the following conditions:

• The EB bit in the TRCOER register is set to 0 (output from TRCIO B enabled).

• The POLB bit in the TRCCR2 register is set to 0 (“L” active).

TRCIOB output does not switch to “L” because

no compare match wit h the TRCGRB re gister

has occurred

If compare matches occur simultaneously with registers TRCGRA and

TRCGRB, the compare match with the TRCGRB register has priority.

TRCIOB output switches to “L”. (In other words, no change).

TRCIOB out put swi t che s to “L” at compare mat ch with the

TRCGRB register. (In other words, no change).

Set to 0 by a program

Duty 100%

Set to 0 by a program

R8C/34C Group 19. Timer RC

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 293 of 723

19.7 PWM2 Mode

This mode outputs a single PWM waveform. After a gi ven wait duratio n has elapsed fol lowing the t rigger, the pin

output switches to active level. Then, after a given duration, the output switches back to inactive level.

Furthermore, the counter stops at the same time the output returns to inactive level, making it possible to use

PWM2 mode to output a programmable wait one-shot waveform.

Since timer RC uses multiple general registers in PWM2 mode, other modes cannot be used in conjunction wi th it.

Figure 19.16 shows a PW M2 Mode Block Diagram, Table 19.1 3 lists the Specifications of PWM2 Mode, Table

19.14 lists the Fu nctions of TRCGRj Register in PWM2 Mod e, and Figures 19.17 to 19.19 show Operating

Examples of PWM2 Mode.

Figure 19.16 PWM2 Mode Block Diagram

TRCTRG Input

control

TRCIOB Output

control

Comparator TRCGRATRC

TRCGRD

Compare match signal

Comparator TRCGRB

Comparator TRCGRC

Note:

1. The BFD bit in the TRCMR register is set to 1 (the TRCGRD register functions as the buffer register for the TRCGRB regi ster).

Count clear signal

Trigger signal

(Note 1)

R8C/34C Group 19. Timer RC

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 294 of 723

j = A, B, or C

Table 19.13 Specifications of PWM2 Mode

Item Specification

Count source

f1, f2, f4, f8, f32, fOCO40M, fOCO-F

External signal (rising edge) input to TRCCLK pin

Count operation Increment TRC register

PWM waveform PWM period: 1/fk × (m + 1) (no TRCTRG input)

Active level width: 1/fk × (n - p)

Wait time from count start or trigger: 1/fk × (p + 1)

fk: Count source frequency

m: TRCGRA register setting value

n: TRCGRB register setting value

p: TRCGRC register setting value

Count start conditions • Bits TCEG1 to TCEG0 in the TRCCR2 register are set to 00b (TRCTRG trigger

disabled) or the CSEL bit in the TRCCR2 register is set to 0 (count continues).

1 (count starts) is written to the TSTART bit in the TRCMR register.

• Bits TCEG1 to TCEG0 in the TRCCR2 register are set to 01b, 10b, or 11b (TRCTRG

trigger enabled) and the TSTART bi t in the TRCMR register is set to 1 (count starts).

A trigger is input to the TRCTRG pin

Count stop conditions • 0 (count stops) is written to the TSTART bit in the TRCMR register while the CSEL bit in

the TRCCR2 register is set to 0 or 1.

The TRCIOB pin outputs the initial level in accord ance with the value of the TOB bit in

the TRCCR1 register. The TRC register retains th e value before count stops.

• Th e count stops due to a compare match with TRCGRA while the CSEL bit in the

TRCCR2 register is set to 1

The TRCIOB pin outputs the initial level. The TRC register retains the value before

count stops if the CCLR bit in the TRCCR1 register is set to 0. The TRC register is set

to 0000h if the CCLR bit in the TRCCR1 register is set to 1.

Interrupt req uest

generation timing • Compare match (contents of TRC and TRCGRj registers match)

• The TRC regi ster overflows

TRCIOA/TRCTRG pin

function Programmable I/O port or TRCTRG input

TRCIOB pin function PWM output

TRCIOC and TRCIOD pin

functions Programmable I/O port

INT0 pin function Programmable I/O port, pulse output forced cutoff signal input, or INT0 interrupt input

Read from timer The count value can be read by reading the TRC register.

Write to timer The TRC register can be written to.

Selectable functions • External tri gger and valid edge selection

The edge or edges of the signal input to the TRCTRG pin can be used as the PWM

output trigger: rising edge, falling edge, or both rising and falling edges

• Buffer operation (Refer to 19.3.2 Buffer Operation.)

• Pulse output forced cutoff signal input (Refer to 19.3.4 Forced Cutoff of Pulse

Output.)

• Digital filter (Refer to 19.3.3 Di git al Filter.)

• A/D trigger generation

m+1

TRCTRG input

TRCIOB output

(TRCTRG: Rising edge, active level is “H”)

n-p

n+1

p+1 p+1

n+1

n-p

R8C/34C Group 19. Timer RC

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 295 of 723

19.7.1 Timer RC Control Register 1 (TRCCR1) in PWM2 Mode

Notes:

1. Set to these bits when the TSTART bit in t he TRCMR register is set to 0 (count stops).

2. If the pin function is set for waveform output (refer to 7.5 Port Settings), the initial output level is output when the

TRCCR1 register is set.

3. To select fOCO-F, set it to the clock frequency higher than the CPU clock frequency.

Address 0121h

Bitb7b6b5b4b3b2b1b0

Symbol CCLR TCK2 TCK1 TCK0 TOD TOC TOB TOA

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 TOA TRCIOA output level select bit (1) Disabled in PWM2 mode R/W

b1 TOB TRCIOB output level select bit (1, 2) 0: Active level “H”

(Initial output “L”

“H” output by compare match in the TRCGRC

“L” output by compare match in the TRCGRB

1: Active level “L”

(Initial output “H”

“L” output by compare match in the TRCGRC

“H” output by compare match in the TRCGRB

R/W

b2 TOC TRCIOC output level select bit (1) Disabled in PWM2 mode R/W

b3 TOD TRCIOD output level select bit (1) R/W

b4 TCK0 Count source select bit (1) b6 b5 b4

0 0 0: f1

0 0 1: f2

0 1 0: f4

0 1 1: f8

1 0 0: f32

1 0 1: TRCCLK input rising edge

1 1 0: fOCO40M

1 1 1: fOCO-F (3)

R/W

b5 TCK1 R/W

b6 TCK2 R/W

b7 CCLR TRC counter clear se lect bit 0: Disable clear (free-running operation)

1: Clear by compare match in the TRCGRA

R/W

R8C/34C Group 19. Timer RC

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 296 of 723

19.7.2 Timer RC Control Register 2 (TRCCR2) in PWM2 Mode

Notes:

1. Enabled when in PWM mode.

2. Enabled when in output compare function, PWM mode, or PWM2 mode. For notes on PWM2 mode, refer to

19.9.6 TRCMR Register in PWM2 Mode.

3. Enabled when in PWM2 mode.

Address 0130h

Bitb7b6b5b4b3b2b1b0

Symbol TCEG1 TCEG0 CSEL — — POLD POLC POLB

After Reset00011000

Bit Symbol Bit Name Function R/W

b0 POLB PWM mode output level control

bit B (1) 0: TRCIOB output level selected as “L” active

1: TRCIOB output level selected as “H” active R/W

b1 POLC PWM mode output level control

bit C (1) 0: TRCIOC output level selected as “L” active

1: TRCIOC output level selected as “H” active R/W

b2 POLD PWM mode output level control

bit D (1) 0: TRCIOD output level selected as “L” active

1: TRCIOD output level selected as “H” active R/W

b3 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. —

b4 —

b5 CSEL TRC count operation select bit (2) 0: Count continues at compare match with the

TRCGRA register

1: Count stops at compare match with the TRCGRA

R/W

b6 TCEG0 TRCTRG input edge select bit (3) b7 b6

0 0: Disable the trigger input from the TRCTRG pin

0 1: Rising edge selected

1 0: Falling edge selected

1 1: Both edges selected

R/W

b7 TCEG1 R/W

R8C/34C Group 19. Timer RC

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 297 of 723

19.7.3 Timer RC Digital Filter Function Select Register (TRCDF) in PWM2 Mode

Notes:

1. These bits are enabled for the input capture function.

2. These bits are enabled when in PWM2 mode and bits TCEG1 to TCEG0 in the TRCCR2 register are set to 01b,

10b, or 11b (TRCTRG trigger input enabled).

j = A, B, C, or D

BFC, BFD: Bits in TRCMR register

Note:

1. Do not set the TRCGRB and TRCGRC registers to the same value.

Address 0131h

Bitb7b6b5b4b3b2b1b0

Symbol DFCK1 DFCK0 — DFTRG DFD DFC DFB DFA

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 DFA TRCIOA pin digital filter function select bit (1) 0: Function is not used

1: Function is used R/W

b1 DFB TRCIOB pin digital filter function select bit (1) R/W

b2 DFC TRCIOC pin digital filter function select bit (1) R/W

b3 DFD TRCIOD pin digital filter function select bit (1) R/W

b4 DFTRG TRCTRG pin digital filter function select bit (2) R/W

b5 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b6 DFCK0 Clock select bits for digital filter function (1, 2) b7 b6

0 0: f32

0 1: f8

1 0: f1

1 1: Count source (clock selected by bits

TCK2 to TCK0 in the TRCCR1

R/W

b7 DFCK1 R/W

Table 19.14 Functions of TRCGRj Register in PWM2 Mode

TRCGRA −General register. Set the PWM period. TRCIOB pin

TRCGRB −General register. Set the PWM output change point.

TRCGRC (1) BFC = 0 General register. Set the PWM output change point (wait time

after trigger).

TRCGRD (1) BFD = 0 (Not used in PWM2 mode) −

TRCGRD BFD = 1 Buffer register. Set the next PWM output change point. (Refer to

19.3.2 Buffer Operation.) TRCIOB pin

R8C/34C Group 19. Timer RC

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 298 of 723

19.7.4 Operating Example

Figure 19.17 Operating Example of PWM2 Mode (TRCTRG Trigger Input Disabled)

Set to 0 by a program Set to 0 by a program

TRC register value

Count source

m+1

n+1

0000h

FFFFh

p+1

TRCIOB output

m: TRCGRA register setting value

n: TRCGRB register setting value

p: TRCGRC register setting value

TSTART bit in

TRCMR register

Count stops

because the

CSEL bit is

set to 1

“L” initial output

“H” output at TRCGRC

IMFA bit in

TRCSR register

Set to 0 by a program

IMFB bit in

TRCSR register

CSEL bit in

TRCCR2 register

Set to 1 by

a program

IMFC bit in

TRCSR register

Transfer

TRCGRB register

TRCGRD register n Next data

Transfer

Transfer from buffer register to general register

The above applies under the followi ng condit ions:

• The TOB bit in the TRCCR1 register is set to 0 (initial level is “L”, “H” output by compare match with the TRCGRC register, “L” output by compare

match with the TRCGRB register).

• Bits TCEG1 and TCEG0 in the TRCCR2 register are set to 00b (TRCTRG trigger input disabled).

Set to 0000h

by a program

Previous value held if the

TSTART bit is set to 0

TSTART bit

is set to 0

TRC register cleared

at TRCGRA register

compare match

p+1

“H” output at TRCGRC register

compare match

No change

Return to initial output

if the TSTART bit is

set to 0

R8C/34C Group 19. Timer RC

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 299 of 723

Figure 19.18 Operating Example of PWM2 Mode (TRCTRG Trigger Input Enabled)

Set to 0 by

a program

TRC reg ister valu e

Count source

m+1

n+1

0000h

FFFFh

p+1

TRCIOB ou tpu t

m: TR CGRA register setti ng value

n: TRCGRB register setting value

p: TRCGRC re gist er se ttin g valu e

TSTART b it in

TRCMR register

Count stops

because t he

CSEL b it is

set to 1

“L” initial output

“H” output at

TRCGRC register

compare match

IMF A bit in

TRCSR register

Set to 0 by

a program

IMFB bit in

TRCSR register

CSEL bit in

TRCCR2 register

IMFC bit in

TRCSR register

Transfer

TRCGRB register

TRCGR D regi ster Next data

Transfer

Transfer fro m bu ffe r registe r to g ene ral re gister

The abo ve ap plie s u n d er the f ollo wi ng co ndi tio ns:

• The T OB b it in the TRCCR1 reg iste r is set to 0 (initial le vel is “L”, “H” out pu t b y compare ma tc h w ith the T R CGRC register, “L” ou tpu t b y compare m atc h w ith t he

TRCGRB re g is t e r).

• Bits TCE G 1 a nd TCEG0 in the TRCCR2 reg iste r are se t to 1 1b (trigger at bo th rising an d f all ing ed ge s o f T R CTRG inpu t).

Set to 0000h

by a program

Previous value

held if the

TSTART bit is

set to 0

The TSTART

bit is set to 0

TRC re gis ter cle a red

at TRCGRA register

compare match

Return to in itia l v alue if the

TSTAR T b it is set to 0

TRC regi ste r (counte r)

cleared at T RCTRG pin

trigger input

TRCTRG inp ut Count starts

TSTART bit

is set to 1

n+1

p+1 p+1

“L” output at

TRCGRB register

compare match

Inactive level so

TRCTRG input is

enabled

Active level so T R C T RG

input is disabled

Set to 0 by

a program Set to 0 by

a program

Transfer

Transfer from buffer register to general register

Set to 1 by

a program

Changed by a program

Count starts at

TRCTRG p in

trigger in pu t

R8C/34C Group 19. Timer RC

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 300 of 723

Figure 19.19 Operating Example of PWM2 Mode (Duty 0% and Duty 100%)

• TRCGRC register setting value greater than TRCGRA

TRC register value

Set to 0 by a

program

0000h

IMFB bit in

TRCSR register

IMFC bit in

TRCSR register

TSTART bit in

TRCMR register

TRCIOB outp ut

The above applies under the following conditions:

• The TOB bit in the TRCCR1 register is set to 0 (initial level is “L”, “H” output by compare match with the TRCGRC reg i ster, “L” output by compare

match with the TRCGRB register).

• Bits TCE G1 and TCEG0 in the TRCCR2 register are set to 00b (TRCTRG trigger input disabled).

p+1

IMFA bit in

TRCSR register

“L” initial

output

No compare match with

TRCGRB register, so

“H” output continues

“H” output at TRCGRC register

compar e ma t c h

m+1

• TRCGRB register setting value greater than TRCGRA

TRC register value

0000h

IMFB bit in

TRCSR register

IMFC bit in

TRCSR register 0

TSTART bit in

TRCMR register

TRCIOB outp ut

n+1

IMFA bit in

TRCSR register

“L” initial

output

“L” output at

TRCGRB register

compare match

with no change.

No compare match

with TRCGRC regi ster,

so “L” outp ut continues

m+1

m: TRCG RA register setting value

n: TRCGRB register setting value

p: TRCGRC register setting value

R8C/34C Group 19. Timer RC

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 301 of 723

19.8 Timer RC Interrupt

Timer RC generates a timer RC interrupt request from five sources. The timer RC interrupt uses the single TRCIC

Table 19.15 lists the Registers Associated with Timer RC Interrupt, and Figure 19.20 is a Timer RC Interrupt Block

Diagram.

Figure 19.20 Timer RC Interrupt Block Diagram

Like other maskable interrupts, the timer RC interru pt is controlled by the combination of the I flag, IR bit, bits

ILVL0 to ILVL2, and IPL. However, it differs from other maskable interrupts in the following respects because

a single interrupt source (timer RC interrupt) is generated from multiple interrupt request sources.

• The IR bit in the TRCIC register is set to 1 (interrupt requested) when a bit i n the TRCSR register is set to 1

and the corresponding bit in the TRCIER register is also set to 1 (in terrupt enabled).

• The IR bit is set to 0 (no interrupt requ ested) when the bit in th e TRCSR register or the corresponding bit in

the TRCIER registe r is set to 0, or both are set to 0. In other words, the interrupt request is not main tained if

the IR bit is once set to 1 but the interrupt is not acknowledged.

• If another interrupt source is triggered after the IR bit is set to 1, the IR bit remains set to 1 and does not

change.

• If multiple bits in the TRCIER register are set to 1, use the TRCSR register to determine the source of the

interrupt request.

• The bits in the TRCSR register are not automatically set to 0 wh en an interrupt is acknowledged. Set t hem to

0 within the interrupt routine. Refer to 19.2.5 Timer RC Status Register (TRCSR), for the procedure for

setting these bits to 0.

Refer to 19.2.4 Timer RC Interrupt Enable Register (TRCIER), for details of the TRCIER register.

Refer to 11.3 Interrupt Control, for details of the TRCIC register and 11.1.5.2 Relocatable Vector Tables ,

for information on interrupt vectors.

Table 19.15 Registers Associated with Timer RC Interrupt

Timer RC Status Register Timer RC Interr upt Enable Register Timer RC Interrupt Con tr ol Re gist er

TRCSR TRCIER TRCIC

Timer RC interrupt request

(IR bit in TRCIC register)

IMFA bit

IMIEA bit

IMFB bit

IMIEB bit

IMFC bit

IMIEC bit

IMFD bit

IMIED bit

OVF bit

OVIE bit

IMFA, IMFB, IMFC, IMFD, OVF: Bits in TRCSR register

IMIEA, IMIEB, IMIEC, IMIED, OVIE: Bits in TRCIER register

R8C/34C Group 19. Timer RC

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 302 of 723

19.9 Notes on Timer RC

19.9.1 TRC Register

•The following note applies when the CCLR bit in the TRCCR1 register is set to 1 (clear TRC register at

compare match with TRCGRA register).

When using a program to write a value to the TRC register while the TSTART bit in the TRCMR register is

set to 1 (count starts), ensure that the write does not overlap with the timing with which the TRC register is set

to 0000h.

If the timing of the write t o the TRC register and the sett ing of the TRC reg ister to 0000h coincid e, the write

value will not be written to the TRC register and the TRC register will be set to 0000h.

•Reading from the TRC register immediately after writing to it can result in the value previous to the write

being read out. To prevent this, execute the JMP.B instruction between the read and the write instructions.

Program Example MOV.W #XXXXh, TRC ;W rite

JMP.B L1 ;JMP.B instruction

L1: MOV.W TRC,DATA ;Read

19.9.2 TRCSR Register

Reading from the TRCSR register immediately after writing to it can result in the value previous to the write

being read out. To prevent this, execute the JMP.B instruction between the read and the write instructions.

Program Example MOV.B #XXh, TRCSR ;Write

JMP.B L1 ;JMP.B instruction

L1: MOV.B TRCSR,DATA ;Read

19.9.3 TRCCR1 Register

To set bits TCK2 to TCK0 in the TRCCR1 register to 111b (fOCO-F), set fOCO-F to the clock frequency

higher than the CPU clock frequency.

19.9.4 Count Source Switching

•Stop the count before switching the count source.

Switching procedure

(1) Set the TSTART bit in the TRCMR register to 0 (count stops).

(2) Change the settings of bits TCK2 to TCK0 in the TRCCR1 register.

•After switching the count source from fOCO40M to another clock, allow a minimum of two cycles of f1 to

elapse after changing the clock setting before stopping fOCO40M.

Switching procedure

(1) Set the TSTART bit in the TRCMR register to 0 (count stops).

(2) Change the settings of bits TCK2 to TCK0 in the TRCCR1 register.

(3) Wait for a minimum of two cycles of f1.

(4) Set the FRA00 bit in the FRA0 register to 0 (high-speed on-chip oscillator off).

R8C/34C Group 19. Timer RC

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 303 of 723

•After switching the count source fro m fOCO-F to fOCO40M, allow a minimum of two cy cles of fOCO-F to

elapse after changing the clock setting before stopping fOCO-F.

Switching procedure

(1) Set the TSTART bit in the TRCMR register to 0 (count stops).

(2) Change the settings of bits TCK2 to TCK0 in the TRCCR1 register.

(3) Wait for a minimum of two cycles of fOCO-F.

(4) Set the FRA00 bit in the FRA0 register to 0 (high-speed on-chip oscillator off).

•After switching the count source from fOCO-F to a clock other than fOCO40M, allow a minimum of one

cycle of fOCO-F + fOCO40M to elapse after changing the clock setting before stoppin g fOCO-F.

Switching procedure

(1) Set the TSTART bit in the TRCMR register to 0 (count stops).

(2) Change the settings of bits TCK2 to TCK0 in the TRCCR1 register.

(3) Wait for a minimum of one cycle of fOCO-F + fOCO40M.

(4) Set the FRA00 bit in the FRA0 register to 0 (high-speed on-chip oscillator off).

19.9.5 Input Capture Function

•Set the pulse width of the input capture signal as follow s:

[When the digital filter is not used]

Three or more cycles of the timer RC operation clock (refer to Table 19.1 Timer RC Operation Clock)

[When the digital filter is used]

Five cycles of the digital filter sampling clock + three cycles of the timer RC operating clock, minimum (refer

to Figure 19.5 Digital Filter Bloc k Di agram)

•The value of the TRC register is transferred to the TRCGRj register one or two cycles of the timer RC

operation clock after the inpu t capture signal is i nput to the TRCIOj (j = A, B, C, or D) pi n (when the digi tal

filter function is not used).

19.9.6 TRCMR Register in PWM2 Mode

When the CSEL bit in the TRCCR2 register is set to 1 (count stops at compare match with the TRCGRA

19.9.7 Count Source fOCO40M

The count source fOCO40M can be used with supply voltage VCC = 2.7 to 5.5 V. For supply voltage other than

that, do not set bits TCK2 to TCK0 in the TRC CR1 register to 110b (select fOCO40M as the count source).

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 304 of 723

20. Timer RD

Timer RD has 2 16-bit timers (timer RD0 and timer RD1).

20.1 Overview

Timer RDi (i=0 or 1) has 4 I/O pins.

The operation clock of timer RD is f1, fOCO40M or fOCO-F. Table 20.1 lists the Timer RD Operation Clocks.

Figure 20.1 shows a Timer RD Block Diagram, and Table 20.2 lists Pin Configuration of Timer RD.

Timer RD has 5 modes:

• Timer mode

- Input capture function Transfer the counter value to a register with an external signal as the

trigger

- Output compare function Detect register value matches with a counter

(Pin output can be changed at detection)

The following 4 modes use the output compare function.

• PWM mode O utput pulse of any width continuously

• Reset synchronous PWM mode Output three-phase waveforms (6) without sawtooth wave modulation and

dead time

• Complementary PWM mode Output three-phase waveforms (6) with triangular wave modulation and

dead time

• PWM3 mode Output PWM waveform s (2) wi th a fixed period

In the input capture function, output compare function, and PWM mode, timer RD0 and timer RD1 have the

equivalent functions, and functions or modes can be selected individually for each pin. Also, a combination of

these functions and modes can be used in timer RDi.

In reset synchronous PWM mode, complementary PWM mode, and PW M3 mode, a waveform is output with a

combination of counters and registers in timer RD0 and timer RD1.

Table 20.1 Timer RD Operation Clocks

Condition Operation Clock of Timer RD

The count source is f1, f2, f4, f8, f32, fC2, or TRDCLK input

(bits TCK2 to TCK0 in registers TRDCR0 and TRDCR1 are set to a value from 000b

to 101b).

The count source is fOCO40M

(bits TCK2 to TCK0 in registers TRDCR0 and TRDCR1 are set to 110b). fOCO40M

The count source is fOCO-F

(bits TCK2 to TCK0 in registers TRDCR0 and TRDCR1 are set to 111b). fOCO-F

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 305 of 723

Figure 20.1 Timer RD Block Diagram

Table 20.2 Pin Configuration of Timer RD

Pin Name Assigned Pin I/O Function

TRDIOA0/TRDCLK P2_0 I/O Function varies according to the mode. Refer

to descriptions of individua l m odes for details.

TRDIOB0 P2_2 I/O

TRDIOC0 P2_1 I/O

TRDIOD0 P2_3 I/O

TRDIOA1 P2_4 I/O

TRDIOB1 P2_5 I/O

TRDIOC1 P2_6 I/O

TRDIOD1 P2_7 I/O

TRDi register

Da ta b us

TRDGRAi register

TRDGRBi register

TRDGRCi regist er

TRDGRDi regist er

TRDCRi register

TRDIORAi register

TRDIORCi register

TRDSRi register

TRDIERi register

TRDPOCRi register

TRDECR register

TRDADCR register

TRDSTR register

TRDMR register

TRDPMR register

TRDFCR register

TRDOER1 register

Timer RD control

circuit

INT0

TRDIOA0/TRDCLK (1)

TRDIOB0 (1)

TRDIOC0 (1)

TRDIOD0 (1)

TRDIOB1 (2)

TRDIOC1 (2)

TRDIOD1 (2)

TRDIOA1 (2)

Count source

select circui t

f1, f2, f4, f8, f32, fC2

fOCO40M, fOCO-F

Timer RD0 interrupt

request

Timer RD1 interrupt

request

A/D trigger

Timer RDi

i = 0 or 1

TRDDFi register

TRDOER2 register

TRDOCR regist er

Notes

1: The TRDPSR0 register is us ed to select which pin is assigned.

2: The TRDPSR1 register is us ed to select which pin is assigned.

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 306 of 723

20.2 Common Items for Multiple Modes

20.2.1 Count Sources

The count source selection method is the same in all modes. However, fC2 cannot be selected in PWM, reset

synchronous PWM, complem entary PWM, or PWM3 mode. The external clock cannot b e selected in PWM3

mode.

i = 0 or 1

Note:

1. The count source fOCO40M can be used with VCC = 2.7 to 5.5 V.

Figure 20.2 Block Diagram of Count Source

Set the pulse width of the external clock which inputs to the TRDCLK pin to 3 cycles or above of the operation

clock of timer RD (refer to Table 20.1 Timer RD Operation Clocks).

When selecting fOCO40M or fOCO-F for the count source, set the FRA00 bit in the FRA0 register to 1 (high-

speed on-chip oscillator on) before setting bits TCK2 to TCK0 in the TRDCRi (i = 0 or 1) register to 110b

(fOCO40M) or 111b (fOCO-F).

Table 20.3 Count Source Selection

Count Source Selection

f1, f2, f4, f8, f32 The count source is selected by bits TCK2 to TCK0 in the TRDCRi register.

fOCO40M (1)

fOCO-F The FRA00 bit in the FRA0 register is set to 1 (high-speed on-chip oscillator

frequency).

Bits TCK2 to TCK0 in the TRDCRi register is set to 110b (fOCO40M).

Bits TCK2 to TCK0 in the TRDCRi register is set to 111b (fOCO-F).

fC2 Bits TCK2 to TCK0 in the TRDCRi register is set to 101b (TRDCLKi input or fC2)

The ITCLKi bit in the TRDECR register is set to 1 (fC2)

External signal input

to TRDCLK pin The STCLK bit in the TRDFCR register is set to 1 (external clock input enabled).

Bits TCK2 to TCK0 in the TRDCRi register are set to 101b

(count source: external clock).

The valid edge is selected by bits CKEG1 to CKEG0 in the TRDCRi register.

The PD2_0 bit in the PD2 register is set to 0 (input mode).

TRDCLK/

TRDIOA0

TCK2 to TCK0

TRDi register

ITCLK0, ITCLK1: Bits in TRDECR register

TCK2 to TCK0, CKEG1 to CKEG 0: Bits in TRDCRi register

STCLK: Bit in TRDFCR register

f32

= 001b

= 010b

= 011b

= 000b

= 101b

= 100b

Valid edge

selected

CKEG1 to CKEG0

TRDIOA0 I/O or programmable I/O port

Count source

STCLK = 0

fOCO40M = 110b

ITCLKi = 0

STCLK = 1

ITCLKi = 1

fC2

fOCO-F = 111b

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 307 of 723

20.2.2 Buffer Operation

The TRDGRCi (i = 0 or 1) register can be used as the buffer register of the TRDGRAi register, and the

TRDGRDi register can be used as the buffer register of the TRDGRBi register by means of bits BFCi and BFDi

in the TRDMR register.

• TRDGRAi buffer register: TRDGRCi register

• TRDGRBi buffer register: TRDGRDi register

Buffer operation depends on the mode. Table 20.4 lists the Buffer Operation in Each Mode.

i = 0 or 1

Figure 20.3 Buffer Operation in Input Capture Function

Table 20.4 Buffer Operation in Each Mode

Function an d M od e Transfer Timi ng Transfer Register

Input capture function Input capture signal input Transfer content in TRDGRAi

(TRDGRBi) register to buffer register

Output compare function Compare match with TRDi register

and TRDGRAi (TRD GRBi) register Transfer content in buffer regis ter to

TRDGRAi (TRDGRB i) register

PWM mode

Reset synchronous PWM

mode Compare match withTRD0 register

and TRDGRA0 register Transfer content in buffer register to

TRDGRAi (TRDGRB i) register

Complementar y PWM

mode • Compare match with TRD0 register

and TRDGRA0 register

• TRD1 register unde rflow

Transfer content in buffer regis ter to

registers TRDGRB0, TRDGRA1, and

TRDGRB1

PWM3 mode Compare match with TRD0 register

and TRDGRA0 register Transfer content in buffer register to

registers TRDGRA0, TRDGRB0,

TRDGRA1, and TRDGRB1

Transfer

TRDGRAi register

n-1 n+1

TRDIOAi in pu t

TRDi register

i = 0 or 1

The above applies under the following conditions:

• The BFCi bit in the TRDMR register is set to 1 (the TRDGRCi register is used as the buffer register of

the TRDGRAi register).

• Bits IOA2 to IOA0 in the TRDIORAi register are set to 100b (input capture at the falling edge).

Transfer

TRDGRCi register

(buffer)

TRDGRCi register

(buffer) TRDGRAi

TRDIOAi input

(input capture signal)

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 308 of 723

Figure 20.4 Buffer Operation in Output Compare Function

Perform the following for the timer mode (inpu t capture and output compare functions).

When using the TRDGRCi (i = 0 or 1) register as the buffer register of the TRDGRAi register

• Set the IOC3 bit in the TRDIORCi register to 1 (g eneral register or buffer register).

• Set the IOC2 bit in the TRDIORCi register to the same value as the IOA2 bit in the TRDIORAi register.

When using the TRDGRDi register as the buffer register of the TRDGRBi register

• Set the IOD3 bit in the TRDIORCi regist er to 1 (g eneral register or buffer register).

• Set the IOD2 bit in the TRDIORCi register to the same value as the IOB2 bit in the TRDIORAi register.

Bits IMFC and IMFD in the TRDSRi register are set to 1 at the input edge of the TRDIOCi pin when also using

registers TRDGRCi and TRDGRDi as the buffer register in the in put capture function.

When also using registers TRDGRCi an d TRDGRDi as bu ffer registers for the outp ut compare function , reset

synchronous PWM mode, complementary PWM mode, and PWM3 mode, bits IMFC and IMFD in the TRDSRi

mnTRDGRAi register

m-1 m+1

TRDi register

i = 0 or 1

The above applies under the following conditions:

• BFCi bit in the TRDMR register is set to 1 (the TRDGRCi register is used as the buffer register of

the TRDGRAi register).

• Bits IOA2 to IOA0 in the TRDIORAi register are set to 001b (“L” output by the compare match).

Transfer

TRDGRCi register

(buffer)

TRDIOAi output

TRDGRCi register

(buffer) TRDGRAi

Compare match signal

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 309 of 723

20.2.3 Synchronous Operation

The TRD1 register is synchronized with the TRD0 register.

• Synchronous preset

When the SYNC bit in the TRDMR register is set to 1 (synchronous operation), the data is written to both the

TRD0 and TRD1 registers after writing to the TRDi register.

• Synchronous clear

When the SYNC bit in the TRDMR register is set to 1 and bits CCLR2 to CCLR0 in the TRDCRi register are

set to 011b (synchronous clear), the TRD0 register is set to 0000h at the same time as the TRD1 register is set

to 0000h.

Also, when the SYNC bit in the TRDMR register is set to 1 and bits CCLR2 to CCLR0 in the TRDCRi

Figure 20.5 Synchronous Operation

Value in

TRD0 register

TRDIOA0 input

nn is set

n writing

Value in

TRD1 register

Set to 0000h with TRD0 register

Set to 0000h by input capture

The above applies under the following conditions:

• The SYNC bit in the TRDMR register is set to 1 (synchronous operation).

• Bits CCLR2 to CCLR0 in the TRDCR0 register are set to 001b (set the TRD0 register to 0000h in input capture).

Bits CCLR2 to CCLR0 in the TRDCR1 register are set to 011b (set the TRD1 register to 0000h synchronizing with

the TRD0 register).

• Bits IOA2 to IOA0 in the TRDIORA0 register are set to 100b.

• Bits CMD1 to CMD0 in the TRDFCR register are set to 00b. (Input capture at the rising edge of the TRD IOA0 in put)

The PWM 3 bit in the TRDFCR register is set to 1.

n is set

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 310 of 723

20.2.4 Pulse Output Forced Cutoff

In the output compare function , PWM mode, reset synchrono us PWM mo de, complem entary PWM mo de, and

PWM3 mode, the TRDIOji (i = 0 or 1, j = A, B, C, or D) output pin can be forcibly set to a programmable I/O

port by the INT0 pin input, and pulse output can be cu t off.

The pins used for output in these functions or modes can function as the out put pin of timer RD when the

applicable bit in the TRDOER1 register is set to 0 (enable timer RD output). When the PTO bit in the

TRDOER2 register to 1 (pulse output forced cutoff signal input INT0 enabled), all bits in the TRDOER1

after “L” is applied to the INT0 pin. The TRDIOji outpu t pin is set to the p rogrammable I/ O port after “L” is

applied to the INT0 pin and waiting for 1 to 2 cycles of the timer RD operation clock (refer to Table 20.1

Timer RD Operation Clocks).

Make the following settings to use this function:

• Set the pin status (high impedance, “L” or “H” output) to pulse output forced cutoff by registers P2 and PD2.

• Set the INT0EN bit in the INTEN register to 1 (INT0 inpu t enab led) and th e IN T0PL b it to 0 (one edge), and

set the POL bit in the INT0IC register to 0 (falling edge selected).

• Set the PD4_5 bit in the PD4 register to 0 (input mode).

• Set the INT0 digital filter by bits INT0F1 to INT0F0 in the INTF register.

• Set the PTO bit in the TRDOER2 register to 1 (pulse output forced cutoff signal input INT0 enabled).

The IR bit in the INT0IC register is set to 1 (interrupt requested) in accordance with the setting of the POL bit in

the INT0IC register and the INT0PL bit in the INTEN register and a change in the INT0 pin input (refer to 11.8

Notes on Int er r upts).

For details on interrupts, refer to 11. Interrupts.

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 311 of 723

Figure 20.6 Pulse Output Forced Cutoff

INT0 input TRDIOA0

PTO bit

EA0 bit

TRDIOB0

EB0 bit

TRDIOC0

EC0 bit

TRDIOD0

ED0 bit

TRDIOA1

EA1 bit

TRDIOB1

EB1 bit

TRDIOC1

EC1 bit

TRDIOD1

ED1 bit

Port P2_0

output data

Port P2_0

input data

Port P2_2

output data

Port P2_2

input data

Port P2_1

output data

Port P2_1

input data

Port P2_3

output data

Port P2_3

input data

Port P2_4

output data

Port P2_4

input data

Port P2_5

output data

Port P2_5

input data

Port P2_6

output data

Port P2_6

input data

Port P2_7

output data

Port P2_7

input data

PTO: Bit in TRDOER2 register

EA0, EB0, EC0, ED0, EA1, EB1, EC1, ED1: Bits in TRDOER1 register

EA0 bit

writing value

EB0 bit

writing value

EC0 bit

writing value

ED0 bit writing

value

EA1 bit w riting

value

EB1 bit writing

value

EC1 bit

writing value

ED1 bit

writing value

Timer RD

output data

Timer RD

output data

Timer RD

output data

Timer RD

output data

Timer RD

output data

Timer RD

output data

Timer RD

output data

Timer RD

output data

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 312 of 723

20.3 Input Capture Function

The input capture function measures the external signal width and period. The content of the TRDi register

(counter) is transferred to the TRDGRji register as a trigger of the TRDIOji (i = 0 or 1, j = A, B, C, or D) pin

external signal (input capture). Since this function is enabled with a combination of the TRDIOji pin and TRDGRji

The TRDGRA0 register can also select fOCO128 si gnal as inpu t-capture trigger input.

Figure 20.7 show s a Block Diagram of Input Capture Functi on, Table 20.5 lists the Inpu t Capture Function

Specifications. Figure 20.8 shows an Operat ing Example of Input Capture Function.

Figure 20.7 Block Diagram of Input Capture Function

i = 0 or 1

Notes 1: When the BFCi bit in the TRDMR register is set to 1 (the TRDGRCi register is used as the buffer register of

the TRDGRAi regis t e r).

2: When the B F Di bi t i n the TR DM R regi s t e r is s et t o 1 (th e TRDG RDi reg ister is use d as t he buf f e r regi s t er of

the TRDGRBi regis t e r).

3: The trigger input of the TRDGRA0 register can select the TRDIOA0 pin input or fOCO128 signal.

TRDGRAi

Input capture signal

TRDGRCi

TRDGRBi

Input capture signal

TRDGRDi

TRDIOBi

(Note 1)

(Note 2)

TRDIOCi

TRDIODi

Input capture signal

Divided

by 128 IOA3 = 0

IOA3 = 1

fOCO-S

fOCO-F

fOCO128

TRDIOAi (3) Edge

selection

Only TRDGRA0 available

Edge

selection

Edge

selection

Edge

selection

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 313 of 723

i = 0 or 1, j = A, B, C, or D

Table 20.5 Input Capture Function Specifications

Item Specification

Count sources f1, f2, f4, f8, f32, fC2, fOCO40M, fOCO-F

External signal input to th e TR DCL K pin (va lid edg e selected by a

program)

Count operations Increment

Count period When bits CCLR2 to CCLR0 in the TRDCRi register are set to 000b

(free-running op eration).

1/fk × 65536 fk: Frequency of count source

Count start condition 1 (count starts) is written to the TSTARTi bit in the TRDSTR register.

Count stop condition 0 (count stops) is written to the TSTARTi bit in the TRDSTR register

when the CSELi bit in the TRDSTR register is set to 1.

Interrupt request generation

timing • Input capture (valid edge of TRDIOji input or fOCO128 signal edge)

• TRDi register overflows

TRDIOA0 pin function Programmable I/O port, input-capture input, or TRDCLK (external clock)

input

TRDIOB0, TRDIOC0,

TRDIOD0, TRDIOA1 to

TRDIOD1 pin functions

Programmable I/O port, or input-capture input (selectable by pin)

INT0 pin function Programmable I/O port or INT0 interrupt input

Read from timer The cou n t valu e ca n be rea d by rea ding the TRDi register.

Write to timer • When the SYNC bit in the TRDMR register is set to 0 (timer RD0 and

timer RD1 operate independently).

Data can be written to the TRDi register.

• When the SYNC bit in the TRDMR register is set to 1 (timer RD0 and

timer RD1 operate synchronously).

Data can be written to both the TRD0 and TRD1 registers by writing to

the TRDi register.

Selectable functions • Input-capture input pin selection

Either 1 pin or multiple pins among TRDIOAi, TRDIOBi, TRDIOCi, or

TRDIODi.

• Input-capture input valid edge selection

The rising edge, falling edge, or both the rising and falling edges

• Timing for setting the TRDi register to 0000h

At overflow or input capture

• Buffer operation (Refer to 20.2.2 Buffer Operation.)

• Synchronous operation (Refer to 20.2.3 Synchronous Operation.)

• Digital filter

The TRDIOji input is sampled, and when the sampled input level match

as 3 times, the level is determined.

• Input-capture trigger selection

fOCO128 can be selected for input-capture trigger input of the

TRDGRA0 register.

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 314 of 723

20.3.1 Module Standby Control Register (MSTCR)

Notes:

1. When the MSTIIC bit is set to 1 (standby), any access to the SSU or the I2C bus associated registers (addresses

0193h to 019Dh) is disabled.

2. When the MSTTRD bi t is set to 1 (stand by), any acce ss to the ti mer RD associated regi sters (addresse s 0135h

to 015Fh) is disabled.

3. To set the MSTTRD bit to 1 (standby), set bits TCK2 to TCK0 in the TRDCRi (i = 0 or 1) register to 000b (f1).

4. When the MSTTRC bi t is set to 1 (stand by), any acce ss to the time r RC associated registers (addresses 0120h

to 0133h) is disabled.

20.3.2 Timer RD Control Expansion Register (TRDECR)

Note:

1. Enabled when in time r mode.

Address 0008h

Bitb7b6b5b4b3b2b1b0

Symbol — — MSTTRC MSTTRD MSTIIC — — —

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b1 —

b2 —

b3 MSTIIC SSU, I2C bus standby bit 0: Active

1: Standby (1) R/W

b4 MSTTRD Timer RD standby bit 0: Active

1: Standby (2, 3) R/W

b5 MSTTRC Timer RC standby bit 0: Active

1: Standby (4) R/W

b6 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b7 —

Address 0135h

Bitb7b6b5b4b3b2b1b0

Symbol ITCLK1 — — — ITCLK0 — — —

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b1 —

b2 —

b3 ITCLK0 Timer RD0 fC2 select bit 0: TRDCLK input selected

1: fC2 selected (1) R/W

b4 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b5 —

b6 —

b7 ITCLK1 Timer RD1 fC2 select bit 0: TRDCLK input selected

1: fC2 selected (1) R/W

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 315 of 723

20.3.3 Timer RD Start Register (TRDSTR) in Input Capture Function

Set the TRDSTR register using the MOV instruction (do not use the bi t handling instruction). Refer to 20.10.1

TRDSTR Register of Notes on Timer RD.

20.3.4 Timer RD Mode Register (TRDMR) in Input Capture Function

Address 0137h

Bitb7b6b5b4b3b2b1b0

Symbol — — — — CSEL1 CSEL0 TSTART1 TSTART0

After Reset11111100

Bit Symbol Bit Name Function R/W

b0 TSTART0 TRD0 count start flag 0: Count stops

1: Count starts R/W

b1 TSTART1 TRD1 count start flag R/W

b2 CSEL0 TRD0 count operation select bit Set to 1 in the input capture function. R/W

b3 CSEL1 TRD1 count operation select bit R/W

b4 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. —

b5 —

b6 —

b7 —

Address 0138h

Bitb7b6b5b4b3b2b1b0

Symbol BFD1 BFC1 BFD0 BFC0 — — — SYNC

After Reset00001110

Bit Symbol Bit Name Function R/W

b0 SYNC Timer RD synchronous bit 0: Registers TRD0 and TRD1 operate

independently

1: Registers TRD0 and TRD1 operate

synchronously

R/W

b1 — Nothing is assig ned. If necessary, set to 0.

When read, the content is 1. —

b2 —

b3 —

b4 BFC0 TRDGRC0 register function select bit 0: General register

1: Buffer register of TRDGRA0 register R/W

b5 BFD0 TRDGRD0 register function select bit 0: General register

1: Buffer register of TRDGRB0 register R/W

b6 BFC1 TRDGRC1 register function select bit 0: General register

1: Buffer register of TRDGRA1 register R/W

b7 BFD1 TRDGRD1 register function select bit 0: General register

1: Buffer register of TRDGRB1 register R/W

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 316 of 723

20.3.5 Timer RD PWM Mode Register (TRDPMR) in Input Capture Function

20.3.6 Timer RD Function Control Register (TRDFCR) in Input Capture Function

Notes:

1. Set bits CMD1 to CMD0 when both the TS TART 0 and TSTART1 bits in the TRDSTR register are set to 0 (count

stops).

2. When bits CMD1 to CMD0 are set to 00b (timer mode, PWM mode, or PWM3 mode), the setting of the PWM3 bit

is enabled.

Address 0139h

Bitb7b6b5b4b3b2b1b0

Symbol — PWMD1 PWMC1 PWMB1 — PWMD0 PWMC0 PWMB0

After Reset10001000

Bit Symbol Bit Name Function R/W

b0 PWMB0 PWM mode of TRDIOB0 select bit Set to 0 (timer mode) in the input capture function. R/W

b1 PWMC0 PWM mode of TRDIOC0 select bit R/W

b2 PWMD0 PWM mode of TRDIOD0 select bit R/W

b3 — Nothing is assig ned. If necessary, set to 0. When read, the content is 1. —

b4 PWMB1 PWM mode of TRDIOB1 select bit Set to 0 (timer mode) in the input capture function. R/W

b5 PWMC1 PWM mode of TRDIOC1 select bit R/W

b6 PWMD1 PWM mode of TRDIOD1 select bit R/W

b7 — Nothing is assig ned. If necessary, set to 0. When read, the content is 1. —

Address 013Ah

Bitb7b6b5b4b3b2b1b0

Symbol PWM3 STCLK ADEG ADTRG OLS1 OLS0 CMD1 CMD0

After Reset10000000

Bit Symbol Bit Name Function R/W

b0 CMD0 Combination mode select bit (1) Set to 00b (timer mode, PWM mode, or PWM3

mode) in the input capture function. R/W

b1 CMD1 R/W

b2 OLS0 Normal-ph ase output level select bit

(in reset synchronous PWM mode or

complementary PWM mode)

This bit is disabled in the input capture function. R/W

b3 OLS1 Coun ter-phase output level select bit

(in reset synchronous PWM mode or

complementary PWM mode)

R/W

b4 ADTRG A/D trigger enable bit

(in complementary PWM mode) R/W

b5 ADEG A/D trigger edge select bit

(in complementary PWM mode) R/W

b6 ST CLK External clock input select bit 0: External clock input disabled

1: External clock input enabled R/W

b7 PWM3 PWM3 mode select bit (2) Set this bit to 1 (other than PWM3 mode) in the

input capt ure function. R/W

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 317 of 723

20.3.7 Timer RD Digital Filter Function Select Register i (TRDDFi) (i = 0 or 1) in

Input Capture Function

Address 013Eh (TRDDF0), 013Fh (TRDDF1)

Bitb7b6b5b4b3b2b1b0

Symbol DFCK1 DFCK0 — — DFD DFC DFB DFA

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 DFA TRDIOA pin digital filter function select

bit 0: Functi on is not used

1: Function is use d R/W

b1 DFB TRDIOB pin digital filter function select

bit R/W

b2 DFC TRDIOC pin digital filter function select

bit R/W

b3 DFD TRDIOD pin digital filter function select

bit R/W

b4 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b5 —

b6 DFCK0 Clock select bits for digital fi lter function b7 b6

0 0: f32

0 1: f8

1 0: f1

1 1: Count source (clock selected by bits TCK2

to TCK0 in the TRDCRi register)

R/W

b7 DFCK1 R/W

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 318 of 723

20.3.8 Timer RD Control Register i (TRDCRi) (i = 0 or 1) in Input Capture Function

Notes:

1. Enabled when the ITCLKi bit in the TRDECR register is set to 0 (TRDCLK input) and the STCLK bit in the

TRDFCR register is 1 (external clock input enabled).

2. Enabled when the ITCLKi bit in the TRDECR register is set to 1 (fC2) in timer mode.

3. Enabled when bits TCK2 to TCK0 are set to 101b (TRDCLK input or fC2), the ITCLKi bit in the TRDECR is set to

0 (TRDCLK input), and the STCLK bit in the TR DFCR register is set to 1 (external clock input enabled).

4. This setting is en able d when th e SYNC bit in the T RDMR re gister i s set to 1 (registers T RD0 and TR D1 operate

synchronously).

5. To select fOCO-F, set it to the clock frequency higher than the CPU clock frequency.

Address 0140h (TRDCR0), 015 0h (TRDCR1)

Bitb7b6b5b4b3b2b1b0

Symbol CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TCK2 TCK1 TCK0

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 TCK0 Count source select bit b2 b1 b0

0 0 0: f1

0 0 1: f2

0 1 0: f4

0 1 1: f8

1 0 0: f32

1 0 1: TRDCLK input (1) or fC2 (2)

1 1 0: fOCO40M

1 1 1: fOCO-F (5)

R/W

b1 TCK1 R/W

b2 TCK2 R/W

b3 CKEG0 External clock edge select bit (3) b4 b3

0 0: Count at the rising edge

0 1: Count at the falling edge

1 0: Count at both edges

1 1: Do not set.

R/W

b4 CKEG1 R/W

b5 CCLR0 TRDi counter clear select bit b7 b6 b5

0 0 0: Disable clear (free-running ope ra ti on )

0 0 1: Clear by input capture in the TRDGRAi register

0 1 0: Clear by input capture in the TRDGRBi register

0 1 1: Synchronous clear (clear simultaneously with

other timer RDi counter) (4)

1 0 0: Do not set.

1 0 1: Clear by input capture in the TRDGRCi register

1 1 0: Clear by input capture in the TRDGRDi register

1 1 1: Do not set.

R/W

b6 CCLR1 R/W

b7 CCLR2 R/W

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 319 of 723

20.3.9 Timer RD I/O Control Register Ai (TRDIORAi) (i = 0 or 1) in Input Capture

Function

Notes:

1. To select 1 (the TRDGRCi register is used as a buffer register of the TRD GRAi register) for this bit by the BFCi

bit in the TRDMR re gister, set the IOC2 bit in the TRDIORCi register to the same value as the IOA2 bit in the

TRDIORAi register.

2. To select 1 (the TRDGRDi register is used as a buffer register of the TRD GRBi register) for this bit by the BFDi

bit in the TRDMR re gister, set the IOD2 bit in the TRDIORCi register to the same value as the IOB2 bit in the

TRDIORAi register.

3. The IOA3 bit is enabled in the TRDIORA0 register only. Set to the IOA3 bit in TRDIORA1 to 1.

4. The IOA 3 bi t i s ena b l ed wh e n th e IOA2 bit is set to 1 (input capture function).

Address 0141h (TRDIORA0), 0151h (TRDIORA1)

Bitb7b6b5b4b3b2b1b0

Symbol— IOB2IOB1IOB0IOA3IOA2IOA1IOA0

After Reset10001000

Bit Symbol Bit Name Function R/W

b0 IOA0 TRDGRA control bit b1 b0

0 0: Input capture to the TRDGRAi register at the

rising edge

0 1: Input capture to the TRDGRAi register at the

falling edge

1 0: Input capture to the TRDGRAi register at both

edges

1 1: Do not set.

R/W

b1 IOA1 R/W

b2 IOA2 TRDGRA mode select bit (1) Set to 1 (input capture) in the input capture functi on. R/W

b3 IOA3 Input capture input switch bit (3, 4) 0: fOCO128 Signal

1: TRDIOA0 pin input R/W

b4 IOB0 TRDGRB control bit b5 b4

0 0: Input capture to the TRDGRBi register at the

rising edge

0 1: Input capture to the TRDGRBi register at the

falling edge

1 0: Input capture to the TRDGRBi register at both

edges

1 1: Do not set.

R/W

b5 IOB1 R/W

b6 IOB2 TRDGRB mode select bit (2) Set to 1 (input capture) in the input capture functi on. R/W

b7 — Nothing is assig ned. If necessary, set to 0. When read, the content is 1. —

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 320 of 723

20.3.10 Timer RD I/O Control Register Ci (TRDIORCi) (i = 0 or 1) in Input Capture

Function

Notes:

1. To select 1 (the TRDGRCi register is used as a buffer register of the TRD GRAi register) for this bit by the BFCi

bit in the TRDMR re gister, set the IOC2 bit in the TRDIORCi register to the same value as the IOA2 bit in the

TRDIORAi register.

2. To select 1 (the TRDGRDi register is used as a buffer register of the TRD GRBi register) for this bit by the BFDi

bit in the TRDMR re gister, set the IOD2 bit in the TRDIORCi register to the same value as the IOB2 bit in the

TRDIORAi register.

Address 0142h (TRDIORC 0), 0152h (TRDIORC1)

Bitb7b6b5b4b3b2b1b0

Symbol IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0

After Reset10001000

Bit Symbol Bit Name Function R/W

b0 IOC0 TRDGRC control bit b1 b0

0 0: Input capture to the TRDGRCi register at the

rising edge

0 1: Input capture to the TRDGRCi register at the

falling edge

1 0: Input capture to the TRDGRCi register at both

edges

1 1: Do not set.

R/W

b1 IOC1 R/W

b2 IOC2 TRDGRC mode select bit (1) Set to 1 (input capture) in th e input capture

function. R/W

b3 IOC3 TRDGRC register function select bit Set to 1 (general registe r or buffer register) in the

input capture function. R/W

b4 IOD0 TRDGRD control bit b5 b4

0 0: Input capture to the TRDGRDi register at the

rising edge

0 1: Input capture to the TRDGRDi register at the

falling edge

1 0: Input capture to the TRDGRDi register at both

edges

1 1: Do not set.

R/W

b5 IOD1 R/W

b6 IOD2 TRDGRD mode select bit (2) Set to 1 (input capture) in th e input capture

function. R/W

b7 IOD3 TRDGRD register function select bit Set to 1 (general registe r or buffer register) in the

input capture function. R/W

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 321 of 723

20.3.11 Timer RD Status Register i (TRDSRi) (i = 0 or 1) in Input Capture Function

Notes:

1. Nothing is assigned to b5 in the TRDSR0 register. When writing to b5, write 0. When reading, the content is 1.

2. The writing results are as follows:

• This bit is set to 0 when the read result is 1 and 0 is written to the same bit.

• This bit remains unchanged even if the read result is 0 and 0 is written to the same bit. (This bit remains 1 even

if it is set to 1 from 0 after reading, and writing 0.)

• This bit remains unchanged if 1 is written to it.

3. Edge selected by bits IOj1 to IOj0 (j = A or B) in the TRDIORAi register.

4. Edge selected by bits IOk1 to IOk0 (k = C or D) in the TRDIORCi register.

Including when the BFki bit in the TRDMR register is set to 1 (TRDGRki is used as the buffer register).

Address 0143h (TRDSR0), 0153h (TRDSR1)

Bitb7b6b5b4b3b2b1b0

Symbol — — UDF OVF IMFD IMFC IMFB IMFA

After Reset 1 1 1 0 0 0 0 0 TRDSR0 register

After Reset 1 1 0 0 0 0 0 0 TRDSR1 register

Bit Symbol Bit Name Function R/W

b0 IMFA Input capture / compare match flag A [Source for setting this bit to 0]

Write 0 after read (2).

[Source for setting th is bit to 1].

TRDSR0 register:

fOCO128 signal edge when the IOA3 bit in the

TRDIORA0 register is set to 0 (fOCO128 signal).

TRDIOA0 pin input edge when the IOA3 bit in the

TRDIORA0 register is set to 1 (TRDIOA0 input) (3).

TRDSR1 register:

Input edge of TRDIOA1 pin (3).

R/W

b1 IMFB Input capture / compare match flag B [Source for setting this bit to 0]

Write 0 after read (2).

[Source for setting th is bit to 1]

Input edge of TRDIOBi pin (3).

R/W

b2 IMFC Input capture / compare match flag C [Source for settin g this bit to 0]

Write 0 after read (2).

[Source for setting th is bit to 1]

Input edge of TRDIOCi pin (4).

R/W

b3 IMFD Input capture / compare match flag D [Source for settin g this bit to 0]

Write 0 after read (2).

[Source for setting th is bit to 1]

Input edge of TRDIODi pin (4).

R/W

b4 OVF Overflow flag [Source for setting this bit to 0]

Write 0 after read (2).

[Source for setting th is bit to 1]

When the TRDi register overflows.

R/W

b5 UDF Und erflow flag (1) This bit is disabled in the input capture function. R/W

b6 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. —

b7 —

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 322 of 723

20.3.12 Timer RD Interrupt Enable Register i (TRDIERi) (i = 0 or 1) in Input Capture

Function

20.3.13 Timer RD Counter i (TRDi) (i = 0 or 1) in Input Capture Function

Access the TRDi register in 16-bit units. Do not access it in 8-bit units.

Address 0144h (TRDIER0), 0154h (TRDIER1)

Bitb7b6b5b4b3b2b1b0

Symbol — — — OVIE IMIED IMIEC IMIEB IMIEA

After Reset11100000

Bit Symbol Bit Name Function R/W

b0 IMIEA Input capture/compare match interrupt

enable bit A 0: Disable interrupt (IMIA) by the IMFA bit

1: Enable interrupt (IMIA) by the IMFA bit R/W

b1 IMIEB Input capture/compare match interrupt

enable bit B 0: Disable interrupt (IMIB) by the IMFB bit

1: Enable interrupt (IMIB) by the IMFB bit R/W

b2 IMIEC Input capture/compare match interrupt

enable bit C 0: Disable interrupt (IMIC) by the IMFC bit

1: Enable interrupt (IMIC) by the IMFC bit R/W

b3 IMIED Input capture/compare match interrupt

enable bit D 0: Disable interrupt (IMID) by the IMFD bit

1: Enable interrupt (IMID) by the IMFD bit R/W

b4 OVIE Overflow/underflow interrupt enable

bit 0: Disable interrupt (OVI) by the OVF bit

1: Enable interrupt (OVI) by the OVF bit R/W

b5 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. —

b6 —

b7 —

Address 0147h to 0146h (TRD0), 0157h to 0156h (TRD1)

Bitb7b6b5b4b3b2b1b0

Symbol————————

After Reset00000000

Bit b15 b14 b13 b12 b11 b10 b9 b8

Symbol————————

After Reset00000000

Bit Function Setting Range R/W

b15 to b0 Count the count source. Coun t operation is incremented.

When an overflow occurs, the OVF bit in the TRDSRi register is set to 1. 0000h to FFFFh R/W

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 323 of 723

20.3.14 Timer RD General Registers Ai, Bi, Ci, and Di (TRDGRAi, TRDGRBi,

TRDGRCi, TRDGRDi) (i = 0 or 1) in Input Capture Function

Access registers TRDGRAi to TRDGRDi in 16-bit units. Do not access them in 8-bit units.

The following registers are disabled in the input capture function: TRDOER1, TRDOER2, TRDOCR,

TRDPOCR0, and TRDPOCR1.

i = 0 or 1, j = A, B, C, or D

BFCi, BFDi: Bits in TRDMR register

Set the pulse width o f the input captu re signal applied to the TRDIOji pin t o 3 cycles or more of t he timer RD

operation clock (refer to Table 2 0.1 Timer RD Operation Cl ocks) for no digital filter (the DFj bit in the

TRDDFi register set to 0).

Address 0149h to 0148h (TRDGRA0), 014Bh to 014Ah (TRDGRB0),

014Dh to 014Ch (TRDGRC0), 014Fh to 014Eh (TRDGRD0),

0159h to 0158h (TRDGRA1), 015Bh to 015Ah (TRDGRB1),

015Dh to 015Ch (TRDGRC1), 015Fh to 015Eh (TRDGRD1)

Bitb7b6b5b4b3b2b1b0

Symbol————————

After Reset11111111

Bit b15 b14 b13 b12 b11 b10 b9 b8

Symbol————————

After Reset11111111

Bit Function R/W

b15 to b0 Refer to Table 20.6 TRDGRji Register Functions in Input Capture Function R/W

Table 20.6 TRDGRji Register Functions in Input Capture Function

TRDGRAi −General register

The value in the TRDi register can be read at input

capture.

TRDIOAi

TRDGRBi TRDIOBi

TRDGRCi BFCi = 0 General register

The value in the TRDi register can be read at input

capture.

TRDIOCi

TRDGRDi BFDi = 0 TRDIODi

TRDGRCi BFCi = 1 Buffer register

The value in the TRDi register can be read at input

capture. (Refer to 20.2.2 Buffer Operation.)

TRDIOAi

TRDGRDi BFDi = 1 TRDIOBi

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 324 of 723

20.3.15 Timer RD Pin Select Register 0 (TRDPSR0)

The TRDPSR0 register selects which pin is assigned to the timer RD I/O. To use the I/O pin for timer RD, set

this register.

Set the TRDPSR0 register before setting the timer RD associated registers. Also, do not change the setting

value in this register during timer RD operation.

20.3.16 Timer RD Pin Select Register 1 (TRDPSR1)

The TRDPSR1 register selects which pin is assigned to the timer RD I/O. To use the I/O pin for timer RD, set

this register.

Set the TRDPSR1 register before setting the timer RD associated registers. Also, do not change the setting

value in this register during timer RD operation.

Address 0184h

Bitb7b6b5b4b3b2b1b0

Symbol — TRDIOD0SEL0 TRDIOC0SEL1 TRDIOC0SEL0 TRDIOB0SEL1 TRDIOB0SEL0 — TRDIOA0SEL0

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 TRDIOA0SEL0 TRDIOA0/TRDCLK pin select bit 0: TRDIOA0/TRDCLK pin not used

1: P2_0 assigned R/W

b1 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b2 TRDIOB0SEL0 TRDIOB0 pin select bit b3 b2

0 0: TRDIOB0 pin not used

0 1: Do not set.

1 0: P2_2 assigned

1 1: Do not set.

R/W

b3 TRDIOB0SEL1 R/W

b4 TRDIOC0SEL0 TRDIOC0 pin select bit b5 b4

0 0: TRDIOC0 pin not used

0 1: Do not set.

1 0: P2_1 assigned

1 1: Do not set.

R/W

b5 TRDIOC0SEL1 R/W

b6 TRDIOD0SEL0 TRDIOD0 pin select bit 0: TRDIOD0 pin not used

1: P2_3 assigned R/W

b7 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

Address 0185h

Bitb7b6b5b4b3b2b1b0

Symbol — TRDIOD1SEL0 — TRDIOC1SEL0 — TRDIOB1SEL0 — TRDIOA1SEL0

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 TRDIOA1SEL0 TRDIOA1 pin select bit 0: TRDIOA1 pin not used

1: P2_4 assigned R/W

b1 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b2 TRDIOB1SEL0 TRDIOB1 pin select bit 0: TRDIOB1 pin not used

1: P2_5 assigned R/W

b3 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b4 TRDIOC1SEL0 TRDIOC1 pin select bit 0: TRDIOC1 pin not used

1: P2_6 assigned R/W

b5 — Reserved bit Set to 0. R/W

b6 TRDIOD1SEL0 TRDIOD1 pin select bit 0: TRDIOD1 pin not used

1: P2_7 assigned R/W

b7 — Reserved bit Set to 0. R/W

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 325 of 723

20.3.17 Operating Example

Figure 20.8 Operating Example of Input Capture Func tion

Set to 0 by a program

Transfer

i = 0 or 1

The above applies under the following conditions:

Bits CCLR2 to CCLR0 in the TRDCRi register are set to 001b. (the TRDi regist er set to 0000h by TRDGRAi register input capture).

Bits TCK2 to TCK0 in the TRDCRi register are set to 101b (TRDCLK input for the count source).

Bits CKEG1 to CKEG0 in the TRDCRi register are set to 01b (count at the falling edge for the count source).

Bits IOA2 to IOA0 in the TRDIORAi register are set to 101b (input capture at the falling edge of the TRDIOAi input).

The BFCi bit in the TRDMR register is set to 1 (the TRDGRCi register is used as the buffer register of the TRDGRAi register).

Count value

in TRDi register

FFFFh

0009h

0006h

TSTARTi bit in

TRDSTR register 65536

TRDGRAi reg ister

0000h

TRDIOAi input

TRDGRCi regi s ter

IMFA bit in

TRDSRi register

OVF bit in

TRDSRi register

0009h0006h

0006h

TRDCLK input

count source

Transfer

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 326 of 723

20.3.18 Digital Filter

The TRDIOji (i = 0 or 1, j = A, B, C, or D) input is sampled, and when the sampled input level matches 3 times,

its level is determined. Select the digital filter function and sampl ing clo c k by the TRDDFi reg ister.

Figure 20.9 shows a Block Diagram of Digital Filter.

Figure 20.9 Block Diagram of Digital Filter

Clock period selected by

bits TCK2 to TCK0 or

bits DFCK1 to DFCK0

Sampling clock

TRDIOji input signal

Input signal th rough

digital filtering

Transmission ca nnot be

performed without 3-time match

because the in put signal is

assumed to be noise.

Signal transmission delayed

up to 5-sampli ng c lock

Recognition of the

signal change with

3-time match

i = 0 or 1, j = A, B, C, or D

ITCLK0, ITCL K1: Bits in TRDECR regist er

TCK0 to TCK2: Bit s i n TRDCRi register

DFCK0 to DFCK1 and DFj: Bits in TRDDF register

IOA0 to IOA2 and IOB0 to IOB2: Bits in TRDIORAi register

IOC0 to IOC3 and IOD0 to IOD3: Bits in TRDIORCi register

Latch

Match

detection

circuit

Edge detection

circuit

DFj

Sampling clock

IOA2 to IOA0

IOB2 to IOB0

IOC3 to IOC0

IOD3 to IOD0

TRDIOji input signal

Latch

Timer RD operation clock

f1, fOCO40M)

= 100b

= 011b

= 010b

= 001b

f32

f1 = 000b

= 101b

TRDCLK ITCLKi = 0

ITCLKi = 1

fC2

DFCK1 to DFCK0

f32

Count source

= 110b

fOCO40M = 00b

= 01b

= 10b

= 11b

= 111b

fOCO-F

TCK2 to TCK0

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 327 of 723

20.4 Output Compare Function

This function detects matches (compare match) between the content of the TRDGRji (j = A, B, C, or D) regi ster

and the content of the TRDi (i = 0 or 1) register. When the content matches, a user-set level is ou tput from the

TRDIOji pin. Since this fu nction is enabled with a combination of the TRDIOji pin and TRDGRji register, the

output compare function, or any other mode or function, can be selected for each individual pin. Figure 20.10

shows a Block Diagram of Output Compare Function, Table 20.7 lists the Output Compare Function

Specifications. Figure 20.11 shows an Operating Example of Output Compare Function.

Figure 20.10 Block Diagram of Output Compare Function

TRDIOA0 Output

control Comparator TRDGRA0

TRD0

TRDIOC0 Output

control Comparator TRDGRC0

Compare match signal

TRDIOB0 Output

control Comparator TRDGRB0

TRDIOD0 Output

control Comparator TRDGRD0

Timer RD0

TRDIOA1 Output

control Comparator TRDGRA1

TRD1

TRDIOC1 Output

control Comparator TRDGRC1

TRDIOB1 Output

control Comparator TRDGRB1

TRDIOD1 Output

control Comparator TRDGRD1

Timer RD1

Compare match signal

IOC3 = 0 in

TRDIORC0 register

IOC3 = 1

IOD3 = 0 in

TRDIORC0 register

IOD3 = 1

IOC3 = 0 in

TRDIORC1 register

IOC3 = 1

IOD3 = 0 in

TRDIORC1 register

IOD3 = 1

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 328 of 723

i = 0 or 1, j = A, B, C, or D

Table 20.7 Output Compare Function Specifications

Item Specification

Count sources f1, f2, f4, f8, f32, fC2, fOCO40M, fOCO-F

External signal input to the TRDCLK pin (valid edge selected by a program)

Count operations Increment

Count period • When bits CCLR2 to CCLR0 in the TRDCRi register are set to 000b (free-running

operation).

1/fk × 65536 fk: Frequency of count source

• Bits CCLR1 to CCLR0 in the TRDCRi register are set to 01b or 10b (set the TRDi

Frequency of count source x (n+1)

n: Setting value in the TRDGRji register

Waveform output timing Compare match

Count start condition 1 (count starts) is written to the TSTARTi bit in the TRDSTR register.

Count stop conditions • 0 (count stops) is written to the TSTARTi bit in the TRDSTR register when the

CSELi bit in the TRDSTR register is set to 1.

The output compare output pin holds output level before the count stops.

• Wh en the CSELi bit in the TRDSTR register is set to 0, the count stops at the

compare match in the TRDGRAi register.

The output compare output pin holds level after output change by the compare

match.

Interrupt request generation

timing • Compare match (The content of the TRDi register matches content of the TRDGRji

• TRDi register overflows

TRDIOA0 pin function Programmable I/O port, output-compare output, or TRDCLK (external clock) input

TRDIOB0, TRDIOC0,

TRDIOD0, TRDIOA1 to

TRDIOD1 pin functions

Programmable I/O port or output-compare output (Selectable by pin)

INT0 pin function Programmable I/O port, pulse output forced cutoff signal input, or INT0 interrupt input

Read from timer The count value can be read by reading the TRDi register.

Write to timer • When the SYNC bit in the TRDMR register is set to 0 (timer RD0 and ti mer RD1

operate independently).

Data can be written to the TRDi register.

• When the SYNC bit in the TRDMR register is set to 1 (timer RD0 and timer RD1

operate synchronously).

Data can be written to both the TRD0 and TRD1 registers by writi ng to the TRDi

Selectable functions • Output-compare output pin selection

Either 1 pin or multiple pins among TRDIOAi, TRDIOBi, TRDIOCi, or TRDIODi.

• Output level at the compare match selection

“L” output, “H” output, or output level inversed

• Initial output level selected

Set the level at period from the count start to the compare match.

• Tim ing for setting the TRDi register to 0000h

Overflow or compare match in the TRDGRAi register

• Buffer operation (Refer to 20.2.2 Buffer Operation.)

• Synchronous operation (Refer to 20.2.3 Synchronou s Op eration.)

• Changing output pins for registers TRDGRCi and TRDGRDi

The TRDGRCi register can be used as output control of the TRDIOAi pin and the

TRDGRDi register can be used as output control of the TRDIOBi pin.

• Pulse output forced cutoff signal input (Refer to 20.2.4 Pulse Output Forced

Cutoff.)

• Ti m er RD can be used as the internal timer without output.

• A/D trigger generation

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 329 of 723

20.4.1 Module Standby Control Register (MSTCR)

Notes:

1. When the MSTIIC bit is set to 1 (standby), any access to the SSU or the I2C bus associated registers (addresses

0193h to 019Dh) is disabled.

2. When the MSTTRD bi t is set to 1 (stand by), any acce ss to the ti mer RD associated regi sters (addresse s 0135h

to 015Fh) is disabled.

3. To set the MSTTRD bit to 1 (standby), set bits TCK2 to TCK0 in the TRDCRi (i = 0 or 1) register to 000b (f1).

4. When the MSTTRC bi t is set to 1 (stand by), any acce ss to the time r RC associated registers (addresses 0120h

to 0133h) is disabled.

20.4.2 Timer RD Control Expansion Register (TRDECR)

Note:

1. Enabled when in time r mode.

Address 0008h

Bitb7b6b5b4b3b2b1b0

Symbol — — MSTTRC MSTTRD MSTIIC — — —

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b1 —

b2 —

b3 MSTIIC SSU, I2C bus standby bit 0: Active

1: Standby (1) R/W

b4 MSTTRD Timer RD standby bit 0: Active

1: Standby (2, 3) R/W

b5 MSTTRC Timer RC standby bit 0: Active

1: Standby (4) R/W

b6 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b7 —

Address 0135h

Bitb7b6b5b4b3b2b1b0

Symbol ITCLK1 — — — ITCLK0 — — —

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b1 —

b2 —

b3 ITCLK0 Timer RD0 fC2 select bit 0: TRDCLK input selected

1: fC2 selected (1) R/W

b4 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b5 —

b6 —

b7 ITCLK1 Timer RD1 fC2 select bit 0: TRDCLK input selected

1: fC2 selected (1) R/W

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 330 of 723

20.4.3 Timer RD Trigger Control Register (TRDADCR)

Address 0136h

Bitb7b6b5b4b3b2b1b0

Symbol ADTRGD1E ADTRGC1E ADTRGB1E ADTRGA1E ADTRGD0E ADTRGC0E ADTRGB0E ADTRGA0E

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 ADTRGA0E A/D trigger A0 enable bit 0: A/D trigger disabled

1: A/D trigger generated at compare match with

registers TRD0 and TRDGRB0

R/W

b1 ADTRGB0E A/D trigger B0 enable bit 0: A/D trigger disabled

1: A/D trigger generated at compare match with

registers TRD0 and TRDGRB0

R/W

b2 ADTRGC0E A/D trigger C0 enable bit 0: A/D trigger disabled

1: A/D trigger generated at compare match with

registers TRD0 and TRDGRC0

R/W

b3 ADTRGD0E A/D trigger D0 enable bit 0: A/D trigger disabled

1: A/D trigger generated at compare match with

registers TRD0 and TRDGRD0

R/W

b4 ADTRGA1E A/D trigger A1 enable bit 0: A/D trigger disabled

1: A/D trigger generated at compare match with

registers TRD1 and TRDGRA1

R/W

b5 ADTRGB1E A/D trigger B1 enable bit 0: A/D trigger disabled

1: A/D trigger generated at compare match with

registers TRD1 and TRDGRB1

R/W

b6 ADTRGC1E A/D trigger C1 enable bit 0: A/D trigger disabled

1: A/D trigger generated at compare match with

registers TRD1 and TRDGRC1

R/W

b7 ADTRGD1E A/D trigger D1 enable bit 0: A/D trigger disabled

1: A/D trigger generated at compare match with

registers TRD1 and TRDGRD1

R/W

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 331 of 723

20.4.4 Timer RD Start Register (TRDSTR) in Output Compare Function

Notes:

1. When the CSEL0 bit is set to 1, write 0 to the TSTART0 bit.

2. When the CSEL1 bit is set to 1, write 0 to the TSTART1 bit.

3. When the CSEL0 bit is set to 0 and the compare match signal (TRDIOA0) is generated, this bit is set to 0 (count

stops).

4. When the CSEL1 bit is set to 0 and the compare match signal (TRDIOA1) is generated, this bit is set to 0 (count

stops).

Set the TRDSTR register using the MOV instruction (do not use the bi t handling instruction). Refer to 20.10.1

TRDSTR Register of Notes on Timer RD.

Address 0137h

Bitb7b6b5b4b3b2b1b0

Symbol — — — — CSEL1 CSEL0 TSTART1 TSTART0

After Reset11111100

Bit Symbol Bit Name Function R/W

b0 TSTART0 TRD0 count start flag (3) 0: Count stops (1)

1: Count starts R/W

b1 TSTART1 TRD1 count start flag (4) 0: Count stops (2)

1: Count starts R/W

b2 CSEL0 TRD0 count operation select bit 0: Count stops at the compare match with the

TRDGRA0 register

1: Count continues after the compare match with

the TRDGRA0 register

R/W

b3 CSEL1 TRD1 count operation select bit 0: Count stops at the compare match with the

TRDGRA1 register

1: Count continues after the compare match with

the TRDGRA1 register

R/W

b4 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. —

b5 —

b6 —

b7 —

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 332 of 723

20.4.5 Timer RD Mode Register (TRDMR) in Output Compare Function

Note:

1. When selecting 0 (change the TRDGRji r egi ste r output pin) by the IOj3 (j = C or D) bit in the TRDIORCi (i = 0 or

1) register, set the BFji bit in the TRDMR register to 0.

Address 0138h

Bitb7b6b5b4b3b2b1b0

Symbol BFD1 BFC1 BFD0 BFC0 — — — SYNC

After Reset00001110

Bit Symbol Bit Name Function R/W

b0 SYNC Timer RD syn c hronous bit 0: Regist ers TRD0 and TRD1 operate independently

1: Registers TRD0 and TRD1 operate synchronously R/W

b1 — Nothing is assig ned. If necessary, set to 0. When read, the content is 1. —

b2 —

b3 —

b4 BFC0 TRDGRC0 register function select

bit (1) 0: General register

1: Buffer register of TRDGRA0 register R/W

b5 BFD0 TRDGRD0 register function select

bit (1) 0: General register

1: Buffer register of TRDGRB0 register R/W

b6 BFC1 TRDGRC1 register function select

bit (1) 0: General register

1: Buffer register of TRDGRA1 register R/W

b7 BFD1 TRDGRD1 register function select

bit (1) 0: General register

1: Buffer register of TRDGRB1 register R/W

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 333 of 723

20.4.6 Timer RD PWM Mode Register (TRDPMR) in Output Compare Function

20.4.7 Timer RD Function Control Register (TRDFCR) in Output Compare

Function

Notes:

1. Set bits CMD1 to CMD0 when both the TS TART 0 and TSTART1 bits in the TRDSTR register are set to 0 (count

stops).

2. When bits CMD1 to CMD0 are set to 00b (timer mode, PWM mode, or PWM3 mode), the setting of the PWM3 bit

is enabled.

Address 0139h

Bitb7b6b5b4b3b2b1b0

Symbol — PWMD1 PWMC1 PWMB1 — PWMD0 PWMC0 PWMB0

After Reset10001000

Bit Symbol Bit Name Function R/W

b0 PWMB0 PWM mode of TRDIOB0 select bit Set to 0 (timer mode) in the output compare

function. R/W

b1 PWMC0 PWM mode of TRDIOC0 select bit R/W

b2 PWMD0 PWM mode of TRDIOD0 select bit R/W

b3 — Nothing is assig ned. If necessary, set to 0. When read, the content is 1. —

b4 PWMB1 PWM mode of TRDIOB1 select bit Set to 0 (timer mode) in the output compare

function. R/W

b5 PWMC1 PWM mode of TRDIOC1 select bit R/W

b6 PWMD1 PWM mode of TRDIOD1 select bit R/W

b7 — Nothing is assig ned. If necessary, set to 0. When read, the content is 1. —

Address 013Ah

Bitb7b6b5b4b3b2b1b0

Symbol PWM3 STCLK ADEG ADTRG OLS1 OLS0 CMD1 CMD0

After Reset10000000

Bit Symbol Bit Name Function R/W

b0 CMD0 Combination mode select bit (1) Set to 00b (timer mode, PWM mode, or PWM3

mode) in the output compare function. R/W

b1 CMD1 R/W

b2 OLS0 Normal-ph ase output level select bit

(in reset synchronous PWM mode or

complementary PWM mode)

This bit is disabled in the output compare

function. R/W

b3 OLS1 Coun ter-phase output level select bit

(in reset synchronous PWM mode or

complementary PWM mode)

R/W

b4 ADTRG A/D trigger enable bit

(in complementary PWM mode) R/W

b5 ADEG A/D trigger edge select bit

(in complementary PWM mode) R/W

b6 ST CLK External clock input select bit 0: External clock input disabled

1: External clock input enabled R/W

b7 PWM3 PWM3 mode select bit (2) Set this bit to 1 (other than PWM3 mode) in the

output compare function. R/W

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 334 of 723

20.4.8 Timer RD Output Master Enable Register 1 (TRDOER1) in Output Compare

Function

20.4.9 Timer RD Output Master Enable Register 2 (TRDOER2) in Output Compare

Function

Note:

1. Refer to 20.2.4 Pulse Output Forced Cutoff.

Address 013Bh

Bitb7b6b5b4b3b2b1b0

Symbol ED1 EC1 EB1 EA1 ED0 EC0 EB0 EA0

After Reset11111111

Bit Symbol Bit Name Function R/W

b0 EA0 TRDIOA0 output disable bit 0: Enable output

1: Disable output (The TRDIOA0 pin is used as a

programmable I/O port.)

R/W

b1 EB0 TRDIOB0 output disable bit 0: Enable output

1: Disable output (The TRDIOB0 pin is used as a

programmable I/O port.)

R/W

b2 EC0 TRDIOC0 output disable bit 0: Enable output

1: Disable output (The TRDIOC0 pin is used as a

programmable I/O port.)

R/W

b3 ED0 TRDIOD0 output disable bit 0: Enable output

1: Disable output (The TRDIOD0 pin is used as a

programmable I/O port.)

R/W

b4 EA1 TRDIOA1 output disable bit 0: Enable output

1: Disable output (The TRDIOA1 pin is used as a

programmable I/O port.)

R/W

b5 EB1 TRDIOB1 output disable bit 0: Enable output

1: Disable output (The TRDIOB1 pin is used as a

programmable I/O port.)

R/W

b6 EC1 TRDIOC1 output disable bit 0: Enable output

1: Disable output (The TRDIOC1 pin is used as a

programmable I/O port.)

R/W

b7 ED1 TRDIOD1 output disable bit 0: Enable output

1: Disable output (The TRDIOD1 pin is used as a

programmable I/O port.)

R/W

Address 013Ch

Bitb7b6b5b4b3b2b1b0

SymbolPTO———————

After Reset01111111

Bit Symbol Bit Name Function R/W

b0 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. —

b1 —

b2 —

b3 —

b4 —

b5 —

b6 —

b7 PTO INT0 of pulse output forced cutoff

signal input enabled bit (1) 0: Pulse output forced cutoff input disabled

1: Pulse output forced cutoff input enabled

(All bits in the TRDOER1 register are set to 1

(disable output) when “L” is applied to the INT0

pin.)

R/W

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 335 of 723

20.4.10 Timer RD Output Control Register (TRDOCR) in Output Compare Function

Write to the TRDOCR register when both the TSTART0 and TSTART1 bits in the TRDSTR register are set to

0 (count stopped).

If the pin fu nction is set f or wavefo rm outpu t (refer to 7.5 Port Set tings), the initial output level is output when

the TRDOCR register is set.

Address 013Dh

Bitb7b6b5b4b3b2b1b0

Symbol TOD1 TOC1 TOB1 TOA1 TOD0 TOC0 TOB0 TOA0

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 TOA0 TRDIOA0 output level select bit 0: Initial output “L”

1: Initial output “H” R/W

b1 TOB0 TRDIOB0 output level select bit 0: Initial output “L”

1: Initial output “H” R/W

b2 TOC0 TRDIOC0 initial output level select bit 0: “L”

1: “H” R/W

b3 TOD0 TRDIOD0 initial output level select bit R/W

b4 TOA1 TRDIOA1 initial output level select bit R/W

b5 TOB1 TRDIOB1 initial output level select bit R/W

b6 TOC1 TRDIOC1 initial output level select bit R/W

b7 TOD1 TRDIOD1 initial output level select bit R/W

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 336 of 723

20.4.11 Timer RD Control Register i (TRDCRi) (i = 0 or 1) in Output Compare

Function

Notes:

1. Enabled when the ITCLKi bit in the TRDECR register is set to 0 (TRDCLK input) and the STCLK bit in the

TRDFCR register is 1 (external clock input enabled).

2. Enabled when the ITCLKi bit in the TRDECR register is set to 1 (fC2) in timer mode.

3. Enabled when bits TCK2 to TCK0 are set to 101b (TRDCLK input or fC2), the ITCLKi bit in the TRDECR is set to

0 (TRDCLK input), and the STCLK bit in the TR DFCR register is set to 1 (external clock input enabled).

4. This setting is en able d when th e SYNC bit in the T RDMR re gister i s set to 1 (registers T RD0 and TR D1 operate

synchronously).

5. To select fOCO-F, set it to the clock frequency higher than the CPU clock frequency.

Address 0140h (TRDCR0), 015 0h (TRDCR1)

Bitb7b6b5b4b3b2b1b0

Symbol CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TCK2 TCK1 TCK0

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 TCK0 Count source select bit b2 b1 b0

0 0 0: f1

0 0 1: f2

0 1 0: f4

0 1 1: f8

1 0 0: f32

1 0 1: TRDCLK input (1) or fC2 (2)

1 1 0: fOCO40M

1 1 1: fOCO-F (5)

R/W

b1 TCK1 R/W

b2 TCK2 R/W

b3 CKEG0 External clock edge select bit (3) b4 b3

0 0: Count at the rising edge

0 1: Count at the falling edge

1 0: Count at both edges

1 1: Do not set.

R/W

b4 CKEG1 R/W

b5 CCLR0 TRDi counter clear select bit b7 b6 b5

0 0 0: Disable clear (free-running ope ra ti on )

0 0 1: Clear by compare match with the TRDGRAi

0 1 0: Clear by compare match with the TRDGRBi

0 1 1: Synchronous clear (clear simultaneously with

other timer RDi counter) (4)

1 0 0: Do not set.

1 0 1: Clear by compare match with the TRDGRCi

1 1 0: Clear by compare match with the TRDGRDi

1 1 1: Do not set.

R/W

b6 CCLR1 R/W

b7 CCLR2 R/W

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 337 of 723

20.4.12 Timer RD I/O Control Register Ai (TRDIORAi) (i = 0 or 1) in Output

Compare Function

Notes:

1. To select 1 (the TRDGRCi register is used as a buffer register of the TRD GRAi register) for this bit by the BFCi

bit in the TRDMR re gister, set the IOC2 bit in the TRDIORCi register to the same value as the IOA2 bit in the

TRDIORAi register.

2. To select 1 (the TRDGRDi register is used as a buffer register of the TRD GRBi register) for this bit by the BFDi

bit in the TRDMR re gister, set the IOD2 bit in the TRDIORCi register to the same value as the IOB2 bit in the

TRDIORAi register.

Address 0141h (TRDIORA0), 0151h (TRDIORA1)

Bitb7b6b5b4b3b2b1b0

Symbol— IOB2IOB1IOB0IOA3IOA2IOA1IOA0

After Reset10001000

Bit Symbol Bit Name Function R/W

b0 IOA0 TRDGRA control bit b1 b0

0 0: Disable pin output by the compare match

(TRDIOAi pin functions as programmable I/O port)

0 1: “L” output by compare match with the TRDGRAi

1 0: “H” output by compare match with the TRDGRAi

1 1: Toggle output by compare match with the

TRDGRAi re gi ster

R/W

b1 IOA1 R/W

b2 IOA2 TRDGRA mode select bit (1) Set to 0 (output compare) in the output compare

function. R/W

b3 IOA3 Input capture input switch bit Set to 1. R/W

b4 IOB0 TRDGRB control bit b5 b4

0 0: Disable pin output by the compare match

(TRDIOBi pin functions as programmable I/O port)

0 1: “L” output by compare match with the TRDGRBi

1 0: “H” output by compare match with the TRDGRBi

1 1: Toggle output by compare match with the

TRDGRBi re gi ster

R/W

b5 IOB1 R/W

b6 IOB2 TRDGRB mode select bit (2) Set to 0 (output compare) in the output compare

function. R/W

b7 — Nothing is assig ned. If necessary, set to 0. When read, the content is 1. —

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 338 of 723

20.4.13 Timer RD I/O Control Register Ci (TRDIORCi) (i = 0 or 1) in Output

Compare Function

Notes:

1. To select 1 (the TRDGRCi register is used as a buffer register of the TRD GRAi register) for this bit by the BFCi

bit in the TRDMR re gister, set the IOC2 bit in the TRDIORCi register to the same value as the IOA2 bit in the

TRDIORAi register.

2. To select 1 (the TRDGRDi register is used as a buffer register of the TRD GRBi register) for this bit by the BFDi

bit in the TRDMR re gister, set the IOD2 bit in the TRDIORCi register to the same value as the IOB2 bit in the

TRDIORAi register.

Address 0142h (TRDIORC 0), 0152h (TRDIORC1)

Bitb7b6b5b4b3b2b1b0

Symbol IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0

After Reset10001000

Bit Symbol Bit Name Function R/W

b0 IOC0 TRDGRC control bit b1 b0

0 0: Disable pin output by compare match

0 1: “L” output by compare match with the

TRDGRCi register

1 0: “H” output by compa re m at ch w it h th e

TRDGRCi register

1 1: Toggle output by compare match with the

TRDGRCi register

R/W

b1 IOC1 R/W

b2 IOC2 TRDGRC mode select bit (1) Set to 0 (output compare) in the output compare

function. R/W

b3 IOC3 TRDGRC register function select bit 0: TRDIOA output register

(Refer to 20.4.21 Changing Output Pins in

Registers TRDGRCi (i = 0 or 1) and TRDGRDi.)

1: General register or buffer register

R/W

b4 IOD0 TRDGRD control bit b5 b4

0 0: Disable pin output by compare match

0 1: “L” output by compare match with the

TRDGRDi register

1 0: “H” output by compa re m at ch w it h th e

TRDGRDi register

1 1: Toggle output by compare match with the

TRDGRDi register

R/W

b5 IOD1 R/W

b6 IOD2 TRDGRD mode select bit (2) Set to 0 (output compare) in the output compare

function. R/W

b7 IOD3 TRDGRD register function select bit 0: TRDIOB output register

(Refer to 20.4.21 Changing Output Pins in

Registers TRDGRCi (i = 0 or 1) and TRDGRDi.)

1: General register or buffer register

R/W

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 339 of 723

20.4.14 Timer RD Status Register i (TRDSRi) (i = 0 or 1) in Output Compare

Function

Notes:

1. Nothing is assigned to b5 in the TRDSR0 register. When writing to b5, write 0. When reading, the content is 1.

2. The writing results are as follows:

• This bit is set to 0 when the read result is 1 and 0 is written to the same bit.

• This bit remains unchanged even if the read result is 0 and 0 is written to the same bit. (This bit remains 1 even

if it is set to 1 from 0 after reading, and writing 0.)

• This bit remains unchanged if 1 is written to it.

3. Including when the BFji bit in the TRD MR reg ister is set to 1 (TRDGRji is used as the buffer register).

Address 0143h (TRDSR0), 0153h (TRDSR1)

Bitb7b6b5b4b3b2b1b0

Symbol — — UDF OVF IMFD IMFC IMFB IMFA

After Reset 1 1 1 0 0 0 0 0 TRDSR0 register

After Reset 1 1 0 0 0 0 0 0 TRDSR1 register

Bit Symbol Bit Name Function R/W

b0 IMFA Input capture / compare match flag A [Source for setting this bit to 0]

Write 0 after read (2)

[Source for setting this bit to 1]

When the value in the TRDi register matches with

the value in the TRDGRAi register.

R/W

b1 IMFB Input capture / compare match flag B [Source for setting this bit to 0]

Write 0 after read (2)

[Source for setting this bit to 1]

When the value in the TRDi register matches with

the value in the TRDGRBi register.

R/W

b2 IMFC Input capture / compare match flag C [Source for setting this bit to 0]

Write 0 after read (2)

[Source for setting this bit to 1]

When the value in the TRDi register matches with

the value in the TRDGRCi register (3).

R/W

b3 IMFD Input capture / compare match flag D [Source for setting this bit to 0]

Write 0 after read (2)

[Source for setting this bit to 1]

When the value in the TRDi register matches with

the value in the TRDGRDi register (3).

R/W

b4 OVF Overflow flag [Source fo r setting this bit to 0]

Write 0 after read (2)

[Source for setting this bit to 1]

When the TRDi register overfl ows.

R/W

b5 UDF Underflow flag (1) This bit is disabled in the output compare function. R/W

b6 — Nothing is assig ned. If necessary, set to 0. When read, the content is 1. —

b7 —

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 340 of 723

20.4.15 Timer RD Interrupt Enable Register i (TRDIERi) (i = 0 or 1) in Output

Compare Function

20.4.16 Timer RD Counter i (TRDi) (i = 0 or 1) in Output Compare Function

Access the TRDi register in 16-bit units. Do not access it in 8-bit units.

Address 0144h (TRDIER0), 0154h (TRDIER1)

Bitb7b6b5b4b3b2b1b0

Symbol — — — OVIE IMIED IMIEC IMIEB IMIEA

After Reset11100000

Bit Symbol Bit Name Function R/W

b0 IMIEA Input capture/compare match interrupt

enable bit A 0: Disable interrupt (IMIA) by the IMFA bit

1: Enable interrupt (IMIA) by the IMFA bit R/W

b1 IMIEB Input capture/compare match interrupt

enable bit B 0: Disable interrupt (IMIB) by the IMFB bit

1: Enable interrupt (IMIB) by the IMFB bit R/W

b2 IMIEC Input capture/compare match interrupt

enable bit C 0: Disable interrupt (IMIC) by the IMFC bit

1: Enable interrupt (IMIC) by the IMFC bit R/W

b3 IMIED Input capture/compare match interrupt

enable bit D 0: Disable interrupt (IMID) by the IMFD bit

1: Enable interrupt (IMID) by the IMFD bit R/W

b4 OVIE Overflow/underflow interrupt enable

bit 0: Disable interrupt (OVI) by the OVF bit

1: Enable interrupt (OVI) by the OVF bit R/W

b5 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. —

b6 —

b7 —

Address 0147h to 0146h (TRD0), 0157h to 0156h (TRD1)

Bitb7b6b5b4b3b2b1b0

Symbol————————

After Reset00000000

Bit b15 b14 b13 b12 b11 b10 b9 b8

Symbol————————

After Reset00000000

Bit Function Setting Range R/W

b15 to b0 Count the count source. Coun t operation is incremented.

When an overflow occurs, the OVF bit in the TRDSRi register is set to 1. 0000h to FFFFh R/W

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 341 of 723

20.4.17 Timer RD General Registers Ai, Bi, Ci, and Di (TRDGRAi, TRDGRBi,

TRDGRCi, TRDGRDi) (i = 0 or 1) in Output Compare Function

Access registers TRDGRAi to TRDGRDi in 16-bit units. Do not access them in 8-bit units.

The following registers are disabled in the output comp are function: TRDDF0, TRDDF1, TRDPOCR0, and

TRDPOCR1.

i = 0 or 1, j = A, B, C, or D

BFji: Bit in TRDMR register, IOj3: Bit in TRDIORCi register

Address 0149h to 0148h (TRDGRA0), 014Bh to 014Ah (TRDGRB0),

014Dh to 014Ch (TRDGRC0), 014Fh to 014Eh (TRDGRD0),

0159h to 0158h (TRDGRA1), 015Bh to 015Ah (TRDGRB1),

015Dh to 015Ch (TRDGRC1), 015Fh to 015Eh (TRDGRD1)

Bitb7b6b5b4b3b2b1b0

Symbol————————

After Reset11111111

Bit b15 b14 b13 b12 b11 b10 b9 b8

Symbol————————

After Reset11111111

Bit Function R/W

b15 to b0 Refer to Table 20.8 TRDGRji Register Function in Output Compare Function R/W

Table 20.8 TRDGRji Register Function in Output Compare Function

Output PinBFji IOj3

TRDGRAi −−General register. Write the compare value. TRDIOAi

TRDGRBi TRDIOBi

TRDGRCi 0 1 General register. Write the compare value. TRDIOCi

TRDGRDi TRDIODi

TRDGRCi 1 1 Buffer register. Writ e th e ne xt co mpa re valu e

(Refer to 20.2.2 Buffer Opera ti on .) TRDIOAi

TRDGRDi TRDIOBi

TRDGRCi 0 0 TRDIOAi output control (Refer to 20.4.21 Changing Output

Pins in Registers TRDGRCi (i = 0

or 1) and TRDGRDi.)

TRDIOAi

TRDGRDi TRDIOBi output control TRDIOBi

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 342 of 723

20.4.18 Timer RD Pin Select Register 0 (TRDPSR0)

The TRDPSR0 register selects which pin is assigned to the timer RD I/O. To use the I/O pin for timer RD, set

this register.

Set the TRDPSR0 register before setting the timer RD associated registers. Also, do not change the setting

value in this register during timer RD operation.

20.4.19 Timer RD Pin Select Register 1 (TRDPSR1)

The TRDPSR1 register selects which pin is assigned to the timer RD I/O. To use the I/O pin for timer RD, set

this register.

Set the TRDPSR1 register before setting the timer RD associated registers. Also, do not change the setting

value in this register during timer RD operation.

Address 0184h

Bitb7b6b5b4b3b2b1b0

Symbol — TRDIOD0SEL0 TRDIOC0SEL1 TRDIOC0SEL0 TRDIOB0SEL1 TRDIOB0SEL0 — TRDIOA0SEL0

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 TRDIOA0SEL0 TRDIOA0/TRDCLK pin select bit 0: TRDIOA0/TRDCLK pin not used

1: P2_0 assigned R/W

b1 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b2 TRDIOB0SEL0 TRDIOB0 pin select bit b3 b2

0 0: TRDIOB0 pin not used

0 1: Do not set.

1 0: P2_2 assigned

1 1: Do not set.

R/W

b3 TRDIOB0SEL1 R/W

b4 TRDIOC0SEL0 TRDIOC0 pin select bit b5 b4

0 0: TRDIOC0 pin not used

0 1: Do not set.

1 0: P2_1 assigned

1 1: Do not set.

R/W

b5 TRDIOC0SEL1 R/W

b6 TRDIOD0SEL0 TRDIOD0 pin select bit 0: TRDIOD0 pin not used

1: P2_3 assigned R/W

b7 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

Address 0185h

Bitb7b6b5b4b3b2b1b0

Symbol — TRDIOD1SEL0 — TRDIOC1SEL0 — TRDIOB1SEL0 — TRDIOA1SEL0

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 TRDIOA1SEL0 TRDIOA1 pin select bit 0: TRDIOA1 pin not used

1: P2_4 assigned R/W

b1 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b2 TRDIOB1SEL0 TRDIOB1 pin select bit 0: TRDIOB1 pin not used

1: P2_5 assigned R/W

b3 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b4 TRDIOC1SEL0 TRDIOC1 pin select bit 0: TRDIOC1 pin not used

1: P2_6 assigned R/W

b5 — Reserved bit Set to 0. R/W

b6 TRDIOD1SEL0 TRDIOD1 pin select bit 0: TRDIOD1 pin not used

1: P2_7 assigned R/W

b7 — Reserved bit Set to 0. R/W

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 343 of 723

20.4.20 Operating Example

Figure 20.11 Operating Example of Output Compare Functio n

Value in TRDi register

m+1 m+1

TSTARTi bit in

TRDSTR register

TRDIOAi output

IMFA bit in

TRDSRi register

TRDIOBi output

IMFB bit in

TRDSRi register

TRDIOCi output

IMFC bit in

TRDSRi register

Initial output “H”

“L” output by compare match

Set to 0 by a program

Count source

i = 0 or 1 M: Value set in TRDGRAi register

n: Value set in TRDGRBi register

p: Value set in TRDGRCi register

The above applies under the fol lowing conditi ons:

The CSELi bit in the TRDSTR register is set to 1 (the TRDi register is not stopped by compare match).

Bits BFCi and BFDi in the TRDMR register are set to 0 (registers TRDGRCi and TRDGRDi are not used as buffer registers).

Bits EAi, EBi, and ECi in the TRDOER1 register are set to 0 (enable the TRDIOAi, TRDIOBi and TRDIOCi pin outputs).

Bits CCLR2 t o CCLR0 in the TRDCRi register are set to 001b (set the TRDi register to 000h by compare match in the TRDGRAi register).

Set bits IOD3 to IOD0 in the TRDIORCi register to 1000b (TRDGRDi register does not control TRDIOBi pin output, pin output at compare match is disabled).

n+1

P+1

Count

stops

Count

restarts

Output level

held

Output level

held

Output level

held

Set to 0 by a program

“H” output by compare match

Output inverted by compare match

Initial outpu t “L”

Initial output “L”

Bits TOAi and TOBi in the TRDOCR register is set to 0 (initial output “L” to compare match), the TOCi bit is set to 1 (initial output “H” to compare match).

Bits IOA2 to IOA0 in t he TRDIORAi register are set to 011b (TRDIOAi output inverted at TRDGRAi register compare match).

Bits IOB2 to IOB0 in the TRDIORAi register are set to 010b (TRDIOBi “H” output at TRDGRBi register compare match).

Bits IOC3 to IOC0 in the TRDIORCi register are set to 1001b (TRDIOCi “L” output at TRDGRCi register compare match).

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 344 of 723

20.4.21 Changing Output Pins in Registers TRDGRCi (i = 0 or 1) and TRDGRDi

The TRDGRCi register can be used for output control of the TRDIO Ai pin, and t he TRDGRDi regist er can be

used for output control of the TRDIOBi pin. Therefore, each pin output can be controlled as follows:

• TRDIOAi output is controlled by the values in registers TRDGRAi and TRDG RCi.

• TRDIOBi output is controlled by the values in registers TRDGRBi and TRDGRDi.

Change output pins in registers TRDGRCi and TRDGRDi as follows:

• Select 0 (change TRDGRji register output pin) by the IOj3 (j = C or D) bit in the TRDIORCi register.

• Set the BFji bit in the TRDMR register to 0 (general register).

• Set different values in registers TRDGRCi and TRDGRAi. Also, set different values in registers TRDGRDi

and TRDGRBi.

Figure 20.13 shows an Operating Examp le When TRDGRCi Register is Used for Out put Control of TRDIOA i

Pin and TRDGRDi Register is Used for Output Control of TRDIOBi Pin.

Figure 20.12 Changing Output Pins in Registers TRDGRCi and TRDGRDi

TRDIOA0 Output

control Comparator TRDGRA0

TRD0

TRDIOC0 Output

control Comparator TRDGRC0

Compare match signal

TRDIOB0 Output

control Comparator TRDGRB0

TRDIOD0 Output

control Comparator TRDGRD0

Timer RD0

TRDIOA1 Output

control Comparator TRDGRA1

TRD1

TRDIOC1 Output

control Comparator TRDGRC1

TRDIOB1 Output

control Comparator TRDGRB1

TRDIOD1 Output

control Comparator TRDGRD1

Timer RD1

Compare match signal

IOC3 = 0 in

TRDIORC0 register

IOC3 = 1

IOD3 = 0 in

TRDIORC0 register

IOD3 = 1

IOC3 = 0 in

TRDIORC1 register

IOC3 = 1

IOD3 = 0 in

TRDIORC1 register

IOD3 = 1

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 345 of 723

Figure 20.13 Operating Example When TRDGRCi Register is Used for Output Control of TRDIOAi

Pin and TRDGRDi Register is Us ed for Output Control of TRDIOBi Pin

Set to 0 by a programSet to 0 by a program

Value in TRDi register

Count source

TRDIOAi output

FFFFh

TRDIOBi output

m: Value set in TRDGRAi register

n: Value set in TRDGRCi register

p: Value set in TRDGRBi register

q: Value set in TRDGRDi register

The above applies under the following conditions:

The CSELi bit in the TRDSTR register is set to 1 (the TRDi register is not stopped by compare match).

Bits BFCi and BFDi in the TRDMR register are set to 0 (registers TRDGRCi and TRDGRDi are not used as buffer register).

Bits EAi and EBi in the TRDOER1 register are set to 0 (enable TRDIOAi and TRDIOBi pin outputs).

Bits CCLR2 to CCLR0 in the TRDCRi register are set to 001b (set the TRDi register to 0000h by compare match in the TRDGRAi register).

Bits TOAi and TOBi in the TRDOCR register are set to 0 (initial output “L” to compare match).

Bits IOA2 to IOA0 in the TRDIORAi register are set to 011b (TRDIOAi output inverted at TRDGRAi register compare match).

Bits IOB2 to IOB0 in the TRDIORAi register are set to 011b (TRDIOBi output inverted at TRDGRBi register compare match).

Bits IOC3 to IOC0 in the TRDIORCi register are set to 0011b (TRDIOAi output inverted at TRDGRCi register compare match).

Bits IOD3 to IOD0 in the TRDIORCi register are set to 0011b (TRDIOBi output inverted at TRDGRDi register compare match).

i = 0 or 1

m+1

n+1

0000h

m-n

p+1

p-qq+1

IMFA bit in

TRDSRi register

IMFC bit in

TRDSRi register

Set to 0 by a program

Output inverted by compare match

Initial output “L”

IMFB bit in

TRDSRi register

IMFD bit in

TRDSRi register

Initial output “L”

Set to 0 by a program

Output inverted by compare match

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 346 of 723

20.4.22 A/D Trigger Generation

A compare match signal with registers TRDi (i = 0 or 1) and TRDGRji (j = A, B, C, or D) can be used as the

conversion start trigger of the A/D converter.

The TRDADCR register is used to select which compare match is used.

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 347 of 723

20.5 PWM Mode

In PWM mode, a PWM waveform is output. Up to 3 PWM waveforms with the same period can be output by timer

RDi (i = 0 or 1). Also, up to 6 PWM waveforms with the same period can be output by synchronizing timer RD0

and timer RD1. Since this mode functions by a combination of the TRDIOji (i = 0 or 1, j = B, C, or D) pin and

TRDGRji register, the PWM mode, or any other mode or function, can be selected for each individual pin.

(However, since the TRDGRAi register is used when using any pin for PWM mode, the TRDGRAi register cannot

be used for other modes.)

Figure 20.14 shows a Block Diagram o f PWM Mode, and Table 20.9 lists t he PWM Mode Specifi cations. Figures

20.15 and 20.16 show the Operations of PWM Mode.

Figure 20.14 Block Diagram of PWM Mode

TRDIOBi

Output

control

TRDGRAi

TRDi

Compare match signal

TRDGRBi

TRDIOCi

TRDGRCi

TRDGRDi

TRDIODi

(Note 1)

(Note 2)

i = 0 or 1

Notes:

1. When the BFCi bit in the TRDMR register is set to 1 (the TRDGRCi register is used as the

buffer register of the TRDGRAi register).

2. When the BFDi bit in the TRDMR register is set to 1 (the TRDGRDi register is used as the

buffer register of the TRDGRBi register).

Compare match signal

Comparator

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 348 of 723

i = 0 or 1

j = B, C, or D

h = A, B, C, or D

Table 20.9 PWM Mode Specifications

Item Specification

Count sources f1, f2, f4, f8, f32, fOCO40M, fOCO-F

External signal input to the TRDCLK pin (valid edge selected by a

program)

Count operations Increment

PWM waveform PWM period: 1/fk x (m+1)

Active level width: 1/fk x (m-n)

Inactive leve l width: 1/fk x (n+1)

fk: Frequency of count source

m: Value set in the TRDGRAi register

n: Value set in the TRDGRji register

Count start condition 1 (count starts) is written to the TSTARTi bit in the TRDSTR register.

Count stop conditions • 0 (count stops) is written to the TSTARTi bit in the TRDSTR register

when the CSELi bit in the TRDSTR register is set to 1.

The PWM output pin holds output level before the count stops.

• When th e CSELi bit in the TRDSTR register is set to 0, the count

stops at the compare match in the TRDGR Ai reg i ste r.

The PWM output pin holds level after output change by compare

match.

Interrupt request generation

timing • Compare match (The content of the TRDi register matches content of

the TRDGRhi register.)

• TRDi register overflows

TRDIOA0 pin function Programmable I/O port or TRDCLK (external clock) input

TRDIOA1 pin function Programmable I/O port

TRDIOB0, TRDIOC0, TRDIOD0,

TRDIOB1, TRDIOC1, TRDIOD1

pin functions

Programmable I/O port or pulse output (selectable by pin)

INT0 pin function Prog rammable I/O port, pulse output forced cutoff signal inpu t, or INT0

interrupt input

Read from timer The count value can be read by reading the TRDi regi ster.

Write to timer The value can be written to the TRDi register.

Selectable functions • One to three PWM output pins selectable with timer RDi

Either 1 pin or multiple pins of the TRDIOBi, TRDIOCi or TRDIODi

pin.

• Active level selectable for each pin.

• Initial output level selectable for each pin.

• Synchrono us operation (Refer to 20.2.3 Synchronous Operation.)

• Buffer operation (Refer to 20.2.2 Buffer Operation.)

• Pulse outp ut forced cutoff signal input (Refer to 20.2.4 Pulse Output

Forced Cutoff.)

• A/D trigger generation

m+1

n+1 m-n (When “L” is selected as the active lev el)

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 349 of 723

20.5.1 Module Standby Control Register (MSTCR)

Notes:

1. When the MSTIIC bit is set to 1 (standby), any access to the SSU or the I2C bus associated registers (addresses

0193h to 019Dh) is disabled.

2. When the MSTTRD bi t is set to 1 (stand by), any acce ss to the ti mer RD associated regi sters (addresse s 0135h

to 015Fh) is disabled.

3. To set the MSTTRD bit to 1 (standby), set bits TCK2 to TCK0 in the TRDCRi (i = 0 or 1) register to 000b (f1).

4. When the MSTTRC bi t is set to 1 (stand by), any acce ss to the time r RC associated registers (addresses 0120h

to 0133h) is disabled.

20.5.2 Timer RD Control Expansion Register (TRDECR)

Note:

1. Enabled when in time r mode.

Address 0008h

Bitb7b6b5b4b3b2b1b0

Symbol — — MSTTRC MSTTRD MSTIIC — — —

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b1 —

b2 —

b3 MSTIIC SSU, I2C bus standby bit 0: Active

1: Standby (1) R/W

b4 MSTTRD Timer RD standby bit 0: Active

1: Standby (2, 3) R/W

b5 MSTTRC Timer RC standby bit 0: Active

1: Standby (4) R/W

b6 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b7 —

Address 0135h

Bitb7b6b5b4b3b2b1b0

Symbol ITCLK1 — — — ITCLK0 — — —

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b1 —

b2 —

b3 ITCLK0 Timer RD0 fC2 select bit 0: TRDCLK input selected

1: fC2 selected (1) R/W

b4 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b5 —

b6 —

b7 ITCLK1 Timer RD1 fC2 select bit 0: TRDCLK input selected

1: fC2 selected (1) R/W

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 350 of 723

20.5.3 Timer RD Trigger Control Register (TRDADCR)

Address 0136h

Bitb7b6b5b4b3b2b1b0

Symbol ADTRGD1E ADTRGC1E ADTRGB1E ADTRGA1E ADTRGD0E ADTRGC0E ADTRGB0E ADTRGA0E

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 ADTRGA0E A/D trigger A0 enable bit 0: A/D trigger disabled

1: A/D trigger generated at compare match with

registers TRD0 and TRDGRB0

R/W

b1 ADTRGB0E A/D trigger B0 enable bit 0: A/D trigger disabled

1: A/D trigger generated at compare match with

registers TRD0 and TRDGRB0

R/W

b2 ADTRGC0E A/D trigger C0 enable bit 0: A/D trigger disabled

1: A/D trigger generated at compare match with

registers TRD0 and TRDGRC0

R/W

b3 ADTRGD0E A/D trigger D0 enable bit 0: A/D trigger disabled

1: A/D trigger generated at compare match with

registers TRD0 and TRDGRD0

R/W

b4 ADTRGA1E A/D trigger A1 enable bit 0: A/D trigger disabled

1: A/D trigger generated at compare match with

registers TRD1 and TRDGRA1

R/W

b5 ADTRGB1E A/D trigger B1 enable bit 0: A/D trigger disabled

1: A/D trigger generated at compare match with

registers TRD1 and TRDGRB1

R/W

b6 ADTRGC1E A/D trigger C1 enable bit 0: A/D trigger disabled

1: A/D trigger generated at compare match with

registers TRD1 and TRDGRC1

R/W

b7 ADTRGD1E A/D trigger D1 enable bit 0: A/D trigger disabled

1: A/D trigger generated at compare match with

registers TRD1 and TRDGRD1

R/W

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 351 of 723

20.5.4 Timer RD Start Register (TRDSTR) in PWM Mode

Notes:

1. When the CSEL0 bit is set to 1, write 0 to the TSTART0 bit.

2. When the CSEL1 bit is set to 1, write 0 to the TSTART1 bit.

3. When the CSEL0 bit is set to 0 and the compare match signal (TRDIOA0) is generated, this bit is set to 0 (count

stops).

4. When the CSEL1 bit is set to 0 and the compare match signal (TRDIOA1) is generated, this bit is set to 0 (count

stops).

Set the TRDSTR register using the MOV instruction (do not use the bi t handling instruction). Refer to 20.10.1

TRDSTR Register of Notes on Timer RD.

20.5.5 Timer RD Mode Register (TRDMR) in PWM Mode

Address 0137h

Bitb7b6b5b4b3b2b1b0

Symbol — — — — CSEL1 CSEL0 TSTART1 TSTART0

After Reset11111100

Bit Symbol Bit Name Function R/W

b0 TSTART0 TRD0 count start flag (3) 0: Count stops (1)

1: Count starts R/W

b1 TSTART1 TRD1 count start flag (4) 0: Count stops (2)

1: Count starts R/W

b2 CSEL0 TRD0 count operation select bit 0: Count stops at the compare match with the

TRDGRA0 register

1: Count continues after the compare match with

the TRDGRA0 register

R/W

b3 CSEL1 TRD1 count operation select bit 0: Count stops at the compare match with the

TRDGRA1 register

1: Count continues after the compare match with

the TRDGRA1 register

R/W

b4 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. —

b5 —

b6 —

b7 —

Address 0138h

Bitb7b6b5b4b3b2b1b0

Symbol BFD1 BFC1 BFD0 BFC0 — — — SYNC

After Reset00001110

Bit Symbol Bit Name Function R/W

b0 SYNC Timer RD syn c hronous bit 0: Regist ers TRD0 and TRD1 operate independently

1: Registers TRD0 and TRD1 operate synchronously R/W

b1 — Nothing is assig ned. If necessary, set to 0. When read, the content is 1. —

b2 —

b3 —

b4 BFC0 TRDGRC0 register function select

bit 0: General register

1: Buffer register of TRDGRA0 register R/W

b5 BFD0 TRDGRD0 register function select

bit 0: General register

1: Buffer register of TRDGRB0 register R/W

b6 BFC1 TRDGRC1 register function select

bit 0: General register

1: Buffer register of TRDGRA1 register R/W

b7 BFD1 TRDGRD1 register function select

bit 0: General register

1: Buffer register of TRDGRB1 register R/W

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 352 of 723

20.5.6 Timer RD PWM Mode Register (TRDPMR) in PWM Mode

20.5.7 Timer RD Function Control Register (TRDFCR) in PWM Mode

Notes:

1. Set bits CMD1 to CMD0 when both the TS TART 0 and TSTART1 bits in the TRDSTR register are set to 0 (count

stops).

2. When bits CMD1 to CMD0 are set to 00b (timer mode, PWM mode, or PWM3 mode), the setting of the PWM3 bit

is enabled.

Address 0139h

Bitb7b6b5b4b3b2b1b0

Symbol — PWMD1 PWMC1 PWMB1 — PWMD0 PWMC0 PWMB0

After Reset10001000

Bit Symbol Bit Name Function R/W

b0 PWMB0 PWM mode of TRDIOB0 select bit 0: Timer mode

1: PWM mode R/W

b1 PWMC0 PWM mode of TRDIOC0 select bit R/W

b2 PWMD0 PWM mode of TRDIOD0 select bit R/W

b3 — Nothing is assig ned. If necessary, set to 0. When read, the content is 1. —

b4 PWMB1 PWM mode of TRDIOB1 select bit 0: Timer mode

1: PWM mode R/W

b5 PWMC1 PWM mode of TRDIOC1 select bit R/W

b6 PWMD1 PWM mode of TRDIOD1 select bit R/W

b7 — Nothing is assig ned. If necessary, set to 0. When read, the content is 1. —

Address 013Ah

Bitb7b6b5b4b3b2b1b0

Symbol PWM3 STCLK ADEG ADTRG OLS1 OLS0 CMD1 CMD0

After Reset10000000

Bit Symbol Bit Name Function R/W

b0 CMD0 Combination mode select bit (1) Set to 00b (timer mode, PWM mode, or PWM3

mode) in PWM mode. R/W

b1 CMD1 R/W

b2 OLS0 Normal-ph ase output level select bit

(in reset synchronous PWM mode or

complementary PWM mode)

This bit is disabled in PWM mode. R/W

b3 OLS1 Coun ter-phase output level select bit

(in reset synchronous PWM mode or

complementary PWM mode)

R/W

b4 ADTRG A/D trigger enable bit

(in complementary PWM mode) R/W

b5 ADEG A/D trigger edge select bit

(in complementary PWM mode) R/W

b6 ST CLK External clock input select bit 0: External clock input disabled

1: External clock input enabled R/W

b7 PWM3 PWM3 mode select bit (2) Set this bit to 1 (other than PWM3 mode) in

PWM mode. R/W

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 353 of 723

20.5.8 Timer RD Output Master Enable Registe r 1 (TRDOER1) in PWM Mode

20.5.9 Timer RD Output Master Enable Registe r 2 (TRDOER2) in PWM Mode

Note:

1. Refer to 20.2.4 Pulse Output Forced Cutoff.

Address 013Bh

Bitb7b6b5b4b3b2b1b0

Symbol ED1 EC1 EB1 EA1 ED0 EC0 EB0 EA0

After Reset11111111

Bit Symbol Bit Name Function R/W

b0 EA0 TRDIOA0 output disable bit Set this bit to 1 (the TRDIOA0 pin is used as a

programmable I/O port) in PWM mode. R/W

b1 EB0 TRDIOB0 output disable bit 0: Enable output

1: Disable output (The TRDIOB0 pin is used as a

programmable I/O port.)

R/W

b2 EC0 TRDIOC0 output disable bit 0: Enable output

1: Disable output (The TRDIOC0 pin is used as a

programmable I/O port.)

R/W

b3 ED0 TRDIOD0 output disable bit 0: Enable output

1: Disable output (The TRDIOD0 pin is used as a

programmable I/O port.)

R/W

b4 EA1 TRDIOA1 output disable bit Set this bit to 1 (the TRDIOA1 pin is used as a

programmable I/O port) in PWM mode. R/W

b5 EB1 TRDIOB1 output disable bit 0: Enable output

1: Disable output (The TRDIOB1 pin is used as a

programmable I/O port.)

R/W

b6 EC1 TRDIOC1 output disable bit 0: Enable output

1: Disable output (The TRDIOC1 pin is used as a

programmable I/O port.)

R/W

b7 ED1 TRDIOD1 output disable bit 0: Enable output

1: Disable output (The TRDIOD1 pin is used as a

programmable I/O port.)

R/W

Address 013Ch

Bitb7b6b5b4b3b2b1b0

SymbolPTO———————

After Reset01111111

Bit Symbol Bit Name Function R/W

b0 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. —

b1 —

b2 —

b3 —

b4 —

b5 —

b6 —

b7 PTO INT0 of pulse output forced cutoff

signal input enabled bit (1) 0: Pulse output forced cutoff input disabled

1: Pulse output forced cutoff input enabled

(All bits in the TRDOER1 register are set to 1

(disable output) when “L” is applied to the INT0

pin.)

R/W

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 354 of 723

20.5.10 Timer RD Output Control Register (TRDOCR) in PWM Mode

Note:

1. If the pin function is set for waveform output (refer to 7.5 Port Settings), the initial output level is output when the

TRDOCR register is set.

Write to the TRDOCR register when both the TSTART0 and TSTART1 bits in the TRDSTR register are set to

0 (count stops).

20.5.11 Timer RD Control Register i (TRDCRi) (i = 0 or 1) in PWM Mode

Notes:

1. Enabled when the ITCLKi bit in the TRDECR register is set to 0 (TRDCLK input) and the STCLK bit in the

TRDFCR register is 1 (external clock input enabled).

2. Enabled when the ITCLKi bit in the TRDECR register is set to 1 (fC2) in timer mode.

3. Enabled when bits TCK2 to TCK0 are set to 101b (TRDCLK input or fC2), the ITCLKi bit in the TRDECR is set to

0 (TRDCLK input), and the STCLK bit in the TR DFCR register is set to 1 (external clock input enabled).

4. To select fOCO-F, set it to the clock frequency higher than the CPU clock frequency.

Address 013Dh

Bitb7b6b5b4b3b2b1b0

Symbol TOD1 TOC1 TOB1 TOA1 TOD0 TOC0 TOB0 TOA0

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 TOA0 TRDIOA0 output level select bi t Set this bit to 0 (enable output) in PWM mode. R /W

b1 TOB0 TRDIOB0 output level select bit (1) 0: Initial output is inactive level

1: Initial output is active level R/W

b2 TOC0 TRDIOC0 initial output level select bit (1) R/W

b3 TOD0 TRDIOD0 initial output level select bit (1) R/W

b4 TOA1 TRDIOA1 initial output level select bit Set this bit to 0 (enable outp ut) in PWM mode. R/W

b5 TOB1 TRDIOB1 initial output level select bit (1) 0: Inactive level

1: Active level R/W

b6 TOC1 TRDIOC1 initial output level select bit (1) R/W

b7 TOD1 TRDIOD1 initial output level select bit (1) R/W

Address 0140h (TRDCR0), 015 0h (TRDCR1)

Bitb7b6b5b4b3b2b1b0

Symbol CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TCK2 TCK1 TCK0

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 TCK0 Count source select bit b2 b1 b0

0 0 0: f1

0 0 1: f2

0 1 0: f4

0 1 1: f8

1 0 0: f32

1 0 1: TRDCLK input (1) or fC2 (2)

1 1 0: fOCO40M

1 1 1: fOCO-F (4)

R/W

b1 TCK1 R/W

b2 TCK2 R/W

b3 CKEG0 External clock edge select bit (3) b4 b3

0 0: Count at the rising edge

0 1: Count at the falling edge

1 0: Count at both edges

1 1: Do not set.

R/W

b4 CKEG1 R/W

b5 CCLR0 TRDi counter clear select bit S et to 001b (th e TRDi register cleared at compare

match with TRDGRAi register) in PWM mode. R/W

b6 CCLR1 R/W

b7 CCLR2 R/W

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 355 of 723

20.5.12 Timer RD Status Register i (TRDSRi) (i = 0 or 1) in PWM Mode

Notes:

1. Nothing is assigned to b5 in the TRDSR0 register. When writing to b5, write 0. When reading, the content is 1.

2. The writing results are as follows:

• This bit is set to 0 when the read result is 1 and 0 is written to the same bit.

• This bit remains unchanged even if the read result is 0 and 0 is written to the same bit. (This bit remains 1 even

if it is set to 1 from 0 after reading, and writing 0.)

• This bit remains unchanged if 1 is written to it.

3. Including when the BFji bit in the TRD MR reg ister is set to 1 (TRDGRji is used as the buffer register).

Address 0143h (TRDSR0), 0153h (TRDSR1)

Bitb7b6b5b4b3b2b1b0

Symbol — — UDF OVF IMFD IMFC IMFB IMFA

After Reset 1 1 1 0 0 0 0 0 TRDSR0 register

After Reset 1 1 0 0 0 0 0 0 TRDSR1 register

Bit Symbol Bit Name Function R/W

b0 IMFA Input capture / compare match flag A [Source for setting this bit to 0]

Write 0 after read (2)

[Source for setting this bit to 1]

When the value in the TRDi register matches with

the value in the TRDGRAi register.

R/W

b1 IMFB Input capture / compare match flag B [Source for setting this bit to 0]

Write 0 after read (2)

[Source for setting this bit to 1]

When the value in the TRDi register matches with

the value in the TRDGRBi register.

R/W

b2 IMFC Input capture / compare match flag C [Source for setting this bit to 0]

Write 0 after read (2)

[Source for setting this bit to 1]

When the value in the TRDi register matches with

the value in the TRDGRCi register (3).

R/W

b3 IMFD Input capture / compare match flag D [Source for setting this bit to 0]

Write 0 after read (2)

[Source for setting this bit to 1]

When the value in the TRDi register matches with

the value in the TRDGRDi register (3).

R/W

b4 OVF Overflow flag [Source fo r setting this bit to 0]

Write 0 after read (2)

[Source for setting this bit to 1]

When the TRDi register overfl ows.

R/W

b5 UDF Underflow flag (1) This bit is disabled in PWM Mode. R/W

b6 — Nothing is assig ned. If necessary, set to 0. When read, the content is 1. —

b7 —

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 356 of 723

20.5.13 Timer RD Interrupt Enable Register i (TRDIERi) (i = 0 or 1) in PWM Mode

20.5.14 Timer RD PWM Mode Output Level Control Register i (TRDPOCRi) (i = 0 or

1) in PWM Mode

Address 0144h (TRDIER0), 0154h (TRDIER1)

Bitb7b6b5b4b3b2b1b0

Symbol — — — OVIE IMIED IMIEC IMIEB IMIEA

After Reset11100000

Bit Symbol Bit Name Function R/W

b0 IMIEA Input capture/compare match interrupt

enable bit A 0: Disable interrupt (IMIA) by the IMFA bit

1: Enable interrupt (IMIA) by the IMFA bit R/W

b1 IMIEB Input capture/compare match interrupt

enable bit B 0: Disable interrupt (IMIB) by the IMFB bit

1: Enable interrupt (IMIB) by the IMFB bit R/W

b2 IMIEC Input capture/compare match interrupt

enable bit C 0: Disable interrupt (IMIC) by the IMFC bit

1: Enable interrupt (IMIC) by the IMFC bit R/W

b3 IMIED Input capture/compare match interrupt

enable bit D 0: Disable interrupt (IMID) by the IMFD bit

1: Enable interrupt (IMID) by the IMFD bit R/W

b4 OVIE Overflow/underflow interrupt enable

bit 0: Disable interrupt (OVI) by the OVF bit

1: Enable interrupt (OVI) by the OVF bit R/W

b5 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. —

b6 —

b7 —

Address 0145h (TRDPOCR0), 0155h (TRDPOCR1)

Bitb7b6b5b4b3b2b1b0

Symbol — — — — — POLD POLC POLB

After Reset11111000

Bit Symbol Bit Name Function R/W

b0 POLB PWM mode output level control bit B 0: “L” active TRDIOBi output level is selected

1: “H” active TRDIOBi output level is selected R/W

b1 POLC PWM mode output level control bit C 0: “L” active TRDIOCi output level is selected

1: “H” active TRDIOCi output level is selected R/W

b2 POLD PWM mode output level control bit D 0: “L” active TRDIODi output level is selected

1: “H” active TRDIODi output level is selected R/W

b3 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. —

b4 —

b5 —

b6 —

b7 —

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 357 of 723

20.5.15 Timer RD Counter i (TRDi) (i = 0 or 1) in PWM Mode

Access the TRDi register in 16-bit units. Do not access it in 8-bit units.

20.5.16 Timer RD General Registers Ai, Bi, Ci, and Di (TRDGRAi, TRDGRBi,

TRDGRCi, TRDGRDi) (i = 0 or 1) in PWM Mode

Access registers TRDGRAi to TRDGRDi in 16-bit units. Do not access them in 8-bit units.

The following registers are disabled in the PWM mode: TRDDF0, TRDDF1, TRDIORA0, TRDIORC0,

TRDIORA1, and TRDIORC1.

i = 0 or 1

BFCi, BFDi: Bits in TRDMR register

Address 0147h to 0146h (TRD0), 0157h to 0156h (TRD1)

Bitb7b6b5b4b3b2b1b0

Symbol————————

After Reset00000000

Bit b15 b14 b13 b12 b11 b10 b9 b8

Symbol————————

After Reset00000000

Bit Function Setting Range R/W

b15 to b0 Count the count source. Coun t operation is incremented.

When an overflow occurs, the OVF bit in the TRDSRi register is set to 1. 0000h to FFFFh R/W

Address 0149h to 0148h (TRDGRA0), 014Bh to 014Ah (TRDGRB0),

014Dh to 014Ch (TRDGRC0), 014Fh to 014Eh (TRDGRD0),

0159h to 0158h (TRDGRA1), 015Bh to 015Ah (TRDGRB1),

015Dh to 015Ch (TRDGRC1), 015Fh to 015Eh (TRDGRD1)

Bitb7b6b5b4b3b2b1b0

Symbol————————

After Reset11111111

Bit b15 b14 b13 b12 b11 b10 b9 b8

Symbol————————

After Reset11111111

Bit Function R/W

b15 to b0 Refer to Table 20.10 TRDGRji Register Functions in PWM Mode R/W

Table 20.10 TRDGRji Register Functions in PWM Mode

TRDGRAi −General register. Set the PWM period −

TRDGRBi −General register. Set the changing point of PWM output TRDIOBi

TRDGRCi BFCi = 0 General register. Set the changing po int of PWM output TRDIOCi

TRDGRDi BFDi = 0 TRDIOD i

TRDGRCi BFCi = 1 Buffer register . Set the ne xt PWM per iod

(Refer to 20.2.2 Buffer Operation.) −

TRDGRDi BFDi = 1 Buffer register. Set the changing point of the next PWM

output

(Refer to 20.2.2 Buffer Operation.)

TRDIOBi

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 358 of 723

20.5.17 Timer RD Pin Select Register 0 (TRDPSR0)

The TRDPSR0 register selects which pin is assigned to the timer RD I/O. To use the I/O pin for timer RD, set

this register.

Set the TRDPSR0 register before setting the timer RD associated registers. Also, do not change the setting

value in this register during timer RD operation.

20.5.18 Timer RD Pin Select Register 1 (TRDPSR1)

The TRDPSR1 register selects which pin is assigned to the timer RD I/O. To use the I/O pin for timer RD, set

this register.

Set the TRDPSR1 register before setting the timer RD associated registers. Also, do not change the setting

value in this register during timer RD operation.

Address 0184h

Bitb7b6b5b4b3b2b1b0

Symbol — TRDIOD0SEL0 TRDIOC0SEL1 TRDIOC0SEL0 TRDIOB0SEL1 TRDIOB0SEL0 — TRDIOA0SEL0

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 TRDIOA0SEL0 TRDIOA0/TRDCLK pin select bit 0: TRDIOA0/TRDCLK pin not used

1: P2_0 assigned R/W

b1 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b2 TRDIOB0SEL0 TRDIOB0 pin select bit b3 b2

0 0: TRDIOB0 pin not used

0 1: Do not set.

1 0: P2_2 assigned

1 1: Do not set.

R/W

b3 TRDIOB0SEL1 R/W

b4 TRDIOC0SEL0 TRDIOC0 pin select bit b5 b4

0 0: TRDIOC0 pin not used

0 1: Do not set.

1 0: P2_1 assigned

1 1: Do not set.

R/W

b5 TRDIOC0SEL1 R/W

b6 TRDIOD0SEL0 TRDIOD0 pin select bit 0: TRDIOD0 pin not used

1: P2_3 assigned R/W

b7 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

Address 0185h

Bitb7b6b5b4b3b2b1b0

Symbol — TRDIOD1SEL0 — TRDIOC1SEL0 — TRDIOB1SEL0 — TRDIOA1SEL0

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 TRDIOA1SEL0 TRDIOA1 pin select bit 0: TRDIOA1 pin not used

1: P2_4 assigned R/W

b1 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b2 TRDIOB1SEL0 TRDIOB1 pin select bit 0: TRDIOB1 pin not used

1: P2_5 assigned R/W

b3 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b4 TRDIOC1SEL0 TRDIOC1 pin select bit 0: TRDIOC1 pin not used

1: P2_6 assigned R/W

b5 — Reserved bit Set to 0. R/W

b6 TRDIOD1SEL0 TRDIOD1 pin select bit 0: TRDIOD1 pin not used

1: P2_7 assigned R/W

b7 — Reserved bit Set to 0. R/W

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 359 of 723

20.5.19 Operating Example

Figure 20.15 Operating Example of PWM Mode

Value in TRDi register

Count source

m+1

n+1

TRDIOCi outpu t

m-n

p+1 m-p

m-qq+1

TRDIODi output

m: Value set in TRDGRAi register

n: Value set in TRDGRBi register

p: Value set in TRDGRCi register

q: Value set in TRDGRDi register

Inactive level “L”

Active level “H”

Inactive level “H”

Active level “L”

Set to 0 by a program Set to 0 by a program

Set to 0 by a program

TRDIOBi output

IMFA bit in

TRDSRi register

IMFB bit in

TRDSRi register

IMFC bit in

TRDSRi register

IMFD bit in

TRDSRi register

i = 0 or 1

Set to 0 by a program

The above applies under th e foll owing condi t ions:

Bits BFCi and BFDi in the TRDMR register are set t o 0 (registers TRDG RCi and TRDG RDi are not used as buf f er registers).

Bits EBi, ECi and EDi in the TRDOER1 register are set to 0 (enable TRDIOBi , TRDI OC i and TRDIO Di pin outpu ts).

Bits TOBi and TOCi in the T RDOCR regis ter are set t o 0 (inact iv e level), the TO Di bit is se t t o 1 (acti ve level ).

The POLB bit in the TR DPOCRi regist er is set to 1 (acti ve leve l “H”), bit s POLC and POL D are set to 0 (active l evel “L”).

Initial out put “L”

to compare match

Initial output “H”

to compare match

Initia l out put “L”

to compare match

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 360 of 723

Figure 20.16 Operating Example of PWM Mode (Duty 0%, Duty 100%)

Value in TRDi register

m: Value set in TRDGRAi register

Set to 0 by a program

Rewrite by a program

0000h

Duty 0%

TRDGRBi register

IMFA bit in

TRDSRi register

IMFB bit in

TRDSRi register

TSTARTi bit in

TRDSTR regi ster

TRDIOBi outp ut

p (p>m)n

Since no compare match in the TRDGRBi register is

generated, “L” is not applied to the TRDIOBi out put

Value in TRDi register

0000h

TRDGRBi register

IMFA bit in

TRDSRi register

IMFB bit in

TRDSRi register

TSTARTi bit in

TRDSTR regi ster

TRDIOBi outp ut

“L” is appli ed to TRDIOBi output by compare match

with the TRDGRBi register wit h no change.

i = 0 or 1

The above applies under the following conditions:

The EBi bit in the TRDO ER1 register is set to 0 (ena ble TRDIOBi output).

The POLB bit in the TRDPOCRi register is set to 0 (active level “L”).

Rewrite by a program

Set to 0 by a program

When compare m at c hes wit h regi st e rs T RDGRAi and TRDGRBi are gene rat ed

simultaneously, the compare match with the TRDGRBi register has priority.

“L” is applie d to the T RDIOBi output without any change.

Duty 100%

Set to 0 by a program

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 361 of 723

20.5.20 A/D Trigger Generation

A compare match signal with registers TRDi (i = 0 or 1) and TRDGRji (j = A, B, C, or D) can be used as the

conversion start trigger of the A/D converter.

The TRDADCR register is used to select which compare match is used.

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 362 of 723

20.6 Reset Synchronous PWM Mode

In this mode, 3 normal-phases and 3 counter-phases of the PWM waveform are output with the same period (three-

phase, sawtooth wave modulati on, and no dead time).

Figure 20.17 shows a Block Diagram of Reset Synchronous PWM Mode, and Table 20.11 lists the Reset

Synchronous PWM Mode Specificatio ns. Figure 20.18 shows an Operating Example of Reset Sy nchronous PWM

Mode.

Refer to Figure 20.16 Operating Example of PWM Mode (Duty 0 %, Duty 100%) for an operating example of

PWM Mode with duty 0% and duty 100%.

Figure 20.17 Block Diagram of Reset Synchronous PWM Mode

Period TRDIOC0

TRDIOB0

TRDIOD0

TRDIOA1

TRDIOC1

TRDIOB1

TRDIOD1

PWM1

PWM2

PWM3

Waveform control

TRDGRB0

TRDGRA1

TRDGRB1

Normal-phase

Counter-phase

TRDGRA0

TRDGRD0

TRDGRC1

TRDGRD1

TRDGRC0

Buffer (1)

Normal-phase

Counter-phase

Normal-phase

Counter-phase

Note:

1.When bits BFC0, BFD0, BFC1, and BFD1 in the TRDMR register are set to 1 (buffer register).

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 363 of 723

j = A, B, C, or D

Table 20.11 Reset Synchronous PWM Mode Specifications

Item Specification

Count sources f1, f2, f4, f8, f32, fOCO40M, fOCO-F

External signal input to the TRDCLK pin (valid edge selected by a

program)

Count operations The TRD0 register is incremented (the TRD1 register is not used).

PWM waveform PWM period : 1/fk × (m+1)

Active level width of normal-phase: 1/fk × (m-n)

Active level width of counter-phase: 1/fk × (n+1)

fk: Frequency of count source

m: Value set in the TRDGRA0 register

n: Value set in the TRDGRB0 register (PWM1 output),

Value set in the TRDGRA1 register (PWM2 output),

Value set in the TRDGRB1 register (PWM3 output)

Count start condition 1 (count starts) is written to the TSTART0 bit in the TRDSTR register.

Count stop conditions • 0 (count stops) is written to the TSTART0 bit in the TRDSTR register

when the CSEL0 bit in the TRDSTR register is set to 1.

The PWM output pin holds output level before the count stops.

• When the CSEL0 bit in the TRDSTR register is set to 0, th e co un t

stops at the compare match in the TRDGRA0 register.

The PWM output pin holds level after output change at compare

match.

Interrupt request generation

timing • Compare match (The content of the TRD0 register matches content

of registers TRDGRj0, TRDGRA1, and TRDGRB1)

• The TRD0 register overflows

TRDIOA0 pin function Programmable I/O port or TRDCLK (external clock) input

TRDIOB0 pin function PWM1 output normal-phase output

TRDIOD0 pin function PWM1 output counter-phase output

TRDIOA1 pin function PWM2 output normal-phase output

TRDIOC1 pin function PWM2 output counter-phase output

TRDIOB1 pin function PWM3 output normal-phase output

TRDIOD1 pin function PWM3 output counter-phase output

TRDIOC0 pin function Output inverted every PWM period

INT0 pin function Programmable I/O port, pulse output forced cutoff signal input, or

INT0 interrupt input

Read from timer The count value can be read by reading the TRD0 register.

Write to timer The v alue ca n be written to the TRD0 register.

Selectable functions • The normal-phase and counter-phase active level and initial output

level are selected individually.

• Buffer operation (Refer to 20.2.2 Buffer Op era ti on .)

• Pulse output forced cutoff signal input (Refer to 20.2.4 Pulse

Output Forced Cutoff.)

• A/D trigger generation

m+1

Normal-phase

n+1 (When “L” is selected as the active level)

Counter-phase

m-n

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 364 of 723

20.6.1 Module Standby Control Register (MSTCR)

Notes:

1. When the MSTIIC bit is set to 1 (standby), any access to the SSU or the I2C bus associated registers (addresses

0193h to 019Dh) is disabled.

2. When the MSTTRD bi t is set to 1 (stand by), any acce ss to the ti mer RD associated regi sters (addresse s 0135h

to 015Fh) is disabled.

3. To set the MSTTRD bit to 1 (standby), set bits TCK2 to TCK0 in the TRDCRi (i = 0 or 1) register to 000b (f1).

4. When the MSTTRC bi t is set to 1 (stand by), any acce ss to the time r RC associated registers (addresses 0120h

to 0133h) is disabled.

20.6.2 Timer RD Control Expansion Register (TRDECR)

Note:

1. Enabled when in time r mode.

Address 0008h

Bitb7b6b5b4b3b2b1b0

Symbol — — MSTTRC MSTTRD MSTIIC — — —

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b1 —

b2 —

b3 MSTIIC SSU, I2C bus standby bit 0: Active

1: Standby (1) R/W

b4 MSTTRD Timer RD standby bit 0: Active

1: Standby (2, 3) R/W

b5 MSTTRC Timer RC standby bit 0: Active

1: Standby (4) R/W

b6 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b7 —

Address 0135h

Bitb7b6b5b4b3b2b1b0

Symbol ITCLK1 — — — ITCLK0 — — —

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b1 —

b2 —

b3 ITCLK0 Timer RD0 fC2 select bit 0: TRDCLK input selected

1: fC2 selected (1) R/W

b4 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b5 —

b6 —

b7 ITCLK1 Timer RD1 fC2 select bit 0: TRDCLK input selected

1: fC2 selected (1) R/W

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 365 of 723

20.6.3 Timer RD Trigger Control Register (TRDADCR)

Address 0136h

Bitb7b6b5b4b3b2b1b0

Symbol ADTRGD1E ADTRGC1E ADTRGB1E ADTRGA1E ADTRGD0E ADTRGC0E ADTRGB0E ADTRGA0E

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 ADTRGA0E A/D trigger A0 enable bit 0: A/D trigger disabled

1: A/D trigger generated at compare match with

registers TRD0 and TRDGRB0

R/W

b1 ADTRGB0E A/D trigger B0 enable bit 0: A/D trigger disabled

1: A/D trigger generated at compare match with

registers TRD0 and TRDGRB0

R/W

b2 ADTRGC0E A/D trigger C0 enable bit 0: A/D trigger disabled

1: A/D trigger generated at compare match with

registers TRD0 and TRDGRC0

R/W

b3 ADTRGD0E A/D trigger D0 enable bit 0: A/D trigger disabled

1: A/D trigger generated at compare match with

registers TRD0 and TRDGRD0

R/W

b4 ADTRGA1E A/D trigger A1 enable bit 0: A/D trigger disabled

1: A/D trigger generated at compare match with

registers TRD1 and TRDGRA1

R/W

b5 ADTRGB1E A/D trigger B1 enable bit 0: A/D trigger disabled

1: A/D trigger generated at compare match with

registers TRD1 and TRDGRB1

R/W

b6 ADTRGC1E A/D trigger C1 enable bit 0: A/D trigger disabled

1: A/D trigger generated at compare match with

registers TRD1 and TRDGRC1

R/W

b7 ADTRGD1E A/D trigger D1 enable bit 0: A/D trigger disabled

1: A/D trigger generated at compare match with

registers TRD1 and TRDGRD1

R/W

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 366 of 723

20.6.4 Timer RD Start Register (TRDSTR) in Reset Synchronous PWM Mode

Notes:

1. When the CSEL0 bit is set to 1, write 0 to the TSTART0 bit.

2. When the CSEL1 bit is set to 1, write 0 to the TSTART1 bit.

3. When the CSEL0 bit is set to 0 and the compare match signal (TRDIOA0) is generated, this bit is set to 0 (count

stops).

4. When the CSEL1 bit is set to 0 and the compare match signal (TRDIOA1) is generated, this bit is set to 0 (count

stops).

Set the TRDSTR register using the MOV instruction (do not use the bi t handling instruction). Refer to 20.10.1

TRDSTR Register of Notes on Timer RD.

20.6.5 Timer RD Mode Register (TRDMR) in Reset Synchronous PWM Mode

Address 0137h

Bitb7b6b5b4b3b2b1b0

Symbol — — — — CSEL1 CSEL0 TSTART1 TSTART0

After Reset11111100

Bit Symbol Bit Name Function R/W

b0 TSTART0 TRD0 count start flag (3) 0: Count stops (1)

1: Count starts R/W

b1 TSTART1 TRD1 count start flag (4) 0: Count stops (2)

1: Count starts R/W

b2 CSEL0 TRD0 count operation select bit 0: Count stops at the compare match with the

TRDGRA0 register

1: Count continues after the compare match with

the TRDGRA0 register

R/W

b3 CSEL1 TRD1 count operation select bit 0: Count stops at the compare match with the

TRDGRA1 register

1: Count continues after the compare match with

the TRDGRA1 register

R/W

b4 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. —

b5 —

b6 —

b7 —

Address 0138h

Bitb7b6b5b4b3b2b1b0

Symbol BFD1 BFC1 BFD0 BFC0 — — — SYNC

After Reset00001110

Bit Symbol Bit Name Function R/W

b0 SYNC Timer RD synchronous bit Set this bit to 0 (registers TRD and TRD1 operate

independently) in reset synchronous PWM mode. R/W

b1 — Nothing is assig ned. If necessary, set to 0. When read, the content is 1. —

b2 —

b3 —

b4 BFC0 TRDGRC0 register function select bit 0: General register

1: Buffer register of TRDGRA0 register R/W

b5 BFD0 TRDGRD0 register function select bit 0: General register

1: Buffer register of TRDGRB0 register R/W

b6 BFC1 TRDGRC1 register function select bit 0: General register

1: Buffer register of TRDGRA1 register R/W

b7 BFD1 TRDGRD1 register function select bit 0: General register

1: Buffer register of TRDGRB1 register R/W

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 367 of 723

20.6.6 Timer RD Function Control Register (TRDFCR) in Reset Synchronous

PWM Mode

Notes:

1. Set bits CMD1 to CMD0 when bo th the TSTART0 and TSTART1 bits are set to 0 (count stops).

2. When bits CMD1 to CMD0 are set to 00b (timer mode, PWM mode, or PWM3 mode), the setting of the PWM3 bit

is enabled.

Address 013Ah

Bitb7b6b5b4b3b2b1b0

Symbol PWM3 STCLK ADEG ADTRG OLS1 OLS0 CMD1 CMD0

After Reset10000000

Bit Symbol Bit Name Function R/W

b0 CMD0 Combination mode select bit (1) Set to 01b (reset synchronous PWM mode) in

reset synchronous PWM mode. R/W

b1 CMD1 R/W

b2 OLS0 Normal-ph ase output level select bit

(in reset synchronous PWM mode or

complementary PWM mode)

0: Initial output “H”, Active level “L”

1: Initial output “L”, Active level “H” R/W

b3 OLS1 Coun ter-phase output level select bit

(in reset synchronous PWM mode or

complementary PWM mode)

R/W

b4 ADTRG A/D trigger enable bit

(in complementary PWM mode) This bit is disabled in reset synchronous PWM

mode. R/W

b5 ADEG A/D trigger edge select bit

(in complementary PWM mode) R/W

b6 STCLK External clock input select bit 0: External clock input disabled

1: External clock input enabled R/W

b7 PWM3 PWM3 mode select bit (2) This bit is disabled in reset synchronous PWM

mode. R/W

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 368 of 723

20.6.7 Timer RD Output Master Enable Register 1 (TRDOER1) in Reset

Synchronous PWM Mode

20.6.8 Timer RD Output Master Enable Register 2 (TRDOER2) in Reset

Synchronous PWM Mode

Note:

1. Refer to 20.2.4 Pulse Output Forced Cutoff.

Address 013Bh

Bitb7b6b5b4b3b2b1b0

Symbol ED1 EC1 EB1 EA1 ED0 EC0 EB0 EA0

After Reset11111111

Bit Symbol Bit Name Function R/W

b0 EA0 TRDIOA0 output disable bit Set this bit to 1 (the TRDIOA0 pin is used as a

programmable I/O port) in reset synchronous PWM

mode.

R/W

b1 EB0 TRDIOB0 output disable bit 0: Enable output

1: Disable output (The TRDIOB0 pin is used as a

programmable I/O port.)

R/W

b2 EC0 TRDIOC0 output disable bit 0: Enable output

1: Disable output (The TRDIOC0 pin is used as a

programmable I/O port.)

R/W

b3 ED0 TRDIOD0 output disable bit 0: Enable output

1: Disable output (The TRDIOD0 pin is used as a

programmable I/O port.)

R/W

b4 EA1 TRDIOA1 output disable bit 0: Enable output

1: Disable output (The TRDIOA1 pin is used as a

programmable I/O port.)

R/W

b5 EB1 TRDIOB1 output disable bit 0: Enable output

1: Disable output (The TRDIOB1 pin is used as a

programmable I/O port.)

R/W

b6 EC1 TRDIOC1 output disable bit 0: Enable output

1: Disable output (The TRDIOC1 pin is used as a

programmable I/O port.)

R/W

b7 ED1 TRDIOD1 output disable bit 0: Enable output

1: Disable output (The TRDIOD1 pin is used as a

programmable I/O port.)

R/W

Address 013Ch

Bitb7b6b5b4b3b2b1b0

SymbolPTO———————

After Reset01111111

Bit Symbol Bit Name Function R/W

b0 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. —

b1 —

b2 —

b3 —

b4 —

b5 —

b6 —

b7 PTO INT0 of pulse output forced cutoff

signal input enabled bit (1) 0: Pulse output forced cutoff input disabled

1: Pulse output forced cutoff input enabled

(All bits in the TRDOER1 register are set to 1

(disable output) when “L” is applied to the INT0

pin.)

R/W

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 369 of 723

20.6.9 Timer RD Control Register 0 (TRDCR0) in Reset Synchronous PWM Mode

Notes:

1. Enabled when the ITCLKi bit in the TRDECR register is set to 0 (TRDCLK input) and the STCLK bit in the

TRDFCR register is 1 (external clock input enabled).

2. Enabled when the ITCLKi bit in the TRDECR register is set to 1 (fC2) in timer mode.

3. Enabled when bits TCK2 to TCK0 are set to 101b (TRDCLK input or fC2), the ITCLKi bit in the TRDECR is set to

0 (TRDCLK input), and the STCLK bit in the TR DFCR register is set to 1 (external clock input enabled).

4. To select fOCO-F, set it to the clock frequency higher than the CPU clock frequency.

The TRDCR1 register is not used in reset synchrono us PWM mode.

Address 0140h

Bitb7b6b5b4b3b2b1b0

Symbol CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TCK2 TCK1 TCK0

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 TCK0 Count source select bit b2 b1 b0

0 0 0: f1

0 0 1: f2

0 1 0: f4

0 1 1: f8

1 0 0: f32

1 0 1: TRDCLK input (1) or fC2 (2)

1 1 0: fOCO40M

1 1 1: fOCO-F (4)

R/W

b1 TCK1 R/W

b2 TCK2 R/W

b3 CKEG0 External clock edge select bit (3) b4 b3

0 0: Count at the rising edge

0 1: Count at the falling edge

1 0: Count at both edges

1 1: Do not set.

R/W

b4 CKEG1 R/W

b5 CCLR0 TRD0 counter clear select bit Set to 001b (TRD0 register cleared at compare match

with TRDGRA0 register) in reset synchronous PWM

mode.

R/W

b6 CCLR1 R/W

b7 CCLR2 R/W

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 370 of 723

20.6.10 Timer RD Status Register i (TRDSRi) (i = 0 or 1) in Reset Synchronous

PWM Mode

Notes:

1. Nothing is assigned to b5 in the TRDSR0 register. When writing to b5, write 0. When reading, the content is 1.

2. The writing results are as follows:

• This bit is set to 0 when the read result is 1 and 0 is written to the same bit.

• This bit remains unchanged even if the read result is 0 and 0 is written to the same bit. (This bit remains 1 even

if it is set to 1 from 0 after reading, and writing 0.)

• This bit remains unchanged if 1 is written to it.

3. Including when the BFji bit in the TRD MR reg ister is set to 1 (TRDGRji is used as the buffer register).

Address 0143h (TRDSR0), 0153h (TRDSR1)

Bitb7b6b5b4b3b2b1b0

Symbol — — UDF OVF IMFD IMFC IMFB IMFA

After Reset 1 1 1 0 0 0 0 0 TRDSR0 register

After Reset 1 1 0 0 0 0 0 0 TRDSR1 register

Bit Symbol Bit Name Function R/W

b0 IMFA Input capture / compare match flag A [Source for setting this bit to 0]

Write 0 after read (2).

[Source for setting this bit to 1]

When the value in the TRDi register matches with

the value in the TRDGRAi register.

R/W

b1 IMFB Input capture / compare match flag B [Source for setting this bit to 0]

Write 0 after read (2).

[Source for setting this bit to 1]

When the value in the TRDi register matches with

the value in the TRDGRBi register.

R/W

b2 IMFC Input capture / compare match flag C [Source for setting this bit to 0]

Write 0 after read (2).

[Source for setting this bit to 1]

When the value in the TRDi register matches with

the value in the TRDGRCi register (3).

R/W

b3 IMFD Input capture / compare match flag D [Source for setting this bit to 0]

Write 0 after read (2).

[Source for setting this bit to 1]

When the value in the TRDi register matches with

the value in the TRDGRDi register (3).

R/W

b4 OVF Overflow flag [Source fo r setting this bit to 0]

Write 0 after read (2).

[Source for setting this bit to 1]

When the TRDi register overfl ows.

R/W

b5 UDF Underflow flag (1) This bit is disabled in reset synchronous PWM

mode. R/W

b6 — Nothing is assig ned. If necessary, set to 0. When read, the content is 1. —

b7 —

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 371 of 723

20.6.11 Timer RD Interrupt Enable Register i (TRDIERi) (i = 0 or 1) in Reset

Synchronous PWM Mode

20.6.12 Timer RD Counter 0 (TRD0) in Reset Synchronous PWM Mode

Access the TRD0 register in 16-bit units. Do not access it in 8-bit units.

The TRD1 register is not used in reset synchronous PWM mode.

Address 0144h (TRDIER0), 0154h (TRDIER1)

Bitb7b6b5b4b3b2b1b0

Symbol — — — OVIE IMIED IMIEC IMIEB IMIEA

After Reset11100000

Bit Symbol Bit Name Function R/W

b0 IMIEA Input capture/compare match interrupt

enable bit A 0: Disable interrupt (IMIA) by the IMFA bit

1: Enable interrupt (IMIA) by the IMFA bit R/W

b1 IMIEB Input capture/compare match interrupt

enable bit B 0: Disable interrupt (IMIB) by the IMFB bit

1: Enable interrupt (IMIB) by the IMFB bit R/W

b2 IMIEC Input capture/compare match interrupt

enable bit C 0: Disable interrupt (IMIC) by the IMFC bit

1: Enable interrupt (IMIC) by the IMFC bit R/W

b3 IMIED Input capture/compare match interrupt

enable bit D 0: Disable interrupt (IMID) by the IMFD bit

1: Enable interrupt (IMID) by the IMFD bit R/W

b4 OVIE Overflow/underflow interrupt enable

bit 0: Disable interrupt (OVI) by the OVF or UDF bit

1: Enable interrupt (OVI) by the OVF or UDF bit R/W

b5 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. —

b6 —

b7 —

Address 0147h to 0146h

Bitb7b6b5b4b3b2b1b0

Symbol————————

After Reset00000000

Bit b15 b14 b13 b12 b11 b10 b9 b8

Symbol————————

After Reset00000000

Bit Function Setting Range R/W

b15 to b0 Count the count source. Coun t operation is incremented.

When an overflow occurs, the OVF bit in the TRDSR0 register is set to 1. 000 0h to FFFFh R /W

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 372 of 723

20.6.13 Timer RD General Registers Ai, Bi, Ci, and Di (TRDGRAi, TRDGRBi,

TRDGRCi, TRDGRDi) (i = 0 or 1) in Reset Synchronous PWM Mode

Access registers TRDGRAi to TRDGRDi in 16-bit units. Do not access them in 8-bit units.

The following registers are disabled in the reset synchronous PWM mode: TRDPMR, TRDOCR, TRDDF0 ,

TRDDF1, TRDIORA0, TRDIORC0, TRDPOCR0, TRDIORA1, TRDIORC1, and TRDPOCR1.

BFC0, BFD0, BFC1, BFD1: Bits in TRDMR register

Address 0149h to 0148h (TRDGRA0), 014Bh to 014Ah (TRDGRB0),

014Dh to 014Ch (TRDGRC0), 014Fh to 014Eh (TRDGRD0),

0159h to 0158h (TRDGRA1), 015Bh to 015Ah (TRDGRB1),

015Dh to 015Ch (TRDGRC1), 015Fh to 015Eh (TRDGRD1)

Bitb7b6b5b4b3b2b1b0

Symbol————————

After Reset11111111

Bit b15 b14 b13 b12 b11 b10 b9 b8

Symbol————————

After Reset11111111

Bit Function R/W

b15 to b0 Refer to Table 20.12 TRDGRji Register Functions in Reset Synchronous PWM Mode R/W

Table 20.12 TRDGRji Register Functions in Reset Synchronous PWM Mode

TRDGRA0 −General register. Set the PWM period. (Output inverted every PWM

period and TRDIOC0 pin)

TRDGRB0 −General register. Set the changing point of

PWM1 output. TRDIOB0

TRDIOD0

TRDGRC0 BFC0 = 0 (These regis te rs ar e no t used in reset

synchronous PWM mode.) −

TRDGRD0 BFD0 = 0

TRDGRA1 −General register. Set the changing point of

PWM2 output. TRDIOA1

TRDIOC1

TRDGRB1 −General register. Set the changing point of

PWM3 output. TRDIOB1

TRDIOD1

TRDGRC1 BFC1 = 0 (These poin ts ar e no t use d in rese t

synchronous PWM mode.) −

TRDGRD1 BFD1 = 0

TRDGRC0 BFC0 = 1 Buffer register. Set the next PWM period.

(Refer to 20.2.2 Buffer Operation.)(Output inverted every PWM

period and TRDIOC0 pin)

TRDGRD0 BFD0 = 1 Buffer register. Set the changing point of

the next PWM1 output.

(Refer to 20.2.2 Buffer Operation.)

TRDIOB0

TRDIOD0

TRDGRC1 BFC1 = 1 Buffer register. Set the changing point of

the next PWM2 output.

(Refer to 20.2.2 Buffer Operation.)

TRDIOA1

TRDIOC1

TRDGRD1 BFD1 = 1 Buffer register. Set the changing point of

the next PWM3 output.

(Refer to 20.2.2 Buffer Operation.)

TRDIOB1

TRDIOD1

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 373 of 723

20.6.14 Timer RD Pin Select Register 0 (TRDPSR0)

The TRDPSR0 register selects which pin is assigned to the timer RD I/O. To use the I/O pin for timer RD, set

this register.

Set the TRDPSR0 register before setting the timer RD associated registers. Also, do not change the setting

value in this register during timer RD operation.

20.6.15 Timer RD Pin Select Register 1 (TRDPSR1)

The TRDPSR1 register selects which pin is assigned to the timer RD I/O. To use the I/O pin for timer RD, set

this register.

Set the TRDPSR1 register before setting the timer RD associated registers. Also, do not change the setting

value in this register during timer RD operation.

Address 0184h

Bitb7b6b5b4b3b2b1b0

Symbol — TRDIOD0SEL0 TRDIOC0SEL1 TRDIOC0SEL0 TRDIOB0SEL1 TRDIOB0SEL0 — TRDIOA0SEL0

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 TRDIOA0SEL0 TRDIOA0/TRDCLK pin select bit 0: TRDIOA0/TRDCLK pin not used

1: P2_0 assigned R/W

b1 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b2 TRDIOB0SEL0 TRDIOB0 pin select bit b3 b2

0 0: TRDIOB0 pin not used

0 1: Do not set.

1 0: P2_2 assigned

1 1: Do not set.

R/W

b3 TRDIOB0SEL1 R/W

b4 TRDIOC0SEL0 TRDIOC0 pin select bit b5 b4

0 0: TRDIOC0 pin not used

0 1: Do not set.

1 0: P2_1 assigned

1 1: Do not set.

R/W

b5 TRDIOC0SEL1 R/W

b6 TRDIOD0SEL0 TRDIOD0 pin select bit 0: TRDIOD0 pin not used

1: P2_3 assigned R/W

b7 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

Address 0185h

Bitb7b6b5b4b3b2b1b0

Symbol — TRDIOD1SEL0 — TRDIOC1SEL0 — TRDIOB1SEL0 — TRDIOA1SEL0

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 TRDIOA1SEL0 TRDIOA1 pin select bit 0: TRDIOA1 pin not used

1: P2_4 assigned R/W

b1 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b2 TRDIOB1SEL0 TRDIOB1 pin select bit 0: TRDIOB1 pin not used

1: P2_5 assigned R/W

b3 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b4 TRDIOC1SEL0 TRDIOC1 pin select bit 0: TRDIOC1 pin not used

1: P2_6 assigned R/W

b5 — Reserved bit Set to 0. R/W

b6 TRDIOD1SEL0 TRDIOD1 pin select bit 0: TRDIOD1 pin not used

1: P2_7 assigned R/W

b7 — Reserved bit Set to 0. R/W

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 374 of 723

20.6.16 Operating Example

Figure 20.18 Operating Example of Reset Synchronous PWM Mode

Initial output “L”

Active level “L”

Value in TRD0 register

Count source

m+1

TRDIOD0 output

m-n

TRDIOD1 output

m: Value set in TRDGRA0 register

n: Value set in TRDGRB0 register

p: Value set in TRDGRA1 register

q: Value set in TRDGRB1 register

Active level “L”

Set to 0 by a program

TRDIOB0 output

IMFA bit in

TRDSR0 register

IMFB bit in

TRDSR0 register

IMFA bit in

TRDSR1 register

IMFB bit in

TRDSR1 register

TSTARTi bit in

TRDSTR register

n+1

TRDIOC1 output

TRDIOA1 output

m-q

m-p

TRDIOB1 output

TRDIOC0 output

p+1

Initial output “H”

i = 0 or 1

The above applies under the following conditions:

Bits OLS1 and OLS0 in the TRDFCR register are set to 0 (initial output level “H”, active level “L”).

0000h

Set to 0 by a program

Set to 0 b y a pr og r a m Set to 0 by a program

Transfer from the buffer register to the

general register during buffer operation Transfer from the buffer register to the

general register during buffer operation

q+1

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 375 of 723

20.6.17 A/D Trigger Generation

A compare match signal with registers TRDi (i = 0 or 1) and TRDGRji (j = A, B, C, or D) can be used as the

conversion start trigger of the A/D converter.

The TRDADCR register is used to select which compare match is used.

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 376 of 723

20.7 Complemen tary PWM Mode

In this mode, 3 normal-phases and 3 counter-phases of the PWM waveform are output with the same period (three-

phase, triangular wave modulation, and with dead tim e).

Figure 20.19 shows a Block Di agram of Complementary PWM Mode, and Table 20.13 lists the Com plementary

PWM Mode Specifications. Figure 20.20 shows Output Model of Complementary PWM Mod e, and Figure 20.21

shows Operating Example of Compleme ntary PWM Mode.

Figure 20.19 Block Diagram of Complementary PWM Mode

Period TRDIOC0

TRDIOB0

TRDIOD0

TRDIOA1

TRDIOC1

TRDIOB1

TRDIOD1

PWM1

PWM2

PWM3

Waveform con trol

TRDGRB0

TRDGRA1

TRDGRB1

Normal-phase

Counter-phase

TRDGRA0

TRDGRD0

TRDGRC1

TRDGRD1

Buffer

Normal-phase

Counter-phase

Normal-phase

Counter-phase

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 377 of 723

i = 0 or 1, j = A, B, C, or D

Note:

1. After a count starts, the PWM period is fixed.

Table 20.13 Complementary PWM Mode Specifications

Item Specification

Count sources f1, f2, f4, f8, f32, fOCO40M, fOCO-F

External signal input to the TRDC LK pin (valid edge selected by a program)

Set bits TCK2 to TCK0 in the TRDCR1 register to the same value (same count

source) as bits TCK2 to TCK0 in the TRDCR0 register.

Count operations Increment or decrement

Registers TRD0 and TRD1 are decremented with the compare match in registers

TRD0 and TRDGRA0 during increment operation. The TRD1 register value is

changed from 0000h to FFFFh during decrement operation, and registers TRD0 and

TRD1 are incremented.

PWM operations PWM period: 1/fk × (m+2-p) × 2 (1)

Dead time: p

Active level width of normal-phase: 1/fk × (m-n-p+1) × 2

Active level width of counter-phase: 1/fk × (n+1-p) × 2

fk: Frequency of count source

m: Value set in the TRDGRA0 register

n: Value set in the TRDGRB0 register (PWM1 output)

Value set in the TRDGRA1 register (PWM2 output)

Value set in the TRDGRB1 register (PWM3 output)

p: Value set in the TRD0 register

Count start condition 1 (count starts) is written to bits TSTART0 and TSTART 1 in the TRDSTR register.

Count stop conditions 0 (count stops) is written to bits TSTART0 and TSTART1 in the TRDSTR register

when the CSEL0 bit in the TRDSTR register is set to 1.

(The PWM output pin holds output level before the count stops.)

Interrupt request generation

timing • Compare match (The content of the TRDi register matches content of the TRDGRji

• The TR D1 register underflows

TRDIOA0 pin function Programmable I/O port or TRDCLK (extern al clock) inpu t

TRDIOB0 pin function PWM1 output normal-phase output

TRDIOD0 pin function PWM1 output counter-phase output

TRDIOA1 pin function PWM2 output normal-phase output

TRDIOC1 pin function PWM2 output counter-phase output

TRDIOB1 pin function PWM3 output normal-phase output

TRDIOD1 pin function PWM3 output counter-phase output

TRDIOC0 pin function Output inverted every 1/2 period of PWM

INT0 pin function Programmable I/O port, pulse output forced cutoff signal input or INT0 interrupt input

Read from timer The count value can be read by reading the TRDi register.

Write to timer The value can be written to the TRDi register.

Selectable functions • Pulse output force d cutoff signal input (Refer to 20.2.4 Pulse Outpu t F orced

Cutoff.)

• The no rmal-phase and counter-phase active level and initial output level are

selected individually.

• Transfer timing fro m the buffer register selection

• A/D trigger gen eration

n+1

Normal-phase

(When “L” is selected as the active level)

Counter-phase

m+2-p

n+1-p pm-p-n+1

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 378 of 723

20.7.1 Module Standby Control Register (MSTCR)

Notes:

1. When the MSTIIC bit is set to 1 (standby), any access to the SSU or the I2C bus associated registers (addresses

0193h to 019Dh) is disabled.

2. When the MSTTRD bi t is set to 1 (stand by), any acce ss to the ti mer RD associated regi sters (addresse s 0135h

to 015Fh) is disabled.

3. To set the MSTTRD bit to 1 (standby), set bits TCK2 to TCK0 in the TRDCRi (i = 0 or 1) register to 000b (f1).

4. When the MSTTRC bi t is set to 1 (stand by), any acce ss to the time r RC associated registers (addresses 0120h

to 0133h) is disabled.

20.7.2 Timer RD Control Expansion Register (TRDECR)

Note:

1. Enabled when in time r mode.

Address 0008h

Bitb7b6b5b4b3b2b1b0

Symbol — — MSTTRC MSTTRD MSTIIC — — —

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b1 —

b2 —

b3 MSTIIC SSU, I2C bus standby bit 0: Active

1: Standby (1) R/W

b4 MSTTRD Timer RD standby bit 0: Active

1: Standby (2, 3) R/W

b5 MSTTRC Timer RC standby bit 0: Active

1: Standby (4) R/W

b6 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b7 —

Address 0135h

Bitb7b6b5b4b3b2b1b0

Symbol ITCLK1 — — — ITCLK0 — — —

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b1 —

b2 —

b3 ITCLK0 Timer RD0 fC2 select bit 0: TRDCLK input selected

1: fC2 selected (1) R/W

b4 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b5 —

b6 —

b7 ITCLK1 Timer RD1 fC2 select bit 0: TRDCLK input selected

1: fC2 selected (1) R/W

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 379 of 723

20.7.3 Timer RD Trigger Control Register (TRDADCR) in Complementary PWM

Mode

Address 0136h

Bitb7b6b5b4b3b2b1b0

Symbol ADTRGD1E ADTRGC1E ADTRGB1E ADTRGA1E ADTRGD0E ADTRGC0E ADTRGB0E ADTRGA0E

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 ADTRGA0E A/D tri gger A0 enable bit Set to 0 in complementary PWM mode. R/W

b1 ADTRGB0E A/D trigger B0 enable bit 0: A/D trigger disabled

1: A/D trigger generated at compare match with

registers TRD0 and TRDGRB0

R/W

b2 ADTRGC0E A/D trigger C0 enable bit 0: A/D trigger disabled

1: A/D trigger generated at compare match with

registers TRD0 and TRDGRC0

R/W

b3 ADTRGD0E A/D trigger D0 enable bit 0: A/D trigger disabled

1: A/D trigger generated at compare match with

registers TRD0 and TRDGRD0

R/W

b4 ADTRGA1E A/D trigger A1 enable bit 0: A/D trigger disabled

1: A/D trigger generated at compare match with

registers TRD1 and TRDGRA1

R/W

b5 ADTRGB1E A/D trigger B1 enable bit 0: A/D trigger disabled

1: A/D trigger generated at compare match with

registers TRD1 and TRDGRB1

R/W

b6 ADTRGC1E A/D trigger C1 enable bit 0: A/D trigger disabled

1: A/D trigger generated at compare match with

registers TRD1 and TRDGRC1

R/W

b7 ADTRGD1E A/D trigger D1 enable bit 0: A/D trigger disabled

1: A/D trigger generated at compare match with

registers TRD1 and TRDGRD1

R/W

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 380 of 723

20.7.4 Timer RD Start Register (TRDSTR) in Complementary PWM Mode

Notes:

1. When the CSEL0 bit is set to 1, write 0 to the TSTART0 bit.

2. When the CSEL1 bit is set to 1, write 0 to the TSTART1 bit.

3. When the CSEL0 bit is set to 0 and the compare match signal (TRDIOA0) is generated, this bit is set to 0 (count

stops).

4. When the CSEL1 bit is set to 0 and the compare match signal (TRDIOA1) is generated, this bit is set to 0 (count

stops).

Set the TRDSTR register using the MOV instruction (do not use the bi t handling instruction). Refer to 20.10.1

TRDSTR Register of Notes on Timer RD.

20.7.5 Timer RD Mode Register (TRDMR) in Complementary PWM Mode

Address 0137h

Bitb7b6b5b4b3b2b1b0

Symbol — — — — CSEL1 CSEL0 TSTART1 TSTART0

After Reset11111100

Bit Symbol Bit Name Function R/W

b0 TSTART0 TRD0 count start flag (3) 0: Count stops (1)

1: Count starts R/W

b1 TSTART1 TRD1 count start flag (4) 0: Count stops (2)

1: Count starts R/W

b2 CSEL0 TRD0 count operation select bit 0: Count stops at the compare match with the

TRDGRA0 register

1: Count continues after the compare match with

the TRDGRA0 register

R/W

b3 CSEL1 TRD1 count operation select bit 0: Count stops at the compare match with the

TRDGRA1 register

1: Count continues after the compare match with

the TRDGRA1 register

R/W

b4 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. —

b5 —

b6 —

b7 —

Address 0138h

Bitb7b6b5b4b3b2b1b0

Symbol BFD1 BFC1 BFD0 BFC0 — — — SYNC

After Reset00001110

Bit Symbol Bit Name Function R/W

b0 SYNC Timer RD synchronous bit Set this bit to 0 (registers TRD0 and TRD1 operate

independently) in complementary PWM mode. R/W

b1 — Nothing is assig ned. If necessary, set to 0. When read, the content is 1. —

b2 —

b3 —

b4 BFC0 TRDGRC0 register function select

bit Set this bit to 0 (general register) in complementary

PWM mode. R/W

b5 BFD0 TRDGRD0 register function select

bit 0: General register

1: Buffer register of TRDGRB0 register R/W

b6 BFC1 TRDGRC1 register function select

bit 0: General register

1: Buffer register of TRDGRA1 register R/W

b7 BFD1 TRDGRD1 register function select

bit 0: General register

1: Buffer register of TRDGRB1 register R/W

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 381 of 723

20.7.6 Timer RD Function Control Register (TRDFCR) in Complementary PWM

Mode

Notes:

1. When setting bits CMD1 to CMD0 to 10b or 11b, the MCU enters complementary PWM mode in spite of the

setting of the TRDPMR register.

2. Set bits CMD1 to CMD0 when both the TS TART 0 and TSTART1 bits in the TRDSTR register are set to 0 (count

stops).

3. Set bits ADCAP1 to ADCAP0 in the ADMOD register to 01b (A/D conversion starts by conversion trigger from

timer RD).

4. When bits CMD1 to CMD0 are set to 00b (timer mode, PWM mode, or PWM3 mode), the setting of the PWM3 bit

is enabled.

Address 013Ah

Bitb7b6b5b4b3b2b1b0

Symbol PWM3 STCLK ADEG ADTRG OLS1 OLS0 CMD1 CMD0

After Reset10000000

Bit Symbol Bit Name Function R/W

b0 CMD0 Combination mode select bit (1, 2) b1 b0

1 0: Complementary PWM mode

(transfer from the buffer register to the

general register at the underflow in the TRD1

1 1: Complementary PWM mode

(transfer from the buffer register to the

general register at the co mpare match with

registers TRD0 and TRDGRA0.)

Other than above: Do not set.

R/W

b1 CMD1 R/W

b2 OLS0 Normal-ph ase output level select bit

(in reset synchronous PWM mode or

complementary PWM mode)

0: Initial output “H”, Active level “L”

1: Initial output “L”, Active level “H” R/W

b3 OLS1 Coun ter-phase output level select bit

(in reset synchronous PWM mode or

complementary PWM mode)

0: Initial output “H”, Active level “L”

1: Initial output “L”, Active level “H” R/W

b4 ADTRG A/D trigger enable bit

(in complementary PWM mode) 0: Disable A/D trigger

1: Enable A/D trigger (3) R/W

b5 ADEG A/D trigger edge select bit

(in complementary PWM mode) 0: A/D trigger is generated at compare match

between registers TRD0 and TRDGRA0

1: A/D trigger is generated at underflow in the

TRD1 register

R/W

b6 STCLK External clock input select bit 0: External clock input disabled

1: External clock input enabled R/W

b7 PWM3 PWM3 mode select bit (4) This bit is disabled in complementary PWM mode. R/W

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 382 of 723

20.7.7 Timer RD Output Master Enable Register 1 (TRDOER1) in Complementary

PWM Mode

20.7.8 Timer RD Output Master Enable Register 2 (TRDOER2) in Complementary

PWM Mode

Note:

1. Refer to 20.2.4 Pulse Output Forced Cutoff.

Address 013Bh

Bitb7b6b5b4b3b2b1b0

Symbol ED1 EC1 EB1 EA1 ED0 EC0 EB0 EA0

After Reset11111111

Bit Symbol Bit Name Function R/W

b0 EA0 TRDIOA0 output disable bit Set this bit to 1 (the TRDIOA0 pin is used as a

programmable I/O port) in complementary PWM

mode.

R/W

b1 EB0 TRDIOB0 output disable bit 0: Enable output

1: Disable output (The TRDIOB0 pin is used as a

programmable I/O port.)

R/W

b2 EC0 TRDIOC0 output disable bit 0: Enable output

1: Disable output (The TRDIOC0 pin is used as a

programmable I/O port.)

R/W

b3 ED0 TRDIOD0 output disable bit 0: Enable output

1: Disable output (The TRDIOD0 pin is used as a

programmable I/O port.)

R/W

b4 EA1 TRDIOA1 output disable bit 0: Enable output

1: Disable output (The TRDIOA1 pin is used as a

programmable I/O port.)

R/W

b5 EB1 TRDIOB1 output disable bit 0: Enable output

1: Disable output (The TRDIOB1 pin is used as a

programmable I/O port.)

R/W

b6 EC1 TRDIOC1 output disable bit 0: Enable output

1: Disable output (The TRDIOC1 pin is used as a

programmable I/O port.)

R/W

b7 ED1 TRDIOD1 output disable bit 0: Enable output

1: Disable output (The TRDIOD1 pin is used as a

programmable I/O port.)

R/W

Address 013Ch

Bitb7b6b5b4b3b2b1b0

SymbolPTO———————

After Reset01111111

Bit Symbol Bit Name Function R/W

b0 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. —

b1 —

b2 —

b3 —

b4 —

b5 —

b6 —

b7 PTO INT0 of pulse output forced cutoff

signal input enabled bit (1) 0: Pulse output forced cutoff input disabled

1: Pulse output forced cutoff input enabled

(All bits in the TRDOER1 register are set to 1

(disable output) when “L” is applied to the INT0

pin.)

R/W

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 383 of 723

20.7.9 Timer RD Control Register i (TRDCRi) (i = 0 or 1) in Complementary PWM

Mode

Notes:

1. Enabled when the ITCLKi bit in the TRDECR register is set to 0 (TRDCLK input) and the STCLK bit in the

TRDFCR register is 1 (external clock input enabled).

2. Enabled when the ITCLKi bit in the TRDECR register is set to 1 (fC2) in timer mode.

3. Set bits TCK2 to TCK0 and bi ts CKEG1 to CKEG0 in registers TRDCR0 and TRDCR1 to the same values.

4. Enabled when bits TCK2 to TCK0 are set to 101b (TRDCLK input or fC2), the ITCLKi bit in the TRDECR is set to

0 (TRDCLK input), and the STCLK bit in the TR DFCR register is set to 1 (external clock input enabled).

5. To select fOCO-F, set it to the clock frequency higher than the CPU clock frequency.

Address 0140h (TRDCR0), 015 0h (TRDCR1)

Bitb7b6b5b4b3b2b1b0

Symbol CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TCK2 TCK1 TCK0

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 TCK0 Count source select bit (3) b2 b1 b0

0 0 0: f1

0 0 1: f2

0 1 0: f4

0 1 1: f8

1 0 0: f32

1 0 1: TRDCLK input (1) or fC2 (2)

1 1 0: fOCO40M

1 1 1: fOCO-F (5)

R/W

b1 TCK1 R/W

b2 TCK2 R/W

b3 CKEG0 External clock edge select bit (3, 4) b4 b3

0 0: Count at the rising edge

0 1: Count at the falling edge

1 0: Count at both edges

1 1: Do not set.

R/W

b4 CKEG1 R/W

b5 CCLR0 TRDi counter clear select bit Set to 000b (disable clearing (free-running operation))

in complementary PWM mode. R/W

b6 CCLR1 R/W

b7 CCLR2 R/W

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 384 of 723

20.7.10 Timer RD Status Register i (TRDSRi) (i = 0 or 1) in Complementary PWM

Mode

Notes:

1. Nothing is assigned to b5 in the TRDSR0 register. When writing to b5, write 0. When reading, the content is 1.

2. The writing results are as follows:

• This bit is set to 0 when the read result is 1 and 0 is written to the same bit.

• This bit remains unchanged even if the read result is 0 and 0 is written to the same bit. (This bit remains 1 even

if it is set to 1 from 0 after reading, and writing 0.)

• This bit remains unchanged if 1 is written to it.

3. Including when the BFji bit in the TRD MR reg ister is set to 1 (TRDGRji is used as the buffer register).

Address 0143h (TRDSR0), 0153h (TRDSR1)

Bitb7b6b5b4b3b2b1b0

Symbol — — UDF OVF IMFD IMFC IMFB IMFA

After Reset 1 1 1 0 0 0 0 0 TRDSR0 register

After Reset 1 1 0 0 0 0 0 0 TRDSR1 register

Bit Symbol Bit Name Function R/W

b0 IMFA Input capture / compare match flag A [Source for setting this bit to 0]

Write 0 after read (2).

[Source for setting this bit to 1]

When the value in the TRDi register matches with

the value in the TRDGRAi register.

R/W

b1 IMFB Input capture / compare match flag B [Source for setting this bit to 0]

Write 0 after read (2).

[Source for setting this bit to 1]

When the value in the TRDi register matches with

the value in the TRDGRBi register.

R/W

b2 IMFC Input capture / compare match flag C [Source for setting this bit to 0]

Write 0 after read (2).

[Source for setting this bit to 1]

When the value in the TRDi register matches with

the value in the TRDGRCi register (3).

R/W

b3 IMFD Input capture / compare match flag D [Source for setting this bit to 0]

Write 0 after read (2).

[Source for setting this bit to 1]

When the value in the TRDi register matches with

the value in the TRDGRDi register (3).

R/W

b4 OVF Overflow flag [Source fo r setting this bit to 0]

Write 0 after read (2).

[Source for setting this bit to 1]

When the TRDi register overfl ows.

R/W

b5 UDF Underflow flag (1) [Source for setting this bit to 0]

Write 0 after read (2).

[Source for setting this bit to 1]

When the TRD1 register underflo ws.

R/W

b6 — Nothing is assig ned. If necessary, set to 0. When read, the content is 1. —

b7 —

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 385 of 723

20.7.11

Timer RD Interrupt Enable Register i (TRDIERi) (i = 0 or 1) in Complementary

PWM Mode

Address 0144h (TRDIER0), 0154h (TRDIER1)

Bitb7b6b5b4b3b2b1b0

Symbol — — — OVIE IMIED IMIEC IMIEB IMIEA

After Reset11100000

Bit Symbol Bit Name Function R/W

b0 IMIEA Input capture/compare match interrupt

enable bit A 0: Disable interrupt (IMIA) by the IMFA bit

1: Enable interrupt (IMIA) by the IMFA bit R/W

b1 IMIEB Input capture/compare match interrupt

enable bit B 0: Disable interrupt (IMIB) by the IMFB bit

1: Enable interrupt (IMIB) by the IMFB bit R/W

b2 IMIEC Input capture/compare match interrupt

enable bit C 0: Disable interrupt (IMIC) by the IMFC bit

1: Enable interrupt (IMIC) by the IMFC bit R/W

b3 IMIED Input capture/compare match interrupt

enable bit D 0: Disable interrupt (IMID) by the IMFD bit

1: Enable interrupt (IMID) by the IMFD bit R/W

b4 OVIE Overflow/underflow interrupt enable

bit 0: Disable interrupt (OVI) by the OVF or UDF bit

1: Enable interrupt (OVI) by the OVF or UDF bit R/W

b5 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. —

b6 —

b7 —

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 386 of 723

20.7.12 Timer RD Counter 0 (TRD0) in Complementary PWM Mode

Access the TRD0 register in 16-bit units. Do not access it in 8-bit units.

20.7.13 Timer RD Counter 1 (TRD1) in Complementary PWM Mode

Access the TRD1 register in 16-bit units. Do not access it in 8-bit units.

Address 0147h to 0146h

Bitb7b6b5b4b3b2b1b0

Symbol————————

After Reset00000000

Bit b15 b14 b13 b12 b11 b10 b9 b8

Symbol————————

After Reset00000000

Bit Function Setting Range R/W

b15 to b0 Set the dead time.

Count a count source. Count operation is incremented or decremented.

When an overflow occurs, the OVF bit in the TRDSR0 register is set to 1.

0000h to FFFFh R/W

Address 0157h to 0156h

Bitb7b6b5b4b3b2b1b0

Symbol————————

After Reset00000000

Bit b15 b14 b13 b12 b11 b10 b9 b8

Symbol————————

After Reset00000000

Bit Function Setting Range R/W

b15 to b0 Set 0000h.

Count a count source. Count operation is incremented or decremented.

When an underflow occurs, the UDF bit in the TRDSR1 register is set to 1.

0000h to FFFFh R/W

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 387 of 723

20.7.14 Timer RD General Registers Ai, Bi, C1, and Di (TRDGRAi, TRDGRBi,

TRDGRC1, TRDGRDi) (i = 0 or 1) in Complementary PWM Mode

Access registers TRDGRAi to TRDGRDi in 16-bit units. Do not access them in 8-bit units.

The TRDGRC0 register is not used in complementary PWM mode.

The following registers are dis abled in the complementary PWM mode: TRDPMR, TRDOCR, TRDDF0,

TRDDF1, TRDIORA0, TRDIORC0, TRDPOCR0, TRDIORA1, TRDIORC1, and TRDPOCR1.

Address 0149h to 0148h (TRDGRA0), 014Bh to 014Ah (TRDGRB0),

014Fh to 014Eh (TRDGRD0),

0159h to 0158h (TRDGRA1), 015Bh to 015Ah (TRDGRB1),

015Dh to 015Ch (TRDGRC1), 015Fh to 015Eh (TRDGRD1)

Bitb7b6b5b4b3b2b1b0

Symbol————————

After Reset11111111

Bit b15 b14 b13 b12 b11 b10 b9 b8

Symbol————————

After Reset11111111

Bit Function R/W

b15 to b0 Refer to Table 20.14 TRDGRji Register Functions in Complementary PWM Mo de R/W

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 388 of 723

BFD0, BFC1, BFD1: Bits in TRDMR register

Since values cannot be written to the TRDGRB0, TRDGRA1, or TRDGRB1 register directly after count

operation starts (prohibited item), use the TRDGRD0, TRDGRC1, or TRDGRD1 register as a buffer register.

However, to write data to the TRDGRD0, TRDGRC1, or TRDGRD1 register, set bits BFD0, BFC1, and BFD1

to 0 (general register). After this, bits BFD0, BFC1, and BFD1 may be set to 1 (buffer register).

Table 20.14 TRDGRji Register Functions in Complementary PWM Mode

TRDGRA0 −General register. Set the PWM period at initialization.

Setting range: Setting value or above in TRD0 register

FFFFh - TRD0 register settin g value or below

Do not write to this register when the TSTART0 and TSTART1

bits in the TRDSTR register are set to 1 (count starts).

(Output inverted every half

period of TRDIOC0 pin)

TRDGRB0 −General register. Set the changing point of PWM1 output at

initialization.

Setting range: Setting value or above in TRD0 register

TRDGRA0 register - TRD0 register setting

value or below

Do not write to this register when the TSTART0 and TSTART1

bits in the TRDSTR register are set to 1 (count starts).

TRDIOB0

TRDIOD0

TRDGRA1 −General register. Set the changing point of PWM2 output at

initialization.

Setting range: Setting value or above in TRD0 register

TRDGRA0 register - TRD0 register setting

value or below

Do not write to this register when the TSTART0 and TSTART1

bits in the TRDSTR register are set to 1 (count starts).

TRDIOA1

TRDIOC1

TRDGRB1 −General register. Set the changing point of PWM3 output at

initialization.

Setting range: Setting value or above in TRD0 register

TRDGRA0 register - TRD0 register setting

value or below

Do not write to this register when the TSTART0 and TSTART1

bits in the TRDSTR register are set to 1 (count starts).

TRDIOB1

TRDIOD1

TRDGRC0 −This register is not used in complementary PWM mode. −

TRDGRD0 BFD0 = 1 Buffer register. Set the changing point of next PWM1 output.

(Refer to 20.2.2 Buffer Operation.)

Setting range: Setting value or above in TRD0 register

TRDGRA0 register - TRD0 register setting

value or below

Set this register to the same value as the TRDGRB0 register

for initialization.

TRDIOB0

TRDIOD0

TRDGRC1 BFC1 = 1 Buffer register. Set the changing point of next PWM2 output.

(Refer to 20.2.2 Buffer Operation.)

Setting range: Setting value or above in TRD0 register

TRDGRA0 register - TRD0 register setting

value or below

Set this register to the same value as the TRDGRA1 register

for initialization.

TRDIOA1

TRDIOC1

TRDGRD1 BFD1 = 1 Buffer register. Set the changing point of next PWM3 output.

(Refer to 20.2.2 Buffer Operation.)

Setting range: Setting value or above in TRD0 register

TRDGRA0 register - TRD0 register setting

value or below

Set this register to the same value as the TRDGRB1 register

for initialization.

TRDIOB1

TRDIOD1

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 389 of 723

20.7.15 Timer RD Pin Select Register 0 (TRDPSR0)

The TRDPSR0 register selects which pin is assigned to the timer RD I/O. To use the I/O pin for timer RD, set

this register.

Set the TRDPSR0 register before setting the timer RD associated registers. Also, do not change the setting

value in this register during timer RD operation.

20.7.16 Timer RD Pin Select Register 1 (TRDPSR1)

The TRDPSR1 register selects which pin is assigned to the timer RD I/O. To use the I/O pin for timer RD, set

this register.

Set the TRDPSR1 register before setting the timer RD associated registers. Also, do not change the setting

value in this register during timer RD operation.

Address 0184h

Bitb7b6b5b4b3b2b1b0

Symbol — TRDIOD0SEL0 TRDIOC0SEL1 TRDIOC0SEL0 TRDIOB0SEL1 TRDIOB0SEL0 — TRDIOA0SEL0

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 TRDIOA0SEL0 TRDIOA0/TRDCLK pin select bit 0: TRDIOA0/TRDCLK pin not used

1: P2_0 assigned R/W

b1 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b2 TRDIOB0SEL0 TRDIOB0 pin select bit b3 b2

0 0: TRDIOB0 pin not used

0 1: Do not set.

1 0: P2_2 assigned

1 1: Do not set.

R/W

b3 TRDIOB0SEL1 R/W

b4 TRDIOC0SEL0 TRDIOC0 pin select bit b5 b4

0 0: TRDIOC0 pin not used

0 1: Do not set.

1 0: P2_1 assigned

1 1: Do not set.

R/W

b5 TRDIOC0SEL1 R/W

b6 TRDIOD0SEL0 TRDIOD0 pin select bit 0: TRDIOD0 pin not used

1: P2_3 assigned R/W

b7 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

Address 0185h

Bitb7b6b5b4b3b2b1b0

Symbol — TRDIOD1SEL0 — TRDIOC1SEL0 — TRDIOB1SEL0 — TRDIOA1SEL0

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 TRDIOA1SEL0 TRDIOA1 pin select bit 0: TRDIOA1 pin not used

1: P2_4 assigned R/W

b1 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b2 TRDIOB1SEL0 TRDIOB1 pin select bit 0: TRDIOB1 pin not used

1: P2_5 assigned R/W

b3 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b4 TRDIOC1SEL0 TRDIOC1 pin select bit 0: TRDIOC1 pin not used

1: P2_6 assigned R/W

b5 — Reserved bit Set to 0. R/W

b6 TRDIOD1SEL0 TRDIOD1 pin select bit 0: TRDIOD1 pin not used

1: P2_7 assigned R/W

b7 — Reserved bit Set to 0. R/W

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 390 of 723

20.7.17 Operating Example

Figure 20.20 Output Model of Complementary PWM Mode

Value in TRDi register

TRDIOD0 output

0000h

Value in TRDGRA0

Value in TRDGRB0

Value in TRDGRA1

Value in TRDGRB1

TRDIOB0 output

TRDIOC1 output

TRDIOA1 output

TRDIOD1 output

TRDIOB1 output

TRDIOC0 output

Value in TRD0 register

Value in TRD1 register

i = 0 or 1

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 391 of 723

Figure 20.21 Operating Example of Complementary PWM Mode

m+2-p

n+1

n+1-p pn+1-p

m-p-n+1

Value in TRDi register

Count source

TRDIOD0 output

m: Value set in TRDGRA0 register

n: Value set in TRDGRB0 register

p: Value set in TRD0 register

TRDIOB0 output

IMFA b it in

TRDSR0 register

TRDGRB0 register

Bits TSTART0 and TSTART1

in TRDSTR register

TRDIOC0 output

0000h

m+1

(m-p-n+1) × 2

Width of normal-

phase active level

Dead

time (n+1-p) × 2

Width of counter-phase active level

Set to

FFFFh

UDF bit in

TRDSR1 register

Following data

Modify with a program

TRDGRD0 register

Transfer (when bits CMD1 to CMD0 are set to 11b) Transfer (when bits CMD1 to CMD0

are set to 10b)

Value in TRD1 register

Value in TRD0 register

CMD0, CMD1: Bits in TRDFCR register

i = 0 or 1

The above applies under the following conditions:

Bits OLS1 and OLS0 in TRDFCR are set to 0 (initial output level “H”, active level “L” for normal-phase and counter-phase)

Set to 0 by a program

Active level “L”

Initial ou tp ut “H”

Set to 0 by a program

IMFB b it in

TRDSR0 register

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 392 of 723

20.7.18 Transfer Timing from Buffer Register

• Transfer from the TRDGRD0, TRDGRC1, or TRDGRD1 register to the TRDGRB0, TRDGRA1, or

TRDGRB1 register.

When bits CMD1 to CMD0 in the TRDFCR register are set to 10b, the content is transferred when the TRD1

When bits CMD1 to CMD0 are set to 11b, the content is transferred at compare match between registers

TRD0 and TRDGRA0.

20.7.19 A/D Trigger Generation

Compare match between registers TRD0 and TRDGRA0 and TRD1 underflow can be used as the conversion

start trigger of the A/D converter.

Use bits ADEG and ADTRG in the TRDFCR register and the TRDADCR register to make settings.

In addition, set bits ADCAP1 to ADCAP0 in the ADMOD register to 01b (A/D conversion starts by conversion

trigger from timer RD).

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 393 of 723

20.8 PWM3 Mode

In this mode, 2 PWM waveforms are output with the same period.

Figure 20.22 shows a Block Diagram of PWM3 Mode, and Table 20.15 lists the PWM3 Mode Specifications.

Figure 20.23 shows an Operating Example of PWM3 Mode.

Figure 20.22 B lock Diagram of PWM3 Mode

TRDIOA0 Output

control

TRDGRC0

Compare match signal

TRDIOB0 Output

control

Comparator TRDGRA0TRD0

TRDGRC1

Compare match signal

Comparator TRDGRA1

TRDGRD0Comparator TRDGRB0

TRDGRD1Comparator TRDGRB1

Compare match signal

Buffer

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 394 of 723

i = 0 or 1, j = A, B, C, or D

Table 20.15 PWM3 Mode Specifications

Item Specification

Count sources f1, f2, f4, f8, f32, fOCO40M, fOCO-F

Count operations The TRD0 register is incremented (th e TRD1 is not used).

PWM waveform PWM period: 1/fk × (m+1)

Active level width of TRDIOA0 output: 1/fk × (m-n)

Active level width of TRDIOB0 output: 1/fk × (p-q)

fk:Frequency of count source

m:Value set in the TRDGRA0 register

n: Value set in the TRDGRA1 register

p: Value set in the TRDGRB0 register

q: Value set in the TRDGRB1 register

Count start condition 1 (count starts) is written to the TSTART0 bit in the TRDSTR r egister.

Count stop conditions • 0 (count stops) is written to the TSTART0 bit in the TRDSTR

The PWM output pin holds output level before the count stops.

• When the CSEL0 bit in the TRDSTR register is set to 0, the count

stops at compare match with the TRDGRA0 register.

The PWM output pin holds level after output change by compare

match.

Interrupt request generation

timing • Compare match (The content of the TRDi register matches content

of the TRDGRji register.)

• The TRD0 register overflows

TRDIOA0, TRDIOB0 pin

functions PW M ou tp ut

TRDIOC0, TRDIOD0, TRDIOA1

to TRDIOD1 pin functions Programmable I/O port

INT0 pin function Programmable I/O port, pulse output forced cutoff signal input, or

INT0 interrupt input

Read from timer The count value can be read by reading the TRD0 register.

Write to timer The value can be written to the TRD0 register.

Selectable functions • Pulse output forced cutoff signal input (Refer to 20.2.4 Pulse

Output Forced Cutoff.)

• Buffer operation (Refer to 20.2.2 Buffer Operation.)

• Active level selectable for each pin

• A/D trigger generation

m+1

TRDIOA0 out pu t

TRDIOB0 out pu t

(When “H” is selected as the active level)

p-q

m-n

n+1

p+1

q+1

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 395 of 723

20.8.1 Module Standby Control Register (MSTCR)

Notes:

1. When the MSTIIC bit is set to 1 (standby), any access to the SSU or the I2C bus associated registers (addresses

0193h to 019Dh) is disabled.

2. When the MSTTRD bi t is set to 1 (stand by), any acce ss to the ti mer RD associated regi sters (addresse s 0135h

to 015Fh) is disabled.

3. To set the MSTTRD bit to 1 (standby), set bits TCK2 to TCK0 in the TRDCRi (i = 0 or 1) register to 000b (f1).

4. When the MSTTRC bi t is set to 1 (stand by), any acce ss to the time r RC associated registers (addresses 0120h

to 0133h) is disabled.

20.8.2 Timer RD Control Expansion Register (TRDECR)

Note:

1. Enabled when in time r mode.

Address 0008h

Bitb7b6b5b4b3b2b1b0

Symbol — — MSTTRC MSTTRD MSTIIC — — —

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b1 —

b2 —

b3 MSTIIC SSU, I2C bus standby bit 0: Active

1: Standby (1) R/W

b4 MSTTRD Timer RD standby bit 0: Active

1: Standby (2, 3) R/W

b5 MSTTRC Timer RC standby bit 0: Active

1: Standby (4) R/W

b6 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b7 —

Address 0135h

Bitb7b6b5b4b3b2b1b0

Symbol ITCLK1 — — — ITCLK0 — — —

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b1 —

b2 —

b3 ITCLK0 Timer RD0 fC2 select bit 0: TRDCLK input selected

1: fC2 selected (1) R/W

b4 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b5 —

b6 —

b7 ITCLK1 Timer RD1 fC2 select bit 0: TRDCLK input selected

1: fC2 selected (1) R/W

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 396 of 723

20.8.3 Timer RD Trigger Control Register (TRDADCR)

Address 0136h

Bitb7b6b5b4b3b2b1b0

Symbol ADTRGD1E ADTRGC1E ADTRGB1E ADTRGA1E ADTRGD0E ADTRGC0E ADTRGB0E ADTRGA0E

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 ADTRGA0E A/D trigger A0 enable bit 0: A/D trigger disabled

1: A/D trigger generated at compare match with

registers TRD0 and TRDGRB0

R/W

b1 ADTRGB0E A/D trigger B0 enable bit 0: A/D trigger disabled

1: A/D trigger generated at compare match with

registers TRD0 and TRDGRB0

R/W

b2 ADTRGC0E A/D trigger C0 enable bit 0: A/D trigger disabled

1: A/D trigger generated at compare match with

registers TRD0 and TRDGRC0

R/W

b3 ADTRGD0E A/D trigger D0 enable bit 0: A/D trigger disabled

1: A/D trigger generated at compare match with

registers TRD0 and TRDGRD0

R/W

b4 ADTRGA1E A/D trigger A1 enable bit 0: A/D trigger disabled

1: A/D trigger generated at compare match with

registers TRD1 and TRDGRA1

R/W

b5 ADTRGB1E A/D trigger B1 enable bit 0: A/D trigger disabled

1: A/D trigger generated at compare match with

registers TRD1 and TRDGRB1

R/W

b6 ADTRGC1E A/D trigger C1 enable bit 0: A/D trigger disabled

1: A/D trigger generated at compare match with

registers TRD1 and TRDGRC1

R/W

b7 ADTRGD1E A/D trigger D1 enable bit 0: A/D trigger disabled

1: A/D trigger generated at compare match with

registers TRD1 and TRDGRD1

R/W

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 397 of 723

20.8.4 Timer RD Start Register (TRDSTR) in PWM3 Mode

Notes:

1. When the CSEL0 bit is set to 1, write 0 to the TSTART0 bit.

2. When the CSEL1 bit is set to 1, write 0 to the TSTART1 bit.

3. When the CSEL0 bit is set to 0 and the compare match signal (TRDIOA0) is generated, this bit is set to 0 (count

stops).

4. When the CSEL1 bit is set to 0 and the compare match signal (TRDIOA1) is generated, this bit is set to 0 (count

stops).

Set the TRDSTR register using the MOV instruction (do not use the bi t handling instruction). Refer to 20.10.1

TRDSTR Register of Notes on Timer RD.

20.8.5 Timer RD Mode Register (TRDMR) in PWM3 Mode

Address 0137h

Bitb7b6b5b4b3b2b1b0

Symbol — — — — CSEL1 CSEL0 TSTART1 TSTART0

After Reset11111100

Bit Symbol Bit Name Function R/W

b0 TSTART0 TRD0 count start flag (3) 0: Count stops (1)

1: Count starts R/W

b1 TSTART1 TRD1 count start flag (4) 0: Count stops (2)

1: Count starts R/W

b2 CSEL0 TRD0 count operation select bit 0: Count stops at the compare match with the

TRDGRA0 register

1: Count continues after the compare match with

the TRDGRA0 register

R/W

b3 CSEL1 TRD1 count operation select bit

[this bit is not used in PWM3 mode] 0: Count stops at the compare match with the

TRDGRA1 register

1: Count continues after the compare match with

the TRDGRA1 register

R/W

b4 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. —

b5 —

b6 —

b7 —

Address 0138h

Bitb7b6b5b4b3b2b1b0

Symbol BFD1 BFC1 BFD0 BFC0 — — — SYNC

After Reset00001110

Bit Symbol Bit Name Function R/W

b0 SYNC Timer RD synchronous bit Set this bit to 0 (TRD0 and TRD1 operate

independently) in PWM3 mode. R/W

b1 — Nothing is assig ned. If necessary, set to 0. When read, the content is 1. —

b2 —

b3 —

b4 BFC0 TRDGRC0 register function select bit 0: Ge neral register

1: Buffer register of TRDGRA0 register R/W

b5 BFD0 TRDGRD0 register function select bit 0: Ge neral register

1: Buffer register of TRDGRB0 register R/W

b6 BFC1 TRDGRC1 register function select bit 0: Ge neral register

1: Buffer register of TRDGRA1 register R/W

b7 BFD1 TRDGRD1 register function select bit 0: Ge neral register

1: Buffer register of TRDGRB1 register R/W

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 398 of 723

20.8.6 Timer RD Function Control Register (TRDFCR) in PWM3 Mode

Notes:

1. Set bits CMD1 to CMD0 when both the TS TART 0 and TSTART1 bits in the TRDSTR register are set to 0 (count

stops).

2. When bits CMD1 to CMD0 are set to 00b (timer mode, PWM mode, or PWM3 mode), the setting of the PWM3 bit

is enabled.

Address 013Ah

Bitb7b6b5b4b3b2b1b0

Symbol PWM3 STCLK ADEG ADTRG OLS1 OLS0 CMD1 CMD0

After Reset10000000

Bit Symbol Bit Name Function R/W

b0 CMD0 Combination mode select bit (1) Set to 00b (timer mode, PWM mode, or PWM3

mode) in PWM3 mode. R/W

b1 CMD1 R/W

b2 OLS0 Normal-ph ase output level select bit

(enabled in reset synchronous PWM

mode or complementary PWM mode)

This bit is disabled in PWM3 mode. R/W

b3 OLS1 Coun ter-phase output level select bit

(enabled in reset synchronous PWM

mode or complementary PWM mode)

R/W

b4 ADTRG A/D trigger enable bit

(enabled in complementary PWM mode) R/W

b5 ADEG A/D trigger edge select bit

(enabled in complementary PWM mode) R/W

b6 ST CLK External clock input select bit Set this bit to 0 (external clock input disabled)

in PWM3 mode. R/W

b7 PWM3 PWM3 mode select bit (2) Set this bit to 0 (PWM3 mode) in PWM3

mode. R/W

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 399 of 723

20.8.7 Timer RD Output Master Enable Register 1 (TR DOER1) in PWM3 Mode

20.8.8 Timer RD Output Master Enable Register 2 (TR DOER2) in PWM3 Mode

Note:

1. Refer to 20.2.4 Pulse Output Forced Cutoff.

Address 013Bh

Bitb7b6b5b4b3b2b1b0

Symbol ED1 EC1 EB1 EA1 ED0 EC0 EB0 EA0

After Reset11111111

Bit Symbol Bit Name Function R/W

b0 EA0 TRDIOA0 output disable bit 0: Enable output

1: Disable output (The TRDIOA0 pin is used as a

programmable I/O port.)

R/W

b1 EB0 TRDIOB0 output disable bit 0: Enable output

1: Disable output (The TRDIOB0 pin is used as a

programmable I/O port.)

R/W

b2 EC0 TRDIOC0 output disable bit Set these bits to 1 (programmable I/O port) in

PWM3 mode. R/W

b3 ED0 TRDIOD0 outpu t disable bit R/W

b4 EA1 TRDIOA1 output disable bit R/W

b5 EB1 TRDIOB1 output disable bit R/W

b6 EC1 TRDIOC1 outpu t disable bit R/W

b7 ED1 TRDIOD1 outpu t disable bit R/W

Address 013Ch

Bitb7b6b5b4b3b2b1b0

SymbolPTO———————

After Reset01111111

Bit Symbol Bit Name Function R/W

b0 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. —

b1 —

b2 —

b3 —

b4 —

b5 —

b6 —

b7 PTO INT0 of pulse output forced cutoff

signal input enabled bit (1) 0: Pulse output forced cutoff input disabled

1: Pulse output forced cutoff input enabled

(All bits in the TRDOER1 register are set to 1

(disable output) when “L” is applied to the INT0

pin.)

R/W

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 400 of 723

20.8.9 Timer RD Output Control Register (TRDOCR) in PWM3 Mode

Note:

1. If the pin function is set for waveform output (refer to 7.5 Port Settings), the initial output level is output when the

TRDOCR register is set.

Write to the TRDOCR register when both bits TSTART0 and TSTART1 in the TRDSTR register are set to 0

(count stops).

Address 013Dh

Bitb7b6b5b4b3b2b1b0

Symbol TOD1 TOC1 TOB1 TOA1 TOD0 TOC0 TOB0 TOA0

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 TOA0 TRDIOA0 output level select bit (1) 0: Active level “H”,

initial output “L”,

output “H” at compare match with the TRDGRA1

output “L” at compare match with the TRDGRA0

1: Active level “L”,

initial output “H”,

output “L” at compare match with the TRDGRA1

output “H” at compare match with the TRDGRA0

R/W

b1 TOB0 TRDIOB0 output level select bit (1) 0: Active level “H”,

initial output “L”,

output “H” at compare match with the

TRDGRB1register,

output “L” at compare match with the TRDGRB0

1: Active level “L”,

initial output “H”,

output “L” at compare match with the TRDGRB1

output “H” at compare match with the TRDGRB0

R/W

b2 TOC0 TRDIOC0 initial output level select bit These bits are disabled in PWM3 mo de. R/W

b3 TOD0 TRDIOD0 initial output level select bit R/W

b4 TOA1 TRDIOA1 initial output level select bit R/W

b5 TOB1 TRDIOB1 initial output level select bit R/W

b6 TOC1 TRDIOC1 initial output level select bit R/W

b7 TOD1 TRDIOD1 initial output level select bit R/W

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 401 of 723

20.8.10 Timer RD Control Register 0 (TRDCR0) in PWM3 Mode

Note:

1. To select fOCO-F, set it to the clock frequency higher than the CPU clock frequency.

The TRDCR1 register is not used in PWM3 mode.

Address 0140h

Bitb7b6b5b4b3b2b1b0

Symbol CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TCK2 TCK1 TCK0

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 TCK0 Count source select bit b2 b1 b0

0 0 0: f1

0 0 1: f2

0 1 0: f4

0 1 1: f8

1 0 0: f32

1 0 1: Do not set.

1 1 0: fOCO40M

1 1 1: fOCO-F (1)

R/W

b1 TCK1 R/W

b2 TCK2 R/W

b3 CKEG0 External clock edge select bit These bits are disabled in PWM3 mode. R/W

b4 CKEG1 R/W

b5 CCLR0 TRD0 counter clear select bit Set to 001b (the TRD0 register cleared at compare

match with TRDGRA0 register) in PWM3 mode. R/W

b6 CCLR1 R/W

b7 CCLR2 R/W

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 402 of 723

20.8.11 Timer RD Status Register i (TRDSRi) (i = 0 or 1) in PWM3 Mode

Notes:

1. Nothing is assigned to b5 in the TRDSR0 register. When writing to b5, write 0. When reading, the content is 1.

2. The writing results are as follows:

• This bit is set to 0 when the read result is 1 and 0 is written to the same bit.

• This bit remains unchanged even if the read result is 0 and 0 is written to the same bit. (This bit remains 1 even

if it is set to 1 from 0 after reading, and writing 0.)

• This bit remains unchanged if 1 is written to it.

3. Including w hen the BFji (j = C or D) bit in the TRDMR register is set to 1 (TRDGRji is used as the buffer register).

Address 0143h (TRDSR0), 0153h (TRDSR1)

Bitb7b6b5b4b3b2b1b0

Symbol — — UDF OVF IMFD IMFC IMFB IMFA

After Reset 1 1 1 0 0 0 0 0 TRDSR0 register

After Reset 1 1 0 0 0 0 0 0 TRDSR1 register

Bit Symbol Bit Name Function R/W

b0 IMFA Input capture / compare match flag A [Source for setting this bit to 0]

Write 0 after read (2).

[Source for setting this bit to 1]

When the value in the TRDi register matches with

the value in the TRDGRAi register.

R/W

b1 IMFB Input capture / compare match flag B [Source for setting this bit to 0]

Write 0 after read (2).

[Source for setting this bit to 1]

When the value in the TRDi register matches with

the value in the TRDGRBi register.

R/W

b2 IMFC Input capture / compare match flag C [Source for setting this bit to 0]

Write 0 after read (2).

[Source for setting this bit to 1]

When the value in the TRDi register matches with

the value in the TRDGRCi register (3).

R/W

b3 IMFD Input capture / compare match flag D [Source for setting this bit to 0]

Write 0 after read (2).

[Source for setting this bit to 1]

When the value in the TRDi register matches with

the value in the TRDGRDi register (3).

R/W

b4 OVF Overflow flag [Source fo r setting this bit to 0]

Write 0 after read (2).

[Source for setting this bit to 1]

When the TRDi register overfl ows.

R/W

b5 UDF Underflow flag (1) This bit is disabled in PWM3 Mode. R/W

b6 — Nothing is assig ned. If necessary, set to 0. When read, the content is 1. —

b7 —

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 403 of 723

20.8.12 Timer RD Interrupt Enable Register i (TRDIERi) (i = 0 or 1) in PWM3 Mode

20.8.13 Timer RD Counter 0 (TRD0) in PWM3 Mode

Access the TRD0 register in 16-bit units. Do not access it in 8-bit units.

The TRD1 register is not used in PWM3 mode.

Address 0144h (TRDIER0), 0154h (TRDIER1)

Bitb7b6b5b4b3b2b1b0

Symbol — — — OVIE IMIED IMIEC IMIEB IMIEA

After Reset11100000

Bit Symbol Bit Name Function R/W

b0 IMIEA Input capture/compare match interrupt

enable bit A 0: Disable interrupt (IMIA) by the IMFA bit

1: Enable interrupt (IMIA) by the IMFA bit R/W

b1 IMIEB Input capture/compare match interrupt

enable bit B 0: Disable interrupt (IMIB) by the IMFB bit

1: Enable interrupt (IMIB) by the IMFB bit R/W

b2 IMIEC Input capture/compare match interrupt

enable bit C 0: Disable interrupt (IMIC) by the IMFC bit

1: Enable interrupt (IMIC) by the IMFC bit R/W

b3 IMIED Input capture/compare match interrupt

enable bit D 0: Disable interrupt (IMID) by the IMFD bit

1: Enable interrupt (IMID) by the IMFD bit R/W

b4 OVIE Overflow/underflow interrupt enable

bit 0: Disable interrupt (OVI) by the OVF bit

1: Enable interrupt (OVI) by the OVF bit R/W

b5 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. —

b6 —

b7 —

Address 0147h to 0146h

Bitb7b6b5b4b3b2b1b0

Symbol————————

After Reset00000000

Bit b15 b14 b13 b12 b11 b10 b9 b8

Symbol————————

After Reset00000000

Bit Function Setting Range R/W

b15 to b0 Count a count source. Cou nt operation is incremented.

When an overflow occurs, the OVF bit in the TRDSR0 register is set to 1. 000 0h to FFFFh R /W

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 404 of 723

20.8.14 Timer RD General Registers Ai, Bi, Ci, and Di (TRDGRAi, TRDGRBi,

TRDGRCi, TRDGRDi) (i = 0 or 1) in PWM3 Mode

Access registers TRDGRAi to TRDGRDi in 16-bit units. Do not access them in 8-bit units.

The following registers are disabled in the PWM3 mode function: TRDPMR, TRDDF0, TRDDF1,

TRDIORA0, TRDIORC0, TRDPOCR0, TRDIORA1, TRDIORC1, and TRDPOCR1.

Address 0149h to 0148h (TRDGRA0), 014Bh to 014Ah (TRDGRB0),

014Dh to 014Ch (TRDGRC0), 014Fh to 014Eh (TRDGRD0),

0159h to 0158h (TRDGRA1), 015Bh to 015Ah (TRDGRB1),

015Dh to 015Ch (TRDGRC1), 015Fh to 015Eh (TRDGRD1)

Bitb7b6b5b4b3b2b1b0

Symbol————————

After Reset11111111

Bit b15 b14 b13 b12 b11 b10 b9 b8

Symbol————————

After Reset11111111

Bit Function R/W

b15 to b0 Refer to Table 20.16 TRDGRji Register Functions in PWM3 Mode R/W

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 405 of 723

BFC0, BFD0, BFC1, BFD1: Bits in TRDMR register

Registers TRDGRC0, TRDGRC1, TRDGRD0, and TRDGRD1 are not used in PWM3 mode. To use them as

buffer registers, set bits BFC0, BFC1, BFD0, and BFD1 to 0 (general register) and write a value to the

TRDGRC0, TRDGRC1, TRDGRD0, or TRDGRD1 register. After this, bits BFC0, BFC1, BFD0, and BFD1

may be set to 1 (buffer register).

Table 20.16 TRDGRji Register Functions in PWM3 Mode

TRDGRA0 −General register. Set the PWM period.

Setting range: Value set in TRDGRA1 re gister or above TRDIOA0

TRDGRA1 General register. Set the changing point (the active level

timing) of PWM output.

Setting range: Value set in TRDGRA0 register or below

TRDGRB0 General register. Set the changing point (the timing that

returns to initial output level) of PWM output.

Setting range: Value set in TRDGRB1 re gister or above

Value set in TRDGRA0 register or below

TRDIOB0

TRDGRB1 General register. Set the changing point (a ctive level timing) of

PWM output.

Setting range: Value set in TRDGRB0 register or below

TRDGRC0 BFC0 = 0 (These registers is not used in PWM3 mode.) −

TRDGRC1 BFC1 = 0

TRDGRD0 BFD0 = 0

TRDGRD1 BFD1 = 0

TRDGRC0 BFC0 = 1 Buf fe r re gist er . Set the next PWM period.

(Refer to 20.2.2 Buffer Operation.)

Setting range: Value set in TRDGRC1 re gister or above

TRDIOA0

TRDGRC1 BFC1 = 1 Buffer register. Set the changing point of next PWM output.

(Refer to 20.2.2 Buffer Operation.)

Setting range: Value set in TRDGRC0 register or below

TRDGRD0 BFD0 = 1 Buffer register. Set the changing point of next PWM output.

(Refer to 20.2.2 Buffer Operation.)

Setting range: Value set in TRDGRD1 re gister or above,

setting value or below in TRDGRC0 register.

TRDIOB0

TRDGRD1 BFD1 = 1 Buffer register. Set the changing point of next PWM output.

(Refer to 20.2.2 Buffer Operation.)

Setting range: Value set in TRDGRD0 register or below

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 406 of 723

20.8.15 Timer RD Pin Select Register 0 (TRDPSR0)

The TRDPSR0 register selects which pin is assigned to the timer RD I/O. To use the I/O pin for timer RD, set

this register.

Set the TRDPSR0 register before setting the timer RD associated registers. Also, do not change the setting

value in this register during timer RD operation.

20.8.16 Timer RD Pin Select Register 1 (TRDPSR1)

The TRDPSR1 register selects which pin is assigned to the timer RD I/O. To use the I/O pin for timer RD, set

this register.

Set the TRDPSR1 register before setting the timer RD associated registers. Also, do not change the setting

value in this register during timer RD operation.

Address 0184h

Bitb7b6b5b4b3b2b1b0

Symbol — TRDIOD0SEL0 TRDIOC0SEL1 TRDIOC0SEL0 TRDIOB0SEL1 TRDIOB0SEL0 — TRDIOA0SEL0

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 TRDIOA0SEL0 TRDIOA0/TRDCLK pin select bit 0: TRDIOA0/TRDCLK pin not used

1: P2_0 assigned R/W

b1 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b2 TRDIOB0SEL0 TRDIOB0 pin select bit b3 b2

0 0: TRDIOB0 pin not used

0 1: Do not set.

1 0: P2_2 assigned

1 1: Do not set.

R/W

b3 TRDIOB0SEL1 R/W

b4 TRDIOC0SEL0 TRDIOC0 pin select bit b5 b4

0 0: TRDIOC0 pin not used

0 1: Do not set.

1 0: P2_1 assigned

1 1: Do not set.

R/W

b5 TRDIOC0SEL1 R/W

b6 TRDIOD0SEL0 TRDIOD0 pin select bit 0: TRDIOD0 pin not used

1: P2_3 assigned R/W

b7 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

Address 0185h

Bitb7b6b5b4b3b2b1b0

Symbol — TRDIOD1SEL0 — TRDIOC1SEL0 — TRDIOB1SEL0 — TRDIOA1SEL0

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 TRDIOA1SEL0 TRDIOA1 pin select bit 0: TRDIOA1 pin not used

1: P2_4 assigned R/W

b1 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b2 TRDIOB1SEL0 TRDIOB1 pin select bit 0: TRDIOB1 pin not used

1: P2_5 assigned R/W

b3 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b4 TRDIOC1SEL0 TRDIOC1 pin select bit 0: TRDIOC1 pin not used

1: P2_6 assigned R/W

b5 — Reserved bit Set to 0. R/W

b6 TRDIOD1SEL0 TRDIOD1 pin select bit 0: TRDIOD1 pin not used

1: P2_7 assigned R/W

b7 — Reserved bit Set to 0. R/W

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 407 of 723

20.8.17 Operating Example

Figure 20.23 Operating Example of PWM3 Mode

Value in TRD 0 register

Count source

TRDIO A0 ou tput

0000h

FFFFh

TRDIO B0 ou tput

m: Value set in TRDGRA0 register

n: Value set in TRD GR A1 reg ister

p: Value set in TRD GR B0 reg ister

q: Value set in TRD GR B1 reg ister

TSTART0 bit in

TRDSTR register

Set to 0 by a program Set to 0 by a program

m+1

n+1 m-n

p+1

q+1 p-q

Count stop

Output “H” at compare

match with t he

TRDGRA1 register

Set to 0 by a p rogra mSet to 0 by a program

Set to 0 by a program

Transfer

m Following data

Transfer

Output “L” at compare match

with the TRDGRA0 register

Transfer from buffer re g ister to

general register Transfer from buffer register to

general register

Initial outpu t “L”

j = either A or B

The above applies under the following conditions:

• Both the TOA0 and TOB0 bits in the TRDOCR register are set to 0 (initial output level “L”, output “H” by compare match with the

TRDGRj1 register, output “L” at compare match with the TRDGRj0 register).

• The BFC0 bit in the TRDM R register is set to 1 (the TRDGRC0 register is used as the buffer register of the TRDGRA0 register).

CSEL0 bit in

TRDSTR register

IMFA bit in

TRDSR0 register

IMFB bit in

TRDSR0 register

TRDGRA0 register

TRDGRC0 register

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 408 of 723

20.8.18 A/D Trigger Generation

A compare match signal with registers TRDi (i = 0 or 1) and TRDGRji (j = A, B, C, or D) can be used as the

conversion start trigger of the A/D converter.

The TRDADCR register is used to select which compare match is used.

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 409 of 723

20.9 Timer RD Interrupt

Timer RD generates the timer RDi (i = 0 or 1) interrupt request from six so urces for each timer RD0 and timer

RD1. The timer RD interrupt has 1 TRDiIC register (bits IR, and ILVL0 to ILVL2), and 1 vector for each timer

RD0 and timer RD1.

Table 20.17 lists the Registers Associated with Timer RD Interrupt, and Figure 20.24 shows a Block Diagram of

Timer RD Interrupt.

Figure 20.24 B lock Diagram of Timer RD Interrupt

As with other maskable interrupts, the timer RD interrupt is controll ed by the combination of the I flag, IR bit, bits

ILVL0 to ILVL2, and IPL. However, since the i nterrup t source (timer RD interrupt) is generated by a combination

of multiple interrupt request sources, the following differences from other maskable interrupts apply:

• When bits in the TRDSRi register corresponding to bits set to 1 in the TRDIERi register are set to 1 (enable

interrupt), the IR bit in the TRDiIC register is set to 1 (interrupt requested).

• When either bits in the TRDSRi register or bits in the TRDIERi register corresponding to bits in the TRDSRi

interrupt is not acknowledged aft e r the IR bit is set to 1, the interrupt request w ill not be maintained.

• When the conditions of other request sources are met, the IR bit remains 1.

• When multiple bits i n the TRDIERi register are set to 1, which request source causes an interrupt is determined

by the TRDSRi register.

• Since each bit in the TRDSRi register is not automatically set to 0 even if the interrupt is acknowledged, set each

bit to 0 in the interrupt routine. For information on how to set these bits to 0, refer to the descripti ons of the

registers used in the different modes (20.3.11, 20.4.14, 20.5.12, 20.6.10, 20.7.10, and 20.8.11).

Refer to Registers TRDSR0 to TRDSR1 in each mode (20.3.11, 20.4.14, 20.5.12, 20.6.10, 20.7.10, and 20.8.11)

for the TRDSRi register. Refer to Registers TRDIER0 to TRDIER1 in each mode (20.3.12, 20.4.15, 20.5.13,

20.6.11, 20.7.11, and 20.8.12) for the TRDIERi register.

Refer to 11.3 Interrupt Control for information on the TRDiIC register and 11.1.5.2 Relocatable Vector Tables

for the interrupt vectors.

Table 20.17 Registers Associated with Timer RD Interrupt

Timer RD

Status Register Timer RD

Interrupt Enable Register Timer RD

Interrupt Control Register

Timer RD0 TRDSR 0 TRDI ER0 TRD0IC

Timer RD1 TRDSR 1 TRDI ER1 TRD1IC

Timer RDi interrupt request

(IR bit in TRDiIC register)

IMFA bit

IMIEA bit

IMFB bit

IMIEB bit

IMFC bit

IMIEC bit

IMFD bit

IMIED bit

UDF bit

OVF bit

OVIE bit

i = 0 or 1

IMFA, IMFB , IMFC, IMFD, O V F, UDF : Bits in TRDSR i reg is te r

IMIEA, IMIEB, IMIEC, IMIED, OVIE: Bits in TRDIERi register

Timer RDi

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 410 of 723

20.10 Notes on Timer RD

20.10.1 TRDSTR Register

•Set the TRDSTR register using the MOV instruction.

•When the CSELi (i = 0 to 1) is set to 0 (the count stops at compare match of registers TRDi and TRDGRAi),

the count does not stop and the TSTARTi bit remains unchanged even if 0 (count stops) is written to the

TSTARTi bit.

Therefore, set the TSTARTi bit to 0 to change othe r bits with out changi ng the TSTARTi bit when the CSELi

bit is se to 0.

To stop counting by a program, set the TSTARTi bit after setting the CSELi bit t o 1. Althoug h the CSELi b it

is set to 1 and the TSTARTi bit is set to 0 at the same time (with 1 instruction), the count cannot be st opped.

•Table 20.18 lists the TRDIOji (j = A, B, C, or D) Pin Output Level when Count Stops to use the TRDIOji (j =

A, B, C, or D) pin with the timer RD output.

20.10.2 TRDi Register (i = 0 or 1)

•When writing the value to the TRDi register by a program while the TSTARTi bit in th e TRDSTR register is

set to 1 (count starts), avoid overlapping with the timing for setting the TRDi register to 0000h, and then

write.

If the timing for setting the TRDi register to 00 00h overlaps with the timing for writing the value to the TRDi

These precautions are applicable when selecting the following by bits CCLR2 to CCLR0 in the TRDCRi

- 001b (Clear the TRDi register by input capture/compare match in the TRDGRAi register.)

- 010b (Clear the TRDi register by input capture/compare match in the TRDGRBi register.)

- 011b (Synchronous clear)

- 101b (Clear the TRDi register by input capture/compare match in the TRDGRCi register.)

- 110b (Clear the TRDi register by input capture/compare match in the TRDGRDi register.)

•When writing the value to the TRDi register and continuously reading the same register, the value before

writing may be read. In this case, execute the JMP.B instruction between the writing and reading.

Program example MO V.W #XXXXh, TRD 0 ;Writing

JMP.B L1 ;JMP.B

L1: MOV.W TRD0,DATA ;Reading

20.10.3 TRDSRi Register (i = 0 or 1)

When writing the value to the TRDSRi register and continuously reading the same register, the value before

writing may be read. In this case, execute the JMP.B instruction between the writing and reading.

Program example MO V.B #XXh, TRDSR0 ;Writ ing

JMP.B L1 ;JMP.B

L1: MOV.B TRDSR0,DATA ;Reading

20.10.4 TRDCRi Register (i = 0 or 1)

To set bits TCK2 to TCK0 in the TRDCRi register to 111b (fOCO-F), set fOCO-F to the clock frequency higher

than the CPU clock frequency.

Table 20.18 TRDIOji (j = A, B, C, or D) Pin Output Level when Count Stops

Count Stop TRDIOji Pin Output when Count Stops

When the CSELi bit is set to 1, set the TSTARTi bit to 0 and the count

stops. Hold the output level immediatel y before the

count stops.

When the CSELi bit is set to 0, the count stops at compare match of

registers TRDi and TRDGRAi. Hold the output level after output changes by

compare match.

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 411 of 723

20.10.5 Count Source Switch

•Switch the count source after the count stops.

Switching procedure

(1) Set the TSTARTi (i = 0 or 1) bit in the TRDSTR register to 0 (count stops).

(2) Change bits TCK2 to TCK0 in the TRDCRi register.

•When changing the count source from fOC O40M to another source and stopping fOCO40M, wait 2 cycles of

f1 or more after setting the clock switch, and then stop fOCO40M.

Switching procedure

(1) Set the TSTARTi (i = 0 or 1) bit in the TRDSTR register to 0 (count stops).

(2) Change bits TCK2 to TCK0 in the TRDCRi register.

(3) Wait 2 or more cycles of f1.

(4) Set the FRA00 bit in the FRA0 register to 0 (high-speed on-chip oscillator stops).

•After switching the count source fro m fOCO-F to fOCO40M, allow a minimum of two cy cles of fOCO-F to

elapse after changing the clock setting before stopping fOCO-F.

Switching procedure

(1) Set the TSTARTi (i = 0 to 1) bit in the TRDSTR register to 0 (count stops).

(2) Change the settings of bits TCK2 to TCK0 in the TRDCRi regi st er.

(3) Wait for a minimum of two cycles of fOCO-F.

(4) Set the FRA00 bit in the FRA0 register to 0 (high-speed on-chip oscillator off).

•After switching the count source from fOCO-F to a clock other than fOCO40M, allow a minimum of one

cycle of fOCO-F + fOCO40M to elapse after changing the clock setting before stoppin g fOCO-F.

Switching procedure

(1) Set the TSTARTi (i = 0 to 1) bit in the TRDSTR register to 0 (count stops).

(2) Change the settings of bits TCK2 to TCK0 in the TRDCRi register.

(3) Wait for a minimum of one cycle of fOCO-F + fOCO40M.

(4) Set the FRA00 bit in the FRA0 register to 0 (high-speed on-chip oscillator off).

20.10.6 Input Capture Function

•Set the pulse width of the input capture signal to 3 or more cycles of the timer RD operation clock (refer to

Table 20.1 Timer RD Operation Clocks).

•The value in the TRDi register is transferred to th e TRDGRji register 2 to 3 cycles of the timer RD operation

clock after the input capture signal is applied to the TRDIOji pin (i = 0 or 1, j = A, B, C, or D) (no digital

filter).

20.10.7 Reset Synchronous PWM Mode

•When reset synchronous PWM mode is used for moto r control, make sure OLS0 = OLS1.

•Set to reset synchronous PWM mode by the following pro cedure:

Switching procedure

(1) Set the TSTART0 bit in the TRDSTR register to 0 (count stops).

(2) Set bits CMD1 to CMD0 in the TRDFCR register to 00b (timer mode, PWM mode, and PWM3 mode).

(3) Set bits CMD1 to CMD0 to 01b (reset synchronous PWM mode).

(4) Set the other registers associated with timer RD again.

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 412 of 723

20.10.8 Complementary PWM Mode

•When complementary PWM mode is used for motor control , m ake sure OLS0 = OLS1.

•Change bits CMD1 to CMD0 in the TRDFCR register in the following procedure.

Switching procedure: When setting to complementary PWM mode (including re-set), or changing the transfer

timing from the buffer register to the general register in complementary PWM mode.

(1) Set both the TSTART0 and TSTART1 bits in the TRDSTR register to 0 (count stops).

(2) Set bits CMD1 to CMD0 in the TRDFCR register to 00b (timer mode, PWM mode, and PWM3 mode).

(3) Set bits CMD1 to CMD0 to 10b or 11b (complementary PWM mode).

(4) Set the registers associated with other timer RD again.

Switching procedure: When stopping complementary PWM mode

(1) Set both the TSTART0 and TSTART1 bits in the TRDSTR register to 0 (count stops).

(2) Set bits CMD1 to CMD to 00b (timer mode, PWM mode, and PWM3 mode).

•Do not write to TRDGRA0, TRDGRB0, TRDGRA1, or TRDG RB1 regi ster during operation.

When changing the PWM waveform, transfer the values written to registers TRDGRD0, TRDGRC1, and

TRDGRD1 to registers TRDGRB0, TRDGRA1, and TRDGRB1 using the buffer operation.

However, to write data to the TRDGRD0, TRDGRC1, or TRDGRD1 register, set bits BFD0, BFC1, and

BFD1 to 0 (general register). After this, bits BFD0, BFC1, and BFD1 may be set to 1 (buffer register).

The PWM period cannot be changed.

•If the value in the TRDGRA0 register is assume d to be m, the TRD0 register counts m-1, m, m+1, m, m-1, in

that order, when changing from increment to decrement operation.

When changing from m to m+1, the IMFA bit is set to 1. Also, bits CMD1 to CMD0 in the TRDFCR regi ster

are set to 11b (complementary PWM mode, buffer data transferred at compare match between registers TRD0

and TRDGRA0), the content in the buffer registers (TRDGRD0, TRDGRC1, and TRDGRD1) is transferred

to the general registers (TRDGRB0, TRDGRA1, and TRDGRB1).

During m+1, m, and m-1 op eration, th e IMFA bit remai ns uncha nged and d ata are n ot transferred to reg isters

such as the TRDGRA0 register.

Figure 20.25 Operation at Compare Match between Registers TRD0 and TRDGRA0 in

Complementary PWM Mode

No change

IMFA b i t in

TRDSR0 register

Transferred from

buffer register

TRD G RB0 register

TRD G RA1 register

TRD G RB1 register

Count value in TRD0

Se tting value in

TRDGRA0

m+1

Set to 0 by a program

Not transferred from buffer register

W hen bits CMD1 to CM D0 in the

TRDFCR register are set to 11b

(tra nsfe r fr om the buffer re giste r to the

general register at compare match of

between registers TRD0 and

TRDGRA0).

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 413 of 723

•The TRD1 register counts 1, 0, FFFFh, 0, 1, in that order, when changing from decrement to increment

operation.

The UDF bit is set to 1 when changing between 1 , 0, and FFFFh op eration. A lso, when b its CM D1 to C MD0

in the TRDFCR register are set to 10b (complementary PWM mode, buffer data transferred at underflow in

the TRD1 register), the content in the buffer registers (TRDGRD0, TRDGRC1, and TRDGRD1) is

transferred to the general registers (TRDG RB0, TRDGRA1, and TRDGRB1). During FFFFh, 0, 1 operation,

data are not transferred to registers such as the TRDGRB0 register. Also, at this time, the OVF bit remains

unchanged.

Figure 20.26 Operation when TRD1 Register Underflows in Complementary PWM Mode

No change

UDF bit in

TRDSR0 register

Transferred from

buffer regist er

TRDGRB0 register

TRDGRA1 register

TRDGRB1 register

Count value in TRD0

Set to 0 by a program

Not transferred from buf fer register

When bits CMD1 to CMD0 in the

TRDFCR register are set to 10b

(transfer from the buffer register to th e

general register when the TRD1 register

underflows).

OVF bit in

TRDSR0 register

FFFFh

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 414 of 723

•Select with bits CMD1 to CMD0 the timing of data transfer from the buffer register to the general register.

However, transfer takes place with the following timing in spite of the value of bits CMD1 to CMD0 in the

following cases:

Value in buffer register ≥ value in TRDGRA0 register:

Transfer take place at underflow of the TRD1 register.

After this, when the buffer register is set to 0001h or above and a smaller value than the value of the

TRDGRA0 register, and the TRD1 register un derflows for the first time after setting, the value is transferred

to the general register. After that, the value is transferred with the timing selected by bits CMD1 to CMD0.

Figure 20.27 Operation whe n Value in Buffer Register ≥ Value in TRDGRA0 Register in

Complementary PWM Mode

0000h

TRDGRD0 register

TRDIOB0 output

m+1

n2 n1

n2 n2 n1n1TRDGRB0 register

Transfer

Transfer at

underflow of TRD1

n3 > m

Transfer at

underflow of TRD1

of fir st setting to

n2 < m

TRDIOD0 output

m: Value set in TRDGRA0 register

The above applies under the following conditions:

• Bits CMD1 to CMD0 in the TRDFCR register are set to 11b (data in the buffer register is transferred at compare match

between registers TRD0 and TRDGRA0 in complementary PWM mode).

• Both the OSL0 and OLS1 bits in the TRDFCR register are set to 1 (active ‘H” for normal-phase and counter-phase).

Count value in TRD0

Count value in TRD1

Transfer with timing set by

bits CMD1 to CMD0 Transfer with timing set by

bit s CMD1 to CM D0

Transfer Transfer Transfer

R8C/34C Group 20. Timer RD

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 415 of 723

When the value in the buffer register is set to 0000h:

Transfer takes place at compare match between registers TRD0 and TRDGRA0.

After this, when the buffer register is set to 0001h or above and a smaller value than the value of the

TRDGRA0 register, and a compare match occurs between registers TRD0 and TRDGRA0 for the first time

after setting, the value is transferred to the general register. After that, th e value i s transferred with the timi ng

selected by bits CMD1 to CMD0.

Figure 20.28 Operation when Value in Buffer Register Is Set to 0000h in Complementary PWM

Mode

20.10.9 Count Source fOCO40M

The count source fOCO40M can be used with supply voltage VCC = 2.7 to 5.5 V. For supply voltage other than

that, do not set bits TCK2 to TCK0 in registers TRDCR0 and TRDCR to 110b (select fOCO40M as the count

source).

0000h

TRDGRD0 register

TRDIOB0 output

m+1

0000h n1

0000h

n1 n1n2TRDGRB0 register

Transfer

Transfer at compare

match between

registers TRD0 and

TRDGR A0 because

content in TRDG R D 0

0000h.

Transfer at compare

ma tch between

registers TRD0 and

TRDGR A0 because

of firs t se tt in g to

0001h ≤ n1 < m

Transfer with timing

set by bits CMD1 to

CMD0

TRDIOD0 output

m: Value set in TRDGRA0 register

The above applies under the f ollowing conditions:

• Bits CMD1 to CMD0 in the TRDFCR register are set to 10b (data in the buffer register is transferred at underflow of t he T RD1 register in

PWM mode).

• Both the OLS0 and OLS1 bits in the TRDFCR register are set to 1 (active “H” for normal-phase and counter-phase).

Count value in TRD0 register

Count value in TRD1 register

Transfer with timing

set by bits CMD1 to

CMD0

Transfer Transfer Transfer

R8C/34C Group 21. Timer RE

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 416 of 723

21. Timer RE

Timer RE has an 8-bit counter with a 4-bit prescaler.

21.1 Overview

Timer RE has the following 2 modes:

•Real-time clock mode Generat e 1-seco nd signal from fC4 and count seconds, minutes, hours, and days of

the week.

•Output compare mode Count a count source and detect com pare matches.

The count source for timer RE is the operating clock that regulates the timing of timer operations.

Table 21.1 lists the Pin Configuration of Timer RE.

Table 21.1 Pin Configuration of Timer RE

Pin Name Assigned Pin I/O Function

TREO P0_4 or P6_0 Output Function differs according to the mode.

Refer to descriptions of individual modes

for details.

R8C/34C Group 21. Timer RE

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 417 of 723

21.2 Real-Time Clock Mode

In real-time clock mode, a 1-second signal is generated from fC4 using a divide-by-2 frequency divider, 4-bit

counter, and 8-bit counter and used to count seconds, minutes, hours, and days of the week. Figure 21.1 shows a

Block Diagram of Real-Time Clock Mode and Table 21.2 lists the Real -Time Clock Mode Specifications. Table

21.3 lists the Interrupt Sources, Figu re 21.2 shows the Definition of Time Representation and Figure 21.3 shows

the Operating Example in Real-Time Clock Mode.

Figure 21.1 Block Diagram of Real-Time Clock Mode

TREWK

TREHR

TREMIN

TRESEC

H12_H24

bit PM

bit

MNIE

HRIE

WKIE

000

DYIE

SEIE

Timer RE

interrupt

INT

bit

BSY

bit

Overflow

Timing

control

Data bus

Overflow Overflow

TREO pin (1)

(1s) Overflow

(1/256)

(1/16)

fC4

(8.192kHz)

RCS6 t o RCS4

= 000b

= 010b

= 100b

= 011b TOENA

= 001b

8-bit counter4-bit counter1/2

TOENA, H12_H24, PM, INT: Bits in TRECR1 register

SEIE, MNIE, HRIE, DYIE, WKIE: Bits in TRECR2 register

BSY: Bit in TRESEC, TREMIN, TREHR, TREWK register

RCS4 to RCS6: Bits in TRECSR register

Note

1: The TREOSEL0 bi t i n the TIMSR regis ter is used to se l ec t whi c h pi n i s assigned.

R8C/34C Group 21. Timer RE

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 418 of 723

Table 21.2 Real-Time Clock Mode Specifications

Item Specification

Count source fC4

Count operation Increment

Count start condition 1 (count starts) is written to TSTART bit in TRECR1 register

Count stop condition 0 (count stops) is written to TSTART bit in TRECR1 register

Interrupt request generation

timing Select any one of the following:

• Update second data

• Update minute dat a

• Update hour data

• Update day of week dat a

• When d ay of week data is set to 000b (Sunday)

TREO pin function Programmable I/O ports or output of f2, fC, f4, f8 or, 1Hz

Read from timer When reading TRESEC, TREM IN, TREHR, or TREWK register, the co unt

value can be read. The values read from registers TRESEC, TREMIN,

and TREHR are represen ted by the BCD code.

Write to timer When bits TSTART and T CSTF in the TRECR1 register are set to 0 ( timer

stops), the value can be written to registers TRESEC, TREMIN, TREHR,

and TREWK. The values written to registers TRESEC, TREMIN, and

TREHR are represente d by the BCD codes.

Select function • 12-hour mode/24-hour mode switch function

• TREO pin select function

P0_4 or P6_0 is selected by the TREOSEL0 bit in the TIMSR register.

R8C/34C Group 21. Timer RE

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 419 of 723

21.2.1 Timer RE Second Data Register (TRESEC) in Real-Time Clock Mode

21.2.2 Timer RE Minute Data Register (TREMIN) in Real-Time Clock Mode

Address 0118h

Bitb7b6b5b4b3b2b1b0

Symbol BSY SC12 SC11 SC10 SC03 SC02 SC01 SC00

After Reset00000000

Bit Symbol Bit Name Function Setting Range R/W

b0 SC00 1st digit of second count bit Count 0 to 9 every second. When the digit

moves up, 1 is added to the 2nd digit of

second.

0 to 9

(BCD code) R/W

b1 SC01 R/W

b2 SC02 R/W

b3 SC03 R/W

b4 SC10 2nd digit of second count bit When counting 0 to 5, 60 seconds are

counted. 0 to 5

(BCD code) R/W

b5 SC11 R/W

b6 SC12 R/W

b7 BSY Timer RE busy flag This bit is set to 1 while registers TRESEC, TREMIN,

TREHR, and TREWK are updated R

Address 0119h

Bitb7b6b5b4b3b2b1b0

Symbol BSY MN12 MN11 MN10 MN03 MN02 MN01 MN00

After Reset00000000

Bit Symbol Bit Name Function Setting Range R/W

b0 MN00 1st digit of minute count bit Count 0 to 9 every minute. When the digit

moves up, 1 is added to the 2nd digit of

minute.

0 to 9

(BCD code) R/W

b1 MN01 R/W

b2 MN02 R/W

b3 MN03 R/W

b4 MN10 2nd digit of minute count bit When counting 0 to 5, 60 minutes are

counted. 0 to 5

(BCD code) R/W

b5 MN11 R/W

b6 MN12 R/W

b7 BSY Timer RE busy flag This bit is set to 1 while registers TRESEC, TREMIN,

TREHR, and TREWK are updated. R

R8C/34C Group 21. Timer RE

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 420 of 723

21.2.3 Timer RE Hour Data Register (TREHR) in Real-Time Clock Mode

21.2.4 Timer RE Day of Week Data Register (TREWK) in Real-Time Clock Mode

Address 011Ah

Bitb7b6b5b4b3b2b1b0

Symbol BSY — HR11 HR10 HR03 HR02 HR01 HR00

After Reset00000000

Bit Symbol Bit Name Function Setting Range R/W

b0 HR00 1st digit of hour count bit Count 0 to 9 every hour. When the digit

moves up, 1 is added to the 2nd digit of

hour.

0 to 9

(BCD code) R/W

b1 HR01 R/W

b2 HR02 R/W

b3 HR03 R/W

b4 HR10 2nd digit of hour count bit Count 0 to 1 w hen the H12_H24 bit is set

to 0 (12-hour mode).

Count 0 to 2 w hen the H12_H24 bit is set

to 1 (24-hour mode).

0 to 2

(BCD code) R/W

b5 HR11 R/W

b6 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b7 BSY Timer RE busy flag This bit is set to 1 while registers TRESEC, TREMIN,

TREHR, and TREWK are updated. R

Address 011Bh

Bitb7b6b5b4b3b2b1b0

Symbol BSY — — — — WK2 WK1 WK0

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 WK0 Day of week count bit b2 b1 b0

0 0 0: Sunday

0 0 1: Monday

0 1 0: Tuesday

0 1 1: Wednesday

1 0 0: Thursday

1 0 1: Friday

1 1 0: Saturday

1 1 1: Do not set.

R/W

b1 WK1 R/W

b2 WK2 R/W

b3 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b4 —

b5 —

b6 —

b7 BSY Timer RE busy flag This bit is set to 1 while registers TRESEC, TREMIN,

TREHR, and TREWK are updated. R

R8C/34C Group 21. Timer RE

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 421 of 723

21.2.5 Timer RE Control Register 1 (TRECR1) in Real-Time Clock Mode

Note:

1. This bit is automatically modified while timer RE counts.

Figure 21.2 Definition of Time Representation

Address 011Ch

Bitb7b6b5b4b3b2b1b0

Symbol TSTART H12_H24 PM TRERST INT TOENA TCSTF —

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b1 TCSTF Timer RE count status flag 0: Count stopped

1: Counting R

b2 TOENA TREO pin output en able bit 0: Disable clock output

1: Enable clock output R/W

b3 INT Interrupt request timing bit Set to 1 in real-time clock mode. R/W

b4 T RERST Timer RE reset bit When setting this bit to 0, after setting it to 1, the followings

will occur.

• Regi sters TRESEC, TREMIN, TREHR, TREWK, and

TRECR2 are set to 00h.

• Bits TCSTF, INT, PM, H12_H24, and TSTART in the

TRECR1 register are set to 0.

• The 8-bit counter is set to 00h and the 4-bit counter is set

to 0h.

R/W

b5 PM A.m./p.m. bit When the H12_H24 bit is set to 0 (12-hour mode) (1)

0: a.m.

1: p.m.

When the H12_H24 bit is set to 1 (24-hour mode), its value

is undefined.

R/W

b6 H12_H24 Operating mode select bit 0: 12-hour mode

1: 24-hour mode R/W

b7 TSTART Timer RE count start bit 0: Count stops

1: Count starts R/W

Noon

H12_H24 bit = 1

(24-hour mode)

Contents of PM bit 0 (a.m.) 1 (p.m.)

Contents of

TREHR Register H12_H24 bit = 0

(12-hour mode)

Contents in TREWK register 000 (Sunday)

0 1 2 3 4 5 7 9 11 13 15 176 8 10 12 14 16

0 1 2 3 4 5 7 9 11 1356810 024

H12_H24 bit = 1

(24-hour mode)

Contents of PM bit 1 (p. m.)

Contents of

TREHR Register H12_H24 bit = 0

(12-hour mode)

Contents in TREWK register 000 (Sunday)

18 19 20 21 22 23 1 30 2 ⋅⋅⋅

6 7 8 9 10 11 1 30 2

Date changes

⋅⋅⋅

⋅⋅⋅0 (a.m.)

001 (Monday) ⋅⋅⋅

PM bit and H12_H24 bits: Bits in TRECR1 register

The above applies to the case when count starts from a.m. 0 on Sunday.

R8C/34C Group 21. Timer RE

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 422 of 723

21.2.6 Timer RE Control Register 2 (TRECR2) in Real-Time Clock Mode

Note:

1. Do not set multiple enable bits to 1 (enable interrupt).

Address 011Dh

Bitb7b6b5b4b3b2b1b0

Symbol — — COMIE WKIE DYIE HRIE MNIE SEIE

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 SEIE Periodic interrupt triggered every

second enable bit (1) 0: Disable periodic interrupt triggered every second

1: Enable periodic interrupt triggered every second R/W

b1 MNIE Periodic interrupt triggered every

minute enable bit (1) 0: Disable periodic interrupt triggered every minute

1: Enable periodic interrupt triggered every minute R/W

b2 HRIE Periodic interrupt triggered every

hour enable bit (1) 0: Disable periodic interrupt triggered every hour

1: Enable periodic interrupt triggered every hour R/W

b3 DYIE Periodic interrupt triggered every

day enable bit (1) 0: Disable periodic interrupt triggered every day

1: Enable periodic interrupt triggered every day R/W

b4 WKIE Periodic interrupt triggered every

week enable bit (1) 0: Disable periodic interrupt triggered every week

1: Enable periodic interrupt triggered every week R/W

b5 COMIE Compare match interrupt ena ble bit Set to 0 in real-time clock mode. R/W

b6 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b7 —

Table 21.3 Interrupt Sources

Factor Interrupt Source Interrupt Enable Bit

Periodic interrupt

triggered every week Value in TREWK register is set to 000b (Sunday)

(1-week perio d) WKIE

Periodic interrupt

triggered every da y TREWK register is updated (1-day period) DYIE

Periodic interrupt

triggered every ho ur TREHR register is updated (1-hour period) HRIE

Periodic interrupt

triggered every minute TREMIN register is updated (1-minute period) MNIE

Periodic interrupt

triggered every second TRESEC register is updated (1-second period) SEIE

R8C/34C Group 21. Timer RE

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 423 of 723

21.2.7 Timer RE Count Source Select Register (TRECSR) in Real-Time Clock

Mode

Note:

1. Write to bits RCS4 to RCS6 when the TOENA bit in the T RECR1 register is set to 0 (disable clock output).

21.2.8 Timer Pin Select Register (TIMSR)

The TIMSR register selects which pin is assigned to the timer RE output. To use the output pin for timer RE, set

this register.

Set the TIMSR register before setting the timer RE associated registers. Also, do not change the setting value in

this register during timer RE operation.

Address 011Eh

Bitb7b6b5b4b3b2b1b0

Symbol — RCS6 RCS5 RCS4 RCS3 RCS2 RCS1 RCS0

After Reset00001000

Bit Symbol Bit Name Function R/W

b0 RCS0 Count source select bit Set to 00b in real-time clock mode. R/W

b1 RCS1 R/W

b2 RCS2 4-bit counter select bit Set to 0 in real-time clock mode. R/W

b3 RCS3 Real-time clock mode select bit Set to 1 in real-time clock mode. R/W

b4 RCS4 Clock output select bit (1) b6 b5 b4

0 0 0: f2

0 0 1: fC

0 1 0: f4

0 1 1: 1Hz

1 0 0: f8

Other than above: Do not set.

R/W

b5 RCS5 R/W

b6 RCS6 R/W

b7 — Nothing is assig ned. If necessary, set to 0. When read, the content is 0. —

Address 0186h

Bitb7b6b5b4b3b2b1 b0

Symbol———————TREOSEL0

After Reset0000000 0

Bit Symbol Bit Name Function R/W

b0 TREOSEL0 TREO pin select bit 0: P0_4 assigned

1: P6_0 assigned R/W

b1 — N othing is assigned. If necessary, set to 0. When read, the content is 0. —

b2 —

b3 —

b4 —

b5 —

b6 —

b7 —

R8C/34C Group 21. Timer RE

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 424 of 723

21.2.9 Operating Example

Figure 21.3 Operating Example in Real-Time Clock Mode

IR bit in TREIC register

Bits WK2 to WK0 in

TREWK regist e r

(when SEIE bit in TRECR2 register is set

to 1 (enable periodic interrupt triggered

every second))

(when MNIE bit in TRECR2 register is set

to 1 (enable periodic interrupt triggered

every minu te))

PM bit in

TRECR1 register

Bits HR11 to HR00 in

TREHR register (Not changed)

Set to 0 by acknowledgement

of interrupt request

or a program

Bits MN12 to MN00 in

TREMIN register

58 59 00

BSY bit

Approx.

62.5 ms

Bits SC12 to SC00 in

TRESEC reg ister

BSY: Bit in registers TRESEC, TREMIN, TREHR, and TREWK

Approx.

62.5 ms

(Not change d)

(Not changed)

R8C/34C Group 21. Timer RE

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 425 of 723

21.3 Output Compare Mode

In output compare mode, the internal count source divided by 2 is counted using the 4-bit or 8-bit counter and

compare value match is detect ed with the 8-bit counter. Figure 21.4 shows a Block Diagram of Output Compare

Mode and Table 21.4 lists the Output Compare Mode Specifications. Figure 21.5 shows the Operating Example in

Output Compare Mode.

Figure 21.4 Block Diagram of Output Compare Mode

fC4

f32

4-bit

counter 8-bit

counter

TRESEC TREMIN

1/2 RCS2 = 1

RCS2 = 0

COMIE Timer RE interrupt

Match

signal

= 00b

= 01b

= 10b

= 11b

RCS1 to RC S 0

TRERST, TOENA: Bits in TRECR1 register

COMIE: Bit in TRECR2 register

RCS0 to RCS2, RCS4 to RCS6: Bits in TRECSR register

RReset

TRERST

Data bus

Comparison

circuit

RCS6 to RCS4

=000b

=010b

=100b

=110b TOENA

=001b

TREO pin (1)

Note

1: The TREOSEL0 bit in the TIMSR register is used to

select which pin is assigned.

R8C/34C Group 21. Timer RE

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 426 of 723

Table 21.4 Output Compare Mode Specifications

Item Specification

Count sources f4, f8, f32, fC4

Count operations •Increment

• When the 8-bit counter content matches with the TREMIN register

content, the value returns to 00h and count continues.

The count value is held while count stops.

Count period • When RCS2 = 0 (4-bit counter is not used)

1/fi x 2 x (n+1)

• When RCS2 = 1 ( 4-bit counter is used)

1/fi x 32 x (n+1)

fi: Frequency of coun t source

n: Setting value of TREMIN register

Count start condition 1 (count starts) is written to the TSTART bit in the TRECR1 register

Count stop condition 0 (count stops) is written to the TSTART bit in the TRECR1 register

Interrupt request generation

timing When the 8-bit counter content matches with the TREMIN register content

TREO pin function Select any one of the following:

• Programmable I/O ports

• Output f2, fC, f4, or f8

• Compare output

Read from timer When reading the TRESEC register, the 8-bit counter value can be read.

When reading the TREMIN register, the compare value can be read.

Write to timer Writing to the TRESEC register is disabled.

When bits TSTART and TCSTF in the TRECR1 register are set to 0 (timer

stops), writing to the TREMIN register is enab led.

Selectable func tion s •Select use of 4-bit counte r

• Compare output function

Every time the 8-bit counter value matches the TREMIN register valu e,

TREO output polarity is revers ed. The TREO pin outputs “L” after reset

is deasserted and the timer RE is reset by the TRERST bit in the

TRECR1 register. Output level is held by setting th e TSTART bit to 0

(count stops).

• TREO pin select function

P0_4 or P6_0 is selected by the TREOSEL0 bit in the TIMSR register.

R8C/34C Group 21. Timer RE

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 427 of 723

21.3.1 Timer RE Counter Data Register (TRESEC) in Output Compare Mode

21.3.2 Timer RE Compare Data Register (TREMIN) in Output Compare Mode

Address 0118h

Bitb7b6b5b4b3b2b1b0

Symbol————————

After Reset00000000

Bit Function R/W

b7 to b0 8-bit counter data can be read.

Although Timer RE stops counting, the count value is held.

The TRESEC register is set to 00h at the compare match.

Address 0119h

Bitb7b6b5b4b3b2b1b0

Symbol————————

After Reset00000000

Bit Function R/W

b7 to b0 8-bit compare data is stored. R/W

R8C/34C Group 21. Timer RE

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 428 of 723

21.3.3 Timer RE Control Register 1 (TRECR1) in Output Compare Mode

21.3.4 Timer RE Control Register 2 (TRECR2) in Output Compare Mode

Address 011Ch

Bitb7b6b5b4b3b2b1b0

Symbol TSTART H12_H24 PM TRERST INT TOENA TCSTF —

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b1 T CSTF Timer RE count status flag 0: Count stopped

1: Counting R

b2 TOENA TREO pin output enable bit 0: Disable clock output

1: Enable clock output R/W

b3 INT Interrupt requ est timing bit S et to 0 in outp ut compare mode. R /W

b4 TRERST Timer RE reset bit When setting this bit to 0, after setting it to 1, the

following will occur.

• Registers TRESEC, TREMIN, TREHR, TREWK,

and TRECR2 are set to 00h.

• Bits TCSTF, INT, PM, H12_H24, and TSTART in

the TRECR1 register are set to 0.

• The 8-bit counter is set to 00h and the 4-bit

counter is set to 0h.

R/W

b5 PM A.m./p.m. bit Set to 0 in output compare mode. R/W

b6 H12_H2 4 Oper ating mode select bit R/W

b7 TSTART Timer RE count start bit 0: Count stops

1: Count starts R/W

Address 011Dh

Bitb7b6b5b4b3b2b1b0

Symbol — — COMIE WKIE DYIE HRIE MNIE SEIE

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 SEIE Periodic interrupt triggered every

second enable bit Set to 0 in output compare mode. R/W

b1 MNIE Periodic interrupt triggered every

minute enable bit R/W

b2 HRIE Periodic interrupt triggered every hour

enable bit R/W

b3 DYIE Periodic interrupt triggered every day

enable bit R/W

b4 WKIE Periodic interrupt triggered every

week enable bit R/W

b5 COMIE Compare match interrupt enable bit 0: Disable compare match interrupt

1: Enable compare match interrupt R/W

b6 — Nothing is assig ned. If necessary, set to 0. When read, the content is 0. —

b7 —

R8C/34C Group 21. Timer RE

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 429 of 723

21.3.5 Timer RE Count Source Select Register (TRECSR) in Output Compare

Mode

Notes:

1. Write to bits RCS0 to RCS2 when the TCSTF bit in the TRECR1 register is set to 0 (count stopped).

2. Write to bits RCS4 to RCS6 when the TOENA bit in the T RECR1 register is set to 0 (disable clock output).

21.3.6 Timer Pin Select Register (TIMSR)

The TIMSR register selects which pin is assigned to the timer RE output. To use the output pin for timer RE, set

this register.

Set the TIMSR register before setting the timer RE associated registers. Also, do not change the setting value in

this register during timer RE operation.

Address 011Eh

Bitb7b6b5b4b3b2b1b0

Symbol — RCS6 RCS5 RCS4 RCS3 RCS2 RCS1 RCS0

After Reset00001000

Bit Symbol Bit Name Function R/W

b0 RCS0 Count source select bit (1) b1 b0

0 0: f4

0 1: f8

1 0: f32

1 1: fC4

R/W

b1 RCS1 R/W

b2 RCS2 4-bi t co un te r s elect bit (1) 0: Not used

1: Used R/W

b3 RCS3 Real-time clock mode select bit Set to 0 in output compa re mode. R/W

b4 RCS4 Clock output select bit (2) b6 b5 b4

0 0 0: f2

0 0 1: fC

0 1 0: f4

1 0 0: f8

1 1 0: Compare outp ut

Other than above: Do not set.

R/W

b5 RCS5 R/W

b6 RCS6 R/W

b7 — Nothing is assig ned. If necessary, set to 0. When read, the content is 0. —

Address 0186h

Bitb7b6b5b4b3b2b1 b0

Symbol———————TREOSEL0

After Reset0000000 0

Bit Symbol Bit Name Function R/W

b0 TREOSEL0 TREO pin select bit 0: P0_4 assigned

1: P6_0 assigned R/W

b1 — N othing is assigned. If necessary, set to 0. When read, the content is 0. —

b2 —

b3 —

b4 —

b5 —

b6 —

b7 —

R8C/34C Group 21. Timer RE

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 430 of 723

21.3.7 Operating Example

Figure 21.5 Operating Example in Output Comp are Mode

2 cycles of maximum count source

00h

8-bit counter content

(hexadecimal number)

Count start s

Time

TSTART bit in

TRECR1 register

IR bit in

TREIC register

The above appli es und er th e fo llo wing conditions.

TOENA bit in TRECR1 register = 1 (enable clock out pu t)

COMIE bit in T RECR2 register = 1 (enable com pare matc h int errupt )

RCS6 to RCS4 bits in TR ECSR register = 110b (compare output )

Set to 1 by a program

Set to 0 by ackn owledgement of interrupt reques t

or a program

TREMIN register

setting value

Matched

TREO output

TCSTF bit in

TRECR1 register

Output polarit y is inv e rte d

when the compar e matches

Matched Matched

R8C/34C Group 21. Timer RE

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 431 of 723

21.4 Notes on Timer RE

21.4.1 Starting and Stopping Count

Timer RE has the TSTART bit for instructing the count to start or stop, and the TCSTF bit, which indicates

count start or stop. Bits TSTART and TCSTF are in the TRECR1 regi ster.

Timer RE starts counting and the TCSTF bit is set to 1 (count starts) when the TSTART bit is set to 1 (count

starts). It takes up to 2 cycles of the count source until the TCSTF bit is set to 1 after setting the TSTART bit to

1. During this time, do not access registers associated with timer RE (1) other than the TCSTF bit.

Also, timer RE stops counting when setting the TSTART bit to 0 (count stops) and the TCSTF bit is set to 0

(count stops). It takes the tim e for up to 2 cycles of the count source unti l the TCSTF bit is set to 0 afte r setting

the TSTART bit to 0. During this time, do not access registers associated with timer RE other than the TCSTF

bit.

Note:

1. Registers associated with timer RE: TRESEC, TREMIN, TREHR, TREWK, TRECR1, TRECR2, and

TRECSR.

21.4.2 Register Setting

Write to the following registers or bits when timer RE is stopped.

•Registers TRESEC, TREMIN, TREHR, TREWK, and TRECR2

•Bits H12_H24, PM, and INT in TRECR1 register

•Bits RCS0 to RCS3 in TRECSR register

Timer RE is stopped when bits TSTART and TCSTF in the TRECR1 register are set to 0 (timer RE stopped).

Also, set all above-mentioned registers and bits (immediately before timer RE count starts) before setting the

TRECR2 register.

Figure 21.6 shows a Setting Example in Real-Time Clock Mode.

R8C/34C Group 21. Timer RE

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 432 of 723

Figure 21.6 Setting Example in Real-Time Clock Mode

Stop timer RE operation

TCSTF in TRECR1 = 0?

TSTART in TRECR1 = 0

TRERST in TRECR1 = 1

TRERST in TRECR1 = 0

Setting of registers TRECSR,

TRESEC, TREMIN, TREHR,

TREWK, and bits H12_H24, PM,

and INT in TRECR1 register

Setting of TRECR2

TSTART in TRECR1 = 1

TCSTF in TRECR1 = 1?

TREIC ← 00h

(disable timer RE interrupt)

Setting of TREIC (IR bit ← 0,

select interrupt priority level)

Timer RE register

and control circuit reset

Select clock output

Select clock source

Seconds, minutes, hours, days of week, operating mode

Set a.m./p.m., interrupt timing

Select interrupt source

Start timer RE operation

TOENA in TRECR1 = 0 Disable timer RE clock output

(When it is necessary)

TOENA in TRECR1 = 1 Enable timer RE clock output

(When it is necessary)

R8C/34C Group 21. Timer RE

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 433 of 723

In real-time clock mode, read registers TRESEC, TREMIN, TREHR, and TREWK when time data is updated

and read the PM bit in the TRECR1 register when the BSY bit is set to 0 (not while data is updated).

Also, when reading several registers, an incorrect time will be read if data is updated befo re another register is

read after reading any register.

In order to prevent this, use the reading procedure shown below.

•Using an interrupt

Read necessary contents of registers TRESEC, TREMIN, TREHR, and TREWK and the PM bit in the

TRECR1 register in the timer RE in terrupt routine.

•Monitoring with a program 1

Monitor the IR bit in the TREIC register with a program and read necessary contents of registers TRESEC,

TREMIN, TREHR, and TREWK and the PM bit in the TRECR1 register after the IR bit in the TREIC register

is set to 1 (timer RE interrupt request generated).

•Monitoring with a program 2

(1) Monitor the BSY bit.

(2) Monitor until the BSY bit is set to 0 after the BSY bit is set to 1 (approximate ly 62.5 ms while the BSY bit

is set to 1).

(3) Read necessary contents of registers TRESEC, TREMIN, TREHR, and TREWK and the PM bit in the

TRECR1 register after the BSY bit is set to 0.

•Using read results if they are the same value twice

(1) Read necessary contents of registers TRESEC, TREMIN, TREHR, and TREWK and the PM bit in the

TRECR1 register.

(2) Read the same register as (1) and compare the contents.

(3) Recognize as the correct value if the contents match. If the contents do not match, repeat until the read

contents match with the previous contents.

Also, when reading several registers, read them as continuously as possible.

R8C/34C Group 22. Serial Interface (UARTi (i = 0 or 1))

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 434 of 723

22. Serial Interface (UARTi (i = 0 or 1))

The serial interface consists of three channels, UART0 to UART2. This chapter describes the UARTi (i = 0 or 1).

22.1 Overview

UART0 and UART 1 have a dedicated timer to generate a transfer clock and operate independently. UART0 and

UART1 support clock synchronous serial I/O mode and clock asynchronous serial I/O mode (UART mode).

Figure 22.1 shows a UARTi (i = 0 or 1) Block Diagram. Figure 22.2 shows a Block Diagram of UARTi

Transmit/Receive Unit. Table 22.1 lists the Pin Configuration of UARTi (i = 0 or 1).

Figure 22.1 UARTi (i = 0 or 1) Block Diagram

= 01b

= 10b

CLK1 and CLK0 = 00b

RXDi

f32

1/16

1/2

1/(n0+1)

UART reception

UART transmission

Clock synchronous type

(internal clock selected)

Clock synchronous type Reception control

circuit

Transmission

control circuit

CKDIR = 0

CKDIR = 1

Receive clock

Transmit clock

Transmit/

receive

unit

UiBRG register

CKDIR = 0

Internal

External

CKDIR = 1

UARTi

TXDi

CLK

polarity

switch

circuit

CLKi

Clock synchronous type

(external cl oc k se lected)

Clock synchronous type

(internal clock selected)

CKDIR: Bit in UiMR register

CLK0, CLK1: Bits in UiC0 register

i = 0 or 1

= 11b

R8C/34C Group 22. Serial Interface (UARTi (i = 0 or 1))

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 435 of 723

Figure 22.2 Block Diagram of UARTi Transmit/Receive Unit

Table 22.1 Pin Configuration of UARTi (i = 0 or 1)

Pin Name Assigned Pin I/O Function

TXD0 P1_4 Output Serial data output

RXD0 P1_5 Input Serial data input

CLK0 P1_6 I/O Transfer clock I/O

TXD1 P0_1 or P6_3 Output Serial data output

RXD1 P0_2 or P6_4 Input Serial data input

CLK1 P0_3, P6_2, or P6_5 I/O Transfer clock I/O

RXDi

1SP

2SP

SP SP PAR

PRYE = 0

PAR

disabled

PAR enabled

PRYE = 1 UART UART (9 bits)

D7 D6 D5 D4 D3 D2 D1 D0

UARTi receive register

UiRB register

0000000D8

MSB/LSB conversion circuit

Data bus high-order bits

Data bus low- order bits

D7 D6 D5 D4 D3 D2 D1 D0 UiTB register

TXDi

1SP

2SP

SP SP PAR

UARTi transmit register

0i = 0 or 1

SP: Stop bit

PAR: Parity bit

UART (7 bits)

UART (8 bits)

Clock

synchronous

type

Clock

synchronous

type UART (7 bits)

Clock

synchronous

type

UART (7 bits)

Clock

synchronous

type

UART (8 bits)

UART (9 bits)

UART (7 bits)

UART (8 bits)

Clock

synchronous

type

UART (9 bits)

UART

PRYE = 1

PAR enabled

PAR

disabled

PRYE = 0

Clock

synchronous

type

MSB/LSB conversion circuit

UART (8 bits)

UART (9 bits)

R8C/34C Group 22. Serial Interface (UARTi (i = 0 or 1))

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 436 of 723

22.2 Registers

22.2.1 UARTi Transmit/Receive Mode Register (UiMR) (i = 0 or 1)

22.2.2 UARTi Bit Rate Register (UiBRG) (i = 0 or 1)

Write to the UiBRG register while transmission and reception stop.

Use the MOV instruction to write to this register.

Set bits CLK0 and CLK1 in the UiC0 register before writing to the UiBRG register.

Address 00A0h (U0MR), 0160h (U1MR)

Bitb7b6b5b4b3b2b1b0

Symbol — PRYE PRY STPS CKDIR SMD2 SMD1 SMD0

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 SMD0 Serial I/O mode select bit b2 b1 b0

0 0 0: Serial interf ace di sa bl e d

0 0 1: Clock synchronous serial I/O mode

1 0 0: UART mode, transfer data 7 bits long

1 0 1: UART mode, transfer data 8 bits long

1 1 0: UART mode, transfer data 9 bits long

Other than above: Do not set.

R/W

b1 SMD1 R/W

b2 SMD2 R/W

b3 CKDIR Internal/external clock select bit 0: Internal clock

1: External clock R/W

b4 STPS Stop bit length select bit 0: One stop bit

1: Two stop bits R/W

b5 PRY Odd/even parity select bit Enabled when PRYE = 1

0: Odd parity

1: Even parity

R/W

b6 PRYE Parity enable bit 0: Parity disabled

1: Parity enabled R/W

b7 — Reserved bit Set to 0. R/W

Address 00A1h (U0BRG), 0161h (U1BR G)

Bitb7b6b5b4b3b2b1b0

Symbol————————

After ResetXXXXXXXX

Bit Function Setting Range R/W

b7 to b0 If the setting value is n, UiBRG divides the count source by n+1. 00h to FFh W

R8C/34C Group 22. Serial Interface (UARTi (i = 0 or 1))

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 437 of 723

22.2.3 UARTi Transmit Buffer Register (UiTB) (i = 0 or 1)

If the transfer data is 9 bits long, write data to the high-order byte first, then low-order byte of the UiTB register.

Use the MOV instruction to write to this register.

Address 00A3h to 00A2h (U0TB), 0163h to 0162h (U1TB)

Bitb7b6b5b4b3b2b1b0

Symbol————————

After ResetXXXXXXXX

Bit b15 b14 b13 b12 b11 b10 b9 b8

Symbol————————

After ResetXXXXXXXX

Bit Symbol Function R/W

b0 — Transmit data W

b1 —

b2 —

b3 —

b4 —

b5 —

b6 —

b7 —

b8 —

b9 — Nothing is assigned. If necessary, set to 0. When read, the content is undefined. —

b10 —

b11 —

b12 —

b13 —

b14 —

b15 —

R8C/34C Group 22. Serial Interface (UARTi (i = 0 or 1))

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 438 of 723

22.2.4 UARTi Transmit/Receive Control Register 0 (UiC0) (i = 0 or 1)

Note:

1. If the BRG count source is switched, set the UiBRG register again.

22.2.5 UARTi Transmit/Receive Control Register 1 (UiC1) (i = 0 or 1)

Notes:

1. The RI bit is set to 0 when the higher byte of the UiRB register is read.

2. In UART mode, set the UiRRM bit to 0 (continuous receive mode disabled).

Address 00A4h (U0C0), 0164h (U1C0)

Bitb7b6b5b4b3b2b1b0

Symbol UFORM CKPOL NCH — TXEPT — CLK1 CLK0

After Reset00001000

Bit Symbol Bit Name Function R/W

b0 CLK0 BRG count source select bit (1) b1 b0

0 0: f1 selected

0 1: f8 selected

1 0: f32 selected

1 1: fC selected

R/W

b1 CLK1 R/W

b2 — Reserved bit Set to 0. R/W

b3 TXEPT Transmit register empty flag 0: Data present in the transmit register

(transmission in progress)

1: No data in the transmit register

(transmission completed)

b4 — Nothing is assig ned. If necessary, set to 0. When read, the content is 0. —

b5 NCH Data output select bit 0: TXDi pin set to CMOS output

1: TXDi pin set to N-channel open-drain output R/W

b6 CKPOL CLK polarity select bit 0: Transmit data output at the falling edge and receive

data input at the rising edge of the transfer clock

1: Transmit data output at the rising edge and receive

data input at the falling edge of the transfer clock

R/W

b7 UFORM Transfer format select bit 0: LSB first

1: MSB first R/W

Address 00A5h (U0C1), 0165h (U1C1)

Bitb7b6b5b4b3b2b1b0

Symbol — — UiRRM UiIRS RI RE TI TE

After Reset00000010

Bit Symbol Bit Name Function R/W

b0 TE Transmit enab le bit 0: Transmission disabled

1: Transmission enabled R/W

b1 TI Transmit buffer empty fl ag 0: Data present in the UiTB register

1: No data in the UiTB register R

b2 RE Receive enable bit 0: Reception disabled

1: Reception enable d R/W

b3 RI Receive complete flag (1) 0: No data in the UiRB register

1: Data present in the UiRB register R

b4 UiIRS UARTi transmit interrupt source

select bit 0: Transmission buffer empty (TI = 1)

1: Transmission completed (TXEPT = 1) R/W

b5 UiRRM UARTi continuous receive mode

enable bit (2) 0: Continuous receive mode disabled

1: Continuous receive mode enabled R/W

b6 — Nothing is assig ned. If necessary, set to 0. When read, the content is 0. —

b7 —

R8C/34C Group 22. Serial Interface (UARTi (i = 0 or 1))

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 439 of 723

22.2.6 UARTi Receive Buffer Register (UiRB) (i = 0 or 1)

Note:

1. Bits SUM, PER, FER, and OER are set to 0 (no error) when either of the following is set:

- Bits SMD2 to SMD0 in the UiMR register are set to 000b (serial interface disabled), or

- The RE bit in the UiC1 register is set to 0 (reception disabled)

The SUM bit is set to 0 (no error) when all of bits PER, FER, and OER are set to 0 (no error).

Bits PER and FER are also set to 0 when the high-order byte of the UiRB register is read.

When setting bits SMD2 to SMD0 in the UiMR register to 000b, set the TE bit in the UiC1 register to 0

(transmission disabled) and the RE bit to 0 (reception disabled).

2. These error flags are invalid when bits SMD 2 to SMD0 in the UiMR register are set to 001b (clock synchronous

serial I/O mode). When read, the content is unde f i n ed .

Always read the UiRB register in 16-bit units.

Address 00A7h to 00A6h (U0RB), 0167h to 0166h (U1RB)

Bitb7b6b5b4b3b2b1b0

Symbol————————

After ResetXXXXXXXX

Bit b15 b14 b13 b12 b11 b10 b9 b8

Symbol SUM PER FER OER — — — —

After ResetXXXXXXXX

Bit Symbol Bit Name Function R/W

b0 — — Receive data (D7 to D0) R

b1 —

b2 —

b3 —

b4 —

b5 —

b6 —

b7 —

b8 — — Receive data (D8) R

b9 — Nothing is assigned. If necessary, set to 0. When read, the content is undefined. —

b10 —

b11 —

b12 OER Overrun error flag (1) 0: No overrun error

1: Overrun error R

b13 FER Framing error flag (1, 2) 0: No framing error

1: Framing error R

b14 PER Parity error flag (1, 2) 0: No parity error

1: Parity error R

b15 SUM Error sum flag (1, 2) 0: No error

1: Error R

R8C/34C Group 22. Serial Interface (UARTi (i = 0 or 1))

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 440 of 723

22.2.7 UART0 Pin Select Register (U0SR)

The U0SR register selects which pin is assigned to the UART0 I/O. To use the I/O pin for UART0, set this

Set the U0SR register before setting the UART0 associated registers. Also, do not change the setting value in

this register during UART0 operation.

22.2.8 UART1 Pin Select Register (U1SR)

The U1SR register selects which pin is assigned to the UART1 I/O. To use the I/O pin for UART1, set this

Set the U1SR register before setting the UART1 associated registers. Also, do not change the setting value in

this register during UART1 operation.

Address 0188h

Bitb7b6b5b4b3b2b1b0

Symbol — — — CLK0SEL0 — RXD0SEL0 — TXD0SEL0

After Reset000 0 0 0 0 0

Bit Symbol Bit Name Function R/W

b0 TXD0SEL0 TXD0 pin sel ect bit 0: TXD0 pin not used

1: P1_4 assigned R/W

b1 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b2 RXD0SEL0 RXD0 pin select bit 0: RXD0 pin not used

1: P1_5 assigned R/W

b3 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b4 CLK0SEL0 CLK0 pin select bit 0: CLK0 pin not used

1: P1_6 assigned R/W

b5 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b6 —

b7 —

Address 0189h

Bitb7b6b5b4b3b2b1b0

Symbol — — CLK1SEL1 CLK1SEL0 RXD1SEL1 RXD1SEL0 TXD1SEL1 TXD1SEL0

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 TXD1SEL0 TXD1 pin select bit b1 b0

0 0: TXD1 pin not used

0 1: P0_1 assigned

1 0: P6_3 assigned

1 1: Do not set.

R/W

b1 TXD1SEL1 R/W

b2 RXD1SEL0 RXD1 pin select bit b3 b2

0 0: RXD1 pin not used

0 1: P0_2 assigned

1 0: P6_4 assigned

1 1: Do not set.

R/W

b3 RXD1SEL1 R/W

b4 CLK1SEL0 CLK1 pin select bit b5 b4

0 0: CLK1 pin not used

0 1: P0_3 assigned

1 0: P6_2 assigned

1 1: P6_5 assigned

R/W

b5 CLK1SEL1 R/W

b6 — N othing is assigned. If necessary, set to 0. When read, the content is 0. —

b7 —

R8C/34C Group 22. Serial Interface (UARTi (i = 0 or 1))

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 441 of 723

22.3 Clock Synchronous Serial I/O Mode

In clock synchronous serial I/O mode, data is transmitted and received using a transfer clock.

Table 22.2 lists the Clock Synchronous Serial I/O Mode Specifications. Table 22.3 lists the Registers Used and

Settings in Clock Synchronous Serial I/O Mode.

i = 0 or 1

Notes:

1. When an external clock is selected, the requirements must be met in either of th e following states:

- The external clock is held high when the CKPOL bit in the UiC0 register is set to 0 (transmit data

output at the falling edge and receive data input at the rising edge of the transfer clock)

- The external clock is held low when the CKPOL bit in the UiC0 register is set to 1 (transmit data

output at the rising edge and receive data input at the falling edge of the transfer clock)

2. If an overrun error occurs, the receive data (b0 to b8) in the UiRB register will be undefined.

The IR bit in the SiRIC register remains unchanged.

Table 22.2 Clock Synchronous Serial I/O Mode Specifications

Item Specification

Transfer data format • Transfer data length: 8 bits

Transfer clocks • The CKDIR bit in the UiMR register is set to 0 (internal clock): fi/(2(n+1))

fi = f1, f8, f32, fC n = setting value in the UiBRG register: 00h to FFh

• The CKDIR bit is set to 1 (external clock): Input from the CLKi pin

Transmit start conditions •To start transmission, the following require ments must be met: (1)

- The TE bit in the UiC1 register is set to 1 (transmission enabled).

- The TI bit in the UiC1 register is set to 0 (data present in the UiTB

Receive start conditions • To start reception, the following requirements must be met: (1)

- The RE bit in the UiC1 register is set to 1 (reception enabled).

- The TE bit in the UiC1 register is set to 1 (transmission enabled).

- The TI bit in the UiC1 register is set to 0 (data present in the UiTB

Interrupt request

generation timing • For transmission: One of the following can be sele cted.

- The UiIRS bit is set to 0 (transmit buffer empty):

When data is transferred from the UiTB register to the UARTi transmit

- The UiIRS bit is set to 1 (transmission completed):

When data transmission from the UARTi transmit register is completed.

• For reception:

When data is transferred from the UARTi receive register to the UiRB

Error detection • Overrun error (2)

This error occurs if the serial interface st ar ts re ce ivin g th e next un it of da ta

before reading the UiRB register and receives the 7th bit of the next unit of

data.

Selectable func tion s • CLK polarity selection

Transfer data in put/output can be sele cted to occur sync hrono usly with the

rising or the falling edge of the transfer clock.

• LSB first, MSB first selection

Whether transmitting or receiving data beg ins with bit 0 o r begin s with b it 7

can be selected.

• Continu ous receive mode selection

Reception is enabled immediately by reading the UiRB register.

R8C/34C Group 22. Serial Interface (UARTi (i = 0 or 1))

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 442 of 723

i = 0 or 1

Note:

1. Set the bits not listed in this table to 0 when writing to the above registers in clock synchronous

serial I/O mode.

Table 22.3 Registers Used and Settings in Clock Synchronous Serial I/O Mode

UiTB b0 to b7 Set data transmission.

UiRB b0 to b7 Receive data can be read.

OER Overrun error flag

UiBRG b0 to b7 Set a bit rate.

UiMR SMD2 to SMD0 Set to 001b.

CKDIR Select the internal clock or external clock.

UiC0 CLK1, CLK0 Select the count source for the UiBRG register.

TXEPT Transmit register empty flag

NCH Select TXDi pin output mode.

CKPOL Select the transfer clock polarity.

UFORM Select LSB first or MSB first.

UiC1 TE Set to 1 to enable transmission/reception

TI Transmit buffer empty flag

RE Set to 1 to enable reception.

RI Receive complete flag

UiIRS Select the UARTi transmit interrupt source.

UiRRM Set to 1 to use continuous re ceive mode.

(1)

R8C/34C Group 22. Serial Interface (UARTi (i = 0 or 1))

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 443 of 723

Table 22.4 lists the I/O Pin Functions in Clock Synchronous Serial I/ O Mode.

After UARTi (i = 0 or 1 ) operating mode is selected, the TXDi pin outputs a “H” level until transfer starts. (If the

NCH bit is set to 1 (N-channel open-drain ou tput), this pin is in the high-impedance state.)

Table 22.4 I/O Pin Functions in Clock Synchronous Serial I/O Mode

Pin Name Function Selection Method

TXD0 (P1_4) Serial data output TXD0SEL0 bit in U0SR register = 1

For reception only:

P1_4 can be used as a port by setting TX D0SEL0 bit = 0.

RXD0 (P1_5) Serial data input RXD0SEL0 bit in U0SR register = 1

PD1_5 bit in PD1 register = 0

For transmission only:

P1_5 can be used as a port by setting RXD0SEL0 bit = 0.

CLK0 (P1_6) Transfer clock output CLK0SEL0 bit in U0SR register = 1

CKDIR bit in U0MR register = 0

Transfer clock input C LK0SEL0 bit in U0SR register = 1

CKDIR bit in U0MR register = 1

PD1_6 bit in PD1 register = 0

TXD1 (P0_1 or

P6_3) Serial data outpu t •TXD1 (P0_1)

Bits TXD1SEL1 to TXD1SEL0 in U1SR register = 01b (P0_1)

• TXD1 (P6_3)

Bits TXD1SEL1 to TXD1SEL0 in U1SR register = 10b (P6_3)

• For reception only:

P0_1 and P6_3 can be used as a port by setting b its TXD1SEL1

to TXD1SEL0 = 00b.

RXD1 (P0_2 or

P6_4) Serial data input • RXD1 (P0_2)

Bits RXD1SEL1 to RXD1SEL0 in U1SR register = 01b (P0_2)

PD0_2 bit in PD0 register = 0

• RXD1 (P6_4)

Bits RXD1SEL1 to RXD1SEL0 in U1SR register = 10b (P6_4)

PD6_4 bit in PD6 register = 0

• For transmission only:

P0_2 and P6_4 can be used as a port by setting bits RXD1SEL1

to RXD1SEL0 = 00b.

CLK1 (P0_3,

P6_2, or P6_5) Transfer clock output • CLK1 (P0_3)

Bits CLK1SEL1 to CLK1SEL0 in U1SR register = 01b (P0_3)

CKDIR bit in U1MR register = 0

• CLK1 (P6_2)

Bits CLK1SEL1 to CLK1SEL0 in U1SR register = 10b (P6_2)

CKDIR bit in U1MR register = 0

• CLK1 (P6_5)

Bits CLK1SEL1 to CLK1SEL0 in U1SR register = 11b (P6_5)

CKDIR bit in U1MR register = 0

Transfer clock input •CLK1 (P0_3)

Bits CLK1SEL1 to CLK1SEL0 in U1SR register = 01b (P0_3)

CKDIR bit in U1MR register = 1

PD0_3 bit in PD0 register = 0

• CLK1 (P6_2)

Bits CLK1SEL1 to CLK1SEL0 in U1SR register = 10b (P6_2)

CKDIR bit in U1MR register = 1

PD6_2 bit in PD6 register = 0

• CLK1 (P6_5)

Bits CLK1SEL1 to CLK1SEL0 in U1SR register = 11b (P6_5)

CKDIR bit in U1MR register = 1

PD6_5 bit in PD6 register = 0

R8C/34C Group 22. Serial Interface (UARTi (i = 0 or 1))

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 444 of 723

Figure 22.3 Transmit and Receive Timing in Clock Synchronous Serial I/O Mode

Transfer clock

TE bit in

UiC1 register

TXDi

• Transmit Timing Example (Internal Clock Selected)

Data is set in UiTB register.

Data transfer from UiTB register to UARTi transmit register

CLKi

TCLK Pulsing stops because TE bit is set to 0.

D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7

TC = TCLK = 2(n+1)/fi

fi: Frequency of UiBRG count source (f1, f8, f32, fC)

n: Setting value in UiBRG register

The above applies when:

• CKDIR bit in UiMR register = 0 (i nt ernal clock)

• CKPOL bit in UiC0 register = 0 (transmit data output at the falling edge and

receive data input at the rising edge of the transfer clock)

• UiIRS bit in UiC1 register = 0

(interru pt request gener ation when the transmit buff er is empty)

Set to 0 by an interrupt request acknowledgement or by a program.

Dummy data is set in UiTB register.

Data transfer from UiTB register to UARTi transmit register

1/fEXT

D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5

Receive data taken in

Data read from UiRB register

Data transfer from UARTi receive register

to UiRB register

TI bit in

UiC1 register

TXEPT bit in

UiC0 register

IR bit in

SiTIC register

Set to 0 when an interrupt request is acknowledged or by a program.

• Receive Timing Example (External Clock Sel ected)

RE bit in

UiC1 register

TE bit in

UiC1 register

TI bit in

UiC1 register

RI bit in

UiC1 register

IR bit in

SiRIC register

CLKi

RXDi

The above ap plies when:

• CKDIR bit in UiMR register = 1 (external clock)

• CKPOL bit in UiC0 register = 0 (transmit data output at the falling edge and

receive data input at th e rising edge of the transfer c l ock)

The following s hould be met when “ H” is applied to the CLKi pin before receiving data:

• TE bit in U i C1 register = 1 (transmissi on enabled)

• RE bit in UiC1 register = 1 (reception enable d)

• Dummy data is written to UiTB register

fEXT: Frequency of external clock

i = 0 or 1

R8C/34C Group 22. Serial Interface (UARTi (i = 0 or 1))

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 445 of 723

22.3.1 Measure for Dealing with Communication Errors

If communication is aborted or a communication error occurs while transmitting or receiving in clock

synchronous serial I/O mode, follo w the procedures below:

(1) Set the TE bit in the UiC1 register (i = 0 or 1) to 0 (transmission disabled) and the RE bit to 0 (reception

disabled).

(2) Set bits SMD2 to SMD0 in the UiMR register to 000b (se rial interface disabled).

(3) Set bits SMD2 to SMD0 in the UiMR register to 001b (clock synchronous serial I/O mode).

(4) Set the TE bit in the UiC1 register to 1 (transmission enabled) and the RE bit to 1 (reception enabled).

R8C/34C Group 22. Serial Interface (UARTi (i = 0 or 1))

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 446 of 723

22.3.2 Polarity Select Function

Figure 22.4 shows the Transfer Clock Polarity. Use the CKPOL bit in the UiC0 (i = 0 or 1) register to select the

transfer clock polarity.

Figure 22.4 Transfer Clock Polarity

22.3.3 LSB First/MSB First Select Function

Figure 22.5 show s the Transfer Format. Use the UFORM bit in the UiC0 (i = 0 to 1) register to select th e

transfer format.

Figure 22.5 Transfer Format

CLKi(1)

D0TXDi

• CKPO L bit in UiC0 register = 0 (transmit data output at the falling edge and

receive data input at the rising edge of the transfer clock)

D1 D2

Notes:

1. The CLKi pin level is high during no transfer.

2. The CLKi pin level is low during no transfer.

D3 D4 D5 D6 D7

D0RXDi D1 D2 D3 D4 D5 D6 D7

CLKi (2)

D0TXDi D1 D2 D3 D4 D5 D6 D7

D0RXDi D1 D2 D3 D4 D5 D6 D7

• CKPO L bit in UiC0 register = 1 (transmit data output at the rising edge and

receive data input at the falling edge of the transfer clock)

i = 0 or 1

CLKi

TXDi

• UFORM bit in UiC0 register = 0 (LSB first) (1)

D1 D2 D3 D4 D5 D6 D7

D0RXDi D1 D2 D3 D4 D5 D6 D7

CLKi

TXDi D6 D5 D4 D3 D2 D1 D0

RXDi

• UFORM bit in UiC0 registe r = 1 (MSB first) (1)

Note:

1. The above applies when:

CKPOL bit in UiC0 register = 0 (transmit data output at the falling edge and

receive data input at the rising edge of the transfer clock).

D7 D6 D5 D4 D3 D2 D1 D0

i = 0 or 1

R8C/34C Group 22. Serial Interface (UARTi (i = 0 or 1))

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 447 of 723

22.3.4 Continuous Receive Mode

Continuous receive mode is selected by setting the UiRRM bit in the UiC1 register (i = 0 or 1) to 1 (continuous

receive mode enabled). In this mode, reading the UiRB register sets the TI bit in the UiC1 register t o 0 (data

present in the UiTB register). If the UiRRM bit is set to 1, do not write dummy data to the UiTB register by a

program.

R8C/34C Group 22. Serial Interface (UARTi (i = 0 or 1))

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 448 of 723

22.4 Clock Asynchronous Serial I/O (UART) Mode

The UART mode allows data transmission and reception after setting the desired bit rate and transfer data format.

Table 22.5 lists the UART Mode Specifications. Table 22.6 lists the Registers Used and Settings in UART Mode.

i = 0 or 1

Notes:

1. If an overrun error occurs, the receive data (b0 to b8) in the UiRB register will be undefined.

The IR bit in the SiRIC register remains unchanged.

2. The framing error flag and the parity error flag are set to 1 when data is transferred from the UARTi

receive register to the UiRB register.

Table 22.5 UART Mode Specifications

Item Specification

Transfer data formats • Character bits (transfer data): Selectable among 7, 8 or 9 bits

• Start bit: 1 bit

• Parity bit: Selectable among odd, even, or none

• Stop bits: Selectable among 1 or 2 bits

Transfer clocks • The CKDIR bit in the UiMR register is set to 0 (internal clock): fj/(16(n+1) )

fj = f1, f8, f32, fC n = setting value in the UiBRG register: 00h to FFh

• The CKDIR bit is set to 1 (external clock): fEXT/(16(n+1))

fEXT: Input from the CLKi pin,

n = setting value in the UiBRG register: 00h to FFh

Transmit start conditions • To start tr ansmission, the following requirements must be met:

- The TE bit in the UiC1 register is set to 1 (transmission enabled).

- The TI bit in the UiC1 register is set to 0 (data present in the UiTB

Receive start conditions •To start reception, the following requi rements must be met:

- The RE bit in the UiC1 register is set to 1 (reception enabled).

- Start bit detection

Interrupt request

generation timing • For transmission: One of the following can be selected.

- The UiIRS bit is set to 0 (transmit buffer empty):

When data is transferred from the UiTB register to the UARTi transmit

- The UiIRS bit is set to 1 (transfer completed):

When data transmission from the UARTi transmit register is completed.

• For reception:

When data is transferred from the UARTi receive register to the UiRB

Error detection •Overrun error (1)

This error occurs if the serial interface starts receiving the next unit of data

before reading the UiRB register and receive the bit one before the last

stop bit of the next unit of data.

•Framing error

This error occurs when the set number of stop bits is not detected. (2)

• Parity error

This error occurs when par ity is enabled, and the number of 1’s in the

parity and character bi ts do not match the set number of 1’s. (2)

• Error sum flag

This flag is set to 1 if an overrun, framing, or parity error occurs.

R8C/34C Group 22. Serial Interface (UARTi (i = 0 or 1))

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 449 of 723

i = 0 or 1

Notes:

1. The bits used for transmission/rece i ve data are as follows:

- Bits b0 to b6 when transfer data is 7 bits long

- Bits b0 to b7 when transfer data is 8 bits long

- Bits b0 to b8 when transfer data is 9 bits long

2. The contents of the following are undefined:

- Bits 7 and 8 when the transfer data is 7 bits long

- Bit 8 when the transfer data is 8 bits long

Table 22.6 Registers Used and Settings in UART Mode

UiTB b0 to b8 Set transmit data. (1)

UiRB b0 to b8 Receive data can be read. (2)

OER,FER,PER,SUM Error flag

UiBRG b0 to b7 Set a bit rate.

UiMR SMD2 to SMD0 Set to 100b when transfer data is 7 bits long.

Set to 101b when transfer data is 8 bits long.

Set to 110b when transfer data is 9 bits long.

CKDIR Select the internal clock or external clock.

STPS Select the stop bit.

PRY, PRYE Select whether parity is included and wheth er odd or even.

UiC0 CLK0, CLK1 Select the count source for the UiBRG register.

TXEPT Transmit register empty flag

NCH Select TXDi pin output mode.

CKPOL Set to 0.

UFORM Select LSB first or MSB first when transfer data is 8 bits long.

Set to 0 when transfer data is 7 bits or 9 bits long .

UiC1 TE Set to 1 to enable transmission.

TI Transmit buffer empty flag

RE Set to 1 to enable reception.

RI Receive complete flag

UiIRS Select the UARTi transmit interrupt source.

UiRRM Set to 0.

R8C/34C Group 22. Serial Interface (UARTi (i = 0 or 1))

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 450 of 723

Table 22.7 lists the I/O Pin Functions in UART Mode.

After the UARTi (i = 0 to 1) operating mode is selected, the TXDi pin outputs a “H” level until transfer starts. (If

the NCH bit is set to 1 (N-channel open-drain output), this pin is in the high-impedance state.)

Table 22.7 I/O Pin Functions in UART Mode

Pin name Function Selection Method

TXD0 (P1_4) Serial data output TXD0SEL0 bit in U0SR register = 1

For reception only:

P1_4 can be used as a port by setting TX D0SEL0 bit = 0.

RXD0 (P1_5) Serial data input RXD0SEL0 bit in U0SR register = 1

PD1_5 bit in PD1 register = 0

For transmission only:

P1_5 can be used as a port by setting RXD0SEL0 bit = 0.

CLK0 (P1_6)

Programmable I/O port

CLK0SEL0 bit in U0SR register = 0 (CLK0 pin not used)

Transfer clock input CLK0 SEL0 bit in U0SR regi ster = 1

CKDIR bit in U0MR register = 1

PD1_6 bit in PD1 register = 0

TXD1 (P0_1 or

P6_3) Serial data output • TXD1 (P0_1)

Bits TXD1SEL1 to TXD1SEL0 in U1SR register = 01b (P0_1)

• TXD1 (P6_3)

Bits TXD1SEL1 to TXD1SEL0 in U1SR register = 10b (P6_3)

• For reception only:

P0_1 and P6_3 can be used as a port by setting bits

TXD1SEL1 to TXD1SEL0 = 00b.

RXD1 (P0_2 or

P6_4) Serial data input •RXD1 (P0_2)

Bits RXD1SEL1 to RXD1SEL0 in U1SR register = 01b (P0_2)

PD0_2 bit in PD0 register = 0

• RXD1 (P6_4)

Bits RXD1SEL1 to RXD1SEL0 in U1SR register = 10b (P6_4)

PD6_4 bit in PD6 register = 0

• For transmission only:

P0_2 and P6_4 can be used as a port by setting bits

RXD1SEL1 to RXD1SEL0 = 00b.

CLK1 (P0_3,

P6_2, or P6_5) Programmable I/O port Bits CLK1SEL1 to CLK1SEL0 in U1SR register = 00b

(CLK1 pin not used)

Transfer clock input • CLK1 (P0_3)

Bits CLK1SEL1 to CLK1SEL0 in U1SR register = 01b (P0_3)

CKDIR bit in U1MR register = 1

PD0_3 bit in PD0 register = 0

• CLK1 (P6_2)

Bits CLK1SEL1 to CLK1SEL0 in U1SR register = 10b (P6_2)

CKDIR bit in U1MR register = 1

PD6_2 bit in PD6 register = 0

• CLK1 (P6_5)

Bits CLK1SEL1 to CLK1SEL0 in U1SR register = 11b (P6_5)

CKDIR bit in U1MR register = 1

PD6_5 bit in PD6 register = 0

R8C/34C Group 22. Serial Interface (UARTi (i = 0 or 1))

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 451 of 723

Figure 22.6 Transmit Timing in UART Mode

Data is set in UiTB register.

Data is set in UiTB regi ster.

D1 D2 D3 D4 D5 D6 D7 P SP

ST D0 D1 D2 D3 D4 D5 D6 D7 P SPST D0 D1ST

D1 D2 D3 D4 D5 D6 D7 D8 SP SP

ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SPST D0 D1ST

Transfer clock

TE bit in

UiC1 register

TXDi

Set to 0 when an interrupt request is acknowledged or by a program.

• Transmit Timing Example When Transfer Data 8 Bits is Long (Parity Enabled, One Stop Bit)

TC = 16 (n + 1) / fj or 16 (n + 1) / fEXT

fj: Frequency of UiBRG count source (f1, f8, f32, fC)

fEXT: Frequency of UiBRG count source (external clock)

n: Settin g value in UiBRG regi s ter

i = 0 or 1

The above applies when:

• PRYE bit in UiMR register = 1 (parity enabled)

• STPS bit in UiMR register = 0 (one stop bit)

• UiIRS bit in UiC1 register = 1

(interrupt request generation when transmission is completed)

Start

bit Parity

bit

Pulsing stops because TE bit is set to 0.

TXDi

Data transfer from UiTB register to

UARTi transmit register

TI bit in

UiC1 register

TXEPT bit in

UiC0 register

IR bit in

SiTIC register

Stop

bit

• Transmit Timing Example When Transfer Data is 9 Bits Long (Parity Disabled, Two Stop Bits)

Stop

bit

Stop

bit

Start

bit

Transfer clock

TE bit in

UiC1 register

TI bit in

UiC1 register

TXEPT bit in

UiC0 register

IR bit in

SiTIC register

Data transfer from UiTB register to

UARTi transmit register

TC = 16 (n + 1) / fj or 16 (n + 1) / fEXT

fj: Frequency of UiBRG count source (f1, f8, f32, fC)

fEXT: Frequency of UiBRG count source (external clock)

n: Setting value in UiBRG register

i = 0 or 1

Set to 0 when an interrupt request is acknowledged or by a program.

The above applies when:

• PRYE bit in UiMR register = 0 (pa rity disabled)

• STPS bit in UiMR register = 1 (two stop bits)

• UiIRS bit in UiC1 register = 0

(interrupt request generation when the transmit buffer is empty)

R8C/34C Group 22. Serial Interface (UARTi (i = 0 or 1))

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 452 of 723

Figure 22.7 Receive Timing in UART Mode

UiBRG output

Set to 0 when an interrupt request is ac knowledged or by a program.

• Receive Timing Example When Transfer Data is 8 Bits Long (Parity Disabled, One Stop Bit)

The above applies when :

• PRYE bit in UiMR register = 0 (parity disabled)

• STPS bit in UiMR register = 0 (one s t op bi t)

i = 0 or 1

RE bit in

UiC1 register

Start bit Stop bit

D0 D1 D7

RXDi

Transfer clock

“L” is determined. Receive dat a taken in

Reception starts when a transfer clock is

generated at the falling edge of the start bit. Data transfer from UARTi receive register to UiRB register

RI bit in

UiC1 register

IR bit in

SiRIC register

R8C/34C Group 22. Serial Interface (UARTi (i = 0 or 1))

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 453 of 723

22.4.1 Bit Rate

In UART mode, the bit rate is the frequency divided by the UiBRG (i = 0 or 1) register and divided by 16.

Figure 22.8 Formula for Calculating Setting Value in UiBRG (i = 0 or 1) Register

i = 0 or 1

Note:

1. For the high-speed on-chip oscillator, the correction value in the FRA4 register should be written into the FRA1

This applies when the high-speed on-chip oscillator is selected as the system clock and bits FRA2 2 to FRA20

in the FRA2 register are set to 000b (divide-by-2 mode). For the precision of the high-speed on-chip oscillator,

refer to 33. Electrical Characteristics.

Table 22.8 Bit Rate Setting Example in UART Mode (Internal Clock Selected)

Bit Rate

(bps)

UiBRG

Count

Source

System Clock = 20 MHz System Clock = 18.432 MHz (1) System Clock = 8 MHz

UiBRG

Setting

Value

Actual Time

(bps)

Setting

Error

(%)

UiBRG

Setting

Value

Actual Time

(bps)

Setting

Error

(%)

UiBRG

Setting

Value

Actual

Time

(bps)

Setting

Error

(%)

1200 f8 129 (81h) 1201.92 0.16 119 (77h) 1200.00 0.00 51 (33h) 1201.92 0.16

2400 f8 64 (40h) 2403.85 0.16 59 (3Bh) 2400.00 0.00 25 (19h) 2403.85 0.16

4800 f8 32 (20h) 4734.85 -1.36 29 (1Dh) 4800.00 0.00 12 (0Ch) 4807.69 0.16

9600 f1 129 (81h) 9615.38 0.16 119 (77h) 9600.00 0.00 51 (33h) 9615.38 0.16

14400 f1 86 (56h) 14367.82 -0.22 79 (4Fh) 14400.00 0.00 34 (22h) 14285.71 -0.79

19200 f1 64 (40h) 19230.77 0.16 59 (3Bh) 19200.00 0.00 25 (19h) 19230.77 0.16

28800 f1 42 (2Ah) 29069.77 0.94 39 (27h) 28800.00 0.00 16 (10h) 29411.76 2.12

38400 f1 32 (20h) 37878.79 -1.36 29 (1Dh) 38400.00 0.00 12 (0Ch) 38461.54 0.16

57600 f1 21 (15h) 56818.18 -1.36 19 (13h) 57600.00 0.00 8 (08h) 55555.56 -3.55

115200 f1 10 (0Ah) 113636.36 -1.36 9 (09h) 11520 0.00 0.00 −−−

UART mode

• Internal clock selected

Setting value in UiBRG register = fj

Bit Rate × 16 − 1

fj: Count source frequency of UiBRG register (f1, f8, f32, or fC)

• External clock selected fEXT

Bit Rate × 16 − 1

fEXT: Count source frequency of UiBRG register (external clock)

Setting value in UiBRG register =

i = 0 or 1

R8C/34C Group 22. Serial Interface (UARTi (i = 0 or 1))

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 454 of 723

22.4.2 Measure for Dealing with Communication Errors

If communication is aborted or a communication error occurs while transmitting or receiving in UART mode,

follow the procedures below:

(1) Set the TE bit in the UiC1 register (i = 0 or 1) to 0 (transmission disabled) and the RE bit to 0 (reception

disabled).

(2) Set bits SMD2 to SMD0 in the UiMR register to 000b (se rial interface disabled).

(3) Set bits SMD2 to SMD0 in the UiMR register to 100b (UART mode, transfer data 7 bits long), 101b

(UART mode, transfer data 8 bits long), or 110b (UART mode, transfer data 9 bits long).

(4) Set the TE bit in the UiC1 register to 1 (transmission enabled) and the RE bit to 1 (reception enabled).

R8C/34C Group 22. Serial Interface (UARTi (i = 0 or 1))

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 455 of 723

22.5 Notes on Serial Interface (UARTi (i = 0 or 1))

•When reading data from the UiRB (i = 0 or 1) register either in clock synchronous serial I/O mode or in clock

asynchronous serial I/O mode, always read data in 16-bit unit s.

When the high-order byte of the UiRB register is read, bits PER and FER in the UiRB register and the RI bit in

the UiC1 register are set to 0.

To check receive errors, read the UiRB register and then use the read data.

Program example to read the receive buffer register:

MOV.W 00A6H,R0 ; Read the U0RB register

•When writing data to the UiTB register in clock asynchronous serial I/O mode with 9-bit transfer data length,

write data to the high-order byte first and then the low-order byte, in 8-bit units.

Program example to write to the transmit buffer register:

MOV.B #XXH,00A3H ; Write to the high-order byte of the U0TB register

MOV.B #XXH,00A2H ; Write to the low-order byte of the U0TB register

R8C/34C Group 23. Serial Interface (UART2)

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 456 of 723

23. Serial Interface (UART2)

The serial interface consists of three channels, UART0 to UART2. This chapter describes the UART2.

23.1 Overview

UART2 has a dedicated timer to generate a transfer clock.

Figure 23.1 shows a UART2 Block Diagram. Figure 23.2 shows a Block Diagram of UART2 Transmit/R eceive

Unit. Table 23.1 lists the Pin Confi guratio n of UART2.

UART2 has the following modes:

• Clock synchronous serial I/O mode

• Clock asynchronous serial I/O mode (UART mode)

• Special mode 1 (I2C mode)

• Multiprocessor communication function

Figure 23.1 UART2 Block Diagram

n: Setting value in U2BRG register

RXD2

1/(n+1) 1/16

U2BRG

Clock synchronous type

(internal clock selected)

Clock synchronous type

(internal clock selected)

Clock synchronous type

(external clock selec ted)

CLK2

Clock source selection

f32

CKDIR

internal

CKDIR

external

RTS2

CTS2

Transmit/

receive

unit

TXD2

CLK

polarity

switching

circuit

CTS/RTS disabled

CTS/RTS selected

Receive

clock

TXD

polarity

switching

circuit

CLK1 to CLK0

= 00b

= 01b

= 10b

CKPOL

UART reception

UART transmission

Clock synchronous type

CRS = 1

CRS = 0

RXD polarity

switching circuit

CRD = 0

VSS

CKDIR

= 0

CKDIR

= 1

SMD2 to SMD0

= 010b, 100b, 101b, 110b

= 001b

CKDIR = 0

SMD2 to SMD0, CKDIR: Bits in U2MR register

CLK1, CLK0, CKPOL, CRD, CRS: Bits in U2C0 register

DF2EN: Bit in URXDF register

CTS2/RTS2

DF2EN = 1

Digital fil ter

DF2EN = 0

= 11b

CKDIR = 1

= 100b, 101b, 110b

= 001b, 010b

1/16

1/2

Transmit

clock

CRD = 1

Reception

control circuit

Transmission

control circuit

R8C/34C Group 23. Serial Interface (UART2)

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 457 of 723

Figure 23.2 Block Diagram of UART2 Transmit/Receive Unit

Table 23.1 Pin Configuration of UART2

Pin Name Assigned Pin I/O Function

TXD2 P3_4, P3_7, or P6_6 Output Serial data output

RXD2 P3_4, P3_7, or P4_5 Input Serial data input

CLK2 P3_5 or P6_5 I/O Transfer clock I/O

CTS2 P3_3 Input Transmit control input

RTS2 P3_3 Output Receive control input

SCL2 P3_4, P3_7, or P4_5 I/O I2C mode clock I/O

SDA2 P3_4, P3_7, or P6_6 I/O I2C mode data I/O

UART

(8 bits)

UART

(9 bits)

U2ERE = 1

PAR

disabled

PAR

enabled

PRYE = 0

PRYE = 1

2SP

STPS = 1

1SP

SP SP PAR

UART

(7 bits)

UART

(8 bits)

UART (7 bits)

UART

(9 bits)

Clock

synchronous type

Data bus low-order bits

TXD2

UART2 transmit register

D8 D7 D6 D5 D4 D3 D2 D1 D0

SP: Stop bit

PAR: Parity bit

SMD2 to SMD0, STPS, PRYE, IOPOL, CKDIR: Bits in U2MR register

CLK1, CLK0, CKPOL, CRD, CRS: Bits in U2C0 register

U2ERE: Bit in U2C1 register

U2TB

UART

(8 bits)

UART

(9 bits)

I2C

Clock

synchronous type

U2RB

UART2 receive register

PAR

1SP

PAR

enabled

PAR

disabled

UART

(7 bits)

UART

(8 bits) UART (7 bits)

I2C

Clock

synchronous

type

Clock

synchronous type

RXD2

Data bus high-order bits

Logic inversion circuit + MSB/LSB conversion circuit

D7 D6 D5 D4 D3 D2 D1 D0

D80000000

Inverted

Not inverted

Error signal

output

circuit

TXD data

inversion

circuit

Error signal output enabled

Error signal output disabled

Inverted

Not inverted

Logic inversion circuit + MSB/LSB conversion circuit

IOPOL = 0

RXD data

inversion circuit

STPS = 0

2SP

PRYE = 0

SMD = 0

IOPOL = 0

I2C

Clock

synchronous

type

IOPOL = 1

SP STPS = 1 PRYE = 1

UART

(9 bits)

I2C

Clock

synchronous

type

U2ERE = 0

IOPOL = 1

STPS = 0

SMD = 1

R8C/34C Group 23. Serial Interface (UART2)

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 458 of 723

23.2 Registers

23.2.1 UART2 Transmit/Receive Mode Register (U2MR)

23.2.2 UART2 Bit Rate Register (U2BRG)

Write to the U2BRG register while transmission and reception stop.

Use the MOV instruction to write to this register.

Set bits CLK1 to CLK0 in the U2C0 register before writing to the U2BRG register.

Address 00A8h

Bitb7b6b5b4b3b2b1b0

Symbol IOPOL PRYE PRY STPS CKDIR SMD2 SMD1 SMD0

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 SMD0 Serial I/O mode select bit b2 b1 b0

0 0 0: Serial interf ace disabled

0 0 1: Clock synchronou s seria l I/O mode

0 1 0: I2C mode

1 0 0: UART mode, transfer data 7 bits long

1 0 1: UART mode, transfer data 8 bits long

1 1 0: UART mode, transfer data 9 bits long

Other than above: Do not set.

R/W

b1 SMD1 R/W

b2 SMD2 R/W

b3 CKDIR Internal/external clock select bit 0: Internal clock

1: External clock R/W

b4 STPS Stop bit length select bit 0: One stop bit

1: Two stop bits R/W

b5 PRY Odd/even parity select bit Enabled when PRYE = 1

0: Odd parity

1: Even parity

R/W

b6 PRYE Parity enable bit 0: Parity disabled

1: Parity enabled R/W

b7 IOPOL TXD, RXD I/O polarity switch bit 0: Not inverted

1: Inverted R/W

Address 00A9h

Bitb7b6b5b4b3b2b1b0

Symbol————————

After ResetXXXXXXXX

Bit Function Setting Range R/W

b7 to b0 If the setting value is n, U2BRG divides the count source by n+1. 00h to FFh W

R8C/34C Group 23. Serial Interface (UART2)

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 459 of 723

23.2.3 UART2 Transmit Buffer Register (U2TB)

Note:

1. Set bits b0 to b7 after setting the MPTB bit.

Address 00ABh to 00AAh

Bitb7b6b5b4b3b2b1 b0

Symbol——————— —

After ResetXXXXXXX X

Bit b15 b14 b13 b12 b11 b10 b9 b8

Symbol——————— MPTB

After ResetXXXXXXX X

Bit Symbol Function R/W

b0 — Transmit data (D7 to D0) W

b1 —

b2 —

b3 —

b4 —

b5 —

b6 —

b7 —

b8 MPTB Transmit data (D8) (1)

[When the multiprocessor communication function is not used]

Transmit data (D8)

[When the multiprocessor communication function is used]

• To transfer an ID, set the MPTB bit to 1.

• To transfer data, set the MPTB bit to 0.

b9 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b10 —

b11 —

b12 —

b13 —

b14 —

b15 —

R8C/34C Group 23. Serial Interface (UART2)

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 460 of 723

23.2.4 UART2 Transmit/Receive Control Register 0 (U2C0)

Notes:

1. If bits CLK1 to CLK0 are switch ed, set the U2BRG register again.

2. The UFORM bit is enabled when bits SMD 2 to SMD0 in the U2MR registe r are set to 001b (cl ock synchronous

serial I/O mode), or set to 101b (UART mode, transfer data 8 bits long).

Set the UFORM bit to 1 when bits SMD2 to SMD0 are set to 010b (I2C mode), and to 0 when bits SMD2 to SMD0

are set to 100b (UART mode, transfer data 7 bits long) or 110b (UART mode, transfer data 9 bits long).

Address 00ACh

Bitb7b6b5b4b3b2b1b0

Symbol UFORM CKPOL NCH CRD TXEPT CRS CLK1 CLK0

After Reset00001000

Bit Symbol Bit Name Function R/W

b0 CLK0 U2BRG count source

select bit (1)

b1 b0

0 0: f1 selected

0 1: f8 selected

1 0: f32 selected

1 1: fC selected

R/W

b1 CLK1 R/W

b2 CRS CTS/RTS function select bit Enabled when CRD = 0

0: CTS function selected

1: RTS function selected

R/W

b3 TXEPT Transmit register empty flag 0: Data present in the transmit register

(transmission in progress)

1: No data in the transmit register

(transmission completed)

b4 CRD CTS/RTS disable bit 0: CTS/RTS function enabled

1: CTS/RTS function disabled R/W

b5 NCH Data output select bit 0: Pins TXD2/SDA2, SCL2 set to CMOS output

1: Pins TXD2/SDA2, SCL2 set to N-channel open-drain

output

R/W

b6 CKPOL CLK polarity select bit 0: Transmit data output at the falling edge and receive

data input at the rising edge of the transfer clock

1: Transmit data output at th e rising edge and receive

data input at the falling edge of the transfer clock

R/W

b7 UFORM Transfer format select bit (2) 0: LSB first

1: MSB first R/W

R8C/34C Group 23. Serial Interface (UART2)

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 461 of 723

23.2.5 UART2 Transmit/Receive Control Register 1 (U2C1)

Note:

1. The U2LCH bit is enabled when bits SMD2 to SMD0 in the U2MR register are set to 001b (clock synchronous

serial I/O mode), 100b (UART mode, transfer data 7 bits long), or 101b (UART mode, transfer data 8 bits long).

Set the U2LCH bit to 0 when bits SMD2 to SMD0 are set to 010b (I2C mode) or 110b (UART mode, transfer data

9 bits long).

Address 00ADh

Bitb7b6b5b4b3b2b1b0

Symbol U2ERE U2LCH U2RRM U2IRS RI RE TI TE

After Reset00000010

Bit Symbol Bit Name Function R/W

b0 TE Transmit enable bit 0: Transmission disabled

1: Transmission enabled R/W

b1 TI Transmit buffer empty flag 0: Data present in the U2TB register

1: No data in the U2TB register R

b2 RE Receive enable bit 0: Reception disabled

1: Reception enabled R/W

b3 RI Receive complete flag 0: No data in the U2RB register

1: Data present in the U2RB register R

b4 U2IRS UART2 transmit interrupt source

select bit 0: Transmit buffer empty (TI = 1)

1: Transmission completed (TXEPT = 1) R/W

b5 U2RRM UART2 continuous receive mode

enable bit 0: Continuous receive mode disabled

1: Continuous receive mode enabled R/W

b6 U2LCH Data logic select bit (1) 0: Not inverted

1: Inverted R/W

b7 U2ERE Error signal output enable bit 0: Output disabled

1: Output enabled R/W

R8C/34C Group 23. Serial Interface (UART2)

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 462 of 723

23.2.6 UART2 Receive Buffer Register (U2RB)

Notes:

1. When bits SMD2 to SMD0 in the U2MR register are set to 000b (serial interface disabled) or the RE bit in the

U2C1 register is set to 0 (reception disabled), all of bits SUM, PER, FER, and OER are set to 0 (no error). The

SUM bit is set to 0 (no error) when all of bits PER, FER, and OER ar e set to 0 (no error). Bits PER and FER are

set to 0 by reading the lower byte of the U2RB register.

When setting bits SMD2 to SMD0 in the U2MR register to 000b, set the TE bit in the U2C1 register to 0

(transmission disabled) and the RE bit to 0 (reception disabled).

2. These error flags are disabled when bits SMD2 to SMD0 in the U2MR register are set to 001b (clock

synchronous serial I/O mode) or to 010b (I2C mode). When read, the content is undefined.

Address 00AFh to 00AEh

Bitb7b6b5b4b3b2b1 b0

Symbol——————— —

After ResetXXXXXXX X

Bit b15 b14 b13 b12 b11 b10 b9 b8

Symbol SUM PER FER OER — — — MPRB

After ResetXXXXXXX X

Bit Symbol Bit Name Function R/W

b0 — — Receive data (D7 to D0) R

b1 —

b2 —

b3 —

b4 —

b5 —

b6 —

b7 —

b8 MPRB — Receive data (D8) (1)

[When the multiprocessor communication function is

not used]

Receive da ta (D8)

[When the multiprocessor communication function is

used]

• When the MPRB bit is set to 0, received D0 to D7

are data fi el d s .

• When the MPRB bit is set to 1, received D0 to D7

are ID fields.

b9 — N othing is assigned. If necessary, set to 0. When read, the content is undefined. —

b10 —

b11 — Reserved bit Set to 0. R/W

b12 OER Overrun error flag (1) 0: No overrun error

1: Overrun error R

b13 FER Framing error flag (1, 2) 0: No framing error

1: Framing error R

b14 PER Parity error flag (1, 2) 0: No parity error

1: Parity error R

b15 SUM Error sum flag (1, 2) 0: No error

1: Error R

R8C/34C Group 23. Serial Interface (UART2)

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 463 of 723

23.2.7 UART2 Digital Filter Function Select Register (URXDF)

Note:

1. The RXD2 digital filter can be used only in clock asynchronous serial I/O (UART) mode. When bits SMD2 to

SMD0 in the U2MR register are set to 001b (clock synchronous serial I/O mode) or 010b (I2C mode), set the

DF2EN bit to 0 (RXD2 digital filter disabled).

23.2.8 UART2 Special Mode Register 5 (U2SMR5)

Note:

1. When the MP bit is set to 1 (multiprocessor communica tion enabled), the settings of bits PRY an d PRYE in the

U2MR register are disab led. If bits SMD2 to SMD0 in the U 2MR register are set to 001b (clock synchron ous

serial I/O mode), set the MP bit to 0 (multiprocessor communication disab led).

Address 00B0h

Bitb7b6b5b4b3b2b1b0

Symbol—————DF2EN——

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b1 —

b2 DF2EN RXD2 digital filter enable bit (1) 0: RXD2 digital filter disabled

1: RXD2 digital filter enabled R/W

b3 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b4 —

b5 —

b6 —

b7 —

Address 00BBh

Bitb7b6b5b4b3b2b1b0

Symbol — — — MPIE — — — MP

After Reset00000000

Bit Symbol Bit Name Function R/W

b0 MP Multiprocessor communication

enable bit 0: Multiprocessor communication disabled

1: Multiprocessor communication enabled (1) R/W

b1 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b2 —

b3 —

b4 MPIE Multiprocessor communication

control bit This bit is enabled when the MP bit is set to 1

(multiprocessor communication enab led).

When the MPIE bit is set to 1, the following will

result:

• Receive data in which the multiprocessor bit is 0

is ignored. Setting of the RI bit in the U2C1

• On recei v ing receive data in which the

multiprocessor bit is 1, the MPIE bit is set to 0 and

receive operation other than multiprocessor

communication is performed.

R/W

b5 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

b6 —

b7 — Reserved bit Set to 0. R/W

R8C/34C Group 23. Serial Interface (UART2)

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 464 of 723

23.2.9 UART2 Special Mode Register 4 (U2SMR4)

Note:

1. This bit is set to 0 when each condition is generated.

23.2.10 UART2 Special Mode Register 3 (U2SMR3)

Notes:

1. Bits DL2 to DL0 are used to ge nerate a delay in SDA2 output digitall y in I2C mode. In other than I2C mode, set

these bits to 000b (no delay).

2. The amount of delay varies w ith the load on pi ns SCL2 and SDA2 . When an externa l clock is used, the amoun t

of delay increases by about 100 ns.

Address 00BCh

Bitb7b6b5b4b3b2 b1 b0

Symbol SWC9 SCLHI ACKC ACKD STSPSEL STPREQ RSTAREQ STAREQ

After Reset000000 0 0

Bit Symbol Bit Name Function R/W

b0 STAREQ Start condition generate bit (1) 0: Clear

1: Start R/W

b1 RSTAREQ Restart condition generate bit (1) 0: Clear

1: Start R/W

b2 STPREQ Stop condition generate bit (1) 0: Clear

1: Start R/W

b3 STSPSEL SCL, SDA output select bit 0: Start and stop conditions not output

1: Start and stop conditions output R/W

b4 ACKD ACK data bit 0: ACK

1: NACK R/W

b5 ACKC ACK data output enable bit 0: Serial interface data output

1: ACK data output R/W

b6 SCLHI SCL output stop enable bit 0: Disabled

1: Enabled R/W

b7 SWC9 SCL wait bit 3 0: SCL “L” hold disabled

1: SCL “L” hold enabled R/W

Address 00BDh

Bitb7b6b5b4b3b2b1b0

Symbol DL2 DL1 DL0 — NODC — CKPH —

After Reset000X0X0X

Bit Symbol Bit Name Function R/W

b0 — Nothing is assigned. If necessary, set to 0. When read, the content is undefined. —

b1 CKPH Clock phase set bit 0: No clock delay

1: With clock delay R/W

b2 — Nothing is assigned. If necessary, set to 0. When read, the content is undefined. —

b3 NODC Clock output select bit 0: CLK2 set to CMOS output

1: CLK2 set to N-channel open-drain output R/W

b4 — Nothing is assigned. If necessary, set to 0. When read, the content is undefined. —

b5 DL0 SDA2 digital delay setup bi t (1, 2) b7 b6 b5

0 0 0: No delay

0 0 1: 1 to 2 cycle(s) of U2BRG count source

0 1 0: 2 to 3 cycles of U2BRG count source

0 1 1: 3 to 4 cycles of U2BRG count source

1 0 0: 4 to 5 cycles of U2BRG count source

1 0 1: 5 to 6 cycles of U2BRG count source

1 1 0: 6 to 7 cycles of U2BRG count source

1 1 1: 7 to 8 cycles of U2BRG count source

R/W

b6 DL1 R/W

b7 DL2 R/W

R8C/34C Group 23. Serial Interface (UART2)

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 465 of 723

23.2.11 UART2 Special Mode Register 2 (U2SMR2)

23.2.12 UART2 Special Mode Register (U2SMR)

Note:

1. The BBS bit is set to 0 by writing 0 by a program (Writing 1 has no effect).

Address 00BEh

Bitb7b6b5b4b3b2b1b0

Symbol — SDHI SWC2 STAC — SWC CSC IICM2

After Reset X0000000

Bit Symbol Bit Name Function R/W

b0 IICM2 I2C mode select bit 2 Refer to Table 23.12 I2C Mode Functions.R/W

b1 CSC Clock synchronization bit 0: Disabled

1: Enabled R/W

b2 SWC SCL wait output bit 0: Disab led

1: Enabled R/W

b3 — Reserved bit Set to 0. R/W

b4 STAC UART2 initialization bit 0: Disabled

1: Enabled R/W

b5 SWC2 SCL wait output bit 2 0: Transfer clock

1: “L” output R/W

b6 SDHI SDA output disable bit 0: Enabled

1: Disabled (high-impedance) R/W

b7 — Nothing is assigned. If necessary, set to 0. When read, the content is undefined. —

Address 00BFh

Bitb7b6b5b4b3b2b1b0

Symbol—————BBS—IICM

After Reset X0000000

Bit Symbol Bit Name Function R/W

b0 IICM I2C mode select bit 0: Other than I2C mode

1: I2C mode R/W

b1 — Reserved bit Set to 0. R/W

b2 BBS Bus busy flag (1) 0: Stop condition detected

1: Start condition detected (busy) R/W

b3 — Reserved bits Set to 0. R/W

b4 —

b5 —

b6 —

b7 — Nothing is assigned. If necessary, set to 0. When read, the content is undefined. —

R8C/34C Group 23. Serial Interface (UART2)

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 466 of 723

23.2.13 UART2 Pin Select Register 0 (U2SR0)

The U2SR0 register selects wh ich pin is assigned to the UART2 I/O. To use the I/O pin fo r UART2, set this

Set the U2SR0 register before setting the UART2 associated registers. Also, do not change the setting value in

this register during UART2 operation.

23.2.14 UART2 Pin Select Register 1 (U2SR1)

The U2SR1 register selects wh ich pin is assigned to the UART2 I/O. To use the I/O pin fo r UART2, set this

Set the U2SR1 register before setting the UART2 associated registers. Also, do not change the setting value in

this register during UART2 operation.

Address 018Ah

Bitb7b6b5 b4b3b2 b1 b0

Symbol — — RXD2SEL1 RXD2SEL0 — TXD2SEL2 TXD2SEL1 TXD2SEL0

After Reset000 000 0 0

Bit Symbol Bit Name Function R/W

b0 TXD2SEL0 TXD2/SDA2 pin select bit b2 b1 b0

0 0 0: TXD2/SDA2 pin not used

0 0 1: P3_7 assigned

0 1 0: P3_4 assigned

0 1 1: Do not set.

1 0 0: Do not set.

1 0 1: P6_6 assigned

1 1 0: Do not set.

1 1 1: Do not set.

R/W

b1 TXD2SEL1 R/W

b2 TXD2SEL2 R/W

b3 — N othing is assigned. If necessary, set to 0. When read, the content is 0. —

b4 RXD2SEL0 RXD2/SCL2 pin select bit b5 b4

0 0: RXD2/SCL2 pin not used

0 1: P3_4 assigned

1 0: P3_7 assigned

1 1: P4_5 assigned

R/W

b5 RXD2SEL1 R/W

b6 — Reserved bit Set to 0. R/W

b7 — N othing is assigned. If necessary, set to 0. When read, the content is 0. —

Address 018Bh

Bitb7b6b5 b4 b3b2 b1 b0

Symbol — — — CTS2SEL0 — — CLK2SEL1 CLK2SEL0

After Reset000 0 00 0 0

Bit Symbol Bit Name Function R/W

b0 CLK2SEL0 CLK2 pin select bit b1 b0

0 0: CLK2 pin not used

0 1: P3_5 assigned

1 0: Do not set.

1 1: P6_5 assigned

R/W

b1 CLK2SEL1 R/W

b2 — N othing is assigned. If necessary, set to 0. When read, the content is 0. —

b3 —

b4 CTS2SEL0 CTS2/RTS2 pin select bit 0: CTS2/RTS2 pin not used

1: P3_3 assigned R/W

b5 — Reserved bit Set to 0. R/W

b6 — N othing is assigned. If necessary, set to 0. When read, the content is 0. —

b7 —

R8C/34C Group 23. Serial Interface (UART2)

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 467 of 723

23.3 Clock Synchronous Serial I/O Mode

In clock synchronous serial I/O mode, data is transmitted and received using a transfer clock.

Table 23.2 lists the Clock Synchronous Serial I/O Mode Specifications. Table 23.3 lists the Registers Used and

Settings in Clock Synchronous Serial I/O Mode.

Notes:

1. When an external clock is selected, the requirements must be met in either of the following states:

- The external clock is held high when the CKPOL bit in the U2C0 register is set to 0 (transmit data output

at the falling edge and receive data input at the rising edge of the transfer clock)

- The external clock is held low when the CKPOL bit in the U2C0 register is set to 1 (transmit data out put

at the rising edge and receive data input at the falling edge of the transfer clock)

2. If an overrun error occurs, the receive data in the U2RB register will be undefined. The IR bit in the S2RIC

Table 23.2 Clock Synchronous Serial I/O Mode Specifications

Item Specification

Transfer data format Transfer data length: 8 bits

Transfer clock • The CKDIR bit in th e U2MR register is set to 0 (internal clock): fj/(2(n+1))

fj = f1, f8, f32, fC n = setting value in the U2BRG register: 00h to FFh

• The CKDIR bit is set to 1 (external clock): Input from the CLK2 pin

Transmit/receive control Selectable fro m the CTS function, RTS function, or CTS/RTS function disable d.

Transmit start conditions To start transmission, the following requirements must be met: (1)

• The TE bi t in the U2C1 register is set to 1 (transmission enabled)

• The TI bit in the U2C1 register is set to 0 (data present in the U2TB register)

• If the CTS function is selected, input to the CTS2 pin = “L”.

Receive start conditions To start reception, the following requirements must be met: (1)

• The RE bit in the U2C1 register is set to 1 (reception enabled).

• The TE bi t in the U2C1 register is set to 1 (transmission enabled).

• The TI bit in the U2C1 register is set to 0 (data present in the U2TB register).

Interrupt req uest generation

timing For transmission , one of the following conditions can be selected.

• The U2IRS bit in the U2C1 register is set to 0 (transmit buffer empty):

When data is transferred from the U2TB register to the UART2 transmit register

(at start of transmission).

• The U2IRS bit is set to 1 (transmission completed):

When data transmission from the UART2 transmit register is completed.

For reception

• When data is transferred from the UART2 receive register to the U2RB register

(at completion of reception).

Error detection Overrun error (2)

This error occurs if the serial interface starts receiving the next unit of data before

reading the U2RB register and receives the 7th bit of the next unit of data.

Selectable functions • CLK polarity selection

Transfer data I/O can be selected to occu r synchronously with the rising or falling

edge of the transfer clock.

• LSB first, MSB first selection

Whether transmitting or receivin g data begins with bit 0 or begins with bit 7 can be

selected.

• Continuo us receive mode selection

Reception is enabled immed i at el y by reading the U2RB reg i ster.

• Serial data logic switching

This function inverts the logic value of the transmit/receive data.

R8C/34C Group 23. Serial Interface (UART2)

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 468 of 723

Note:

1. Set the bits not listed in this table to 0 when writing to the above registers in clock synchronous

serial I/O mode.

Table 23.3 Registers Used and Settings in Clock Synchronous Serial I/O Mode

U2TB (1) b0 to b7 Set transmit data.

U2RB (1) b0 to b7 Receive data can be read.

OER Overrun error flag

U2BRG b0 to b7 Set a bit rate.

U2MR (1) SMD2 to SMD0 Set to 001b.

CKDIR Select the internal clock or external clock.

IOPOL Set to 0.

U2C0 CLK1, CLK0 Select the count source for the U2BRG register.

CRS Select either CTS or RTS to use fu nctions.

TXEPT Transmit register empty flag

CRD Enable or disable the CTS or RTS function.

NCH Select TXD2 pin output mode.

CKPOL Select the transfer clock polarity.

UFORM Select LSB first or MSB first.

U2C1 TE Set to 1 to enable transmission/reception.

TI Transmit buffer empty flag

RE Set to 1 to enable reception.

RI Receive complete flag

U2IRS Select the source of UART2 transmit interrupt.

U2RRM Set to 1 to use continuous receive mode.

U2LCH Set to 1 to use inverted data logic.

U2ERE Set to 0.

U2SMR b0 to b7 Set to 0.

U2SMR2 b0 to b7 Set to 0.

U2SMR3 b0 to b2 Set to 0.

NODC Select clock output mode.

b4 to b7 Set to 0.

U2SMR4 b0 to b7 Set to 0.

URXDF DF2EN Set to 0.

U2SMR5 MP Set to 0.

R8C/34C Group 23. Serial Interface (UART2)

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 469 of 723

Table 23.4 lists the Pin Fun ctions in Clock Synchronous Serial I/O Mode (Multiple Transfer Clock Output Pin

Function Not Selected).

Note that for a period from wh en UART2 operating mode is selected to when transfer starts, the TXD2 pin outputs

a “H” level. (When N-channel open-drain output is selected, this pin is in the high-impedance state.)

Figure 23.3 shows the Transmit and Receive Timing in Clock Synchronous Serial I/O Mode.

Table 23.4 Pin Functions in Clock Synch ronous Se rial I/O Mode (Multiple Tr ansfer Clo ck Output

Pin Function Not Selected)

Pin Name Function Selection Method

TXD2

(P3_4, P3_7, or

P6_6)

Serial data output • TXD2 (P3_4)

Bits TXD2SEL2 to TXD2SEL0 in U2SR0 r egister = 010b (P3_4)

• TXD2 (P3_7)

Bits TXD2SEL2 to TXD2SEL0 in U2SR0 r egister = 001b (P3_7)

• TXD2 (P6_6)

Bits TXD2SEL2 to TXD2SEL0 in U2SR0 r egister = 101b (P6_6)

• For reception only:

P3_4, P3_7 and P6_6 can be used as ports by setting

TXD2SEL2 to TXD2SEL0 to 000b.

RXD2

(P3_4, P3_7, or

P4_5)

Serial data input • RXD2 (P3_4)

Bits RXD2SEL1 to RXD2SEL0 in U2SR0 register = 01b (P3_4)

PD3_4 bit in PD3 register = 0

• RXD2 (P3_7)

Bits RXD2SEL1 to RXD2SEL0 in U2SR0 register = 10b (P3_7)

PD3_7 bit in PD3 register = 0

• RXD2 (P4_5)

Bits RXD2SEL1 to RXD2SEL0 in U2SR0 register = 11b (P4_5)

PD4_5 bit in PD4 register = 0

• For transmission only:

P3_4, P3_7, and P4_5 can be used as ports by setting

RXD2SEL1 to RXD2SEL0 to 00b.

CLK2

(P3_5 or P6_5) Transfer clock output • CLK2 (P3_5)

Bits CLK2SEL1 to CLK2SEL0 in U2SR1 register = 01b (P3_5)

CKDIR bit in U2MR register = 0

• CLK2 (P6_5)

Bits CLK2SEL1 to CLK2SEL0 in U2SR1 register = 11b (P6_5)

CKDIR bit in U2MR register = 0

Transfer clock input • CLK2 (P3_5)

Bits CLK2SEL1 to CLK2SEL0 in U2SR1 register = 01b (P3_5)

CKDIR bit in U2MR register = 1

PD3_5 bit in PD3 register = 0

• CLK2 (P6_5)

Bits CLK2SEL1 to CLK2SEL0 in U2SR1 register = 11b (P6_5)

CKDIR bit in U2MR register = 1

PD6_5 bit in PD6 register = 0

CTS2/RTS2

(P3_3) CTS input CTS2SEL 0 bit in U2SR1 register = 1

CRD bit in U2C0 register = 0

CRS bit in U2C0 register = 0

PD3_3 bit in PD3 register = 0

RTS output CT S2 SEL 0 bit in U2SR1 register = 1

CRD bit in U2C0 register = 0

CRS bit in U2C0 register = 1

I/O port CTS2SEL0 bit in U2SR1 register = 0

R8C/34C Group 23. Serial Interface (UART2)

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 470 of 723

Figure 23.3 Transmit and Receive Timing in Clock Synchronous Serial I/O Mode

D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7

TCLK Pulsing stops because TE bit is set to 0.

Data is set in U2TB register.

Data transfer from U2TB register to UART2 transmit register

TC = TCLK = 2(n+1)/fj

fj: Frequency of U2BRG count source

(f1, f8, f32, fC)

n: Setting value in U2BRG register

Transfer clock

TE bit in

U2C1 register

TI bit in

U2C1 register

CLK2

TXD2

TXEPT flag in

U2C0 register

CTS2

IR bit in

S2TIC register

Set to 0 when an interrupt request is acknowledged or by a program.

Pulsing stops because “H” is applied

to CTS2.

1/fEXT

Dummy data is set in U2TB register.

CLK2

RXD2

RTS2

RE bit in

U2C1 register

Data transfer from U2TB register to UART2 transmit register

Data read from U2RB register

fEXT: Frequency of external clock

Make sure the following conditions are met

when the CLK2 pin input before receiving data is high:

•TE bit in U2C0 register = 1 (transmission enabled)

•RE bit in U2C1 register = 1 (reception enabled)

•Dummy data is written to U2TB register

Data transfer from UART2 receive

Set to 0 when an interrupt request is acknowledged or by a program.

D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D0 D1 D2 D3 D4 D5

D6 D6

TE bit in

U2C1 register

TI bit in

U2C1 register

OER flag in

U2RB register

IR bit in

S2RIC register

RI bit in

U2C1 register

The above applies when:

•CKDIR bit in U2MR register = 0 (internal clock)

•CRD bit in U2C0 register = 0 (CTS/RTS function enabled), CRS bit = 0 (CTS function selected)

•CKPOL bit in U2C0 register = 0 (transmit data output at the falling edge and

receive data input at the rising edge of the transfer clock)

•U2IRS bit in U2C1 register = 0 (interrupt request generation when the U2TB register is empty)

The above applies when:

•CKDIR bit in U2MR register = 1 (external clock)

•CRD bit in U2C0 register = 0 (CTS/RTS function enabled), CRS bit = 1 (RTS function selected)

•CKPOL bit in U2C0 register = 0 (transmit data output at the falling edge and

receive data input at the rising edge of the transfer clock)

Received data taken in

“L” is applied when U2RB register is read.

(1) Transmit Timing Example (Internal Clock Selected)

(2) Receive Timing Example (External Clock Selected)

R8C/34C Group 23. Serial Interface (UART2)

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 471 of 723

23.3.1 Measure for Dealing with Communication Errors

If communication is aborted or a communication error occurs while transmitting or receiving in clock

synchronous serial I/O mode, follo w the procedures below:

(1) Set the TE bit in the U2C1 register to 0 (transmission disabled) and the RE bit to 0 (reception disabled).

(2) Set bits SMD2 to SMD0 in the U2MR register to 000b (s erial interface disabled).

(3) Set bits SMD2 to SMD0 in the U2MR register to 001b (clock synchronous serial I/O mode).

(4) Set the TE bit in the U2C1 register to 1 (transmission enabled) and the RE bit to 1 (reception enabled).

23.3.2 CLK Polarity Select Function

Use the CKPOL bit in the U2C0 register to select the transfer clock po larity. Figure 23.4 shows the Transfer

Clock Polarity.

Figure 23.4 Transfer Clock Polarity

(2)CKPOL bit in U2C0 register = 1 (transmit data output at the rising edge and

receive data input at th e falling edge of the transfer clock)

D1 D2 D3 D4 D5 D6 D7

TXD2

RXD2

CLK2

(1)CKPOL bit in U2C0 register = 0 (transmit data output at the falling edge and

receive data input at the rising edge of the transfer clock)

D1 D2 D3 D4 D5 D6 D7D0

TXD2

RXD2

CLK2

The above applies when:

•UFORM bit in U2C0 register = 0 (LSB first)

•U2LCH bit in U2C1 register = 0 (not inverted)

“H” output from CLK2 pin

during no transfer

“L” output from CLK2 pin

during no transfer

R8C/34C Group 23. Serial Interface (UART2)

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 472 of 723

23.3.3 LSB First/MSB First Select Function

Use the UFORM bit in the U2C0 register to select the transfer format. Figure 23.5 shows the Transfer Format.

Figure 23.5 Transfer Format

23.3.4 Continuous Receive Mode

In continuous receive mode, receive operation is enabled when the receive buffer register is read. It is not

necessary to write dummy data to the transmit buffer register to enable receive operation in this mode.

However, a dummy read of the receive buffer register is required when starting the operating mode.

When the U2RRM bit in the U2C1 register is set to 1 (continuous receive mode), the TI bit in the U2C1 register

is set to 0 (data present in the U2TB register) by reading the U2RB register. If the U2RRM bit is set to 1, do not

write dummy data to the U2TB register by a program.

(1) UFORM Bit in U2C0 Register = 0 (LSB first)

D1 D2 D3 D4 D5 D6 D7D0

TXD2

RXD2

CLK2

(2) UFORM Bit in U2C0 Register = 1 (MSB first)

D6 D5 D4 D3 D2 D1 D0D7

TXD2

RXD2

CLK2

The above applies when:

•CKPOL bit in U2C0 register = 0

(transmit data output at the falling edge and receive da ta input

at the rising edge of the transfer clock)

•U2LCH bit in U2C1 register = 0 (not inverted)

R8C/34C Group 23. Serial Interface (UART2)

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 473 of 723

23.3.5 Serial Data Logic Switching Function

If the U2LCH bit in the U2C1 register is set to 1 (inverted), the data written to the U2TB register has its logic

inverted before being transmitted. Similarly, the received data has its logic inverted when read from the U2RB

Figure 23.6 Serial Data Logic Switching

23.3.6 CTS/RTS Function

The CTS function is used to start transmit and receive operation when “L” is applied to the CTS2/RTS2 pin.

Transmit and receive operation begins when the CTS2/RTS2 pin is held lo w. If the “L” signal is switc hed to

“H” during a transmit or receive operation, the operation stops before the next data.

For the RTS function, the CTS2/RTS2 pin outputs “L” when the MCU is ready for a receive operation. The

output level goes high at the first falling edge of the CLK2 pin.

• The CRD bit in the U2C0 register = 1 (CTS/RTS function disabled)

The CTS2/RTS2 pin operates as the programmable I/O function.

• The CRD bit = 0, CRS bit = 0 (CTS function selected)

The CTS2/RTS2 pin operates as the CTS function.

• The CRD bit = 0, CRS bit = 1 (RTS function selected)

The CTS2/RTS2 pin operates as the RTS function.

D0 D1 D2 D3 D4 D5 D6 D7

Transfer Clock

TXD2

(not inve rted)

(1) U2LC H Bit in U2C 1 R egister = 0 (not inverted)

(2) U2LC H Bit in U2C 1 R egister = 1 (inverted)

The above applies when:

•C KP OL b it in U2C0 r e g is te r = 0 (tr a ns mit d a ta ou tp ut a t th e fallin g ed g e o f th e tra ns fe r c lo c k )

•U F OR M b it in U2C0 r e g is te r = 0 (LS B firs t)

D0 D1 D2 D3 D4 D5 D6 D7

Transfer Clock

TXD2

(inverted)

R8C/34C Group 23. Serial Interface (UART2)

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 474 of 723

23.4 Clock Asynchronous Serial I/O (UART) Mode

In UART mode, da ta is transmitted and received after setting the desired bit rate an d transfer data format. Tab le

23.5 lists the UART Mode Specifications. Table 23.6 lists the Registers Used and Settings in UART Mode.

Notes:

1. If an overrun error occurs, the receive data in the U2RB register will be undefined. The IR bit in the S2RIC

2. The framing error flag and the parity error flag are set to 1 when data is transferred from the UART2 receive

Table 23.5 UART Mode Specifications

Item Specification

Transfer data format • Character bits (transfer data): Selectable from 7, 8, or 9 bits

• Start bit:1 bit

• Parity bit: Selectable from odd, even, or none

• Stop bits: Selectable from 1 bit or 2 bits

Transfer clock • The CKDIR bit in the U2MR register is set to 0 (internal clock): fj/(16(n + 1))

fj = f1, f8, f32, fC n = setting value in the U2BRG register: 00h to FFh

• The CKDIR bit is set to 1 (external clock): fEXT/(16(n + 1))

fEXT: Input from CLK2 pin n: Setting value in the U2BRG register: 00h to FFh

Transmit/receive control Selectable from the CTS function, RTS function , or CTS/RTS functi on disabled.

Transmit start conditions To start transmission, the following requirements must be met:

• The TE bit in the U2C1 register is set to 1 (transmission enabled).

• The TI bit in the U2C1 register is set to 0 (data present in the U2TB register).

• If the CTS function is selected, inpu t to the CTS2 pin = “L”.

Receive start conditions To start reception, the following requirements must be met:

• The RE bit in the U2C1 register is set to 1 (reception enabled).

• Start bit detection

Interrupt req uest generation

timing For transmission, one of the following conditions can be selected.

• The U2IRS bit in the U2C1 register is set to 0 (transmit buffer empty):

When data is transferred from the U2TB register to the UART2 transmit register

(at start of transmission).

• The U2IRS bit is set to 1 (transmission completed):

When data transmission fro m the UART2 transmit register is completed.

For reception

• When data is transferred from the UART2 receive register to the U2RB register

(at completion of reception).

Error detection • Overrun error (1)

This error occurs if the serial interface starts receiving the next unit of data before

reading the U2RB register and receives the bit one before the last stop bit of the

next unit of da ta.

• Framing error (2)

This error occurs when the set number of stop bits is not detected.

• Parity error (2)

This error occurs when if pari ty is enabled, the number of 1’s in the parity and

character bits does not match the set number of 1’s.

• Error sum flag

This flag is set to 1 if an overrun, framing, or parity error occurs.

Selectable functions • LSB first, MSB first selection

Whether transmitting or receiving data begins with bit 0 or begins with bit 7 can be

selected.

• Serial data logic switching

This function inverts the logic of the tr ansmit/receive data. The start and stop bits

are not inverted.

• TXD, RXD I/O polarity switching

This function inve rts the polarities of the TXD pin output and RXD pin input. The

logic levels of all I/O data are inverted.

• RXD2 digital filter selection

The RXD2 input signal can be enabled or disabled.

R8C/34C Group 23. Serial Interface (UART2)

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 475 of 723

Notes:

1. The bits used for transmit/receive data are as follows:

- Bits b0 to b6 when transfe r da ta is 7 bits long

- Bits b0 to b7 when tra nsfe r da ta is 8 bit s long

- Bits b0 to b8 when tra nsfe r da ta is 9 bit s long

2. The contents of the following are undefined:

- Bits b7 and b8 when transfer data is 7 bits long

- Bit b8 when transfer data is 8 bits long

Table 23.6 Registers Used and Settings in UART Mode

U2TB b0 to b8 Set transmit data. (1)

U2RB b0 to b8 Receive data can be read. (1, 2)

OER, FER, PER, SUM Error flag

U2BRG b0 to b7 Set a bit rate.

U2MR SMD2 to SMD0 Set to 100b when transfer data is 7 bits long.

Set to 101b when transfer data is 8 bits long.

Set to 110b when transfer data is 9 bits long.

CKDIR Select the internal clock or external clock.

STPS Select the stop bit.

PRY, PRYE Select whether parity is included and whether odd or even.

IOPOL Select the TXD/RXD I/O polarity.

U2C0 CLK0, CLK1 Select the count source for the U2BRG register.

CRS Select CTS or RTS to use funct i on s.

TXEPT Trans mit register empty flag

CRD Enable or disable the CTS or RTS function.

NCH Select TXD2 pin output mode.

CKPOL Set to 0.

UFORM Select LSB first or MSB first when transfer data is 8 bits long.

Set to 0 when transfer data is 7 or 9 bits long.

U2C1 TE Set to 1 to enable transmission.

TI Transm it buffer empty flag

RE Set to 1 to enable reception.

RI Receive complete flag

U2IRS Select the UART2 transmit interrupt so urce.

U2RRM Set to 0.

U2LCH Set to 1 to use inverted data logic.

U2ERE Set to 0.

U2SMR b0 to b7 Set to 0.

U2SMR2 b0 to b7 Set to 0.

U2SMR3 b0 to b7 Set to 0.

U2SMR4 b0 to b7 Set to 0.

URXDF DF2EN Select the digital filter disabled or enabled.

U2SMR5 MP Set to 0.

R8C/34C Group 23. Serial Interface (UART2)

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 476 of 723

Table 23.7 lists the I/O Pin Functions in UART Mode.

Note that for a period from when the UART2 operating mode is selected to when transfer starts, the TXD2 pin

outputs “H”. (When N-channel open-drain output is selected, this pin is in the high-impedance state.)

Figure 23.7 shows the Transmit Timing in UART Mode. Figure 23.8 shows the Receive Timing in UART Mode.

Table 23.7 I/O Pin Functions in UART Mode

Pin Name Function Selection Method

TXD2

(P3_4, P3_7,

or P6_6)

Serial data output • TXD2 (P3_4)

Bits TXD2SEL2 to TXD2SEL0 in U2SR0 register = 010b (P3_4)

• TXD2 (P3 _7)

Bits TXD2SEL2 to TXD2SEL0 in U2SR0 register = 001b (P3_7)

• TXD2 (P6 _6)

Bits TXD2SEL2 to TXD2SEL0 in U2SR0 register = 101b (P6_6)

• For reception only:

P3_4, P3_7, and P6_6 can be used as ports by setting

TXD2SEL2 to TXD2SEL0 to 000b.

RXD2

(P3_4, P3_7,

or P4_5)

Serial data input • RXD2 (P3_4)

Bits RXD2SEL1 to RXD2SEL0 in U2SR0 register = 01b (P3_4)

PD3_4 bit in PD3 register =0

• RXD2 (P3_7)

Bits RXD2SEL1 to RXD2SEL0 in U2SR0 register = 10b (P3_7)

PD3_7 bit in PD3 register = 0

• RXD2 (P4_5)

Bits RXD2SEL1 to RXD2SEL0 in U2SR0 register = 11b (P4_5)

PD4_5 bit in PD4 register = 0

• For transmission only:

P3_4, P3_7, and P4_5 can be used as ports by setting

RXD2SEL1 to RXD2SEL0 to 00b.

CLK2

(P3_5 or P6_5) I/O port Bits CLK2SEL1 to CLK2SEL0 in U2SR1 register = 00b

Transfer clock input •CLK2 (P3_5)

Bits CLK2SEL1 to CLK2SEL0 in U2SR1 register = 01b (P3_5)

CKDIR bit in U2MR register = 1

PD3_5 bit in PD3 register = 0

• CLK2 (P6_5)

Bits CLK2SEL1 to CLK2SEL0 in U2SR1 register = 11b (P6_5)

CKDIR bit in U2MR register = 1

PD6_5 bit in PD6 register = 0

CTS2/RTS2

(P3_3) CTS input CTS2SEL0 bit in U2SR1 register = 1

CRD bit in U2C0 register = 0

CRS bit in U2C0 register = 0

PD3_3 bit in PD3 register = 0

RTS output CTS2SEL0 bit in U2SR1 register = 1

CRD bit in U2C0 register = 0

CRS bit in U2C0 register = 1

I/O port CTS2SEL0 bit in U2SR1 register = 0

R8C/34C Group 23. Serial Interface (UART2)

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 477 of 723

Figure 23.7 Transmit Timing in UART Mode

D0 D1 D2 D3 D4 D5 D6 D7

ST P

Parity

bit

TXD2

CTS2

The above applies when:

•PRYE bit in U2MR register = 1 (parity enabled )

•STPS bit in U2MR register = 0 (one stop bit)

•CRD bit in U2C0 register = 0 (C TS /RTS fun ction enab led), CRS b it = 0 (CT S function sele cted)

•U2IRS bit in U2C1 register = 1 (interrupt request gene ration whe n transmission is completed )

TC = 16(n + 1)/fj or 16(n + 1)/fEXT

fj: Frequency of U2BRG count source (f1, f8, f32, fC)

fEXT: Frequency of U2BRG count source (e xternal clock)

n: Sett ing valu e in U2BR G

Set to 0 when an interrupt request is acknowledged or by a program.

D0 D1 D2 D3 D4 D5 D6 D7

ST PD0 D1

TXD2

The above applies when:

•PRYE bit in U2MR register = 0 (parity disabled)

•STPS bit in U2MR register = 1 (two stop bits)

•CRD bit in U2C0 register = 1 (C TS /RT S function disabled)

•U2IRS bit in U2C1 register = 0 (interrupt r eq uest ge nera tion when the tra nsm it buffer is em pty)

Transfer clock

Set to 0 when an interrupt request is acknowledged or by a program.

Transfer clock

Stop

bit

Data is set in U2TB register.

Start bit

D0 D1 D2 D3 D4 D5 D6 D7ST D8 D0 D1 D2 D3 D4 D5 D6 D7ST D8 D0 D1

SP SP

Stop

bit

The transfer clock stops once because “H” is applied to CTS pin when the stop bit is verified.

The transfer clock resumes running immediately after “L” is applied to CTS pin.

Data is set in U2TB register.

Data transfer from U2TB register

to UART2 transmit register

Stop

bit

TE bit in

U2C1 register

TI bit in

U2C1 register

TXEPT bit in

U2C0 register

IR bit in

S2TIC register

TE bit in

U2C1 register

TI bit in

U2C1 register

TXEPT bit in

U2C0 register

IR bit in

S2TIC register

Pulsing stops because TE bit is set to 0.

Start bit

TC = 16(n + 1)/fj or 16(n + 1)/fEXT

fj: Frequency of U2BRG count source (f1, f8, f32, fC)

fEXT: Frequency of U2BRG count source (external clock)

n: Setting value in U2BRG

(1) Transmit Timing Example When Transfer Data 8 Bits is Long (Parity Enabled, One Stop Bit)

(2) Transmit Timing Example When Transfer Data 9 Bits is Long (Parity Disabled, Two Stop Bits)

Data transfer from U2TB register

to UART2 transmit register

R8C/34C Group 23. Serial Interface (UART2)

REJ09B0586-0100 Rev.1.00 Jan 13, 2010

Page 478 of 723

Figure 23.8 Receive Timing in UART Mode

23.4.1 Bit Rate

In UART mode, the bit rate is the frequency divided by the U2BR G register divided by 16. Tab le 23.8 lists the

Bit Rate Setting Example in UART Mode (Internal Clock Selected).

Note:

1. For the high-speed on-chip oscillator, the correction value in the FRA4 register should be written into the FRA1

This applies when the high-speed on-chip oscillator is selected as the system clock and bits FRA22 to FRA20

in the FRA2 register are set to 000b (divide-by-2 mode). For the precision of the high-speed on-chi p oscillator,

refer to 33. Electrical Characteristics.

Table 23.8 Bit Rate Setting Example in UART Mode (Internal Clock Selected)

Bit Rate

(bps)

U2BRG

Count

Source

System Clock = 20 MHz System Clock = 18.4 32 MHz (1) System Clock = 8 MHz