StrongIRFET™
IRFS7430-7PPbF
1 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback November 6, 2014
HEXFET® Power MOSFET
D
S
G
G D S
Gate Drain Source
Application
Brushed Motor drive applications
BLDC Motor drive applications
PWM Inverterized topologies
Battery powered circuits
Half-bridge and full-bridge topologies
Electronic ballast applications
Synchronous rectifier applications
Resonant mode power supplies
OR-ing and redundant power switches
DC/DC and AC/DC converters
Benefits
Improved Gate, Avalanche and Dynamic dV/dt Ruggedness
Fully Characterized Capacitance and Avalanche SOA
Enhanced body diode dV/dt and dI/dt Capability
Lead-Free, RoHS Compliant
Base part number Package Type Standard Pack Orderable Part Number
Form Quantity
IRFS7430-7PPbF Tube 50 IRFS7430-7PPbF
Tape and Reel Left 800 IRFS7430TRL7PP
D2Pak-7Pin
VDSS 40V
RDS(on) typ. 0.55m
max 0.75m
ID (Silicon Limited) 522A
ID (Package Limited) 240A
Fig 1. Typical On-Resistance vs. Gate Voltage Fig 2. Maximum Drain Current vs. Case Temperature
46810 12 14 16 18 20
VGS, Gate -to -Source Voltage (V)
0.0
1.0
2.0
3.0
4.0
RDS(on)
, Drain-to -Source On Resistance (m
)
ID = 100A
TJ = 25°C
TJ = 125°C
25 50 75 100 125 150 175
TC , Case Temperature (°C)
0
100
200
300
400
500
600
ID, Drain Current (A)
Limited By Package
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Absolute Maximium Rating
Symbol Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Silicon Limited) 522
A
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V (Silicon Limited) 369
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Wire Bond Limited) 240
IDM Pulsed Drain Current 1200*
PD @TC = 25°C Maximum Power Dissipation 375 W
Linear Derating Factor 2.5 W/°C
VGS Gate-to-Source Voltage ± 20 V
TJ
TSTG
Operating Junction and
Storage Temperature Range -55 to + 175°C
Soldering Temperature, for 10 seconds (1.6mm from case) 300
Avalanche Characteristics
EAS (Thermally limited) Single Pulse Avalanche Energy 764mJ
EAS (Thermally limited) Single Pulse Avalanche Energy 1454
IAR Avalanche Current See Fig 15, 16, 23a, 23b A
EAR Repetitive Avalanche Energy mJ
Thermal Resistance
Symbol Parameter Typ. Max. Units
RJC Junction-to-Case ––– 0.4
RJA Junction-to-Ambient ––– 40
°C/W
Static @ TJ = 25°C (unless otherwise specified)
Symbol Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage 40 ––– ––– V VGS = 0V, ID = 250µA
V(BR)DSS/TJ Breakdown Voltage Temp. Coefficient ––– 26 ––– mV/°C Reference to 25°C, ID = 2mA
RDS(on) Static Drain-to-Source On-Resistance ––– 0.55 0.75 VGS = 10V, ID = 100A
––– 0.93 ––– VGS = 6V, ID = 50A
VGS(th) Gate Threshold Voltage 2.2 3.0 3.9 V VDS = VGS, ID = 250µA
IDSS Drain-to-Source Leakage Current ––– ––– 1.0 µA VDS =40 V, VGS = 0V
––– ––– 150 VDS =40V,VGS = 0V,TJ =125°C
IGSS Gate-to-Source Forward Leakage ––– ––– 100 nA VGS = 20V
Gate-to-Source Reverse Leakage ––– ––– -100 VGS = -20V
RG Gate Resistance ––– 2.2 –––
m
Notes:
Calculated continuous current based on maximum allowable junction temperature. Bond wire current limit is 240A
by source bonding technology. Note that current limitations arising from heating of the device leads may occur with
some lead mounting arrangements. (Refer to AN-1140)
Repetitive rating; pulse width limited by max. junction temperature.
Limited by TJmax, starting TJ = 25°C, L = 153µH, RG = 50, IAS = 100A, VGS =10V.
ISD 100A, di/dt 1403A/µs, VDD V(BR)DSS, TJ 175°C.
Pulse width 400µs; duty cycle 2%.
C
oss eff. (TR) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS.
C
oss eff. (ER) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 to 80% VDSS.
R
is measured at TJ approximately 90°C.
Limited by TJmax, starting TJ = 25°C, L = 1mH, RG = 50, IAS = 54A, VGS =10V.
When mounted on 1" square PCB (FR-4 or G-10 Material). Please refer to AN-994 for more details:
http://www.irf.com/technical-info/appnotes/an-994.pdf
*Pulse drain current is limited at 960A by source bonding technology.
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Dynamic Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Symbol Parameter Min. Typ. Max. Units Conditions
gfs Forward Transconductance 176 ––– ––– S VDS = 10V, ID =100A
Qg Total Gate Charge ––– 305 460 ID = 100A
Qgs Gate-to-Source Charge ––– 84 ––– VDS = 20V
Qgd Gate-to-Drain Charge ––– 96 ––– VGS = 10V
Qsync Total Gate Charge Sync. (Qg– Qgd) ––– 209 –––
td(on) Turn-On Delay Time ––– 28 –––
ns
VDD = 20V
tr Rise Time ––– 79 ––– ID = 30A
td(off) Turn-Off Delay Time ––– 161 ––– RG= 2.7
tf Fall Time ––– 93 ––– VGS = 10V
Ciss Input Capacitance ––– 13975 –––
pF
VGS = 0V
Coss Output Capacitance ––– 2140 ––– VDS = 25V
Crss Reverse Transfer Capacitance ––– 1438 ––– ƒ = 1.0MHz, See Fig.7
Coss eff.(ER)
Effective Output Capacitance (Energy Relat-
ed) ––– 2620 ––– VGS = 0V, VDS = 0V to 32V
See Fig.11
Coss eff.(TR) Output Capacitance (Time Related) ––– 3306 ––– VGS = 0V, VDS = 0V to 32V
Diode Characteristics
Symbol Parameter Min. Typ. Max. Units Conditions
IS Continuous Source Current ––– ––– 522
A
MOSFET symbol
(Body Diode) showing the
ISM Pulsed Source Current ––– ––– 1200*integral reverse
(Body Diode) p-n junction diode.
VSD Diode Forward Voltage ––– 0.8 1.2 V TJ = 25°C,IS = 100A,VGS = 0V
dv/dt Peak Diode Recovery dv/dt ––– 1.6 ––– V/ns TJ = 175°C,IS =100A,VDS = 40V
trr Reverse Recovery Time ––– 50 ––– ns TJ = 25°C VDD = 34V
––– 58 ––– TJ = 125°C IF = 100A,
Qrr Reverse Recovery Charge ––– 59 ––– nC TJ = 25°C di/dt = 100A/µs
––– 72 ––– TJ = 125°C
IRRM Reverse Recovery Current ––– 2.2 ––– A TJ = 25°C
nC
D
S
G
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Fig 6. Normalized On-Resistance vs. Temperature
Fig 5. Typical Transfer Characteristics
Fig 4. Typical Output Characteristics
Fig 3. Typical Output Characteristics
Fig 7. Typical Capacitance vs. Drain-to-Source Voltage Fig 8. Typical Gate Charge vs. Gate-to-Source Voltage
0.1 110 100
VDS, Drain-to-Source Voltage (V)
0.1
1
10
100
1000
ID, Drain-to-Source Current (A)
VGS
TOP 15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
60µs PULSE WIDTH
Tj = 25°C
4.5V
0.1 110 100
VDS, Drain-to-Source Voltage (V)
10
100
1000
ID, Drain-to-Source Current (A)
4.5V
60µs PULSE WIDTH
Tj = 175°C
VGS
TOP 15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
2345678
VGS, Gate-to-Source Voltage (V)
0.1
1
10
100
1000
ID, Drain-to-Source Current (A)
TJ = 25°C
TJ = 175°C
VDS = 10V
60µs PULSE WIDTH
-60 -20 20 60 100 140 180
TJ , Junction Temperature (°C)
0.4
0.8
1.2
1.6
2.0
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID = 100A
VGS = 10V
0.1 110 100
VDS, Drain-to-Source Voltage (V)
100
1000
10000
100000
1000000
C, Capacitance (pF)
VGS = 0V, f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
Coss
Crss
Ciss
0 50 100 150 200 250 300 350 400
QG, Total Gate Charge (nC)
0.0
2.0
4.0
6.0
8.0
10.0
12.0
14.0
VGS, Gate-to-Source Voltage (V)
VDS= 32V
VDS= 20V
ID = 100A
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Fig 10. Maximum Safe Operating Area
Fig 11. Drain-to–Source Breakdown Voltage Fig 12. Typical Coss Stored Energy
Fig 13. Typical On-Resistance vs. Drain Current
Fig 9. Typical Source-Drain Diode Forward Voltage
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
VSD, Source-to-Drain Voltage (V)
0.1
1
10
100
1000
ISD, Reverse Drain Current (A)
TJ = 25°C
TJ = 175°C
VGS = 0V
0.1 1 10 100
VDS, Drain-to-Source Voltage (V)
0.1
1
10
100
1000
10000
ID, Drain-to-Source Current (A)
Tc = 25°C
Tj = 175°C
Single Pulse
10msec
1msec
OPERATION IN THIS AREA
LIMITED BY RDS(on)
100µsec
DC
Limited by Package
-60 -20 20 60 100 140 180
TJ , Temperature ( °C )
40
41
42
43
44
45
46
47
48
V(BR)DSS, Drain-to-Source Breakdown Voltage (V)
Id = 2.0mA
-5 0 5 10 15 20 25 30 35 40 45
VDS, Drain-to-Source Voltage (V)
0.0
0.5
1.0
1.5
2.0
2.5
Energy (µJ)
0100 200 300 400 500
ID, Drain Current (A)
0.0
2.0
4.0
6.0
8.0
10.0
RDS(on), Drain-to -Source On Resistance (
m)
VGS = 5.5V
VGS = 6.0V
VGS = 7.0V
VGS = 8.0V
VGS = 10V
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Fig 14. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 16. Maximum Avalanche Energy vs. Temperature
Fig 15. Avalanche Current vs. Pulse width
Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.irf.com)
1.Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of Tjmax. This is validated for every
part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not
exceeded.
3. Equation below based on circuit and waveforms shown in Figures
23a, 23b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage
increase during avalanche).
6. Iav = Allowable avalanche current.
7. T = Allowable rise in junction temperature, not to exceed Tjmax
(assumed as 25°C in Figure 14, 15).
t
av = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
Z
thJC(D, tav) = Transient thermal resistance, see Figures 13)
PD (ave) = 1/2 ( 1.3·BV·Iav) = T/ ZthJC
I
av = 2T/ [1.3·BV·Zth]
E
AS (AR) = PD (ave)·tav
1E-006 1E-005 0.0001 0.001 0.01 0.1
t1 , Rectangular Pulse Duration (sec)
0.0001
0.001
0.01
0.1
1
Thermal Response ( Z
thJC ) °C/W
0.20
0.10
D = 0.50
0.02
0.01
0.05
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
tav (sec)
1
10
100
1000
Avalanche Current (A)
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming j = 25°C and
Tstart = 150°C.
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming Tj = 150°C and
Tstart =25°C (Single Pulse)
25 50 75 100 125 150 175
Starting TJ , Junction Temperature (°C)
0
100
200
300
400
500
600
700
800
EAR , Avalanche Energy (mJ)
TOP Single Pulse
BOTTOM 1.0% Duty Cycle
ID = 100A
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Fig 17. Threshold Voltage vs. Temperature
Fig 21. Typical Stored Charge vs. dif/dt
Fig 18. Typical Recovery Current vs. dif/dt
-75 -25 25 75 125 175 225
TJ , Temperature ( °C )
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
VGS(th), Gate threshold Voltage (V)
ID = 250µA
ID = 1.0mA
ID = 1.0A
0200 400 600 800 1000
diF /dt (A/µs)
0
2
4
6
8
10
12
14
16
IRRM (A)
IF = 60A
VR = 34V
TJ = 25°C
TJ = 125°C
0200 400 600 800 1000
diF /dt (A/µs)
2
4
6
8
10
12
14
IRRM (A)
IF = 100A
VR = 34V
TJ = 25°C
TJ = 125°C
0200 400 600 800 1000
diF /dt (A/µs)
0
100
200
300
400
500
600
700
QRR (nC)
IF = 60A
VR = 34V
TJ = 25°C
TJ = 125°C
0200 400 600 800 1000
diF /dt (A/µs)
50
100
150
200
250
300
350
400
450
QRR (nC)
IF = 100A
VR = 34V
TJ = 25°C
TJ = 125°C
Fig 20. Typical Stored Charge vs. dif/dt
Fig 19. Typical Recovery Current vs. dif/dt
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Fig 22. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs
Fig 23a. Unclamped Inductive Test Circuit
R
G
I
AS
0.01
t
p
D.U.T
L
VDS
+
-V
DD
DRIVER
A
15V
20V
Fig 24a. Switching Time Test Circuit
Fig 25a. Gate Charge Test Circuit
tp
V
(BR)DSS
I
AS
Fig 23b. Unclamped Inductive Waveforms
Fig 24b. Switching Time Waveforms
Vds
Vgs
Id
Vgs(th)
Qgs1 Qgs2 Qgd Qgodr
Fig 25b. Gate Charge Waveform
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Qualification Information†
Qualification Level
Industrial
(per JEDEC JESD47F) ††
Moisture Sensitivity Level D2Pak-7Pin MSL1
RoHS Compliant Yes
† Qualification standards can be found at International Rectifier’s web site: http://www.irf.com/product-info/reliability/
†† Applicable version of JEDEC standard at the time of product release.
IR WORLD HEADQUARTERS: 101 N. Sepulveda Blvd., El Segundo, California 90245, USA
To contact International Rectifier, please visit http://www.irf.com/whoto-call/
Revision History
Date Comments
11/6/2014 Updated EAS (L =1mH) = 1454mJ on page 2
Updated note 9 “Limited by TJmax, starting TJ = 25°C, L = 1mH, RG = 50, IAS = 54A, VGS =10V”. on page 2
