1-/2-Channel 15 V Digital Potentiometer
AD5260/AD5262
Rev. A
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FEATURES
256 positions
AD5260: 1 channel
AD5262: 2 channels (independently programmable)
Potentiometer replacement
20 kΩ, 50 kΩ, 200 kΩ
Low temperature coefficient: 35 ppm/°C
4-wire, SPI-compatible serial data input
5 V to 15 V single-supply; ±5.5 V dual-supply operation
Power on midscale preset
APPLICATIONS
Mechanical potentiometer replacement
Instrumentation: gain, offset adjustment
Stereo channel audio level control
Programmable voltage-to-current conversion
Programmable filters, delays, time constants
Line impedance matching
Low resolution DAC replacement
GENERAL DESCRIPTION
The AD5260/AD5262 provide a single- or dual-channel, 256-
position, digitally controlled variable resistor (VR) device.1
These devices perform the same electronic adjustment function
as a potentiometer or variable resistor. Each channel of the
AD5260/AD5262 contains a fixed resistor with a wiper contact
that taps the fixed resistor value at a point determined by a
digital code loaded into the SPI-compatible serial-input register.
The resistance between the wiper and either end point of the
fixed resistor varies linearly with respect to the digital code
transferred into the VR latch. The variable resistor offers a
completely programmable value of resistance, between the A
terminal and the wiper or the B terminal and the wiper. The
fixed A-to-B terminal resistance of 20 Ω, 50 Ω, or 200 Ω has a
nominal temperature coefficient of 35 ppm/°C. Unlike the
majority of the digital potentiometers in the market, these
devices can operate up to 15 V or ±5 V provided proper supply
voltages are furnished.
Each VR has its own VR latch that holds its programmed
resistance value. These VR latches are updated from an internal
serial-to-parallel shift register, which is loaded from a standard
3-wire serial-input digital interface. The AD5260 contains an
8-bit serial register whereas the AD5262 contains a 9-bit serial
register. Each bit is clocked into the register on the positive
FUNCTIONAL BLOCK DIAGRAMS
RDAC
REGISTER
LOGIC
8
POWER-ON
RESET
SERIAL INPUT REG IST ER
AD5260
S
HDN
VDD
VSS
VL
CS
CLK
SDI
GND
A
WB
SDO
PR
02695-001
Figure 1. AD5260
RDAC1
REGISTER RDAC2
REGISTER
LOGIC
8
POWER-ON
RESET
SERI AL INP UT REG IST ER
AD5262
SHDN
VDD
VSS
VL
CS
CLK
SDI
GND
A
1W1B1 A2W2B2
SDO
PR
02695-002
Figure 2. AD5262
edge of the CLK pin. The AD5262 address bit determines the
corresponding VR latch to be loaded with the last eight bits of
the data word during the positive edging of CS strobe. A serial
data output pin at the opposite end of the serial register enables
simple daisy-chaining in multiple VR applications without
additional external decoding logic. An optional reset pin (PR)
forces the wiper to the midscale position by loading 0x80 into
the VR latch.
The AD5260/AD5262 are available in thin surface-mount
14-lead TSSOP and 16-lead TSSOP packages. All parts are
guaranteed to operate over the extended industrial temperature
range of −40°C to +85°C.
1 The terms digital potentiometers, VR, and RDAC are used interchangeably.
AD5260/AD5262
Rev. A | Page 2 of 24
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagrams............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics—20 kΩ, 50 kΩ, 200 kΩ Versions .. 3
Timing Diagrams.......................................................................... 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Typical Performance Characteristics ............................................. 9
Test Circuits..................................................................................... 14
Theory of Operation ...................................................................... 15
Digital Interfacing ...................................................................... 15
Daisy-Chain Operation ............................................................. 16
RDAC Structure.......................................................................... 16
Programming the Variable Resistor......................................... 16
Programming the Potentiometer Divider ............................... 17
Layout and Power Supply Bypassing ....................................... 18
Terminal Voltage Operating Range ......................................... 18
Power-Up Sequence ................................................................... 18
RDAC Circuit Simulation Model............................................. 18
Macro Model Net List for RDAC ............................................. 18
Applications Information.............................................................. 19
Bipolar DC or AC Operation from Dual Supplies................. 19
Gain Control Compensation .................................................... 19
Programmable Voltage Reference............................................ 19
8-Bit Bipolar DAC ...................................................................... 19
Bipolar Programmable Gain Amplifier................................... 20
Programmable Voltage Source with Boosted Output ........... 20
Programmable 4 mA-to-20 mA Current Source ................... 20
Programmable Bidirectional Current Source......................... 21
Programmable Low-Pass Filter ................................................ 21
Programmable Oscillator .......................................................... 21
Resistance Scaling ...................................................................... 22
Outline Dimensions ....................................................................... 23
Ordering Guide .......................................................................... 24
REVISION HISTORY
8/10—Rev. 0 to Rev. A
Updated Format..................................................................Universal
Deleted Figure 1; Renumbered Sequentially................................. 1
Changes to General Description Section ...................................... 1
Changes to Conditions of Channel Resistance Matching
(AD5262 only) Parameter, Voltage Divider Temperature
Coefficient Parameter, Full-Scale Error Parameter, and Zero-
Scale Error Parameter, Table 1........................................................ 3
Changes to Table 2 and Table 3....................................................... 5
Changes to Table 4............................................................................ 6
Changes to Table 5............................................................................ 7
Changes to Table 6............................................................................ 8
Changes to Figure 11 Caption and Figure 12 ................................9
Changes to Figure 31...................................................................... 12
Changes to Figure 35 Caption ...................................................... 13
Changes to Figure 43 and Figure 46............................................. 14
Deleted Potentiometer Family Selection Guide ......................... 18
Change to Programmable Voltage Source with Boosted Output
Section.............................................................................................. 20
Changes to Figure 64...................................................................... 21
Updated Outline Dimensions....................................................... 23
Changes to Ordering Guide.......................................................... 24
3/02—Revision 0: Initial Version
AD5260/AD5262
Rev. A | Page 3 of 24
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—20 kΩ, 50 kΩ, 200 kΩ VERSIONS
VDD = +15 V, VSS = 0 V, or VDD = +5 V, VSS = –5 V; VL = +5 V; VA = +5 V, VB = 0 V, −40°C < TA < +85°C, unless otherwise noted.
The AD5260/AD5262 contain 1968 transistors. Die size: 89 mil × 105 mil (9345 sq mil).
Table 1.
Parameter Symbol Conditions Min Typ1 Max Unit
DC CHARACTERISTICS RHEOSTAT MODE Specifications apply to all VRs
Resistor Differential Nonlinearity2 R-DNL RWB, VA = no connect −1 ±¼ +1 LSB
Resistor Nonlinearity2 R-INL RWB, VA = no connect −1 ±½ +1 LSB
Nominal Resistor Tolerance3 ΔRAB TA = 25°C −30 30 %
Resistance Temperature Coefficient ΔRAB/ΔT Wiper = no connect 35 ppm/°C
Wiper Resistance RW IW = 1 V/RAB 60 150 Ω
Channel Resistance Matching (AD5262 only) ΔRWB/RWB Channel 1 and Channel 2 RWB,
DX = 0x80
0.1 %
Resistance Drift ΔRAB 0.05 %
DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Specifications apply to all VRs
Resolution N 8 Bits
Differential Nonlinearity4 DNL −1 ±1/4 +1 LSB
Integral Nonlinearity4 INL −1 ±1/2 +1 LSB
Voltage Divider Temperature Coefficient ΔVW/ΔT Code = half scale 5 ppm/°C
Full-Scale Error WFSE Code = full scale −2 −1 +0 LSB
Zero-Scale Error VWZSE Code = zero scale 0 1 2 LSB
RESISTOR TERMINALS
Voltage Range5 VA, B, W VSS VDD V
Ax and Bx Capacitance6 C
A,B f = 5 MHz, measured to GND,
code = half scale
25 pF
Wx Capacitance6 CW f = 1 MHz, measured to GND,
code = half scale
55 pF
Common-Mode Leakage Current ICM VA = VB = VDD/2 1 nA
Shutdown Current7 ISHDN 5 μA
DIGITAL INPUTS and OUTPUTS
Input Logic High VIH 2.4 V
Input Logic Low VIL 0.8 V
Input Logic High VIH VL = 3 V, VSS = 0 V 2.1 V
Input Logic Low VIL VL = 3 V, VSS = 0 V 0.6 V
Output Logic High (SDO) VOH RPULL-UP = 2 kΩ to 5 V 4.9 V
Output Logic Low (SDO) VOL IOL = 1.6 mA, VLOGIC = 5 V 0.4 V
Input Current8 IIL VIN = 0 V or 5 V ±1 μA
Input Capacitance6 CIL 5 pF
POWER SUPPLIES
Logic Supply VL 2.7 5.5 V
Power Single-Supply Range VDD RANGE VSS = 0 V 4.5 16.5 V
Power Dual-Supply Range VDD/SS RANGE ±4.5 ±5.5 V
Logic Supply Current IL VL = 5 V 60 μA
Positive Supply Current IDD VIH = 5 V or VIL = 0 V 1 μA
Negative Supply Current ISS VSS= −5 V 1 μA
Power Dissipation9 P
DISS V
IH = 5 V or VIL = 0 V,
VDD = +5 V, VSS = –5 V
0.3 mW
Power Supply Sensitivity PSS ΔVDD= +5 V, ±10% 0.003 0.01 %/%
AD5260/AD5262
Rev. A | Page 4 of 24
Parameter Symbol Conditions Min Typ1 Max Unit
DYNAMIC CHARACTERISTICS6, 10
Bandwidth –3 dB BW RAB = 20 kΩ/50 kΩ/200 kΩ 310/130/30 kHz
Total Harmonic Distortion THDW VA = 1 VRMS, VB = 0 V, f = 1 kHz,
RAB = 20 kΩ
0.014 %
VW Settling Time tS VA = +5 V, VB = −5 V, ±1 LSB
error band, RAB = 20 kΩ
5 μs
Crosstalk11 CT VA = VDD, VB = 0 V, measure VW
with adjacent RDAC making
full-scale code change (AD5262
only)
1 nV-sec
Analog Crosstalk CTA VA1 = VDD, VB1 = 0 V, measure VW1
with VW2 = 5 V p-p at f = 10 kHz,
RAB = 20 kΩ/200 kΩ (AD5262
only)
–64 dB
Resistor Noise Voltage eN_WB RWB = 20 kΩ, f = 1 kHz 13 nV/√Hz
INTERFACE TIMING CHARACTERISTICS6, 12 Specifications apply to all parts
Clock Frequency fCLK 25 MHz
Input Clock Pulse Width tCH, tCL Clock level high or low 20 ns
Data Setup Time tDS 10 ns
Data Hold Time tDH 10 ns
CLK to SDO Propagation Delay13 tPD RL = 1 kΩ, CL< 20 pF 1 160 ns
CS Setup Time tCSS 5 ns
CS High Pulse Width tCSW 20 ns
Reset Pulse Width tRS 50 ns
CLK Fall to CS Rise Hold Time tCSH 0 ns
CS Rise to Clock Rise Setup tCS1 10 ns
1 Typical values represent average readings at 25°C and VDD = +5 V, VSS = −5 V.
2 Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. IW = VDD/R for both VDD = +5 V and
VSS = −5V.
3 VAB = VDD, wiper = no connect.
4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output digital-to-analog converter. VA = VDD and VB = 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
5 Resistor Terminal A, Terminal B, and Terminal W have no limitations on polarity with respect to each other.
6 Guaranteed by design and not subject to production test.
7 Measured at the Ax terminals. All Ax terminals are open-circuit in shutdown mode.
8 Worst-case supply current consumed when all logic-input levels set at 2.4 V, which is the standard characteristic of CMOS logic.
9 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
10 All dynamic characteristics use VDD = +5 V, VSS = −5 V, VL = +5 V.
11 Measured at VW where an adjacent VW is making a full-scale voltage change.
12 See Figure 5 for location of measured values. All input control voltages are specified with tR = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.
Switching characteristics are measured using VL = 5 V.
13 Propagation delay depends on value of VDD, RL, and CL.
AD5260/AD5262
Rev. A | Page 5 of 24
TIMING DIAGRAMS
Table 2. AD5260 8-Bit Serial Data Word Format
Data
B7 (MSB) B6 B5 B4 B3 B2 B1 B0 (LSB)
D7 D6 D5 D4 D3 D2 D1 D0
27 26 2
5 2
4 2
3 2
2 2
1 2
0
Table 3. AD5262 9-Bit Serial Data Word Format
ADDR Data
B8 B7 (MSB) B6 B5 B4 B3 B2 B1 B0 (LSB)
A0 D7 D6 D5 D4 D3 D2 D1 D0
28 27 26 2
5 2
4 2
3 2
2 2
1 2
0
RDAC REGIST E R L O AD
CS
D7 D6 D5 D4 D3 D2 D1 D0
SDI 1
0
CLK 1
0
1
0
V
OUT
1
0
0
2695-004
Figure 3. AD5260 Timing Diagram
RDAC REGIST E R LOAD
CS
D7A0 D6 D5 D4 D3 D2 D1 D0
SDI 1
0
CLK 1
0
1
0
V
OUT
1
0
02695-005
Figure 4. AD5262 Timing Diagram
1
0
1
0
1
0
1
0
VDD
VOUT 0V ±1 L SB
±1 L S B E RROR BRAND
Ax OR Dx
A'x OR D' x
Dx
D'x
t
DS
t
CH
t
S
t
CL
t
CSS
t
PD
t
DH
t
CSH
t
CS1
t
CSW
CS
SDO
(DATA OUT)
SDI
(DAT A IN)
CLK
02695-006
Figure 5. Detailed Timing Diagram
PR
1
0
V
DD
0V ±1 LSB ERROR BAND ±1 LSBD
t
RS
t
S
02695-007
Figure 6. Preset Timing Diagram
AD5260/AD5262
Rev. A | Page 6 of 24
ABSOLUTE MAXIMUM RATINGS
TA =25°C, unless otherwise noted.
Table 4.
Parameter Rating
VDD to GND −0.3 V to +17 V
VSS to GND 0 V to −7 V
VDD to VSS 17 V
VL to GND 0 V to +7 V
VA, VB, VW to GND VSS, VDD
AX to BX, AX to WX, BX to WX
Intermittent1 ±20 mA
Continuous ±5 mA
Digital Inputs and Output Voltage
to GND
−0.3 V to VL + 0.3 V, or
+7 V (whichever is less)
Operating Temperature Range −40°C to +85°C
Maximum Junction Temperature
(TJ MAX) 150°C
Storage Temperature Range −65°C to +150°C
Lead Temperature (Soldering,10 sec) 300°C
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C
Thermal Resistance2 θJA
14-Lead TSSOP 206°C/W
16-Lead TSSOP 150°C/W
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
1 Maximum terminal current is bounded by the maximum current handling of
the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance setting.
2 Package power dissipation = (TJ MAX − TA)/θJA.
AD5260/AD5262
Rev. A | Page 7 of 24
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
AD5260
NC = NO CONNECT
1
2
3
4
5
6
7
W
B
V
DD
SDI
CLK
S
HDN
A
14
13
12
11
10
9
8
NC
V
L
V
SS
CS
PR
GND
SDO
TOP VIEW
(No t t o Scale)
0
2695-008
Figure 7. AD5260 Pin Configuration
Table 5. AD5260 Pin Function Descriptions
Pin No. Mnemonic Description
1 A A Terminal.
2 W Wiper Terminal.
3 B B Terminal.
4 VDD Positive Power Supply. Specified for operation at both 5 V or 15 V (sum of |VDD| + |VSS| ≤ 15 V).
5 SHDN Active Low Input. Terminal A, open-circuit. Shutdown controls variable resistor.
6 CLK Serial Clock Input, Positive Edge Triggered.
7 SDI Serial Data Input.
8 CS Chip Select Input, Active Low. When CS returns high, data is loaded into the RDAC register.
9 PR Active Low Preset to Midscale. Sets RDAC registers to 0x80.
10 GND Ground.
11 VSS Negative Power Supply. Specified for operation from 0 V to −5 V.
12 VL Logic Supply Voltage. Needs to be the same voltage as the digital logic controlling the AD5260.
13 NC No Connect. Users should not connect anything other than a dummy pad on this pin.
14 SDO Serial Data Output. Open-drain transistor requires a pull-up resistor.
AD5260/AD5262
Rev. A | Page 8 of 24
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
AD5262
TOP VIEW
(Not to Scale)
W1
B1
V
DD
SDI
CLK
SHDN
A1 W2
B2
A2
SDO
V
L
V
SS
CS
PR
GND
02695-009
Figure 8. AD5262 Pin Configuration
Table 6. AD5262 Pin Function Descriptions
Pin No. Mnemonic Description
1 SDO Serial Data Output. Open-drain transistor requires a pull-up resistor.
2 A1 A Terminal RDAC 1.
3 W1 Wiper RDAC 1, Address A0 = 0.
4 B1 B Terminal RDAC 1.
5 VDD Positive Power Supply. Specified for operation at both 5 V or 15 V. (Sum of |VDD| + |VSS| ≤ 15 V)
6 SHDN Active Low Input. Terminal A, open-circuit. Shutdown controls variable Resistor 1 through Resistor R2.
7 CLK Serial Clock Input, Positive Edge Triggered.
8 SDI Serial Data Input.
9 CS Chip Select Input, Active Low. When CS returns high, data in the serial input register is decoded, based on the
Address Bit A0, and loaded into the target RDAC register.
10 PR Active Low Preset to Midscale. Sets RDAC registers to 0x80.
11 GND Ground.
12 VSS Negative Power Supply. Specified for operation at either 0 V or −5 V (sum of |VDD| + |VSS| < 15 V).
13 VL Logic Supply Voltage. Needs to be same voltage as the digital logic controlling the AD5262.
14 B2 B Terminal RDAC 2.
15 W2 Wiper RDAC 2, Address A0 = 1.
16 A2 A Terminal RDAC 2.
AD5260/AD5262
Rev. A | Page 9 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
POTENTI O M E TER MODE DNL (LSB)
T
A
= –40°C
T
A
= +25°C
T
A
= +85°C
T
A
= +125°C
CODE (Deci m al)
0 32 64 96 128 160 192 224 256
02695-013
V
DD
= +5V
V
SS
= –5V
R
AB
= 20kΩ
CODE (D ecimal)
RHEOSTAT MODE INL (LSB )
–0.2
–0.1
0.1
0
0 32 64 96 128 160 192 224 256
0.2
0.3
0.4
0.5
0.6
0.7
0.8
+15V
+5V
±5V +12V
02695-010
Figure 12. DNL vs. Code
Figure 9. R-INL vs. Code vs. Supply Voltages
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0 32 64 96 128 160 192 224 256
CODE (Decimal)
POTENTIOMETER MODE INL (LSB)
+15V
+5V
±5V
02695-014
CODE (Decimal)
RHEOSTAT MODE DNL (LSB)
–0.25 0 32 64 96 128 160 192 224 256
–0.20
–0.15
–0.10
–0.05
0
0.05
0.10
+15V
+12V
+5V
±5V
02695-011
Figure 13. INL vs. Code vs. Supply Voltages
Figure 10. R-DNL vs. Code vs. Supply Voltages
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
POTENTI OME TER M ODE DNL (LSB)
0 32 64 96 128 160 192 224 256
CODE (Deci m al)
+15V
+5V
±5V
02695-015
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
0 32 64 96 128 160 192 224 256
CODE (Dec i mal )
PO T E NT I OM ET E R MODE I NL (LSB)
VDD = +5V
TA = +125°C
TA = +85° C TA = –40°C
TA = +25°C
VSS = –5V
RAB = 20kΩ
02695-012
Figure 14. DNL vs. Code vs. Supply Voltages
Figure 11. INL vs. Code
AD5260/AD5262
Rev. A | Page 10 of 24
–1.0
–0.5
0
0.5
1.0
0 5 10 15 20
|V
DD
– V
SS
| (V)
POTENTIOMETER MODE INL (LSB)
AVG – 3σ
AVG
AVG + 3σ
02695-016
Figure 15. INL vs. Supply Voltages
–2.0
–1.0
–1.5
–0.5
0
0.5
2.0
1.0
1.5
05
10 15 20
|V
DD
– V
SS
| (V)
RHEOST
A
T MODE INL (LSB)
AVG – 3σ
AVG
AVG + 3σ
02695-017
Figure 16. R-INL vs. Supply Voltages
4
24
44
64
84
104
124
–5 –1 3 7 11 15
V
DD
(V)
WIPE R RE S ISTANCE (Ω)
R
ON
@ V
DD
/V
SS
= +5V/0V
R
ON
@ V
DD
/V
SS
= +5V/–5V
R
ON
@ V
DD
/V
SS
= +15V/0V
02695-018
Figure 17. Wiper On Resistance vs. Bias Voltage
0
0.5
1.0
1.5
2.0
2.5
–40 –20 0 20 40 60 80 100
TEMPERATURE (°C)
FSE (LSB)
V
DD
/V
SS
=+5V/0V
V
DD
/V
SS
=+15/0V
V
DD
/V
SS
=±5V
02695-019
Figure 18. Full-Scale Error vs. Temperature
0
0.5
1.0
1.5
2.0
2.5
–40 –20 0 20 40 60 80 100
TE MP E RATURE (°C)
ZSE (LSB)
V
DD
/V
SS
=+15/0V
V
DD
/V
SS
=±5V
V
DD
/V
SS
=+5V/0V
02695-020
Figure 19. Zero-Scale Error vs. Temperature
0.001
0.01
0.1
1
–40–726599212
TE MPERATURE (°C)
I
DD
/I
SS
SUPPLY CURRENT (µ A)
5
V
LOGIC
= 5V
V
IH
= 5V
V
IL
= 0V
V
DD
/V
SS
= ±5V
V
DD
/V
SS
= +15/0V
02695-021
Figure 20. Supply Current vs. Temperature
AD5260/AD5262
Rev. A | Page 11 of 24
24.5
25.0
25.5
26.0
26.5
27.0
27.5
28.0
–40–726599212
TE M P E RATURE (°C)
I
LOGIC
(µA)
5
V
DD
/V
SS
= ±5V
V
DD
/V
SS
= +1 5/0V
0
2695-022
Figure 21. ILOGIC vs. Temperature
10
100
1000
0 1.0 2.0 3.0 4.00.5 1.5 2.5 3.5 4.5 5.0
V
IH
(V)
I
LOGIC
(µA)
02695-023
V
DD
/V
SS
= 5V/0V
V
LOGIC
= 5V
V
DD
/V
SS
= 5V/0V
V
LOGIC
= 3V
Figure 22. ILOGIC vs. Digital Input Voltage
–20
–10
0
10
20
30
40
50
60
70
80
0 32 64 96 128 160 192 224 256
CODE ( Decimal)
RHEOST
T MODE TEMPCO (ppm/°C)
50kΩ
20kΩ
200kΩ
02695-024
Figure 23. Rheostat Mode Tempco ΔRWB /ΔT vs. Code
–60
–40
–20
0
20
40
60
80
100
120
0 32 64 96 128 160 192 224 256
CODE ( Decimal )
PO TENTI OMETER MODE TEM P CO ( pp m/° C)
50kΩ
20kΩ
200kΩ
02695-025
Figure 24. Potentiometer Mode Tempco ΔVWB/ΔT vs. Code
FREQUENCY (Hz)
GAIN (dB)
1k 1M
6
–48
–54
–42
–36
–30
–24
–18
–12
–6
0
10k 100k
COD E = 0xFF
0x01
0x02
0x04
0x08
0x10
0x20
0x40
0x80
T
A
= 25°C
02695-026
Figure 25. Gain vs. Frequency vs. Code, RAB = 20 kΩ
FREQUENCY (Hz)
GAIN (dB)
1k 1M
6
–48
–42
–36
–30
–24
–18
–12
–6
0
10k 100k
COD E = 0xFF
0x01
0x02
0x04
0x08
0x10
0x20
0x40
0x80
T
A
= 25°C
02695-027
–54
Figure 26. Gain vs. Frequency vs. Code, RAB = 50 kΩ
AD5260/AD5262
Rev. A | Page 12 of 24
FREQUENCY (Hz)
GAIN (dB)
1k 1M
–54
6
–48
–42
–36
–30
–24
–18
–12
–6
0
10k 100k
T
A
= 25°C CODE = 0xF F
0x01
0x02
0x04
0x08
0x10
0x20
0x40
0x80
02695-028
Figure 27. Gain vs. Frequency vs. Code, RAB = 200 kΩ
FRE QUENCY ( Hz)
1k 1M10k 100k
–3dB
BANDWIDTHS V
IN
= 50mV rms
V
DD
/V
SS
= ±5V
f
–3dB
= 30kHz , R = 200kΩ
f
–3dB
= 131kHz , R = 50kΩ
f
–3dB
= 310kHz , R = 20 kΩ
GAIN (dB)
–54
6
–48
–42
–36
–30
–24
–18
–12
–6
0
02695-029
Figure 28. −3 dB Bandwidth
FRE QUENCY ( Hz)
NORM ALI Z E D G AI N FLA T N ESS ( d B)
100 100k1k
0
0.1
0.2
0.3
–0.4
–0.3
–0.2
–0.7
–0.6
–0.5
–0.1
10k
CODE = 0x80
V
DD
/V
SS
= ±5V
T
A
= 25°C
R = 200kΩ
R = 50kΩ
R = 20kΩ
02695-030
Figure 29. Normalized Gain Flatness vs. Frequency
FRE QUENCY ( Hz )
ILOGIC (µA)
10k 10M100k
600
300
400
500
0
100
200
1M
CODE 0x FF
CODE 0x55
VDD/VSS = ±5V
VDD/VSS = +5V/ 0V
02695-031
Figure 30. ILOGIC vs. Frequency
FRE Q UE NC Y ( Hz )
PSRR (d B)
100 1M
0
60
10k
10
1k
20
30
40
50
100k
–PSRR @ V
DD
= ±5V DC ± 10 % p-p AC
+PSRR @ V
DD
= ±5V DC ± 10% p-p AC
CODE = 0x80, V
A
= V
DD
, V
B
= 0V
02695-032
Figure 31. PSRR vs. Frequency
20mV/DIV
1µs/DIV
5V/DIV
02695-033
Figure 32. Midscale Glitch Energy, Code 0x80 to 0x7F
AD5260/AD5262
Rev. A | Page 13 of 24
HOURS OF OPERAT ION AT 15 0°C
CHANG E IN T E RM INA L RE S I
S
TA NC E ( %)
05
–0.20
0.10
–0.10
0
0.05
00
100 200 250 300 350 400 450
AVG – 3σ
50 150
–0.05
–0.15
AVG + 3σ
AVG
0
2695-037
CODE = 0x80
V
DD
/V
SS
= ±5V
SAMPLE SIZ E = 135 UNITS
5V/DIV
20µs/DIV
5V/DIV
02695-034
Figure 36. Long-Term Resistance Drift
Figure 33. Large Signal Settling Time
CHANNEL-TO-CHANNEL R
AB
MATCH (%)
FREQUENCY
–0.50
0
40
30
CODE SET TO MIDSCALE
T
A
= 150°C
3 LOTS
SAMPLE SIZE = 135 UNI TS
20
10
–0.40 –0.30 –0.20 –0.10 0 0.10 0.20
02695-038
10mV/DIV
40ns/DIV
02695-035
Figure 34. Digital Feedthrough vs. Time Figure 37. Channel-to-Channel Resistance Matching (AD5262)
CODE (Deci mal)
THEORETIC
L I
WB_MAX
(mA)
02
0.01
100
0.1
1
10
56
32 64 96 128 160 192 224
V
A
= V
B
= OPEN
T
A
= 25°C
R
AB
= 20kΩ
R
AB
= 50kΩ
R
AB
= 200kΩ
02695-036
Figure 35. Theoretical Maximum Current vs. Code
AD5260/AD5262
Rev. A | Page 14 of 24
TEST CIRCUITS
Figure 38 to Figure 46 define the test conditions used in Table 1.
V
MS
AW
B
DUT
V
+ = V
DD
1LS B = V +/2
N
V+
02695-039
Figure 38. Potentiometer Divider Nonlinearity Error (INL, DNL)
NC
IW
VMS
AW
B
DUT NC = NO CONNECT
02695-040
Figure 39. Resistor Position Nonlinearity Error
(Rheostat Operation; R-INL, R-DNL)
I
W
= V
DD
/R
NOMINAL
V
MS2
V
W
V
MS1
R
W
= (V
MS1
– V
MS2
)/I
W
AW
B
DUT
02695-041
Figure 40. Wiper Resistance
PSS (%/%) =
V+ = V
DD
± 10%
PSRR (dB) = 20 log ∆V
MS
∆V
DD
∆V
MS
%
∆V
DD
%
()
V
DD
V
A
V
MS
AW
B
V+
02695-042
Figure 41. Power Supply Sensitivity (PSS, PSSR)
+13V
–13V
W
A
B
VOUT
OFFSET
GND
DUT
AD8610
VIN
0
2695-043
Figure 42. Gain vs. Frequency
W
B
VSS TO VDD
DUT CO DE = 0x00
RW=0.1V
IW
IW0.1V
A = NC
02695-044
Figure 43. Incremental On Resistance
W
B
I
CM
A
NC
GND
NC
V
SS
V
CM
V
DD
DUT
02695-045
Figure 44. Common-Mode Leakage Current
SDI
CLK
CS
V
LOGIC
I
LOGIC
DIG IT AL INPUT
VOLTAGE
02695-046
Figure 45. VLOGIC Current vs. Digital Input Voltage
A1
RDAC1 RDAC2
W1
NC
B1
A2
W2
B2
C
TA
= 20 log (V
OUT
/V
IN
)
NC = NO CONNECT
V
IN
V
OUT
V
SS
V
DD
02695-047
Figure 46. Analog Crosstalk
AD5260/AD5262
Rev. A | Page 15 of 24
THEORY OF OPERATION
The AD5260/AD5262 provide a single- or dual-channel, 256-
position, digitally controlled variable resistor (VR) device and
operate up to 15 V maximum voltage. Changing the programmed
VR settings is accomplished by clocking an 8-/9-bit serial data
word into the SDI (serial data input) pin. For the AD5262, the
format of this data word is one address bit. A0 represents the
first bit, B8, followed by eight data bits, B7 to B0, with MSB
first. Table 2 and Table 3 provide the serial register data word
format. See Table 7 for the AD5262 address assignment to decode
the location of the VR latch receiving the serial register data in
Bit B7 through Bit B0. VR outputs can be changed one at a time
in random sequence. The AD5260/AD5262 preset to a midscale,
simplifying fault condition recovery at power-up. Midscale can
also be achieved at any time by asserting the PR pin. Both parts
have an internal power-on preset that places the wiper in a
midscale preset condition at power-on. Operation of the power-
on preset function depends only on the state of the VL pin.
The AD5260/AD5262 contain a power shutdown SHDN pin
that places the RDAC in an almost zero power consumption
state where Terminals Ax are open circuited and the Wiper W
is connected to B, resulting in only leakage currents being con-
sumed in the VR structure. In the shutdown mode, the VR latch
settings are maintained so that, when returning to operational
mode from power shutdown, the VR settings return to their
previous resistance values.
Table 7. AD5262 Address Decode Table
A0 Latch Loaded
0 RDAC1
1 RDAC2
DIGITAL INTERFACING
The AD5260/AD5262 contain a 4-wire SPI-compatible digital
interface (SDI, SDO, CS, and CLK). For the AD5260, the 8-bit
serial word must be loaded with the MSB first. The format of
the word is shown in . For the AD5262, the 9-bit serial
word must be loaded with Address Bit A0 first, then the MSB
of the data. The format of the word is shown in .
Table 2
Table 3
A0
SER
REG
D7
D6
D5
D4
D3
D2
D1
D0
A1
W1
B1
V
DD
CS
CLK
SDO
A2
W2
B2
GND
RDAC
LATCH
2
PR
RDAC
LATCH
1
PR
PR
SDI
V
L
V
SS
SHDN
POWER-
ON
PRESET
EN
ADDR
DEC
02695-048
Figure 47. AD5262 Block Diagram
The positive-edge sensitive CLK input requires clean transitions
to avoid clocking incorrect data into the serial input register. Stand-
ard logic families work well. If mechanical switches are used for
product evaluation, they should be debounced by a flip-flop or
other suitable means. Figure 47 shows more detail of the inter-
nal digital circuitry. When CS is low, the clock loads data into
the serial input register on each positive clock edge (see ). Table 8
Table 8. Truth Table1
CLK CS PR SHDN Register Activity
Low Low High High No SR effect, enables SDO pin.
↑ Low High High Shift one bit in from the SDI pin.
The eighth previously entered
bit is shifted out of the SDO pin.
X ↑ High High Load SR data into RDAC latch.
X High High High No operation.
X X Low High Sets all RDAC latches to half
scale, wiper centered, and SDO
latch cleared.
X High ↑ High Latches all RDAC latches to 0x80.
X High High Low Open circuits all Resistor A
terminals, connects W to B, and
turns off SDO output transistor.
1 ↑ = positive edge, X = don’t care, SR = shift register.
The data setup and data hold times in Table 1 determine the
data valid time requirements. The AD5260 uses an 8-bit serial
input data register word that is transferred to the internal
RDAC register when the CS line returns to logic high. For the
AD5262, the last nine bits of the data word entered into the
serial register are held when CS returns high. Any extra bits are
ignored. At the same time CS goes high, it gates the address
decoder, enabling one of two positive edge-triggered AD5262
RDAC latches (see ). Figure 48
AD5260/AD5262
Rev. A | Page 16 of 24
RDAC1
RDAC2
AD5260/AD5262
SDI
CLK
CS ADDR
DECODE
SERIAL
REGISTER
02695-049
Figure 48. Equivalent Input Control Logic
The target RDAC latch is loaded with the last eight bits of
the serial data word completing one RDAC update. For the
AD5262, two separate 9-bit data words must be clocked in to
change both VR settings.
During shutdown (SHDN), the SDO output pin is forced to the
off (logic high) state to disable power dissipation in the pull-up
resistor. See for the equivalent SDO output circuit
schematic.
Figure 49
SDI
CLK
CS
SHDN
PR
SERIAL
REGISTER DQ
CK RS
SDO
02695-050
Figure 49. Detail SDO Output Schematic of the AD5260
All digital inputs are protected with a series input resistor and
parallel Zener ESD structure as shown in Figure 50. This applies
to the CS, SDI, SDO, PR, SHDN, and CLK digital input pins.
340ΩLOGIC
02695-051
Figure 50. ESD Protection of Digital Pins
A, B, W
V
SS
02695-052
Figure 51. ESD Protection of Resistor Terminals
DAISY-CHAIN OPERATION
The serial data output (SDO) pin contains an open-drain N-
channel FET. This output requires a pull-up resistor to transfer
data to the SDI pin of the next package. This allows for daisy-
chaining several RDACs from a single processor serial data line.
The pull-up resistor termination voltage can be larger than the
VDD supply voltage. It is recommended to increase the clock
period when using a pull-up resistor to the SDI pin of the
following device in series because capacitive loading at the
daisy-chain node connecting SDO and SDI between devices
may induce time delay to subsequent devices. Users should
be aware of this potential problem to achieve data transfer
successfully (see Figure 52). If two AD5260s are daisy-chained,
this requires a total of 16 bits of data. The first eight bits, complying
with the format shown in Table 2, go to U2, and the second
eight bits with the same format go to U1. The CS pin should be
kept low until all 16 bits are clocked into their respective serial
registers, and the CS pin is then pulled high to complete the
operation.
V
DD
CS CLK
SDOSDIMOSI
MICRO-
CONTROLLER
SCLK SS
R
P
2.2kΩ
AD5260 AD5260
U1 U2
02695-055
CS CLK
SDOSDI
Figure 52. Daisy-Chain Configuration
RDAC STRUCTURE
The RDAC contains a string of equal resistor segments with an
array of analog switches that act as the wiper connection. The
number of positions is the resolution of the device. The AD5260/
AD5262 have 256 connection points, allowing it to provide better
than 0.4% settability resolution. Figure 53 shows an equivalent
structure of the connections between the three terminals that
make up one channel of the RDAC. SWA and SWB are always
on, while one of the switches SW(0) to SW(2N – 1) is on one at a
time, depending on the resistance position decoded from the
data bits. Because the switch is not ideal, there is a 60 Ω wiper
resistance, RW. Wiper resistance is a function of supply voltage
and temperature. The lower the supply voltage is, the higher the
wiper resistance becomes. Similarly, the higher the temperature
is, the higher the wiper resistance becomes. Users should be
aware of the contribution of the wiper resistance when accurate
prediction of the output resistance is needed.
D7
D6
D5
D4
D3
D2
D1
D0
RDAC
LATCH
AND
DECODE
Ax
Wx
Bx
R
S
= R
AB
/2
N
R
S
R
S
R
S
R
S
S
HDN
DIGITAL CIRCUI TRY
OM ITTED FO R CLARI TY
02695-056
Figure 53. Simplified RDAC Architecture
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation
The nominal resistances of the RDAC between Terminal A and
Terminal B are available with values of 20 kΩ, 50 kΩ, and 200 kΩ.
The final three digits of the part number determine the nominal
resistance value, for example, 20 kΩ = 20, 50 kΩ = 50, 200 kΩ =
200. The nominal resistance (RAB) of the VR has 256 contact points
AD5260/AD5262
Rev. A | Page 17 of 24
accessed by the wiper terminal, plus the B terminal contact. The
8-bit data in the RDAC latch is decoded to select one of the 256
possible settings. Assuming a 20 kΩ part is used, the wiper’s first
connection starts at the B terminal for data 0x00. Because there
is a 60 Ω wiper contact resistance, such a connection yields a
minimum of 60 Ω resistance between Terminal W and Terminal B.
The second connection is the first tap point corresponding to
138 Ω (RWB = RAB/256 RW = 78 Ω + 60 Ω) for Data 0x01. The third
connection is the next tap point representing 216 Ω (78 × 2 + 60)
for Data 0x02, and so on. Each LSB data value increase moves
the wiper up the resistor ladder until the last tap point is reached at
19,982 Ω (RAB − 1 LSB + RW). The wiper does not directly connect
to the B terminal. See Figure 53 for a simplified diagram of the
equivalent RDAC circuit.
The general equation determining the digitally programmed
output resistance between W and B is
W
AB
WB RR
D
DR +×= 256
)( (1)
where D is the decimal equivalent of the binary code that is
loaded in the 8-bit RDAC register and RAB is the nominal end-
to-end resistance.
For example, when RAB = 20 kΩ, VB = 0 V, and the A terminal is
open circuit, the following output resistance values of RWB are
set for the RDAC latch codes shown in Table 9. The result is the
same if Terminal A is tied to W.
Table 9. RWB vs. Code
RDAC (Dec) RWB (Ω) Output State
256 19,982 Full scale (RAB – 1 LSB + RW)
128 10,060 Midscale
1