KMM366S104CTL PC66 SDRAM MODULE Revision History Revision .3 (Mar. 1998) *Some Parameter values & Characteristics of comp. level are changed as below : - Input leakage currents (Inputs) : 5uA to 1uA. - Input leakage currents (I/O) : 5uA to 1.5uA. - Cin to be measured at V DD = 3.3V, T A = 23C, f = 1MHz, V REF = 1.4V 200mV. - AC Operating Condition is changed as defined : V IH(max) = 5.6V AC. The overshoot voltage duration is 3ns. V IL(min) = -2.0V AC. The undershoot voltage duration is 3ns. *2K/32ms is changed to 4K/64ms. REV. 3 Mar. '98 KMM366S104CTL PC66 SDRAM MODULE KMM366S104CTL SDRAM DIMM 1Mx64 SDRAM DIMM based on 1Mx16, 4K Refresh, 3.3V Synchronous DRAMs with SPD GENERAL DESCRIPTION FEATURE The Samsung KMM366S104CTL is a 1M bit x 64 Synchronous Dynamic RAM high density memory module. The Samsung KMM366S104CTL consists of four CMOS 1M x 16 bit Synchronous DRAMs in TSOP-II 400mil package and a 1K or 2K EEPROM in 8-pin TSSOP package on a 168-pin glass-epoxy substrate. Two 0.33uF decoupling capacitors are mounted on the printed circuit board in parellel for each SDRAM. The KMM366S104CTL is a Dual In-line Memory Module and is intended for mounting into 168-pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications. * Performance range * * * * * * * * Max Freq. (Speed) KMM366S104CTL-G0 100MHz (10ns) Burst Mode Operation Auto & Self Refresh Capability (4096 cycles / 64ms) LVTTL compatible inputs and outputs Single 3.3V 0.3V power supply MRS cycle with address key programs Latency (Access from column address) Burst Length (1, 2, 4, 8 & Full page) Data Scramble (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock Serial Presence Detect with EEPROM PCB : Height(1,000mil), single sided component PIN NAMES PIN CONFIGURATIONS (Front Side / Back Side) Pin Front Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 VSS DQ0 DQ1 DQ2 DQ3 V DD DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 V DD DQ14 DQ15 *CB0 *CB1 VSS NC NC V DD WE DQM0 Front 29 DQM1 CS0 30 31 DU 32 V SS 33 A0 34 A2 35 A4 36 A6 37 A8 38 A10/AP 39 *BA1 40 VDD 41 VDD 42 CLK0 43 V SS 44 DU 45 CS2 46 DQM2 47 DQM3 48 DU 49 VDD 50 NC 51 NC 52 *CB2 53 *CB3 54 V SS 55 DQ16 56 DQ17 Pin Front Pin Back Pin Back Pin Back 57 DQ18 85 VSS 113 DQM5 141 DQ50 58 DQ19 86 DQ32 114 *CS1 142 DQ51 59 87 DQ33 115 RAS 143 V DD VDD 60 DQ20 88 DQ34 116 VSS 144 DQ52 61 89 DQ35 117 NC NC A1 145 62 *V REF 90 V DD 118 A3 146 *VREF 63 *CKE1 91 DQ36 119 NC A5 147 64 92 DQ37 120 V SS A7 148 VSS 65 DQ21 93 DQ38 121 A9 149 DQ53 66 DQ22 94 DQ39 122 BA0 150 DQ54 67 DQ23 95 DQ40 123 *A11 151 DQ55 68 VSS 124 V DD 152 VSS 96 V SS 69 DQ24 97 DQ41 125 *CLK1 153 DQ56 70 DQ25 98 DQ42 126 *A12 154 DQ57 71 DQ26 99 DQ43 127 VSS 155 DQ58 72 DQ27 100 DQ44 128 CKE0 156 DQ59 73 VDD 101 DQ45 129 *CS3 157 V DD 74 DQ28 102 V DD 130 DQM6 158 DQ60 75 DQ29 103 DQ46 131 DQM7 159 DQ61 76 DQ30 104 DQ47 132 *A13 160 DQ62 77 DQ31 105 *CB4 133 V DD 161 DQ63 78 V SS 106 *CB5 134 162 VSS NC 79 *CLK2 107 VSS 135 163 *CLK3 NC 80 NC 108 NC NC 136 *CB6 164 81 NC 109 NC 137 *CB7 165 **SA0 82 **SDA 110 V DD 138 VSS 166 **SA1 83 **SCL 111 CAS 139 DQ48 167 **SA2 84 VDD 112 DQM4 140 DQ49 168 V DD Pin Name Function A0 ~ A10/AP Address Input (multiplexed) BA0 Select Bank DQ0 ~ DQ63 Data Input / Output CLK0 Clock Input CKE0 Clock Enable Input CS0, CS2 Chip Select Input RAS Row Address Storbe CAS Column Address Strobe WE Write Enable DQM0 ~ 7 DQM V DD Power Supply (3.3V) V SS Ground *V REF Power Supply for Reference SDA Serial Data I/O SCL Serial Clock SA0 ~ 2 Address in EEPROM DU Dont use NC No Connection * These pins are not used in this module. ** These pins should be NC in the system which does not support SPD. SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice. REV. 3 Mar. '98 KMM366S104CTL PC66 SDRAM MODULE PIN CONFIGURATION DESCRIPTION Pin Name Input Function CLK System Clock Active on the positive going edge to sample all inputs. CS Chip Select Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM CKE Clock Enable Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. CKE should be enabled 1CLK+t SS prior to valid command. A0 ~ A10/AP Address Row / column addresses are multiplexed on the same pins. Row address : RA0 ~ RA10, column address : CA0 ~ CA7 BA0 Bank Select Address Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. RAS Row Address Strobe Latches row addresses on the positive going edge of the CLK with Enables row access & precharge. CAS Column Address Strobe Latches column addresses on the positive going edge of the CLK with Enables column access. WE Write Enable Enables write operation and row precharge. Latches data in starting from CAS, WE active. DQM0 ~ 7 Data Input/Output Mask Makes data output Hi-Z, t SHZ after the clock and masks the output. Blocks data input when DQM active. (Byte masking) DQ0 ~ 63 Data Input/Output Data inputs/outputs are multiplexed on the same pins. VDD /V SS Power Supply/Ground Power and ground for the input buffers and the core logic. RAS low. CAS low. REV. 3 Mar. '98 KMM366S104CTL PC66 SDRAM MODULE FUNCTIONAL BLOCK DIAGRAM * CS0 DQM0 DQM4 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 LDQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 UDQM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CS U0 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 LDQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 UDQM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CS U2 * CS2 DQM2 DQM6 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 LDQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 UDQM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CS U1 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 LDQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 UDQM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CS U3 Serial PD A0 ~ An, BA0 SDRAM U0 ~ U3 RAS SDRAM U0 ~ U3 CAS SDRAM U0 ~ U3 WE SDRAM U0 ~ U3 CKE0 SDRAM U0 ~ U3 SCL A0 SDA A2 SA0 SA1 SA2 10 CLK0 * * * 10 DQn A1 10 Every DQpin of SDRAM U0 U1 U2 U3 10 VDD * * Vss * * CLK1/2/3 Two 0.33uF Capacitors per each SDRAM To all SDRAMs 10pF REV. 3 Mar. '98 KMM366S104CTL PC66 SDRAM MODULE ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to Vss V IN , VOUT -1.0 ~ 4.6 V Voltage on V DD supply relative to Vss VDD , V DDQ -1.0 ~ 4.6 V TSTG -55 ~ +150 C Storage temperature Power dissipation PD 4 W Short circuit current IOS 50 mA Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC OPERATING CONDITIONS AND CHARACTERISTICS Recommended operating conditions (Voltage referenced to V Parameter SS = 0V, T A = 0 to 70 C) Symbol Min Typ Max Unit Supply voltage V DD 3.0 3.3 3.6 V Note Input high votlage VIH 2.0 3.0 V DDQ +0.3 V 1 Input low voltage V IL -0.3 0 0.8 V 2 Output high voltage V OH 2.4 - - V IOH = -2mA Output low voltage VOL - - 0.4 V IOL = 2mA Input leakage current(Inputs) IIL -4 - 4 uA 3 Input leakage current (I/O pins) IIL -1.5 - 1.5 uA 3,4 Note : 1. V IH (max) = 5.6V AC. The overshoot voltage duration is 3ns. 2. V IL (min) = -2.0V AC. The undershoot voltage duration is 3ns. 3. Any input 0V VIN VDDQ. Input leakage currents include HI-Z output leakage for all bi-directional buffers with Tri-State outputs. 4. Dout is disabled, 0V V OUT V DDQ. CAPACITANCE (V DD = 3.3V, T A = 23C, f = 1MHz, V REF =1.4V 200 mV) Symbol Min Max Unit Input capacitance (A0 ~ A10/AP, BA0) Parameter CIN1 30 40 pF Input capacitance ( RAS, CAS, WE) CIN2 30 40 pF Input capacitance (CKE0) CIN3 25 35 pF Input capacitance (CLK0) CIN4 25 35 pF Input capacitance ( CS0, CS2) CIN5 15 25 pF Input capacitance (DQM0 ~ DQM7) CIN6 5 15 pF Data input/output capacitance (DQ0 ~ DQ63) C OUT 5 15 pF MAXIMUM TRACE LENGTHS Signal Max lengths Unit Signal Max lengths Unit A0 ~ A10/AP 8.0 BA0 8.0 inches CKE0 5.5 inches inches CS0, CS2 4.0 RAS inches 8.0 inches DQM0 ~ DQM7 3.0 inches CAS 8.0 inches DQ0 ~ DQ63 2.0 inches WE 8.0 inches REV. 3 Mar. '98 KMM366S104CTL PC66 SDRAM MODULE DC CHARACTERISTICS (Recommended operating condition unless otherwise noted, T Parameter Operating Current (One Bank Active) Symbol ICC1 A = 0 to 70 C) Test Condition CAS Latency Burst Length =1 t RC tRC (min) I OL = 0 mA Version 320 ICC2 P CKEV IL (max), t CC = 15ns 4 ICC2 PS CKE & CLK V IL(max), t CC = 4 ICC2 N CKEV IH (min), CSVIH (min), t CC = 15ns Input signals are changed one time during 30ns 60 ICC2 NS CKEV IH (min), CLK V IL (max), t CC = Input signals are stable 16 Active Standby Current in power-down mode ICC3 P CKEV IL (max), t CC = 15ns 8 ICC3 PS CKE & CLK V IL(max), t CC = 4 Active Standby Current in non power-down mode (One Bank Active) ICC3 N CKEV IH (min), CSVIH (min), t CC = 15ns Input signals are changed one time during 30ns ICC3 NS CKEV IH (min), CLK V IL (max), t CC = Input signals are stable Precharge Standby Current in power-down mode Precharge Standby Current in non power-down mode I OL = 0 mA Page Burst 2Banks Activated t CCD = 2CLKs Operating Current (Burst Mode) ICC4 Refresh Current ICC5 tRC tRC (min) Self Refresh Current ICC6 CKE0.2V Unit Note mA 1 -0 mA mA mA 100 mA 60 mA 3 460 2 400 mA 1 320 mA 2 4 mA Note : 1. Measured with outputs open. 2. Refresh period is 64ms. REV. 3 Mar. '98 KMM366S104CTL PC66 SDRAM MODULE AC OPERATING TEST CONDITIONS (VDD = 3.3V 0.3V, T A = 0 to 70 C) Parameter Input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition Value Unit 2.4 / 0.4 V 1.4 V tr / tf = 1 / 1 ns 1.4 V See Fig. 2 3.3V Vtt=1.4V 1200 * Output 50 VOH (DC) = 2.4V, I OH = -2mA VOL (DC) = 0.4V, I OL = 2mA * Output * Z0=50 50pF 870 50pF * (Fig. 1) DC Output Load Circuit (Fig. 2) AC Output Load Circuit OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) Parameter Symbol Version Unit Note -0 Row active to row active delay t RRD(min) 20 ns 1 RAS to CAS delay t RCD(min) 26 ns 1 Row precharge time t RP(min) 26 ns 1 t RAS(min) 50 ns 1 t RAS(max) 100 us ns 1 Row active time Row cycle time t RC(min) 80 Last data in to row precharge t RDL(min) 12 ns 2 Last data in to new col. address delay t CDL(min) 1 CLK 2 Last data in to burst stop t BDL(min) 1 CLK 2 Col. address to col. address delay t CCD(min) 1 CLK 3 ea 4 Number of valid output data CAS Latency=3 2 CAS Latency=2 1 Note : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. REV. 3 Mar. '98 KMM366S104CTL PC66 SDRAM MODULE AC CHARACTERISTICS (AC operating conditions unless otherwise noted) Refer to the individual componenet, not the whole module. Parameter -0 Symbol Min CLK cycle time CAS Latency=3 tCC CAS Latency=2 CLK to valid output delay CAS Latency=3 Output data hold time CAS Latency=3 10 Unit Note ns 1 ns 1, 2 ns 2 Max 1000 13 7 tSAC CAS Latency=2 8 tOH CAS Latency=2 3 3 CLK high pulse width tCH 3.5 ns 3 CLK low pulse width tCL 3.5 ns 3 Input setup time tSS 2.5 ns 3 Input hold time tSH 1 ns 3 CLK to output in Low-Z tSLZ 1 ns 2 CLK to output in Hi-Z CAS Latency=3 tSHZ CAS Latency=2 7 ns 8 Note : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf)=1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. REV. 3 Mar. '98 KMM366S104CTL PC66 SDRAM MODULE FREQUENCY vs. AC PARAMETER RELATIONSHIP TABLE KMM366S104CTL-G0 (Unit : number of clock) CAS Latency tRC tRAS tRP tRRD tRCD tCCD tCDL tRDL 80ns 50ns 26ns 20ns 26ns 10ns 10ns 12ns 100MHz (10.0ns) 3 8 5 3 2 3 1 1 2 83MHz (12.0ns) 3 7 5 3 2 3 1 1 1 75MHz (13.0ns) 2 7 4 2 2 2 1 1 1 66MHz (15.0ns) 2 6 4 2 2 2 1 1 1 60MHz (16.7ns) 2 5 3 2 2 2 1 1 1 Frequency REV. 3 Mar. '98 KMM366S104CTL PC66 SDRAM MODULE SIMPLIFIED TRUTH TABLE COMMAND Register Mode Register Set Auto Refresh Refresh Write & Column Address CS RAS CAS WE DQM H X L L L L X OP CODE L L L H X X Entry Self Refresh Exit Auto Precharge Disable H BA0 A10/AP L H L H H H H X X X X H X L L H H X V H X L H L H X V H X L H L L X H X L H H L X H X L L H L X V Auto Precharge Enable Entry H L H L H L H X X X L V V V X X X X H X X X L H H H H X X X L V V V 3 Row Address L Column Address (A 0~A 7) Column Address (A 0~A 7) H Both Banks Exit 3 3 L Entry 1, 2 X Auto Precharge Disable Clock Suspend or Active Power Down Note 3 H Bank Selection A9 ~ A0 L Auto Precharge Enable Burst Stop Precharge CKEn H Bank Active & Row Addr. Read & Column Address CKEn-1 X V L X H 4 4, 5 4 4, 5 6 X X X X X Precharge Power Down Mode X Exit L DQM H No Operation Command H H X X H X X X L H H H X V X X X 7 (V=Valid, X=Don t Care, H=Logic High, L=Logic Low) Note : 1. OP Code : Operand Code A 0 ~ A 10 /AP, BA 0 : Program keys. (@MRS) 2. MRS can be issued only at both banks precharge state. A new command can be issued after 2 clock cycle of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at both banks precharge state. 4. BA 0 : Bank select address. If "Low" at read, write, row active and precharge, bank A is selected. If "High" at read, write, row active and precharge, bank B is selected. If A 10 /AP is "High" at row precharge, BA 0 is ignored and both banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the assoiated bank can be issued at t RP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2) REV. 3 Mar. '98 KMM366S104CTL PC66 SDRAM MODULE PACKAGE DIMENSIONS Units : Inches (millimeters) 5.250 (133.350) 0.157 0.004 (4.000 0.100 ) 0.700 (17.780) 0.118 (3.000) B A 0.250 (6.350) 0.350 (8.890) 0.250 (6.350) 1.450 (36.830) 2.150 (54.61) 4.550 (115.57) 0.200 Min .450 (11.430) C 0.100Max (2.54Max) (5.08 Min) .118DIA .004 (3.000DIA .100) 0.100Min (2.540Min) 1.000 (25.40) R 0.079 (R 2.000) 0.054 (1.372) 5.014 (127.350) 0.118 (3.000) 0.100 Min 0.250 (6.350 ) 0.250 (6.350 ) 0.123 .005 (3.125 .125) 0.079 .004 (2.000 .100) Detail A (2.540 Min) 0.050 0.0039 (1.270 0.10) 0.039 .002 (1.000 .050) 0.123 .005 (3.125 .125) 0.079 .004 (2.000 .100) Detail B 0.010Max (0.250 Max) 0.050 (1.270 ) Detail C Tolerances : .005(.13) unless otherwise specified The used device is 1Mx16 SDRAM, TSOP SDRAM Part No. : KM416S1020CT REV. 3 Mar. '98