ADS ADS 780 ADS7805 780 5 5 SBAS020D - JANUARY 1996 - REVISED OCTOBER 2006 16-Bit, 10s Sampling, CMOS ANALOG-to-DIGITAL CONVERTER FEATURES DESCRIPTION The ADS7805 is a complete 16-bit sampling, Analog-toDigital (A/D) converter using state-of-the-art CMOS structures. It contains a complete 16-bit, capacitor-based, Successive Approximation Register (SAR) A/D converter with Sample-and-Hold (S/H), reference, clock, interface for microprocessor use, and 3-state output drivers. 100kHz min SAMPLING RATE STANDARD 10V INPUT RANGE 86dB min SINAD WITH 20kHz INPUT 3.0 LSB max INL DNL: 16 Bits No Missing Codes SINGLE +5V SUPPLY OPERATION PIN-COMPATIBLE WITH 12-BIT ADS7804 USES INTERNAL OR EXTERNAL REFERENCE FULL PARALLEL DATA OUTPUT 100mW max POWER DISSIPATION 0.3" DIP-28 AND SO-28 The ADS7805 is specified at a 100kHz sampling rate and ensured over the full temperature range. Laser-trimmed scaling resistors provide an industry-standard 10V input range while the innovative design allows operation from a single +5V supply, with power dissipation under 100mW. The ADS7805 is available in a 0.3" DIP-28 and an SO-28 package. Both are fully specified for operation over the industrial -25C to +85C range; however, they will function over the -40C to +85C temperature range. Clock Successive Approximation Register and Control Logic R/C CS BYTE BUSY CDAC 20k 10V Input 10k 4k Comparator Output Latches and 3-State Drivers 3-State Parallel Data Bus CAP Buffer Internal +2.5V Ref 4k REF Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright (c) 1996-2006, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS(1) Analog Inputs: VIN ............................................................................. 25V REF .................................................. +VANA + 0.3V to AGND2 - 0.3V CAP .................. Indifinite Short to AGND2 Momentary Short to VANA Ground Voltage Differences: DGND, AGND1, AGND2 ................... 0.3V VANA ....................................................................................................... 7V VDIG to VANA ...................................................................................... +0.3V VDIG ........................................................................................................ 7V Digital Inputs .......................................................... -0.3V to +VDIG + 0.3V Maximum Junction Temperature ................................................... +165C Internal Power Dissipation ............................................................. 825mW Lead Temperature (soldering, 10s) ............................................... +300C This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. NOTE: (1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. PACKAGE/ORDERING INFORMATION(1) PRODUCT MAXIMUM LINEARITY ERROR (LSB) MINIMUM SIGNAL-TO(NOISE + DISTORTION) RATIO (dB) ADS7805P 4 ADS7805PB 3 ADS7805U PACKAGE-LEAD PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE PACKAGE MARKING 83 DIP-28 NT -25C to +85C 86 DIP-28 NT -25C to +85C 4 83 SO-28 DW ADS7805U 4 83 SO-28 ADS7805UB 3 86 ADS7805UB 3 86 ORDERING NUMBER TRANSPORT MEDIA, QUANTITY NT ADS7805P Tube, 13 NT ADS7805PB Tube, 13 -25C to +85C DW ADS7805U Tube, 28 DW -25C to +85C DW ADS7805U/1K Tape and Reel, 1000 SO-28 DW -25C to +85C DW ADS7805UB Tube, 28 SO-28 DW -25C to +85C DW ADS7805UB/1K Tape and Reel, 1000 NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. ELECTRICAL CHARACTERISTICS TA = -25C to +85C, fS = 100kHz, VDIG = VANA = +5V, using internal reference, unless otherwise specified. ADS7805P, U PARAMETER CONDITIONS MIN TYP RESOLUTION DC ACCURACY Integral Linearity Error No Missing Codes Transition Noise(2) Full-Scale Error(3,4) Full-Scale Error Drift Full-Scale Error(3,4) Full-Scale Error Drift Bipolar Zero Error(3) Bipolar Zero Error Drift Power Supply Sensitivity (VDIG = VANA = VD) AC ACCURACY Spurious-Free Dynamic Range Total Harmonic Distortion Signal-to-(Noise+Distortion) Signal-to-Noise Full-Power Bandwidth(6) SAMPLING DYNAMICS Aperture Delay Transient Response Overvoltage Recovery(7) 2 MIN TYP 16 ANALOG INPUT Voltage Ranges Impedance Capacitance THROUGHPUT SPEED Conversion Cycle Throughput Rate ADS7805PB, UB MAX 10 23 35 Acquire and Convert 10 16 Bits V k pF 10 s kHz 3 LSB(1) Bits LSB % ppm/C % ppm/C mV ppm/C LSB 100 4 15 16 1.3 7 2 2 +4.75V < VD < +5.25V fIN = 20kHz fIN = 20kHz fIN = 20kHz -60dB Input fIN = 20kHz UNITS 10 23 35 100 Ext. 2.5000V Ref Ext. 2.5000V Ref MAX 1.3 0.5 5 0.5 2 10 2 8 90 0.25 0.25 10 8 94 -90 83 -94 86 30 32 83 86 250 250 40 FS Step 40 2 150 2 150 dB(5) dB dB dB dB kHz ns s ns ADS7805 www.ti.com SBAS020D ELECTRICAL CHARACTERISTICS (Cont.) TA = -25C to +85C, fS = 100kHz, VDIG = VANA = +5V, using internal reference, unless otherwise specified. ADS7805P, U PARAMETER CONDITIONS REFERENCE Internal Reference Voltage Int. Ref. Source Current (must use external buffer) Internal Reference Drift Ext. Ref. Voltage Range for Specified Linearity External Reference Current Drain Ext. 2.5000V Ref DIGITAL OUTPUTS Data Format Data Coding VOL VOH Leakage Current Output Capacitance TYP MAX MIN TYP MAX UNITS 2.48 2.5 1 8 2.5 2.52 2.48 2.52 2.7 100 2.3 2.5 1 8 2.5 2.7 100 V A ppm/C V A +0.8 VD + 0.3V 10 10 -0.3 +2.0 +0.8 VD + 0.3V 10 10 V V A A +0.4 2.3 DIGITAL INPUTS Logic Levels VIL VIH IIL IIH -0.3 +2.0 Parallel 16 Bits Binary Two's Complement ISINK = 1.6mA ISOURCE = 500A High-Z State, VOUT = 0V to VDIG High-Z State +0.4 TEMPERATURE RANGE Specified Performance Operating Temperature(8) Derated Performance Storage Thermal Resistance (JA) DIP-28 SO-28 Must be VANA 5 15 5 15 V V A pF 83 83 83 83 ns ns +5.25 +5.25 100 V V mA mA mW +85 +85 +125 +150 C C C C +4 +4 DIGITAL TIMING Bus Access Time Bus Relinquish Time POWER SUPPLIES Specified Performance VDIG VANA IDIG IANA Power Dissipation ADS7805PB, UB MIN +4.75 +4.75 +5 +5 0.3 16 fS = 100kHz +5.25 +5.25 +4.75 +4.75 +5 +5 0.3 16 100 -25 -40 -55 -65 +85 +85 +125 +150 75 75 -25 -40 -55 -65 75 75 C/W C/W NOTES: (1) LSB means Least Significant Bit. For the 16-bit, 10V input ADS7805, one LSB is 305V. (2) Typical rms noise at worst case transitions and temperatures. (3) As measured with fixed resistors, see Figure 4. Adjustable to zero with external potentiometer. (4) Full-scale error is the worst case of -Full Scale or +Full Scale untrimmed deviation from ideal first and last code transitions, divided by the transition voltage (not divided by the full-scale range) and includes the effect of offset error. (5) All specifications in dB are referred to a full-scale 10V input. (6) Full-Power Bandwidth defined as Full-Scale input frequency at which Signal-to-(Noise + Distortion) degrades to 60dB, or 10 bits of accuracy. (7) Recovers to specified performance after 2 * FS input overvoltage. (8) Functionality test at -40C. ADS7805 SBAS020D www.ti.com 3 PIN CONFIGURATION VIN 1 28 VDIG AGND1 2 27 VANA REF 3 26 BUSY CAP 4 25 CS AGND2 5 24 R/C D15 (MSB) 6 23 BYTE D14 7 22 D0 (LSB) ADS7805 DIGITAL I/O D13 8 21 D1 D12 9 20 D2 D11 10 19 D3 D10 11 18 D4 D9 12 17 D5 D8 13 16 D6 DGND 14 15 D7 PIN # NAME 1 VIN DESCRIPTION 2 AGND1 3 REF Reference Input/Output. 2.2F tantalum capacitor to ground. Reference Buffer Capacitor. 2.2F tantalum capacitor to ground. Analog Input. See Figure 7. Analog Ground. Used internally as ground reference point. 4 CAP 5 AGND2 6 D15 (MSB) O Data Bit 15. Most Significant Bit (MSB) of conversion results. Hi-Z state when CS is HIGH, or when R/C is LOW. 7 D14 O Data Bit 14. Hi-Z state when CS is HIGH, or when R/C is LOW. 8 D13 O Data Bit 13. Hi-Z state when CS is HIGH, or when R/C is LOW. 9 D12 O Data Bit 12. Hi-Z state when CS is HIGH, or when R/C is LOW. 10 D11 O Data Bit 11. Hi-Z state when CS is HIGH, or when R/C is LOW. 11 D10 O Data Bit 10. Hi-Z state when CS is HIGH, or when R/C is LOW. 12 D9 O Data Bit 9. Hi-Z state when CS is HIGH, or when R/C is LOW. 13 D8 O Data Bit 8. Hi-Z state when CS is HIGH, or when R/C is LOW. 14 DGND 15 D7 O Data Bit 7. Hi-Z state when CS is HIGH, or when R/C is LOW. 16 D6 O Data Bit 6. Hi-Z state when CS is HIGH, or when R/C is LOW. 17 D5 O Data Bit 5. Hi-Z state when CS is HIGH, or when R/C is LOW. 18 D4 O Data Bit 4. Hi-Z state when CS is HIGH, or when R/C is LOW. 19 D3 O Data Bit 3. Hi-Z state when CS is HIGH, or when R/C is LOW. 20 D2 O Data Bit 2. Hi-Z state when CS is HIGH, or when R/C is LOW. 21 D1 O Data Bit 1. Hi-Z state when CS is HIGH, or when R/C is LOW. 22 D0 (LSB) O Data Bit 0. Least Significant Bit (LSB) of conversion results. Hi-Z state when CS is HIGH, or when R/C is LOW. 23 BYTE I Selects 8 most significant bits (LOW) or 8 least significant bits (HIGH). 24 R/C I With CS LOW and BUSY HIGH, a Falling Edge on R/C Initiates a new conversion. With CS LOW, a rising edge on R/C enables the parallel output. Analog Ground Digital Ground 25 CS I Internally OR'd with R/C. If R/C LOW, a falling edge on CS initiates a new conversion. 26 BUSY O At the start of a conversion, BUSY goes LOW and stays LOW until the conversion is completed and the digital outputs have been updated. 27 VANA Analog Supply Input. Nominally +5V. Decouple to ground with 0.1F ceramic and 10F tantalum capacitors. 28 VDIG Digital Supply Input. Nominally +5V. Connect directly to pin 27. Must be VANA. TABLE I. Pin Assignments. 4 ADS7805 www.ti.com SBAS020D TYPICAL CHARACTERISTICS TA = +25C, fS = 100kHz, VDIG = VANA = +5V, using internal reference and fixed resistors shown in Figure 6b, unless otherwise specified. FREQUENCY SPECTRUM (8192 Point FFT; fIN = 45kHz, 0dB) 0 0 -20 -20 -40 -40 Amplitude (dB) Amplitude (dB) FREQUENCY SPECTRUM (8192 Point FFT; fIN = 20kHz, 0dB) -60 -80 -100 -60 -80 -100 -120 -120 -140 -140 0.0 12.5 25.0 37.5 50.0 0.0 25.0 37.5 50.0 Frequency (kHz) SIGNAL-TO-(NOISE + DISTORTION) vs INPUT FREQUENCY AND INPUT AMPLITUDE SIGNAL-TO-(NOISE + DISTORTION) vs TEMPERATURE (fIN = 20kHz, 0dB; fS = 50kHz, 100kHz) 100.0 90 0dB 80 95.0 70 -20dB 60 SINAD (dB) SINAD (dB) 12.5 Frequency (kHz) 50 40 30 50kHz 90.0 85.0 100kHz -60dB 20 80.0 10 75.0 0 0 5 10 15 20 25 30 35 40 -50 45 -25 0 Input Signal Frequency (kHz) 105 -85 16-Bit LSBs -80 SFDR 100 -90 -95 THD 90 85 -105 SINAD 80 -110 -25 0 25 50 75 Temperature (C) 100 125 150 All Codes INL 8192 16384 24576 32768 40960 49152 57344 65535 Decimal Code -100 SNR -50 3 2 1 0 -1 -2 -3 0 125 150 16-Bit LSBs 95 100 LINEARITY vs CODE 110 THD (dB) SFDR, SNR, and SINAD (dB) AC PARAMETERS vs TEMPERATURE (fIN = 20kHz, 0dB) 25 50 75 Temperature (C) 3 2 1 0 -1 -2 -3 All Codes DNL 0 8192 16384 24576 32768 40960 49152 57344 65535 Decimal Code ADS7805 SBAS020D www.ti.com 5 TYPICAL CHARACTERISTICS (Cont.) TA = +25C, fS = 100kHz, VDIG = VANA = +5V, using internal reference and fixed resistors shown in Figure 6b, unless otherwise specified. CONVERSION TIME vs TEMPERATURE 8.0 2.515 7.9 2.510 7.8 Conversion Time (s) Internal Reference (V) INTERNAL REFERENCE VOLTAGE vs TEMPERATURE 2.520 2.505 2.500 2.495 2.490 7.7 7.6 7.5 7.4 7.3 2.485 2.480 7.2 -50 -25 0 25 50 75 100 125 -50 150 -25 0 25 50 75 100 125 150 Temperature (C) Temperature (C) BPZ ERROR (INTERNAL REFERENCE) mV From Ideal 8 4 0 -4 -8 ENDPOINT ERRORS (EXTERNAL REFERENCE) Percent From Ideal 0.2 +FS Error 0.1 0.0 -0.1 -0.2 ENDPOINT ERRORS (EXTERNAL REFERENCE) Percent From Ideal 0.2 -FS Error 0.1 0.0 -0.1 -0.2 -50 -25 0 25 50 75 100 125 150 Temperature (C) 6 ADS7805 www.ti.com SBAS020D BASIC OPERATION Table II for a summary of CS, R/C, and BUSY states and Figures 3 through 5 for timing diagrams. Figure 1 shows a basic circuit to operate the ADS7805 with a full parallel data output. Taking R/C (pin 24) LOW for a minimum of 40ns (7s max) will initiate a conversion. BUSY (pin 26) will go LOW and stay LOW until the conversion is completed and the output registers are updated. Data will be output in Binary Two's Complement with the MSB on pin 6. BUSY going HIGH can be used to latch the data. All convert commands will be ignored while BUSY is LOW. The ADS7805 will begin tracking the input signal at the end of the conversion. Allowing 10s between convert commands assures accurate acquisition of a new signal. The offset and gain are adjusted internally to allow external trimming with a single supply. The external resistors compensate for this adjustment and can be left out if the offset and gain will be corrected in software (refer to the "Calibration" section). CS and R/C are internally OR'd and level triggered. There is not a requirement which input goes LOW first when initiating a conversion. If, however, it is critical that CS or R/C initiates conversion `n', be sure the less critical input is LOW at least 10ns prior to the initiating input. To reduce the number of control pins, CS can be tied LOW using R/C to control the read and convert modes. This will have no effect when using the internal data clock in the serial output mode. However, the parallel output will become active whenever R/C goes HIGH. Refer to the "Reading Data" section. CS R/C BUSY 1 X X None. Databus is in Hi-Z state. 0 1 Initiates conversion "n". Databus remains in Hi-Z state. 0 1 Initiates conversion "n". Databus enters Hi-Z state. 0 1 Conversion "n" completed. Valid data from conversion "n" on the databus. 1 1 Enables databus with valid data from conversion "n". 1 0 Enables databus with valid data from conversion "n-1"(1). Conversion n in progress. 0 0 Enables databus with valid data from conversion "n-1"(1). Conversion "n" in progress. 0 0 New conversion initiated without acquisition of a new signal. Data will be invalid. CS and/or R/C must be HIGH when BUSY goes HIGH. X X 0 New convert commands ignored. Conversion "n" in progress. STARTING A CONVERSION The combination of CS (pin 25) and R/C (pin 24) LOW for a minimum of 40ns immediately puts the sample-and-hold of the ADS7805 in the hold state and starts conversion `n'. BUSY (pin 26) will go LOW and stay LOW until conversion `n' is completed and the internal output register has been updated. All new convert commands during BUSY LOW will be ignored. CS and/or R/C must go HIGH before BUSY goes HIGH or a new conversion will be initiated without sufficient time to acquire a new signal. The ADS7805 will begin tracking the input signal at the end of the conversion. Allowing 10s between convert commands assures accurate acquisition of a new signal. Refer to OPERATION NOTE: (1) See Figures 3 and 4 for constraints on data valid from conversion "n-1". Table II. Control Line Functions for "Read" and "Convert". 200 33.2k + 1 28 2 27 2.2F 3 26 4 25 5 24 B15 (MSB) 6 23 B14 7 + + 0.1F + +5V 10F BUSY 2.2F R/C 22 B0 (LSB) ADS7805 B13 8 21 B1 B12 9 20 B2 B11 10 19 B3 B10 11 18 B4 B9 12 17 B5 B8 13 16 B6 14 15 B7 Convert Pulse 40ns min 6s max FIGURE 1. Basic Operation. ADS7805 SBAS020D www.ti.com 7 READING DATA PARALLEL OUTPUT (During a Conversion) The ADS7805 outputs full or byte-reading parallel data in Binary Two's Complement data output format. The parallel output will be active when R/C (pin 24) is HIGH and CS (pin 25) is LOW. Any other combination of CS and R/C will tristate the parallel output. Valid conversion data can be read in a full parallel, 16-bit word or two 8-bit bytes on pins 6-13 and pins 15-22. BYTE (pin 23) can be toggled to read both bytes within one conversion cycle. Refer to Table III for ideal output codes and Figure 2 for bit locations relative to the state of BYTE. DIGITAL OUTPUT BINARY TWO'S COMPLEMENT DESCRIPTION ANALOG INPUT Full-Scale Range 10V Least Significant Bit (LSB) 305V +Full Scale (10V - 1LSB) Mid-scale One LSB below Mid-scale -Full Scale BINARY CODE After conversion `n' has been initiated, valid data from conversion `n - 1' can be read and will be valid up to 7s after the start of conversion `n'. Do not attempt to read data from 7s after the start of conversion `n' until BUSY (pin 26) goes HIGH; this may result in reading invalid data. Refer to Table IV and Figures 3 to 5 for timing specifications. Note! For the best possible performance, data should not be read during a conversion. The switching noise of the asynchronous data transfer can cause digital feedthrough degrading the converter's performance. The number of control lines can be reduced by tying CS LOW while using R/C to initiate conversions and activate the output mode of the converter (see Figure 3). HEX CODE SYMBOL DESCRIPTION t1 Convert Pulse Width MIN TYP MAX UNITS 7000 ns Data Valid Delay after R/C LOW 8 s 65 8 ns s 40 9.999695V 0111 1111 1111 1111 7FFF t2 0V 0000 0000 0000 0000 0000 t3 t4 BUSY Delay from R/C LOW BUSY LOW -305V 1111 1111 1111 1111 FFFF t5 BUSY Delay after End of Conversion -10V 1000 0000 0000 0000 8000 t6 Aperture Delay 40 t7 Conversion Time 7.6 8 s 2 s 83 ns Table III. Ideal Input Voltages and Output Codes. PARALLEL OUTPUT (After a Conversion) After conversion `n' is completed and the output registers have been updated, BUSY (pin 26) will go HIGH. Valid data from conversion `n' will be available on D15-D0 (pins 6-13 and 15-22). BUSY going HIGH can be used to latch the data. Refer to Table IV and Figures 3 to 5 for timing specifications. 220 t8 Acquisition Time t9 Bus Relinquish Time 10 35 50 ns ns t10 BUSY Delay after Data Valid 200 ns t11 Previous Data Valid after R/C LOW 7.4 s t7 + t6 Throughput Time 9 10 s t12 R/C to CS Setup Time 10 ns t13 Time Between Conversions 10 s t14 Bus Access Time and BYTE Delay 10 83 ns TABLE IV. Conversion Timing. BYTE LOW BYTE HIGH +5V Bit 15 (MSB) 6 Bit 14 7 23 Bit 7 6 22 Bit 0 (LSB) Bit 6 7 ADS7805 23 22 Bit 8 ADS7805 Bit 13 8 21 Bit 1 Bit 5 8 21 Bit 9 Bit 12 9 20 Bit 2 Bit 4 9 20 Bit 10 Bit 11 10 19 Bit 3 Bit 3 10 19 Bit 11 Bit 10 11 18 Bit 4 Bit 2 11 18 Bit 12 Bit 9 12 17 Bit 5 Bit 1 12 17 Bit 13 Bit 8 13 16 Bit 6 Bit 0 (LSB) 13 16 Bit 14 14 15 Bit 7 14 15 Bit 15 (MSB) FIGURE 2. Bit Locations Relative to State of BYTE (pin 23). 8 ADS7805 www.ti.com SBAS020D t1 R/C t13 t2 t4 BUSY t3 t6 MODE DATA BUS t5 Acquire Previous Data Valid Convert Acquire t7 t8 Previous Data Valid Hi-Z t9 Not Valid Convert Hi-Z Data Valid Data Valid t10 t11 FIGURE 3. Conversion Timing with Outputs Enabled after Conversion (CS Tied LOW). t12 t12 t12 t12 R/C t1 CS t3 t4 BUSY t6 MODE Convert Acquire Acquire t7 Hi-Z State DATA BUS Data Valid Hi-Z State t9 t14 FIGURE 4. Using CS to Control Conversion and Read Timing. t12 t12 R/C CS BYTE Pins 6-13 Hi-Z High Byte t14 Pins 15-22 Hi-Z Low Byte Low Byte t14 High Byte Hi-Z t9 Hi-Z FIGURE 5. Using CS and BYTE to Control Data Bus. ADS7805 SBAS020D www.ti.com 9 INPUT RANGES SOFTWARE CALIBRATION The ADS7805 offers a standard 10V input range. Figure 6 shows the necessary circuit connections for the ADS7805 with and without hardware trim. Offset and full-scale error(1) specifications are tested and specified with the fixed resistors shown in Figure 6b. Adjustments for offset and gain are described in the "Calibration" section of this data sheet. To calibrate the offset and gain of the ADS7805 in software, no external resistors are required. See the "No Calibration" section for details on the effects of the external resistors. Range of offset and gain errors with and without external resistors is shown in Table V. The offset and gain are adjusted internally to allow external trimming with a single supply. The external resistors compensate for this adjustment and can be left out if the offset and gain will be corrected in software (refer to the "Calibration" section). NO CALIBRATION The nominal input impedance of 23k results from the combination of the internal resistor network shown on the front page of the product data sheet and the external resistors. The input resistor divider network provides inherent overvoltage protection ensured to at least 25V. The 1% resistors used for the external circuitry do not compromise the accuracy or drift of the converter. They have little influence relative to the internal resistors, and tighter tolerances are not required. Figure 6b shows circuit connections. The external resistors shown in Figure 6b may not be necessary in some applications. These resistors provide compensation for an internal adjustment of the offset and gain which allows calibration with a single supply. The nominal transfer function of the ADS7805 will be bound by the shaded region (see Figure 7) with a typical offset of -30mV and a typical gain error of -1.5%. Refer to Table V for range of offset and gain errors with and without external resistors. WITH EXTERNAL RESISTORS WITHOUT EXTERNAL RESISTORS UNITS BP0 -10 < BPO < 10 -30 < BPO < 30 -50 < BPO < -15 -150 < BPO < -45 mV LSBs Gain Error -0.5 < error < 0.5 -2 < error < -1 % of FSR NOTE: (1) Full-scale error includes offset and gain errors measured at both +FS and -FS. CALIBRATION The ADS7805 can be trimmed in hardware or software. The offset should be trimmed before the gain since the offset directly affects the gain. To achieve optimum performance, several iterations may be required. TABLE V. Offset and Gain Errors With and Without External Resistors. HARDWARE CALIBRATION To calibrate the offset and gain of the ADS7805, install the proper resistors and potentiometers as shown in Figure 6a. The calibration range is 15mV for the offset and 60mV for the gain. 10V With Hardware a) 10V Without Hardware b) Trim Trim 200 1 10V 2 33.2k +5V 2.2F 50k Offset 50k + 3 200 1 10V VIN 2 AGND1 33.2k 2.2F + 3 REF VIN AGND1 REF 576k 4 Gain 2.2F 4 CAP + 2.2F 5 5 AGND2 CAP + AGND2 NOTE: Use 1% metal film resistors. FIGURE 6. Circuit Diagram With and Without External Resistors. 10 ADS7805 www.ti.com SBAS020D Digital Output 7FFF -10V -9.99983V -9.9998V -50mV 9.9997V -15mV 9.999815V +10V Analog Input Ideal Transfer Function With External Resistors Range of Transfer Function Without External Resistors 8000 FIGURE 7. Full-Scale Transfer Function. REFERENCE CAP The ADS7805 can operate with its internal 2.5V reference or an external reference. By applying an external reference to pin 5, the internal reference can be bypassed. The reference voltage at REF is buffered internally with the output on CAP (pin 4). The internal reference has an 8 ppm/C drift (typical) and accounts for approximately 20% of the full-scale error (FSE = 0.5% for low grade, 0.25% for high grade). REF REF (pin 3) is an input for an external reference or the output for the internal 2.5V reference. A 2.2F capacitor should be connected as close to the REF pin as possible. The capacitor and the output resistance of REF create a low-pass filter to bandlimit noise on the reference. Using a smaller value capacitor will introduce more noise to the reference degrading the SNR and SINAD. The REF pin should not be used to drive external AC or DC loads. CAP (pin 4) is the output of the internal reference buffer. A 2.2F capacitor should be placed as close to the CAP pin as possible to provide optimum switching currents for the CDAC throughout the conversion cycle and compensation for the output of the internal buffer. Using a capacitor any smaller than 1F can cause the output buffer to oscillate and may not have sufficient charge for the CDAC. Capacitor values larger than 2.2F will have little effect on improving performance. The output of the buffer is capable of driving up to 2mA of current to a DC load. DC loads requiring more than 2mA of current from the CAP pin will begin to degrade the linearity of the ADS7805. Using an external buffer will allow the internal reference to be used for larger DC loads and AC loads. Do not attempt to directly drive an AC load with the output voltage on CAP. This will cause performance degradation of the converter. The range for the external reference is 2.3V to 2.7V and determines the actual LSB size. Increasing the reference voltage will increase the full-scale range and the LSB size of the converter which can improve the SNR. ADS7805 SBAS020D www.ti.com 11 LAYOUT SIGNAL CONDITIONING POWER For optimum performance, tie the analog and digital power pins to the same +5V power supply and tie the analog and digital grounds together. As noted in the electrical specifications, the ADS7805 uses 90% of its power for the analog circuitry. The ADS7805 should be considered as an analog component. The +5V power for the A/D converter should be separate from the +5V used for the system's digital logic. Connecting VDIG (pin 28) directly to a digital supply can reduce converter performance due to switching noise from the digital logic. For best performance, the +5V supply can be produced from whatever analog supply is used for the rest of the analog signal conditioning. If +12V or +15V supplies are present, a simple +5V regulator can be used. Although it is not suggested, if the digital supply must be used to power the converter, be sure to properly filter the supply. Either using a filtered digital supply or a regulated analog supply, both VDIG and VANA should be tied to the same +5V source. GROUNDING Three ground pins are present on the ADS7805. DGND is the digital supply ground. AGND2 is the analog supply ground. AGND1 is the ground which all analog signals internal to the A/D converter are referenced. AGND1 is more susceptible to current induced voltage drops and must have the path of least resistance back to the power supply. The FET switches used for the sample-and-hold on many CMOS A/D converters release a significant amount of charge injection which can cause the driving op amp to oscillate. The FET switch on the ADS7805, compared to the FET switches on other CMOS A/D converters, releases 5%-10% of the charge. There is also a resistive front end which attenuates any charge which is released. The end result is a minimal requirement for the anti-alias filter on the front end. Any op amp sufficient for the signal in an application will be sufficient to drive the ADS7805. The resistive front end of the ADS7805 also provides an ensured 25V overvoltage protection. In most cases, this eliminates the need for external input protection circuitry. INTERMEDIATE LATCHES The ADS7805 does have tri-state outputs for the parallel port, but intermediate latches should be used if the bus will be active during conversions. If the bus is not active during conversion, the tri-state outputs can be used to isolate the A/D converter from other peripherals on the same bus. Tristate outputs can also be used when the A/D converter is the only peripheral on the data bus. Intermediate latches are beneficial on any monolithic A/D converter. The ADS7805 has an internal LSB size of 38V. Transients from fast switching signals on the parallel port, even when the A/D converter is tri-stated, can be coupled through the substrate to the analog circuitry causing degradation of converter performance. All the ground pins of the A/D converter should be tied to the analog ground plane, separated from the system's digital logic ground, to achieve optimum performance. Both analog and digital ground planes should be tied to the "system" ground as near to the power supplies as possible. This helps to prevent dynamic digital ground currents from modulating the analog ground through a common impedance to power ground. 12 ADS7805 www.ti.com SBAS020D Revision History DATE REVISION PAGE 10/06 D 3 8/06 C 2 SECTION Absolute Maximum Ratings DESCRIPTION CAP and REF were switched. Package/Ordering Information Corrected typos in ordering table. NOTE: Page numbers for previous revisions may differ from page numbers in the current version. ADS7805 SBAS020D www.ti.com 13 PACKAGE OPTION ADDENDUM www.ti.com 21-May-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) ADS7805P NRND PDIP NT 28 13 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type ADS7805PB NRND PDIP NT 28 13 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type ADS7805PBG4 NRND PDIP NT 28 13 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type ADS7805PG4 NRND PDIP NT 28 13 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type ADS7805U NRND SOIC DW 28 20 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS7805U/1K NRND SOIC DW 28 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS7805U/1KE4 NRND SOIC DW 28 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS7805UB NRND SOIC DW 28 20 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS7805UB/1K NRND SOIC DW 28 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS7805UB/1KE4 NRND SOIC DW 28 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS7805UBE4 NRND SOIC DW 28 20 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS7805UBG4 NRND SOIC DW 28 20 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS7805UE4 NRND SOIC DW 28 20 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS7805UG4 NRND SOIC DW 28 20 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 1 Samples (Requires Login) PACKAGE OPTION ADDENDUM www.ti.com 21-May-2010 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADS7805U/1K SOIC DW 28 1000 330.0 32.4 11.35 18.67 3.1 16.0 32.0 Q1 ADS7805UB/1K SOIC DW 28 1000 330.0 32.4 11.35 18.67 3.1 16.0 32.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS7805U/1K SOIC DW 28 1000 367.0 367.0 55.0 ADS7805UB/1K SOIC DW 28 1000 367.0 367.0 55.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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