EL1503ACLZ-T13 - Intersil - Datasheet.Directory

FN7039.2

EL1503A

High Power Differential Line Driver

The EL1503A ADSL Line Driver contains two wideband

high-voltage drivers which are ideally suited for both ADSL

and HDSL2 applications. They can supply a 39.2VP-P signal

into a 22Ω load while exhibiting very low distortion. T he

EL1503A also has a number of power saving features. The

IADJ pin can be used to set the maximum supply current and

the C0 and C1 pins can be us ed to digitally vary the supply

current to one of four modes. These modes include full

power, low power, terminate only and power down.

The EL1503A uses current-feedback type amplifiers, which

achieve a high slew rate while consuming moderate power.

They retain their frequency response over a wide range of

externally set gains. The EL1503A operates on ±5V to ±12V

supplies and consumes only 12.5mA per amplifier.

The device is supplied in a thermally-en hanced 20 Ld SOIC

(0.300”) and the small footprint (4x5mm) 24 Ld QFN

packages. Center pins on each side of the 20 Ld and 16 Ld

packages are used as ground connections and heat

spreaders. The QFN package has the potential for a low θJA

(<40°C/W) and dissipates heat by means of a thermal pad

that is soldered onto the PCB. All package options are

specified for operation over the full -40°C to +85°C

temperature range.

Features

• High power ADSL driver

•39.2V

P-P differential output drive into 22Ω

•42.4V

P-P differential output drive into 65Ω

• Driver 2nd/3rd harmonics of

-66dBc/-72dBc at 2VP-P into 100Ω differential

• Supply current of 12.5mA per amplifier

• Supply current control

• Power saving modes

• Standard surface-mount packages

• Ultra-small QFN package

• Pb-free plus anneal available (RoHS compliant)

Applications

• ADSL line drivers

• HDSL2 line drivers

• Video distribution amplifiers

Pinouts EL1503A

(24 LD QFN)

TOP VIEW

EL1503A

[20 LD SOIC (0.300”)]

TOP VIEW

*GND pins are heat spreaders

THERMAL

PAD

VS-

GND

VS+

GND

VOUTA

VIN-A

VIN-B

VOUTB

VIN+A

IADJ

VIN+B

-+ -+

POWER

CONTROL

LOGIC

VIN-A

VOUTA

VS-

GND*

VIN+A

VIN-B

VS+

GND*

IADJ

VOUTB

GND*

VIN+B

Data Sheet March 26, 2007

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

2FN7039.2

March 26, 2007

Ordering Information

PART NUMBER PART MARKING TAPE & REEL PACKAGE PKG. DWG. #

EL1503ACM EL1503ACM - 20 Ld SOIC (0.300") MDP0027

EL1503ACM-T13 EL1503ACM 13” 20 Ld SOIC (0.300") MDP0027

EL1503ACMZ (See Note) EL1503ACMZ - 20 Ld SOIC (0.300") (Pb-Free) MDP0027

EL1503ACMZ-T13 (See Note) EL1503ACMZ 13” 20 Ld SOIC (0.300") (Pb-Free) MDP0027

EL1503ACL 1503ACL - 24 Ld QFN MDP0046

EL1503ACL-T7 1503ACL 7” 24 Ld QFN MDP0046

EL1503ACL-T13 1503ACL 13” 24 Ld QFN MDP0046

EL1503ACLZ (See Note) 1503ACLZ - 24 Ld QFN (Pb-Free) MDP0046

EL1503ACLZ-T7 (See Note) 1503ACLZ 7” 24 Ld QFN (Pb-Free) MDP0046

EL1503ACLZ-T13 (See Note) 1503ACLZ 13” 24 Ld QFN (Pb-Free) MDP0046

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate

termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL

classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

EL1503A

3FN7039.2

March 26, 2007

Absolute Maximum Ratings (TA = +25°C)

VS+ to VS- Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28V

VS+ Voltage to Ground . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +28V

VS- Voltage to Ground. . . . . . . . . . . . . . . . . . . . . . . . . .-28V to 0.3V

Input C0/C1 to Ground. . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +7V

Driver VIN+ Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VS- to VS+

Current into any Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8mA

Output Current from Driver (static) . . . . . . . . . . . . . . . . . . . . 100mA

Operating Temperature Range . . . . . . . . . . . . . . . . .-40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . . . . . . .-60°C to +150°C

Operating Junction Temperature . . . . . . . . . . . . . . .-40°C to +150°C

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests

are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA

Electrical Specifications VS = ±12V, RF = 1.5kΩ, RL= 65Ω, IADJ = C0 = C1 = 0V, TA = +25°C. Amplifiers tested separately.

PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT

SUPPLY CHARACTERISTICS

IS+(Full Pow er ) Positive Supply Current per Amplifier All outputs at 0V, C0 = C1 = 0V 10 12.5 16 mA

IS-(Full Power) Negative Supply Current per Amplifier All outputs at 0V, C0 = C1 = 0V -15 -11.5 -9 mA

IS+(Low Power) Positive Supply Current per Amplifier All outputs at 0V, C0 = 5V, C1 = 0V 7 9 11.5 mA

IS-(Low Power) Negative Supply Current per Amplifier All outputs at 0V, C0 =5V, C1 = 0V -10.5 -8 -6 mA

IS+(Terminate) Positive Supply Current per Amplifier All outputs at 0V, C0 = 0V, C1 = 5V 4 5.1 7 mA

IS-(Terminate) Negative Supply Current per Amplifier All outputs at 0V, C0 = 0V, C1 = 5V -6 -4 -3 mA

IS+(Power Down ) Positive Supply Current per Amplifier All outputs at 0V, C0 = C1 = 5V 0.75 1.05 1.7 mA

IS-(Power Down ) Negative Supply Current per Amplifier All outputs at 0V, C0 = C1 = 5V -0.5 -0.25 0.07 mA

IGND GND Supply Current per Amplifier All outputs at 0V -1 mA

INPUT CHARACTERISTICS

VOS Input Offset Voltage -30 30 mV

ΔVOS VOS Mismatch -15 15 mV

IB+ Non-Inverting Input Bias Current -15 15 µA

IB- Inverting Input Bias Current -50 50 µA

ΔIB-I

B- Mismatch -30 30 µA

ROL Transimpedance 0.4 0.8 MΩ

eNInput Noise Voltage 3.5 nV/√Hz

iN-Input Noise Current 13 pA/√Hz

VIH Input High Voltage C0 & C1 inputs 2.7 V

VIL Input Low Voltage C0 & C1 inputs 0.8 V

IIH1 Input High Current for C1C1 = 5V 1.5 8 µA

IIH0 Input High Current for C0C0 = 5V 0.75 4 µA

IIL Input Low Current for C1or C0C1 = 0V, C0 = 0V -1 1 µA

OUTPUT CHARACTERISTICS

VOUT Loaded Output Swing RL = 65Ω±10.3 ±10.6 V

RL = 22Ω±9.3 ±9.8 V

IOL Linear Output Current AV = 5, RL = 10Ω, f = 100kHz,

THD = --60dBc 450 mA

IOUT Output Current VOUT = 1V, RL = 1Ω1A

EL1503A

4FN7039.2

March 26, 2007

DYNAMIC PERFORMANCE

BW -3dB Bandwidth AV = +5 80 MHz

HD2 2nd Harmonic Distortion fC = 1MHz, RL = 100Ω, VOUT = 2VP-P -76 dBc

fC = 1MHz, RL = 25Ω, VOUT = 2VP-P -72 dBc

HD3 3rd Harmonic Distortion fC = 1MHz, RL = 100Ω, VOUT = 2VP-P -76 dBc

fC = 1MHz, RL = 25Ω, VOUT = 2VP-P -72 dBc

SR Slewrate VOUT from -8V to +8V Measured at ±4V 700 1100 V/µs

Electrical Specifications VS = ±12V, RF = 1.5kΩ, RL= 65Ω, IADJ = C0 = C1 = 0V, TA = +25°C. Amplifiers tested separately. (Continued)

PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT

Typical Performance Curves

FIGURE 1. DRIVER DIFFERENTIAL FREQUENCY

RESPONSE vs RF (FULL POWER MODE) FIGURE 2. DRIVER DIFFERENTIAL FREQUENCY

RESPONSE vs RF (FULL POWER MODE)

FIGURE 3. DRIVER DIFFERENTIAL FREQUENCY

RESPONSE vs RF (2/3 POWER MODE) FIGURE 4. DRIVER DIFFERENTIAL FREQUENCY

RESPONSE vs RF (2/3 POWER MODE)

1M 100M

GAIN (dB)

FREQUENCY (Hz)

10M

100K

VS=±12V

AV=10

RL=100Ω

RF=2.0kΩ

RF=2.43kΩ

RF=2.74kΩ

RF=1.82kΩ

RF=1.5kΩRF=1.3kΩ

1M 100M

GAIN (dB)

FREQUENCY (Hz)

10M

100K

RF=2.0kΩ

RF=2.4kΩ

RF=2.74kΩ

VS=±5V

AV=10

RL=100Ω

RF=1.3kΩ

RF=1.82kΩ

RF=1.5kΩ

1M 100M

GAIN (dB)

FREQUENCY (Hz)

10M

100K

VS=±12V

AV=10

RL=100ΩRF=1.5kΩ

RF=2.43kΩ

RF=2.74kΩ

RF=2.0kΩ

RF=1.82kΩ

RF=1.3kΩ

1M 100M

GAIN (dB)

FREQUENCY (Hz)

10M

100K

RF=1.82kΩ

RF=1.3kΩ

RF=2.0kΩ

RF=2.4kΩ

RF=1.5kΩ

RF=2.74kΩ

VS=±5V

AV=10

RL=100Ω

EL1503A

5FN7039.2

March 26, 2007

FIGURE 5. DRIVER DIFFERENTIAL FREQUENCY

RESPONSE vs RF (TERMINATE MODE) FIGURE 6. DRIVER DIFFERENTIAL FREQUENCY

RESPONSE vs RF (TERMINATE MODE)

FIGURE 7. DRIVER DIFFERENTIAL FREQUENCY

RESPONSE vs RF (FULL POWER MODE) FIGURE 8. DRIVER DIFFERENTIAL FREQUENCY

RESPONSE vs RF (FULL POWER MODE)

FIGURE 9. DRIVER DIFFERENTIAL FREQUENCY

RESPONSE vs RF (2/3 POWER MODE) FIGURE 10. DRIVER DIFFERENTIAL FREQUENCY

RESPONSE vs RF (2/3 POWER MODE)

Typical Performance Curves (Continued)

1M100M

GAIN (dB)

FREQUENCY (Hz)

10M

100K

RF=2.0kΩ

RF=2.43kΩ

RF=2.74kΩ

RF=1.82kΩ

VS=±12V

AV=10

RL=100Ω

1M 100M

GAIN (dB)

FREQUENCY (Hz)

10M

100K

RF=1.84kΩ

RF=2.0kΩRF=2.43kΩ

RF=2.74kΩ

VS=±5V

AV=10

RL=100Ω

1M 100M

GAIN (dB)

FREQUENCY (Hz)

10M

100K

RF=1.3kΩ

RF=2.0kΩ

RF=1.82kΩ

RF=2.4kΩ

RF=1.5kΩ

RF=2.74kΩ

VS=±12V

AV=5

RL=100Ω

1M 100M

GAIN (dB)

FREQUENCY (Hz)

10M

100K

RF=2.0kΩ

RF=1.82kΩ

RF=2.4k

RF=1.5kΩ

RF=2.74k

VS=±5V

AV=5

RL=100Ω

1M 100M

GAIN (dB)

FREQUENCY (Hz)

10M

100K

RF=1.3kΩ

RF=2.0kΩ

RF=1.82kΩ

RF=2.43kΩ

RF=1.5kΩ

RF=2.74kΩ

VS=±12V

AV=5

RL=100Ω

1M 100M

GAIN (dB)

FREQUENCY (Hz)

10M

100K

RF=1.5kΩ

RF=2.4kΩ

RF=2.0kΩ

RF=2.74kΩ

RF=1.82kΩ

VS=±5V

AV=5

RL=100Ω

EL1503A

6FN7039.2

March 26, 2007

FIGURE 1 1. DRIVER DIFFERENTIAL FREQUENCY

RESPONSE vs RF (TERMINATE MODE) FIGURE 12. DRIVER DIFFERENTIAL FREQUENCY

RESPONSE vs RF (TERMINATE MODE)

FIGURE 13. DRIVER INPUT VOL TAGE and FEEDBACK

CURRENT NOISE vs FREQUENCY FIGURE 14. SUPPLY CURRENT vs SUPPLY VOLTAGE

FIGURE 15. POSITIVE SUPPLY REJECTION vs FREQUENCY FIGURE 16. NEGATIVE SUPPLY REJECTION vs FREQUENCY

Typical Performance Curves (Continued)

1M 100M

GAIN (dB)

FREQUENCY (Hz)

10M

100K

RF=2.74kΩ

RF=2.43kΩ

RF=2.0kΩ

RF=1.82kΩ

VS=±12V

AV=5

RL=100Ω

1M 100M

GAIN (dB)

FREQUENCY (Hz)

10M

100K

RF=2.4kΩ

RF=2.0kΩ

RF=2.74kΩ

RF=1.82kΩ

VS=±5V

AV=5

RL=100Ω

eN (nV/√Hz)

FREQUENCY (Hz)

10K

100

100 100K1K

iN (pA/√Hz)

IS (mA)

VS (V)

41208

2610

IS- (FULL POWER)

+ (2/3 POWER)

- (2/3 POWER)

IS- (TERMINATE)

+ (FULL POWER)

-40

SUPPLY REJECTION (dB)

FREQUENCY (Hz)

-100

10M

10K 100K 100M1M

-20

-60

-80

RIGHT

DRIVER

LEFT

DRIVER

-40

SUPPLY REJECTION (dB)

FREQUENCY (Hz)

-100

10M

10K 100K 100M1M

-20

-60

-80

RIGHT

DRIVER

LEFT

DRIVER

EL1503A

7FN7039.2

March 26, 2007

FIGURE 17. OUTPUT IMPEDANCE vs FREQUENCY FIGURE 18. OUTPUT IMPEDANCE vs FREQUENCY

FIGURE 19. DIFFERENTIAL HARMONIC DISTORTION vs

OUTPUT AMPLITUDE (FUL L POWER) FIGURE 20. DIFFERENTIAL HARMONIC DISTORTION vs

OUTPUT AMPLITUDE (FULL POWER)

FIGURE 21. DIFFERENTIAL HARMONIC DISTORTION vs

OUTPUT AMPLITUDE (2/3 POWER) FIGURE 22. DIFFERENTIAL HARMONIC DISTORTION vs

OUTPUT AMPLITUDE

Typical Performance Curves (Continued)

OUTPUT IMPEDANCE (Ω)

FREQUENCY (Hz)

100

100M10K 1M

100K 10M

TERMINATE

2/3 POWER

FULL POWER

VS=±12V

AV=1

RL=1.5kΩ

OUTPUT IMPEDANCE (Ω)

FREQUENCY (Hz)

100

100M10K 1M

100K 10M

FULL POWER

VS=±5V

AV=1

RL=1.5kΩTERMINATE

2/3 POWER

-45

-55

-65

-75

-85

1 5 9 131721

VOP-P (V)

HD (dB)

HD3

HD2

VS=±12V

AV=5

RL=100Ω

fC=1MHz

-40

-45

-70

-75

-85

123 5 78

VOP-P (V)

HD (dB)

-55

-80

HD3

HD2

-50

-60

-65

VS=±5V

AV=5

RL=100Ω

fC=1MHz

-50

-55

-60

-80

-85

1 5 9 131721

VOP-P (V)

HD (dB)

HD3

HD2

-65

-70

-75

VS=±5V

AV=5

RL=100Ω

fC=1MHz

-40

-50

-60

-70

-80

123 5 78

VOP-P (V)

HD (dB)

HD3

HD2

VS=±5V

AV=5

RL=100Ω

fC=1MHz

EL1503A

8FN7039.2

March 26, 2007

FIGURE 23. DIFFERENTIAL TOT AL HARMONIC DISTORTION

vs OUTPUT AMPLITUDE FIGURE 24. DIFFERENTIAL TOT AL HARMONIC DISTORTION

vs OUTPUT AMPLITUDE

FIGURE 25. DIFFERENTIAL HARMONIC DISTORTION vs

OUTPUT AMPLITUDE (FUL L POWER) FIGURE 26. DIFFERENTIAL HARMONIC DISTORTION vs

OUTPUT AMPLITUDE (FULL POWER)

FIGURE 27. DIFFERENTIAL HARMONIC DISTORTION vs

OUTPUT AMPLITUDE (2/3 POWER) FIGURE 28. DIFFERENTIAL HARMONIC DISTORTION vs

OUTPUT AMPLITUDE (2/3 POWER)

Typical Performance Curves (Continued)

-45

-50

-60

-70

-80

1 5 9 131721

VOP-P (V)

THD (dB)

-55

-65

-75

2/3 POWER

FULL POWER

VS=±12V

AV=5

RL=100Ω

fC=1MHz

-40

-50

-60

-70

-80

123 5 78

VOP-P (V)

THD (dB)

2/3 POWER

FULL POWER

VS=±5V

AV=5

RL=100Ω

fC=1MHz

-74

HD (dB)

VOP-P (V)

-78

-60

19113

-62

-76

515

-72

-68

-64

-66

-70

3711 17

HD3

HD2

VS=±12V

AV=5

RL=100Ω

fC=1MHz

-72

HD (dB)

VOP-P (V)

-80

-56

614

-60

-76

-68

-64

HD3

HD2

VS=±5V

AV=5

RL=100Ω

fC=1MHz

-66

HD (dB)

VOP-P (V)

-70

-54

19113

-68

515

-64

-60

-56

-58

-62

3711 17

HD3

HD2

VS=±12V

AV=5

RL=100Ω

fC=1MHz

-68

HD (dB)

VOP-P (V)

-72

-58

614

-60

-70

-66

-64

-62

HD3

HD2

VS=±5V

AV=5

RL=100Ω

fC=1MHz

EL1503A

9FN7039.2

March 26, 2007

FIGURE 29. DIFFERENTIAL TOT AL HARMONIC DISTORTION

vs OUTPUT AMPLITUDE FIGURE 30. DIFFERENTIAL TOT AL HARMONIC DISTORTION

vs OUTPUT AMPLITUDE

FIGURE 31. DIFFERENTIAL BANDWIDTH vs SUPPLY

VOLTAGE FIGURE 32. DIFFERENTIAL PEAKING vs SUPPLY VOLTAGE

FIGURE 33. IS vs RSET FIGURE 34. IS vs RSET

Typical Performance Curves (Continued)

-63

THD (dBc)

VOP-P (V)

-67

-55

719115

-57

-65

31117

-61

-59

9513

2/3 POWER

FULL POWER

VS=±12V

AV=5

RL=100Ω

fC=1MHz

-63

THD (dBc)

VOP-P (V)

-67

-55

471

-57

-65

-61

-59

2/3 POWER

FULL POWER

VS=±5V

AV=5

RL=100Ω

fC=1MHz

BW (MHz)

±VS (V)

2/3 POWER MODE

TERMINATE MODE

FULL POWER MODE

6 7 8 9 10 11 12

AV=10

RF=1.82kΩ

2.0

PEAKING (dB)

±VS (V)

3.5

3.0

1.5

2.5

2/3 POWER MODE

TERMINATE MODE

FULL POWER MODE

0.5

6 7 8 9 101112

1.0

AV=10

RF=1.82kΩ

410

±IS (mA)

RSET (kΩ)

IS+ (FULL POWER)

IS- (FULL POWER)

IS+ 2/3 POWER)

IS- 2/3 POWER)

IS+ (TERMINATE)

IS- (TERMINATE)

VS = ±12V

RSET to GND

410

±IS (mA)

RSET (kΩ)

VS = ±5V

RSET to GND

IS+ (FULL POWER)

IS- (FULL POWER)

IS+ 2/3 POWER)

IS- 2/3 POWER)

IS+ (TERMINATE)

IS- (TERMINATE)

EL1503A

10 FN7039.2

March 26, 2007

FIGURE 35. IS vs ISET FIGURE 36. IS vs ISET

FIGURE 37. POWER DISSIP A TION vs AMBIENT

TEMPERATURE for VARIOUS MOUNTED θJAsFIGURE 38. POWER DISSIP A TION vs AMBIENT

TEMPERATURE

Typical Performance Curves (Continued)

±IS (mA)

ISET (µA)

100 5000 300

200 400

- (FULL POWER)

+ (2/3 POWER)

- (2/3 POWER)

+ (TERMINATE)

- (TERMINATE)

+ (FULL POWER)

VS = ±12V

±IS (mA)

ISET (µA)

100 5000 300

200 400

- (FULL POWER)

+ (2/3 POWER)

- (2/3 POWER)

+ (TERMINATE)

- (TERMINATE)

+ (FULL POWER)

VS = ±12V

0 100

0.5

POWER DISSIPATION (W)

AMBIENT TEMPERATURE (°C)

4.5

-40 20-20 60 80

3.5

3.0

2.5

2.0

1.5

1.0

4.0 θJA = 30°C/W

θJA = 43°C/W

θJA = 53°C/W

θJA = 80°C/W

1500 25 50 75 100 125

AMBIENT TEMPERATURE (°C)

POWER DISSIPATION (W)

3.0

0.5

1.0

1.5

2.0

2.5

2.703W

=37°C/W

QFN24

POWER DISSIPATION & THERMAL RESISTANCE USING

JEDEC JESD51-7 HIGH EFFECTIVE THERMAL

CONDUCTIVITY (4-LA YER) TEST BOARD, QFN EXPOSED

DIEPAD SOLDERED TO PCB PER JESD51-5

EL1503A

11 FN7039.2

March 26, 2007

Test Circuit

100

332Ω

56Ω

1/2W

1.5kΩ

R16

1.5kΩ

56Ω

1/2W

RIGHT

DRIVER

OUT

RIGHT

DRIVER

VS+

GND

R17

51Ω

5µF 0.1µF

RSET

51Ω

LEFT

DRIVER

LEFT

DRIVER

OUT

GND

0.1µF 5µF

C2C1

VIN-A VIN-B

VIN+A

GND

VS-

VOUTAVOUTB

VS+

GND

VIN+B

IADJ

TANTALUM TANTALUM

EL1503A

12 FN7039.2

March 26, 2007

Pin Descriptions

20 Ld SOIC

(0.300") 24 Ld QFN PIN NAME FUNCTION CIRCUIT

123V

IN-A Channel A Inverting Input

CIRCUIT 1

224V

OUTA Ch annel A Output (Reference Circuit 1)

33V

S- Negative Supply

4, 5, 6, 7 7 GND Ground Connection

88V

IN+A Channel A Non-Inverting Input

CIRCUIT 2

99C

1Current Control Bit 1

CIRCUIT 3

10 10 C0Current Control Bit 0 (Reference Circuit 3)

11 1, 2, 4, 5, 6, 14,

15, 16, 18, 19,

NC Not Connected

12 11 IADJ Supply Current Control Pin

CIRCUIT 4

13 12 VIN+B Channel B Non-Inverting Input (Reference Circuit 2)

14, 15, 16, 17 13 GND Ground Connection

18 17 VS+ Positive Supply

19 20 VOUTB Channel B Output (Reference Circuit 1)

20 21 VIN-B Channel B Inverting Input (Reference Circuit 1)

- 7 Reserve for Future Use Internally Unconnected

VS+

VS-

VS+

6.7V

VS+

EL1503A

13 FN7039.2

March 26, 2007

Applications Information

The EL1503A consists of two high-power line driver

amplifiers that can be connected for full duplex differential

line transmission. The amplifiers are designed to be used

with signals up to 4MHz and produce low distortion levels. A

typical interface circuit is shown in Figure 39 below.

The amplifiers are wired with one in positive gain and the

other in a negative gain configura tion to generate a

differential output for a single-ended input. They will exhibit

very similar frequency responses for gains of three or

greater and thus generate very small common-mode outputs

over frequency, but for low gains the two drivers RF's need

to be adjusted to give similar frequency responses. The

positive-gain driver will generally exhibit more bandwidth and

peaking than the negative-gain driver.

If a differential signal is available to the drive amplifiers, they

may be wired so:

Each amplifier has identical positive gain connections, and

optimum common-mode rejection occurs. Further, DC input

errors are duplicated and create common-mode rather than

differential line errors.

Input Connections

The EL1503A amplifiers are somewhat sensitive to source

impedance. In particular, they do not like being driven by

inductive sources. More than 100nH of source impedance

can cause ringing or even oscillations. This inductance is

equivalent to about 4” of unshielded wiring, or 6” of

unterminated transmission line. Normal high-fre quency

construction obviates any such problem.

Power Supplies & Dissipation

Due to the high power drive capability of the EL1503A, much

attention needs to be paid to power dissipation. The power

that needs to be dissipated in the EL1503A has two main

contributors. The first is the quiescent current dissipation.

The second is the dissipation of the output stage.

The quiescent power in the EL1503A is not constant with

varying outputs. In reality, 7mA of the 12.5mA needed to

power each driver is converted in to output current.

Therefore, in the equation be low we should subtract the

average output current, IO, or 7mA, whichever is the low est.

We’ll call this term IX.

Therefore, we can determine a quiescent curre nt with the

equation:

where:

VS is the supply voltage (VS+ to VS-)

IS is the maximum quiescent supply current (IS+ + IS-)

IX is the lesser of IO or 7mA (generally IX = 7mA)

The dissipation in the output stage has two main

contributors. Firstly, we have the average voltage drop

across the output transistor and secondly, the average

output current. For minimal power dissipation, the user

should select the supply voltage and the line transformer

ratio accordingly. The supply voltage should be kept as low

as possible, while the transformer ratio should be selected

so that the peak voltage required from the EL1503A is close

to the maximum available outpu t swing. There is a trade of

however with the selection of transformer ratio. As the ratio

is increased, the receive signal available to the receivers is

reduced.

Once the user has selected the transformer ratio, the

dissipation in the output stages can be selected with the

following equation:

where:

VS is the supply voltage (VS+ to VS-)

VO is the average output voltage per channel

IO is the average output current per channel

The overall power dissipation (PDISS) is obtained by adding

PDquiescent and PDtransistor.

FIGURE 39. TYPICAL LINE INTERFACE CONNECTION

RECEIVE

OUT -

RECEIVE

OUT +

DRIVER

INPUT

RFR

RIN

ROUT

LINE +

RECEIVE

AMPLIFIERS

ZLINE

LINE -

FIGURE 40. DRIVERS WIRED FOR DIFFERENTIAL INPUT

2RG

PDquiescent VSIS2IX

–()×=

PDtransistors 2I

OVS

-------

⎝

⎛

×× VO

–⎠

⎞

EL1503A

14 FN7039.2

March 26, 2007

Then, the θJA requirement needs to be calculated. This is

done using the equation:

where:

TJUNCT is the maximum die temperature (150°C)

TAMB is the maximum ambient temperature

PDISS is the dissipation calculated above

θJA is the junction to ambient thermal resistance for the

package when mounted on the PCB

This θJA value is then used to calculate the area of copper

needed on the board to dissipate the power. The graph

below show various θJA for the SO20 mounted on different

copper foil areas.

A separate application note details the 24 Ld QFN PCB

design considerations.

Single Supply Operation

The EL1503A can also be powered from a single supply

voltage. When operating in this mode, the GND pins can still

be connected directly to GND. To calculate power

dissipation, the equations in the previous section should be

used, with VS equal to half the supply rail.

EL1503A PCB Design

A separate application note details the 24 Ld QFN PCB

design considerations. The SOIC power packages

(20 lea ds) ar e designed so that heat may be conducted

away from the device in an efficient manner . To disperse this

heat, the center leads (4 per side for the 20 lead and 2 per

side for the 16 lead) are internally connected to the mounting

platform of the die. Heat flows through the leads into the

circuit board copper , then spreads and convects to air . Thus,

the ground plane on the component side of the board

becomes the heatsink. This has proven to be a very effective

technique, but several aspects of board layout should be

noted. First, the heat shoul d not be shunted to internal

copper layers of the board nor backside foil, since the

feedthroughs and fiberglass of the board are not very

thermally conductive. To obtain the best thermal resistance

of the mounted part, θJA, the topside copper ground plane

should have as much area as possible and be as thick as

practical. If possible, the solder mask should be cut away

from the EL1503A to improve thermal resistance. Finally,

metal heatsinks can be placed against the board close to the

part to draw heat toward the chassis.

Output Loading

While the drive amplifiers can output in excess of 500mA

transiently, the internal metallization is not designed to carry

more than 100mA of steady DC current and there is no

current-limit mechanism. This allows safely driving rms

sinusoidal currents of 2 X 100mA, or 200mA. This current is

more than that required to drive line impedances to large

output levels, but output short circuits cannot be tolerated.

The series output resistor will usually limit currents to safe

values in the event of line shorts. Driving lines with no series

resistor is a serious hazard.

The amplifiers are sensitive to capacitive loading. More than

25pF will cause peaking of th e frequency response. The

same is true of badly terminated lines connected without a

series matching resistor.

Power Supplies

The power supplies should be well bypassed close to the

EL1503A. A 3.3µF tantalum capacitor for each supply works

well. Since the load currents are differential, they should not

travel through the board copper and set up ground loops that

can return to amplifier inputs. Due to the class AB output

stage design, these currents have heavy harmonic content.

If the ground terminal of the positive and negative bypass

capacitors are connected to each other directl y an d then

returned to circuit ground, no such ground loops will occur.

This scheme is employed in the layout of the EL1503A

demonstration board, and documentation can be obtained

from the factory.

Feedback Resistor Value

The bandwidth and peaking of the amplifiers varies with

supply voltage somewhat and with gain se ttings. The

feedback resistor values can be adjusted to produce an

optimal frequency response. Here is a series of resistor

values that produce an optimal driver frequency response

(1dB peaking) for different supply voltages and gains:

θJA TJUNCT TAMB

–()

PDISS

-------------------------------------------------

012 910678345

FIGURE 41. THERMAL RESIST ANCE of 20 Ld SOIC (0.300")

EL1503A vs BOARD COPPER AREA

MOUNTED DEVICE θJA (°C/W)

Note: 2oz. COPPER USED

TOP FOIL ONLY-WITH SOLDER MASK

TOP FOIL-WITH 0.45IN2 BOTTOM

FOIL WITH MANY FEEDTHROUGHS

TOP FOIL ONLY-NO SOLDER MASK

AREA OF CIRCUIT BOARD HEAT SINK (in2)

TABLE 1. OPTIMUM DRIVER FEEDBACK RESISTOR for

VARIOUS GAINS and SUPPLY VOLTAGES

SUPPLY

VOLTAGE

DRIVER VOLTAGE GAIN

2.5 5 10

±5V

±12V 2.7k

2.2k 2.2k

2.0k 2.0k

2.0k

EL1503A

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No lice nse is gran t ed by i mpli catio n or other wise u nder an y p a tent or patent rights of Int ersi l or it s sub sidi aries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN7039.2

March 26, 2007

Power Control Function

The EL1503A contains two forms of power control operation.

Two digital inputs, C0 and C1, can be used to control the

supply current of the EL1503A drive ampli fi ers. As the

supply current is reduced, the EL1503A will start to exhibit

slightly higher levels of distortio n and the frequency

response will be limited. The 4 power modes of the EL1503A

are set up as shown in the table 2.

Another method for controlling the power consumption of the

EL1503A is to connect a resistor from the IADJ pin to ground.

When this pin is grounded (the normal state), the supply

current per channel is as per the specifications table on page

3. When a resistor is inserted, the supply curre nt is scaled

according to the “IS vs RSET” graphs on page 10 in the

Performance Curves section.

Both methods of power control can be used simultaneously.

In this case, positive and negative supply currents (per amp)

are given by the equations belo w:

TABLE 2. POWER MODES of the EL1503A

C1C0OPERATION

00I

S full power mode (CO or CP)

012/3 I

S power mode (CO or CP)

101/3 I

S terminate only mode

1 1 Power down

IS+1mAC(123)⁄ 12.5mA

1(RSET 1k)÷+

-------------------------------------------

××

C(013)⁄ 12.5mA

1(RSET 1k)÷+

-------------------------------------------

××

IS-0C(123)⁄ 12.5mA

1(RSET 1k)÷+

-------------------------------------------

××

(13)⁄ 12.5mA

1(RSET 1k)÷+

-------------------------------------------

××

EL1503A

16 FN7039.2

March 26, 2007

EL1503A

Small Outline Package Family (SO)

GAUGE

PLANE

A1 L

DETAIL X 4° ±4°

SEATING

PLANE

0.010 BMCA

0.004 C

0.010 BMCA

(N/2)

NN (N/2)+1

PIN #1

I.D. MARK

h X 45°

SEE DETAIL “X”

0.010

MDP0027

SMALL OUTLINE PACKAGE FAMILY (SO)

SYMBOL

INCHES

TOLERANCE NOTESSO-8 SO-14

SO16

(0.150”)

SO16 (0.300”)

(SOL-16)

SO20

(SOL-20)

SO24

(SOL-24)

SO28

(SOL-28)

A 0.068 0.068 0.068 0.104 0.104 0.104 0.104 MAX -

A1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 ±0.003 -

A2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 ±0.002 -

b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 ±0.003 -

c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 ±0.001 -

D 0.193 0.341 0.390 0.406 0.504 0.606 0.704 ±0.004 1, 3

E 0.236 0.236 0.236 0.406 0.406 0.406 0.406 ±0.008 -

E1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 ±0.004 2, 3

e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 Basic -

L 0.025 0.025 0.025 0.030 0.030 0.030 0.030 ±0.009 -

L1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 Basic -

h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 Reference -

N 8 14 16 16 20 24 28 Reference -

Rev. M 2/07

NOTES:

1. Plastic or metal protrusions of 0.006” maximum per side are not included.

2. Plastic interlead protrusions of 0.010” maximum per side are not included.

3. Dimensions “D” and “E1” are measured at Datum Plane “H”.

4. Dimensioning and tolerancing per ASME Y14.5M-1994

17 FN7039.2

March 26, 2007

EL1503A

QFN (Quad Flat No-Lead) Package Family

PIN #1

I.D. MARK

(N-2)

(N-1)

(N/2)

0.075

TOP VI EW

(N/2)

PIN #1 I.D.

(N-2)

(N-1)

N LEADS

BOTTOM VIEW

DETAIL X

PLANE

SEATING

N LEADS

SEE DETAIL "X"

A1 (L)

N LEADS

& EXPOSED PAD

0.10

SIDE VIEW

0.10 BA

0.075 C

(E2)

(D2)

0.08 C

(c)

MDP0046

QFN (QUAD FLAT NO-LEAD) PACKAGE FAMILY

(COMPLIANT TO JEDEC MO-220)

SYMBOL

MILLIMETERS

TOLERANCE NOTESQFN44 QFN3 QFN32

A 0.90 0.90 0.90 0.90 ±0.10 -

A1 0.02 0.02 0.02 0.02 +0.03/-0.02 -

b 0.25 0.25 0.23 0.22 ±0.02 -

c 0.20 0.20 0.20 0.20 Reference -

D 7.00 5.00 8.00 5.00 Basic -

D2 5.10 3.80 5.80 3.60/2.48 Reference 8

E 7.00 7.00 8.00 6.00 Basic -

E2 5.10 5.80 5.80 4.60/3.40 Reference 8

e 0.50 0.50 0.80 0.50 Basic -

L 0.55 0.40 0.53 0.50 ±0.05 -

N 44 38 32 32 Reference 4

ND 11 7 8 7 Reference 6

NE 11 12 8 9 Reference 5

SYMBOL

MILLIMETERS TOLER-

ANCE NOTESQFN28 QFN2 QFN20 QFN16

A 0.90 0.90 0.90 0.90 0.90 ±0.10 -

A1 0.02 0.02 0.02 0.02 0.02 +0.03/

-0.02 -

b 0.25 0.25 0.30 0.25 0.33 ±0.02 -

c 0.20 0.20 0.20 0.20 0.20 Reference -

D 4.00 4.00 5.00 4.00 4.00 Basic -

D2 2.65 2.80 3.70 2.70 2.40 Reference -

E 5.00 5.00 5.00 4.00 4.00 Basic -

E2 3.65 3.80 3.70 2.70 2.40 Reference -

e 0.50 0.50 0.65 0.50 0.65 Basic -

L 0.40 0.40 0.40 0.40 0.60 ±0.05 -

N 28 24 20 20 16 Reference 4

ND 6 5 5 5 4 Reference 6

NE 8 7 5 5 4 Reference 5

Rev 11 2/07

NOTES:

1. Dimensioning and tolerancing per ASME Y14.5M-1994.

2. Tiebar view shown is a non-functional feature.

3. Bottom-side pin #1 I.D. is a diepad chamfer as shown.

4. N is the total number of terminals on the device.

5. NE is the number of terminals on the “E” side of the package

(or Y-direction).

6. ND is the number of terminals on the “D” side of the package

(or X-direction). ND = (N/2)-NE.

7. Inward end of terminal may be square or circular in shape with radius

(b/2) as shown.

8. If two values are listed, multiple exposed pad options are available.

Refer to device-specific datasheet.