SiT5155
±0.5 ppm, Elite Platform™ Super-TCXO for GNSS/GPS
Description
The SiT5155 is a ±0.5 ppm MEMS Super-TCXO that is
engineered for high reliability, GNSS-based precision
positioning and timing applications.
Leveraging SiTime’s unique DualMEMS™ temperature
sensing and TurboCompensation™ technologies, the
SiT5155 delivers the best dynamic performance for timing
stability in the presence of environmental stressors such as
air flow, temperature perturbation, vibration, shock, and
electromagnetic interference. This device also integrates
multiple on-chip regulators to filter power supply noise,
eliminating the need for a dedicated external LDO.
The SiT5155 offers three device configurations that can be
ordered using Ordering Codes for:
The SiT5155 can be factory programmed for specific
combinations of frequency, voltage, and pull range.
Programmability enables designers to optimize clock
configurations while eliminating long lead times and
customization costs associated with quartz devices where
each frequency is custom built.
Refer to Manufacturing Guideline for proper reflow profile
and PCB cleaning recommendations to ensure best
performance.
Features
◼ 12 frequencies from 10 MHz to 40 MHz
◼ Factory programmable options for short lead time
◼ Best dynamic stability under airflow, thermal shock
▪ ±0.5 ppm stability across temperature
▪ ±15 ppb/°C typical frequency slope (ΔF/ΔT)
◼ -40°C to +105°C operating temperature
◼ No activity dips or micro jumps
◼ Resistant to shock, vibration and board bending
◼ On-chip regulators eliminate the need for external LDOs
◼ Digital frequency pulling (DCTCXO) via I2C
▪ Digital control of output frequency and pull range
▪ Up to ±3200 ppm pull range
▪ Frequency pull resolution down to 5 ppt
◼ 2.5 V, 2.8 V, 3.0 V and 3.3 V supply voltage
◼ LVCMOS or clipped sinewave output
◼ RoHS and REACH compliant
◼ Pb-free, Halogen-free, Antimony-free
Applications
◼ Precision GNSS systems
◼ Microwave backhaul
◼ Professional audio and video equipment
◼ Network routers and switches
◼ Storage and servers
◼ Test and measurement
Block Diagram
Figure 1. SiT5155 Block Diagram
5.0 mm x 3.2 mm Package Pinout
OE / VC / NC 1
2
3
456
7
8
910
SCL / NC
NC
GND
NC
NC
VDD
CLK
A0 / NC
SDA / NC
Figure 2. Pin Assignments (Top view)
(Refer to Table 13 for Pin Descriptions)
Rev 1.04
May 23, 2020
www.sitime.com
SiT5155 ±0.5 ppm, Elite Platform™ Super-TCXO for GNSS/GPS
Rev 1.04
Page 2 of 38
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Ordering Information
The part number guide illustrated below is for reference only, in which boxes identify order codes having more than one option.
To customize and build an exact part number, use the SiTime Part Number Generator. To validate the part number, use the
SiTime Part Number Decoder.
SiT5155AC - F
K
- 33 E 0 - 10.000000 T
SiT5155AC - F
K
- 33 V T - 10.000000 T
SiT5155AC - F
K
G33 J R - 10.000000 T
Part
Family Silicon
Revision
Letter
Pull Range – DCTCXO mode only
"T": ±6.25 ppm
"R": ±10 ppm
"Q": ±12.5 ppm
"M": ±25 ppm
"B": ±50 ppm
"C": ±80 ppm
"E": ±100 ppm
"F": ±125 ppm
"G": ±150 ppm
"H": ±200 ppm
"X": ±400 ppm
"L": ±600 ppm
"Y": ±800 ppm
"S": ±1200 ppm
"Z": ±1600 ppm
"U": ±3200 ppm
Supply Voltage
"25": 2.5 V ±10%
"28": 2.8 V ±10%
"30": 3.0 V ±10%
"33": 3.3 V ±10%
Frequency
12 GNSS/GPS Frequencies (MHz):
10.000000, 10.949297, 16.367600,
16.367667, 16.368000, 16.369000,
16.384000, 20.000000, 24.553500,
25.000000, 26.000000, 40.000000
Pin 1 Function – DCTCXO mode only
"I": Output Enable
"J": No Connect, software OE control
Temperature Range
"I": Industrial, -40 to 85°C
"C": Extended Commercial, -20 to 70°C
"E": Extended Industrial, -40 to 105°C
TCXO
VCTCXO
DCTCXO
Package Size
"F": 5.0 mm x 3.2 mm Pin 1 Function – TCXO mode only
"E": Output Enable
"N": No Connect
I2C Address Mode – DCTCXO mode only
“0”, “1”, “2”, “3”, “4”, “5”, “6”, “7”, “8”, “9”, “A”, “B”,
“C”, “D”, “E”, “F”: Order code representing hex
value of I2C address. When the I2C address is
factory programmed using this code, pin A0 is no
connect (NC).
“G”: I2C pin addressable mode. Address is set by
the logic on A0 pin.
Packaging
"T": 12 mm Tape & Reel, 3 ku reel
"Y": 12 mm Tape & Reel, 1 ku reel
“X”: 12 mm Tape & Reel, 250 u reel
(blank): bulk[2]
Output Waveform
"-": LVCMOS[1]
"C": Clipped Sinewave
Frequency Stability
"K": for ±0.5 ppm
Notes:
1. “-“ corresponds to the default rise/fall time for LVCMOS output as specified in Table 1 (Electrical Characteristics). Contact SiTime for other rise/fall time
options for best EMI or driving multiple loads. For differential outputs, contact SiTime.
2. Bulk is available for sampling only.
SiT5155 ±0.5 ppm, Elite Platform™ Super-TCXO for GNSS/GPS
Rev 1.04
Page 3 of 38
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TABLE OF CONTENTS
Description ................................................................................................................................................................................... 1
Features ....................................................................................................................................................................................... 1
Applications ................................................................................................................................................................................. 1
Block Diagram ............................................................................................................................................................................. 1
5.0 mm x 3.2 mm Package Pinout ............................................................................................................................................... 1
Ordering Information .................................................................................................................................................................... 2
Electrical Characteristics .............................................................................................................................................................. 4
Device Configurations and Pin-outs ............................................................................................................................................. 9
Pin-out Top Views ................................................................................................................................................................. 9
Test Circuit Diagrams for LVCMOS and Clipped Sinewave Outputs ......................................................................................... 10
Waveforms ................................................................................................................................................................................. 12
Timing Diagrams ........................................................................................................................................................................ 13
Typical Performance Plots ......................................................................................................................................................... 14
Architecture Overview ................................................................................................................................................................ 16
Frequency Stability ............................................................................................................................................................. 16
Output Frequency and Format ............................................................................................................................................ 16
Output Frequency Tuning ................................................................................................................................................... 16
Pin 1 Configuration (OE, VC, or NC) .................................................................................................................................. 17
Device Configurations ................................................................................................................................................................ 17
TCXO Configuration ........................................................................................................................................................... 17
VCTCXO Configuration ...................................................................................................................................................... 18
DCTCXO Configuration ...................................................................................................................................................... 19
VCTCXO-Specific Design Considerations ................................................................................................................................. 20
Linearity .............................................................................................................................................................................. 20
Control Voltage Bandwidth ................................................................................................................................................. 20
FV Characteristic Slope KV ................................................................................................................................................. 20
Pull Range, Absolute Pull Range ........................................................................................................................................ 21
DCTCXO-Specific Design Considerations ................................................................................................................................. 22
Pull Range and Absolute Pull Range .................................................................................................................................. 22
Output Frequency ............................................................................................................................................................... 23
I2C Control Registers .......................................................................................................................................................... 25
Register Descriptions .......................................................................................................................................................... 25
Register Address: 0x00. Digital Frequency Control Least Significant Word (LSW) ............................................................ 25
Register Address: 0x01. OE Control, Digital Frequency Control Most Significant Word (MSW) ......................................... 26
Register Address: 0x02. DIGITAL PULL RANGE CONTROL[15]......................................................................................... 27
Serial Interface Configuration Description .......................................................................................................................... 28
Serial Signal Format ........................................................................................................................................................... 28
Parallel Signal Format ........................................................................................................................................................ 29
Parallel Data Format ........................................................................................................................................................... 29
I2C Timing Specification ...................................................................................................................................................... 31
I2C Device Address Modes ................................................................................................................................................. 32
Schematic Example ............................................................................................................................................................ 33
Dimensions and Patterns ........................................................................................................................................................... 34
Layout Guidelines ...................................................................................................................................................................... 35
Manufacturing Guidelines .......................................................................................................................................................... 35
Additional Information ................................................................................................................................................................ 36
Revision History ......................................................................................................................................................................... 37
SiT5155 ±0.5 ppm, Elite Platform™ Super-TCXO for GNSS/GPS
Rev 1.04
Page 4 of 38
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Electrical Characteristics
All Min and Max limits are specified over temperature and rated operating voltage with 15 pF output load unless otherwise
stated. Typical values are at 25°C and 3.3 V Vdd.
Table 1. Output Characteristics
Parameters
Symbol
Min.
Typ.
Max.
Unit
Condition
Frequency Coverage
Nominal Output Frequency Range
F_nom
10.000000, 10.949297
16.367600, 16.367667
16.368000, 16.369000
16.384000, 20.000000
24.553500, 25.000000
26.000000, 40.000000
MHz
Temperature Range
Operating Temperature Range
T_use
-20
–
+70
°C
Extended Commercial, ambient temperature
-40
–
+85
°C
Industrial, ambient temperature
-40
–
+105
°C
Extended Industrial, ambient temperature
Frequency Stability
Frequency Stability over
Temperature
F_stab
–
–
±0.5
ppm
Referenced to (max frequency + min frequency)/2 over the
rated temperature range. Vc=Vdd/2 for VCTCXO
Initial Tolerance
F_init
–
–
±1
ppm
Initial frequency at 25°C at 48 hours after 2 reflows
Supply Voltage Sensitivity
F_Vdd
–
±7.10
±16.25
ppb
Vdd ±5%
Output Load Sensitivity
F_load
–
±0.81
±2.75
ppb
LVCMOS output, 15 pF ±10%. Clipped sinewave output,
10 kΩ || 10 pF ±10%
Frequency vs. Temperature Slope
ΔF/ΔT
–
±15
±25
ppb/°C
0.5°C/min temperature ramp rate, -40 to 105°C
Dynamic Frequency Change during
Temperature Ramp
F_dynamic
–
±0.13
±0.21
ppb/s
0.5°C/min temperature ramp rate, -40 to 105°C
One-Year Aging
F_1y
–
±1
–
ppm
At 25°C, after 2-days of continued operation. Aging is
measured with respect to day 3
20-Year Aging
F_20y
–
±2
–
ppm
At 25°C, after 2-days of continued operation. Aging is
measured with respect to day 3
LVCMOS Output Characteristics
Duty Cycle
DC
45
–
55
%
Rise/Fall Time
Tr, Tf
0.8
1.2
1.9
ns
10% - 90% Vdd
Output Voltage High
VOH
90%
–
–
Vdd
IOH = +3 mA
Output Voltage Low
VOL
–
–
10%
Vdd
IOL = -3 mA
Output Impedance
Z_out_c
–
17
–
Ohms
Impedance looking into output buffer, Vdd = 3.3 V
–
17
–
Ohms
Impedance looking into output buffer, Vdd = 3.0 V
–
18
–
Ohms
Impedance looking into output buffer, Vdd = 2.8 V
–
19
–
Ohms
Impedance looking into output buffer, Vdd = 2.5 V
Clipped Sinewave Output Characteristics
Output Voltage Swing
V_out
0.8
–
1.2
V
Clipped sinewave output, 10 kΩ || 10 pF ±10%
Rise/Fall Time
Tr, Tf
–
3.5
4.6
ns
20% - 80% Vdd, F_nom = 20 MHz
Start-up Characteristics
Start-up Time
T_start
–
2.5
3.5
ms
Time to first pulse, measured from the time Vdd reaches
90% of its final value. Vdd ramp time = 100 µs from 0V to
Vdd
Output Enable Time
T_oe
–
–
680
ns
See Timing Diagrams section below
Time to Rated Frequency Stability
T_stability
–
5
45
ms
Time to first accurate pulse within rated stability, measured
from the time Vdd reaches 90% of its final value. Vdd
ramp time = 100 µs
SiT5155 ±0.5 ppm, Elite Platform™ Super-TCXO for GNSS/GPS
Rev 1.04
Page 5 of 38
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Table 2. DC Characteristics
Parameters
Symbol
Min.
Typ.
Max.
Unit
Condition
Supply Voltage
Supply Voltage
Vdd
2.25
2.5
2.75
V
Contact SiTime for 2.25 V to 3.63 V continuous supply
voltage support
2.52
2.8
3.08
V
2.7
3.0
3.3
V
2.97
3.3
3.63
V
Current Consumption
Current Consumption
Idd
–
44
53
mA
F_nom = 20 MHz, No Load, TCXO and DCTCXO modes
–
48
57
mA
F_nom = 20 MHz, No Load, VCTCXO mode
OE Disable Current
I_od
–
43
51
mA
OE = GND, output weakly pulled down. TCXO, DCTCXO
–
47
55
mA
OE = GND, output weakly pulled down. VCTCXO mode
Table 3. Input Characteristics
Parameters
Symbol
Min.
Typ.
Max.
Unit
Condition
Input Characteristics – OE Pin
Input Impedance
Z_in
75
–
–
kΩ
Internal pull up to Vdd
Input High Voltage
VIH
70%
–
–
Vdd
Input Low Voltage
VIL
–
–
30%
Vdd
Frequency Tuning Range – Voltage Control or I2C mode
Pull Range
PR
±6.25
–
–
ppm
VCTCXO mode; contact SiTime for ±12.5 and ±25 ppm
±6.25
±10
±12.5
±25
±50
±80
±100
±125
±150
±200
±400
±600
±800
±1200
±1600
±3200
–
–
ppm
DCTCXO mode
Absolute Pull Range[3]
APR
±2.75
–
–
ppm
DCTCXO, VCTCXO for PR = ±6.25 ppm
Upper Control Voltage
VC_U
90%
–
–
Vdd
VCTCXO mode
Lower Control Voltage
VC_L
–
–
10%
Vdd
VCTCXO mode
Control Voltage Input Impedance
VC_z
8
–
–
MΩ
VCTCXO mode
Control Voltage Input Bandwidth
VC_bw
–
10
–
kHz
VCTCXO mode; contact SiTime for other bandwidth options
Frequency Control Polarity
F_pol
Positive
VCTCXO mode
Pull Range Linearity
PR_lin
–
0.5
1.0
%
VCTCXO mode
I2C Interface Characteristics, 200 Ohm, 550 pF (Max I2C Bus Load)
Bus Speed
F_I2C
≤ 400
kHz
-40 to 105°C
≤ 1000
kHz
-40 to 85°C
Input Voltage Low
VIL_I2C
–
–
30%
Vdd
DCTCXO mode
Input Voltage High
VIH_I2C
70%
–
–
Vdd
DCTCXO mode
Output Voltage Low
VOL_I2C
–
–
0.4
V
DCTCXO mode
Input Leakage current
IL
0.5
–
24
µA
0.1 VDD< VOUT < 0.9 VDD. Includes typical leakage current
from 200 kΩ pull resister to VDD. DCTCXO mode
Input Capacitance
CIN
–
–
5
pF
DCTCXO mode
Note:
3. APR = PR – initial tolerance – 20-year aging – frequency stability over temperature. Refer to Table 17 for APR with respect to other pull range options.
SiT5155 ±0.5 ppm, Elite Platform™ Super-TCXO for GNSS/GPS
Rev 1.04
Page 6 of 38
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Table 4. Jitter & Phase Noise – LVCMOS, -40°C to 85°C
Parameters
Symbol
Min.
Typ.
Max.
Unit
Condition
Jitter
RMS Phase Jitter (random)
T_phj
–
0.31
0.48
ps
F_nom = 10 MHz, Integration bandwidth = 12 kHz to 5 MHz
RMS Period Jitter
T_jitt_per
–
0.8
1.1
ps
F_nom = 10 MHz, population 10 k
Peak Cycle-to-Cycle Jitter
T_jitt_cc
–
6
9
ps
F_nom = 10 MHz, population 1 k, measured as absolute
value
Phase Noise
1 Hz offset
–
-80
-74
dBc/Hz
F_nom = 10 MHz
TCXO and DCTCXO modes, and VCTCXO mode with
±6.25 ppm pull range
10 Hz offset
–
-108
-102
dBc/Hz
100 Hz offset
–
-127
-123
dBc/Hz
1 kHz offset
–
-148
-145
dBc/Hz
10 kHz offset
–
-154
-151
dBc/Hz
100 kHz offset
–
-154
-150
dBc/Hz
1 MHz offset
–
-167
-163
dBc/Hz
5 MHz offset
–
-168
-164
dBc/Hz
Spurious
T_spur
–
-112
-105
dBc
F_nom = 10 MHz, 1 kHz to 5 MHz offsets
Table 5. Jitter & Phase Noise – Clipped Sinewave, -40°C to 85°C
Parameters
Symbol
Min.
Typ.
Max.
Unit
Condition
Jitter
RMS Phase Jitter (random)
T_phj
–
0.31
0.45
ps
F_nom = 20 MHz, Integration bandwidth = 12 kHz to 5 MHz
Phase Noise
1 Hz offset
–
-74
-68
dBc/Hz
F_nom = 20 MHz
TCXO and DCTCXO modes, and VCTCXO mode with
±6.25 ppm pull range
10 Hz offset
–
-102
-97
dBc/Hz
100 Hz offset
–
-121
-117
dBc/Hz
1 kHz offset
–
-142
-140
dBc/Hz
10 kHz offset
–
-148
-146
dBc/Hz
100 kHz offset
–
-149
-145
dBc/Hz
1 MHz offset
–
-162
-159
dBc/Hz
5 MHz offset
–
-164
-160
dBc/Hz
Spurious
T_spur
–
-109
-104
dBc
F_nom = 20 MHz, 1 kHz to 5 MHz offsets
SiT5155 ±0.5 ppm, Elite Platform™ Super-TCXO for GNSS/GPS
Rev 1.04
Page 7 of 38
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Table 6. Jitter & Phase Noise – LVCMOS, -40°C to 105°C
Parameters
Symbol
Min.
Typ.
Max.
Unit
Condition
Jitter
RMS Phase Jitter (random)
T_phj
–
0.31
0.48
ps
F_nom = 10 MHz, Integration bandwidth = 12 kHz to 5 MHz
RMS Period Jitter
T_jitt_per
–
0.8
1.1
ps
F_nom = 10 MHz, population 10 k
Peak Cycle-to-Cycle Jitter
T_jitt_cc
–
6
9
ps
F_nom = 10 MHz, population 1 k, measured as absolute
value
Phase Noise
1 Hz offset
–
-80
-74
dBc/Hz
F_nom = 10 MHz
TCXO and DCTCXO modes, and VCTCXO mode with
±6.25 ppm pull range
10 Hz offset
–
-108
-102
dBc/Hz
100 Hz offset
–
-127
-123
dBc/Hz
1 kHz offset
–
-148
-145
dBc/Hz
10 kHz offset
–
-154
-151
dBc/Hz
100 kHz offset
–
-154
-150
dBc/Hz
1 MHz offset
–
-167
-162
dBc/Hz
5 MHz offset
–
-168
-163
dBc/Hz
Spurious
T_spur
–
-112
-101
dBc
F_nom = 10 MHz, 1 kHz to 5 MHz offsets, Vdd = 2.5 V
–
-112
-106
dBc
F_nom = 10 MHz, 1 kHz to 5 MHz offsets, Vdd = 2.8 V,
3.0 V, 3.3 V
Table 7. Jitter & Phase Noise – Clipped Sinewave, -40°C to 105°C
Parameters
Symbol
Min.
Typ.
Max.
Unit
Condition
Jitter
RMS Phase Jitter (random)
T_phj
–
0.31
0.46
ps
F_nom = 20 MHz, Integration bandwidth = 12 kHz to 5 MHz
Phase Noise
1 Hz offset
–
-74
-68
dBc/Hz
F_nom = 20 MHz
TCXO and DCTCXO modes, and VCTCXO mode with
±6.25 ppm pull range
10 Hz offset
–
-102
-97
dBc/Hz
100 Hz offset
–
-121
-117
dBc/Hz
1 kHz offset
–
-142
-140
dBc/Hz
10 kHz offset
–
-148
-146
dBc/Hz
100 kHz offset
–
-149
-145
dBc/Hz
1 MHz offset
–
-162
-158
dBc/Hz
5 MHz offset
–
-164
-159
dBc/Hz
Spurious
T_spur
–
-109
-103
dBc
F_nom = 20 MHz, 1 kHz to 5 MHz offsets
SiT5155 ±0.5 ppm, Elite Platform™ Super-TCXO for GNSS/GPS
Rev 1.04
Page 8 of 38
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Table 8. Absolute Maximum Limits
Attempted operation outside the absolute maximum ratings may cause permanent damage to the part.
Actual performance of the IC is only guaranteed within the operational specifications, not at absolute maximum ratings.
Parameter
Test Conditions
Value
Unit
Storage Temperature
-65 to 125
°C
Continuous Power Supply Voltage Range (Vdd)
-0.5 to 4
V
Human Body Model (HBM) ESD Protection
JESD22-A114
2000
V
Soldering Temperature (follow standard Pb-free soldering guidelines)
260
°C
Junction Temperature[4]
130
°C
Input Voltage, Maximum
Any input pin
Vdd + 0.3
V
Input Voltage, Minimum
Any input pin
-0.3
V
Note:
4. Exceeding this temperature for an extended period of time may damage the device.
Table 9. Thermal Considerations[5]
Package
JA[6] (°C/W)
JC, Bottom (°C/W)
Ceramic 5.0 mm x 3.2 mm
54
15
Note:
5. Measured in still air. Refer to JESD51 for θJA and θJC definitions.
6. Devices soldered on a JESD51 2s2p compliant board.
Table 10. Maximum Operating Junction Temperature[7]
Max Operating Temperature (ambient)
Maximum Operating Junction Temperature
70°C
80°C
85°C
95°C
105°C
115°C
Note:
7. Datasheet specifications are not guaranteed if junction temperature exceeds the maximum operating junction temperature.
Table 11. Environmental Compliance
Parameter
Test Conditions
Value
Unit
Mechanical Shock Resistance
MIL-STD-883F, Method 2002
30000
g
Mechanical Vibration Resistance
MIL-STD-883F, Method 2007
70
g
Temperature Cycle
JESD22, Method A104
–
–
Solderability
MIL-STD-883F, Method 2003
–
–
Moisture Sensitivity Level
MSL1 @260°C
–
–
SiT5155 ±0.5 ppm, Elite Platform™ Super-TCXO for GNSS/GPS
Rev 1.04
Page 9 of 38
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Device Configurations and Pin-outs
Table 12. Device Configurations
Configuration
Pin 1
Pin 5
I2C Programmable Parameters
TCXO
OE/NC
NC
–
VCTCXO
VC
NC
–
DCTCXO
OE/NC
A0/NC
Frequency Pull Range, Frequency Pull Value, Output Enable control.
Pin-out Top Views
OE/NC 1
2
3
456
7
8
910
NC
NC
GND
NC
NC
VDD
CLK
NC
NC
Figure 3. TCXO
VC 1
2
3
456
7
8
910
NC
NC
GND
NC
NC
VDD
CLK
NC
NC
Figure 4. VCTCXO
OE / NC 1
2
3
456
7
8
910
SCL
NC
GND
NC
NC
VDD
CLK
A0 / NC
SDA
Figure 5. DCTCXO
Table 13. Pin Description
Pin
Symbol
I/O
Internal Pull-up/Pull Down
Resistor
Function
1
OE/NC[10]/VC
OE – Input
100 kΩ Pull-Up
H[8]: specified frequency output
L: output is high impedance. Only output driver is disabled.
NC – No Connect
–
H or L or Open: No effect on output frequency or other device functions
VC – Input
–
Control Voltage in VCTCXO Mode
2
SCL/NC[10]
SCL – Input
200 kΩ Pull-Up
I2C serial clock input.
No Connect
H or L or Open: No effect on output frequency or other device functions
3
NC[10]
No Connect
–
H or L or Open: No effect on output frequency or other device functions
4
GND
Power
–
Connect to ground
5
A0/NC[10]
A0 – Input
100 kΩ Pull-Up
Device I2C address when the address selection mode is via the A0 pin.
This pin is NC when the I2C device address is specified in the ordering
code.
A0 Logic Level I2C Address
0 1100010
1 1101010
NC – No Connect
–
H or L or Open: No effect on output frequency or other device functions.
6
CLK
Output
–
LVCMOS, or clipped sinewave oscillator output
7
NC[10]
No Connect
–
H or L or Open: No effect on output frequency or other device functions
8
NC[10]
No Connect
–
H or L or Open: No effect on output frequency or other device functions
9
VDD
Power
–
Connect to power supply[9]
10
SDA/NC[10]
SDA – Input/Output
200 kΩ Pull Up
I2C Serial Data.
NC – No Connect
–
H or L or Open: No effect on output frequency or other device functions.
Notes:
8. In OE mode for noisy environments, a pull-up resistor of 10 kΩ or less is recommended if pin 1 is not externally driven. If pin 1 needs to be left floating, use
the NC option.
9. A 0.1 μF capacitor in parallel with a 10 μF capacitor are required between VDD and GND. The 0.1 μF capacitor is recommended to place close to the
device, and place the 10 μF capacitor less than 2 inches away.
10. All NC pins can be left floating and do not need to be soldered down.
SiT5155 ±0.5 ppm, Elite Platform™ Super-TCXO for GNSS/GPS
Rev 1.04
Page 10 of 38
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Test Circuit Diagrams for LVCMOS and Clipped Sinewave Outputs
9 8 7 6
1 2 3 4
510
Power
Supply
VDD Test Point
Vdd
OE Function
CLK
15pF
(including probe
and fixture
capacitance)
10µF
0.1µF
+
-
10µF
0.1µF 9 8 7 6
1 2 3 4
510
Power
Supply
VDD CLK Test Point
Vdd
OE Function
10kΩ
(including probe
and fixture
resistance and
capacitance)
10pF
+
-
Figure 6. LVCMOS Test Circuit (OE Function)
Figure 7. Clipped Sinewave Test Circuit (OE Function)
for AC and DC Measurements
10µF
0.1µF
+
-
9 8 7 6
1 2 3 4
510
Power
Supply
VDD Test Point
Control
Voltage
VC Function
CLK
15pF
(including probe
and fixture
capacitance)
Figure 8. LVCMOS Test Circuit (VC Function)
9 8 7 6
2 3 4
510
Power
Supply
VDD CLK Test Point
1
Control
Voltage
VC Function
10kΩ
(including probe
and fixture
resistance and
capacitance)
10pF
10µF
0.1µF
+
-
Figure 9. Clipped Sinewave Test Circuit (VC Function)
for AC and DC Measurements
9 8 7 6
1 2 3 4
510
Power
Supply
VDD Test Point
Any state
or floating
NC Function
CLK
15pF
(including probe
and fixture
capacitance)
10µF
0.1µF
+
-
Figure 10. LVCMOS Test Circuit (NC Function)
9 8 7 6
2 3 4
510
Power
Supply
VDD CLK Test Point
10pF
1
Any state
or floating
NC Function
10kΩ
(including probe
and fixture
resistance and
capacitance)
10µF
0.1µF
+
-
Figure 11. Clipped Sinewave Test Circuit (NC Function)
for AC and DC Measurements
SiT5155 ±0.5 ppm, Elite Platform™ Super-TCXO for GNSS/GPS
Rev 1.04
Page 11 of 38
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Test Circuit Diagrams for LVCMOS and Clipped Sinewave Outputs (continued)
9 8 7 6
1 2 3 4
510
Power
Supply
VDD Test Point
Any state
or floating NC
Function
CLK
SCL
SDA[11]
15pF
(including probe
and fixture
capacitance)
10µF
0.1µF
+
-
A0/NC
Figure 12. LVCMOS Test Circuit (I2C Control), DCTCXO mode for AC and DC Measurements
9 8 7 6
1 2 3 4
510
Power
Supply
VDD Test Point
Any state
or floating NC
Function
CLK
SCL
SDA[11]
10pF 10kΩ
(including probe
and fixture
resistance and
capacitance)
10µF
0.1µF
+
-
A0/NC
Figure 13. Clipped Sinewave Test Circuit (I2C Control), DCTCXO mode for AC and DC Measurements
9 8 7 6
2 3 4
510
Power
Supply
VDD CLK
10pF
1
Any state
or floating
NC Function
10kΩ
(including probe
and fixture
resistance and
capacitance)
10µF
0.1µF
+
-
Test Point
A0/NC
Figure 14. Clipped Sinewave Test Circuit for Phase Noise Measurements, Applies to All Configurations
(NC Function shown for example only)
Note:
11. SDA is open-drain and may require pull-up resistor if not present in I2C test setup.
SiT5155 ±0.5 ppm, Elite Platform™ Super-TCXO for GNSS/GPS
Rev 1.04
Page 12 of 38
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Waveforms
90 % Vdd
50 % Vdd
10 % Vdd
tr tf
High Pulse
(TH) Low Pulse
(TL)
Period
Figure 15. LVCMOS Waveform Diagram[12]
tr tf
High Pulse
(TH) Low Pulse
(TL)
Period
20 % Vout
50 % Vout
80 % Vout
Vout
Figure 16. Clipped Sinewave Waveform Diagram[12]
Note:
12. Duty Cycle is computed as Duty Cycle = TH/Period.
SiT5155 ±0.5 ppm, Elite Platform™ Super-TCXO for GNSS/GPS
Rev 1.04
Page 13 of 38
www.sitime.com
Timing Diagrams
90% Vdd Vdd
Vdd Pin
Voltage
CLK Output
T_start
T_start: Time to start from power-off
HZ
Figure 17. Startup Timing
50% Vdd
Vdd
OE Voltage
CLK Output
T_oe
T_oe: Time to re-enable the clock output
HZ
Figure 18. OE Enable Timing (OE Mode Only)
SiT5155 ±0.5 ppm, Elite Platform™ Super-TCXO for GNSS/GPS
Rev 1.04
Page 14 of 38
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Typical Performance Plots
Figure 19. Duty Cycle (LVCMOS)
Figure 20. Rise Time (LVCMOS)
Figure 21. IDD TCXO (LVCMOS)
Figure 22. IDD VCTCXO (LVCMOS)
Figure 23. RMS Phase Jitter, TCXO & DCTCXO (LVCMOS)
Figure 24. RMS Period Jitter (LVCMOS)
Figure 25. IDD DCTCXO (LVCMOS)
Figure 26. RMS Phase Jitter, VCTCXO (LVCMOS)
45
47
49
51
53
55
10 15 20 25 30 35 40
Duty cycle (%)
Frequency (MHz)
2.5 V 2.8 V 3.0 V 3.3 V
0,90
0,95
1,00
1,05
1,10
1,15
1,20
1,25
10 15 20 25 30 35 40
Rise time (ns)
Frequency (MHz)
2.5 V 2.8 V 3.0 V 3.3 V
40
41
42
43
44
45
46
47
48
10 15 20 25 30 35 40
Current consumption (mA)
Frequency (MHz)
2.5 V 2.8 V 3.0 V 3.3 V
44
45
46
47
48
49
50
51
52
10 20 30 40 50 60
Current consumption (mA)
Frequency (MHz)
2.5 V 2.8 V 3.0 V 3.3 V
0
100
200
300
400
500
10 15 20 25 30 35 40
Phase Jitter (fs RMS)
Frequency (MHz)
2.5 V 2.8 V 3.0 V 3.3 V
0,50
0,70
0,90
1,10
1,30
1,50
1,70
1,90
10 15 20 25 30 35 40
Period Jitter (ps RMS)
Frequency (MHz)
2.5 V 3.3 V
40
41
42
43
44
45
46
47
48
10 15 20 25 30 35 40
Current consumption (mA)
Frequency (MHz)
2.5 V 2.8 V 3.0 V 3.3 V
0
100
200
300
400
500
10 15 20 25 30 35 40
Phase Jitter (fs RMS)
Frequency (MHz)
2.5 V 2.8 V 3.0 V 3.3 V