October 2013
©2012 Fairchild Semiconductor Corporation
FDME820NZT Rev.C2 www.fairchildsemi.com
1
FDME820NZT N-Channel PowerTrench® MOSFET
FDME820NZT
N-Channel PowerTrench® MOSFET
20 V, 9 A, 18 mΩ
Features
Max rDS(on) = 18 mΩ at VGS = 4.5 V, ID = 9 A
Max rDS(on) = 24 mΩ at VGS = 2.5 V, ID = 7.5 A
Max rDS(on) = 32 mΩ at VGS = 1.8 V, ID = 7 A
Low profile: 0.55 mm maximum in the new package
MicroFET 1.6x1.6 Thin
Free from halogenated compounds and antimony oxides
HBM ESD protection level >2.5 kV (Note3)
RoHS Compliant
General Description
This Single N-Channel MOSFET has been designed using
Fairchild Semiconductor’s advanced Power Trench process to
optimize the rDS(ON) @ VGS = 1.8 V on special MicroFET
leadframe.
Applications
Li-lon Battery Pack
Baseband Switch
Load Switch
DC-DC Conversion
MicroFET 1.6x1.6 Thin
G
D
D
TOP
BOTTOM
Pin 1 D
G
DS
D
DS
D
D
S
MOSFET Maximum Ratings TA = 25 °C unless otherwise noted
Thermal Characteristics
Package Marking and Ordering Information
Symbol Parameter Ratings Units
VDS Drain to Source Voltage 20 V
VGS Gate to Source Voltage ±12 V
IDDrain Current -Continuous TA = 25 °C (Note 1a) 9 A
-Pulsed 40
PDPower Dissipation for Single Operation TA = 25 °C (Note 1a) 2.1 W
Power Dissipation for Single Operation TA = 25 °C (Note 1b) 0.7
TJ, TSTG Operating and Storage Junction Temperature Range -55 to +150 °C
RθJA Thermal Resistance, Junction to Ambient (Note 1a) 70 °C/W
RθJA Thermal Resistance, Junction to Ambient (Note 1b) 190
Device Marking Device Package Reel Size Tape Width Quantity
8T FDME820NZT MicroFET 1.6x1.6 Thin 7 ’’ 8 mm 5000 units
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2
FDME820NZT N-Channel PowerTrench® MOSFET
©2012 Fairchild Semiconductor Corporation
FDME820NZT Rev.C2
Electrical Characteristics TJ = 25 °C unless otherwise noted
Off Characte ristics
On Characteristics
Dynamic Characteristics
Switching Characteristics
Drain-Source Diode Characteristics
Symbol Parameter Test Conditions Min Typ Max Units
BVDSS Drain to Source Breakdown Voltage ID = 250 μA, VGS = 0 V 20 V
ΔBVDSS
ΔTJ
Breakdown Voltage Temperature
Coefficient ID = 250 μA, referenced to 25 °C 20 mV/°C
IDSS Zero Gate Voltage Drain Current VDS = 16 V, VGS = 0 V 1 μA
IGSS Gate to Source Leakage Current VGS = ±12 V, VDS = 0 V ±10 μA
VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 250 μA 0.5 0.8 1.0 V
ΔVGS(th)
ΔTJ
Gate to Source Threshold Voltage
Temperature Coefficient ID = 250 μA, referenced to 25 °C -3 mV/°C
rDS(on) Drain to Source On Resistance
VGS = 4.5 V, ID = 9 A 14 18
mΩ
VGS = 2.5 V, ID = 7.5 A 17 24
VGS = 1.8 V, ID = 7 A 26 32
VGS = 4.5 V, ID = 9 A ,
TJ = 125 °C 19 24
Ciss Input Capacitance VDS = 10 V, VGS = 0 V,
f = 1 MHz
865 pF
Coss Output Capacitance 203 pF
Crss Reverse Transfer Capacitance 190 pF
RgGate Resistance 1.0 Ω
td(on) Turn-On Delay Time VDD = 10 V, ID = 4 A
VGS = 4.5 V, RGEN = 2 Ω
9ns
trRise Time 5ns
td(off) Turn-Off Delay Time 19 ns
tfFall Time 5ns
QgTotal Gate Charge VDD = 4.2 V, ID = 3 A, VGS = 4.3 V 8.0 nC
QgTotal Gate Charge VDD = 4.2 V, ID = 3 A, VGS = 4.5 V 8.5 nC
Qgs Gate to Source Gate Charge VDD = 10 V, ID = 9 A 1.4 nC
Qgd Gate to Drain “Miller” Charge 3.2 nC
VSD Source to Drain Diode Forward Voltage VGS = 0 V, IS = 1.6 A (Note 2) 0.7 1.2 V
VGS = 0 V, IS = 9 A (Note 2) 0.8 1.2 V
trr Reverse Recovery Time IF = 9 A, di/dt = 100 A/us 18 ns
Qrr Reverse Recovery Charge 4 nC
Notes:
1. RθJA is determined with the device mounted on a 1 in2 pad 2 oz copper pad o n a 1.5 x 1.5 in. board of FR-4 m aterial. RθJC is guaranteed by design while RθCA is determined by
the user's board design.
2. Pulse Test: Pulse Width < 300μs, Duty cycle < 2.0%.
3. The diode connected between the gate and source serves only as protection ESD. No gate overvoltage rating is implied.
a. 70 °C/W when mounte d on
a 1 in2 pad of 2 oz copper. b. 190 °C/W whe n mounte d on a
minimum pad of 2 oz copper.
G
DF
DS
SF
SS
G
DF
DS
SF
SS
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3
FDME820NZT N-Channel PowerTrench® MOSFET
©2012 Fairchild Semiconductor Corporation
FDME820NZT Rev.C2
Typical Characteristics TJ = 25 °C unless otherwise noted
Figure 1.
0 0.5 1.0 1.5 2.0 2.5
0
10
20
30
40
VGS = 1.5 V
VGS = 2.5 V
VGS = 1.8 V
VDS, DRAIN TO SOURCE VOLTAGE (V)
ID, DRAIN CURRENT (A)
VGS = 4.5 V
VGS = 3 V
VGS = 2 V
PULSE DU R ATION = 80 μs
DUTY CYCLE = 0.5% MA X
On Region Characteristics Figure 2.
0 10203040
0
1
2
3
4
5
VGS = 2 V
VGS = 1.5 V
VGS = 2.5 V
PULSE D U RA TION = 80 μs
DUTY CYCLE = 0.5% MAX
NORMALIZED
DRAIN TO SOU RC E ON-RESISTA NCE
ID, DRA IN CURRENT (A)
VGS = 4.5 V
VGS = 3 V
VGS = 1.8 V
Normalized On-Resistance
vs Drain Current and Gate Voltage
Figure 3. Normalized On Resistance
-75 -50 -25 0 25 50 75 100 125 150
0.6
0.8
1.0
1.2
1.4
1.6
ID = 9 A
VGS = 4.5 V
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
TJ, JUNCTION TEMPER ATURE (oC)
vs Junction Te mperature Figure 4.
0.91.82.73.64.5
0
20
40
60
80
TJ = 125 oC
ID = 9 A
TJ = 25 oC
VGS, GA TE TO SOU RC E VO LTA GE (V)
rDS(on), DRAIN T O
SOURCE ON-RESISTANCE (mΩ)
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
On-Resistance vs Gate to
Source Voltage
Figure 5. Transfer Characteristics
0.0 0.5 1.0 1.5 2.0 2.5 3.0
0
10
20
30
40
TJ = 150 oC
VDS = 5 V
PULSE D U R ATION = 80 μs
DUTY CYCLE = 0.5% MAX
TJ = -55 oC
TJ = 25 oC
ID, DRAIN CURRENT (A)
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 6.
0 0.2 0.4 0.6 0.8 1.0 1.2
0.001
0.01
0.1
1
10
100
1000
TJ = -55 oC
TJ = 25 oC
TJ = 150 oC
VGS = 0 V
IS, REVERSE DRAIN CURRENT (A)
VSD, BODY DIODE FORWARD VOLTAGE (V)
Source to Drain Diode
Forward Voltage vs Source Current
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4
FDME820NZT N-Channel PowerTrench® MOSFET
©2012 Fairchild Semiconductor Corporation
FDME820NZT Rev.C2
Figure 7.
036912
0.0
0.9
1.8
2.7
3.6
4.5 ID = 9 A
VDD = 12 V
VDD = 10 V
VGS, GATE TO SOURCE VOLTAGE (V)
Qg, GATE CHARGE (nC)
VDD = 8 V
Gate Charge Characteristics Figure 8.
0.1 1 10 20
100
1000
2000
f = 1 MHz
VGS = 0 V
CAPACITANCE (pF)
VDS, DRAIN TO SOURCE VOLTAGE (V)
Crss
Coss
Ciss
Capacitance vs Drain
to Source Voltage
Figure 9.
0.001 0.01 0.1 1 10 100
1
10
20
TJ = 100 oC
TJ = 25 oC
TJ = 125 oC
tAV, TIME IN AVALANCHE (ms)
IAS, AVALANCHE CURRENT (A)
Unc l amp e d Ind u ctiv e
Switching Capability Figure 10.
0369121518
10-10
10-9
10-8
10-7
10-6
10-5
10-4
10-3
10-2
10-1
VGS = 0 V
TJ = 125 oC
TJ = 25 oC
VGS, GATE TO SOUR C E VO LTAGE (V)
Ig, GATE LEAKAGE CURRENT (A)
Gate Leakage Current vs Gate
to Source Voltage
Figure 11. Forward Bias Safe
Operating Are a
0.01 0.1 1 10 100
0.01
0.1
1
10
100
100 us
1 ms
1 s
10 ms
DC
10 s
100 ms
ID, DRAIN CURRENT (A)
VDS, DRAIN to SOURCE VOLTAGE (V)
THIS AREA IS
LIMITED BY rDS(on)
SINGLE PULSE
TJ = MAX RATED
RθJA = 190 oC/W
TA = 25 oC
Figure 12.
10-4 10-3 10-2 10-1 110
100 1000
0.1
1
10
100
1000
SINGLE PULSE
RθJA = 190 oC/W
TA = 25 oC
P(PK), PEAK TRANSIENT POW ER (W )
t, PULSE WIDTH (s)
Single Pulse Maximum
Power Dissipation
Typical Characteristics TJ = 25 °C unless otherwise noted
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5
FDME820NZT N-Channel PowerTrench® MOSFET
©2012 Fairchild Semiconductor Corporation
FDME820NZT Rev.C2
Figure 13.
10-4 10-3 10-2 10-1 110
100 1000
0.001
0.01
0.1
1
SINGLE PULSE
RθJA = 190 oC/W
DUTY CYCLE-DESCENDING ORDER
NORMALIZED THERMAL
IMPEDANCE, ZθJA
t, RECTANGULAR PULSE DURATION (s)
D = 0.5
0.2
0.1
0.0 5
0.0 2
0.0 1
2
PDM
t1t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + TA
Junction-to-Ambient Transient Thermal Response Curve
Typical Characteristics TJ = 25 °C unless otherwise noted
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6
FDME820NZT N-Channel PowerTrench® MOSFET
©2012 Fairchild Semiconductor Corporation
FDME820NZT Rev.C2
Dimensional Outline and Pad Layout
FDME820NZT N-Channel PowerTrench® MOSFET
www.fairchildsemi.com
7
©2012 Fairchild Semiconductor Corpo ration
FDME820NZT Rev.C2
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®
™
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Rev. I66
tm
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