REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
AD7801
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 World Wide Web Site: http://www.analog.com
Fax: 617/326-8703 © Analog Devices, Inc., 1997
+2.7 V to +5.5 V, Parallel Input,
Voltage Output 8-Bit DAC
FUNCTIONAL BLOCK DIAGRAM
INPUT
REGISTER DAC
REGISTER I DAC
÷
2
POWER-ON
RESET
AD7801
V
OUT
AGND
PD CLR LDAC REFIN V
DD
DGND
D7
D0
WR
CS
I/V
MUX
CONTROL
LOGIC
FEATURES
Single 8-Bit DAC
20-Pin SOIC/TSSOP Package
+2.7 V to +5.5 V Operation
Internal and External Reference Capability
DAC Power-Down Function
Parallel Interface
On-Chip Output Buffer Rail-to-Rail Operation
Low Power Operation 1.75 mA max @ 3.3 V
Power-Down to 1 mA max @ 258C
APPLICATIONS
Portable Battery Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators
GENERAL DESCRIPTION
The AD7801 is a single, 8-bit, voltage out DAC that operates
from a single +2.7 V to +5.5 V supply. Its on-chip precision output
buffer allows the DAC output to swing rail to rail. The AD7801
has a parallel microprocessor and DSP compatible interface with
high speed registers and double buffered interface logic. Data is
loaded to the input register on the rising edge of CS or WR.
Reference selection for the AD7801 can be either an internal
reference derived from the V
DD
or an external reference applied
at the REFIN pin. The output of the DAC can be cleared by
using the asynchronous CLR input.
The low power consumption of this part makes it ideally suited
to portable battery operated equipment. The power consump-
tion is less than 5 mW at 3.3 V, reducing to less than 3 µW in
power-down mode.
The AD7801 is available in a 20-lead SOIC and a 20-lead
TSSOP package.
PRODUCT HIGHLIGHTS
1. Low Power, Single Supply operation. This part operates
from a single +2.7 V to +5.5 V supply and consumes typically
5 mW at 3 V, making it ideal for battery powered applications.
2. The on-chip output buffer amplifier allows the output of the
DAC to swing rail to rail with a settling time of typically 1.2 µs.
3. Internal or external reference capability.
4. High speed parallel interface.
5. Power-down capability. When powered down the DAC
consumes less than 1 µA at 25°C.
6. Packaged in 20-lead SOIC and TSSOP packages.
–2– REV. 0
AD7801–SPECIFICATIONS
(VDD = +2.7 V to +5.5 V, Internal Reference; CL = 100 pF, RL = 10 kV to VDD and GND.
All specifications TMIN to TMAX unless otherwise noted.)
Parameter B Versions
1
Units Conditions/Comments
STATIC PERFORMANCE
Resolution 8 Bits
Relative Accuracy
2
±1 LSB max
Differential Nonlinearity ±1 LSB max Guaranteed Monotonic
Zero-Code Error @ +25°C 3 LSB typ All Zeros Loaded to DAC Register
Full-Scale Error –0.75 LSB typ All Ones Loaded to DAC Register
Zero-Code Error Drift 100 µV/°C typ
Gain Error
3
±1 % FSR typ
DAC REFERENCE INPUT
REFIN Input Range 1 to V
DD
/2 V min/V max
REFIN Input Impedance 10 MΩ typ
OUTPUT CHARACTERISTICS
Output Voltage Range 0 to V
DD
V min/V max
Output Voltage Settling Time 2 µs max Typically 1.2 µs
Slew Rate 7.5 V/µs typ
Digital-to-Analog Glitch Impulse 1 nV-s typ 1 LSB Change Around Major Carry
Digital Feedthrough 0.2 nV-s typ
DC Output Impedance 40 Ω typ
Short Circuit Current 14 mA typ
Power Supply Rejection Ratio
4
0.0003 %/% max ∆V
DD
= ±10%
LOGIC INPUTS
Input Current ±10 µA max
V
INL
, Input Low Voltage 0.8 V max V
DD
= +5 V
V
INL
, Input Low Voltage 0.6 V max V
DD
= +3 V
V
INH
, Input High Voltage 2.4 V min V
DD
= +5 V
V
INH
, Input High Voltage 2.1 V min V
DD
= +3 V
Pin Capacitance 7 pF max
POWER REQUIREMENTS
V
DD
2.7/5.5 V min/V max
I
DD
(Normal Mode) DAC Active and Excluding Load Current
V
DD
= 3.3 V V
IH
= V
DD
and V
IL
= GND
@ 25°C 1.55 mA max See Figure 6
T
MIN
to T
MAX
1.75 mA max
V
DD
= 5.5 V
@ 25°C 2.35 mA max
T
MIN
to T
MAX
2.5 mA max
I
DD
(Power-Down)
@ 25°C1µA max V
IH
= V
DD
and V
IL
= GND
T
MIN
to T
MAX
2µA max See Figure 18
NOTES
1
Temperature ranges are as follows: B Version: –40°C to +105°C
2
Relative Accuracy is calculated using a reduced code range of 15 to 245.
3
Gain Error is specified between Codes 15 and 245. The actual error at Code 15 is typically 3 LSB.
4
Guaranteed by characterization at product release, not production tested.
Specifications subject to change without notice.
Figure 1. Timing Diagram for Parallel Data Write
t
1
t
2
t
4
t
3
t
5
t
6
t
7
t
8
CS
WR
D7-D0
LDAC
CLR
AD7801
–3–
REV. 0
TIMING CHARACTERISTICS
1, 2
Limit at T
MIN
, T
MAX
Parameter (B Version) Units Conditions/Comments
t
1
0 ns min Chip Select to Write Setup Time
t
2
0 ns min Chip Select to Write Hold Time
t
3
20 ns min Write Pulse Width
t
4
15 ns min Data Setup Time
t
5
4.5 ns min Data Hold Time
t
6
20 ns min Write to LDAC Setup Time
t
7
20 ns min LDAC Pulse Width
t
8
20 ns min CLR Pulse Width
NOTES
1
Sample tested at +25 °C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of
(V
IL
+ V
IH
)/2. tr and tf should not exceed 1 µs on any digital input.
2
See Figure 1.
WARNING!
ESD SENSITIVE DEVICE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7801 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS*
(T
A
= +25°C unless otherwise noted)
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Reference Input Voltage to AGND . . . .–0.3 V to V
DD
+ 0.3 V
Digital Input Voltage to DGND . . . . . .–0.3 V to V
DD
+ 0.3 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . .–0.3 V to +0.3 V
V
OUT
to AGND . . . . . . . . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
Operating Temperature Range
Commercial (B Version) . . . . . . . . . . . . . –40°C to +105°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
SSOP Package, Power Dissipation . . . . . . . . . . . . . . . 700 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . 143°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . .+215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 870 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 74°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . .+215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ORDERING GUIDE
Temperature Package
Model Range Option*
AD7801BR –40°C to +105°C R-20
AD7801BRU –40°C to +105°C RU-20
*R = Small Outline; RU = Thin Shrink Small Outline.
(VDD = +2.7 V to +5.5 V; GND = 0 V; Internal V DD/2 Reference. All specifications TMIN to TMAX
unless otherwise noted.)
AD7801
–4– REV. 0
PIN FUNCTION DESCRIPTIONS
Pin
No. Mnemonic Function
1–8 D7–D0 Parallel Data Inputs. 8-bit data is loaded to the input register of the AD7801 under the control of CS and WR.
9CS Chip Select. Active low logic input.
10 WR Write Input. WR is an active low logic input used in conjunction with CS to write data to the input register.
11 DGND Digital Ground
12 PD Active low input used to put the part into low power mode reducing current consumption to less than 1 µA.
13 LDAC Load DAC Logic Input. When this logic input is taken low the DAC output is updated with the contents of
its DAC register. If LDAC is permanently tied low the DAC is updated on the rising edge of WR.
14 CLR Asynchronous Clear Input (Active Low). When this input is taken low the DAC register is loaded with all
zeroes and the DAC output is cleared to zero volts.
15 V
DD
Power Supply Input. This part can be operated from +2.7 V to +5.5 V and should be decoupled to GND.
16 REFIN External Reference Input. This can be used as the reference for the DAC. The range on this reference input is
1 V to V
DD
/2. If REFIN is tied directly to V
DD
the internal V
DD
/2 reference is selected.
17 AGND Analog Ground reference point and return point for all analog current on the part.
18 NC No Connect Pin.
19 V
OUT
Analog Output Voltage from the DAC. The output amplifier can swing rail to rail on its output.
20 DGND Digital Ground reference point and return point for all digital current on the part.
PIN CONFIGURATION
14
13
12
11
17
16
15
20
19
18
10
9
8
1
2
3
4
7
6
5
TOP VIEW
(Not to Scale)
AD7801
NC = NO CONNECT
(MSB) DB7
AGND
NC
V
OUT
DGND
DB6
DB5
DB4
CLR
V
DD
REFINDB3
DB2
DB1
(LSB) DB0
CS
WR DGND
PD
LDAC
AD7801
–5–
REV. 0
SINK CURRENT – mA
VOUT – mV
800
008
24 6
720
400
240
160
80
640
560
320
480
VDD = 5V AND 3V
INTERNAL REFERENCE
TA = +25 C
DAC LOADED WITH 00HEX
Figure 2. Output Sink Current Capa-
bility with V
DD
= 3 V and V
DD
= 5 V
REFERENCE VOLTAGE – Volts
ERROR – LSBs
0.5
01.0 1.2 2.8
1.4 1.6 1.8 2.2 2.4 2.62.0
0.45
0.25
0.15
0.1
0.05
0.4
0.35
0.2
0.3
V
DD
= 5V
T
A
= +25 C
INL ERROR
DNL ERROR
Figure 5. Relative Accuracy vs.
External Reference
FREQUENCY – Hz
ATTENUATION – dB
1 10 10k100 1k
10
5
–40
0
–5
–10
–15
–20
–25
–30
–35
VDD = 5V
EXTERNAL SINEWAVE REFERENCE
DAC REGISTER LOADED WITH FFHEX
TA = +25°C
Figure 8. Large Scale Signal
Frequency Response
Typical Performance Characteristics–
SOURCE CURRENT – mA
V
OUT
–
Volts
02 846
5
4.92
4.2
4.84
4.76
4.68
4.6
4.52
4.44
4.36
4.28
V
DD
= 5V
INTERNAL REFERENCE
DAC REGISTER LOADED
WITH FFHEX
T
A
= +25°C
Figure 3. Output Source Current
Capability with V
DD
= 5 V
–50 –25 100
TEMPERATURE – C
3.5
2.0
I
DD
– mA
4.0
3.0
2.5
INTERNAL REFERENCE
LOGIC INPUTS = V
DD
OR GND
DAC ACTIVE
V
DD
= 5.5V
V
DD
= 3.3V
1.5
1.0
0.5
00 255075 125
Figure 6. Typical Supply Current
vs. Temperature
T
←
V
OUT
V
DD
= 3V
INTERNAL VOLTAGE
REFERENCE
FULL SCALE CODE
CHANGE 00H-FFH
T
A
= +25°C
1
←
3
←
2
←
V
OUT
CH1 5V, CH2 1V, CH3 20mV
TIME BASE = 200 ns/Div
WR
Figure 9. Full-Scale Settling Time
SOURCE CURRENT – mA
3.5
1.0 01 8234567
3.25
2.5
2.25
1.75
1.25
3.0
2.75
2.0
1.5
V
OUT
– Volts
V
DD
= 3V
INTERNAL REFERENCE
DAC REGISTER LOADED
WITH FFHex
T
A
= +25°C
Figure 4. Output Source Current
Capability with V
DD
= 3 V
V
DD
– Volts
I
DD
– mA
3.0
1.0
4.0
2.5 3.0 5.53.5 4.0 4.5 5.0
LOGIC INPUTS = V
DD
OR GND
LOGIC INPUTS = V
IH
OR V
IL
DAC ACTIVE
INTERNAL REFERENCE
T
A
= +25°C
2.0
0
Figure 7. Typical Supply Current
vs. Supply Voltage
PD
V
OUT
AD7801 POWER-UP TIME
V
DD
= 5V
INTERNAL REFERENCE
DAC IN POWER-DOWN INITIALLY
1
←
2←
CH1 = 2V/div, CH2 = 5V/Div,
TIME BASE = 2 µs/Div
Figure 10. Exiting Power-Down (Full
Power-Down)
AD7801
–6– REV. 0
1
2
M20.0ms
VOUT
VDD
CH1 5.00V CH2 5.00V CH1
T
T
Figure 11. Power-On—Reset
INPUT CODE (15 to 245)
INL ERROR – LSB
0 25632 64 96 128 160 192 224
–0.5
0.4
0.1
–0.1
–0.3
–0.4
0.3
0.2
0
–0.2
0.5 V
DD
= 5V
INTERNAL REFERENCE
5kΩ 100pF LOAD
LIMITED CODE RANGE (15–245)
T
A
= +25°C
Figure 14. Integral Linearity Plot
–Typical Performance Characteristics
–25
4
0
7
6
2
1
5
3
8
9
10
–50 0 25 50 75 100 125
TEMPERATURE – C
ZERO CODE ERROR – LSB
VDD = 2.7 TO 5.5V
DAC LOADED WITH ALL ZEROES
INTERNAL REFERENCE
Figure 12. Zero Code Error vs.
Temperature
V
DD
= 5V
INTERNAL REFERENCE
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
–60 –40 –20 0 20 40 60 80 100 120 140
INL ERROR – LSB
TEMPERATURE – C
Figure 15. Typical INL vs. Temperature
2
←
1
←
WR
V
OUT
V
DD
= 5V
INTERNAL VOLTAGE
REFERENCE
10 LSB STEP CHANGE
T
A
= +258C
CH1 5.00V, CH2 50.0mV, M 250ns
Figure 13. Small-Scale Settling Time
V
DD
= 5V
INTERNAL REFERENCE
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
–60 –40 –20 0 20 40 60 80 100 120 140
TEMPERATURE – C
DNL ERROR – LSB
Figure 16. Typical DNL vs. Temperature
V
DD
= 5V
0.6
0.4
0.2
0
–60 –40 –20 0 20 40 60 80 100 120 140
TEMPERATURE – C
INT REFERENCE ERROR – %
0.8
1.0
Figure 17. Typical Internal Reference
Error vs. Temperature
TEMPERATURE – C
0
–50 –25 150
V
DD
= 5V
LOGIC INPUTS = V
DD
OR GND
100
200
300
400
500
600
700
800
900
1000
POWER DOWN CURRENT – nA
0255075100
Figure 18. Power-Down Current vs.
Temperature
AD7801
–7–
REV. 0
TERMINOLOGY
Integral Nonlinearity
For the DAC, Relative Accuracy or End-Point nonlinearity is a
measure of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer
function. A graphical representation of the transfer curve is
shown in Figure 14.
Differential Nonlinearity
Differential Nonlinearity is the difference between the mea-
sured change and the ideal 1 LSB change between any two
adjacent codes. A specified differential nonlinearity of ±1 LSB
maximum ensures monotonicity.
Zero-Code Error
Zero-Code Error is the measured output voltage from V
OUT
of
the DAC when zero code (all zeros) is loaded to the DAC
latch. It is due to a combination of the offset errors in the DAC
and output amplifier. Zero-code error is expressed in LSBs.
Gain Error
This is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from ideal
expressed as a percent of the full-scale value. It includes full-
scale errors but not offset errors.
Digital-to-Analog Glitch Impulse
Digital-to-Analog Glitch Impulse is the impulse injected into
the analog output when the digital inputs change state with
the DAC selected and the LDAC used to update the DAC. It
is normally specified as the area of the glitch in nV-secs and
measured when the digital input code is changed by 1 LSB at
the major carry transition.
Digital Feedthrough
Digital Feedthrough is a measure of the impulse injected into
the analog output of a DAC from the digital inputs of the same
DAC, but is measured when the DAC is not updated. It is
specified in nV-secs and measured with a full-scale code change
on the data bus, i.e., from all 0s to all 1s and vice versa.
Power Supply Rejection Ratio (PSRR)
This specification indicates how the output of the DAC is affected
by changes in the power supply voltage. Power supply rejection
ratio is quoted in terms of % change in output per % change in
V
DD
for full-scale output of the DAC. V
DD
is varied ±10%.
GENERAL DESCRIPTION
D/A Section
The AD7801 is an 8-bit voltage output digital-to-analog con-
verter. The architecture consists of a reference amplifier and a
current source DAC followed by a current-to-voltage converter
capable of generating rail-to-rail voltages on the output of the
DAC. Figure 19 shows a block diagram of the basic DAC
architecture.
AD7801
V
OUT
REFIN I/V
11.7kΩ
11.7kΩ
CURRENT
DAC
30kΩ
30kΩ
V
DD
REFERENCE
AMPLIFIER
Figure 19. DAC Architecture
The DAC output is internally buffered and has rail-to-rail
output characteristics. The output amplifier is capable of driving
a load of 100 pF and 10 kΩ to both V
DD
and ground. The
reference selection for the DAC can be either internally gener-
ated from V
DD
or externally applied through the REFIN pin. A
comparator on the REFIN pin detects whether the required
reference is the internally generated reference or the externally
applied voltage to the REFIN pin. If REFIN is connected to
V
DD
, the reference selected is the internally generated V
DD
/2
reference. When an externally applied voltage is more than one
volt below V
DD
, the comparator selection switches to the externally
applied voltage on the REFIN pin. The range on the external
reference input is from 1.0 V to V
DD
/2 V. The output voltage
from the DAC is given by:
VO=2VREF ×N
256
where V
REF
is the voltage applied to the external REFIN pin or
V
DD
/2 when the internal reference is selected. N is the decimal
equivalent of the code loaded to the DAC register and ranges
from 0 to 255.
VTH
PMOS
MUX
INT
REF
COMPARATOR
SELECTED REFERENCE
OUTPUT
VDD
REFIN
INT REF
EXT REF
Figure 20. Reference Selection Circuitry
AD7801
–8– REV. 0
Reference
The AD7801 has the ability to use either an external reference
applied through the REFIN pin or an internal reference generated
from V
DD
. Figure 20 shows the reference input arrangement
where either the internal V
DD
/2 or the externally applied reference
can be selected.
The internal reference is selected by tying the REFIN pin to
V
DD
. If an external reference is to be used, this can be directly
applied to the REFIN pin and if this is 1 V below V
DD
, the
internal circuitry will select this externally applied reference as
the reference source for the DAC.
Digital Interface
The AD7801 contains a fast parallel interface allowing this
DAC to interface to industry standard microprocessors,
microcontrollers and DSP machines. There are two modes in
which this parallel interface can be configured to update the
DAC output. The synchronous update mode allows synchro-
nous updating of the DAC output; the automatic update mode
allows the DAC to be updated individually following a write
cycle. Figure 21 shows the internal logic associated with the
digital interface. The PON STRB signal is internally generated
from the power-on reset circuitry and is low during the power-
on reset phase of the power up procedure.
CLEAR
SET SLE
LDAC
ENABLE
DAC CONTROL
LOGIC
MLE
SLE
CLR
PON STRB
CLR
LDAC
CS
WR
Figure 21. Logic Interface
The AD7801 has a double buffered interface, which allows for
synchronous updating of the DAC output. Figure 22 shows a
block diagram of the register arrangement within the AD7801.
MLE SLE
CONTROL LOGIC
CS
WR
LDAC
CLR
415 15 30
8
INPUT
REGISTER
4 TO 15
DECODER
DAC
REGISTER
415 15 30
4 TO 15
DECODER
DAC
REGISTER
DRIVERS
LOWER
NIBBLE
UPPER
NIBBLE
DB7-DB0
DRIVERS
Figure 22. Register Arrangement
Automatic Update Mode
In this mode of operation the LDAC signal is permanently tied
low. The state of the LDAC is sampled on the rising edge of
WR. LDAC being low allows the DAC register to be automati-
cally updated on the rising edge of WR. The output update
occurs on the rising edge of WR. Figure 23 shows the timing
associated with the automatic update mode of operation and
also the status of the various registers during this frame.
HOLD HOLD
TRACK TRACK
D7-D0
WR
CS
LDAC = 0
I/P REG (MLE)
DAC REG (SLE)
V
OUT
TRACK
HOLD
Figure 23. Timing and Register Arrangement for Auto-
matic Update Mode
Synchronous Update Mode
In this mode of operation the LDAC signal is used to update the
DAC output to synchronize with other updates in the system.
The state of the LDAC is sampled on the rising edge of WR. If
LDAC is high, the automatic update mode is disabled and the
DAC latch is updated at any time after the write by taking
LDAC low. The output update occurs on the falling edge of
LDAC. LDAC must be taken back high again before the next
data transfer takes place. Figure 24 shows the timing associated
with the synchronous update mode of operation and also the
status of the various registers during this frame.
HOLD HOLD
D7-D0
WR
CS
LDAC
I/P REG (MLE)
DAC REG (SLE)
V
OUT
HOLD HOLDTRACK
TRACK
Figure 24. Timing and Register Arrangement for Synchro-
nous Update Mode
AD7801
–9–
REV. 0
V
OUT
=2×V
REF
N
256
where:
Nis the decimal equivalent of the binary input
code. N ranges from 0 to 255.
V
REF
is the voltage applied to the external REFIN pin
when the external reference is selected and is V
DD
/2
if the internal reference is used.
Table I. Output Voltage for Selected Input Codes
Digital Analog Output
MSB . . . LSB
1111 1111
2×255
256×V
REF
V
1111 1110
2×254
256×V
REF
V
1000 0001
2×129
256×V
REF
V
1000 0000 V
REF
V
0111 1111
2×127
256×V
REF
V
0000 0001
2×V
REF
256 V
0000 0000 0 V
2VREF
VREF
0
DAC OUTPUT VOLTAGE
DAC INPUT CODE 00 01 7F 80 81 FE FF
Figure 26. DAC Transfer Function
POWER-ON RESET
The AD7801 has a power-on reset circuit designed to allow
output stability during power up. This circuit holds the DAC in
a reset state until a write takes place to the DAC. In the reset
state all zeros are latched into the input register of the DAC and
the DAC register is in transparent mode thus the output of the
DAC is held at ground potential until a write takes place to the
DAC. The power-on reset circuitry generates a PON STRB
signal which is a gating signal used within the logic to identify
a power-on condition.
POWER-DOWN FEATURES
The AD7801 has a power-down feature implemented by
exercising the external PD pin. An active low signal puts the
complete DAC into power-down mode. When in power-down,
the current consumption of the device is reduced to less than
1 µA max at +25°C or 2 µA max over temperature, making the
device suitable for use in portable battery powered equipment.
The internal reference resistors, the reference bias servo loop,
the output amplifier and associated linear circuitry are all shut
down when the power-down is activated. The output terminal
sees a load of ≈ 23 kΩ to GND when in power-down mode as
shown in Figure 25. The contents of the data register are
unaffected when in power-down mode. The device typically
comes out of power-down in 13 µs (see Figure 10).
V
DD
11.7kΩ
11.7kΩ
I
DAC
V
REF
Figure 25. Output Stage During Power-Down
Analog Outputs
The AD7801 contains a voltage output DAC with 8-bit resolution
and rail-to-rail operation. The output buffer provides a gain of
two at the output. Figures 2, 3 and 4 show the source and sink
capabilities of the output amplifier. The slew rate of the output
amplifier is typically 7.5 V/µs and has a full-scale settling to
eight bits with a 100 pF capacitive load in typically 1.2 µs.
The input coding to the DAC is straight binary. Table I shows
the binary transfer function for the AD7801. Figure 26 shows
the DAC transfer function for binary coding. Any DAC output
voltage can be expressed as:
AD7801
–10– REV. 0
Figure 27 shows a typical setup for the AD7801 when using its
internal reference. The internal reference is selected by tying the
REFIN pin to V
DD
. Internally in the reference section there is a
reference detect circuit that will select the internal V
DD
/2 based
on the voltage connected to the REFIN pin. If REFIN is within
a threshold voltage of a PMOS device (approximately 1 V) of
V
DD
the internal reference is selected. When the REFIN voltage
is more than 1 V below V
DD
, the externally applied voltage at
this pin is used as the reference for the DAC. The internal
reference on the AD7801 is V
DD
/2, the output current to
vo l tage converter within the AD7801 provides a gain of two.
Thus the output range of the DAC is from 0 V to V
DD
, based on
Table I.
DATA BUS CONTROL
INPUTS
AD7801
CS WR LDAC
V
OUT
V
OUT
D7-D0
CLR
PD
V
DD
REF IN
V
DD
= 3V TO 5V
V
DD
AGND DGND
10mF0.1mF
Figure 27. Typical Configuration Selecting the Internal
Reference
Figure 28 shows a typical setup for the AD7801 when using an
external reference. The reference range for the AD7801 is from
1 V to V
DD
/2 V. Higher values of reference can be incorporated
but will saturate the output at both the top and bottom end of
the transfer function. There is a gain of two from input to output
on the AD7801. Suitable references for 5 V operation are the
AD780 and REF192. For 3 V operation a suitable external
reference would be the AD589 a 1.23 V bandgap reference.
DATA BUS CONTROL
INPUTS
AD7801
CS WR LDAC
V
OUT
V
OUT
D7-D0
CLR
PD
V
DD
REF IN
V
DD
= 3V TO 5V
V
DD
AGND DGND
10mF0.1mF
0.1mF
EXT REF
V
OUT
V
IN
GND
AD780/REF192 WITH V
DD
= 5V
OR
AD589 WITH V
DD
= 3V
Figure 28. Typical Configuration Using An External
Reference
MICROPROCESSOR INTERFACING
AD7801–ADSP-2101/ADSP-2103 Interface
Figure 29 shows an interface between the AD7801 and the ADSP-
2101/ADSP-2103. The fast interface timing associated with the
AD7801 allows easy interface to the ADSP-2101/ADSP-2103.
LDAC is permanently tied low in this circuit so the DAC
output is updated on the rising edge of the WR signal.
Data is loaded to the AD7801 input register using the following
ADSP-21xx instruction.
DM(DAC) = MR0
MR0 = ADSP-21xx MR0 Register.
DAC = Decoded DAC Address.
ADDR
DECODE
EN
ADDRESS BUS
AD7801*
CS
LDAC
WR
DB7
DB0
DATA BUS
*
ADDITIONAL CIRCUITRY OMITTED FOR CLARITY.
DMA14
DMA0
DMS
WR
DMD15
DMD0
ADSP-2101*/
ADSP-2103*
Figure 29. AD7801–ADSP-2101/ADSP-2103 Interface
AD7801–TMS320C20 Interface
Figure 30 shows an interface between the AD7801 and the
TMS320C20. Data is loaded to the AD7801 using the following
instruction: OUT DAC, D
DAC = Decoded DAC Address.
D = Data Memory Address.
ADDR
DECODE
EN
ADDRESS BUS
AD7801*
CS
LDAC
WR
DB7
DB0
DATA BUS
*
ADDITIONAL CIRCUITRY OMITTED FOR CLARITY.
A15
A0
IS
STRB
D15
D0
TMS320C20
R/W
Figure 30. AD7801–TMS320C20 Interface
AD7801
–11–
REV. 0
In the circuit shown the LDAC is hardwired low thus the DAC
output is updated on the rising edge of WR. Some applications
may require synchronous updating of the DAC in the AD7801.
In this case the LDAC signal can be driven from an external
timer or can be controlled by the microprocessor. One option
for synchronous updating is to decode the LDAC from the ad-
dress bus so a write operation at this address will synchronously
update the DAC output. A simple OR gate with one input
driven from the decoded address and the second input from the
WR signal will implement this function.
AD7801–8051/8088 Interface
Figure 31 shows a serial interface between the AD7801 and the
8051/8088 processors.
ADDR
DECODE
EN
ADDRESS BUS
AD7801*
CS
LDAC
WR
DB7
DB0
DATA BUS
*
ADDITIONAL CIRCUITRY OMITTED FOR CLARITY.
A15
A8
PSEN OR DEN
WR
AD7
AD0
8051/8088*
ALE OCTAL
LATCH
Figure 31. AD7801–8051/8088 Interface
APPLICATIONS
Bipolar Operation Using the AD7801
The AD7801 has been designed for unipolar operation but
bipolar operation is possible using the circuit in Figure 32. The
circuit shown is configured for an output voltage range of –5 V
to +5 V. Rail-to-rail operation at the amplifier output is achievable
by using an AD820 or OP295 as the output amplifier.
The output voltage for any input code can be calculated as
follows:
V
O
=R
2
1+R4
R3
/R1+R2
()
×
2V
REF
D
256
−V
REF
R4
R3
Where D is the decimal equivalent of the code loaded to the
DAC and V
REF
is the reference voltage input.
With V
REF
= 2.5 V, R1 = R3 = 10 kΩ and R2 = R4 = 20 kΩ and
V
DD
= 5 V.
V
O
=10D
256
–5
DATA
BUS CONTROL
INPUTS
AD7801
CS WR LDAC
V
OUT
D7-D0
CLR
PD
V
DD
REF IN
V
DD
= 3V TO 5V
V
DD
AGND DGND
10mF0.1mF
0.1mF
EXT REF
V
OUT
V
IN
GND
AD780/REF192
WITH V
DD
= 5V
OR
AD589 WITH V
DD
= 3V
R1
10kΩ
R2
20kΩ
+5V
±5V
R3
10kΩ
R4
20kΩ
–5V
AD820/
OP295
Figure 32. Bipolar Operation Using the AD7801
Decoding Multiple AD7801s in a System
The CS pin on the AD7801 can be used in applications to
decode a number of DACs. In this application, all DACs in the
system receive the same input data, but only the CS to one of
the DACs will be active at any one time allowing access to one
channel in the system. The 74HC139 is used as a two-to-four
line decoder to address any of the DACs in the system. To
prevent timing errors from occurring, the Enable input on the
74HC139 should be brought to its inactive state while the
Coded Address inputs are changing state. Figure 33 shows a
diagram of a typical setup for decoding multiple AD7801
devices in a system. The built-in power-on reset circuit on the
AD7801 ensures that the outputs of all DACs in the system
power up with zero volts on their outputs.
AD7801
CS
WR
D0
D7 LDAC
VOUT
AD7801
CS
WR
D0
D7 LDAC
VOUT
AD7801
CS
WR
D0
D7 LDAC
VOUT
AD7801
CS
WR
D0
D7 LDAC
VOUT
74HC139
VCC
VDD
1G
1A
1B
DGND
ENABLE
CODED
ADDRESS
WR
1Y0
1Y1
1Y2
1Y3
DATA BUS
Figure 33. Decoding Multiple AD7801s
AD7801
–12– REV. 0
AD7801 as a Digitally Programmable Indicator
A digitally programmable upper limit detector using the DAC is
shown in Figure 34. The upper limit for the test is loaded to the
DAC, which in turn sets the limit for the CMP04. If a signal at
the V
IN
input is not below the programmed value, an LED will
indicate the Fail condition.
1/4
CMP-04
AD7801
V
DD
REFIN
DGND AGND
D7
D0
V
OUT
V
IN
PASS/
1/6
74HC05
1kΩ
PASS
1kΩ
FAIL
10 F
0.1 F
+5V
DV
DD
Figure 34. Digitally Programmable Indicator
Programmable Current Source
Figure 35 shows the AD7801 used as the control element of a
programmable current source. In this circuit the full-scale
current is set to 1 mA. The output voltage from the DAC is
applied across the current setting resistor of 4.7 kΩ in s eries with
the full-scale setting resistor of 470 Ω. Suitable transistors to
place in the feedback loop of the amplifier include the BC107
and the 2N3904, which enable the current source to operate
from a minimum V
SOURCE
of 6 V. The operating range is
determined by the operating characteristics of the transistor.
Suitable amplifiers include the AD820 and the OP295, both of
which have rail-to-rail operation on their outputs. The current
for any digital input code can be calculated as follows:
I=2V
REF
D
()
256 (5 kΩ)
()
AD7801
V
OUT
REF IN
V
DD
= 5V
V
DD
AGND DGND
10µF0.1µF
0.1µF
EXT REF
V
OUT
V
IN
GND
AD780/ REF192
WITH V
DD
= 5V
4.7kΩ
470Ω
+5V
AD820/
OP295 2N3904/
BC107
V
SOURCE
LOAD
Figure 35. Programmable Current Source
Coarse and Fine Adjustment using two AD7801s
The two DACs can be paired together to form a coarse and fine
adjustment function for a setpoint as shown in Figure 36. In this
circuit, the first DAC is used to provide the coarse adjustment
and the second DAC is used to provide the fine adjustment.
Varying the ratio of R1 and R2 will vary the relative effect of the
coarse and fine tune elements in the circuit. For the resistor
values shown, the second DAC has a resolution of 148 µV
giving a fine tune range of 38 mV (approximately 2 LSB) for
operation with a V
DD
of 5 V and a reference of 2.5 V. The
amplifier shown allows a rail-to-rail output voltage to be
achieved on the output. A typical application for the circuit
would be in a setpoint controller.
AD7801
V
OUT
REF IN
V
DD
= 5V
V
DD
AGND DGND
10µF0.1µF
0.1µF
EXT REF
V
OUT
V
IN
GND
AD780/ REF192
WITH V
DD
= 5V
OR
AD589 WITH V
DD
= 3V
+5V
AD820/
OP295
R1
390Ω
AD7801
V
OUT
REF IN V
DD
AGND DGND
R2
51.2kΩ
V
O
R3
51.2kΩR4
390Ω
0.1µF
Figure 36. Coarse and Fine Adjustment
AD7801
–13–
REV. 0
Power Supply Bypassing and Grounding
In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. The printed circuit board on which the
AD7801 is mounted should be designed so that the analog and
digital sections are separated and confined to certain areas of the
board. If the AD7801 is in a system where multiple devices
require an AGND to DGND connection, the connection should
be made at one point only, a star ground point which should be
established as closely as possible to the AD7801. The AD7801
should have ample supply bypassing of 10 µF in parallel with
0.1 µF located as close to the package as possible, ideally right
up against the device. The 10 µF capacitors are the tantalum
bead type. The 0.1 µF capacitors should have low Effective
Series Resistance (ESR) and Effective Series Inductance (ESI),
such as the common ceramic types, which provide a low
impedance path to ground at high frequencies to handle
transient currents due to internal logic switching.
The power supply lines of the AD7801 should use as large a
trace as possible to provide low impedance paths and reduce the
effects of glitches on the supply line. Fast switching signals like
clocks should be shielded with digital ground to avoid radiating
noise to other parts of the board and should never be run near
reference inputs. Avoid crossover of digital and analog signals.
Traces on opposite sides of the board should run at right angles
to each other. This reduces the effect of feedthrough through
the board. A microstrip technique is by far the best, but not
always possible with a double-sided board. In this technique, the
component side of the board is dedicated to the ground plane
while signal traces are placed on the solder side.
AD7801
–14– REV. 0
20-Lead Wide Body SOIC
(R-20)
SEATING
PLANE
0.0118 (0.30)
0.0040 (0.10) 0.0192 (0.49)
0.0138 (0.35)
0.1043 (2.65)
0.0926 (2.35)
0.0500
(1.27)
BSC 0.0125 (0.32)
0.0091 (0.23)
0.0500 (1.27)
0.0157 (0.40)
8°
0°
0.0291 (0.74)
0.0098 (0.25) x 45°
20 11
101
0.5118 (13.00)
0.4961 (12.60)
0.4193 (10.65)
0.3937 (10.00)
0.2992 (7.60)
0.2914 (7.40)
PIN 1
20-Lead TSSOP
(RU-20)
20 11
10
1
0.260 (6.60)
0.252 (6.40)
0.256 (6.50)
0.246 (6.25)
0.177 (4.50)
0.169 (4.30)
PIN 1
SEATING
PLANE
0.006 (0.15)
0.002 (0.05)
0.0118 (0.30)
0.0075 (0.19)
0.0256 (0.65)
BSC
0.0433
(1.10)
MAX
0.0079 (0.20)
0.0035 (0.090)
0.028 (0.70)
0.020 (0.50)
8°
0°
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
–15–
–16–
C2995–12–4/97
PRINTED IN U.S.A.
