DATASHEET IDT6T39007A CLOCK DISTRIBUTION CIRCUIT Description Features The IDT6T39007A is a low-power, four output clock distribution circuit. The device takes a TCXO or 1.8 V to 2.5 V LVCMOS input and generates four high-quality LVDS outputs, and two programmable divided outputs. * * * * * It includes a redundant input with automatic glitch-free switching when the primary reference is removed. The primary input may be selected by the user by pulling the SEL pin low or high. If the primary input is removed and brought back, it will not be re-selected until 1024 cycles have passed. Packaged in 24-pin QFN TCXO sine wave input +2.5 V operating voltage Four buffered LVDS outputs Two programmable outputs for power control up to 3.0 V LVCMOS levels based on VDDO1/VDDO2 * Individual output enables controlled via I2C or OEx * Pb-free, RoHS compliant package * Industrial temperature range (-40C to +85C) The IDT6T39007A specifically addresses the needs of handheld applications in both performance and package size. The device is packaged in a small 4mm x 4mm 24-pin QFN, allowing optimal use for limited board space. Block Diagram VDD 2.5 V 3 SEL OE1 OUT1 LVDS SCLK OE2 OUT2 LVDS SDATA OUT3 LVDS LVCMOS_INB OUT4 LVDS TCXO_INA 100mVpp Divide Logic MUX VDDO1 PWRCTRL_CLK1 VDDO2 PWRCTRL_CLK2 2 GND IDT(R) CLOCK DISTRIBUTION CIRCUIT 1 IDT6T39007A REV H 022212 IDT6T39007A CLOCK DISTRIBUTION CIRCUIT DISTRIBUTION CIRCUITS GND VDD LVCMOS_INB VDDO1 SEL Pin Configuration Table TCXO_INA SEL Pin Assignment SEL Primary Input 0 LVCMOS_INB 1 TCXO_INA OE Pin Configuration Table 1 SCLK SDATA OUT2 OUT2B Connect to ground plane. 13 OUTx LVDS 0 Disabled 1 Enabled OUT3B OE1 OE2 OUT4 OUT4B OEx OUT3 7 GND VDDO2 VDD OUT1 OUT1B Thermal pad connected to silicon substrate. VDD PWRCTRL_CLK1 PWRCTRL_CLK2 19 24- pin QFN Pin Descriptions Pin Number Pin Name Pin Type Pin Description 1 PWRCTRL_CLK1 Output Programmable power control output 1. See I2C table. 2 PWRCTRL_CLK2 Output Programmable power control output 2. See I2C table. 3 SCLK Input I2C clock input. 4 SDATA Input I2C data input. 5 VDDO2 Power Connect to +3.0 V. 6 VDD Power Connect to +2.5 V. 7 GND Power Connect to ground. 8 VDD Power Connect to +2.5 V. 9 OUT4B Output Buffered LVDS output. Outputs tri-state when disabled. 10 OUT4 Output Buffered LVDS output. Outputs tri-state when disabled. 11 OE2 Input Output enable control for OUT2 LVDSpins. Internal pull-up resistor. See table above. 12 OE1 Input Output enable control for OUT1 LVDSpins. Internal pull-up resistor. See table above. 13 OUT3B Output Buffered LVDS output. Outputs tri-state when disabled. 14 OUT3 Output Buffered LVDS output. Outputs tri-state when disabled. 15 OUT2B Output Buffered LVDS output. Outputs tri-state when disabled. IDT(R) CLOCK DISTRIBUTION CIRCUIT 2 IDT6T39007A REV H 022212 IDT6T39007A CLOCK DISTRIBUTION CIRCUIT DISTRIBUTION CIRCUITS Pin Number Pin Name Pin Type 16 OUT2 Output Buffered LVDS output. Outputs tri-state when disabled. 17 OUT1B Output Buffered LVDS output. Outputs tri-state when disabled. 18 OUT1 Output Buffered LVDS output. Outputs tri-state when disabled. 19 GND Power Connect to ground. 20 VDD Power Connect to +2.5 V. 21 LVCMOS_INB Input Connect to primary LVCMOS input INB. See table above. 22 SEL Input Select pin for primary inputs. See table above. Internal pull-up resistor. 23 TCXO_INA Input Connect to TCXO input. 24 VDDO1 Power Connect to +3.0 V. IDT(R) CLOCK DISTRIBUTION CIRCUIT Pin Description 3 IDT6T39007A REV H 022212 IDT6T39007A CLOCK DISTRIBUTION CIRCUIT DISTRIBUTION CIRCUITS General I2C Serial Interface How to Read: How to Write: * * * * * * * * * * * * * * * * * * * * * Controller (host) sends a start bit Controller (host) sends the write address D4(H) IDT clock will acknowledge Controller (host) sends the beginning byte location =N IDT clock will acknowledge Controller (host) sends the data byte count = X IDT clock will acknowledge Controller (host) starts sending Byte N through Byte N + X - 1 (see Note 2) IDT clock will acknowledge each byte one at a time Controller (host) sends a Stop bit * * * Controller (host) sends a start bit Controller (host) sends the write address D4(H) IDT clock will acknowledge Controller (host) sends the beginning byte location =N IDT clock will acknowledge Controller (host) will send a separate start bit Controller (host) sends the read address D5(H) IDT clock will acknowledge Controller (host) sends the data byte count = X IDT clock sends Byte N + X - 1 IDT clock sends Byte 0 through byte X (if X(H) was written to byte 8) Controller (host) will need to acknowledge each byte Controller (host) will send a not acknowledge bit Controller (host) will send a stop bit Index Block Read Operation Controller (Host) Index Block Write Operation Controller (Host) T T IDT (Slave/Receiver) IDT (Slave/Receiver) starTbit Slave Address D4(H) starTbit WR WRite Slave Address D4(H) WR ACK WRite Beginning Byte = N ACK ACK Beginning Byte = N RT ACK Slave Address D5(H) Data Byte Count = X Beginning Byte = N O O ACK ACK ACK Data Byte Count = X . ACK O . O ACK O Byte N + X - 1 O ACK P ReaD RD X B Y T E O Repeat starT O stoP bit O X B Y T E Beginning Byte N O O O Byte N + X - 1 IDT(R) CLOCK DISTRIBUTION CIRCUIT 4 N Not acknowledge P stoP bit IDT6T39007A REV H 022212 IDT6T39007A CLOCK DISTRIBUTION CIRCUIT DISTRIBUTION CIRCUITS I2C Address The IDT6T39007A is a slave-only device that supports block read and block write protocol using a single 7 bit address and read/write bit. A block write (D4(H)) or block read (D5(H)) is made up of seven (7) bits and one (1) read/write bit. A6 A5 A4 A3 A2 A1 A0 R/W# 1 1 0 1 0 1 0 X In applications where the indexed block write and block read are used, the dummy byte (bit 11-18) functions as a register-offset (8 bits) pointer. Byte 0: Control Register Bit Description Type Output(s) Affected R Power Up Condition Undefined 7 Reserved 6 Reserved R Undefined Not applicable 5 OE for OUT3 RW 1 LVDS clock output 1=enabled 0=disabled 4 OE for OUT4 RW 1 LVDS clock output 1=enabled 0=disabled 3 Reserved R Undefined Not applicable 2 Reserved R Undefined Not applicable 1 Reserved R Undefined Not applicable 0 Reserved R Undefined Not applicable IDT(R) CLOCK DISTRIBUTION CIRCUIT 5 Notes Not applicable IDT6T39007A REV H 022212 IDT6T39007A CLOCK DISTRIBUTION CIRCUIT DISTRIBUTION CIRCUITS Byte 1: Control Register Bit Description Type Power Up Condition Output(s) Affected Notes 7 PWRCTRL_CLK1 Divider SEL bit 7 RW 0 PWRCTRL_CLK1 Default is /15 to get 866.666 kHz from 13 MHz 6 PWRCTRL_CLK1 Divider SEL bit 6 RW 0 PWRCTRL_CLK1 Default is /15 to get 866.666 kHz from 13 MHz 5 PWRCTRL_CLK1 Divider SEL bit 5 RW 0 PWRCTRL_CLK1 Default is /15 to get 866.666 kHz from 13 MHz 4 PWRCTRL_CLK1 Divider SEL bit 4 RW 0 PWRCTRL_CLK1 Default is /15 to get 866.666 kHz from 13 MHz 3 PWRCTRL_CLK1 Divider SEL bit 3 RW 1 PWRCTRL_CLK1 Default is /15 to get 866.666 kHz from 13 MHz 2 PWRCTRL_CLK1 Divider SEL bit 2 RW 1 PWRCTRL_CLK1 Default is /15 to get 866.666 kHz from 13 MHz 1 PWRCTRL_CLK1 Divider SEL bit 1 RW 1 PWRCTRL_CLK1 Default is /15 to get 866.666 kHz from 13 MHz 0 PWRCTRL_CLK1 Divider SEL bit 0 RW 1 PWRCTRL_CLK1 Default is /15 to get 866.666 kHz from 13 MHz Byte 2: Control Register Bit Description Type Power Up Condition Output(s) Affected Notes 7 PWRCTRL_CLK2 Divider SEL bit 7 RW 0 PWRCTRL_CLK2 Default is /46 to get 282.6kHz from 13 MHz 6 PWRCTRL_CLK2 Divider SEL bit 6 RW 0 PWRCTRL_CLK2 Default is /46 to get 282.6kHz from 13 MHz 5 PWRCTRL_CLK2 Divider SEL bit 5 RW 1 PWRCTRL_CLK2 Default is /46 to get 282.6kHz from 13 MHz 4 PWRCTRL_CLK2 Divider SEL bit 4 RW 0 PWRCTRL_CLK1 Default is /46 to get 282.6kHz from 13 MHz 3 PWRCTRL_CLK2 Divider SEL bit 3 RW 1 PWRCTRL_CLK1 Default is /46 to get 282.6kHz from 13 MHz IDT(R) CLOCK DISTRIBUTION CIRCUIT 6 IDT6T39007A REV H 022212 IDT6T39007A CLOCK DISTRIBUTION CIRCUIT DISTRIBUTION CIRCUITS 2 PWRCTRL_CLK2 Divider SEL bit 2 RW 1 PWRCTRL_CLK1 Default is /46 to get 282.6kHz from 13 MHz 1 PWRCTRL_CLK2 Divider SEL bit 1 RW 1 PWRCTRL_CLK1 Default is /46 to get 282.6kHz from 13 MHz 0 PWRCTRL_CLK2 Divider SEL bit 0 RW 0 PWRCTRL_CLK1 Default is /46 to get 282.6kHz from 13 MHz Byte 3: Control Register Bit Description Type 7 to 0 Reserved R Power Up Condition Undefined Output(s) Affected Notes Not applicable Byte 4 through 5: Control Register Bit Description Type Output(s) Affected R Power Up Condition Undefined 7 to 0 Reserved Notes Not applicable Byte 6: Control Register Bit Description Type Power Up Output(s) Affected 7 Revision ID bit 3 R 0 Not applicable 6 Revision ID bit 2 R 0 Not applicable 5 Revision ID bit 1 R 0 Not applicable 4 Revision ID bit 0 R 0 Not applicable 3 Vendor ID bit 3 R 0 Not applicable 2 Vendor ID bit 2 R 0 Not applicable 1 Vendor ID bit 1 R 0 Not applicable 0 Vendor ID bit 0 R 1 Not applicable IDT(R) CLOCK DISTRIBUTION CIRCUIT 7 Notes IDT6T39007A REV H 022212 IDT6T39007A CLOCK DISTRIBUTION CIRCUIT DISTRIBUTION CIRCUITS Applications Information External Components A minimum number of external components are required for proper operation. Decoupling Capacitors Decoupling capacitors of 0.01 F should be connected between VDD and GND as close to the device as possible. Do not share ground vias between components. Route power from power source through the capacitor pad and then into IDT pin. PCB Layout Recommendations For optimum device performance and lowest output phase noise, the following guidelines should be observed. 1. Each 0.01F decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. 2. No vias should be used between decoupling capacitor and VDD pin. 3. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Distance of the ferrite bead and bulk decoupling from the device is less critical. 4. An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers (any ferrite beads and bulk decoupling capacitors can be mounted on the back). Other signal traces should be routed away from the IDT6T39007A.This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. IDT(R) CLOCK DISTRIBUTION CIRCUIT 8 IDT6T39007A REV H 022212 IDT6T39007A CLOCK DISTRIBUTION CIRCUIT DISTRIBUTION CIRCUITS Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the IDT6T39007A. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Rating Max Supply Voltage, VDD 5V LVCMOS_INB, SCLK and SDATA Inputs -0.5 V to +3.3 V All Other Inputs and Outputs -0.5 V to VDD+0.5 V Ambient Operating Temperature -40 to +85 C Storage Temperature -65 to +150 C Junction Temperature 125 C Peak Soldering Temperature 260 C Recommended Operation Conditions Parameter Min. Ambient Operating Temperature Typ. Max. Units +85 C -40 Power Supply Voltage (measured in respect to GND) +2.25 +2.5 +2.75 V Output Supply Voltage (VDDO1, VDDO2) VDD +3.0 +3.15 V DC Electrical Characteristics Unless otherwise specified, VDD =2.5 V 10%, VDDO1 = VDDO2 = 3.0 V 5%, Ambient Temp. -40 to +85 C Parameter Operating Supply Voltage Output Supply Voltage Input High Voltage Input Low Voltage Symbol Conditions VDD VDDO VIH VIL VDDO1, VDDO2 Min. Typ. Max. Units +2.25 +2.5 +2.75 V VDD 3.0 3.15 V SEL, OEx, LVCMOS_INB 0.75xVDD SCLK and SDATA 0.7xVDD V SEL, OEx, LVCMOS_INB 0.35xVDD SCLK and SDATA 0.3xVDD V High-Level Output Voltage VOH IOH = -4 mA Low-Level Output Voltage VOL IOL = 4 mA Operating Supply Current IDD No load, all outputs switching at 13 MHz 15 All outputs disabled TBD mA Single-ended clocks 70 mA Short Circuit Current IDT(R) CLOCK DISTRIBUTION CIRCUIT IOS 1.7 9 V 0.7 V 18 mA IDT6T39007A REV H 022212 IDT6T39007A CLOCK DISTRIBUTION CIRCUIT Parameter DISTRIBUTION CIRCUITS Symbol Conditions Min. Typ. Max. Units Output Impedance ZO All clock outputs, OEx=1 15 Internal Pull-Up Resistance Rpu SEL, OEx 500 k Input Capacitance CIN All input pins 6 pF AC Electrical Characteristics - Single-Ended Outputs Unless otherwise stated, VDD =2.5 V 10%, VDDO1 = VDDO2 = 3.0 V 5%, Ambient Temp. -40 to +85 C Parameter Input Frequency Symbol Conditions FIN Variance Input Frequencies LVCMOS_INB, TCXO_INA, Note 2 Time Switch Clock Inputs LVCMOS_INB, TCXO_INA, Note 3 TCXO Input Swing TCXO_INA Min. Typ. Max. Units 12.6 13 13.4 MHz 0.4 MHz 80 100 Output Frequency Error s 900 0 mV ppm Output Rise Time tOR 20% to 80%, Note 1 1 1.5 ns Output Fall Time tOF 80% to 20%, Note 1 1 1.5 ns 50 55 % 1 ms 10 ms Output Clock Duty Cycle Measured at VDDO/2, Note 1 Output Enable time OE goes high, output within 1% of final frequency Clock Stabilization Time from Power Up Power up, output within 1% of final frequency 45 3 Note 1: CL = 8 pF. Note 2: Delta from 13 MHz. Note 3: By removing primary input and then bringing back primary input. IDT(R) CLOCK DISTRIBUTION CIRCUIT 10 IDT6T39007A REV H 022212 IDT6T39007A CLOCK DISTRIBUTION CIRCUIT DISTRIBUTION CIRCUITS AC Electrical Characteristics - LVDS Outputs Unless otherwise stated, VDD = 2.5 V 10%, Ambient Temperature -40 to +85 C Parameter Conditions Min. Typ. Max. Units Differential Output Voltages | VOD | RL = 100 250 350 450 mV VOD VOD Magnitude Change -40 0 40 mV 1.125 1.25 1.375 V 45 50 55 % 3 25 mV Offset Voltage (VOS) Output CLock Duty Cycle Measured at VOS VOS VOS Magnitude Change Output Short Circuit Current (IOS) -10 mA Output Rise Time 20% to 80%, RL = 100 0.5 1.0 ns Output Fall Time 20% to 80%, RL = 100 0.5 1.0 ns IDT(R) CLOCK DISTRIBUTION CIRCUIT 11 IDT6T39007A REV H 022212 IDT6T39007A CLOCK DISTRIBUTION CIRCUIT DISTRIBUTION CIRCUITS Parameter Measurement Information VDD = 2.5V5% Z = 50 SCOPE Qx VOD 80% 80% 50 LVDS Z = 50 nQx Clock Outputs 50 20% 20% tOF tOR 2.5V OUTPUT LOAD AC TEST CIRCUIT OUTPUT RISE/FALL TIME nCLK VDD CLK out Pulse Width DC Input LVDS 100 VOD/ VOD tPERIOD out tPW & tPERIOD VOD SETUP nCLK VOH CLK V DD VOL t( ) out DC Input tjit( ) = t( ) - t( )mean = Phase Jitter 50 50 LVDS out V OS/ VOS PHASE JITTER V OS S ETUP VDD nCLK Cross Points VOD CLK VOS GND DIFFERENTIAL INPUT LEVEL IDT(R) CLOCK DISTRIBUTION CIRCUIT 12 IDT6T39007A REV H 022212 IDT6T39007A CLOCK DISTRIBUTION CIRCUIT DISTRIBUTION CIRCUITS Marking Diagram 6T7AGI YYWW$ Notes: 1. YYWW is the last two digits of the year and week that the part was assembled. 2. "$" is the assembly mark code. 3. "G" after the two-letter package code designates RoHS compliant package. 4. "I" at the end of part number indicates industrial temperature range. 5. Bottom marking: country of origin if not USA. Thermal Characteristics Parameter Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case IDT(R) CLOCK DISTRIBUTION CIRCUIT Symbol Conditions Min. Typ. Max. Units JA Still air 29.1 C/W JA 1 m/s air flow 22.8 C/W JA 2.5 m/s air flow 21.0 C/W 41.8 C/W JC 13 IDT6T39007A REV H 022212 IDT6T39007A CLOCK DISTRIBUTION CIRCUIT DISTRIBUTION CIRCUITS Package Outline and Package Dimensions (24-pin QFN) Package dimensions are kept current with JEDEC Publication No. 95 Seating Plane A1 Index Area N 1 2 (Ref) ND & NE Even (ND-1)x e (Ref) L A3 e N 1 (Typ) If ND & NE 2 are Even 2 Sawn Singulation E E2 E2 Top View (NE-1)x e (Ref) 2 b A D (Ref) ND & NE Odd C 0.08 C Symbol A A1 A3 b e N ND NE D x E BASIC D2 E2 L Min e Thermal Base D2 2 D2 Millimeters Max 0.80 1.00 0 0.05 0.25 Reference 0.18 0.30 0.50 BASIC 24 6 6 4.00 x 4.00 2.3 2.55 2.3 2.55 0.30 0.50 Ordering Information Part / Order Number Marking Shipping Packaging Package Temperature 6T39007ANLGI 6T39007ANLGI8 see page 13 Tray Tape and Reel 24-pin QFN 24-pin QFN -40 to +85 C -40 to +85 C "G" after the two-letter package code are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT(R) CLOCK DISTRIBUTION CIRCUIT 14 IDT6T39007A REV H 022212 IDT6T39007A CLOCK DISTRIBUTION CIRCUIT DISTRIBUTION CIRCUITS Revision History Rev. Originator Date H RDW 02/22/12 IDT(R) CLOCK DISTRIBUTION CIRCUIT Description of Change 1. Added device top-side marking. 15 IDT6T39007A REV H 022212 IDT6T39007A CLOCK DISTRIBUTION CIRCUIT DISTRIBUTION CIRCUITS Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 www.idt.com/go/clockhelp Corporate Headquarters Integrated Device Technology, Inc. www.idt.com (c) 2012 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA