1 www.semtech.com
POWER MANAGEMENT
SC2434
TriPhase Current Mode Controller
with Power Good
May 18, 2005
Description Features
The SC2434, a tri-phase, current mode controller is
designed to work with Semtech smart synchronous
drivers, such as the SC1205, SC1206, and SC1207 to
provide the DC/DC converter solution for the most
demanding Microprocessor applications. Input current
sensing is used to guarantee precision phase to phase
current matching using a single sense resistor on the
input power line. This topology reduces the power loss
and complexity associated with output current sense
methods. Multi phase operation allows significant
reduction in input/output ripple while enhancing
transient response. Two or three phase operation is
selectable. The DAC step size and range are program-
mable with external components thus allowing compliance
with new and emerging VID ranges. A novel approach
implements active droop to minimize output capacitors
during load transients.
!12V input
!Input sensing current mode control
!Selectable 2 or 3 phase operation
!Precision, pulse by pulse phase current matching
!Active drooping allows for best transient response
!Programmable internal oscillator to 1.5 MHz
!Programmable DAC step size/offset allows compli-
ance with VRM9.0 and VRM9.2
!VID 11111 Inhibit (No CPU)
!Externally programmable soft-star t
!0% minimum duty cycle improves transient
response
!Cycle by cycle current limiting plus hiccup
!Power good signal
!Intel Pentium-4 microprocessors
!!
!!
!High perf ormance desktop systems
T ypical Application Circuit
Applications
+12V
C17
1uF
D1
1N4148
+5V
R2
2R2
R9
2R2
L4
600nH
+5V_ATX
C6
4.7uF
+
C21
1500uF/6.3V
D6
1N4148
+
C2
2200uF/16v
VID0
C24 1uF
R_OS
46.4K
+
C26
1500uF/6.3V
C23
2.2nF
+
C7
1500uF/6.3V
D3
1N4148
C16
4.7uF
M4
+
C10
1500uF/6.3V
U1
SC1205
1
2
3
4 5
6
7
8
DRN
TG
BST
CO EN
VS
BG
PGND
C5
4.7uF
M5
R4
1R
+
C18
1500uF/6.3V
R29
100
VCCVID_PWRGD(Open Collector Input)
+
C32
1500uF/6.3V
+12V
VOUT
C35 1uF
C4
1uF
C9
1nF
M6
Differential
Pair
R_COMP
75K
C15
1uF
+12V
C22
1nF
L1
600nH
U2
SC2434
1
2
3
4
5
6
7
8
9
10 11
12
13
14
15
16
17
18
19
20
VID4
VID3
VID2
VID1
VID0
PGIN
ERROUT
PGOUT
FB
OSCREF DACREF
OC+
OC-
AGND
PC
OUT3
OUT2
OUT1
BGOUT
VCC
D2
1N4148
R10
1R
R5
20
D5
1N4148
C34
2.2nF
+
C28
1500uF/6.3V
R15
1K
R_OSC
31.6K
C27
1uF
L2
600nH
VID4
M3
R17
1
SM/R_1206
Differential
Pair
M2
R14
2R2
R6
1
SM/R_1206
C76 0.33uF
C75 0.33uF
C11
2.2nF
U3
SC1205
1
2
3
4 5
6
7
8
DRN
TG
BST
CO EN
VS
BG
PGND
C33
1nF
+
C30
1500uF/6.3V
+
C14
1500uF/6.3V
R1 3m
R16
1R
M1
+
C1
2200uF/16v
V_PULL_UP
+
C19
1500uF/6.3V
R_FB
10K
+
C20
1500uF/6.3V
C77 0.33uF
R_DRP
187K
D4
1N4148
R3
2R2
C31
470pF
R8
NO POP
+
C3
2200uF/16v
VID3
R13
5.1K
+
C25
1500uF/6.3V
+5V
C12 1uF
AGND
C13
10nF
C_COMP
18pF
+12V_ATX
C29
100nF
VID1
C8
1uF
PWR_GOOD
R19
750
VID2
U4
SC1205
1
2
3
4 5
6
7
8
DRN
TG
BST
CO EN
VS
BG
PGND
PGND
R_DAC
37.4K
L3
600nH
R11
1
SM/R_1206
R20
1K
22005 Semtech Corp. www.semtech.com
PRELIMINARYPOWER MANAGEMENT
SC2434
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Unless specified: VCC = +12V, TAMB = 25°C, RDAC = 37.4kΩ, R OSC = 28.5kΩ. See T ypical Application Circuit
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified
in the Electrical Characteristics section is not implied.
Absolute Maximum Ratings
Electrical Characteristics
32005 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC2434
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Notes:
1. If VIDs are left open, no external pull-up is required. When external pull-up is needed, use 3.3V.
2. Max logic input is recommended to be less than 5.5V.
Unless specified: VCC = +12V, TAMB = 25°C, RDAC = 37.4kΩ, R OSC = 28.5kΩ. See T ypical Application Circuit
Electrical Characteristics (Cont.)
42005 Semtech Corp. www.semtech.com
PRELIMINARYPOWER MANAGEMENT
SC2434
Pin Descriptions
Pin Configuration Ordering Information
Note:
(1) Only available in tape and reel packaging. A reel
contains 1000 devices for the SOIC-20 and 2500 devices
for the TSSOP-20 package.
(2) Lead free package. Devices are fully WEEE and RoHS
compliant.
(3) Specify SOIC-20 or TSSOP-20 package.
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14DIVBSM
23DIV
32DIV
41DIV
50DIVBSL
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(20-Pin SOIC or TSSOP)
Top View
VID4
VID3
VID2
VID1
VID0
PGIN
ERROUT
PGOUT
FB
OSCREF
VCC
BGOUT
OUT1
OUT2
OUT3
PC
AGND
OC-
OC+
DACREF
52005 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC2434
Block Diagram
Applications Information- Output Voltage
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4DIV3DIV2DIV1DIV0DIV)CDV(
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
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62005 Semtech Corp. www.semtech.com
PRELIMINARYPOWER MANAGEMENT
SC2434
Theory of Operation
The simplified voltage regulator (VR) based on SC2434
is depicted in Fig. 1. The key timing chart is also shown
in the same picture. The 12V input power passes through
the input filter establishing the input power rail. The cur-
rent sensing resistor located at positive input rail moni-
tors the top FET currents of all the phases. An internal
differential amplifier amplifies the voltage across the
current sensing resistor. The output of the current am-
plifier and an internally generated saw tooth ramp signal
are added together to be the PWM carrier signal. This
signal meets the output of the error amplifier at the pulse
width modulator (PWM). The output of the PWM is then
divided into three phases alternately to be the inputs of
the synchronous drivers.
Feedback and Regulation
The feedback circuitry reads the regulator output volt-
age and compares it with an accurately trimmed bandgap
voltage reference, which is 1.5V with less then 0.8% tol-
erance. The compensation network allows optimization
of the control-loop for system stability and fast transient
responses.
Applications Information Flexible VID
The VID circuitry reads the 5 bit digital command and
converts it into a current flowing into the inverting input
pin of the error amplifier. The output current of the DAC
produces a voltage offset on the feedback resistor, RFB
(see Fig. 1), which changes the set point of the converter
output voltage for different VID combinations.
Active Voltage Positioning
By programming the gain of the error amplifier, one can
easily and accurately implement adaptive output voltage
positioning. This is equivalent to programming the VR
output impedance in an active manner. The advantage
of allowing the VR certain output impedance (typically
1~3 mOhm) is that one can use a minimum amount of
high quality output bulk capacitors to meet the voltage
regulation requirement. Hence, the cost and the size of
the VR solution can be significantly reduced.
SC2434
Fig.1 - The simplified voltage regulator based on SC2434.
72005 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC2434
Phase Current Balance
One of the fundamental challenges for multi-phase solu-
tions is to balance the phase currents to achieve the best
possible electrical and thermal performance. It is quite
easy to use the SC2434 control topology to achieve very
good phase current balance. Since the current of all the
phases passes through the same current sensing compo-
nent and the same current current of all the phases are
well balanced on pulse by pulse basis. This control results
in small and even output voltage ripple and evenly distrib-
uted thermal load. Additional advantages of using input
current mode are less sensing circuitry, less IC pins, and
less power loss on the sensing resistor comparing sensing
inductor current on the output side. Fig. 2 shows the wave-
form of inductor currents under heavy load conditions,
which clearly demonstrates the excellent per formance of
SC2434 on balancing the phase current.
Applications Information (Cont.)
voltage. Fig. 3 shows the measured waveforms of power
up and power down.
Fig. 3 - Shows the measured waveforms of power up and power
down.
Over Current Protection (OCP)
When sensed current signal across the differential input
of the current amplifier exceeds 120mV typical value, OCP
circuitry will pull down the error amplifier output voltage
and also discharge the soft start capacit or . The pull do wn
of the error amplifier will not be released until the soft
capacitor is discharged bellow 0.3V. At this point, the
PWM outputs are reactivated and the soft start capacitor
begins to charge up again through the internal 6 Kohm
resistor. The VR will try to bring up the output v oltage until
the over load or short circuit condition is removed. The
hiccup mode OCP can significantly reduce the average out-
put current under overload conditions. The hiccup timing
is controlled by the sof t star t time constant. Please also
notice that the OCP threshold has less than 10% toler-
ance, hence, the onset of the OCP is quite accurate. The
advantage is that the VR designer does not need to re-
serve big thermal headroom to deal with the worst-case
operation when load is ov er 1 00% but the OCP has yet not
been triggered. An RC filter is needed to filter out the
leading edge voltage spike across the current sensing re-
sistor to pre v ent false triggering of the OCP. The time con-
stant should be around 200nS (please see application
schematic).
Power Good
SC2434 features a power good input and an open collec-
tor power good output. The VR output voltage is scaled
down through a resistive divider and this signal is fed into
PGIN (power good input) pin. The scaled VR output volt-
age has to be bigger than 0.8V otherwise the power good
output pin is pulled down. A 5 Kohm pull-up resistor and
a 0.1uF capacitor t o ground are recommended to prevent
false trigger during logic transition.
Fig. 2 - Measured inductor currents of SC2434 3-phase VR
under heavy load condition.
Under V oltage Lockout (UVLO)
During power up, when UVLO circuitry detects the chip
supply (Vcc) be bigger than 7.5V (typical value with pr oper
hysteresis), the bandgap voltage reference starts to charge
the external sof t start capacitor through a 6 Kohm inter-
nal resistor. When soft start capacitor voltage reaches
0.5V, the output voltage starts to build up which follows
the exponential voltage profile of the sof t star t capacitor.
The soft start process ensures that the output voltage will
have no over shoot. During power down, UVLO will dis-
charge the soft start capacitor to shut of the PWM. The
load will absorb the energy in the output filter and no reso-
nance will occur . Hence, the CPU will not see any negative
Output
volta
g
e Output
volta
g
e
Input
volta
g
e
Input
volta
g
e
82005 Semtech Corp. www.semtech.com
PRELIMINARYPOWER MANAGEMENT
SC2434
Applications Information (Cont.)
Program The Controller
Please refer to Fig. 1 and the application schematics in
this data sheet for the discussion. The resistor from pin
10 to ground, ROSC, programs the switching frequency . The
resistor from pin 11 to ground, RDAC, sets the DAC current
step size. The resistors, RFB, ROS , and RDRP set the DAC
step size, the output voltage set point, and the droop,
respectively.
MathCAD programs are available to calculate the required
parameters upon request.
Programming The Switching Frequency
The oscillator frequency can be selected first by setting the
value of ROSC as given below:
IDAC_LSB 1
16
Vbg
RDAC
.
RFB VIDstep
IDAC_LSB
The per phase switching frequency is 1/3 of the oscilla-
tor frequency in three-phase mode. It is recommended
that per phase switching frequency is 200~300KHz for
good trade off of efficiency vs. transient responses.
Programming The DAC Step Size
The SC2434 allows programming of the output voltage
and the DAC step size by selecting external resistors. The
LSB of the DAC current is given by:
where Vbg is the trimmed voltage reference (Vbg = 1.5V)
and RDAC is the resistor from pin 11 to ground. For the
given VID step size (25mV for VRM9.0 and VRM9.2 speci-
fications), the feedback resistor can be calculated accord-
ing to the LSB of DAC current:
The above two equations are for choosing RDAC and RFB
simultaneously . The advantage of this method is that new
VID step size can be accommodated by modifying external
components while maintaining the required precision.
Choose Current Sensing Resist or According To The
Threshold Of OCP
The SC2434 controller has an over current protection (OCP)
threshold of 120mV. The normal practice is to let the
peak voltage across the sensing resistor corresponding to
full-load operation be 75% of the given OCP threshold:
Rdrp RFB Rsense
.
Gca
.
∆
Vout
∆
Iout
Nphase
.
where Ipeak is the peak current of the output inductor . Since
the choice of sensing resistor values are limited, typically 3
mOhm, 4 mOhm, or 5 mOhm, it is recommended to choose
the sensing resistor with a bigger value than that was cal-
culated, and to use a resistive divider to get the equiva-
lent Rsense value. The two attenuation resistors should
have value of 20 Ohm in parallel. A filter capacitor of
1 0nF is also needed to be acr oss the OC+ and OC- pins of
the controller IC. Please refer the application circuit sche-
matic.
Programming The Dynamic (Active) Droop
T o optimize transient responses, the SC2434 actively regu-
lates output voltage as a function of output current. At
zero current the output is positioned to the upper limit of
the regulation window. As the load increases, the output
“droops” towards the lower limit. This makes optimum
use of the output voltage error band, yielding minimum
output capacitor size and cost.
The droop is adjusted by setting the DC gain of the error
amplifier. This is done by choosing the resistor from the
ERROUT pin to the FB pin (RDRP) of the controller. While
the optimum value of RDRP ma y be derived e xperimentally,
the following equation can provide the first order calcula-
tion for given droop slope:
where Rsense is the current sensing resistance after taken
into account of attenuation, and Gca is the gain of the
current amplifier while Nphase is number of phases being
used.
Any output interconnection impedance not within the feed-
back loop can contribute to additional drooping. This ef-
fect has to be taken into account. Usually, when testing
the regulation at different CPU pins, the results may var y
slightly by same token.
It is important to use surface mount current sensing resis-
tor to minimize the parasitic inductance for accurate cor-
relation between the above equation and the test results.
This is because the inductive contribution, which may also
R
sense 75% "120m
V
I peak
92005 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC2434
be caused by layout inductances, may alter the PWM
comparator trip point. The value of RDRP may have to be
adjusted to compensate for such parasitic effects.
It must be noted that the current amplifier gain is quite
precise, with greater than 80dB of Common Mode
Rejection Ratio (CMRR). Thus the droop accuracy is
primarily based upon external components tolerances. By
employing 1% current sensing element with very low
temperature coefficient, this topology is proved to be the
best comparing the schemes of using Rdson sensing and
using inductor winding resistance sensing. The accurate
drooping translates into minimum amount output bulk
capacitor needed to meet the voltage regulation specifica-
tions and the least system cost.
Programming The DC Level Of The Output Voltage
Kirchoff’s current law can be applied to the error
amplifier’s inverting input (see Fig. 1) to calculate ROS,
the DC level setting resistor. For given output voltage set
point and VID setting, the resistance can be calculated
by:
Applications Information (Cont.)
Hp_ccm sR
,
()G
pwm 1sC
.
Rc
.
1sR
.
C
.
( ) 1 1.5 s
π
Fs
.
.
s
π
Fs
.
2
.
.
Fig. 4 - Loop gain and compensation of the current mode con-
troller.
where Copam is the equivalent internal capacitor across the
error amplifier output and the inverting input with a value
of 11pF.
The power stage transfer function under continuous
conduction mode can be approximated by:
where NDAC_STEP is the number of VID steps down from the
highest set point (VID=00000). For example, when VID
[4:1]=00100, NDAC_STEP = 4. VEO is the error amplifier
output voltage and, as a first approximation, it is equal to
1..7V. Again, VBG = Precision Reference Voltage = 1.5V.
The final value of ROS may need to be fine tuned
experimentally after the droop resist or has been chosen.
Control Loop Compensation
The current mode control yields a power supply easy to
compensate because the power stage has first order (single
pole) behavior. The SC2434 provides internal slope
compensation to avoid sub harmonic oscillation of the
current loop. The added ramp signal has 300mV peak-to-
peak amplitude and the ramp frequency is as same as
the oscillator freq uency .
As depicted in Fig. 4, the gain for the voltage feedback
loop can be expressed as a product of the power stage
gain and the compensator gain:
Loop s R
,
()H
p_ccm sR
,
()H
cs()
.
0
-
+
Err_Amp
Verror
Loop G ain
Copa m
Ccomp Rcomp
-1
Ccomp 1/(R*C)
Rdrp
POWE R
STAGE
Rd rp/Rfb
Vin/(VR*Npha se ) -1
Po wer St age
Compensator
1/(ESRC)
Pole
Fsw/2
Zero
0dB
Fsw/2
-2
-2
1/(R*C)
Vout
where GPWM is the low frequency gain of the power stage.
The power stage has an ESR zero, a dominant pole at
low frequency, and a pair of complex pole located at one
half of the switching frequency . The parame ter used here
are defined as below:
C = output bulk capacitance
R = load resistance
RC = ESR of output bulk capacitor
FSW = switching frequency
The PWM gain is defined as:
Ros Vbg
Vset Vbg
RFB
Veo Vbg
Rdrp NDAC_STEPIDAC_LSB
.
G pwm R ! N
R phase
sense· G CA
102005 Semtech Corp. www.semtech.com
PRELIMINARYPOWER MANAGEMENT
SC2434
Applications Information (Cont.)
The compensator transfer function has two poles and one
zero:
Hcs() Rdrp
RFB
1s
ω
z
1s
ω
p1 1s
ω
p2
.
.
To optimize the transient responses, it is recommended
that:
· To use the first compensat or pole t o cancel the pow er
stage ESR zero;
· To place the compensator zero at one half of the
switching frequency;
· And to place the second compensator pole at high
frequency.
The Bode plots based this model and those obtained from
experiment are depicted in Fig. 5 and Fig. 6, respectively.
It can be seen that the model agrees well with the
experiment. The control model provides us physical
insight of the loop dynamics and helps the designer to
achieve good transient responses and system stability. Here
are few comments:
· The loop crossover frequency (0dB frequency) should
be lower than one fifth (20%) of the switch frequency
to avoid noise pick up and the phase lag introduced
by the complex pole located at one half of the switching
frequency;
· A >20KHz crossover frequency is adequate to assure
good transient response when the VR output
impedance, or droop impedance, is programmed to
be equal to the output capacitor ESR. The ESR
frequency for the output bulk capacitor is usually less
than 20KHz, and beyond that frequency the capacitor
behaves like a resistor up to few hundred KHz, which
is desired for dynamic droop. There is no point to
demand the control loop to have much higher
crossover frequency bey ond the ESR zero frequency .
Fig. 5 - Loop gain Bode plot based on control loop model.
Fig. 6 - Measured loop gain Bode plots.
100 1 .10 31.10 41.10 51.10
6
40
20
0
20
40
Loop-Ga in (dB)
mag_Loop i R,()
0
Fi
100 1 .10 31.10 41.10 51.10 6
180
90
0
90
180
LoopGain (Degree)
phase_Loop i R,()
Fi
100 1 .10 31.10 41.10 51.10
6
40
20
0
20
40
Loop-Ga in (dB)
mag_Loop i R,()
0
Fi
100 1 .10 31.10 41.10 51.10 6
100 1 .10 31.10 41.10 51.10
6
40
20
0
20
40
Loop-Ga in (dB)
mag_Loop i R,()
0
Fi
100 1 .10 31.10 41.10 51.10 6
180
90
0
90
180
LoopGain (Degree)
phase_Loop i R,()
Fi
112005 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC2434
PCB Layout Consideration
Good layout is necessar y for successful implementation of the SC2434 based 3 tri-phase topology. There are few
general rules:
· Reserve enough PCB space f or the power supply (1.2~1.5 square inch for ev ery 10A of load current);
· Place enough high frequency ceramic capacitors inside and around the CPU socket (please follow CPU manufacture’s
decoupling guideline);
· Place bulk output capacitors around the CPU socket as uniformly as possible. The connection copper between
these capacitors and the CPU socket must be short and wide to minimize inductance and resistance;
· Always place the high power parts first;
· Always use a ground plane or ground planes;
· Always try to minimize the stray inductance of the high pulsating current loop which is formed by input capacitors
and the MOSFET half-bridges.
The following layout guideline gives details on how to achieve a good layout:
· Input filter should contain mixed electrolytic capacitors and MLC capacitors. For every 20A of load current, use
about 10uF of MLC caps. Put ML C caps close to current sensing resistor;
· Use surf ace mount current sensing resistor (typically 3~5 mOhm in surface mount package with low t emperature
coefficient and low package inductance, typically less than 0.3nH);
· Try to minimize the stray inductance from the current sensing resistor to the drains of the top FETs by using wide
trace (>0.5” wide and no more than 3” long). This trace can run on inner1 lay er, for e xam ple, if the inner2 layer is
the ground plane, assuming the FETs are on the top lay er. This arrangement f orms so called strip line structure f or
the pulsating power current, which yields least amount of stray inductance. The concept is depicted in Fig. 7;
· Keep the layout as electrically symmetrical as possible, as shown in Fig. 8, to avoid very uneven stray inductance
from the sensing resistor to the drains of the top FETs;
· Use a pair of closely paralleled traces to pick up the sensing voltage across the sensing resistor . The sensing traces
server as differential in put to the OC+ and OC- pins of the SC2 434 contr oller. These traces should run on a routing
lay er (e.g., bottom la yer for 4 la yer PCB case) t o avoid picking up str ong AC magnetic field due t o power current flow .
In this case, the diff erential sensing traces are shielded by the gr ound la y er. The filter cap acr oss the OC+ and OC-
pins should be placed as close as possible to the controller. Pay close attention that never allow power current
flowing on or running close by the sensing traces. Please see Fig. 8;
· Separate power ground from analog ground to prevent power current from running over the analog ground plane.
The SC2434 controller should be placed on the quite analog ground area. The analog ground should be single-
point connected to the PGND near the output capacitor or the CPU socket to provide best possible ground sense.
Refer to the application schematics for those components should be connected directly to the AGND (Vcc decoupling
caps, cap on BGOUT pin, resistors on OSCREF pin, DACREF pin, FB pin, and PGIN pin).
Fig. 7 - Use MLC capacitors and strip line structure to minimize the stray inductance for the switching current loop.
TOP FET BOT FET
DSD S
MLC
VIA VIA
Rsense
Ground Plane
Applications Information (Cont.)
122005 Semtech Corp. www.semtech.com
PRELIMINARYPOWER MANAGEMENT
SC2434
Fig. 8 - Layout concept for input current sensing: (a) use MLC input capacitors; (b) minimize inductance; (c)
keep electrical symmetry; and (d) use differential sensing traces.
A Reference Design Example For Intel Pentium IV
Processor
Brief specifications of this design are listed below:
• Vin=12V
• Vout=1.725V +/- 25mV at 0A load
• Vout droop slope is 1.5 mOhm
• Vout tolerance is +/-25mV for all load conditions
• Iout = 60A max
• VID [4:0] = 00100
The schematic is shown on the cover page of this data
sheet.
Applications Information (Cont.)
132005 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC2434
Bill of Materials - Reference Design
metI.ytQecnerefeReulaV.oNtraP/noitpircseDegakcaProdneV
11 PMOC_CFp74TAXXK074Y306JV,CCLM,R7X,V013060YAHSIV
211CFu33.0TAXXK433Y508JV,CCLM,R7X,V525080YAHSIV
33 4C,3C,2CFu0022pac.celE.lAV51/004.D/LYCPC 430./002.SL oynaS
48 ,31C,9C,5C ,81C,51C 83C,03C,62C
Fu1DN-TC9481CCP,CCLM,V5Y,V615080cinosanaP
53 61C,7C,6CFu7.4DN-TC0091CCP,CCLM,V5Y,V616021cinosanaP
621,41C,01C,8C ,22C,02C,91C ,82C,72C,32C 53C,33C,13C
Fu0051ZBMnocubyRpaC.lAV3.6/523.D/LYCPC 430./521.SL nocibuR
73 63C,42C,11CFn1TAXXK201Y306JV,CCLM,R7X,V613060YAHSIV
83 73C,52C,21CFn2.2TAXXK222Y508JV,CCLM,R7X,V055080YAHSIV
92 92C,71CFu33.0TAXXK433Y308JV,CCLM,R7X,V525080YAHSIV
01112CFn01TAXXK301Y306JV,CCLM,R7X,V013060YAHSIV
11123CFn001TAXXK401Y306JV,CCLM,R7X,V613060YAHSIV
21143CFp074TAXXK174Y306JV,CCLM,R7X,V013060YAHSIV
316 ,4D,3D,2D,1D 6D,5D A3DN-TCSM8414LDylttohcSMSV03CA312ODYEK-IGID
414 4L,3L,2L,1LHn836836-5031FITTrotcudnI,A02,Hn83601./004W/005L/NIoclaF
513 5M,3M,1MLB6306BDFTEFSOMBA362-OTdlihcriaF
612 4M,2ML5407BDFTEFSOMBA362-OTdlihcriaF
7116ML5407PDFTEFSOMBA362-OTdlihcriaF
811 PMOC_RK4.92F24923060WCRC%1MS3060YAHSIV
911 CAD_RK4.73F24733060WCRC%1MS3060YAHSIV
021 PRD_RK781F37813060WCRC%1MS3060YAHSIV
121 BF_RK0.01F20013060WCRC%1MS3060YAHSIV
221 SO_RK4.64F24643060WCRC%1MS3060YAHSIV
321 CSO_RK6.13F26133060WCRC%1MS3060YAHSIV
4211Rm3W0257LR%1RgnisneSMS2152CETNYC
524 31R,8R,5R,2R2R2F2R23060WCRC%1MS3060YAHSIV
6213R02F0R023060WCRC%1MS3060YAHSIV
723 51R,01R,4R0R1F0R133060WCRC%1MS3060YAHSIV
8216R001F00013060WCRC%1MS3060YAHSIV
923 61R,11R,7R0R1F0R16021WCRC%1MS6021YAHSIV
142005 Semtech Corp. www.semtech.com
PRELIMINARYPOWER MANAGEMENT
SC2434
metI.ytQecnerefeReulaV.oNtraP/noitpircseDegakcaProdneV
0319RPOPONF0R13060WCRC%1MS3060YAHSIV
13121RK1.5F11153060WCRC%1MS3060YAHSIV
232 81R,41RK0.1F10013060WCRC%1MS3060YAHSIV
33171R057F00573060WCRC%1MS3060YAHSIV
433 4U,3U,1U5021CSrevirDTEFlauD8-CIOSHCETMES
5312U4342CSrellortnoCedoMtnerruCesahP-irT dooGrewoP/w ro02-CIOS 02-POSST HCETMES
Bill of Materials - Reference Design (Cont.)
Note 1: Magnetic Cool Mu 77041, 5 turns AWG #16 (800nH@0A, 600nH@25A)
152005 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC2434
Applications Information (Cont.)
Efficency (%)
65.00
70.00
75.00
80.00
85.00
90.00
95.00
0 10203040506070
I_out(A)
Typical Performance Of The Reference Design
The reference design implemented 1.5mOhm output droop impedance as shown in Fig. 9.
Fig. 9 - Measured output drooping characteristics of the 60A design.
The efficiency of the design is depends on the MOSFET being used and thermal management requirements of
controlling the PCB temperature and the MOSFET junction temperature. The following efficiency curve is corresponding
to 4mOhm bottom FET, while the top FET has 12 mOhm Rdson.
Fig. 10 - T ypical efficiency curve f or 12 mOhm top FET s and 4 Ohm bottom FET s.
Load Line (Vin=12V, VID=00100)
1.6
1.62
1.64
1.66
1.68
1.7
1.72
1.74
1.76
0 102030405060
I (A)
Vo(V)
Vo
Spec_H
Spec_L
162005 Semtech Corp. www.semtech.com
PRELIMINARYPOWER MANAGEMENT
SC2434
Applications Information (Cont.)
The typical phase node voltage and the output voltage ripple waveform is shown in Fig. 11 under 60A full load
operation, where one can see the output ripple is very small and even with a frequency three times of the switching
frequency.
Fig. 11 - The typical phase node voltage and the output voltage ripple waveform under 60A full load operation.
The typical gate waveform for the top and bottom MOSFETs is also shown here, well-controlled dead time is
demonstrated which ensures high efficiency operation of the VR.
Fig. 12 - The typical gate w avef orm for the top and bott om MOSFET s.
Ch2: HS Gate
Ch 3: Pha se Node
Ch4: LS Gate
172005 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC2434
Applications Information (Cont.)
The transient response for a maximum load step changes (10A to 60A) is shown in Fig. 14, where one can see that
accurate drooping will help to reduce the amount of output capacitance needed. Please notice that using more
multilayer ceramic capacitors for better high frequency decoupling can reduce the narrow voltage spikes.
Fig. 13 - Transient response and the test condition:
Step Load from 10A to 60A
Output Capacitors: 14 units of 560uF OSCON caps, 38 units of 10uF ceramic caps
Ch1: Output Voltage
Ch4: Output Current (1A = 27.5mV di/dt = 370A/uS)
Meet Intel P-4 spec
Output Voltage
Load Current
182005 Semtech Corp. www.semtech.com
PRELIMINARYPOWER MANAGEMENT
SC2434
L
(L1)
c
01
GAGE
PLANE
SEE DETAIL DETAIL
A
A
0.25
.026 BSC
.252 BSC
20
.004
.169
.251 .173
.255
.007 -
20
0.10
0.65 BSC
6.40 BSC
4.40
6.50
-
.177
.259 4.30
6.40
.012 0.19
4.50
6.60
0.30
bxN
2X N/2 TIP S
SEATING
aaa C
E/2
INDICATOR
PIN 1
2X
1 32
N
E1
bbb CA-B D
ccc C
DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS3. OR GATE BURRS.
DATUMS AND TO BE DETERMINED AT DATUM PLANE
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
-B-
NOTES:
1.
2. -A- -H-
SID E VIEW
(.039)
.004
.008
-
.024
-
-
-
-
0°
.018
.003
.031
.002
-
8° 0°
0.20
0.10
-8°
0.45
0.09
0.80
0.05
.030
.007
.047
.042
.006 -
(1.0)
0.60
-
0.75
0.20
-
-
-1.20
1.05
0.15
A
B
C
D
e
e/2
H
PLANE
D
E
A1
A2 A
REFERENCE JEDEC STD MO-153, VARIATI ON AC.
4.
INCHES
b
N
ccc
aaa
bbb
01
E1
E
L
L1
e
D
c
A2
A1
DIM
A
MIN MAX
MILLIMETERS
MIN
DIMENSIONS
NOM MAX NOM
Outline Drawing - TSSOP-20
Land Pattern - TSSOP-20
(.222) (5.65)
Z
G
Y
P
(C) 4.10.161 0.65.026 0.40.016 1.55.061 7.20.283
X
INCHES
DIMENSIONS
Z
P
Y
X
DIM
C
G
MILLIMETERS
THIS LA ND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANU FACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
NOTES:
1.
192005 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC2434
THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFA CTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
NOTES:
1.
REFERENCE IPC-SM-782A, RLP NO. 307A.
2.
(.362) (9.20)
Z
G
Y
P
(C) 7.00.276 1.27
.050 0.60.024 2.20.087 11.40.449
X
INCHES
DIMENSIONS
Z
P
Y
X
DIM
C
G
MILLIMETERS
01
ccc
aaa
bbb
MAX
DIMENSIONS
A1
e
L
N
L1
h
c
E1
E
D
b
A2
MIN
DIM
A
INCHES
NOM MILLIMETERS
NOMMIN MAX
REFERENCE JEDEC STD MS-013, VARIATION AC.4.
E
.041
.013
.104
.100
.012 2.35
-
(1.04)
-
1.04
0.33
-
-
-2.65
2.55
0.30
.030.010 -0.750.25 -
h
h
3. DIMENSIONS "E1 " AND "D" DO NO T INCLUDE MOLD FLA SH, PROT R USI O NS
OR GATE BURRS.
-B-
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
DATUMS AND TO BE DETERMINED AT DATUM PLANE
NOTES:
1.
2. -A- -H-
SIDE VIEW
A
B
C
D
e
H
e/2
bbb CA-B D
SEE DETAIL A
L
(L1)
0.25
PLANE
GAGE c
01
(.041)
.013
-
.004
-
-
-
-
-
0°
.016
.008
.081
.004
.093
8° 0°
0.33
0.10
-8°
0.40
0.20
2.05
0.10
.050 BSC
.406 BSC
20
.010
.291 .295
.012 -
20
0.25
1.27 BSC
10.30 BSC
7.50
-
.299 7.40
.020 0.31
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0.51
.504
2X N/2 TIPS
SEATING
aaa C
E/2
ccc C
2X
213
N
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A1
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D
E1 .500 12.70.508 12.80 12.90
PLANE
DETAIL A
Outline Drawing - SOIC-20
Land Pattern - SOIC-20
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Fxa0933-8472-2-688: HbmGdnalreztiwShcetmeS hcnarBnapaJ 0590-8046-3-18:leT 1590-8046-3-18:xaF
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