MTB50P03HDLT4G - ON Semiconductor

June, 2006 − Rev. 6 1Publication Order Number:

MTB50P03HDL/D

MTB50P03HDL

Preferred Device

Power MOSFET

50 Amps, 30 Volts, Logic Level

P−Channel D2PAK

This Power MOSFET is designed to withstand high energy in the

avalanche and commutation modes. The energy efficient design also

offers a drain−to−source diode with a fast recovery time. Designed for

low voltage, high speed switching applications in power supplies,

converters and PWM motor controls, these devices are particularly

well suited for bridge circuits where diode speed and commutating

safe operating areas are critical and offer additional safety margin

against unexpected voltage transients.

Features

•Avalanche Energy Specified

•Source−to−Drain Diode Recovery Time Comparable to a

Discrete Fast Recovery Diode

•Diode is Characterized for Use in Bridge Circuits

•IDSS and VDS(on) Specified at Elevated Temperature

•Short Heatsink Tab Manufactured − Not Sheared

•Specially Designed Leadframe for Maximum Power Dissipation

•Pb−Free Packages are Available

MAXIMUM RATINGS (TC = 25°C unless otherwise noted)

Rating Symbol Value Unit

Drain−Source Voltage VDSS 30 Vdc

Drain−Gate Voltage (RGS = 1.0 MW)VDGR 30 Vdc

Gate−Source Voltage

− Continuous

− Non−Repetitive (tp ≤ 10 ms) VGS

VGSM

±15

±20 Vdc

Vpk

Drain Current − Continuous

Drain Current − Continuous @ 100°C

Drain Current − Single Pulse (tp ≤ 10 ms)

IDM

150

Adc

Apk

Total Power Dissipation

Derate above 25°C

Total Power Dissipation @ TC = 25°C, when

mounted with the minimum rec omm ended pad siz e

PD125

1.0

2.5

W/°C

Operating and Storage Temperature Range TJ, Tstg − 55 to

150 °C

Single Pulse Drain−to−Source Avalanche

Energy − Starting TJ = 25°C

(VDD = 25 Vdc, VGS = 5.0 Vdc, Peak

IL = 50 Apk, L = 1.0 mH, RG = 25 W)

EAS 1250 mJ

Thermal Resistance

− Junction−to−Case

− Junction−to−Ambient

− Junction−to−Ambient, when mounted with the

minimum recommended pad size

RqJC

RqJA

1.0

62.5

°C/W

Maximum Lead Temperature for Soldering

Purposes, 1/8″ from case for 10 seconds TL260 °C

Stresses exceeding Maximum Ratings may damage the device. Maximum

Ratings are stress ratings only. Functional operation above the Recommended

Operating Conditions is not implied. Extended exposure to stresses above the

Recommended Operating Conditions may affect device reliability.

MARKING DIAGRAM

& PIN ASSIGNMENT

MTB

50P03HG

AYWW

Gate

Drain

Drain 3

Source

50 AMPERES

30 VOLTS

RDS(on) = 25 mW

D2PAK

CASE 418B

STYLE 2

P−Channel

MTB50P03H = Device Code

A = Assembly Location

Y = Year

WW = Work Week

G = Pb−Free Package

Preferred devices are recommended choices for future use

and best overall value.

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See detailed ordering and shipping information in the package

dimensions section on page 7 of this data sheet.

ORDERING INFORMATION

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ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)

Characteristic Symbol Min Typ Max Unit

OFF CHARACTERISTICS

Drain−to−Source Breakdown Voltage (Cpk ≥ 2.0) (Note 3)

(VGS = 0 Vdc, ID = 250 mAdc)

Temperature Coefficient (Positive)

V(BR)DSS 30

−−

26 −

−

Vdc

mV/°C

Zero Gate Voltage Drain Current

(VDS = 30 Vdc, VGS = 0 Vdc)

(VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125°C)

IDSS −

−−

−1.0

mAdc

Gate−Body Leakage Current

(VGS = ±15 Vdc, VDS = 0 Vdc) IGSS − − 100 nAdc

ON CHARACTERISTICS (Note 1)

Gate Threshold Voltage (Cpk ≥ 3.0) (Note 3)

(VDS = VGS, ID = 250 mAdc)

Threshold Temperature Coefficient (Negative)

VGS(th) 1.0

−1.5

4.0 2.0

−

Vdc

mV/°C

Static Drain−Source On−Resistance (Cpk ≥ 3.0) (Note 3)

(VGS = 5.0 Vdc, ID = 25 Adc) RDS(on) − 20.9 25 mW

Drain−Source On−Voltage (VGS = 5.0 Vdc)

(ID = 50 Adc)

(ID = 25 Adc, TJ =125°C)

VDS(on) −

−0.83

−1.5

1.3

Vdc

Forward Transconductance

(VDS = 5.0 Vdc, ID = 25 Adc) gFS 15 20 − mhos

DYNAMIC CHARACTERISTICS

Input Capacitance

(VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz)

Ciss − 3500 4900 pF

Output Capacitance Coss − 1550 2170

Transfer Capacitance Crss − 550 770

SWITCHING CHARACTERISTICS (Note 2)

Turn−On Delay Time

(VDD= 15 Vdc, ID = 50 Adc,

VGS = 5.0 Vdc, RG = 2.3 W)

td(on) − 22 30 ns

Rise Time tr− 340 466

Turn−Off Delay Time td(off) − 90 117

Fall Time tf− 218 300

Gate Charge (See Figure 8)

(VDS = 24 Vdc, ID = 50 Adc,

VGS = 5.0 Vdc)

QT− 74 100 nC

Q1− 13.6 −

Q2− 44.8 −

Q3− 35 −

SOURCE−DRAIN DIODE CHARACTERISTICS

Forward On−Voltage (IS = 50 Adc, VGS = 0 Vdc)

(IS = 50 Adc, VGS = 0 Vdc, TJ = 125°C) VSD −

−2.39

1.84 3.0

−

Vdc

Reverse Recovery Time

(See Figure 15) (IS = 50 Adc, VGS = 0 Vdc,

dIS/dt = 100 A/ms)

trr − 106 − ns

ta− 58 −

tb− 48 −

Reverse Recovery Stored Charge QRR − 0.246 − mC

INTERNAL PACKAGE INDUCTANCE

Internal Drain Inductance

(Measured from the drain lead 0.25″ from package to center of die) LD− 3.5 − nH

Internal Source Inductance

(Measured from the source lead 0.25″ from package to source bond pad) LS− 7.5 − nH

1. Pulse Test: Pulse Width ≤300 ms, Duty Cycle ≤ 2%.

2. Switching characteristics are independent of operating junction temperature.

3. Reflects typical values. Cpk = Max limit − Typ

3 x SIGMA

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TYPICAL ELECTRICAL CHARACTERISTICS

RDS(on), DRAIN−TO−SOURCE RESISTANCE

(NORMALIZED)

RDS(on), DRAIN−TO−SOURCE RESISTANCE (OHMS)

ID, DRAIN CURRENT (AMPS)

TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

IDSS, LEAKAGE (nA)

ID, DRAIN CURRENT (AMPS)

VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)

ID, DRAIN CURRENT (AMPS)

100

0 0.4 0.8 1.2 1.6 2.0

100

Figure 1. On−Region Characteristics

1.5 1.9 2.3 2.7 3.5 4.3

Figure 2. Transfer Characteristics

0 20 40 60 80 100

0.015

0.017

0.021

0.025

0.029

0.015

0.017

0.019

0.021

0.022

Figure 3. On−Resistance versus Drain Current

and Temperature Figure 4. On−Resistance versus Drain Current

and Gate Voltage

−50

0.85

0.95

1.05

1.25

1.35

0 5 10 20 25 30

100

1000

Figure 5. On−Resistance Variation with

Temperature Figure 6. Drain−to−Source Leakage

Current versus Voltage

−25 0 25 50 75 100 125 150

0.2 0.6 1.0 1.4 1.8 3.9

0.027

0.023

0.019

0 20 40 60 80 100

0.020

0.018

0.016

1.15

VGS = 10 V

4 V

8 V 100°C

25°C

TJ = −55°C

TJ = 25°C

10 V

VGS = 5 V

−55°C

VGS = 0 V

TJ = 125°C

100°C

3 V

3.5 V

TJ = 25°C

6 V

3.1

VGS = 5 V

ID = 25 A

TJ = 100°C

25°C

2.5 V

5 V

4.5 V

VDS ≥ 5 V

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POWER MOSFET SWITCHING

Switching behavior is most easily modeled and predicted

by recognizing that the power MOSFET is charge

controlled. The lengths of various switching intervals (Dt)

are determined by how fast the FET input capacitance can

be charged by current from the generator.

The published capacitance data is difficult to use for

calculating rise and fall because drain−gate capacitance

varies greatly with applied voltage. Accordingly, gate

charge data is used. In most cases, a satisfactory estimate of

average input current (IG(AV)) can be made from a

rudimentary analysis of the drive circuit so that

t = Q/IG(AV)

During the rise and fall time interval when switching a

resistive load, VGS remains virtually constant at a level

known as the plateau voltage, VSGP. Therefore, rise and fall

times may be approximated by the following:

tr = Q2 x RG/(VGG − VGSP)

tf = Q2 x RG/VGSP

where

VGG = the gate drive voltage, which varies from zero to VGG

RG = the gate drive resistance

and Q2 and VGSP are read from the gate charge curve.

During the turn−on and turn−off delay times, gate current is

not constant. The simplest calculation uses appropriate

values from the capacitance curves in a standard equation for

voltage change in an RC network. The equations are:

td(on) = RG Ciss In [VGG/(VGG − VGSP)]

td(off) = RG Ciss In (VGG/VGSP)

The capacitance (Ciss) is read from the capacitance curve a t

a voltage corresponding to the off−state condition when

calculating t d(on) and is read at a voltage corresponding to the

on−state when calculating td(off).

At high switching speeds, parasitic circuit elements

complicate the analysis. The inductance of the MOSFET

source l ead, i nside the package and in the circuit wiring which

is c ommon to b oth the d rain and g ate c urrent paths, p roduces

a voltage at the source which reduces the gate drive current.

The voltage is determined by Ldi/dt, but since di/dt is a

function of drain current, the mathematical solution is

complex. The MOSFET output capacitance also complicates

the mathematics. And finally, MOSFETs h ave finite internal

gate resistance which effectively adds t o the resistance of t he

driving source, but the internal resistance is difficult to

measure and, consequently, is not specified.

The resistive switching time variation versus gate

resistance (Figure 9) shows how typical switching

performance is affected by the parasitic circuit elements. I f

the parasitics were not present, the slope of the curves would

maintain a value of unity regardless of the switching speed.

The circuit used to obtain the data is constructed to minimize

common inductance in the drain and gate circuit loops and

is believed readily achievable with board mounted

components. Most power electronic loads are inductive; the

data in the figure is taken with a resistive load, which

approximates an optimally snubbed inductive load. Power

MOSFETs may be safely operated into an inductive load;

however, snubbing reduces switching losses.

GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)

C, CAPACITANCE (pF)

4000

8000

10000

14000

Figure 7. Capacitance Variation

12000

10 0 10 15 20 25

VGS VDS

Crss

Ciss

Crss

2000

6000

Coss

VGS = 0 V TJ = 25°C

VDS = 0 V

Ciss

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QT, TOTAL GATE CHARGE (nC) RG, GATE RESISTANCE (Ohms)

t, TIME (ns)

VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)

Figure 8. Gate−To−Source and Drain−To−Source

Voltage versus Total Charge

110

100

1000 VDD = 30 V ID = 50 A

VGS = 10 V TJ = 25°C

td(on)

td(off)

Figure 9. Resistive Switching Time

Variation versus Gate Resistance

010305060 8020 40

VGS

ID = 50 A

TJ = 25°C

VDS

DRAIN−TO−SOURCE DIODE CHARACTERISTICS

The switching characteristics of a MOSFET body diode

are very important in systems using it as a freewheeling or

commutating diode. Of particular interest are the reverse

recovery characteristics which play a major role in

determining switching losses, radiated noise, EMI and RFI.

System switching losses are largely due to the nature of

the body diode itself. The body diode is a minority carrier

device, therefore it has a finite reverse recovery time, trr, due

to the storage of minority carrier charge, QRR, as shown in

the typical reverse recovery wave form of Figure 12. It is this

stored charge that, when cleared from the diode, passes

through a potential and defines an energy loss. Obviously,

repeatedly forcing the diode through reverse recovery

further increases switching losses. Therefore, one would

like a diode with short trr and low QRR specifications to

minimize these losses.

The abruptness of diode reverse recovery effects the

amount of radiated noise, voltage spikes, and current

ringing. The mechanisms at work are finite irremovable

circuit parasitic inductances and capacitances acted upon by

high di/dts. The diode’s negative di/dt during ta is directly

controlled by the device clearing the stored charge.

However, the positive di/dt during tb is an uncontrollable

diode characteristic and is usually the culprit that induces

current ringing. Therefore, when comparing diodes, the

ratio of tb/ta serves as a good indicator of recovery

abruptness and thus gives a comparative estimate of

probable noise generated. A ratio of 1 is considered ideal and

values less than 0.5 are considered snappy.

Compared to ON Semiconductor standard cell density

low voltage MOSFETs, high cell density MOSFET diodes

are faster (shorter trr), have less stored charge and a softer

reverse recovery characteristic. The softness advantage of

the high cell density diode means they can be forced through

reverse recovery at a higher di/dt than a standard cell

MOSFET diode without increasing the current ringing or the

noise generated. In addition, power dissipation incurred

from switching the diode will be less due to the shorter

recovery time and lower switching losses.

IS, SOURCE CURRENT (AMPS)

VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

0.4 0.6 0.8 1.0 1.2 1.4

VGS = 0 V

TJ = 25°C

1.6 1.8 2.0 2.2 2.4

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IS, SOURCE CURRENT

t, TIME

Figure 11. Reverse Recovery Time (trr)

di/dt = 300 A/msStandard Cell Density

High Cell Density

trr

SAFE OPERATING AREA

The Forward Biased Safe Operating Area curves define

the maximum simultaneous drain−to−source voltage and

drain current that a transistor can handle safely when it is

forward biased. Curves are based upon maximum peak

junction temperature and a case temperature (TC) of 25°C.

Peak repetitive pulsed power limits are determined by using

the thermal response data in conjunction with the procedures

discussed in AN569, “Transient Thermal Resistance −

General Data and Its Use.”

Switching between the off−state and the on−state may

traverse any load line provided neither rated peak current

(IDM) nor rated voltage (VDSS) is exceeded, and that the

transition time (tr, tf) does not exceed 10 ms. In addition the

total power averaged over a complete switching cycle must

not exceed (TJ(MAX) − TC)/(RqJC).

A power MOSFET designated E−FET can be safely used

in switching circuits with unclamped inductive loads. For

reliable operation, the stored ener gy from circuit inductance

dissipated in the transistor while in avalanche must be less

than the rated limit and must be adjusted for operating

conditions di ffering from those specified. Although industry

practice is to rate in terms of energy, avalanche energy

capability is not a constant. The energy rating decreases

non−linearly with an increase of peak current in avalanche

and peak junction temperature.

Although many E−FETs can withstand the stress of

drain−to−source avalanche at currents up to rated pulsed

current (IDM), the energy rating is specified at rated

continuous current (ID), in accordance with industry

custom. The energy rating must be derated for temperature

as shown in the accompanying graph (Figure 13). Maximum

energy at currents below rated continuous ID can safely be

assumed to equal the values indicated.

VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) TJ, STARTING JUNCTION TEMPERATURE (°C)

EAS, SINGLE PULSE DRAIN−TO−SOURCE

AVALANCHE ENERGY (mJ)

ID, DRAIN CURRENT (AMPS)

Figure 12. Maximum Rated Forward Biased

Safe Operating Area

25 15050 100 12575

1400

800

600

400

200

1000

Figure 13. Maximum Avalanche Energy versus

Starting Junction Temperature

0.1 1.0 10 100

100

1000

100 ms

1 ms

10 ms

RDS(on) LIMIT

THERMAL LIMIT

PACKAGE LIMIT

VGS = 20 V

SINGLE PULSE

TC = 25°C

ID = 50 A

1200

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TYPICAL ELECTRICAL CHARACTERISTICS

r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE

(NORMALIZED)

t, TIME (s)

Figure 14. Thermal Response

1.0E−05

1.0

0.01

0.1

0.2

0.02

0.01

SINGLE PULSE

RqJC(t) = r(t) RqJC

D CURVES APPLY FOR POWER

PULSE TRAIN SHOWN

READ TIME AT t1

TJ(pk) − TC = P(pk) RqJC(t)

P(pk)

DUTY CYCLE, D = t1/t2

Figure 15. Diode Reverse Recovery Waveform

di/dt

trr

0.25 IS

TIME

0.5

1.5

2.0

2.5

25 50 75 100 125 150

TA, AMBIENT TEMPERATURE (°C)

PD, POWER DISSIPATION (WATTS)

Figure 16. D2PAK Power Derating Curve

0.1

D = 0.5

0.05

RqJA = 50°C/W

Board material = 0.065 mil FR−4

Mounted on the minimum recommended footprint

Collector/Drain Pad Size ≈450 mils x 350 mils

1.0E−04 1.0E−03 1.0E−02 1.0E−01 1.0E+00 1.0E+01

ORDERING INFORMATION

Device Package Shipping†

MTB50P03HDL D2PAK 50 Units / Rail

MTB50P03HDLG D2PAK

(Pb−Free)

MTB50P03HDLT4 D2PAK 800 / Tape & Reel

MTB50P03HDLT4G D2PAK

(Pb−Free)

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

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PACKAGE DIMENSIONS

SEATING

PLANE

−T−

0.13 (0.005) T

231

3 PL

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A0.340 0.380 8.64 9.65

B0.380 0.405 9.65 10.29

C0.160 0.190 4.06 4.83

D0.020 0.035 0.51 0.89

E0.045 0.055 1.14 1.40

G0.100 BSC 2.54 BSC

H0.080 0.110 2.03 2.79

J0.018 0.025 0.46 0.64

K0.090 0.110 2.29 2.79

S0.575 0.625 14.60 15.88

V0.045 0.055 1.14 1.40

−B−

NOTES:

1. DIMENSIONING AND TOLERANCING

PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. 418B−01 THRU 418B−03 OBSOLETE,

NEW STANDARD 418B−04.

F0.310 0.350 7.87 8.89

L0.052 0.072 1.32 1.83

M0.280 0.320 7.11 8.13

N0.197 REF 5.00 REF

P0.079 REF 2.00 REF

R0.039 REF 0.99 REF

VARIABLE

CONFIGURATION

ZONE RN P

VIEW W−W VIEW W−W VIEW W−W

123

D2PAK 3

CASE 418B−04

ISSUE J

STYLE 2:

PIN 1. GATE

2. DRAIN

3. SOURCE

4. DRAIN

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

8.38

0.33

1.016

0.04

17.02

0.67

10.66

0.42

3.05

0.12

5.08

0.20

ǒmm

inchesǓ

SCALE 3:1

SOLDERING FOOTPRINT*

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operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

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