PIC12F675-I/SNVAOG - Microchip Technology, Inc.

 2009 Microchip Technology Inc. DS41190F

PIC12F629/675

Data Sheet

8-Pin, Flash-Based 8-Bit

CMOS Microcontrollers

*8-bit, 8-pin Devices Protected by Microchip’s Low Pin Count Patent: U.S. Patent No. 5,847,450.

Additional U.S. and foreign patents and applications may be issued or pending.

DS41190F-page 2  2009 Microchip Technology Inc.

Information contained in this publication regarding device

applications a nd the lik e is p ro vided on ly for yo ur con ve nien ce

and may be supers eded by up dates. I t is you r r es ponsibil it y to

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Printed on recycled paper.

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digit al Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC® MCUs and d sPIC® DSCs, KEELOQ® code hopping

devices, Serial EEPROMs, microperiph erals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

 2009 Microchip Technology Inc. DS41190F-page 3

PIC12F629/675

High-Performance RISC CPU:

• Only 35 Instructions to Learn

- All single-cycle instructions except branches

• Operati ng Speed:

- DC – 20 MHz oscillator/clock input

- DC – 200 ns instruction cycle

• Inter rupt Capability

• 8-Level Deep Hardware Stack

• Direct, Indirect, and Relative Addressing modes

S pecial Microcontroller Features:

• Internal and External Oscillator Options

- Precision Internal 4 MHz oscillator factory

calibrated to ±1%

- External Oscillator support for crystals and

resonators

-5s wake-up from Sleep, 3.0V, typical

• Power-Saving Sleep mode

• Wide Operating Voltage Range – 2.0V to 5.5V

• Industri al and Ext end ed Temperatur e Range

• Low-Power Power-on Reset (POR)

• Power-up Timer (PWRT) and Oscillator Start-up

Timer (OST)

• Brown-out Detect (BOD)

• Watchdog Timer (WDT) with Independent

Oscillator for Reliable Operation

• Multiplexed MCLR/Input Pin

• Interrupt-on-Pin Change

• Individual Programmable Weak Pull-ups

• Programmable Code Protection

• High Endurance Flash/EEPROM Cell

- 100,000 writ e Flash endurance

- 1,000,000 write EEPROM endurance

- Flash/Data EEPROM Retention: > 40 years

Low-Power Features:

• Standby Current:

- 1 nA @ 2.0V, typical

• Operating Current:

-8.5A @ 32 kHz, 2.0V, typical

-100A @ 1 MHz, 2.0V, typical

• Watchdog Timer Current

- 300 nA @ 2.0V, typical

• Timer1 Oscillator Current:

-4A @ 32 kHz, 2.0V, typical

Peripheral Feat ures:

• 6 I/O Pins with Individual Direction Control

• High Current Sink/Source for Direct LED Drive

• Analog Comparator module with:

- One analog comparator

- Programmable on-chip comparator voltage

reference (CVREF) module

- Programmable input multiplexing from device

inputs

- Comparator output is externally accessible

•Analog- to-Digital Converter module (PIC12F675):

- 10-bit resolution

- Programmable 4-channel input

- Voltage reference input

• Timer0: 8-Bit Timer/Counter with 8-Bit

Programmable Prescaler

• Enhanced Timer1:

- 16-bit timer/counter with prescaler

- External Gate Input mode

- Option to use OSC1 and OSC2 in LP mode

as Timer1 oscillator, if INTOSC mode

selected

• In-Circuit Serial ProgrammingTM (ICSPTM) via

two pins

* 8-bit, 8-pin devices protected by Microchip’s Low Pin Count Patent: U.S. Patent No. 5,847,450. Additional U.S. and

foreign patents and applications may be issued or pending.

Device

Program

Memory Data Memory I/O 10-bit A/D

(ch) Comparators Timers

8/16-bit

Flash

(words) SRAM

(bytes) EEPROM

(bytes)

PIC12F629 1024 64 128 6 — 1 1/1

PIC12F675 1024 64 128 6 4 1 1/1

8-Pin Flash-Based 8-Bit CMOS Microcontroller

PIC12F629/675

DS41190F-page 4  2009 Microchip Technology Inc.

Pin Diagrams

VSSVDD

GP5/T1CKI/OSC1/CLKIN

GP4/AN3/T1G/OSC2/CLKOUT

GP3/MCLR/VPP

GP0/AN0/CIN+/ICSPDAT

GP1/AN1/CIN-/VREF/ICSPCLK

GP2/AN2/T0CKI/INT/COUT

PIC12F675

VSS

VDD

GP5/T1CKI/OSC1/CLKIN

GP4/T1G/OSC2/CLKOUT

GP3/MCLR/VPP

GP0/CIN+/ICSPDAT

GP1/CIN-/ICSPCLK

GP2/T0CKI/INT/COUT

PIC12F629

8-pin PDIP, SOIC, DFN-S, DFN

 2009 Microchip Technology Inc. DS41190F-page 5

PIC12F629/675

Table of Contents

1.0 Device Overview................. ............... ............... .............. ............... ............... ............... ........... .. ...... ..... ...... ...... ......... ...... ...... ..... . 7

2.0 Memory Org anizati o n.. ............... .............. ............... ............... ................... .............. .................................................................... 9

3.0 GPIO Por t ...................... ................... ................... ................... ............... .................. ................................................................. 21

4.0 Timer0 Module............................... .. .... .. .... ..... .... .. .... .. .. ....... .... .. .. .... .. ....... .. .... .. .... .. .. ................................................................ 29

5.0 Timer1 Module with Gate Control....................... .. .. .... .. .. ....... .... .. .... .. .. ....... .... .. .. .... .. ....... .. .... .. . ............. ...... ...... ..... ...... ...... ...... 32

6.0 Comparat or Module. ................................................................................................................................................................. 37

7.0 Analog-to-Digital Converter (A/D) Module (PIC12F675 only) ........................................... .... .... .... ......... .. ................................. 43

8.0 Data EEPROM Memory ............................................................................................................................................................ 49

9.0 Special Features of the CPU .................................................................................................................................................... 53

10.0 Instruction Set Summary ........................................................................................................................................................... 71

11.0 Development Support ............................................ .. .... .. ......... .. .... .. .... ....... .... .. .... .. ......... .......................................................... 79

12.0 Electri cal Sp e cifica tio n s ..... ........... ............... .......... ............... .......... ............... .......... ................................................................. 83

13.0 DC and AC Characteristics Graphs and Tables ..................................................................................................................... 105

14.0 Packaging Information ............................................................................................................................................................ 115

Appendix A: Data Sheet Revision History .............................. ........... .... .... .... ........... ...... .... ........... .................................................... 125

Appendix B: Device Differences ....................................................................................................................................................... 125

Appendix C: Device Migrations .................................. .... .... .... .. ......... .... .... .... ....... .... .... .... .. ............................................................... 126

Appendix D: Migrating from other PIC® Devices .............................................................................................................................. 126

Index ................................................................................................................................................................................................. 127

On-Line Support ...................................... .. .... .... ......... .... .... .... ......... .... .... .... ......... .... .... ..................................................................... 131

Systems Information and Upgrade Hot Line ..................................................................................................................................... 131

Reader Response ............................................................................................................................................................................. 132

Product Identification System ........................................................................................................................................................... 133

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Customer No tific atio n Syst em

PIC12F629/675

DS41190F-page 6  2009 Microchip Technology Inc.

NOTES:

 2009 Microchip Technology Inc. DS41190F-page 7

PIC12F629/675

1.0 DEVICE OVERVIEW

This do cu me nt co nta i ns dev ic e spec if i c in for m at ion fo r

the PIC12F629/675. Additional information may be

found in the PIC® Mid-Range Reference Manual

(DS33023), which may be obtained from your local

Microchip Sales Representative or downloaded from

the Microchip web site. The Reference Manual should

be co nside red a c omple me nta ry do cume nt to thi s Da ta

Sheet, and is hig hly rec omm end ed re ading for a bett er

understandi ng o f the d ev ic e arc hi tec ture a nd o pera tio n

of the peripheral modules.

The PIC 12 F629 an d PI C12F 67 5 dev ice s are covere d

by this Data Sheet. They are identical, except the

PIC12F6 75 ha s a 10-b it A /D co nver ter. They come i n

8-pin PDIP, SOIC, MLF-S and DFN packages.

Figure 1-1 shows a block diagram of the PIC12F629/

675 dev ices . Table 1-1 shows th e pi nou t de scrip tio n.

FIGURE 1-1: PIC12F62 9/675 BLOCK DIAGRAM

Flash

Program

Memory

1K x 14

13 Data Bus 8

Program

Bus

Instruction Reg

Program Counter

8-Level Stack

(13-bit)

RAM

File

Registers

64 x 8

Direct Addr 7

Addr(1)

Addr MUX

Indirect

Addr

FSR Reg

STATUS Reg

MUX

ALU

W Reg

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Instruction

Decode &

Control

OSC1/CLKIN

OSC2/CLKOUT VDD, VSS

Brown-out

Detect

Timing

Generation

GP5/T1CKI/OSC1/CLKIN

Internal

4 MHz

RAM

GP4/AN3/T1G/OSC2/CLKOUT

GP3/MCLR/VPP

GP2/AN2/T0CKI/INT/COUT

GP1/AN1/CIN-/VREF

GP0/AN0/CIN+

Oscillator

Note 1: Higher or der bit s are from STATUS r egis ter.

Analog

Timer0 Timer1

DATA

EEPROM

128 bytes

EEDATA

EEADDR

Comparator

Analog to Digital Converter

(PIC12F675 only)

AN0 AN1AN2 AN3 CIN- CIN+ COUT

T0CKI

T1CKI

VREF

and reference

T1G

PIC12F629/675

DS41190F-page 8  2009 Microchip Technology Inc.

TABLE 1-1: PIC12F629/675 PINOUT DESCRIPTION

Name Function Input

Type Output

Type Description

GP0/AN0/CIN+/ICSPDAT GP0 TTL CMOS Bidirectional I/O w/ programmable pull-up and

interrupt-on-change

AN0 AN A/D Channel 0 input

CIN+ AN Comparator input

ICS PDAT TTL CMO S Serial programming I/O

GP1/AN1/CIN-/VREF/

ICSPCLK GP1 TTL CMOS Bidirectional I/O w/ programmable pull-up and

interrupt-on-change

AN1 AN A/D Channel 1 input

CIN- AN Comparator input

VREF AN External voltage reference

ICSPCLK ST Serial pr ogramming clock

GP2/AN2/T0CKI/INT/COUT GP2 ST CMOS Bidirectional I/O w/ programmable pull-up and

interrupt-on-change

AN2 AN A/D Channel 2 input

T0CKI ST TMR0 clock input

INT ST External interrupt

COUT CMOS Comparator output

GP3/MCLR/VPP GP 3 TTL Input port w/ interrupt-on-change

MCLR ST Master Clear

VPP HV Programming voltage

GP4/AN3/T1G/OSC2/

CLKOUT

GP4 TTL CMOS Bidirectional I/O w/ programmable pull-up and

interrupt-on-change

AN3 AN A/D Channel 3 input

T1G ST TMR1 gate

OSC2 XTAL Crystal/resonator

CLKOUT CMOS FOSC/4 outp ut

GP5/T1CKI/OSC1/CLKIN

GP5 TTL CMOS Bidirectional I/O w/ programmable pull-up and

interrupt-on-change

T1CKI S T TMR1 cloc k

OSC1 XTAL Crystal/resonator

CLKIN ST External clock input/RC oscillator connection

VSS VSS Power Ground reference

VDD VDD Power Positive supply

Legend: Shade = PIC12F675 only

TTL = TTL input buffer, ST = Schmitt Trigger input buffer

 2009 Microchip Technology Inc. DS41190F-page 9

PIC12F629/675

2.0 MEMORY ORGANIZATION

2.1 Program Memory Organization

The PIC12F629/675 devices have a 13-bit program

counter capable of addressing an 8K x 14 program

memory space. Only the first 1K x 14 (0000h-03FFh)

for the PIC12F629/675 devices is physically imple-

mented. Accessing a location above these boundaries

will cause a w rap-arou nd w ithin the fi rst 1K x 14 sp ac e.

The Res et vector is at 000 0h and the interru pt vector is

at 0004h (see Figure 2-1).

FIGURE 2-1: PROGRAM MEMORY MAP

AND STACK FOR THE

DSTEMP/675

2.2 Data Memory Organization

The data memory (see Figure 2-2) is partitioned into

two banks, which contain the General Purpose

Registers and the Special Function Registers. The

Special Function Registers are located in the first 32

locatio ns of eac h bank. Registe r l oc ati ons 2 0h -5Fh are

General Purpose Registers, implemented as static

RAM and are mapped across both banks. All other

RAM is unimplemen ted and returns ‘0’ when read. RP0

(STATUS<5>) is the bank select bit.

•RP0 = 0 Bank 0 is selected

•RP0 = 1 Bank 1 is selected

2.2.1 GENERAL PURPOSE REGISTER

FILE

The register file is organized as 64 x 8 in the

PIC12F629/675 devices. Each register is accessed,

either directly or indirectly, through the File Select

INDF and FSR Registers”).

PC<12:0>

000h

0004

0005

03FFh

0400h

1FFFh

Stack Level 1

Stack Level 8

Reset Vector

Interrupt Vector

On-chip Program

Memory

CALL, RETURN

RETFIE, RETLW

Stack Level 2

Note: The IRP and RP1 bits STATUS<7:6> are

reser ved and shoul d always be mai ntained

as ‘0’s.

PIC12F629/675

DS41190F-page 10  2009 Microchip Technology Inc.

2.2.2 SPECIAL FUNCTION REGISTERS

The Special Function Registers are registers used by

the CPU and peripheral functions for controlling the

desired operation of the device (see Table 2-1). These

registers are static RAM.

The special registers can be classified into two sets:

core and peripheral. The Special Function Registers

assoc iated with th e “core” are described in this sec tion.

Those related to the operation of the peripheral

features are described in the section of that peripheral

feature.

FIGURE 2-2: DATA MEMORY MAP OF

THE PIC12F 62 9/67 5

Indirect addr.(1)

TMR0

PCL

STATUS

FSR

GPIO

PCLATH

INTCON

PIR1

TMR1L

TMR1H

T1CON

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

20h

7Fh

Bank 0

Unimplemented data memory locations, read as ‘0’.

1: Not a physical register.

2: PIC12F675 only.

CMCON VRCON

General

Purpose

Registers accesses

20h-5Fh

64 Bytes

EEDATA

EEADR

EECON2(1)

5Fh

60h

File

Address File

Address

WPU

IOC

Indirect addr.(1)

OPTION_REG

PCL

STATUS

FSR

TRISIO

PCLATH

INTCON

PIE1

PCON

OSCCAL

80h

81h

82h

83h

84h

85h

86h

87h

88h

89h

8Ah

8Bh

8Ch

8Dh

8Eh

8Fh

90h

91h

92h

93h

94h

95h

96h

97h

98h

99h

9Ah

9Bh

9Ch

9Dh

9Eh

9Fh

A0h

FFh

Bank 1

DFh

E0h

ADRESH(2)

ADCON0(2)

EECON1

ADRESL(2)

ANSEL(2)

 2009 Microchip Technology Inc. DS41190F-page 11

PIC12F629/675

TABLE 2-1: SPECIAL FUNCTION REGISTERS SUMMARY

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOD Page

Bank 0

00h INDF(1) Addressing this Location uses Contents of FSR to Address Data Memory 0000 0000 20,61

01h TMR0 Timer0 Module’s Register xxxx xxxx 29

02h PCL Program Counter ’s (PC) Least Significant Byte 0000 0000 19

03h STATUS IRP(2) RP1(2) RP0 TO PD ZDCC

0001 1xxx 14

04h FSR Indirect Data Memory Address Pointer xxxx xxxx 20

05h GPIO — — GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 --xx xxxx 21

06h —Unimplemented — —

07h —Unimplemented — —

08h —Unimplemented — —

09h —Unimplemented — —

0Ah PCLATH — — — Write Buffer for Upper 5 bits of Program Counter ---0 0000 19

0Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 15

0Ch PIR1 EEIF ADIF ——CMIF——TMR1IF00-- 0--0 17

0Dh —Unimplemented — —

0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit Timer1 xxxx xxxx 32

0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit Timer1 xxxx xxxx 32

10h T1CON — TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON -000 0000 35

11h —Unimplemented — —

12h —Unimplemented — —

13h —Unimplemented — —

14h —Unimplemented — —

15h —Unimplemented — —

16h —Unimplemented — —

17h —Unimplemented — —

18h —Unimplemented — —

19h CMCON —COUT —CINV CIS CM2 CM1 CM0 -0-0 0000 38

1Ah —Unimplemented — —

1Bh —Unimplemented — —

1Ch —Unimplemented — —

1Dh —Unimplemented — —

1Eh ADRESH(3) Most Significant 8 bits of the Left Shifted A/D Result or 2 bits of the Right Shifted Result xxxx xxxx 44

1Fh ADCON0(3) ADFM VCFG —— CHS1 CHS0 GO/DONE ADON 00-- 0000 45,61

Legend: — = unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,

shaded = unimplemented

Note 1: This is not a physical register.

2: These bits are reserved and should always be maintained as ‘0’.

3: PIC12F675 only.

PIC12F629/675

DS41190F-page 12  2009 Microchip Technology Inc.

Bank 1

80h INDF(1) Addressing this Location uses Contents of FSR to Address Data Memory 0000 0000 20,61

81h OPTION_REG GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 14,31

82h PCL Program Counter ’s (PC) Least Significant Byte 0000 0000 19

83h STATUS IRP(2) RP1(2) RP0 TO PD ZDCC0001 1xxx 14

84h FSR Indirect Data Memory Address Pointer xxxx xxxx 20

85h TRISIO —— TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 21

86h —Unimplemented — —

87h —Unimplemented — —

88h —Unimplemented — —

89h —Unimplemented — —

8Ah PCLATH ——— Write Buffer for Upper 5 bits of Program Counter ---0 0000 19

8Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 15

8Ch PIE1 EEIE ADIE ——CMIE——TMR1IE00-- 0--0 16

8Dh —Unimplemented — —

8Eh PCON ——————PORBOD ---- --0x 18

8Fh —Unimplemented — —

90h OSCCAL CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 — — 1000 00-- 18

91h —Unimplemented — —

92h —Unimplemented — —

93h —Unimplemented — —

94h —Unimplemented — —

95h WPU —— WPU5 WPU4 — WPU2 WPU1 WPU0 --11 -111 21

96h IOC —— IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 --00 0000 23

97h —Unimplemented — —

98h —Unimplemented — —

99h VRCON VREN —VRR —VR3 VR2 VR1 VR0 0-0- 0000 42

9Ah EEDATA Data EEPROM Data Regist er 0000 0000 49

9Bh EEADR — Data EEPROM Address Regis ter -000 0000 49

9Ch EECON1 ———— WRERR WREN WR RD ---- x000 50

9Dh EECON2(1) EEPROM Control Register 2 ---- ---- 50

9Eh ADRESL(3) Least Significant 2 bits of the Left Shifted A/D Result of 8 bits or the Right Shifted Result xxxx xxxx 44

9Fh ANSEL(3) — ADCS2 ADCS1 ADCS0 ANS3 ANS2 ANS1 ANS0 -000 1111 46,61

Legend: — = unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,

shaded = unimplemented

Note 1: This is not a physical register .

2: These bits are reserved and should always be maintained as ‘0’.

3: PIC12F675 only.

TABLE 2-1: SPECIAL FUNCTION REGISTERS SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOD Page

 2009 Microchip Technology Inc. DS41190F-page 13

PIC12F629/675

2.2.2.1 STATUS Register

The S TATUS regi ste r, sho wn i n R e gis ter 2-1, contains :

• the arithm etic status of t he ALU

• the Reset status

• the bank select bits for data memory (SRAM)

The STATUS register can be the destination for any

instruction, like any other register. If the STATUS

the Z, DC or C bits, then the write to these three bits is

disabl ed. These bit s are set or clea red according to the

device logic. Furthermore, the TO and PD bits are not

writable. Therefore, the result of an instruction with the

STATUS register as destination may be different than

intended.

For example, CLRF STATUS will clear the upper three

bits and set the Z bit. This leaves the STATUS register

as 000u u1uu (where u = unchanged).

It is recommended, therefore, that only BCF, BSF,

SWAPF and MOVWF instructions are used to alter the

STATUS register, because these instructions do not

affect any Status bits. For other instructions not affect-

ing any S tat us bits, see the “In struction Set Summary”.

Note 1: Bits IRP a nd RP1 (ST ATUS<7:6>) are n ot

used by the PIC12F629/675 and should

be maintained as clear. Use of these bits

is not rec ommended, sinc e this may af fect

upward compatibility with future products.

2: The C and DC bits operate as a Borrow

and Digit Borrow out bit, respectively, in

subtraction. See the SUBLW and SUBWF

instructions for examples.

Reserved Reserved R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

IRP RP1 RP0 TO PD ZDCC

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 IRP: This bit is reserved and should be maintained as ‘0’

bit 6 RP1: This bit is reserved and should be maintained as ‘0’

bit 5 RP0: Register Bank Select bit (used for direct addressing)

0 = Bank 0 (00h - 7Fh)

1 = Bank 1 (80h - FFh)

bit 4 TO: Time-out bit

1 = After power-up, CLRWDT instruction, or SLEEP instruction

0 = A WDT Time-out occurred

bit 3 PD: Power-down bit

1 = After power-up or by the CLRWDT instruction

0 = By execution of the SLEEP instruction

bit 2 Z: Zero bit

1 = The result of an arithmetic or logic operation is zero

0 = The result of an arithmetic or logic operation is not zero

bit 1 DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instruct ions)

For borrow, the polarity is reversed.

1 = A carry-ou t fro m the 4th low order bi t of t he result occurred

0 = No carry-out from the 4th low order bit of the result

bit 0 C: Carry/borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)

1 = A carry-out from the Most Significant bit of the result occurred

0 = No carry-out from the Most Significant bit of the result occurred

Note: For borrow the polarity is reversed. A subtractio n is executed by adding the two’s complement of the second

operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the

source register.

PIC12F629/675

DS41190F-page 14  2009 Microchip Technology Inc.

2.2.2.2 OPTION Register

The OPTION register is a readable and writable

configure:

• TMR0/WDT prescaler

• External GP2 /INT inte rrup t

•TMR0

• Weak pull-ups on GPI O

Note: To achieve a 1:1 prescaler assignment for

TMR0, as sign the pre scale r to th e WDT b y

setting PSA bit to ‘1’ (OPTION<3>). See

Section 4.4 “Prescaler”.

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 GPPU: GPIO Pull-up Enable bit

1 = GPIO pull-ups are disabled

0 = GPIO pull-ups are enabled by individual PORT latch values

bit 6 INTEDG: Interrupt Edge Select bit

1 = Interrupt on rising edge of GP2/INT pin

0 = Interrupt on falling edge of GP2/INT pin

bit 5 T0CS: TMR0 Clock Source Select bit

1 = Transition on GP2/T 0CKI pin

0 = Internal instruction cycle clock (CLKOUT)

bit 4 T0SE: TMR0 Source Edge Select bit

1 = Increment on high-to-low transition on GP2/T0CKI pin

0 = Increment on low-to-high transition on GP2/T0CKI pin

bit 3 PSA: Prescaler Assig nm ent bit

1 = Prescaler is assigned to the WDT

0 = Prescaler is assigned to the TIMER0 module

bit 2-0 PS2:PS0: Prescaler Rate Select bit s

000

001

010

011

100

101

110

111

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

1 : 1

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

Bit Value TMR0 Rate WDT Rate

 2009 Microchip Technology Inc. DS41190F-page 15

PIC12F629/675

2.2.2.3 INTCON Register

The INTCON register is a readable and writable

for TMR0 register overflow, GPIO port change and

external GP2/INT pin interrupts.

Note: Interru pt flag bit s are set whe n an in terr upt

conditi on occurs, regardless of the sta te of

its corresponding enable bit or the global

enable bit, GIE (INTCON<7>). User soft-

ware should ensure the appropriate

interrupt flag bits are clear prior to enabling

an interrupt.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

GIE PEIE T0IE INTE GPIE T0IF INTF GPIF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 GIE: Global Interrupt Enable bit

1 = Enables all unmasked interrupts

0 = Disables all interrupts

bit 6 PEIE: Peripheral Interrupt Enable bit

1 = Enables all unmasked peripheral interrupts

0 = Disables all peripheral interrupts

bit 5 T0IE: TMR0 Overflow Interrupt Enable bit

1 = Enables the TMR0 interrupt

0 = Disables the TMR0 interrupt

bit 4 INTE: GP2/INT External Interrupt Enable bit

1 = Enables the GP2/INT external interrupt

0 = Disables the GP2/INT external interrupt

bit 3 GPIE: Port Change Interrupt Enable bit(1)

1 = Enables the GPIO port change interrupt

0 = Disables the GPI O port change interrupt

bit 2 T0IF: TMR0 Overflow Interrupt Flag bit(2)

1 = TMR0 register has overflowed (must be cleared in software)

0 = TMR0 register did not overflow

bit 1 INTF: GP2/INT External Interrupt Flag bit

1 = The GP2/INT external interrup t occurre d (must be clea red in software)

0 = The GP2/INT external interrupt did not occur

bit 0 GPIF: Port Change Interrupt Flag bit

1 = When at least one of the GP5:GP0 pins changed state (must be cleared in software)

0 = None of the GP5:GP0 pins have changed state

Note 1: IOC register must also be enabled to enable an interrupt-on-change.

2: T0IF bit is set when TIMER0 rolls over. TIMER0 is unchanged on Reset and should be initialized befo re

clearing T0IF bit.

PIC12F629/675

DS41190F-page 16  2009 Microchip Technology Inc.

2.2.2.4 PIE1 Regist er

The PIE1 regis te r con t ai ns th e in terrupt enabl e bi t s, a s

shown in Register 2-4.

Note: Bit PEIE (INTCON<6>) must be set to

enable any peripheral interrupt.

R/W-0 R/W-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0

EEIE ADIE — — CMIE — — TMR1IE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 EEIE: EE Write Complete Interrupt Enable bit

1 = Enables the EE write complete interrupt

0 = Disables the EE write complete interrupt

bit 6 ADIE: A/D Converter Interrupt Enable bit (PIC12F675 only)

1 = Enables the A/D converter interrupt

0 = Disables the A/D converter inte rru pt

bit 5-4 Unimplemented: Read as ‘0’

bit 3 CMIE: Comp ara tor Interrupt Enable bit

1 = Enables the comparator interrupt

0 = Disables the co mparator interrupt

bit 2-1 Unimplemented: Read as ‘0’

bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit

1 = Enables the TMR1 overflow interrupt

0 = Disables the TMR1 overflow interrupt

 2009 Microchip Technology Inc. DS41190F-page 17

PIC12F629/675

2.2.2.5 PIR1 Register

The PIR1 register contains the interrupt flag bits, as

shown in Register 2-5.

Note: Interru pt fl ag bit s are set when an in terrupt

conditi on occ urs , re gardless of the st a te of

its corresponding enable bit or the global

enable bit, GIE (INTCON<7>). User

software should ensure the appropriate

interr upt flag b its ar e clear prior to e nabling

an interrupt.

R/W-0 R/W-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0

EEIF ADIF ——CMIF ——TMR1IF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 EEIF: EEPROM Write Operation Interrupt Flag bit

1 = The write operation completed (must be cleared in software)

0 = The write operation has not completed or has not been started

bit 6 ADIF: A/D Converter Interrupt Flag bit (PIC12F675 only)

1 = The A/D conversion is complete (must be cleared in software)

0 = The A/D conversion is not complete

bit 5-4 Unimplemented: Read as ‘0’

bit 3 CMIF: Comparator Interrupt Flag bit

1 = Comparator input has changed (must be cleared in software)

0 = Comparator input has not changed

bit 2-1 Unimplemented: Read as ‘0’

bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit

1 = TMR1 register overflowed (m ust be cleared in software)

0 = TMR1 register did not overflow

PIC12F629/675

DS41190F-page 18  2009 Microchip Technology Inc.

2.2.2.6 PCON Regist er

The Power Control (PCON) register contains flag bits

to differentiate between a:

• Power-on Reset (PO R)

• Brown-out Detect (BOD)

• Watchdog Timer Reset (WDT)

• External MCLR Reset

The PCON Register bits are shown in Register 2-6.

2.2.2.7 OSCCAL Register

The Oscill ator Calibration register (OSCCAL) is used to

calibra te the inte rnal 4 MHz osc ill ato r. It contains 6 bits

to adjust the frequency up or down to achieve 4 MHz.

The OSCCAL register bits are shown in Register 2-7.

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-x

— — — — — —PORBOD

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-2 Unimplemented: Read as ‘0’

bit 1 POR: Power-on Reset Status bit

1 = No Power-on Reset occurred

0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

bit 0 BOD: Brown-out Detect Status bit

1 = No Brown-out Detect occurred

0 = A Brown-out Detect occurred (must be set in software after a Brown-out Detect occurs)

R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0

CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-2 CAL5:CAL0: 6-bit Signed Oscillator Calibration bits

111111 = Maximum frequency

100000 = Center frequency

000000 = Minimum frequency

bit 1-0 Unimplemented: Read as ‘0’

 2009 Microchip Technology Inc. DS41190F-page 19

PIC12F629/675

2.3 PCL and PCLATH

The Program Counter (PC) is 13-bits wide. The low byte

comes from th e PCL register, which is a r eadable and

writable register. The high byte (PC<12:8>) is not

directly rea dable or wr itable and comes from PCLAT H.

On any Reset, the PC is clear ed. Figure 2-3 shows the

two situations for the loading of the PC. The upper

example in Figur e 2-3 shows how the PC is lo aded on

a write to PCL (PCLATH<4:0>  PCH). The lower

example in Figure 2-3 shows how the PC is loaded

during a CALL or GOTO instruction (PCLATH<4:3> 

PCH).

FIGURE 2-3: LOADING OF PC IN

DIFFERENT SITUATIONS

2.3.1 COMPUTED GOTO

A comput ed GOTO is a ccom pli shed by a ddi ng a n offset

to the PC (ADDWF PCL). When pe rformin g a t able rea d

using a computed GOTO method, care should be

exercised if the table location crosses a PCL memory

boundary (each 256-byte block). Refer to the

Application Note, “Implementing a Table Read”

(AN556).

2.3.2 STACK

The PIC1 2F629/675 fam ily has an 8-le vel deep x 1 3-bit

wide hardware stack (see Figure 2-1). The stack space

is not part of either program or data space and the

Stack Pointer is not readable or writable. The PC is

PUSHed onto the stack when a CALL instruction is

execute d, or an interrup t causes a branch . The stac k is

POPed in th e event of a RETURN, RETLW or a RETFIE

instruction execution. PCLATH is not affected by a

PUSH or POP operation.

The st ack operates as a circular buffer . This means that

af ter the st ack ha s be en PUSHed ei ght time s, th e nin th

push ove rwr ites the va lu e that was s tored fro m the firs t

push. The tenth p us h ov erw ri tes the seco nd push (an d

so on).

12 8 7 0

5PCLATH<4:0>

PCLATH

Instruction with

ALU result

GOTO, CALL

Opcode < 10:0 >

12 11 10 0

PCLATH<4:3>

PCH PCL

PCLATH

PCH PCL

PCL as

Destination

Note 1: There are no Status bits to indicate Stack

Overflow or Stack Underflow condit ions.

2: There are no instructions/mnemonics

called PUSH or POP. These are actions

that occur from the execution of the

CALL, RETURN, RETLW and RETFIE

instructions, or the vectoring to an

interr upt add res s.

PIC12F629/675

DS41190F-page 20  2009 Microchip Technology Inc.

2.4 Indirect Addressing, INDF and

FSR Registers

The INDF register is no t a physica l register. Addressing

the INDF register will cause indirect addressing.

Indirect addressing is possible by using the INDF

actually accesses data pointed to by the File Select

produce 00h. Writing to the INDF register indirectly

results in a no operation (although Status bits may be

affected). An effective 9-bit address is obtained by

concatenating the 8-bit FSR register and the IRP bit

(STAT US<7>), as shown in Figu re 2-4.

A simple program to clear RAM location 20h-2Fh using

indirect addressing is shown in Example 2-1.

EXAMPLE 2-1: INDIR ECT ADDRES S ING

FIGURE 2-2: DIRE CT/INDI RECT ADDRESSING PIC12F629/675

MOVLW 0x20 ;initialize pointer

MOVWF FSR ;to RAM

NEXT CLRF INDF ;clear INDF register

INCF FSR ;inc pointer

BTFSS FSR,4 ;all done?

GOTO NEXT ;no clear next

CONTINUE ;yes continue

For memory map detail see Figure 2-2.

Note 1: The RP1 and IRP bits are reserved; always maintain these bits clear.

Data

Memory

Indirect AddressingDirect Addressing

Bank Select Location Select

RP1(1) RP0 6 0

From Opcode IRP(1) FSR Register

Bank Select Location Select

00 01 10 11 180h

1FFh

00h

7Fh

Bank 0 Bank 1 Bank 2 Bank 3

Not Used

 2009 Microchip Technology Inc. DS41190F-page 21

PIC12F629/675

3.0 GPIO PORT

There are as many as six general purpose I/O pins

available. Depending on which peripherals are

enabled , some or all of the pins may not be a vailable as

general purpose I/O. In general, when a peripheral is

enabled, the associated pin may not be used as a

general purpose I/O pin.

3.1 GPIO and the TRISIO Registers

GPIO is an 6-bit wide, bidirectional port. The

corresponding data direction register is TRISIO.

Setting a TRISIO bit (= 1) will make the corresponding

GPIO pin an input (i.e., put the corresponding output

driver in a High-Impedance mode). Clearing a TRISIO

bit (= 0) will make the corresponding GPIO pin an

output (i.e., put the contents of the output latch on the

select ed pin). The exception is GP3, whi ch is input- only

and its TRISIO bit will always read as ‘1’. Example 3-1

shows how to initialize GPIO.

Readi ng the GPIO regis ter reads the st atus of the pins,

whereas writing to it will write to the PORT latch. All

write operations are read-modify-write operations.

Therefore , a write to a port implies that the port pins are

read, this value is modified, and then written to the

PORT data latch. GP3 reads ‘0’ when MC L RE N = 1.

The TRISIO register controls the direction of the

GP pins, even when they are being used as analog

inputs. The user must ensure the bits in the TRISIO

inputs. I/O pins configured as analog inputs always

read ‘0’.

EXAMPLE 3-1: INITIA LI ZING GPIO

3.2 Additional Pin Functions

Every GPIO pin on the PIC12F629/675 has an

interrupt-o n-change option a nd every GPIO pin, except

GP3, has a w eak pu ll-u p op tio n. The next t w o se cti on s

describe these functions.

3.2.1 WEAK PULL-UP

Each of the GPIO pins, ex cept GP3, has an indivi dually

configurable weak internal pull-up. Control bits WPUx

enable or disable each pull-up. Refer to Register 3-3.

Each we ak p ull -up is au tom aticall y turned off wh en th e

port pin is configured as an output. The pull-ups are

disabled on a Power-on Reset by the GPPU bit

(OPTION<7>).

Note: Additional information on I/O ports may be

found in the PIC® Mid-Range Reference

Manual, (DS33023).

Note: The ANSEL (9Fh) and CMCON (19h)

registers (9Fh) must be initialized to

configure an analog channel as a digital

input. Pin s confi gur ed as analo g in put s will

read ‘0’. T he AN SEL reg ist er is de fin ed f or

the PIC12F675.

BCF STATUS,RP0 ;Bank 0

CLRF GPIO ;Init GPIO

MOVLW 07h ;Set GP<2:0> to

MOVWF CMCON ;digital IO

BSF STATUS,RP0 ;Bank 1

CLRF ANSEL ;Digital I/O

MOVLW 0Ch ;Set GP<3:2> as inputs

MOVWF TRISIO ;and set GP<5:4,1:0>

;as outputs

U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

— — GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 GPIO<5:0>: General Purpose I/O pin

1 = Port pin is >VIH

0 = Port pin is <VIL

PIC12F629/675

DS41190F-page 22  2009 Microchip Technology Inc.

U-0 U-0 R/W-1 R/W-1 R-1 R/W-1 R/W-1 R/W-1

— — TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 TRISIO<5:0>: General Purpose I/O Tri-State Control bit

1 = GPIO pin configured as an input (tri-stated)

0 = GPIO pin configured as an output

Note: TRISIO<3> always reads ‘1’.

U-0 U-0 R/W-1 R/W-1 U-0 R/W-1 R/W-1 R/W-1

—— WPU5 WPU4 — WPU2 WPU1 WPU0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’

bit 5-4 WPU<5:4>: Weak Pull-up Register bit

1 = Pull-up enabled

0 = Pull-up disabled

bit 3 Unimplemented: Read as ‘0’

bit 2-0 WPU<2:0>: Weak Pull-up Register bit

1 = Pull-up enabled

0 = Pull-up disabled

Note 1: Global GPPU must be enabled for individual pull-ups to be enabled.

2: The weak pull-up device is automatically disabled if the pin is in Output mode (TRISIO = 0).

 2009 Microchip Technology Inc. DS41190F-page 23

PIC12F629/675

3.2.2 INTERRUPT-ON-CHANGE

Each o f the GP IO pins i s individual ly configu rable as a n

interrupt-on-change pin. Control bits IOC enable or

disable the interrupt function for each pin. Refer to

Power-on Reset.

For enabled interrupt-on-change pins, the values are

comp ared w ith the old value la tched on the last rea d of

GPIO. Th e ‘mismatch’ o utputs of t he last read are OR’d

together to set, the GP Port Change Interrupt flag bit

(GPIF) in the INTCON register.

This interrupt can wake the device from Sleep. The

user, in the Interrupt Service Routine, can clear the

interr upt in the foll owin g man ner:

a) Any read or write of GPIO. This will end the

mismatch condition.

b) Clear the flag bit GPIF.

A mismatch condition will continue to set flag bit GPIF.

Reading GPIO will end the mismatch condition and

allow flag bit GPIF to be cleared.

Note: If a change on the I/O pin should occur

when th e read o peratio n is be ing ex ecute d

(start of the Q 2 cycle), then the GPIF int er-

rupt flag may not get set.

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

—— IOC5 IOC4 IOC3 IOC2 IOC1 IOC0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 IOC<5:0>: Interrupt-on-Change GPIO Control bits

1 = Interrupt-on-change enabled

0 = Interrupt-on-change disabled

Note 1: Global Interrupt Enable (GIE) must be enabled for individual interrupts to be recognized.

PIC12F629/675

DS41190F-page 24  2009 Microchip Technology Inc.

3.3 Pin Descriptions and Diagrams

Each GPIO pin is multiplexed with other functions. The

pins and their c om bi ned functio ns a re briefl y describe d

here. For specific information about individual funct ions

such as the comparator or the A/D, refer to the

appropriate section in this Data Sheet.

3.3.1 GP0/AN0/CIN+

Figure 3-1 shows th e dia gram fo r this pin. T he GP0 pin

is configurable to function as one of the following:

• a general pu rpose I/O

• an analog input for the A/D (PIC12F675 only)

• an analog input to the comparator

3.3.2 GP1/AN1/CIN-/VREF

Figure 3-1 shows th e dia gram fo r this pin. T he GP1 pin

is configurable to function as one of the following:

• as a general purpose I /O

• an analog input for the A/D (PIC12F675 only)

• an analog input to the comparator

• a voltage reference input for the A/D (PIC12F675

only)

FIGURE 3-1: BLOCK DIAGRAM OF GP0

AND GP1 PINS

I/O pin

VDD

VSS

VDD

Weak

Data Bus

WPU

RD PORT

PORT

TRISIO

IOC

Interrupt-on-Change

To C om parato r

To A/D Converter

Analog

Input Mode

GPPU

Analog

Input Mode

 2009 Microchip Technology Inc. DS41190F-page 25

PIC12F629/675

3.3.3 GP2/AN2/T0CKI/INT/COUT

Figure 3-2 shows th e dia gram fo r this pin. T he GP2 pin

is configurable to function as one of the following:

• a general pu rpose I/O

• an analog input for the A/D (PIC12F675 only)

• the clock inp ut for TMR0

• an external edge triggered interrupt

• a digital output from the comparator

FIGURE 3-2: BLOCK DIAGRAM OF GP2

3.3.4 GP3/MCLR/VPP

Figur e 3-3 show s th e diag ram for th is pin . T he GP3 pin

is configurable to function as one of the following:

• a general purpo se inp ut

• as Ma ster Clear Reset

FIGURE 3-3: BLOCK DIAGRAM OF GP3

I/O pin

VDD

VSS

VDD

Weak

Analog

Input Mode

Data Bus

WPU

PORT

TRISIO

IOC

Interrupt-on-Change

To A/D Converter

COUT

Enable

To INT

To TMR0

Analog

Input Mode

GPPU

RD PORT

Analog

Input

Mode

I/O pin

VSS

Data Bus

RD PORT

PORT

IOC

Interrupt-on-Change

Reset MCLRE

TRISIO VSS

MCLRE

PIC12F629/675

DS41190F-page 26  2009 Microchip Technology Inc.

3.3.5 GP4/AN3/T1G/OSC2/CLKOUT

Figure 3-4 shows th e dia gram fo r this pin. T he GP4 pin

is configurable to function as one of the following:

• a general pu rpose I/O

• an analog input for the A/D (PIC12F675 only)

• a TMR1 gate input

• a crystal/resonator connection

• a clock output

FIGURE 3-4: BLOCK DIAGRAM OF GP4

3.3.6 GP5/T1CKI/OSC1/CLKIN

Figur e 3-5 show s th e diag ram for th is pin . T he GP5 pin

is configurable to function as one of the following:

• a general purpo se I/O

•a TMR1 clock input

• a cryst al/ resonator con nec tio n

• a cloc k inpu t

FIGURE 3-5: BLOCK DIAGRAM OF GP5

I/O pin

VDD

VSS

VDD

Weak

Analog

Input Mode

Data Bus

WPU

PORT

TRISIO

IOC

Interrupt-on-Change

FOSC/4

To A/D Converter

Oscillator

Circuit

OSC1

CLKOUT

Enable

Analog

Input Mode

GPPU

RD PORT

To TMR1 T1G

INTOSC/

RC/EC

(2)

CLK

Modes(1)

CLKOUT

Enable

Note 1: CLK modes are XT, HS, LP, LPTMR1 and CLKOUT

Enable.

2: With CLKOUT option .

I/O pin

VDD

VSS

VDD

Weak

Data Bus

WPU

PORT

TRISIO

IOC

Interrupt-on-Change

To TMR1 or CLKGEN

INTOSC

Mode

RD PORT

INTOSC

Mode

GPPU

Oscillator

Circuit

OSC2

Note 1: Timer1 LP Oscillator enabled

2: When using Timer1 with LP oscillator, the Schmitt

Trigger is by-passed.

(2)

TMR1LPEN(1)

 2009 Microchip Technology Inc. DS41190F-page 27

PIC12F629/675

TABLE 3-2: SUMMARY OF REGISTERS ASSOCIATED WITH GPIO

Add r e s s N a m e Bit 7 Bit 6 B it 5 Bit 4 Bit 3 B it 2 Bit 1 Bit 0 Value on

POR,

BOD

V alue on all

other

Resets

05h GPIO —— GP5 GP4 GP3 GP2 GP1 GP0 --xx xxxx --uu uuuu

0Bh/8Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 000u

19h CMCON —COUT —CINV CIS CM2 CM1 CM0 -0-0 0000 -0-0 0000

81h OPTION_REG GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

85h TRISIO —— TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111

95h WPU —— WPU5 WPU4 — WPU2 WPU1 WPU0 --11 -111 --11 -111

96h IOC —— IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 --00 0000 --00 0000

9Fh ANSEL —ADCS2 ADCS1 ADCS0ANS3ANS2ANS1ANS0-000 1111 -000 1111

Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by GPIO.

PIC12F629/675

DS41190F-page 28  2009 Microchip Technology Inc.

NOTES:

 2009 Microchip Technology Inc. DS41190F-page 29

PIC12F629/675

4.0 TIMER0 MODULE

The Timer0 module timer/counter has the following

features:

• 8-bit timer/counter

• Readable and writable

• 8-bit software programmable prescaler

• Internal or external clock select

• Interrupt on overflow from FFh to 00h

• Edge select for external clock

Figure 4-1 is a bl ock diagram of the T imer0 m odule and

the prescaler shared with the WDT.

4.1 Timer0 Operation

Timer mode is selected by clearing the T0CS bit

(OPTION_REG<5>). In Timer mode, the Timer0

module will increment every instruction cycle (without

prescal er). If TMR0 is written , the incre ment is inhibite d

for the following two instruction cycles. The user can

work around this by writing an adjusted value to the

TMR0 register.

Counter mode is selected by setting the T0CS bit

(OPTION_REG<5>). In this mode, the Timer0 module

will increment either on every rising or falling edge of

pin GP2/T0CKI. The incrementing edge is determined

by the source edge (T0SE) control bit

(OPTION_REG<4 >). Clea ring the T0SE bit se lects the

rising edge.

4.2 Timer0 Interrupt

A Timer0 interrupt is generated when the TMR0

overflow set s the T0IF bit. The inte rrupt can be maske d

by clearing the T0IE bit (INTCON<5>). The T0IF bit

(INTCON<2>) must be cleared in software by the

Timer0 module Interrupt Service Routine before re-

enabling this interrupt. The Timer0 interrupt cannot

wake the processor from Sleep since the timer is shut-

off during Sleep.

FIGURE 4-1: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER

Note: Additional information on the Timer0

module is availabl e i n the PIC® Mid - Range

Reference Manual, (DS33023).

Note: Counter mode has specific external clock

requirements. Additional information on

these requ irement s is availab le in the PIC®

Mid-Range Reference Manual,

(DS33023).

T0CKI

T0SE

CLKOUT

TMR0

Watchdog

Timer

WDT

Time-out

PS0 - PS2

WDTE

Data Bus

Set Flag bit T0IF

on Overflow

T0CS

Note 1: T 0SE , T0CS, PSA, PS 0-PS 2 are bits in the OPTION register.

SYNC 2

Cycles

8-bit

Prescaler

(= FOSC/4)

PSA

PIC12F629/675

DS41190F-page 30  2009 Microchip Technology Inc.

4.3 Using Timer0 with an External

Clock

When no pr escal er is used, t he ex ternal clo ck inp ut is

the same as the pre sc al er outp ut. Th e sy nch ron iz atio n

of T0CKI, with the internal phase clocks, is accom-

plishe d by sampling the prescale r output on the Q2 and

Q4 cycles of the internal phase clocks. Therefore, it is

necessary for T0CKI to be high for at least 2TOSC (and

a small RC delay of 20 ns) and low for at least 2TOSC

(and a small RC delay of 20 ns). Refer to the electrical

specification of the desired device.

Note: The ANSEL (9Fh) and CMCON (19h)

registers must b e initia lized to configure a n

analog channel as a digital input. Pins

configured as analog inputs will read ‘0’.

The ANSEL register is defined for the

PIC12F675.

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 GPPU: GPIO Pull-up Enable bit

1 = GPIO pull-ups are disabled

0 = GPIO pull-ups are enabled by individual PORT latch values

bit 6 INTEDG: Interrupt Edge Select bit

1 = Interrupt on rising edge of GP2/INT pin

0 = Interrupt on falling edge of GP2/INT pin

bit 5 T0CS: TMR0 Clock Source Select bit

1 = Transition on GP2/T 0CK pin

0 = Internal instruction cycle clock (CLKOUT)

bit 4 T0SE: TMR0 Source Edge Select bit

1 = Increment on high-to-low transition on GP2/T0CKI pin

0 = Increment on low-to-high transition on GP2/T0CKI pin

bit 3 PSA: Prescaler Assig nm ent bit

1 = Prescaler is assigned to the WDT

0 = Prescaler is assigned to the TIMER0 module

bit 2-0 PS2:PS0: Prescaler Rate Select bit s

000

001

010

011

100

101

110

111

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

1 : 1

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

Bit Value TMR0 Rate WDT Rate

 2009 Microchip Technology Inc. DS41190F-page 31

PIC12F629/675

4.4 Prescaler

An 8-bit counter is available as a prescaler for the

Timer0 module, or as a postscaler for the Watchdog

Timer. For simplicity, this counter will be referred to as

“prescaler” throughout this Data Sheet. The prescaler

assignment is controlled in software by the control bit

PSA (OPTION_REG<3>). Clearing the PSA bit will

assign the prescaler to Timer0. Prescale values are

select able vi a the PS2:PS0 bit s (OPTIO N_REG<2:0> ).

The prescaler is not readable or writable. When

assigned to the Timer0 module, all instructions writing

to the TMR0 register (e.g., CLRF 1, MOVWF 1,

BSF 1, x....etc.) will clear the prescaler. When

assigned to WDT, a CLRWDT instruction will clear the

prescaler along with the Watchdog Timer.

4.4.1 SWITCHING PRESCALE R

ASSIGNMENT

The prescaler assignment is fully under software

control (i.e., it can be changed “on the fly” during

program execution). To avoid an unintended device

Reset, the following instruction sequence (Example 4-

1) must be executed when changing the prescaler

assignment from Timer0 to WDT.

EXAMPLE 4-1: CHANGIN G PRESCA LER

(TIMER0WDT)

To change prescaler from the WDT to the TMR0

module , use the se quence sh own in Exa mple 4-2. This

preca ution mus t be tak en even if the WDT is dis abled.

EXAMPLE 4-2: CHANGIN G PRESCA LER

(WDTTIMER0)

TABLE 4-1: REGISTERS ASSOCIATED WITH TIMER0

BCF STATUS,RP0 ;Bank 0

CLRWDT ;Clear WDT

CLRF TMR0 ;Clear TMR0 and

; prescaler

BSF STATUS,RP0 ;Bank 1

MOVLW b’00101111’ ;Required if desired

MOVWF OPTION_REG ; PS2:PS0 is

CLRWDT ; 000 or 001

;

MOVLW b’00101xxx’ ;Set postscaler to

MOVWF OPTION_REG ; desired WDT rate

BCF STATUS,RP0 ;Bank 0

CLRWDT ;Clear WDT and

; postscaler

BSF STATUS,RP0 ;Bank 1

MOVLW b’xxxx0xxx’ ;Select TMR0,

; prescale, and

; clock source

MOVWF OPTION_REG ;

BCF STATUS,RP0 ;Bank 0

Address Name Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Value on

POR, BOD

Value on

all other

Resets

01h TMR0 Timer0 Module Regi st er xxxx xxxx uuuu uuuu

0Bh/8Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 000u

81h OPTION_REG GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

85h TRISIO — — TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111

Legend: — = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown.

Shaded cells are not used by the Timer0 module.

PIC12F629/675

DS41190F-page 32  2009 Microchip Technology Inc.

5.0 TIMER1 MODULE WITH GATE

CONTROL

The PIC12F629/675 devices have a 16-bit timer.

Figure 5-1 shows th e basic block diagram of the T imer1

module. Timer1 has the following features:

• 16-bit timer/counter (TMR1H:TMR1L)

• Readable and writable

• Internal or external clock selection

• Synchronous or asynchronous operation

• Interrupt on overflow from FFFFh to 0000h

• Wake-up upon overflow (Asynchronous mode)

• Optional external enable input (T1G)

• Op tional LP oscillator

The Timer1 Control register (T1CON), shown in

select the various features of the Timer1 module.

FIGURE 5-1: TIME R1 BLOCK DIAGRAM

Note: Additional information on timer modules is

available in the PIC® Mid-Range Refer-

ence Manual, (DS33023).

TMR1H TMR1L

LP Oscillator T1SYNC

TMR1CS

T1CKPS<1:0> Sleep Input

FOSC/4

Internal

Clock

Prescaler

1, 2, 4, 8

Synchronize

Detect

Synchronized

Clock Input

OSC1

OSC2

Set Flag bit

TMR1IF on

Overflow

TMR1

TMR1ON

TMR1GE

TMR1ON

TMR1GE

INTOSC

T1OSCEN

w/o CLKOUT

T1G

 2009 Microchip Technology Inc. DS41190F-page 33

PIC12F629/675

5.1 Timer1 Modes of Operation

Timer1 can operate in one of three modes:

• 16-bit timer with prescaler

• 16-bit synchronous counter

• 16-bit asynchronous counter

In Timer mode, Timer1 is incremented on every

instruction cycle. In Counter mode, Timer1 is

incremented on the rising edge of the external clock

input T 1CKI . In ad dit io n, the C ou nter mo de c loc k can

be synchronized to the microcontroller system clock

or run asynchronou s ly.

In counter and timer modules, the counter/timer clock

can be gated by the T1G input.

If an external clock oscillator is needed (and the

microcontroller is using the INTOSC w/o CLKOUT),

Timer1 can use the LP oscillator as a clock source.

5.2 Timer1 Interrupt

The Timer1 register pair (TMR1H:TMR1L) increments

to FFFFh and rolls over to 0000h. When Timer1 rolls

over, the Timer1 interrupt flag bit (PIR1<0>) is set. To

enable the inter rupt on rollo ver , you m ust set th ese bits :

• Timer 1 interru pt Enab le bit (PIE1< 0>)

• PEIE bit (INTCON<6>)

• GIE bit (INTCON<7>).

The interrupt is cleared by clearing the TMR1IF in the

Interrupt Service Routine.

5.3 Timer1 Prescaler

Timer1 ha s four prescaler options allowing 1, 2, 4, or 8

divisions of the clock input. The T1CKPS bits

(T1CON<5:4>) control the prescale counter. The

prescale counter is not directly readable or writable;

however, the prescaler counter is cleared upon a write

to TMR1H or TMR1L.

FIGURE 5-2: TIMER1 INCREMENTING EDGE

Note: In Counter mode, a falling edge must be

registered by the counter prior to the first

incr em enti ng ris ing edge.

Note: The T MR1H:TTMR 1L regi st er pair and the

TMR1IF bit should be cleared before

enabling interrupts.

T1CKI = 1

when TMR1

Enabled

T1CKI = 0

when TMR1

Enabled

Note 1: Ar rows indicate counter in crem ents.

2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the

clock.

PIC12F629/675

DS41190F-page 34  2009 Microchip Technology Inc.

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

—TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’

bit 6 TMR1GE: Timer1 Gate Enable bit

If TMR1ON = 0:

This bit is ignored

If TMR1ON = 1:

1 = Timer1 is on if T1G pin is low

0 = Timer1 is on

bit 5-4 T1CKPS1:T1CKPS0: Ti mer1 Input Clock P rescale Select bits

11 = 1:8 P rescale Value

10 = 1:4 P rescale Value

01 = 1:2 P rescale Value

00 = 1:1 P rescale Value

bit 3 T1OSCEN: LP Oscillator Enable Control bit

If INTOSC without CL KOUT osci lla tor is active:

1 = LP oscillator is enabled for Timer1 clock

0 = LP oscillator is off

Else:

This bit is ignored

bit 2 T1SYNC: Timer1 External Clock Input Synchronization Control bit

TMR1CS = 1:

1 = Do not synchronize external clock input

0 = Synchronize external clock input

TMR1CS = 0:

This bit is ignored. Timer1 uses the internal clock.

bit 1 TMR1CS: Timer1 Clock Source Select bit

1 = External clock from T1OSO/T1CKI pin (on the rising edge)

0 = Internal clock (FOSC/4)

bit 0 TMR1ON: Timer1 On bit

1 = Enables Ti mer1

0 = Stops Timer1

 2009 Microchip Technology Inc. DS41190F-page 35

PIC12F629/675

5.4 Timer1 Operation in

Asynchronous Counter Mode

If control bit T1SYNC (T1CON<2>) is set, the external

clock input is not synchronized. The timer continues to

increment asynchronous to the internal phase clocks.

The timer will continue to run during Sleep and can

generate an interrupt on overflow, which will wake-up

the processor. However, special precautions in

software are needed to read/write the timer

(Section 5.4.1 “Reading and writing Timer1 in asyn-

chronous counter mode”).

5.4.1 READING AND WRITING TIMER1 IN

ASYNCHRONOUS COUNTER MODE

Reading TMR1H or TMR1L, while the timer is running

from an external asynchronous clock, will ensure a

valid read (taken care of in hardware). However, the

user shoul d keep i n mind that r eadi ng the 16-bit time r

in two 8-b it va lu es i tself, po ses cert a in problem s, s inc e

the timer may overflow between the reads.

For write s, it is re comm ended that the us er simply stop

the timer and write the desired values. A write

contention may occur by writing to the timer registers,

while the register is incrementing. This may pro duce an

unpredictable value i n the timer register.

Reading the 16-bit value requires some care.

Examples 12-2 and 12-3 in the PIC® Mid-Range MCU

Family Reference Manual (DS33023) show how to

read and write Timer1 when it is running in

Asynchronous mode.

5.5 Timer1 Oscillator

A cryst al osci llator circ uit is built-in between pins OSC1

(input) and OSC2 (amplifier output). It is enabled by

setting control bit T1OSCEN (T1CON<3>). The

oscill ator is a low -power osc illator rate d up to 37 kH z. It

will co ntinue to run durin g Sleep. It is primarily intende d

for a 32 kHz crystal. Table 9-2 shows the capacitor

select ion for the T im er1 osc il lat or.

The Timer1 oscillator is shared with the system LP

oscillator. Thus, Timer1 can use this mode only when

the system clock is derived from the internal oscillator.

As with the syste m LP oscil lator, the user mu st provide

a software time delay to ensure proper oscillator

start-up.

While enabled, TRISIO4 and TRISIO5 are set. GP4

and GP5 read ‘0’ and TRISIO4 and TRISIO5 are read

‘1’.

5.6 Timer1 Operation During Sleep

Timer1 can only operate during Sleep when setup in

Asynch ronous Counter mode. In this mod e, an external

crystal or clock source can be used to increment the

counter. To setup the timer to wake the device:

• Timer1 must be on (T1CON<0>)

• TMR1IE bit (PIE1<0>) must be set

• PEIE bit (INTCON<6> ) must be set

The device will wake-up on an overflow. If the GIE bit

(INTCON< 7 >) is se t, the de vi ce wil l wa ke -up an d jum p

to the Interrupt Service Routine on an overflow.

TABLE 5-1: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER

Note: The ANSEL (9Fh) and CMCON (19h)

registers must be initia lized to configu re an

analog channel as a digital input. Pins

configured as analog inputs will read ‘0’.

The ANSEL register is defined for the

PIC12F675.

Note: The oscilla tor requi res a s tart-up and s tabi-

lization time before use. Thus, T1OSCEN

should be set and a suitable delay

observed prior to enabling Timer1.

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOD

Value on

all other

Resets

0Bh/8Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 000u

0Ch PIR1 EEIF ADIF — — CMIF ——TMR1IF00-- 0--0 00-- 0--0

0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu

0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu

10h T1CON — TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON -000 0000 -uuu uuuu

8Ch PIE1 EEIE ADIE — — CMIE ——TMR1IE00-- 0--0 00-- 0--0

Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.

PIC12F629/675

DS41190F-page 36  2009 Microchip Technology Inc.

NOTES:

 2009 Microchip Technology Inc. DS41190F-page 37

PIC12F629/675

6.0 COMPARATOR MODULE

The PIC12F629/675 devices have one analog

comparator. The inputs to the comparator are

multiplexed with t he GP0 and GP1 pins. There is an

on-chip Comparator V oltage Reference that can also

be applied to an input of the comparator. In addition ,

GP2 can be configured as the comparator output.

The Comparator Control Regi ster (CMCON), shown

in Register 6-1, contains the bits to control the

comparator.

U-0 R-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

—COUT— CINV CIS CM2 CM1 CM0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’

bit 6 COUT: Comparator Output bit

When CINV = 0:

1 = VIN+ > VIN-

0 = VIN+ < VIN-

When CINV = 1:

1 = VIN+ < VIN-

0 = VIN+ > VIN-

bit 5 Unimplemented: Read as ‘0’

bit 4 CINV: Comparator Output Inversion bit

1 = Output inverted

0 = Output not inverted

bit 3 CIS: Comparator Input Switch bit

When CM2:CM0 = 110 or 101:

1 = VIN- connects to CIN+

0 = VIN- connects to CIN-

bit 2-0 CM2:CM0: Comparator Mode bits

Figure 6-2 shows the Comparator modes and CM2:CM0 bit settings

PIC12F629/675

DS41190F-page 38  2009 Microchip Technology Inc.

6.1 Comparator Operation

A single comparator is shown in Figure 6-1, along with

the relationship between the analog input levels and

the digit al ou tput. When the an alog input a t VIN+ is less

than the analog input VIN-, the o utput of the co mparator

is a digital low level. When the analog input at VIN+ is

greater than the analog input VIN-, the output of the

comparator is a digital high level. The shaded areas of

the output of the comparator in Figure 6-1 represent

the uncertainty due to input offsets and response time.

The polarity of the comparator output can be inverted

by setting the CINV bit (CMCON<4>). Clearing CINV

results in a non-inverted output. A complete table

showing the output state versus input conditions and

the polarity bit is shown in Table 6-1.

TABLE 6-1: OUTPUT STATE VS. INPUT

CONDITIONS

FIGURE 6-1: SINGLE COMP ARATOR

Note: To use CIN+ and CIN- pins as analog

inputs, the appropriate bits must be

programmed in the CMCON (19h) register.

Input Conditions CINV COUT

VIN- > VIN+00

VIN- < VIN+01

VIN- > VIN+11

VIN- < VIN+10

Output

VIN-

VIN+

Output

–

VIN+

VIN-

Note: CINV bit (CMCON<4>) is clear.

 2009 Microchip Technology Inc. DS41190F-page 39

PIC12F629/675

6.2 Comparator Configuration

There are eigh t mod es of operat ion fo r the comp arato r.

The CMCO N regi ster , shown in Reg ister 6-1, is used to

select the mode. Figure 6-2 shows the eight possible

modes. The TRISIO register controls the data direction

of the comparator pins for each mode. If the

Comparator mode is changed, the comparator output

level may not be valid for a specified period of time.

Refer to the specifications in Section 12.0 “Electri-

cal Specifications”.

FIGURE 6-2: COMPARATOR I/O OPERATING MODES

Note: Comparator interrupts should be disabled

during a C omp arator mode change. O ther-

wise, a false interrupt may occur.

Comparator Reset (POR Default Value - low power) Comparator Off (Lowest power)

CM2:CM0 = 000 CM2:CM0 = 111

Comparator without Output Comparator w/o Output and with Internal Reference

CM2:CM0 = 010 CM2:CM0 = 100

Comparator with Output and Internal Reference Multiplexed Input with Internal Reference and Output

CM2:CM0 = 011 CM2:CM0 = 101

Comparator with Output Multiplexed Input with Internal Reference

CM2:CM0 = 001 CM2:CM0 = 110

A = Analog Input, ports always reads ‘0’

D = Digital Input

CIS = Comparator Input Switch (CMCON<3>)

GP1/CIN-

GP0/CIN+ Off (Read as ‘0’)

GP2/COUT D

GP1/CIN-

GP0/CIN+ Off (Read as ‘0’)

GP2/COUT D

GP1/CIN-

GP0/CIN+ COUT

GP2/COUT D

GP1/CIN-

GP0/CIN+ COUT

GP2/COUT D From CVREF Module

GP1/CIN-

GP0/CIN+ COUT

GP2/COUT D

From CV REF Module

GP1/CIN-

GP0/CIN+ COUT

GP2/COUT D

From CVREF Module

CIS = 0

CIS = 1

GP1/CIN-

GP0/CIN+ COUT

GP2/COUT D

GP1/CIN-

GP0/CIN+ COUT

GP2/COUT D

From CVREF Module

CIS = 0

CIS = 1

PIC12F629/675

DS41190F-page 40  2009 Microchip Technology Inc.

6.3 Analog Input Connection

Considerations

A simplified circuit for an analog input is shown in

Figure 6-3. Since the analog pins are connected to a

digital output, they have reverse biased diodes to VDD

and VSS. Th e analog input, th erefore, must be betwee n

VSS and VDD. If the input voltage deviates from this

range by more than 0.6V in either direction, one of the

diodes is forward biased and a latch-up may occur. A

maximum source impedance of 10 k is

recommended for the analog sources. Any external

component connected to an analog input pin, such as

a capacitor or a Zener diode, should have very little

leakage current.

FIGURE 6-3: ANALOG INPUT MODE

6.4 Comparator Output

The comparator output, COUT, is read through the

CMCON reg is ter. This bit is read-on ly. The comparator

output may also be directly output to the GP2 pin in

three of the eight possible modes, as shown in

Figure 6-2. When in one of thes e modes , the ou tput on

GP2 is asynchronous to the internal clock. Figure 6-4

shows the comparator output block diagram.

The TRISIO<2> bit functions as an output enable/

disable for the GP2 pin while the comparator is in an

Output mode.

FIGURE 6-4: MODIFIE D COMPARATOR OUTPUT BLOCK DIAGRAM

Rs < 10K

AIN CPIN

5 pF

VDD

VT = 0.6V

RIC

Leakage

±500 nA

Vss

Legend: CPIN = Input Capacitance

VT= Threshold Voltage

ILEAKAGE = Leakage Current at the pin due to Various Junctions

RIC = Interconnect Resistance

RS= Source Impedance

VA = Analog Voltage

Note 1: When reading the GPIO register, all pins

configured as analog inputs will read as a

‘0’. Pins configured as digital inputs will

convert an analog input according to the

TTL input specification.

2: Analog le vels on any pin that is defined as

a digital inpu t, may caus e the input bu f f er

to consume more current than is

specified.

To GP2/T0CK I pin

RD CMCON

Set CMIF bit

Reset

To Data Bus

CINV

CVREF

RD CMCON

GP1/CIN-

GP0/CIN+

CM2:CM0

 2009 Microchip Technology Inc. DS41190F-page 41

PIC12F629/675

6.5 Comparator Reference

The com par ato r m od ule also allows the selection of an

internally generated voltage reference for one of the

comparator inputs. The internal reference signal is

used for four of the eight Comparator modes. The

VRCON register, Register 6-2, controls the voltage

reference module shown in Figure 6-5.

6.5.1 CONFIGURING THE VOLTAGE

REFERENCE

The voltage reference can output 32 distinct voltage

levels, 16 in a high range and 16 in a low range.

The follow ing equati ons determi ne the output vo ltages :

6.5.2 VOLTAGE REFERENCE

ACCURACY/ERROR

The full range of VSS to VDD cannot be rea liz ed due to

the construction of the module. The transistors on the

top and bottom of the resistor ladder network

(Figure 6-5) keep CVREF from approaching VSS or

VDD. The V olt age Re ference is VDD derived and there-

fore, the CVREF output changes with fluctuations in

VDD. The tested absolute accuracy of the Comparator

Voltage Reference can be found in Section 12.0

“Electrical Specifications”.

FIGURE 6-5: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM

6.6 Comparator Response Time

Response time is the minimum time, after selecting a

new reference voltage or input source, before the

comparator output is ensured to have a valid level. If

the internal reference is changed, the maximum delay

of the internal voltage reference must be considered

when using the comparator outputs. Otherwise, the

maximum delay of the comparators should be used

(Table 12-7).

6.7 Operation During Sleep

Both the comparator and voltage reference, if enabled

before entering Sleep mode, remain active during

Sleep. Thi s results in highe r Sleep currents than shown

in the power-down specifications. The additional cur-

rent consumed by the comparator and the voltage ref-

erence is shown separately in the specifications. To

minim ize power cons umption whil e in Sleep mode, tu rn

off the comparator , CM2:CM0 = 111, and volta ge refer-

ence, VRCON<7> = 0.

While the comparat or is enabled d uring Sleep, an inter-

rupt will wake-up the device. If the device wakes up

from Sleep, the contents of the CMCON and VRCON

registers are not affected.

6.8 Effects of a Reset

A device Reset forces the CMCON and VRCON

registers to their Reset states. This forces the

comparator module to be in the Comparator Reset

mode, CM2:CM0 = 000 and the volt age reference to it s

off state. Thus, all potential inputs are analog inputs

with the comparator and voltage reference disabled to

consume the smallest current possible.

VRR = 1 (low range): CVREF = (VR3:VR0 / 24) x VDD

VRR = 0 (high range): CVREF = (VDD / 4) + (VR3:VR0 x

VDD / 32)

VRR

VR3:VR0

16-1 Analog

8RRR RR

CVREF to

16 Stages

Comparator

Input

VREN

VDD

MUX

PIC12F629/675

DS41190F-page 42  2009 Microchip Technology Inc.

6.9 Comparator Interrupts

The comparator interrupt flag is set whenever there is

a change in the output value of the comparator.

Software will need to maintain information about the

status of the output bits, as read from CMCON<6>, to

determine the actual change that has occurred. The

CMIF bit, PIR1<3>, is the comparator interrupt flag.

This bit must be reset in software by clearing it to ‘0’.

Since it is also possible to write a ‘1’ to this register, a

simulated interrupt may be initiated.

The CMIE bit (PIE1<3>) and the PEIE bit (INT-

CON<6>) must be set to enable the interrupt. In addi-

tion, the GIE bit must also be set. If any o f these bits are

clear ed, t he int erru pt is no t ena bled, thoug h the CMIF

bit will still be set if an interrupt condition occurs.

The user , in the Interrupt Service Routine, can clear the

interrupt in the following man ner:

a) Any read or write of CMCON. This will end the

mismatch condition.

b) Clear flag bit CMIF.

A mismatc h co ndi tio n will co nti nue to set fla g bit CMIF.

Readi ng C M CO N will end the mi sm atc h c ondit ion , an d

allow flag bit CMIF to be cleared.

TABLE 6-2: REGISTERS ASSOCIATED WITH COMPARATOR MODULE

R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

VREN —VRR—VR3VR2VR1VR0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 VREN: CVREF Enable bit

1 = CVREF circuit powered on

0 = CVREF circuit powered down, no IDD drain

bit 6 Unimplemented: Read as ‘0’

bit 5 VRR: CVREF Range Selection bit

1 = Low range

0 = High range

bit 4 Unimplemented: Read as ‘0’

bit 3-0 VR3:VR0: CVREF value selection 0  VR [3:0]  15

When VRR = 1: CVREF = (VR3:VR0 / 24) * VDD

When VRR = 0: CVREF = VDD/4 + (VR3:VR0 / 32) * VDD

Note: If a change in the CMCON register (COUT)

should occur when a read operation is

being exe cuted (start of the Q2 cycle), then

the CMIF (PIR1<3>) interrupt flag may not

get set.

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOD

Value on

all other

Resets

0Bh/8Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 000u

0Ch PIR1 EEIF ADIF ——CMIF— — TMR1IF 00-- 0--0 00-- 0--0

19h CMCON —COUT— CINV CIS CM2 CM1 CM0 -0-0 0000 -0-0 0000

8Ch PIE1 EEIE ADIE ——CMIE— — TMR1IE 00-- 0--0 00-- 0--0

85h TRISIO — — TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111

99h VRCON VREN —VRR— VR3 VR2 VR1 VR0 0-0- 0000 0-0- 0000

Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by th e compara tor module.

 2009 Microchip Technology Inc. DS41190F-page 43

PIC12F629/675

7.0 ANALOG-TO-DIGITAL

CONVERTER (A/D) MODULE

(PIC12F675 ONLY)

The Analog-to-Digital converter (A/D) allows

conversion of an analog input signal to a 10-bit binary

representation of that signal. The PIC12F675 has four

analog inputs, multiplexed into one sample and hold

circuit . The outp ut of the sample and hol d is co nne cted

to the in put of the converte r . Th e converter generat es a

binary result via successive approximation and stores

the result in a 10-bit register. The voltage reference

used in the conversion is software selectable to either

VDD or a voltage applied by the VREF pin. Figure 7-1

shows th e block diagram o f the A/D on the PIC12 F675.

FIGURE 7-1: A/D BLOCK DIAGRAM

7.1 A/D Configuration and Operation

There are two registers available to control the

functionality of the A/D module:

1. ADCON0 (Register 7 -1)

2. ANSEL (Register 7-2)

7.1.1 ANALOG PORT PINS

The ANS3:ANS0 bits (ANSEL<3:0>) and the TRISIO

bits control the operation of the A/D port pins. Set the

corresponding TRISIO bits to set the pin output driver

to its high-impedance state. Likewise, set the

corresponding ANS bit to disable the digital input

buffer.

7.1.2 CHANNEL SELECTION

There are four analog channels on the PIC12F675,

AN0 through AN3. The CHS1:CHS0 bits

(ADCON0<3 :2>) control w hich channel is co nnected to

the sample and hold circuit.

7.1.3 VOLTAGE REFERENCE

There are two options for the voltage reference to the

A/D converte r: either VDD is used, or an an alog volt age

applied to VREF is used. The VCFG bit (ADCON0<6>)

controls the volta ge reference s election. If VCFG is set,

then the voltage on the VREF pin is the reference;

otherwise, VDD is the reference.

7.1.4 CONVERSION CLOCK

The A/D conversion cycle requires 11 TAD. The source

of the conversion clock is software selectable via the

ADCS bits (ANSEL<6:4>). There are seven possible

clock options:

•F

OSC/2

•F

OSC/4

•F

OSC/8

•F

OSC/16

•F

OSC/32

•F

OSC/64

•F

RC (dedicated internal RC oscillator)

For correct conversion, the A/D conversion clock

(1/TAD) must be se lected to ensure a mi nimum TAD of

1.6 s. Table 7-1 shows a few TAD calculations for

selected frequencies.

GP0/AN0

ADC

GP1/AN1/VREF

GP2/AN2

GP4/AN3

VDD

VREF

ADON

GO/DONE

VCFG = 1

VCFG = 0

CHS1:CHS0

ADRESH ADRESL

ADFM

VSS

Note: Analog voltages on any pin that is defined

as a digital input may cause the input

buffer to conduct excess current.

PIC12F629/675

DS41190F-page 44  2009 Microchip Technology Inc.

TABLE 7-1: TAD vs. DEVICE OPERATING FREQUENCIES

7.1.5 STARTING A CONVERSION

The A/D conversion is initiated by setting the

GO/DONE bi t ( ADCO N0< 1>). Wh en t he c onv ers ion is

complete, the A/D module:

• Clears the GO/DONE bit

• Sets the ADIF flag (PIR1<6 >)

• Generates an interrupt (if enabled)

If the conversion must be aborted, the GO/DONE bit

can be cleared in software. The ADRESH:ADRESL

A/D conversion sample. Instead, the

ADRESH:ADRESL registers wi ll re t ain th e va lue of th e

previous conversion. After an aborted conversion, a

AD delay is required before another acquisition can

be initiated. Following the delay, an input acquisition is

automatically started on the selected channel.

7.1.6 CONVERSION OUTPUT

The A/D conversion can be supplied in two formats: left

or right shifted. The ADFM bit (ADCON0<7>) controls

the outpu t format. Figure 7-2 shows the ou tput formats .

FIGURE 7-2: 10-BIT A/D RESULT FORMAT

A/D Clock Source (TAD) Device Frequ ency

Operation ADCS2:ADCS0 20 MHz 5 MHz 4 MHz 1.25 MHz

2 TOSC 000 100 ns(2) 400 ns(2) 500 ns(2) 1.6 s

4 TOSC 100 200 ns(2) 800 ns(2) 1.0 s(2) 3.2 s

8 TOSC 001 400 ns(2) 1.6 s2.0 s6.4 s

16 TOSC 101 800 ns(2) 3.2 s4.0 s12.8 s(3)

32 TOSC 010 1.6 s6.4 s8.0 s(3) 25.6 s(3)

64 TOSC 110 3.2 s12.8 s(3) 16.0 s(3) 51.2 s(3)

A/D RC x11 2 - 6 s(1,4) 2 - 6 s(1,4) 2 - 6 s(1,4) 2 - 6 s(1,4)

Legend:Shaded cells are outside of recommended range.

Note 1: The A/D RC source has a typical TAD time of 4 s for VDD > 3.0V.

2: These values violate the minimum required TAD time.

3: For faster conversion times, the selection of another clock source is recommended.

4: When the device frequency is greater than 1 MHz, the A/D RC clock source is only recommended if the

conversion will be perf ormed during S leep.

Note: The GO/DONE bit should not be set in the

same instruction that turns on the A/D.

ADRESH ADRESL

(ADFM = 0)MSB LSB

Bit 7 Bit 0 Bit 7 Bit 0

10-bit A/D Result Unimplemented: Read as ‘0’

(ADFM = 1)MSB LSB

Bit 7 Bit 0 Bit 7 Bit 0

Unimplemented: Read as ‘0’10-bit A/D Re sult

 2009 Microchip Technology Inc. DS41190F-page 45

PIC12F629/675

R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

ADFM VCFG —— CHS1 CHS0 GO/DONE ADON

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 ADFM: A/D Result Formed Select bit

1 = Right justified

0 = Left justified

bit 6 VCFG: Voltage Reference bit

1 = VREF pin

0 = VDD

bit 5-4 Unimplemented: Read as ‘0’

bit 3-2 CHS1:CHS0: Analog Channel Select bits

00 = Channel 00 (AN0)

01 = Channel 01 (AN1)

10 = Channel 02 (AN2)

11 = Channel 03 (AN3)

bit 1 GO/DONE: A/D Conversion Status bit

1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle.

This bit is automatically cleared by hardware when the A/D conversion has completed.

0 = A/D conversion c ompleted/not in progress

bit 0 ADON: A/D Conversion Status bit

1 = A/D converter module is operating

0 = A/D converter is shut-off and consumes no operating current

PIC12F629/675

DS41190F-page 46  2009 Microchip Technology Inc.

U-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1

— ADCS2 ADCS1 ADCS0 ANS3 ANS2 ANS1 ANS0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’

bit 6-4 ADCS<2:0>: A/D Conve rsi on C loc k Sele ct bits

000 = Fosc/2

001 = Fosc/8

010 = Fosc/32

x11 = F

RC (clock derived from a dedicated internal oscillator = 500 kHz max)

100 = Fosc/4

101 = Fosc/16

110 = Fosc/64

bit 3-0 ANS3:ANS0: Analog Select bits

(Between analog or digital function on pins AN<3:0>, respectively.)

1 = Analog input; pin is assigned as analog input(1)

0 = Digital I/O; pin is assigned to port or special function

Note 1: Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups, and inter-

rupt-on-c hange. The co rrespondin g TRISIO bit must be s et to Input mode in orde r to allow extern al control

of the voltage on the pin.

 2009 Microchip Technology Inc. DS41190F-page 47

PIC12F629/675

7.2 A/D Acquisition Requirements

For the A/D converter to meet its specified accuracy,

the charge holding capacitor (CHOLD) must be allowed

to fully charge to the input channel voltage level. The

analog in put m odel is shown in Figure 7-3. The source

impeda nce (RS) and the inte rnal sam pling swi tch (RSS)

impedance directly affect the time required to charge

the capacitor CHOLD. The sampling switch (RSS)

impedance varies over the device voltage (VDD), see

Figure 7-3. The maximum recommended imped-

ance for analog sources is 10 k. As the impedance

is decreased, the acquisition time may be decreased.

After the analog input channel is selected (changed),

this acquisition must be done before the conversion

can be sta rted.

To calculate the minimum acquisition time,

Equation 7-1 may be used. This equation assumes

that 1/2 LSb error is used (1024 steps for the A/D).

The 1/2 LSb error is the maximum error allowed for

the A/D to me et its spec ifie d re sol ut ion .

To calculate the minimum acquisition time, TACQ, see

the PIC® Mid-Range Reference Manual (DS33023).

EQUATION 7-1: ACQUISITION TIME

FIGURE 7-3: ANALOG INPUT MODEL

TACQ

Amplifier Settling Time +

Hold Capacitor Charging Time +

Temperature Coefficien t

TAMP + TC + TCOFF

2s + TC + [(Temperature -25°C)(0.05s/°C)]

CHOLD (RIC + RSS + RS) In(1/2047)

- 120p F (1k  + 7k + 10k) In(0.00048 85)

16.47s

2s + 16.47s + [(50°C -25C)(0.05s/C)

19.72s

Note 1: The reference voltage (VREF) has no effect on the eq uation, since it cancel s itself out.

2: The charge holding capacitor (CHOLD) is not discharged after each conversion.

3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin

leakage specification.

CPIN

RSANx

5 pF

VDD

VT = 0.6V

VT = 0.6V I LEAKAGE

RIC  1K

Sampling

Switch

SS RSS

CHOLD

= DAC capacitance

VSS

Sampling Switch

567891011

(k)

VDD

= 120 pF

± 500 nA

Legend: CPIN

I LEAKAGE

RIC

CHOLD

= input capacitance

= threshold voltage

= leakage current at the pin due to

= interconnect resistance

= sampling switch

= sample/hold capacitance (from DAC)

various junctions

PIC12F629/675

DS41190F-page 48  2009 Microchip Technology Inc.

7.3 A/D Operation During Sleep

The A/D converter module can operate during Sleep.

This requires the A/D clock source to be set to the

internal RC oscillator. When the RC clock source is

selected, the A/D waits one instruction before starting

the co nve rsion . This a llows the SLEEP instruc tion t o b e

execut ed, thus e lim inating m uc h o f th e s wi tc hin g n ois e

from the conversion. When the conversion is complete,

the GO/DONE bit is cleared, and the result is loaded

into the ADRESH:ADRESL registers. If the A/D

inter rupt is enab le d, the device awa ke ns fro m Slee p. If

the A/D interrupt is not enabled, the A/D module is

turned off, although the ADON bit remains set.

When the A/D clock source is something other than

RC, a SLEEP instruction causes the present conversion

to be aborted, and the A/D module is turned off. The

ADON bit remains set.

7.4 Effects of Reset

A device Reset forces all registers to their Reset state.

Thus the A/D module is turned off and any pending

conversion is aborted. The ADRESH:ADRESL regis-

ters are unchanged.

TABLE 7-2: SUMMARY OF A/D REGISTERS

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR,

BOD

Value on

all other

Resets

05h GPIO — — GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 -- xx xx xx --uu uuuu

0Bh, 8Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 000u

0Ch PIR1 EEIF ADIF — — CMIF — — TMR1IF 00-- 0--0 00 -- 0--0

1Eh ADRESH Most Significant 8 bits of the Left Shifted A/D result or 2 bits of the Right Shifted Result xxxx xx xx uu uu uuuu

1Fh ADCON0 ADFM VCFG —— CHS1 CHS0 GO ADON 00 -- 00 00 00 -- 0000

85h TRISIO — — TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 -- 11 1111 --11 1111

8Ch PIE1 EEIE ADIE — — CMIE — — TMR1IE 00-- 0--0 00-- 0--0

9Eh ADRESL Least Significant 2 bits of the Left Shifted A/D Result or 8 bits of the Right Shifted Result xx xx xxxx uuuu uuuu

9Fh ANSEL — ADCS2 ADCS1 ADCS0 ANS3 ANS2 ANS1 ANS0 -0 00 11 11 -0 00 1111

Legend: x = unknown, u = unchanged, - = unimplemented read as ‘0’. Shade d cells are not used for A/D converter module.

 2009 Microchip Technology Inc. DS41190F-page 49

PIC12F629/675

8.0 DATA EEPROM MEMORY

The EEPROM data memory is readable and writable

during norma l operation (full VDD range). This memo ry

is not directly mapped in the register file space.

Instead, it is indirectly addressed through the Special

Function Registers. There are four SFRs used to read

and write this memory:

• EECON1

• EECON2 (not a physically implemented register)

• EEDATA

• EEADR

EEDATA holds the 8-bit data for read/write, and

EEADR holds the address of the EEPROM location

being accessed. PIC12F629/675 devices have 128

bytes of dat a EEPROM with a n add res s ra nge from 0h

to 7Fh.

The EEPROM data memory allows byte read and write.

A byte write automatically erases the location and

writes the n ew data (erase be fore write). The EEPROM

data memory is rated for high eras e/write cycles. The

write time is controlled by an on-chip timer. The write

time will vary with voltage and temperature as well as

from ch ip t o c hi p . Pl ea s e r efe r t o AC Specif ic ati o ns fo r

exact limits.

When the data memory is code-protected, the CPU

may continue to read and write the data EEPROM

memory . The device programmer can no longer access

this memory.

Additional information on the data EEPROM is

available in the PIC® Mid-Range Reference Manual,

(DS33023).

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 EEDATn: Byte value to write to or read from data EEPROM

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— EADR6 EADR5 EADR4 EADR3 EADR2 EADR1 EADR0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Should be set to ‘0’

bit 6-0 EEADR: Specifies one of 128 locations for EEPROM Read/Write Operation

PIC12F629/675

DS41190F-page 50  2009 Microchip Technology Inc.

8.1 EEADR

The EEADR register can address up to a maximum of

128 bytes of data EEPROM. Only seven of the eight

bits in the register (EEADR<6:0>) are required. The

MSb (bit 7) is ignored.

The upper bit should always be ‘0’ to remain upward

compa tible with devic es that have more d ata EEPROM

memory.

8.2 EECON1 AND EECON2

REGISTERS

EECON1 is the control register with four low-order bits

physically implemented. The upper four bits are non-

impleme nted and read as ‘0’s.

Control bits RD and WR initiate read and write,

respectively. These bits cannot be cleared, only set, in

software. They are cleared in hardware at completion

of the read or write operation. The inability to clear the

WR bit in software prevents the accidental, premature

termination of a write operation.

The WREN bit, when set, will allow a write operation.

On powe r-up, the WR EN bit is clear. The WRERR bit i s

set when a write operation is interrupted by a MCLR

Reset, or a WDT Time-out Reset during normal

operatio n. In these s ituations , following Reset, the us er

can check the WRERR bit, clear it, and rewrite the

location. The data and address will be cleared,

therefore, the EEDATA and EEADR registers will need

to be re-initialized.

Interrupt flag bit EEIF in the PIR1 register is set when

write is complete. This bit must be cleared in software.

EECON2 is not a physical register. Reading EECON2

will read all ‘0’s. The EECON2 register is used

exclusively in the data EEPROM write sequence.

U-0 U-0 U-0 U-0 R/W-x R/W-0 R/S-0 R/S-0

— — — — WRERR WREN WR RD

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-4 Unimplemented: Read as ‘0’

bit 3 WRERR: EEPROM Error Flag bit

1 = A write operation is prematurely terminated (any MCLR Reset, any WDT Reset during normal

operation or BOD detect)

0 = The write operation completed

bit 2 WREN: EEPROM Write Enable bit

1 = Allows write cycle s

0 = Inhibits write to the data EEPROM

bit 1 WR: Write Control bit

1 = Initiates a wr ite cycl e (The bit is cle ared by hardw are o nce wr ite is co mplet e. The WR b it ca n only

be set, not cleared, in software.)

0 = Write cycle to the data EEPROM is complete

bit 0 RD: Read Control bit

1 = Initiates an EEPROM read (Read t akes one cycle. RD is cleared i n hardware. The RD bit c an only

be set, not cleared, in software).

0 = Does not initiate an EEPROM read

 2009 Microchip Technology Inc. DS41190F-page 51

PIC12F629/675

8.3 READING THE EEPROM DATA

MEMORY

To read a data memory location, the user must write

the address to the EEADR register and then set

control bit RD (EECON1<0>), as shown in

Example 8-1. The data is available, in the very next

cycle, in the EEDATA register. Therefore, it can be

read in the next instruction. EEDATA holds this value

until another read, or until it is written to by the user

(during a write operation).

EXAMPLE 8-1: DATA EEPROM READ

8.4 WRITING TO THE EEPROM DATA

MEMORY

To write an EEPROM data location, the user must first

write the address to the EEADR register and the data

to the EEDATA register. Then the user must follow a

specific sequence to initiate the write for each byte, as

shown in Example 8- 2.

EXAMPLE 8-2: DATA EEPROM WRITE

The write will not initiate if the above sequence is not

exactly followed (write 55h to EECON2, write AAh to

EECON2, then set WR bit) for each byte. We strongly

recommend that interrupts be disabled during this

code segment. A cycle count is executed during the

required s equence . Any number th at is not equa l to the

required cycles to execute the required sequence will

prevent the data from being writte n into the EEPROM .

Additionally, the WREN bit in EECON1 must be set to

enable write. This mechanism prevents accidental

writes to data EEPROM due to errant (unexpected)

code execution (i.e., lost programs). The user should

keep the WREN bit clear at all times, except when

updating EEPROM. The WREN bit is not cleared

by hardware.

After a write sequence has been initiated, clearing the

WREN bit wil l not af fect this wr ite cycle. T he WR bit wil l

be inhibi ted from bei ng s et u nle ss the W R EN bit is se t.

At the completion of the write cycle, the WR bit is

cleared in hardware and the EE Write Complete

Interrupt Flag bit (EEIF) is set. The user can either

enable this interrupt or poll this bit. The EEIF bit

(PIR<7>) register must be cleared by software.

8.5 WRITE VERIFY

Depending on the application, good programming

practice may dictate that the value written to the data

EEPROM should be verified (see Example 8-3) to the

desired value to be written.

EXAMPL E 8-3: W RIT E VE RIFY

8.5.1 USING THE DATA EEPROM

The data EEPROM is a high-endurance, byte

addressable array that has been optimized for the

storage of frequently changing information (e.g.,

program variables or other data that are updated

often). Frequently changing values will typically be

updated more often than specifications D120 or

D120A. If th is is not the ca se, an arra y re fres h m us t b e

performed. For this reason, variables that change

infrequently (such as constants, IDs, calibration, etc.)

should be sto r ed in Flas h prog ram memo ry.

8.6 PROTECTION AGAINST

SPURIOUS WRITE

There are conditions when the device may not want to

write to the data EEPROM memory. To protect against

spurious EEPROM writes, various mechanisms have

been buil t in. On power-u p, WREN is cleare d. Also, the

Power-up Timer (72 ms duration) prevents

EEPROM write.

The write initiate seq ue nce an d the WREN bi t together

help prevent an accidental write during:

•brown-out

• power glitch

• software malfunction

BSF STATUS,RP0 ;Bank 1

MOVLW CONFIG_ADDR ;

MOVWF EEADR ;Address to read

BSF EECON1,RD ;EE Read

MOVF EEDATA,W ;Move data to W

BSF STATUS,RP0 ;Bank 1

BSF EECON1,WREN ;Enable write

BCF INTCON,GIE ;Disable INTs

MOVLW 55h ;Unlock write

MOVWF EECON2 ;

MOVLW AAh ;

MOVWF EECON2 ;

BSF EECON1,WR ;Start the write

BSF INTCON,GIE ;Enable INTS

Required

Sequence

BCF STATUS,RP0 ;Bank 0

: ;Any code

BSF STATUS,RP0 ;Bank 1 READ

MOVF EEDATA,W ;EEDATA not changed

;from previous write

BSF EECON1,RD ;YES, Read the

;value written

XORWF EEDATA,W

BTFSS STATUS,Z ;Is data the same

GOTO WRITE_ERR ;No, handle error

: ;Yes, continue

PIC12F629/675

DS41190F-page 52  2009 Microchip Technology Inc.

8.7 DATA EEPROM OPERATIO N

DURING CODE PROTECT

Data me mory can be code prot ected by program ming

the CPD bit to ‘0’.

When the data memory is code protected, the CPU is

able to read and write data to the data EEPROM. It is

recommended to code protect the program memory

when code protecting data memory. This prevents

anyone from programming zeroes over the existing

code (which will execute as NOPs) to reach an added

routine, programmed in unused program memory,

which outputs the contents of data memory.

Programming unused locations to ‘0’ will also help

prevent data memory code protection from becoming

breached.

TABLE 8-1: REGISTERS/BITS ASSOCIATED WITH DATA EEPROM

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOD

Value on all

other

Resets

0Ch PIR1 EEIF ADIF — — CMIF — — TMR1IF 00-- 0--0 00-- 0--0

9Ah EEDATA EEPROM Data Register 0000 0000 0000 0000

9Bh EEADR — EEPROM Address Register -000 0000 -000 0000

9Ch EECON1 — — — — WRERR WREN WR RD ---- x000 ---- q000

9Dh EECON2(1) EEPROM Control Register 2 ---- ---- ---- ----

Legend: x = unknown, u = unchanged, - = unimplemented read as ‘0’, q = value depends upon condition.

Shaded cells are not used by data EEPROM module.

Note 1: EEC ON 2 is not a physical register.

 2009 Microchip Technology Inc. DS41190F-page 53

PIC12F629/675

9.0 SPECIAL FEATURES OF THE

CPU

Certain special circuits that deal with the needs of real

time applications are what sets a microcontroller apart

from other pro ce ssors . The PIC12 F629/675 fam il y has

a host of such features intended to:

• maximize system reliability

• minimize cost through elimination of external

components

• provide power saving operating modes and offer

code protection

These features are:

• Oscillator selection

• Reset

- Power-on Reset (P OR)

- Power-up Timer (PWRT)

- Oscillator Start-up Timer (OST)

- Brown-out Detect (BOD)

• Interrupts

• Watchdog Timer (WDT)

• Sleep

• Code protection

• ID Locations

• In-Circuit Serial Programming

The PIC12F629/675 has a Watchdog Timer that is

controlled by Configuration bits. It runs off its own RC

oscill ator for ad ded reli abili ty. There are two ti mers th at

offer necessary delays on power-up. One is the

Oscillator Start-up Timer (OST), intended to keep the

chip in Reset until the crystal oscillator is stable. The

other is the Pow er-up Timer (PWRT ), which prov ides a

fixed delay of 72 ms (nominal) on power-up only,

designed to keep the part in Reset while the power

supply stabilizes. There is also circuitry to reset the

device if a brown-ou t occurs, whi ch can provide at least

a 72 ms Reset. With these three functions on-chip,

most applications need no external Reset circuitry.

The Sleep mo de is des igned to of fer a ve ry low current

Power-down mode. The user can wake-up from Sleep

through:

•External Reset

• Watchdog Timer wake-up

• An interrupt

Several oscillator options are also made available to

allow the p art to f it th e a pplicati on. The IN T OSC op tio n

saves system cost while the LP crystal option saves

power. A set of Configuration bits are used to select

various o ption s (see Registe r 9.2).

PIC12F629/675

DS41190F-page 54  2009 Microchip Technology Inc.

9.1 Configuration Bits

The Configuration bits can be programmed (read as

‘0’), or lef t unprogrammed (read as ‘1’) to select various

device config urations, as shown in Re gister 9.2. These

bits are mapped in program memory location 2007h.

Note: Address 2007h is beyond the user program

memory space. It belongs to the special con-

figuration memory space (2000h-3FFFh),

which can be accessed only during program-

ming. See PIC12F629/675 Programming

S pecification for more information.

R/P-1 R/P-1 U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1

BG1 BG0 — — —CPDCP BODEN MCLRE PWRTE WDTE F0SC2 F0SC1 F0SC0

bit 13 bit 0

Legend:

P = Programmed using ICSP™

R = Readable bit Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR 1 = bit is set 0 = bit is cleared x = bit is unknown

bit 13-12 BG1:BG0: Bandgap Calibration bits for BOD and POR voltage(1)

00 = Lowest bandgap voltage

11 = Highest bandgap voltage

bit 11-9 Unimplemented: Read as ‘0’

bit 8 CPD: Data Code Protection bit(2)

1 = Data memory code protection is disabled

0 = Data memory code protection is enabled

bit 7 CP: Code Protection bit(3)

1 = Program Memory code protection is disabled

0 = Program Memory code protection is enabled

bit 6 BODEN: Brown-out Detect Enable bit(4)

1 = BOD enabled

0 = BOD disabled

bit 5 MCLRE: GP3/MCLR Pi n Function Select bit(5)

1 = GP3/MCLR pin function is MCLR

0 = GP3/MCLR pin function is digital I/O, MCLR internally tied to VDD

bit 4 PWRTE: Power-up Timer Enable bit

1 = PWRT disabled

0 = PWRT enabled

bit 3 WDTE: Watchdog Timer Enable bit

1 = WDT enabled

0 = WDT disabled

bit 2-0 FOSC2:FOSC0: Oscillator Selection bits

111 = RC oscillator: CLKOUT function on GP4/OSC2/CLKOUT pin, RC on GP5/OSC1/CLKIN

110 = RC oscillator: I/O function on GP4/OSC2/CLKOUT pin, RC on GP5/OSC1/CLKIN

101 = INTOSC oscillator: CLKOUT function on GP4/OSC2/CLKOUT pin, I/O function on GP5/OSC1/CLKIN

100 = INTOSC oscillator: I/O function on GP4/OSC2/CLKOUT pin, I/O function on GP5/OSC1/CLKIN

011 = EC: I/O function on GP4/OSC2/CLKOUT pin, CLKIN on GP5/OSC1/CLKIN

010 = HS oscillator: High speed crystal/resonator on GP4/OSC2/CLKO UT and GP5/OSC1/C LKI N

001 = XT oscillator: Crystal/resonator on GP4/OSC2/CLKOU T and GP5/OSC1/CLKIN

000 = LP oscillator: Low-power crystal on GP4/OSC2/CLKOUT and GP5/OSC1/CLKIN

Note 1: The Bandgap Calibration bits are factory programmed and must be read and saved prior to erasing the device as spec-

ified in the PIC12F629/675 Programming Specification. These bits are reflected in an export of the Configuration Word.

Microchip Development Tools maintain all Calibration bits to factory settings.

2: The entire data EEPROM will be erased when the code protection is turned off.

3: The entire program memory will be erased, including OSCCAL value, when the code protection is turned off.

4: Enabling Brown-out Detect does not automatically enable Power-up Timer.

5: When MCLR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled.

 2009 Microchip Technology Inc. DS41190F-page 55

PIC12F629/675

9.2 Oscillator Configurations

9.2.1 OSCILLA TOR TYP E S

The PIC12F629/675 can be operated in eight different

oscillator option modes. The user can program three

Configuration bits (FOSC2 through FOSC0) to select

one of these eight modes:

• LP Low-Power Crystal

• XT Crystal/Resonator

• HS High-Speed Crys tal/R es ona tor

• RC Extern al Resi stor/Capacitor (2 modes)

• INT O SC In ternal Osci ll ator (2 mod es )

• EC External C loc k In

9.2.2 CRYSTAL OSCILLATOR / CERAMIC

RESONATORS

In XT, LP or HS modes a crystal or ceramic resonator

is connected to the OSC1 and OSC2 pins to establish

oscillation (see Figure 9-1). The PIC12F629/675

oscillator design requires the use of a parallel cut

crystal. Use of a series cut crystal may yield a

frequency outside of the crystal manufacturers

specifications. When in XT, LP or HS modes, the

device can have an external clock source to drive the

OSC1 pin (see Figure 9-2).

FIGURE 9-1: CRYSTAL OPERATION (OR

CERAMIC RESONATOR)

HS, XT OR LP OSC

CONFIGURATION

FIGURE 9-2: EXTERNAL CLOCK INPUT

OPERAT ION (HS, XT, EC,

OR LP OSC

CONFIGURATION)

T ABLE 9-1: CAPACITOR SELECTION FOR

CERAMIC RESONATORS

T ABLE 9-2: CAPACITOR SELECTION FOR

CRYSTAL OSCILLATOR

Note: Additional information on oscillator config-

urations is available in the PIC® Mid-

Range Reference Manual, (DS33023).

Note 1: See Table 9-1 and Table 9-2 for recommended

values of C1 and C2.

2: A se ries resistor may be required for AT strip cut

crystals.

3: RF varies with the Oscillator mode selected

(Approx. value = 10 M

C1(1)

C2(1)

XTAL

OSC2

OSC1

RF(3) Sleep

To Internal

PIC12F629/675

Logic

RS(2)

Ranges Char ac teriz ed:

Mode Freq. OSC1(C1) OSC2(C2)

XT 455 kHz

2.0 MHz

4.0 MHz

68-100 pF

15-68 pF

68-100 pF

15-68 pF

HS 8.0 MHz

16.0 MHz 10-68 pF

10-22 pF 10-68 pF

10-22 pF

Note 1: Higher capacitance increases the stability

of the oscillator but also increases the

start-up time. These values are for design

guidance only. Since each resonator has

its own characteristics, the user should

consult the resonator manufacturer for

appropriate values of external

components.

Mode Freq. OSC1(C1) OSC2(C2)

LP 32 kHz 68-100 pF 68-100 pF

XT 100 kHz

2 MHz

4 MHz

68-150 pF

15-30 pF

150-200 pF

15-30 pF

HS 8 MHz

10 MHz

20 MHz

15-30 pF

Note 1: Higher capacitance increases the stability

of the oscillator but also increases the

start-up time. These values are for design

guidance only. Rs may be required in HS

mode as well as XT mode to avoid

overdriving crystals with low drive level

specification. Since each crystal has its

own characteristics, the user should

consult the crystal manufacturer for

appropriate values of external

components.

Clock from

External Sy stem PIC12F629/675

OSC1

OSC2(1)

Open

Note 1: Functions as GP4 in EC Osc mode.

PIC12F629/675

DS41190F-page 56  2009 Microchip Technology Inc.

9.2.3 EXTERN AL CLOCK IN

For applications where a clock is already available

elsewhere, users may directly drive the PIC12F629/

675 provided that this external clock source meets the

AC/DC timing requirements listed in Section 12.0

“Electrical Specifications”. Figure 9-2 shows how

an ex ternal clock circuit s hould be configured.

9.2.4 RC OSCILLATOR

For applications where precise timing is not a

requirement, the RC oscillator option is available. The

operation and functionality of the RC oscillator is

dependent upon a number of variables. The RC

oscillator frequency is a function of:

• Supply voltage

• Resistor (REXT) and capacitor (CEXT) values

• Operati ng tem pera ture .

The oscillator frequency will vary from unit to unit due

to normal process parameter variation. The difference

in lead frame capacitance between package types will

also affect the oscillation frequency, especially for low

CEXT values. The user also needs to account for the

tolerance of the external R and C components.

Figure 9-3 shows how the R/C combination is

connected.

Two options are available for this Oscillator mode

which allow GP4 to be used as a general purpose I/O

or to output FOSC/4.

FIGURE 9-3: RC OSCILLATOR MODE

9.2.5 INTERNAL 4 MHZ OSCILLATOR

When calib rated, the in ternal oscillat or provide s a fixed

4 MHz (nominal) system clock. See Electrical

Specifications, Section 12.0 “Electrical Specifica-

tions”, for information on variation over voltage and

temperature.

Two options are available for this Oscillator mode

which allow GP4 to be used as a general purpose I/O

or to output FOSC/4.

9.2.5.1 Calibrating the Internal Oscillator

A calibration instruction is programmed into the last

location of program memory. This instruction is a

RETLW XX, where the literal is the calibration value.

The literal is placed in the OSCCAL register to set the

calibration of the internal oscillator. Example 9-1

demonstrates how to calibrate the internal oscillator.

For best operation, decouple (with capacitance) VDD

and VSS as close to the device as possible.

EXAMPLE 9-1: CALIBRA TING THE

INTERNAL OSCILLATOR

9.2.6 CLKOUT

The PIC12F629/675 devices can be configured to

provide a clock out signal in the INTOSC and RC

oscillator modes. When configured, the oscillator

frequency divided by four (FOSC/4) is output on the

GP4/OSC2/CLKOUT pin. FOSC/4 ca n be us ed for t est

purposes or to synchronize other logic.

GP4/OSC2/CLKOUT

CEXT

VDD

REXT

VSS

PIC12F629/675

GP5/OSC1/

FOSC/4

Internal

Clock

CLKIN

Note: Erasing the device will also erase the pre-

programmed internal calibration value for

the inte rnal osci llator. The calibration value

must be saved prior to erasing part as

specified in the PIC12F629/675 Program-

ming specification. Microchip Develop-

ment Tools maintain all Calibration bits to

facto ry set t in gs.

BSF STATUS, RP0 ;Bank 1

CALL 3FFh ;Get the cal value

MOVWF OSCCAL ;Calibrate

BCF STATUS, RP0 ;Bank 0

 2009 Microchip Technology Inc. DS41190F-page 57

PIC12F629/675

9.3 Reset

The PIC12F629/675 differentiates between various

kinds of Re set :

a) Power-on Reset (POR)

b) WDT Reset during normal operation

c) WDT Reset during Sleep

d) MCLR Reset during normal operation

e) MCLR Reset during Sleep

f) Brown-out Detect (BOD)

Some regi sters a re not af fected in any Rese t condi tion;

their st at us is un kn ow n o n POR a nd un ch ang ed in any

other Reset. Most other registers are reset to a “Reset

state” on:

• Power-on Reset

•MCLR

Reset

•WDT Reset

• WDT Reset during Sleep

• Brown-out Detect (BOD) Reset

They are not affected by a WDT wake-up, since this is

viewe d as the resump tio n of normal op era tion . TO and

PD bits are set or cleared differently in different Reset

situations as indicated in Table 9-4. These bits are

used in software to determine the nature of the Reset.

See Table 9-7 for a ful l descri ption of Res et st ates of al l

registers.

A simplified block diagram of the on-chip Reset Circuit

is sh own i n Figure 9-4.

The MCLR Reset path has a noise filter to detect and

ignore small pulses. See Table 12-4 in Electrical

Specifications Section for pulse-width specification.

FIGURE 9-4: SI MPLI FI ED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

External

Reset

MCLR/

VDD

OSC1/

WDT

Module

VDD Rise

Detect

OST/PWRT

On-chip(1)

RC OSC

WDT

Time-out

Power-on Reset

OST

PWRT

Chip_Reset

10-bit Ripple Counter

Reset

Enable OST

Enable PWRT

SLEEP

See Table 9-3 for time-out situations.

Note 1: This is a separate oscillator from the INTOSC/EC oscillator.

Brown-out

Detect BODEN

CLKIN

VPP pin

10-bit Ripple Counter

PIC12F629/675

DS41190F-page 58  2009 Microchip Technology Inc.

9.3.1 MCLR

PIC12F629/675 devices have a noise filter in the

MCLR Reset path. The filter will detect and ignore

small pul ses.

It should be noted that a WDT Reset does not drive

MCLR pin low.

The behavior of the ESD protection on the MCLR pin

has been altered from previous devices of this family.

Volta ges app lied to the pin th at exce ed it s spe cific ation

can resu lt in both MC L R Rese t s a nd e xc es sive c urre nt

bey ond t h e de v ic e sp e ci fic at i on du ri ng th e ESD ev e nt .

For this rea son, Microc hip recomme nds that the MC LR

pin no long er be tied direc tly to VDD. The us e of an RC

network, as shown in Figure 9-5, is suggested.

An internal MCLR option is enabled by setting the

MCLRE bit in the Configuration Word. When enabled,

MCLR is internally tied to VDD. No internal pull-up

option is availab le for the MCLR pin.

FIGURE 9-5: RECOMMENDE D MCLR

CIRCUIT

9.3.2 POWER-ON RESET (POR)

The on-chip POR circuit holds the chip in Reset until

VDD has reached a high enough level for proper

operat ion. To ta ke advant age of the POR, si mply tie the

MCLR pin through a res is tor to VDD. This will eliminate

external RC components usually needed to create

Power-on Reset. A maximum rise time for VDD is

required. See Electrical Specifications for details (see

Section 12.0 “Electrical Spe cificatio ns”). If t he BOD

is enabled, the maximum rise time specification does

not apply. The BOD circuitry will keep the device in

Reset until VDD reaches VBOD (see Section 9.3.5

“Brown-Out Detect (BOD)”).

When the device starts normal operation (exits the

Reset condition), device operating parameters (i.e.,

voltage, frequency, temperature, etc.) must be met to

ensure operation. If these conditions are not met, the

device must be held in Reset until the operating

conditions are met.

For additional information, refer to Application Note

AN607, “Power-up Trouble Shooting”.

9.3.3 POWER-UP TIMER (PWRT)

The P owe r-u p Timer pr ov ides a fi xed 72 ms (nomi nal )

time-out on power-up only, from POR or Brown-out

Detect. The Power-up Timer operates on an internal

RC oscillator. The chip is kept in Reset as long as

PWRT is active. The PWRT delay allows the VDD to

rise to an acceptable level. A Configurati on bit, PWRTE

can disable (if set) or enable (if cleared or

programmed) the Power-up Timer. The Power-up

Timer should always be enabled when Brown-out

Detect is enabled.

The Power-up Time delay will vary from chip to chip

and due to:

•V

DD variation

• Temperature variation

• Process variation.

See DC parameters for details (Section 12.0 “Electri-

cal Specifications”).

9.3.4 OSCILLATOR START-UP TIMER

(OST)

The Oscillator Start-up Timer (OST) provides a 1024

oscillator cycle (from OSC1 input) delay after the

PWRT delay is over. This ensures that the crystal

oscillator or resonator has started and stabilized.

The OST time-out is invoked only for XT, LP and HS

modes and only on Power-on Reset or wake-up from

Sleep.

Note: The POR circuit does not produce an

internal Reset when VDD declines .

VDD PIC12F629/675

MCLR

1 kor greater

0.1 f

(optio nal, not critic al )

 2009 Microchip Technology Inc. DS41190F-page 59

PIC12F629/675

9.3.5 BROWN-OUT DETECT (BOD)

The PIC1 2F629/675 me mbers have on -chip Brow n-out

Detect circuitry. A Configuration bit, BODEN, can

disable (if clear/programmed) or enable (if set) the

Brown-out Detect circuitry. If VDD falls below VBOD for

greater than parameter (TBOD) in Table 12-4 (see

Section 12.0 “Electrical Specifications”), the

Brown-out situation will reset the device. This will occur

regardles s of VDD slew-rate. A Reset i s not guarantee d

to occur if VDD falls below VBOD for l ess than para meter

(TBOD).

On any Reset (Power-on, Brown-out, Watchdog, etc.),

the chip will remain in Reset until VDD rises above

BVDD (see Figure 9-6). The Power-up Timer will now

be invoked, if enabled, and will keep the chip in Reset

an additional 72 ms.

If VDD drops below BVDD while the Power-up Timer is

running, the chip will go back into a Brown-out Detect

and the Power-u p Timer will be re-initialized. Onc e VDD

rises above BVDD, the Power-up Timer will execute a

72 ms Reset.

FIGURE 9-6: BROW N-OUT SITUATIONS

9.3.6 TIME-OUT SEQUENCE

On power-u p, the tim e-out sequ ence is as fo llows: first,

PWRT time-out is invoked after POR has expired.

Then, OST is activated. The total time-out will vary

based on oscillator configuration and PWRTE bit

status. For example, in EC mode with PWRTE bit

erased (PWRT disabled), there will be no time-out at

all. Figure 9-7, Figure 9-8 and Figure 9-9 depict time-

out sequences.

Since the time-outs oc cur from the PO R pulse, if MCLR

is kep t low long e nough , the ti me-out s w ill e xpire. Then

bringing MCLR high will begin execution immediately

(see Figure 9-8). This is useful for testing purposes or

to synchronize more than one PIC12F629/675 device

operating in parallel.

Table 9-6 shows th e R es et co ndi tions for s om e s pec ia l

registers, while Table 9-7 shows the Reset conditions

for all the registers.

9.3.7 POWER CONTROL (PCON) STATUS

The power CONTROL/STATUS register, PCON

(address 8Eh) has two bits.

Bit 0 is BOD (Brown-out). BOD is unknown on Power-

on Reset. It must then be set by the user and checked

on subsequent Res ets to see if BOD = 0, indicating th at

a brown-out has occurred. The BOD Status bit is a

“don’t care” and is not necessarily predictable if the

brown-o ut c irc uit is dis ab led (by se ttin g BOD EN bit = 0

in the Configuration Word).

Bit 1 is POR (Power-on Reset). It is a ‘0’ on Power-on

Reset and unaf fec ted oth erwise. T he user m ust write a

‘1’ to this bit following a Power-on Reset. On a

subsequent Reset, if POR is ‘0’, it will indicate that a

Power-on Reset must have occurred (i.e., VDD may

have gone too low ).

Note: A Brown-out Detect does not enable the

Power-up Timer if the PWRTE bit in the

Configuration Word is set.

72 ms(1)

VBOD

VDD

Internal

Reset

VBOD

VDD

Internal

Reset 72 ms(1)

<72 ms

72 ms(1)

VBOD

VDD

Internal

Reset

Note 1: 72 ms delay only if PWRTE bit is programmed to ‘0’.

PIC12F629/675

DS41190F-page 60  2009 Microchip Technology Inc.

TABLE 9-3: TIME-OUT IN VARIOUS SITUATIONS

TABLE 9-4: STATUS/PCON BITS AND THEIR SIGNIFICANCE

TABLE 9-5: SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT

TABLE 9-6: INITIALIZATION CONDITION FOR SPECIAL REGISTERS

Oscillator Configuration Power-up Brown-out Detect Wake-up

from Sleep

PWRTE = 0PWRTE = 1PWRTE = 0PWRTE = 1

XT, HS, LP TPWRT +

1024•TOSC 1024•TOSC TPWRT +

1024•TOSC 1024•TOSC 1024•TOSC

RC, EC, INTOSC TPWRT —TPWRT ——

POR BOD TO PD

0u11Power-on Reset

1011Brown-out Detect

uu0uWDT Reset

uu00WDT Wake-up

uuuuMCLR Reset during normal operation

uu10MCLR Reset during Sleep

Legend: u = unchanged, x = unknown

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOD

V alue on all

other

Resets(1)

03h STATUS IRP RP1 RPO TO PD ZDC C0001 1xxx 000q quuu

8Eh PCON — — — — ——PORBOD ---- --0x ---- --uq

Legend:u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’, q = value depends on condition.

Note 1: Other (non Power-up) Resets include MCLR Reset, Brown-out Detect and Watchdog Timer Reset during

normal operation.

Condition Program

Counter STATUS

Power-on Reset 000h 0001 1xxx ---- --0x

MCLR Reset during normal operation 000h 000u uuuu ---- --uu

MCLR Reset during Sleep 000h 0001 0uuu ---- --uu

WDT Reset 000h 0000 uuuu ---- --uu

WDT Wake- up PC + 1 uuu0 0uuu ---- --uu

Brown-out Detect 000h 0001 1uuu ---- --10

Interrupt Wake-up from Sleep PC + 1(1) uuu1 0uuu ---- --uu

Legend:u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’.

Note 1: When the wake-up is due to an interrupt and global enable bit GIE is set, the PC is loaded with the

interrupt v ector (0 004h) afte r execution of PC + 1.

 2009 Microchip Technology Inc. DS41190F-page 61

PIC12F629/675

TABLE 9-7: INITIALIZATION CONDITION FOR REGISTERS

Reset

•MCLR

Reset during

normal operation

•MCLR Reset during Sleep

• WDT Reset

• Brown-out Detect(1)

• Wake-up from Sleep

through interrupt

• Wake-up from Sleep

through WDT Time-out

W—xxxx xxxx uuuu uuuu uuuu uuuu

INDF 00h/80h — — —

TMR0 01h xxxx xxxx uuuu uuuu uuuu uuuu

PCL 02h/82h 0000 0000 0000 0000 PC + 1(3)

STATUS 03h/83h 0001 1xxx 000q quuu(4) uuuq quuu(4)

FSR 04h/84h xxxx xxxx uuuu uuuu uuuu uuuu

GPIO 05h --xx xxxx --uu uuuu --uu uuuu

PCLATH 0Ah/8Ah ---0 0000 ---0 0000 ---u uuuu

INTCON 0Bh/8Bh 0000 0000 0000 000u uuuu uuqq(2)

PIR1 0Ch 00-- 0--0 00-- 0--0 qq-- q--q(2,5)

T1CON 10h -000 0000 -uuu uuuu -uuu uuuu

CMCON 19h -0-0 0000 -0-0 0000 -u-u uuuu

ADRESH 1Eh xxxx xxxx uuuu uuuu uuuu uuuu

ADCON0 1Fh 00-- 0000 00-- 0000 uu-- uuuu

OPTION_REG 81h 1111 1111 1111 1111 uuuu uuuu

TRISIO 85h --11 1111 --11 1111 --uu uuuu

PIE1 8Ch 00-- 0--0 00-- 0--0 uu-- u--u

PCON 8Eh ---- --0x ---- --uu(1,6) ---- --uu

OSCCAL 90h 1000 00-- 1000 00-- uuuu uu--

WPU 95h --11 -111 --11 -111 uuuu uuuu

IOC 96h --00 0000 --00 0000 --uu uuuu

VRCON 99h 0-0- 0000 0-0- 0000 u-u- uuuu

EEDATA 9Ah 0000 0000 0000 0000 uuuu uuuu

EEADR 9Bh -000 0000 -000 0000 -uuu uuuu

EECON1 9Ch ---- x000 ---- q000 ---- uuuu

EECON2 9Dh ---- ---- ---- ---- ---- ----

ADRESL 9Eh xxxx xxxx uuuu uuuu uuuu uuuu

ANSEL 9Fh -000 1111 -000 1111 -uuu uuuu

Legend:u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’, q = value depends on condition.

Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently.

2: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up).

3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt

vector (0004h).

4: See Table 9-6 for Reset value for specific condition.

5: If wake-up was due to data EEPROM write completing, Bit 7 = 1; A/D conversion completing, Bit 6 = 1;

Comparator input changing, bit 3 = 1; or Timer1 rolling over, bit 0 = 1. All other interrupts generating a

wake-up will cause th ese bits to = u.

6: If Reset was due to brown-out, then bit 0 = 0. All ot her Resets will cause bit 0 = u.

PIC12F629/675

DS41190F-page 62  2009 Microchip Technology Inc.

FIGURE 9-7: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1

FIGURE 9-8: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2

FIGURE 9-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)

TPWRT

TOST

VDD

MCLR

Internal POR

PWRT T ime-out

OST Time-out

Internal Reset

VDD

MCLR

Internal POR

PWRT Time-out

OST Time-out

Internal Reset

TPWRT

TOST

TPWRT

TOST

VDD

MCLR

Internal POR

PWRT Time-out

OST Time-out

Internal Reset

 2009 Microchip Technology Inc. DS41190F-page 63

PIC12F629/675

9.4 Interrupts

The PIC12F629/675 has 7 sources of interrupt:

• External Inte rrup t GP2/INT

• TMR0 Overfl ow Interru pt

• GPIO Change Interrupts

• Comparator Interrupt

• A/D Interrupt (PIC12F675 only)

• TMR1 Overfl ow Interru pt

• EEPROM Data Write Interrupt

The Interrup t Control register (INTCON) and Peripheral

Interrupt register (PIR) record individual interrupt

requests in flag bits. The INTCON register also has

individual and Global Interrupt Enable (GIE) bits.

A Global Interrupt Enable bit, GIE (INTCON<7>)

enables (if set) all unmasked interrupts, or disables (if

cleared) all interrupts. Individual interrupts can be

disabled through their corresponding enable bits in INT-

CON register and PIE register. GIE is cl eared on R ese t.

The return f rom interrupt instruction, RETFIE, exits

interrupt routine, as well as sets the GIE bit, which

re-enables unmasked inter rupts.

The following interrupt flags are contained in the

INTCON register:

• INT pin interrupt

• GP port change interrupt

• TMR0 ove rflo w interru pt

The peripheral interrupt flags are contained in the

special register PIR1. The corresponding interrupt

enable bit is contained in special register PIE1.

The following interrupt flags are contained in the PIR

• EEPROM data write interrupt

• A/D interrupt

• Comparator interrupt

• Timer1 overflow interrupt

When an interrupt is serviced:

• The GIE is cleared to disable any further interrupt

• The return address is pushed onto the stack

• The PC is loaded with 0004h

Once in the Interrupt Service Routine, the source(s) of

the interrupt can be determined by polling the interrupt

flag bits. The interrupt flag bit(s) must be cleared in

software before re-enabling interrupts to avoid GP2/

INT recursive interrupts.

For external interrupt events, such as the INT pin, or

GP port change interrupt, the interrupt latency will be

three or four instruction cycles. The exact latency

depends upon when the interrupt event occurs (see

Figure 9-11). The latency is the same for one or two-

cycle instructions. Once in the Interrupt Service

Routine, the source(s) of the interrupt can be

determined by polling the interrupt flag bits. The

interrupt flag bit(s) must be cleared in software before

re-enabling interrupts to avoid multiple interrupt

requests.

Note 1: Individual interrupt flag bits are set,

regardless of the status of their

corresponding mask bit or the GIE bit.

2: When an instruction that clears the GIE

bit is executed, any interrupts that were

pending for execution in the next cycle

are ignored. The interrupts which were

ignored are still pending to be serviced

when the GIE bit is set again.

PIC12F629/675

DS41190F-page 64  2009 Microchip Technology Inc.

FIGURE 9-10: INTE RRUP T LOGIC

TMR1IF

TMR1IE

CMIF

CMIE

T0IF

T0IE

INTF

INTE

GPIF

GPIE

GIE

PEIE

Wake-up (If in Sleep mode)

Interrupt to CPU

EEIE

EEIF

ADIF

ADIE (1)

Note 1: P IC12F675 only.

IOC-GP0

IOC0

IOC-GP1

IOC1

IOC-GP2

IOC2

IOC-GP3

IOC3

IOC-GP4

IOC4

IOC-GP5

IOC5

 2009 Microchip Technology Inc. DS41190F-page 65

PIC12F629/675

9.4.1 GP2/INT INTERRUPT

External interrupt on GP2/INT pin is edge-triggered;

either rising if INTEDG bit (OPTION<6>) is set, of

falling, if INTEDG bit is clear. When a valid edge

appears on the GP2/INT pin, the INTF bit (INT-

CON<1>) is set. This interrupt can be disabled by

clear ing th e INTE control bit (IN TCON<4> ). The I NTF

bit must be cleared in software in the Interrupt Service

Routin e bef ore re-e nab li ng thi s in terru pt. Th e GP2 /IN T

interrupt can wake-up the processor from Sleep if the

INTE bit w as set pr ior to going into Sleep. The sta tus of

the GIE bit decides whether or not the processor

branche s to the interru pt vector foll owing wake-up. Se e

Section 9.7 “Power-Down Mode (Sleep)” for details

on Sleep and Figure 9-13 for timing of wake-up from

Sleep through GP2/INT interrupt.

9.4.2 TMR0 INTERRUPT

An overflow (FFh  00h) in the TMR0 register will

set the T0IF (INTCON<2>) bit. The interrupt can

be enabled/disabled by setting/clearing T0IE

(INTCON<5>) bit. For operation of the Timer0 module,

see Section 4.0 “Timer0 Module”.

9.4.3 GPIO INTERRUPT

An input change on GPIO change sets the GPIF

(INTCON<0>) bit. The interrupt can be enabled/

disabled by setting/clearing the GPIE (INTCON<3>)

bit. Plus individual pins can be configured through the

IOC register.

9.4.4 COMPARATOR INTERRUPT

See Section 6.9 “Comparator Interrupts” for

description of comparator interrupt.

9.4.5 A/D CONVERTER INTERRUPT

After a c onv ers io n is co mpl ete , the ADIF flag (PIR<6 >)

is set. T he inte rrupt ca n be en abl ed/dis abled by se tting

or clearing ADIE (PIE<6>).

See Section 7.0 “Analog-to-Digital Converter (A/D)

Module (PIC12F675 only)” for operation of the A/D

converter interrupt.

FIGURE 9-11: INT PIN INTERRUPT TIMING

Note: The ANSEL (9Fh) and CMCON (19h)

registers must be initia lized to configu re an

analog channel as a digital input. Pins

configured as analog inputs will read ‘0’.

The ANSEL register is defined for the

PIC12F675.

Note: If a change on the I/O pin should occur

when th e read o peratio n is be ing ex ecute d

(start of the Q 2 cycle), then the GPIF int er-

rupt flag may not get set.

Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4

OSC1

CLKOUT

INT pin

INTF Fla g

(INTCON<1>)

GIE bit

(INTCON<7>)

INSTRUCTION FLOW

Instruction

Fetched

Instruction

Executed

Interrupt Latency

PC PC + 1 PC + 1 0004h 0005h

Inst (0004h) Inst (0005h)

Dummy Cycl e

Inst (PC) Inst (PC+1)

Inst (PC - 1) Inst (0004h)

Dummy Cycl e

Inst ( PC)

—

512

Note 1: INTF flag is sampled here (every Q1).

2: Asynchronous interrupt latency = 3-4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycle time. Latency

is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.

3: CLKOUT is available only in RC Oscillator mode.

4: For minimum width of INT pulse, refer to AC specs.

5: INTF is enabled to be set any time during the Q4-Q1 cycles.

PIC12F629/675

DS41190F-page 66  2009 Microchip Technology Inc.

TABLE 9-8: SUMMARY OF INTERRUPT REGISTERS

9.5 Context Saving During Interrupts

During an interrupt, only the return PC value is saved

on the stack. Typically, users may wish to save key

registers during an interrupt (e.g., W register and

STATUS register). This must be implemented in

software.

Example 9-2 stores and restores the STATUS and W

in both banks and must be defined at the same offset

from the bank base address (i.e., W_TEMP is defined

at 0x20 in Bank 0 and it must also be defined at 0xA0

in Bank 1 ). The us er registe r, STA T US_TEMP, must be

defined in Bank 0. The Example 9-2:

• Stores the W register

• Stores the STATUS register in Bank 0

• Executes the ISR code

• Restores the STATUS (and bank select bit

• Restores the W register

EXAMPLE 9-2: SA VING THE ST A TUS AND

W REGISTERS IN RAM

9.6 Watchdog Timer (WDT)

The Watchdog Timer is a free running, on-chip RC

oscillator , which requires no external components. This

RC oscillator is sep arate from the external RC oscillator

of the CLKIN pin and INTOSC. That means that the

WDT will run , even if th e clock on th e OSC1 and OSC 2

pins of the device has been stopped (for example, by

execution of a SLEEP instruction). During normal

operation, a WDT Time-out generates a device Reset.

If the devic e is in Sleep mo de, a WDT T ime -out causes

the device to wake-up and continue with normal

operation. The WDT can be permanently disabled by

programming the Configuration bit WDTE as clear

(Section 9.1 “Configuration Bits”).

9.6.1 WDT PERIOD

The WDT ha s a nominal tim e-out period of 18 ms, (wi th

no prescaler). The time-out periods vary with

temperature, VDD and process variations from part to

part (see DC specs). If longer time-out periods are

desired, a prescaler with a division ratio of up to 1:128

can be as si gne d to th e WD T un der soft w are c ont rol b y

writing to the OPTION register. Thus, time-out periods

up to 2.3 seconds can be realized.

The CLRWDT and SLEEP instructions clear the WDT

and the presc al er, if assi gne d to the WD T, and preve nt

it from timing out and generating a device Reset.

The TO bit in the STATUS register will be cleared upon

a Watchdog Timer Ti me-out.

9.6.2 WDT PROGRAMMING

CONSIDERATIONS

It should also be taken in account that under worst-

case con d iti on s (i .e ., VDD = Min., Temperature = Max.,

Max. WDT prescaler) it may take several seconds

before a WDT Time-out occurs.

AddressNameBit 7Bit 6Bit 5Bit 4Bit 3Bit 2 Bit 1Bit 0Value on

POR, BOD

Value on all

other

Resets

0Bh, 8Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 000u

0Ch PIR1 EEIF ADIF ——CMIF——TMR1IF00-- 0--0 00-- 0--0

8Ch PIE1 EEIE ADIE ——CMIE——TMR1IE00-- 0--0 00-- 0--0

Legend: x = unknown, u = unchanged, - = unimplemented read as ‘0’, q = value depends upon condition.

Shaded cells are not used by the Interrupt module.

MOVWF W_TEMP ;copy W to temp register,

could be in either bank

SWAPF STATUS,W ;swap status to be saved into W

BCF STATUS,RP0 ;chang e to bank 0 regardl ess of

current bank

MOVWF STATUS_TEMP ;save status to bank 0 register

:(ISR)

SWAPF STATUS_TEMP,W;swap STATUS_TEMP register into

W, sets bank to original state

MOVWF STATUS ;move W into STATUS register

SWAPF W_TEMP,F ;swap W_TEMP

SWAPF W_TEMP,W ;swap W_TEMP into W

 2009 Microchip Technology Inc. DS41190F-page 67

PIC12F629/675

FIGURE 9-12: WATCHDOG TIMER BLOCK DIAGRAM

TABLE 9-9: SUMMARY OF W ATCHDOG TIMER REGISTERS

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Va lue on

POR, BOD

V alue on all

other

Resets

81h OPTION_REG GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

2007h Config. bits CP BODEN MCLRE PWRTE WDTE F0SC2 F0SC1 F0SC0 uuuu uuuu uuuu uuuu

Legend: u = Unchanged, shaded cells are not used by the Watchdog Timer.

T0CKI

T0SE

CLKOUT

TMR0

Watchdog

Timer

WDT

Time-out

PS0 - PS2

WDTE

Data Bus

Set Flag bit T0IF

on Overflow

T0CS

Note 1: T0SE, T0CS, PSA, PS0-PS2 are bits in the OPTION register.

SYNC 2

Cycles

8-bit

Prescaler

(= FOSC/4)

PSA

PIC12F629/675

DS41190F-page 68  2009 Microchip Technology Inc.

9.7 Power-Down Mode (Sleep)

The Power-down mode is entered by executing a

SLEEP instruction.

If the Watchdog Ti mer is enabled:

• WDT will be cleared but keeps running

•PD

bit in the STATUS register is cleared

•TO

bit is set

• Oscillator driver is turned off

• I/O ports maintain the status they had before

Sleep was executed (driving high, low, or

high-impedance).

For lowest current consumption in this mode, all I/O

pins should be either at VDD, or VSS, with no external

circuitry drawing current from the I/O pin and the com-

parators and CVREF should be disabled. I/O pins that

are hi gh-impedanc e inputs s hould be pul led high or low

externally to avoid switching currents caused by float-

ing inputs. The T0CKI input should also be at VDD or

VSS for lowest current consumption. The contribution

from on-chip pu ll-u ps on GPIO should be consider ed.

The MCLR pin must be at a logic high level (VIHMC).

9.7.1 WAKE-UP FROM SLEEP

The devi ce can wa ke-up from Sleep through on e of the

following events:

1. External Reset input on MCLR pin

2. Watch dog Timer W ake-up (if WDT was enabled)

3. Interrupt from GP2/INT pin, GPIO change, or a

peripheral interrupt.

The first even t will cau se a device Reset. The two latt er

events are considered a continuation of program exe-

cution. The TO and PD bit s in the STATUS register can

be used to determine the cause of device Reset. The

PD bit, which is set on power-up , is cleared when Sleep

is invoked. TO bit is cl eared i f WDT W ak e-up o ccurred.

When the SLEEP instruction is being executed, the

next instruction (PC + 1) is pre-fetched. For the device

to wake -up throug h an inte rrupt eve nt, the co rrespond-

ing inte rrupt enabl e bit mu st be set (enabl ed). W ake-u p

is regardl es s of the st at e of the GIE bi t. If the G IE bit is

clear (disabled), the device continues execution at the

ins truction after the SLEEP instruction. If the GIE bit is

set (enabled) , th e device e x ecutes t he instructi on after

the SLEEP instruction, then branches to the interrupt

address (0004h). In cases where the execution of the

instr u cti o n f oll o w ing SLEEP is not desirable, the user

should hav e an NOP afte r the SLEEP instruction.

The WDT is cleared when the device wakes up from

Sleep, regardless of the source of wake-up.

FIGURE 9-13: WAKE-UP FROM SLEEP THROUGH INTERRUPT

Note: It should be noted that a Reset generated

by a WDT Time-out does not drive MCLR

pin low.

Note: If the global interrupts are disabled (GIE is

cleared ), but any in terru pt source h as both

its interrup t enable b it a nd the corres pon d-

ing interrupt flag bits set, the device will

immediately wake-up from Sleep. The

SLEEP instructi on is com pl ete ly exec ute d.

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

CLKOUT(4)

INT pin

INTF flag

(INTCON<1>)

GIE bit

(INTCON<7>)

INSTRUCTION FLOW

Instruction

Fetched

Instruction

Executed

PC PC + 1 PC + 2

Inst(PC) = Sleep

Inst(PC - 1)

Inst(PC + 1)

Sleep

Processor in

Sleep

Interrupt Latency

(Note 2)

Inst(PC + 2)

Inst(PC + 1)

Inst(0004h) Inst(0005h)

Inst(0004h)

Dummy cycle

PC + 2 0004h 0005h

Dummy cycle

TOST(2)

PC + 2

Note 1: XT, HS or LP Oscillator mode assume d.

2: TOST = 10 24TOSC (drawing not to scale). Approximately 1 s delay will be there for RC Osc mode. See Section 12 for wake-up from

Sleep delay in INTOSC mode.

3: GIE = 1 assumed. In this case after wake-up, the processor jumps to the interrupt routine. If GIE = 0, execution will continue in-line.

4: CLKOUT is not available in XT, HS, LP or EC Osc modes, but shown here for timing reference.

 2009 Microchip Technology Inc. DS41190F-page 69

PIC12F629/675

9.8 Code Protection

If the code protection bit(s) have not been

programmed, the on-chip program memory can be

read out for verificati on purp os es .

9.9 ID Locations

Four memory locations (2000h-2003h) are designated

as ID locations where the user can store checksum or

other code identification numbers. These locations are

not accessible during normal execution but are

readable and writable during Program/Verify. Only the

Least Significant 7 bits of the ID locations are used.

9.10 In-Ci rcuit Serial Programming

The PIC12F629/675 microcontrollers can be serially

progra mmed w hile in t he en d app licati on c ircuit. This is

simply don e with two lines fo r clock and da ta, and three

other lines for:

• power

• ground

• programming voltage

This allows customers to manufacture boards with

unprogrammed devices, and then program the

microcontroller just before shipping the product. This

also allows the most recent firmware or a custom

firmware to be programmed.

The device is placed into a Program/Verify mode by

holding the GP0 and GP1 pins low, while raising the

MCLR (VPP) pin from VIL to VIHH (see Programming

Specification). GP0 becomes the programming data

and GP1 becomes the programming clock. Both GP0

and GP1 are Schmitt Trigger inputs in this mode.

Aft er Reset, to pl ace the de vice in to Program ming/ Ver-

ify mod e, the PC is at loca tion 00h . A 6-bit c omma nd is

then supplied to the device. Depending on the com-

mand, 14-bits of program data are then supplied to or

from the device, depending on whether the command

was a l oad or a read. For complete d eta ils of serial p ro-

gramming, please refer to the Programming Specifica-

tions.

A typical In-Circuit Serial Programming connection is

shown in Figure 9-14.

FIGURE 9-14: TYPICAL IN-CIRCUIT

SERIAL PROGRAMMING

CONNECTION

9.11 In-Circuit Debugger

Since in-circuit debugging requires the loss of clock,

data and MCLR pins, MPLAB® ICD 2 development with

an 8-pin device is not practical. A special 14-pin

PIC12F675-ICD device is used with MPLAB ICD 2 to

provi de separate clock, da ta and MCLR pins and free s

all normally available pins to the user.

This special ICD device is mounted on the top of the

header and its signals are routed to the MPLAB ICD 2

connector. On the bottom of the header is an 8-pin

socket that plugs into the user’s target via the 8-pin

stand-off connector.

When the ICD pin on the PIC12F675-ICD device is

held low, the In-Circuit Debugger functionality is

enabled. This function allows simple debugging

functions when used with MPLAB ICD 2. When the

microcontroller has this feature enabled, some of the

resour ces are not availa ble for genera l use. Table 9-10

shows which features are consumed by the

background debugger:

TABLE 9-10: DEBUGGER RESOURCES

For more i nform at ion , se e 8-P in M PLAB IC D 2 H ead er

Information Sheet (DS51292) available on Microchip’s

web site (www.microchip.com).

Note: The entire data EEPROM and Flash

program memory will be erased when the

code protection is turned off. The INTOSC

calibration data is also erased. See

PIC12F629/675 Programming Specifica-

tion for more information.

I/O pins ICDCLK, ICDDATA

Stack 1 level

Prog ram Me mory Addre ss 0h must be NOP

300h-3FEh

External

Connector

Signals

To Normal

Connections

To Normal

Connections

PIC12F629/675

VDD

VSS

GP3/MCLR/VPP

GP1

GP0

+5V

VPP

CLK

Data I/O

VDD

PIC12F629/675

DS41190F-page 70  2009 Microchip Technology Inc.

NOTES:

 2009 Microchip Technology Inc. DS41190F-page 71

PIC12F629/675

10.0 INSTRUCTION SET SUMMARY

The PIC1 2F629/675 ins truction set is highly orthog onal

and is comprised of three basic categories:

• Byte-oriented operations

• Bit-oriented operations

• Literal and control operations

Each PIC12F629/675 instruction is a 14-bit word

divided into an opcode, which sp ec ifi es the ins truc tio n

type, an d one or mo re operands, which further specify

the operati on of the in struction . The format s for each of

the categories is presented in Figure 10-1, while the

various opcode fields are summarized in Table 10-1.

Table 10-2 lists the instructions recognized by the

MPASMTM assembler. A complete description of

each instruction is also available in the PIC® Mid-

Range Reference Manual ( DS3302 3).

For byte-oriented instructions, ‘f’ represents a file

designator. The file register designator specifies which

file register is to be used by the instruction.

The desti nation designator specifies where the result of

the operation is to be placed. If ‘d’ is zer o , th e r esu lt is

placed in the W re gister . If ‘d’ is one, the result is placed

in the file register specified in the instruction.

For bit-oriented instructions, ‘b’ represents a bit field

designator, which selects the bit affected by the

operatio n, whi le ‘f’ re pre sen t s t he ad dres s o f the f ile in

which the bit is located.

For literal and control operations, ‘k’ represents an

8-bit or 11-bit constant, or literal value.

One instr uction cycle co nsists of four os cillator periods ;

for an oscillator frequency o f 4 MHz, t his gives a normal

instruction execution time of 1 s. All instructions are

executed within a single instruction cycle, unless a

conditional test is true, or the program counter is

change d as a result of an instruction. When this occ urs,

the execution takes two instruction cycles, with the

second cycle executed as a NOP.

All instruction examples use the format ‘0xhh’ to

represent a hexadecimal number, where ‘h’ signifies

a hexadecimal digit.

10.1 READ-MODIFY-WRITE

OPERATIONS

Any instruction that specifies a file register as part of

the instruction performs a Read-Modify-Write (R-M-W)

operation. The register is read, the data is modified,

and the result is stored according to either the instruc-

tion, or the destination designator ‘d’. A read operation

is performed on a register even if the instruction writes

to that register.

For exam pl e, a CLRF GPIO in st ruc tion w i ll read GPIO ,

clear all the data bits, then write the result back to

GPIO. This example would have the unintended result

that the condition that sets the GPIF flag would be

cleared.

TABLE 10-1: OPCODE FIELD

DESCRIPTIONS

FIGURE 10-1: GENERAL FORMAT FOR

INSTRUCTIONS

Note: To maintain upward compatibility with

future products, do not use the OPTION

and TRISIO instructions.

Field Description

fRegister file address (0x00 to 0x7F)

WWorking register (accumulator)

bBit address within an 8-bit file register

kLiteral fie ld, constant data or label

xDon’t care location (= 0 or 1).

The assembler will generate code with x = 0.

It is the recommended form of use for

compatibility with all Microchip software tools.

dDestination select; d = 0: store result in W,

d = 1: store result in file register f.

Default is d = 1.

PC Program Counter

TO Time-out bit

PD Power-down bit

Byte-oriented file register op erations

13 8 7 6 0

d = 0 for destination W

OPCODE d f (FILE #)

d = 1 for destination f

f = 7-bit file register address

Bit-oriente d file register operations

13 10 9 7 6 0

OPCODE b (BIT # ) f (FIL E #)

b = 3-bit bit address

f = 7-bit file register address

Literal and control operations

13 8 7 0

OPCODE k (litera l )

k = 8-bit immediate value

13 11 10 0

OPCODE k (literal )

k = 11-bit immediate value

General

CALL and GOTO instructions only

PIC12F629/675

DS41190F-page 72  2009 Microchip Technology Inc.

TABLE 10-2: PIC12F629/675 INSTRUCTION SET

Mnemonic,

Operands Description Cycles 14-Bit Opcod e Status

Affected Notes

MSb LSb

BYTE-ORIENTED FILE REGISTER OPERATIONS

ADDWF

ANDWF

CLRF

CLRW

COMF

DECF

DECFSZ

INCF

INCFSZ

IORWF

MOVF

MOVWF

NOP

RLF

RRF

SUBWF

SWAPF

XORWF

f, d

Add W and f

AND W with f

Clear f

Clear W

Complement f

Decrement f

Decrement f, Skip if 0

Increment f

Increment f, Skip if 0

Inclusive OR W with f

Move f

Move W to f

No Operation

Rotate Left f through Carry

Rotate Right f through Carry

Subtract W from f

Swap nibbles in f

Exclusive OR W with f

1(2)

0111

0101

0001

1001

0011

1011

1010

1111

0100

1000

0000

1101

1100

0010

1110

0110

dfff

lfff

0xxx

dfff

lfff

0xx0

dfff

ffff

xxxx

ffff

0000

ffff

C,DC,Z

1,2

1,2,3

1,2

1,2,3

1,2

BIT-ORIENTED FILE REGISTER OPERATIONS

BCF

BSF

BTFSC

BTFSS

f, b

Bit Clear f

Bit Set f

Bit Test f, Skip if Clear

Bit Test f, Skip if Set

1 (2)

00bb

01bb

10bb

11bb

bfff

ffff

1,2

LITERAL AND CONTROL OPERATIONS

ADDLW

ANDLW

CALL

CLRWDT

GOTO

IORLW

MOVLW

RETFIE

RETLW

RETURN

SLEEP

SUBLW

XORLW

Add literal and W

AND literal with W

Call subroutine

Clear Watchdog Timer

Go to address

Inclusive OR literal with W

Move litera l to W

Return from interrupt

Return with literal in W

Return from Subroutine

Go into Standby mode

Subtract W from literal

Exclusive OR literal with W

111x

1001

0kkk

0000

1kkk

1000

00xx

0000

01xx

0000

110x

1010

kkkk

0110

kkkk

0000

kkkk

0000

0110

kkkk

0100

kkkk

1001

kkkk

1000

0011

kkkk

C,DC,Z

TO,PD

C,DC,Z

Note 1: When an I/O register is modified as a function of itself (e.g., MOVF GPIO, 1), the value used will be that value present

on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external

device, the data will be written back with a ‘0’.

2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if

assigned to the Timer0 module.

3: If Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is

executed as a NOP.

Note: Addit ional inform ation on the mi d-range instru ction set is available in the PIC ® Mid-Range MCU Family Ref-

erence Manual (DS33023).

 2009 Microchip Technology Inc. DS41190F-page 73

PIC12F629/675

10.2 Instruction Descriptions

ADDLW Add Literal and W

Syntax: [label] ADDLW k

Operands: 0  k  255

Operation: (W) + k  (W)

Status Affected: C, DC, Z

Description: The contents of the W register

are added to the eight-bit literal ‘k’

and the result is placed in the W

ADDWF Add W and f

Syntax: [label] ADDWF f,d

Operands: 0  f  127

d 

Operation: (W) + (f)  (destination)

Status Affected: C, DC, Z

Desc ription: Add the conten ts of the W regis ter

with register ‘f’. If ‘d’ is 0, the

result is stored in the W registe r . I f

‘d’ is 1, the resu lt is stored bac k in

ANDLW AND Literal with W

Syntax: [label] ANDLW k

Operands: 0  k  255

Operation: (W) .AND. (k)  (W)

Status Affected: Z

Description: The contents of W register are

AND’ed with the eight-bit literal

‘k’. The r esult is placed in the W

ANDWF AND W with f

Syntax: [label] ANDWF f,d

Operands: 0  f  127

d 

Operation: (W) .AND. (f)  (destination)

Status Affected: Z

Description: AND the W register with register

‘f’. If ‘d’ is 0, the result is stored in

the W register. If ‘d’ i s 1, the result

is stored back in register ‘f’.

BCF Bit Clear f

Syntax: [label] BCF f,b

Operands: 0  f  127

0  b  7

Operation: 0  (f<b>)

Status Af fe cte d: N o ne

Description: Bit ‘b’ in register ‘f’ is cleared.

BSF Bit Set f

Syntax: [label] BSF f,b

Operands: 0  f  127

0  b  7

Operation: 1  (f<b>)

Status Af fe cte d: N o ne

Description: Bit ‘b’ in register ‘f’ is set.

BTFSS Bit Test f, Skip if Set

Syntax: [label] BTFSS f,b

Operands: 0  f  127

0  b < 7

Operation: skip if (f<b>) = 1

Status Af fe cte d: None

Descr iption: If bit ‘b’ in r egister ‘f’ is ‘0’, the next

instructi on is ex ecuted.

If bit ‘b’ is ‘1’, then the next

instructi on is discard ed an d a NOP

is exec ute d in stead, m ak ing thi s a

2TCY instruction.

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BTFSC Bit Test, Skip if Clear

Syntax: [label] BTFSC f,b

Operands: 0  f  127

0  b  7

Operation: skip if (f<b>) = 0

Status Affected: None

Desc ription: If bit ‘b’ in register ‘f’ is ‘1’ , the next

instruction is executed.

If bit ‘b’, in register ‘f’, is ‘0’, the

next instruction is discarded, and

a NOP is e xecuted inst ead, making

this a 2TCY instruction.

CALL Call Subroutine

Syntax: [ label ] CALL k

Operands: 0  k  2047

Operation: (PC)+ 1 TOS,

k  PC<10:0>,

(PCLATH<4:3>)  PC<12:11>

Status Affected: None

Description: Call Subroutine. First, return

address (PC + 1) is pushed onto

the stack. The eleven-bit immedi-

ate a ddress is loade d into P C bit s

<10:0>. The upper bits of the PC

are load ed from PCLA TH. CALL is

a two-cycle instruction.

CLRF Clear f

Syntax: [label] CLRF f

Operands: 0  f  127

Operation: 00h  (f)

1  Z

Status Affected: Z

Desc ript ion : The conten t s of regi ste r ‘f’ are

cleared and the Z bit is set.

CLRW Clear W

Syntax: [ label ] CLRW

Operands: None

Operation: 00h  (W)

1  Z

Status Affected: Z

Description: W register is cleared. Zero bit (Z)

is set.

CLRWDT Clear Watchdog Timer

Syntax: [ label ] CLRWDT

Operands: None

Operation: 00h  WDT

0  WDT prescaler,

1  TO

1  PD

Status Af fe cte d: TO, PD

Description: CLRWDT instruction resets the

W atchdog T imer . It also resets the

prescaler of the WDT.

Status bits TO and PD are set.

COMF Complement f

Syntax: [ label ] COMF f,d

Operands: 0  f  127

d  [0,1]

Operation: (f)  (destination)

Status Af fe cte d: Z

Description: The contents of register ‘f’ are

complemented. If ‘d’ is 0, the

result is sto red in W. If ‘d’ is 1, the

result is stored back in register ‘f’.

DECF Decrement f

Syntax: [label] DECF f,d

Operands: 0  f  127

d  [0,1]

Operation: (f) - 1  (destination)

Status Af fe cte d: Z

Description: Decrement register ‘f’. If ‘d’ is 0,

the result is stored in the W

stored back in register ‘f’.

 2009 Microchip Technology Inc. DS41190F-page 75

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DECFSZ Decrement f, Skip if 0

Syntax: [ label ] DECFSZ f,d

Operands: 0  f  127

d  [0,1]

Operation: (f) - 1  (destination);

skip if result = 0

Status Affected: None

Description: The contents of register ‘f’ are

decremented. If ‘d’ is 0, the result

is placed in the W register. If ‘d’ is

1, the result is placed back in

If the result is 1, the next instruc-

tion is executed. If the result is 0,

then a NOP is executed instead,

making it a 2TCY instruction.

GOTO Unconditional Branch

Syntax: [ label ] GOTO k

Operands: 0  k  2047

Operation: k  PC<10:0>

PCLATH<4:3>  PC<12:11>

Status Affected: None

Description: GOTO is an unconditional branch.

The e le ven -bi t im me dia t e v al ue i s

loaded into PC bits <10:0>. The

upper bits of PC are loaded from

PCLATH<4:3>. GOTO is a two-

cycle instruction.

INCF Increment f

Syntax: [ label ] INCF f,d

Operands: 0  f  127

d  [0,1]

Operation: (f) + 1  (destination)

Status Affected: Z

Description: The contents of register ‘f’ are

incremented. If ‘d’ is 0, the result

is placed in the W register. If ‘d’ is

1, the result is placed back in

INCFSZ Increment f, Skip if 0

Syntax: [ label ] INCFSZ f,d

Operands: 0  f  127

d  [0,1]

Operation: (f) + 1  (destination),

skip if result = 0

Status Af fe cte d: None

Description: The contents of register ‘f’ are

incremented. If ‘d’ is 0, the result

is placed in the W register. If ‘d’ is

1, the result is placed back in

If the result is 1, the next instruc-

tion is executed. If the result is 0,

a NOP is e xecuted i nstead, making

it a 2TCY instruction.

IORLW Inclusive OR Literal with W

Syntax: [ label ] IORLW k

Operands: 0  k  255

Operation: (W) .OR. k  (W)

Status Af fe cte d: Z

Descr iption: The con tents of t he W register a re

OR’ed with the eight-bit literal ‘k’.

The result is placed in the W

IORWF Inclusive OR W with f

Syntax: [ label ] IORWF f,d

Operands: 0  f  127

d  [0,1]

Operation: (W) .OR. (f)  (destination)

Status Af fe cte d: Z

Description: Inclusive OR the W register with

placed in the W regi ster. If ‘d’ is 1,

the result is placed back in

PIC12F629/675

DS41190F-page 76  2009 Microchip Technology Inc.

RLF Rotate Left f through Carry

Syntax: [ label ] RLF f,d

Operands: 0  f  127

d  [0,1]

Operation: See description below

Status Affected: C

Description: The contents of register ‘f’ are rotated

one bit to the left through the Carry

Fla g. If ‘d’ is 0, the resu lt is pl aced in

the W register . If ‘d’ is 1, the re sult is

stored back in register ‘f’.

RETURN Return from Subroutine

Syntax: [ label ] RETURN

Operands: None

Operation: TOS  PC

Status Affected: None

Description: Return from subro utine. The st ack

is POPed an d the top o f the st a ck

(TOS) is loaded into the program

counter. This is a two-cycle

instruction.

RRF Rotate Right f through Carry

Syntax: [ label ] RRF f,d

Operands: 0  f  127

d  [0,1]

Operation: See description below

Status Affected: C

Desc ript ion : The con ten ts of registe r ‘f’ are

rotat ed one bit to the r ight throug h

the C arry Flag. If ‘d’ is 0, the result

is plac ed in the W regis ter. If ‘d’ is

1, the result is placed back in

SLEEP

Syntax: [ label ] SLEEP

Operands: None

Operation: 00h  WDT,

0  WDT prescaler,

1  TO,

0  PD

Status Af fe cte d: TO, PD

Descripti on: The power-down S tatus bit, PD is

cleared. Time-out Status bit, TO

is set. Watchdog Timer an d its

prescaler are cleare d.

The processor is put into Sleep

mode with th e oscillat or stopped.

SUBLW Subtract W from Literal

Syntax: [ label ] SUBLW k

Operands: 0 k 255

Operation: k - (W) W)

Status Affected: C, DC, Z

Description: The W register is subtracted (2’s

complement method) from the

eight-bit literal ‘k’. The result is

placed in the W register.

SUBWF Subtract W from f

Syntax: [ label ] SUBWF f,d

Operands: 0 f 127

d  [0,1]

Operation: (f) - (W) destination)

Status

Affected: C, DC, Z

Description: Subtract (2’s complement method)

W register from register ‘f’. If ‘d’ is

0, the result is stored in the W

stored back in register ‘f’.

 2009 Microchip Technology Inc. DS41190F-page 77

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SWAPF Swap Nibbles in f

Syntax: [ label ] SWAPF f,d

Operands: 0  f  127

d  [0,1]

Operation: (f<3:0>)  (destination<7:4>),

(f<7:4>)  (destination<3:0>)

Status Affected: None

Description: The upper and lower nibbles of

0, the result is placed in the W

placed in register ‘f’.

XORLW Exclusive OR Literal with W

Syntax: [label] XORLW k

Operands: 0 k 255

Operation: (W) .XOR. k W)

Status Affected: Z

Description: The contents of the W register

are XOR’ed with the eight-bit

literal ‘k’. The result is pla ced in

the W register.

XORWF Exclusive OR W with f

Syntax: [label] XORWF f,d

Operands: 0  f  127

d  [0,1]

Operation: (W) .XOR. (f) destination)

Status Af fe cte d: Z

Description: Exclusive OR the contents of the

W register with register ‘f’. If ‘d’ is

0, the result is stored in the W

stored back in register ‘f’.

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NOTES:

 2009 Microchip Technology Inc. DS41190F-page 79

PIC12F629/675

11.0 DEVELOPMENT SUPPORT

The PIC® microcontrollers and dsPIC® digital signal

controllers are supported with a full range of software

and hardware development tools:

• Integrated Development Environment

- MPLAB® IDE Software

• Compilers/Assemblers/Linkers

- MPLAB C Compiler for Various Device

Families

- HI-TECH C for Various Device Families

- MPASMTM Assembler

-MPLINK

TM Object Linker/

MPLIBTM Object Librarian

- MPLAB Assembler/Linker/Librarian for

Various Device Families

• Simulators

- MPLAB SIM Software Simulator

•Emulators

- MPLAB REAL ICE™ In-Circuit Emulator

• In-Circuit Debuggers

- MPLAB ICD 3

- PICkit™ 3 Debug Express

• Device Progra mmers

- PICkit™ 2 Programmer

- MPLAB PM3 Device Programmer

• Low-Cost Demonstration/Dev elopment Boards,

Evaluation Kits, and Starter Kits

11.1 MPLAB Integrated Development

Environment Software

The MPLAB IDE software brings an ease of software

development previously unseen in the 8/16/32-bit

microcontroller market. The MPLAB IDE is a Windows®

operating system-based application that contains:

• A single graphical interface to all debugging tools

- Simulator

- Programmer (sold separately)

- In-Circuit Emulator (sold separately)

- In-Circuit Deb ugger (so ld separately)

• A full-featured editor with color-coded context

• A multiple project manager

• Customizable data windows with direct edit of

contents

• High-level source code debugging

• Mouse over variable inspection

• Drag and drop variables from source to watch

windows

• Exten si ve on-l in e help

• Integration of select third party tools, such a s

IAR C Compilers

The MPLAB IDE allows you to:

• Edit your sou rce files ( eithe r C or assembly )

• One-tou ch compile o r assemble , and download to

emulator and simulator tools (automatically

updates all project information)

• Debug us ing :

- Sour ce files (C or assembly)

- Mixed C and assembly

- Machine code

MPLAB IDE supports multiple debugging tools in a

single development paradigm, from the cost-effective

simulators, through low-cost in-circuit debuggers, to

full-featured emulators. This eliminates the learning

curve when upgrading to tools with increased flexibility

and power.

PIC12F629/675

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11.2 MPLAB C Compilers for Various

Device Families

The MPLAB C Compiler code development systems

are complete ANSI C compilers for Microchip’s PIC18,

PIC24 and PIC32 families of microcontrollers and the

dsPIC30 and dsPIC33 families of digital signal control-

lers. These compilers provide powerful integration

capabilities, superior code optimization and ease of

use.

For easy source level debugging, the comp ilers provide

symbol info rmation tha t is optimized to the MPLAB IDE

debugger.

11.3 HI-TECH C for Vario us Device

Families

The HI-TECH C Compiler code development systems

are complete ANSI C compilers for Microchip’s PIC

family of microcontrollers and the dsPIC family of digital

signal controllers. These compilers provide powerful

integration capabilities, omniscient code generation

and ease of use.

For easy source level debugging, the comp ilers provide

symbol info rmation tha t is optimized to the MPLAB IDE

debugger.

The compilers include a macro assembler, linker, pre-

process or , and one-s tep driver , and can run on multipl e

platforms.

11.4 MPASM Assembler

The MPASM Assembler is a full-featured, universal

macro assembler for PIC10/12/16/18 MCUs.

The MPASM Assembler generates relocatable object

files fo r the MPLINK Ob ject Linker , Int el® standa rd HEX

files, MAP files to detail memory usage and symbol

reference, absolute LST files that contain source lines

and generated machine code and COFF files for

debugging.

The MPASM Assembler features include:

• Integration into MPLAB IDE projects

• User-defined macros to streamline

assembly co de

• Conditional assembly for multi-purpose

sour ce fil es

• Directives that allow complete control over the

assembly process

11.5 MPLINK Object Linker/

MPLIB Object Librarian

The MPLINK Object Linker combines relocatable

objects created by the MPASM Assembler and the

MPLA B C18 C Compiler. It can link relocatable objects

from precompiled libraries, using directives from a

linker script.

The MPLIB O bject Li brarian manage s the cre ation an d

modification of library files of precompiled code. When

a rout in e from a l ibra ry is c al led fro m a so urc e file, o nl y

the modules that contain that routine will be linked in

with the application. This allows large libraries to be

used efficiently in many different applications.

The object linker/library features include:

• Efficient linking of single libraries instead of many

smaller files

• Enhanced code maintainability by grouping

related modules together

• Flexible creation of libraries with easy module

listing, re placement, delet ion and extraction

11.6 MPLAB Assembler, Linker and

Librarian for Various Device

Families

MPLAB Assembler produces relocatable machine

code from symbolic assembly language for PIC24,

PIC32 and dsPIC devices. MPLAB C Compiler uses

the asse mbler to pro duce i ts o bje ct file . The ass embl er

generates relocatable object files that can then be

archived or lin ked with other relocata ble object files and

arch ives to c rea te an e xecu tabl e fil e. N otab le fe atu res

of the assembler include:

• Support for the entire device instruction set

• Support for fixed-point and floating-point data

• Command line interface

• Rich dire cti ve set

• Flexible macro language

• MPLAB IDE compatibility

 2009 Microchip Technology Inc. DS41190F-page 81

PIC12F629/675

11.7 MPLAB SIM Software Simulator

The MPLAB SIM Software Simulator allows code

development in a PC-hosted environment by simulat-

ing the PIC MCUs and dsPIC® DSCs on an instruction

level. On any given instruction, the data areas can be

examined or modified and stimuli can be applied from

a comprehensive stimulus controller. Registers can be

logged to files for further run-time analysis. The trace

buffer and logic analyzer display extend the power of

the simulator to record and track program execution,

actions on I/O, most periph erals and i nternal regi sters.

The MPLAB SIM Software Simulator fully supports

symbolic debugging using the MPLAB C Compilers,

and the MPASM and MPLAB Assemblers. The soft-

ware simulator offers the flexibility to develop and

debug code outside of the hardware laboratory envi-

ronment, making it an excellent, economical software

developm ent tool .

11.8 MPLAB REAL ICE In-Circuit

Emulator System

MPLAB REAL ICE In-Circuit Emulator System is

Microchip’s next generation high-speed emulator for

Microchip Flash DSC and MCU devices. It debugs and

programs PIC® Flash MCUs and dsPIC® Flash DSCs

with the easy-to-use, powerful graphical user interface of

the MPLAB Integrated D evelopment Environment (IDE),

included with each kit.

The emulator is connected to the design engineer’s PC

using a high-speed USB 2.0 interface and is connected

to the target with either a connector compatible with in-

circuit debugger systems (RJ11) or with the new high-

speed, noise tolerant, Low-Voltage Differential Signal

(LVDS) interconnection (CAT5).

The emulator is field upgrad able through future firmware

downloads in MPLAB IDE. In upcoming releases of

MPLAB IDE, new devices will be supported, and new

features will be added. MPLAB REAL ICE offers signifi-

cant advantages over competitive emulators including

low-cost, full-speed emulation, run-time variable

watches, trace analysis, complex breakpoints, a rugge-

dized probe interface and long (up to three meters) inter-

connection cables.

11.9 MPLAB ICD 3 In-Circuit Debugger

System

MPLAB ICD 3 In-Circuit Debugger System is Micro-

chip’s most cost effective high-speed hardware

debugger/programmer for Microchip Flash Digital Sig-

nal Controller (DSC) and microcontroller (MCU)

device s. It debugs and programs PIC® Flash microcon -

trollers and dsPIC® DSCs with the powerful, yet easy-

to-use graphical user interface of MPLAB Integrated

Development Environment (IDE).

The MPLAB ICD 3 In-Circuit Debugger probe is con-

nect ed to the desi gn enginee r’s PC us ing a high-s peed

USB 2.0 i nte rfac e a nd is co nnected to the target w ith a

connector compatible wi th the MPLAB ICD 2 or MPLAB

REAL ICE systems (RJ-11). MPLAB ICD 3 support s all

MPLAB ICD 2 headers.

11.10 PICkit 3 In-Circuit De bugger/

Programmer and

PICkit 3 Debug Express

The MPLAB PICkit 3 allows debugging and program-

ming of PIC® and dsPIC® Flash microcontrollers at a

most af fordable price point using the powerful graphical

user interface of the MPLAB Integrated Development

Environment (IDE). The MPLAB PICkit 3 is connected

to the design engineer’s PC using a full speed USB

interface and can be connected to the target via an

Microchip debug (RJ-11) connector (compatible with

MPLAB ICD 3 and MPLAB REAL ICE). The connector

uses two device I/O pins and the reset line to imple-

ment in-circuit debugging and In-Circuit Serial Pro-

gramming™.

The PICkit 3 Debug Express include the PICkit 3, demo

board and microcontroller , hookup cables and CDROM

with user’s guide, lessons, tutorial, compiler and

MPLAB IDE software.

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11.11 PICkit 2 Development

Programmer/Debugger and

PICkit 2 Debug Express

The P ICkit™ 2 Develo pment Program mer/Debu gger i s

a low-cost development tool with an easy to use inter-

face fo r programmin g and debu gging Micr ochip’s Flash

families of microcontrollers. The full featured

Windows® programming interface supports baseline

(PIC10F, PIC12F5xx, PIC16F5xx), midrange

(PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30,

dsPIC33, and PIC3 2 fam ilies o f 8 -bit, 16-b it, an d 3 2-b it

microcontrollers, and many Microchip Serial EEPROM

produ cts . With Mic rochip ’s power ful MPL AB Integrate d

Development Environment (IDE) the PICkit™ 2

enables in-circuit debugging on most PIC® microcon-

trollers. In-Circuit-Debugging runs, halts and single

steps the program while the PIC microcontroller is

embedded in the application. When halted at a break-

point, the file reg ist ers can be ex amin ed and m odifie d.

The PICkit 2 Debug Express inclu de the PICkit 2, demo

board and microcontroller , hookup cables and CDROM

with user’s guide, lessons, tutorial, compiler and

MPLAB IDE software.

11.12 MPLAB PM3 Device Programmer

The MPLAB PM3 Device Programmer is a universal,

CE compliant device programmer with programmable

voltage verification at VDDMIN and VDDMAX for

maximum reliability. It features a large LCD display

(128 x 64 ) for me nus an d err or messag es an d a modu-

lar, detachable socket assembly to support various

package type s. The ICSP™ cable assembly is included

as a standard item. In Stand-Alone mode, the MPLAB

PM3 Devic e Programmer can rea d, verify an d program

PIC devices without a PC connection. It can also set

code protection in this mode. The MPLAB PM3

connects to the host PC via an RS-232 or USB cable.

The MPL AB PM3 has high-spe ed comm unications and

optimized algorithms for quick programming of large

memory devices and inc orporates an MMC card for file

storage and data applications.

11.13 Demonstration/Development

Boards, Evaluation Kits, and

Starter Kits

A wide variety of demonstration, development and

evaluation boards for various PIC MCUs and dsPIC

DSCs allows quick application development on fully func-

tional systems. Most boards include prototyping areas for

adding custom circuitry and provide application firmware

and source code for examination and modification.

The board s suppo rt a variety of features, including LEDs,

temperature sensors, switches, speakers, RS-232

interfaces, LCD displays, potentiometers and additional

EEPROM memory .

The demonstration and development boards can be

used in teaching environments, for prototyping custom

circuits and for learning about various microcontroller

applications.

In addition to the PICDEM™ and dsPICDEM™ demon-

stration/development board series of circuits, Microchip

has a line of evaluation kits and demonstration software

for analog filter design, KEELOQ® security ICs, CAN,

IrDA®, PowerSmart battery management, SEEVAL®

evaluation system, Sigma-Delta ADC, flow rate

sensing, plus many more.

Also available are starter kits that contain everything

needed to experience t he specified d evice. This usually

includes a single application and debug capability, all

on one board.

Check the Microchip web page (www.microchip.com)

for the complete list of demonstration, development

and evaluation kits.

 2009 Microchip Technology Inc. DS41190F-page 83

PIC12F629/675

12.0 ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings†

Ambient temperature under bias...........................................................................................................-40 to +125°C

Storage temperature........................................................................................................................ -65°C to +150°C

Volta ge on VDD with respect to VSS ..................................................................................................... -0.3 to +6.5V

Volta ge on MCLR with respect to Vss ..................................................................................................-0.3 to +13.5V

Voltage on all other pins with respect to VSS ........................................................................... -0.3V to (VDD + 0.3V)

Total power dissipati on(1) ...............................................................................................................................800 mW

Maximum curr ent out of VSS pin .....................................................................................................................300 mA

Maximum curr ent into VDD pin........................................................................................................................250 mA

Input clamp current, IIK (VI < 0 or VI > VDD)20 mA

Output clamp current, IOK (Vo < 0 or Vo >VDD)20 mA

Maximum output current sunk by any I/O pin....................................................................................................25 mA

Maximum output current sourced by any I/O pin ..............................................................................................25 mA

Maximum current sunk by all GPIO................................................................................................................125 mA

Maximum current sourced all GPIO................................................................................................................125 mA

Note 1: Power diss ipation is calculat ed as follow s : PDIS = VDD x {IDD -  IOH} +  {(VDD-VOH) x IOH} + (VOl x IOL).

† NOTICE: Stresses above those listed under ‘Absolute Maximum Ratings’ may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions above those

indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for

extended periods may affect device reliability.

Note: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up.

Thus, a series res istor of 5 0-100  sho uld be us ed when ap plying a “low” le vel to the MCLR pin, rathe r than

pulling this pin d irect ly to VSS.

PIC12F629/675

DS41190F-page 84  2009 Microchip Technology Inc.

FIGURE 12-1: PIC12F629/6 75 WITH A/D DISABLED VOLTAGE-FREQUENCY GRAPH,

-40°C  TA  +125°C

FIGURE 12-2: PIC12F675 WITH A/D ENABLED VOLTAGE-FREQUENCY GRAPH,

-40°C  TA  +125°C

5.5

2.0

3.5

2.5

3.0

4.0

4.5

5.0

Frequency (MHz)

VDD

(Volts)

Note 1: The shaded region indicates the permissible combinations of voltage and frequency.

81612 2010

5.5

2.0

3.5

2.5

3.0

4.0

4.5

5.0

Frequency (MHz)

VDD

(Volts)

Note 1: The shaded region indicates the permissible combinations of voltage and frequency.

81612 2010

 2009 Microchip Technology Inc. DS41190F-page 85

PIC12F629/675

FIGURE 12-3: PIC12F675 WITH A/D ENABLED VOLTAGE-FREQUENCY GRAPH,

0°C  TA  +125°C

5.5

2.0

3.5

2.5

3.0

4.0

4.5

5.0

Frequency (MHz)

VDD

(Volts)

Note 1: The shaded region indicates the permissible combinations of voltage and frequency.

81612 2010

2.2

PIC12F629/675

DS41190F-page 86  2009 Microchip Technology Inc.

12.1 DC Characteristics: PIC12F629/675-I (Industrial), PIC12F629/675-E (Extended)

DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

Param

No. Sym Characteristic Min Typ† Max Units Conditions

D001

D001A

D001B

D001C

D001D

VDD Supply Voltage 2.0

2.2

2.5

3.0

4.5

—

5.5

FOSC < = 4 MHz:

PIC12F629/675 with A/D off

PIC12F675 with A/D on, 0°C to +125°C

PIC12F675 with A/D on, -40°C to +125°C

4 MHZ < FOSC < = 10 MH z

D002 VDR RAM Data Retention

Voltage(1) 1.5* — — V Device in Sleep mode

D003 VPOR VDD Start Voltage to

ensure int ernal Power-on

Reset signal

—VSS — V See section on Power-on Reset for details

D004 SVDD VDD Rise Rate to ensure

internal Power-on Reset

signal

0.05* — — V/ms See section on Power-on Reset for details

D005 VBOD —2.1— V

* These parameters are characterized but not tested.

† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.

 2009 Microchip Technology Inc. DS41190F-page 87

PIC12F629/675

12.2 DC Characteristics: PIC12F629/675-I (Industrial)

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40C  TA  +85C for industrial

Param

No. Device Char ac ter is tics Min Typ† Max Unit s Conditions

VDD Note

D010 Supply Current (IDD)—916A2.0FOSC = 32 kHz

LP Oscillator Mode

—1828 A3.0

—3554 A5.0

D011 — 110 150 A2.0F

OSC = 1 MHz

XT Oscillator Mode

— 190 280 A3.0

— 330 450 A5.0

D012 — 220 280 A2.0F

OSC = 4 MHz

XT Oscillator Mode

— 370 650 A3.0

— 0.6 1.4 mA 5.0

D013 — 70 110 A2.0F

OSC = 1 MHz

EC Osci ll ator Mo de

— 140 250 A3.0

— 260 390 A5.0

D014 — 180 250 A2.0F

OSC = 4 MHz

EC Osci ll ator Mo de

— 320 470 A3.0

— 580 850 A5.0

D015 — 340 450 A2.0F

OSC = 4 MHz

INTOSC Mode

— 500 700 A3.0

— 0.8 1.1 mA 5.0

D016 — 180 250 A2.0F

OSC = 4 MHz

EXTRC Mode

— 320 450 A3.0

— 580 800 A5.0

D017 — 2.1 2.95 mA 4.5 FOSC = 20 MHz

HS Osci llator Mode

— 2.4 3.0 mA 5.0

† D at a in “Typ” col umn is at 5.0 V, 25C unle ss otherwise s tated. Th es e p aramete r s are for de si gn g uid anc e

only and are not tested.

Note 1: The t est conditio ns for all I DD measuremen ts in Active Operatio n mode are: O SC1 = exter nal square w ave,

from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabl ed.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O

pin loa di ng and s w itchi ng rate, o sc ill ato r ty pe , internal c ode e xec ut ion p attern, and temperatu re also hav e

an impact on the current consumption.

PIC12F629/675

DS41190F-page 88  2009 Microchip Technology Inc.

12.3 DC Characteristics: PIC12F629/675-I (Industrial)

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40C  TA  +85C for industrial

Param

No. Device Char ac teristics Min Typ† Max Un its Conditions

VDD Note

D020 Power-down Base Current

(IPD) — 0.99 700 nA 2.0 WDT, BOD, Comparators, VREF,

and T1OSC disabled

— 1.2 770 nA 3.0

— 2.9 995 nA 5.0

D021 — 0.3 1.5 A 2.0 WDT Current(1)

—1.83.5A3.0

—8.417A5.0

D022 — 58 70 A 3.0 BOD Current(1)

— 109 130 A5.0

D023 — 3.3 6.5 A 2.0 Compara tor Curren t(1)

—6.18.5A3.0

—11.516 A5.0

D024 — 58 70 A2.0CVREF Current(1)

— 85 100 A3.0

— 138 160 A5.0

D025 — 4.0 6.5 A 2.0 T1 OSC Current(1)

—4.67.0A3.0

— 6.0 10.5 A5.0

D026 — 1.2 775 nA 3.0 A/D Current(1)

— 0.0022 1.0 A5.0

† Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this

peripheral is enabled. The peripheral  current can be determined by subtracting the base IDD or IPD

current from this limit. Max values should be used when calculating total current consumption.

2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is

measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.

 2009 Microchip Technology Inc. DS41190F-page 89

PIC12F629/675

12.4 DC Characteristics: PIC12F629/675-E (Extended)

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40C  TA  +125C for extended

Param

No. Device Char ac ter is tics Min Typ† Max Unit s Conditions

VDD Note

D010E Supply Current (IDD)—916A2.0FOSC = 32 kHz

LP Oscillator Mode

—1828 A3.0

—3554 A5.0

D011E — 110 150 A2.0F

OSC = 1 MHz

XT Oscillator Mode

— 190 280 A3.0

— 330 450 A5.0

D012E — 220 280 A2.0F

OSC = 4 MHz

XT Oscillator Mode

— 370 650 A3.0

— 0.6 1.4 mA 5.0

D013E — 70 110 A2.0F

OSC = 1 MHz

EC Osci ll ator Mo de

— 140 250 A3.0

— 260 390 A5.0

D014E — 180 250 A2.0F

OSC = 4 MHz

EC Osci ll ator Mo de

— 320 470 A3.0

— 580 850 A5.0

D015E — 340 450 A2.0F

OSC = 4 MHz

INTOSC Mode

— 500 780 A3.0

— 0.8 1.1 mA 5.0

D016E — 180 250 A2.0F

OSC = 4 MHz

EXTRC Mode

— 320 450 A3.0

— 580 800 A5.0

D017E — 2.1 2.95 mA 4.5 FOSC = 20 MHz

HS Osci llator Mode

— 2.4 3.0 mA 5.0

† D at a in “Typ” col umn is at 5.0 V, 25C unle ss otherwise s tated. Th es e p aramete r s are for de si gn g uid anc e

only and are not tested.

Note 1: The t est conditio ns for all I DD measuremen ts in Active Operatio n mode are: O SC1 = exter nal square w ave,

from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabl ed.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O

pin loa di ng and s w itchi ng rate, o sc ill ato r ty pe , internal c ode e xec ut ion p attern, and temperatu re also hav e

an impact on the current consumption.

PIC12F629/675

DS41190F-page 90  2009 Microchip Technology Inc.

12.5 DC Characteristics: PIC12F629/675-E (Extended)

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40C  TA  +125C for extended

Param

No. Device Characteristics Min Typ† M ax Units Conditions

VDD Note

D020E Power-down Ba se C urren t

(IPD)— 0.00099 3.5 A 2.0 WDT, BOD, Comparators, VREF,

and T1OSC disabled

— 0.0012 4.0 A3.0

— 0.0029 8.0 A5.0

D021E — 0.3 6.0 A 2.0 WDT Current(1)

—1.89.0A3.0

—8.420A5.0

D022E — 58 70 A 3.0 BOD Current (1)

— 109 130 A5.0

D023E — 3.3 10 A 2.0 Comparator Current(1)

—6.113A3.0

—11.524A5.0

D024E — 58 70 A2.0CVREF Current(1)

—85100A3.0

— 138 165 A5.0

D025E — 4.0 10 A 2.0 T1 OSC Current(1)

—4.612A3.0

—6.020A5.0

D026E — 0.0012 6.0 A 3.0 A/D Current(1)

— 0.0022 8.5 A5.0

† Data in “Typ” colum n is at 5.0 V, 25C unless oth erw is e s t ate d. These p a r ameters are for de si gn g uid an ce

only and are not tested.

Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this

peripheral is enabled. The peripheral  current can be determined by subtracting the base IDD or IPD

current from this limit. Max values should be used when calculating total current consumption.

2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is

measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.

 2009 Microchip Technology Inc. DS41190F-page 91

PIC12F629/675

12.6 DC Characteristics: PIC12F629/675-I (Industrial), PIC12F629/675-E (Extended)

DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

Param

No. Sym Characteristic Min Typ† Max Units Conditions

Input Low Voltage

VIL I/O ports

D030 with TTL buf fer VSS —0.8 V 4.5V  VDD  5.5V

D030A VSS —0.15 VDD VOtherwise

D031 with Schmitt Trigger buffer VSS —0.2 VDD V Entire range

D032 MCLR, OSC1 (RC mode) VSS —0.2 VDD V

D033 OSC1 (XT and LP modes) VSS —0.3 V (Note 1)

D033A OSC1 (HS mode) VSS —0.3 VDD V(Note 1)

Input High Voltage

VIH I/O ports —

D040

D040A with TTL buffer 2.0

(0.25 VDD+0.8) —

—VDD

VDD V

V4.5V  VDD 5.5V

otherwise

D041 with Schmitt Trigger buffer 0.8 VDD —VDD entire range

D042 MCLR 0.8 VDD —VDD V

D043 OSC1 (XT and LP modes) 1.6 —VDD V(Note 1)

D043A OSC1 (HS mode) 0.7 VDD —VDD V(Note 1)

D043B OSC1 (RC mode) 0.9 VDD —VDD V

D070 IPUR GPIO Weak Pull-up Current 50* 250 400* AVDD = 5.0V, VPIN = VSS

Input Leakage Current(3)

D060 IIL I/O ports —011AVSS VPIN VDD,

Pin at high-impedance

D060A Analog input s —011AVSS VPIN VDD

D060B VREF —011AVSS VPIN VDD

D061 MCLR(2) —015AVSS VPIN VDD

D063 OSC1 —015AVSS VPIN VDD, XT, HS and

LP osc configuration

Output Low Voltage

D080 VOL I/O ports ——

0.6 V IOL = 8.5 mA, VDD = 4.5V (Ind.)

D083 OSC2/CLKOUT (RC mode) ——

0.6 V IOL = 1.6 mA, VDD = 4.5V (Ind.)

IOL = 1.2 mA, VDD = 4.5V (Ext.)

Output High Voltage

D090 VOH I/O ports VDD - 0.7 ——VIOH = -3.0 mA, VDD = 4.5V (Ind.)

D092 OSC2/CLKOUT (RC mode) VDD - 0.7 ——VIOH = -1.3 mA, VDD = 4.5V (Ind.)

IOH = -1.0 mA, VDD = 4.5V (Ext.)

* T hese parameters are characterized but not test ed.

† Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use

an external clock in RC mode.

2: The leakage current on the MC LR pin is strong ly depend ent on the applied volt age level. The specified lev els

represent normal operating condi tions. Higher leaka ge current may be measu red at different input volt ages.

3: Negative current is defined as current sourced by the pin.

PIC12F629/675

DS41190F-page 92  2009 Microchip Technology Inc.

12.7 DC Characteristics: PIC12F629/675-I (Indust rial), PIC12F629/675-E (Extended) (Cont .)

DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

Param

No. Sym Characteristic Min Typ† Max Units Conditions

Capacitive Loading Specs

on Output Pins

D100 COSC2 OSC2 pin — — 15* pF In XT, HS and LP modes when

external clock is used to drive

OSC1

D101 CIO All I/O pins — — 50* pF

Data EEPROM Memory

D120 EDByte Endurance 100K 1M — E/W -40C  TA +85°C

D120A EDByte Endurance 10K 100K — E/W +85°C  TA +125°C

D121 VDRW VDD for Read/Write VMIN — 5.5 V Using EECON to read/write

VMIN = Minimum operating

voltage

D122 TDEW Erase/Write cycle time — 5 6 ms

D123 TRETD Characteristic Retention 40 — — Y ear Provided no other specifications

are violated

D124 TREF Number of Total Erase/Write

Cycle s befor e Refres h(1) 1M 10M — E/W -40C  TA +85°C

Program Flash Memory

D130 EPCell Endurance 10K 100K — E/W -40C  TA +85°C

D130A EDCell Endurance 1K 10K — E/W +85°C  TA +125°C

D131 VPR VDD for Read VMIN —5.5VVMIN = Minimum operating

voltage

D132 VPEW VDD for Erase/Write 4.5 — 5.5 V

D133 TPEW Erase/Write cycle time — 2 2.5 ms

D134 TRETD Characteristic Retention 40 — — Y ear Provided no other specifications

are violated

* These parameters are characterized but not tested.

† Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: See Section 8.5.1 “Using the Data EEPROM” for additional information.

 2009 Microchip Technology Inc. DS41190F-page 93

PIC12F629/675

12.8 TIMING PARAMETER SYMBOLOGY

The timing parameter symbols have been created with

one of the following formats:

FIGURE 12-4: LOA D CONDITIONS

1. TppS2ppS

2. TppS

TF Frequency T Time

Lowercase letters (pp) and their meanings:

cc CCP1 osc OSC1

ck CLKOUT rd RD

cs CS rw RD or WR

di SDI sc SCK

do SDO ss SS

dt Data in t0 T0CKI

io I/O port t1 T1CKI

mc MCLR wr WR

Uppercase letters and their mean ings:

SFFall PPeriod

HHigh RRise

I Invalid (High-Impedance) V Valid

L Low Z High-Impedance

Pin Pin

RL=464

CL= 50 pF for all pins

15 pF for OSC2 output

Load Cond ition 1 Load Condition 2

PIC12F629/675

DS41190F-page 94  2009 Microchip Technology Inc.

12.9 AC CHARACTERISTICS: PIC12F629/675 (INDUSTRIAL, EXTENDED)

FIGURE 12-5: EXT ERN AL CLOCK TIMING

TABLE 12-1: EXTERNAL CLOCK TIMING REQUIREMENTS

Param

No. Sym Characteristic Min Typ† Max Units Conditions

FOSC External CLKIN Frequency(1) DC — 37 kHz LP Osc mode

DC — 4 MHz XT mode

DC — 20 MHz HS mode

DC — 20 MHz EC mode

Oscilla tor Frequency(1) 5 — 37 kHz LP Osc mode

—4 —MHzINTOSC mode

DC — 4 MHz RC Osc mode

0.1 — 4 MHz XT Osc mode

1— 20MHzHS Osc mode

OSC External CLKIN Period(1) 27 — sLP Osc mode

50 — ns HS Osc mode

50 — ns EC Osc mode

250 — ns XT Osc mode

Oscillator Perio d (1) 27 200 sLP Osc mode

—250 — nsINTOSC mode

250 — — ns RC Osc mode

250 — 10,000 ns XT Osc mode

50 — 1,000 ns HS Osc mode

CY Instruction Cycle Time(1) 200 TCY DC ns TCY = 4/FOSC

3 TosL,

TosH External CLKIN (OSC1) High

External CLKIN Low 2* — — sLP oscillator, TOSC L/H duty cycle

20* — — ns HS oscillat or, TOSC L/H duty

cycle

100 * — — ns XT oscillator, TOSC L/H duty cycle

4TosR,

TosF External CLKIN Rise

External CLKIN Fall — — 50* ns LP oscillator

— — 25* ns XT oscillator

— — 15* ns HS oscilla tor

* These parameters are characterized but not tested.

† Data in “Typ” c olu mn is at 5 V, 25°C u nle ss oth erwis e s tated. These parameters are f or de si gn g uid anc e o nly

and are not tested .

Note1: Instruction cycle period (TCY) equals four time s the input oscil lat or tim e-b as e pe riod. All spe ci fie d values a r e

based on charac teriza tion da ta f or th at p articular oscil lator ty pe un der st anda rd opera ting c onditi ons with the

device e xecut ing co de. Exc eedin g t hese s peci fied li mit s ma y resu lt in a n u nst able o scil lator o peratio n an d/or

higher than exp ec ted cu rrent consumption. All de vi ce s are tes ted to operat e at “min” valu es w ith an ex ternal

clock applied to OSC1 pin. When an external clock input is used, the ‘max’ cycle time limit is “DC” (no clock)

for all devices.

OSC1

CLKOUT

Q4 Q1 Q2 Q3 Q4 Q1

23344

 2009 Microchip Technology Inc. DS41190F-page 95

PIC12F629/675

TABLE 12-2: PRECISION INTERNAL OSCILLATOR PARAMETERS

Param

No. Sym Characteristic Freq.

Tolerance Min Typ† Max Units Conditions

F10 FOSC Internal C alibrated

INTOSC Frequency

1 3.96 4.00 4.04 MHz VDD = 3.5V, 25C

2 3.92 4.00 4.08 MHz 2.5V VDD  5.5V

0C  TA  +85C

5 3.80 4.00 4.20 MHz 2.0V VDD  5.5V

-40C  TA  +85C (IND)

-40C  TA  +125C (EXT)

F14 TIOSCST Oscillator Wake-up from

Sleep start-up time* ——6 8sV

DD = 2.0V, -40C to +85C

——4 6sVDD = 3.0V, -40C to +85C

——3 5sVDD = 5.0V, -40C to +85C

* These parameters are characterized but not tested.

† Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance

only and are not tested.

PIC12F629/675

DS41190F-page 96  2009 Microchip Technology Inc.

FIGURE 12-6: CLKOUT AND I/O TIMING

TABLE 12-3: CLKOUT AND I/O TIMING REQUIREMENTS

Param

No. Sym Characteristic Min Typ† Max Units Conditions

10 TosH2ckL OSC1 to CLOUT — 75 200 ns (Note 1)

11 TosH2ckH OSC1 to CLOUT — 75 200 ns (Note 1)

12 TckR CLKOUT rise time — 35 100 ns (Note 1)

13 TckF CLKOUT fall time — 35 100 ns (Note 1)

14 TckL2ioV CLKOUT to Port out valid — — 20 ns (Note 1)

15 TioV2ckH Port in valid before CLKOUT T

OSC + 200

ns ——ns (Note 1)

16 TckH2ioI Port in hold after CLKOUT 0 — — ns (Note 1)

17 TosH2ioV OSC1 (Q1 cycle) to Port out vali d — 50 150 * ns

——300ns

18 TosH2ioI OSC1 (Q2 cycle) to Port input

invali d (I/O in hold time) 100 — — ns

19 TioV2osH Port input valid to OSC1

(I/O in setup tim e) 0——ns

20 TioR Port output rise tim e — 10 40 ns

21 TioF Port output fall time — 10 40 ns

22 Tinp INT pin high or low time 25 — — ns

23 Trbp GPIO chan ge INT hig h or low time TCY ——ns

* These parameters are characterized but not tested.

† Data in “Typ” column is at 5.0V, 25C unless otherwise stated.

Note 1: Me as urem en t s are t ak en in RC mo de wh ere CLKO U T outpu t is 4xTOSC.

OSC1

CLKOUT

I/O pi n

(Input)

I/O pin

(Output)

Q4 Q1 Q2 Q3

20, 21

19 18

Old Value New Value

 2009 Microchip Technology Inc. DS41190F-page 97

PIC12F629/675

FIGURE 12-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND

POWER-UP TIMER TIMING

FIGURE 12-8: BROW N-OUT DETECT TIMING AND CHARACTERISTICS

VDD

MCLR

Internal

POR

PWRT

Time-out

OSC

Time-out

Internal

Reset

Watchdog

Timer

Reset

I/O Pins

BVDD

Reset (due to BOD)

VDD

(Device in Brown-out Detect)

(Device not in Brown-out Detect)

72 ms time-out(1)

Note 1: 72 ms delay only if PWRTE bit in Configuration Word is programmed to ‘0’.

PIC12F629/675

DS41190F-page 98  2009 Microchip Technology Inc.

TABLE 12-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,

AND BROWN-OUT DETECT REQUIREMENTS

Param

No. Sym Characteristic Min Typ† Max Units Conditions

30 TMCLMCLR Pul se Width (l ow) 2

TBD —

TBD s

ms VDD = 5V, -40°C to +85°C

Extended temperature

31 TWDT Watch dog Timer Time-out

Period

(No Prescaler)

10 17

17 25

30 ms

ms VDD = 5V, -40°C to +85°C

Extended temperature

32 TOST Oscillation Start-up Timer

Period — 1024TOSC ——TOSC = OSC1 period

33* TPWRT Power-up Timer Period 28*

TBD 72

TBD 132*

TBD ms

ms VDD = 5V, -40°C to +85°C

Extended Temperature

34 TIOZ I/O High-impedance from

MCLR Low or Watchdog Timer

Reset

——2.0s

BVDD Brown-out Detect Voltage 2.025 — 2.175 V

Brown-o ut Hy steres is TBD — — —

35 TBOD Brown-out Detect Pulse Width 100* — — sVDD  BVDD (D005)

* These parameters are characterized but not tested.

† Data in “Typ” colum n is at 5V, 25°C unless oth erw ise stated. These para me ters are for des ign guid anc e onl y

and are not tested.

 2009 Microchip Technology Inc. DS41190F-page 99

PIC12F629/675

FIGURE 12-9: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS

TABLE 12-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS

Param

No. Sym Characteristic Min Typ† Max Units Conditions

40* Tt0H T 0CKI High Pulse Width No Prescaler 0.5 TCY + 20 — — ns

With Prescaler 10 — — ns

41* Tt0L T0CKI Low Pulse Width No Prescaler 0.5 TCY + 20 — — ns

With Prescaler 10 — — ns

42* Tt0P T0CKI Period Greater of:

20 or TCY + 40

— — ns N = prescale value

(2, 4 , ..., 256)

45* Tt1H T 1CKI High Time Synchr onous, No Prescaler 0.5 TCY + 20 — — ns

Synchronous,

with Prescaler 15 — — ns

Asynchronous 30 — — ns

46* Tt1L T1CKI Low T ime Synchronous, No Prescaler 0.5 TCY + 20 — — ns

Synchronous,

with Prescaler 15 — — ns

Asynchronous 30 — — ns

47* Tt1P T1CKI Input

Period Synchronous Greater of:

30 or TCY + 40

— — ns N = prescale value

(1, 2, 4, 8)

Asynchronous 60 — — ns

Ft1 Timer1 oscillator input frequency range

(oscillator enabled by setting bit T1OSCEN) DC — 200* kHz

48 TCKEZtmr1 Delay from external clock edge to timer increment 2 TOSC*—7

TOSC*—

* These parameters are characterized but not tested.

† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

T0CKI

T1CKI

45 46

47 48

TMR0 or

TMR1

PIC12F629/675

DS41190F-page 100  2009 Microchip Technology Inc.

TABLE 12-6: COMPARATOR SPECIFICATIONS

TABLE 12-7: COMPARATOR VOLTAGE REFERENCE SPECIFICATIONS

Comparator Specifications Standard Operating Conditions

-40°C to +125°C (unless otherwise stated)

Sym Characteristics Min Typ Max Units Comments

VOS Input Offset Voltage —  5.0  10 mV

VCM Input Common Mode Voltage 0 — V DD - 1.5 V

CMRR Common Mode Rejection Ratio +55* — — db

TRT Response Time(1) — 150 400* ns

TMC2COV Comparator Mode Change to

Output Valid —— 10* s

* These parameters are characterized but not tested.

Note1: Response time measured with one comparator input at (VDD - 1.5)/2 while the other input transitions from

VSS to VDD - 1.5V.

Voltage Referen ce Specifications Standard Operating Conditions

-40°C to +125°C (unless otherwise stated)

Sym Characteristics Min Typ Max Units Comments

Resolution —

—VDD/24*

VDD/32 —

—LSb

LSb Low Range (VRR = 1)

High Range (VRR = 0)

Absolute Accuracy —

——

— 1/2

1/2* LSb

LSb Low Range (VRR = 1)

High Range (VRR = 0)

Unit Resistor Value (R) — 2 k* — 

Settling Time(1) ——10*s

* These parameters are characterized but not tested.

Note1: Settling time measured while VRR = 1 and VR<3:0> transitions from 0000 to 1111.

 2009 Microchip Technology Inc. DS41190F-page 101

PIC12F629/675

TABLE 12-8: PIC12F675 A/D CONVERTER CHARACTERISTICS:

Param

No. Sym Characteristic Min Typ† Max Units Conditions

A01 NRResol utio n — — 10 bits bit

A02 EABS Total Absolute

Error* —— 1LSbVREF = 5.0V

A03 EIL Integral Error — — 1LSbVREF = 5.0V

A04 EDL Dif fere nti al Error — — 1 LSb No miss ing cod es to 10 bits

VREF = 5.0V

A05 EFS Full Scale Range 2.2* — 5.5* V

A06 EOFF Offset Error — — 1LSbVREF = 5.0V

A07 EGN Gain Error — — 1LSbVREF = 5.0V

A10 — Monotonicity — guaranteed(3) ——VSS  VAIN  VREF+

A20

A20A VREF Refe ren ce Volt age 2 .0

2.5 ——

VDD + 0.3 VAbsolute minimum to ensure 10-bit

accuracy

A21 VREF Reference V High

(VDD or VREF)VSS —VDD V

A25 VAIN Analog Input

Voltage VSS —VREF V

A30 ZAIN Recommended

Impedan ce of

Analog Voltage

Source

—— 10k

A50 IREF VREF Input

Current(2) 10

—

1000

A

During VAIN acquisition.

Based on dif fere nti al of VHOLD to VAIN.

During A/D conversion cycle.

* These para m eter s are characterized but not tested.

† Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: When A/D is off, it will not consume any current other than leakage current. The power-down current spec

includes any such leakage from the A/D module.

2: VREF current is from External VREF or VDD pin, whichever is selected as reference input.

3: The A/D con version resul t never decreases with an increa se in the input v oltage and has no m issing codes.

PIC12F629/675

DS41190F-page 102  2009 Microchip Technology Inc.

FIGURE 12-10: PIC12F675 A/D CONVERSION TIMIN G (NORMA L MODE)

TABLE 12-9: P IC12F675 A/D CONVERSION REQUIREMENTS

Param

No. Sym Characteristic Min Typ† Max Units Conditions

130 TAD A/D Clock Period 1.6 — — sTOSC based, VREF 3.0V

3.0* — — sTOSC based, VREF full range

130 TAD A/D Internal RC

Oscillator Perio d 3.0 * 6.0 9.0* sADCS<1:0> = 11 (RC mode)

At VDD = 2.5V

2.0* 4.0 6.0* sAt V

DD = 5.0V

131 TCNV Conversion Time

(not includin g

Acquisiti on Time)(1)

—11—TAD Set GO bit to new data in A/D result

132 TACQ Acquisition Time (Note 2)

11.5

—

s

s The minimum time is the amplifier

settling time. This may be used if th e

“new” inpu t voltag e has not chan ged

by more than 1 LSb (i.e., 4.1 mV @

4.096V) from the last sampled

volt a ge (as stored on CHOLD).

134 TGO Q4 to A/D Clock

Start —TOSC/2 — — If the A/ D clock sou rce is se lected as

RC, a time of TCY is added befor e

the A/D clock starts. This allows the

SLEEP instruction to be executed.

* These parameters are characterized but not tested.

† Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only

and are not tested.

Note 1: ADRES register may be read on the following TCY cycle.

2: See Section 7 .1 “A/D Configuration and Operation” for minimum conditions.

131

130

132

BSF ADCON0, GO

A/D CLK

A/D DATA

ADRES

ADIF

SAMPLE

OLD_DATA

SAMPLING STOPPED

DONE

NEW_DATA

987 3210

Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the

SLEEP instruction to be executed.

1 TCY

134 (TOSC/2)(1)

1 TCY

 2009 Microchip Technology Inc. DS41190F-page 103

PIC12F629/675

FIGURE 12-11: PIC12F675 A/D CONVERSION TIMING (SLEEP MODE)

TABLE 12-10: PIC12F675 A/D CONVERSION REQUIREMENTS (SLEEP MODE)

Param

No. Sym Characteristic Min Typ† Max Units Conditions

130 TAD A/D Clock Period 1.6 — — sVREF 3.0V

3.0* — — sVREF full range

130 TAD A/D Internal RC

Osci lla tor Perio d 3.0* 6.0 9.0* sADCS<1:0> = 11 (RC mode)

At VDD = 2. 5V

2.0* 4.0 6.0* sAt VDD = 5.0V

131 TCNV Conversion Time

(not including

Acquisition T ime)(1)

—11—T

132 TACQ Acqu is iti on Time (Note 2)

11.5

—

s

s The minimum time is the amplifier

settling time. This may be used if

the “new” input voltage has not

change d by more than 1 LSb (i.e .,

4.1 mV @ 4.096V) from the last

sampled voltage (as stored on

CHOLD).

134 TGO Q4 to A/D Clock

Start —TOSC/2 + TCY — — If the A/D clo ck s ou r ce i s se lec t ed

as RC, a time of TCY is added

before the A/D clock starts. This

allows the SLEEP instruction to b e

executed.

* These parameters are characterized but not tested.

† Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: ADRES register may be read on the following TCY cycle.

2: See Section 7.1 “A/D Configuration and Operation” for minimum conditions.

131

130

BSF ADCON0, GO

A/D CLK

A/D DATA

ADRES

ADIF

SAMPLE

OLD_DATA

SAMP LING STOPPED

DONE

NEW_DATA

9 7 3210

Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the

SLEEP instruction to be executed.

134

132

1 TCY

(TOSC/2 + TCY)(1)

1 TCY

PIC12F629/675

DS41190F-page 104  2009 Microchip Technology Inc.

NOTES:

 2009 Microchip Technology Inc. DS41190F-page 105

PIC12F629/675

13.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES

The graphs and tables provided in this section are for design guidance and are not tested.

In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD

range). This is for information only and devices are ensured to operate properly only within the specified range.

The data presented in this section is a statistical summary of data collected on units from different lots over a period

of time and matrix samples. “Typical” represents the mean of the distribution at 25°C. “Max” or “min” represents

(mean + 3) or (mean - 3) respectively, where  is standard deviation, over the whole temperature range.

FIGURE 13-1: TYPICAL IPD vs. VDD OVER TEMP (-40°C TO +25°C)

FIGURE 13-2: TYPICAL IPD vs. VDD OVER TEMP (+85°C)

Typical Baselin e IPD

0.0E+00

1.0E-09

2.0E-09

3.0E-09

4.0E-09

5.0E-09

6.0E-09

2 2.5 3 3.5 4 4.5 5 5.5

(

)

PD (A)

-40

Typical Baselin e IPD

0.0E+00

5.0E-08

1.0E-07

1.5E-07

2.0E-07

2.5E-07

3.0E-07

3.5E-07

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

PD (A)

PIC12F629/675

DS41190F-page 106  2009 Microchip Technology Inc.

FIGURE 13-3: TYPICAL IPD vs. VDD OVER TEMP (+125°C)

FIGURE 13-4: MAXIMUM IPD vs. VDD OVER TEMP (-40°C TO +25°C)

Typical Baseline IPD

0.0E+00

5.0E-07

1.0E-06

1.5E-06

2.0E-06

2.5E-06

3.0E-06

3.5E-06

4.0E-06

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

PD (A)

125

Maximum Baseline I

0.0E+00

1.0E-08

2.0E-08

3.0E-08

4.0E-08

5.0E-08

6.0E-08

7.0E-08

8.0E-08

9.0E-08

1.0E-07

22.533.544.555.5

VDD (V)

IPD

(

)

-40

 2009 Microchip Technology Inc. DS41190F-page 107

PIC12F629/675

FIGURE 13-5: MAXI MU M IPD vs. VDD OVER TEMP (+85°C)

FIGURE 13-6: MAXI MU M IPD vs. VDD OVER TEMP (+125°C)

Maximum Baseline IPD

0.0E+00

1.0E-07

2.0E-07

3.0E-07

4.0E-07

5.0E-07

6.0E-07

7.0E-07

8.0E-07

9.0E-07

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

PD (A)

Maximum Baseline IPD

0.0E+00

1.0E-06

2.0E-06

3.0E-06

4.0E-06

5.0E-06

6.0E-06

7.0E-06

8.0E-06

9.0E-06

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

PD (A)

125

PIC12F629/675

DS41190F-page 108  2009 Microchip Technology Inc.

FIGURE 13-7: TYPICAL IPD WITH BOD ENABLED vs. VDD OVER TEMP (-40°C TO +125°C)

FIGURE 13-8: TYPICAL IPD WITH CMP ENABLED vs. VDD OVER TEMP ( -40°C TO +125°C)

Typical BOD I

100

110

120

130

3 3.5 4 4.5 5 5.5

(V)

PD (uA)

-40

125

Typical Comparator IPD

0.0E+00

2.0E-06

4.0E-06

6.0E-06

8.0E-06

1.0E-05

1.2E-05

1.4E-05

1.6E-05

1.8E-05

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

(V)

PD (A)

-40

125

 2009 Microchip Technology Inc. DS41190F-page 109

PIC12F629/675

FIGURE 13-9: TYPICAL IPD WITH A/D ENABLE D vs. VDD OVER TEMP (-40°C TO +25°C)

FIGURE 13-10: TYPICAL IPD WITH A/D ENABLED vs. VDD OVER TEMP (+85°C)

Typical A/D I

0.0E+00

5.0E-10

1.0E-09

1.5E-09

2.0E-09

2.5E-09

3.0E-09

3.5E-09

4.0E-09

4.5E-09

5.0E-09

2 2.5 3 3.5 4 4.5 5 5.5

(V)

PD (A)

-40

Typical A/D IPD

0.0E+00

5.0E-08

1.0E-07

1.5E-07

2.0E-07

2.5E-07

3.0E-07

3.5E-07

2 2.5 3 3.5 4 4.5 5 5.5

(V)

IPD

(

)

PIC12F629/675

DS41190F-page 110  2009 Microchip Technology Inc.

FIGURE 13-11: TYPICAL IPD WITH A/D ENABLED vs. VDD OVER TEMP (+125°C)

FIGURE 13-12: TYPICAL IPD WITH T1 OSC ENABLED vs. VDD OVER TEMP (-40°C TO +125°C),

32 kHZ, C1 AND C2=50 pF)

Typical A/D IPD

0.0E+00

5.0E-07

1.0E-06

1.5E-06

2.0E-06

2.5E-06

3.0E-06

3.5E-06

22.533.544.555.5

(V)

PD (A)

125

Typical T1 IPD

0.00E+00

2.00E-06

4.00E-06

6.00E-06

8.00E-06

1.00E-05

1.20E-05

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

(V)

PD (A)

-40

125

 2009 Microchip Technology Inc. DS41190F-page 111

PIC12F629/675

FIGURE 13-13: TYPICAL IPD WITH CVREF ENABLED vs. VDD OVER TEMP (-40°C TO +125°C)

FIGURE 13-14: TYPICAL IPD WITH WDT ENABLED vs. VDD OVER TEMP (-40°C TO +125°C)

Typical C

REF

100

120

140

160

2 2.5 3 3.5 4 4.5 5 5.5

(V)

PD (uA)

-40

125

Typical WDT I

2 2.5 3 3.5 4 4.5 5 5.5

(

)

PD (uA)

-40

125

PIC12F629/675

DS41190F-page 112  2009 Microchip Technology Inc.

FIGURE 13-15: MAXIMUM AND MINIMUMINTOSC FREQ vs. TEMPERATURE WITH 0.1F AND

0.01F DECOUPLING (VDD = 3.5V)

FIGURE 13-16: MAXIMUM AND MINIMUMINTOSC FREQ vs. VDD WITH 0.1F AND 0.01F

DECOUPLING (+25°C)

Internal Oscillator

Frequency vs Temperature

3.80E+06

3.85E+06

3.90E+06

3.95E+06

4.00E+06

4.05E+06

4.10E+06

4.15E+06

4.20E+06

-40°C 0°C 25°C 85°C 125°C

Temperature (°C)

Frequency (Hz)

-3sigma

average

+3sigma

Internal Oscillator

Frequency vs VDD

3.80E+06

3.85E+06

3.90E+06

3.95E+06

4.00E+06

4.05E+06

4.10E+06

4.15E+06

4.20E+06

2.0V 2.5V 3.0V 3.5V 4.0V 4.5V 5.0V 5.5V

VDD (V)

Fre

uenc

(

)

-3sigma

average

+3sigma

 2009 Microchip Technology Inc. DS41190F-page 113

PIC12F629/675

FIGURE 13-17: TYPICAL WDT PERIOD vs. VDD (-40C TO +125C)

WDT Time-o u t

2 2.5 3 3.5 4 4.5 5 5.5

(V)

Time (

mS)

-40

125

PIC12F629/675

DS41190F-page 114  2009 Microchip Technology Inc.

NOTES:

 2009 Microchip Technology Inc. DS41190F-page 115

PIC12F629/675

14.0 PACKAGING INFORMATION

14.1 Packa ge Mark ing Information

XXXXXNNN

8-Lead PDIP (Skinny DIP) Example

XXXXXXXX

YYWW /017

12F629-I

0215

XXXXYYWW

8-Lead SOIC

XXXXXXXX

NNN /0215

Example

12F629-E

017

8-Lead DFN-S

XXXXXXX

NNN

XXXXXXX

XXYYWW -E/021

017

12F629

021 5

Example

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanu mer ic trac eab il ity code

Pb-free JEDEC designator for Matte Tin (Sn)

*This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the ev ent the fu ll Mic rochip part nu mber ca nnot be m arked o n one line , it will

be carried over to the next line, thus limiting the number of available

charact ers for custom er-specific inform ati on .

XXXXXX

8-Lead DFN (4x4 mm)

YYWW

NNN

Example

XXXXXX XXXXXX

0610

017

XXXX

PIC12F629/675

DS41190F-page 116  2009 Microchip Technology Inc.

14.2 Package Details

The following sections give the technical details of the packages.





  !"#$%&"' ()"&'"!&)&#*&&&#

 +%&,&!&

- '!!#.#&"#'#%!&"!!#%!&"!!!&$#/!#

 '!#&.0

1,21!'!&$& "!**&"&&!

 3&'!&"&4#*!(!!&4%&&#&

&&255***''54

6&! 7,8.

'!9'&! 7 7: ;

7"')%! 7 <

&  1,

&&  = = 

##44!!   - 

1!&&   = =

"#&"#>#& .  - -

##4>#& .   <

: 9&  -< -? 

&& 9  - 

9#4!!  <  

69#>#& )  ? 

9*9#>#& )  < 

: *+ 1 = = -

NOTE 1

123

  * ,<1

 2009 Microchip Technology Inc. DS41190F-page 117

PIC12F629/675

 ! ""#$%& !'



  !"#$%&"' ()"&'"!&)&#*&&&#

 +%&,&!&

- '!!#.#&"#'#%!&"!!#%!&"!!!&$#''!#

 '!#&.0

1,2 1!'!&$& "!**&"&&!

.32 %'!("!"*&"&&(%%'&"!!

&&255***''54

6&! 99..

'!9'&! 7 7: ;

7"')%! 7 <

&  1,

: 8&  = = 

##44!!   = =

&#%%+  = 

: >#& . ?1,

##4>#& . -1,

: 9&  1,

,'%@&A   = 

3&9& 9  = 

3&& 9 .3

3& IB = <B

9#4!!   = 

9#>#& ) - = 

#%& DB = B

#%&1&&' EB = B

NOTE 1

12 3

  * ,1

PIC12F629/675

DS41190F-page 118  2009 Microchip Technology Inc.

 ! ""#$%& !'

&&255***''54

 2009 Microchip Technology Inc. DS41190F-page 119

PIC12F629/675

($)*+(,-.( 





  !"#$%&"' ()"&'"!&)&#*&&&#

 4' '$!#&)!&#!

- 4!!*!"&#

 '!#&.0

1,2 1!'!&$& "!**&"&&!

.32 %'!("!"*&"&&(%%'&"!!

&&255***''54

6&! 99..

'!9'&! 7 7: ;

7"')%! 7 <

&  1,

: 8&  < < 

&#%%    

,&&4!! - .3

: 9&  1,

: >#& . ?1,

.$!##9&  -  

.$!##>#& .  - 

,&&>#& ) -  <

,&&9& 9  ? 

,&&&.$!## C  = =

NOTE 2

NOTE 1 12

EXPOSED PAD

NOTE 1

BOTTOM VIEW

TOP VIEW

  * ,1

PIC12F629/675

DS41190F-page 120  2009 Microchip Technology Inc.

&&255***''54

 2009 Microchip Technology Inc. DS41190F-page 121

PIC12F629/675

8-Lead Plastic Dual Flat, No Lead Package (MD) – 4x4x0.9 mm Body [DFN]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Microchip Technology Drawing C04-131E Sheet 1 of 2

PIC12F629/675

DS41190F-page 122  2009 Microchip Technology Inc.

8-Lead Plastic Dual Flat, No Lead Package (MD) – 4x4x0.9 mm Body [DFN]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Microchip Technology Drawing C04-131E Sheet 2 of 2

 2009 Microchip Technology Inc. DS41190F-page 123

PIC12F629/675

($)*+D/-/-%&(

&&255***''54

PIC12F629/675

DS41190F-page 124  2009 Microchip Technology Inc.

NOTES:

 2009 Microchip Technology Inc. DS41190F-page 125

PIC12F629/675

APPENDIX A: DATA SHEET

REVISION HISTORY

Revision A

This is a new data sheet.

Revision B

Added characterization graphs.

Updated specifications.

Added notes to indicate Microchip programmers

maintain all Calibration bits to factory settings and the

PIC12F675 ANSEL register must be initialized to

configure pins as digital I/O.

Updated MLF-S package name to DFN-S.

Revision C

Revision D (01/2007)

Updated Package Drawings; Replace PICmicro with

PIC; Revised Product ID example (b).

Revision E (03/2007)

Replaced Package Drawings (Rev. AM); Replaced

Development Support Section.

Revision F (09/2009)

Update d Registers to new f ormat; Added in formation to

the “Package Marking Information” (8-Lead DFN) and

“Package Detai ls” sect ions (8-L ead Dual Fl at, No Lead

Package (MD) 4X4X0. 9 mm Body (DFN)); Ad ded Land

Patterns for SOIC (SN) and DFN-S (MF) packages;

Updated Register 3-2; Added MD Package to the

Product identification System chapter; Other minor

corrections.

APPENDIX B: DEVICE

DIFFERENCES

The differences between the PIC12F629/675 devices

listed in this data sheet are shown in Table B-1.

TABLE B-1: DEVICE DIFFERENCES

Feature PIC12F629 PIC12F675

A/D No Yes

PIC12F629/675

DS41190F-page 126  2009 Microchip Technology Inc.

APPENDIX C: DEVICE MIGRATIONS

This section is intended to describe the functional and

electrical specification differences when migrating

between functionally similar devices (such as from a

PIC16C74A to a PIC16C74B).

Not Applicable

APPENDIX D: MIGRATING FROM

OTHER PIC®

DEVICES

This discusses some of the issues in migrating from

other PIC dev ices to the PIC12 F6XX famil y of devices .

D.1 PIC12C67X to PIC12F6XX

TABLE 1: FEATURE COMPARISON

Feature PIC12C67X PIC12F6XX

Max Operating Speed 10 MHz 20 MHz

Max Program Memory 2048 bytes 1024 bytes

A/D Resolution 8-bit 10-bit

Data EEPROM 16 bytes 64 bytes

Oscillator Modes 5 8

Brown-out Detect N Y

Internal Pull -up s GP0/1/3 GP0/1/2/4/5

Interrupt-on-change GP0/1/3 GP0/1/2/3/4/5

Comparator N Y

Note: This device has been designed to perform

to the parameters of its data sheet. It has

been tested to an electrical specification

designed to determine its conformance

with these parameters. Due to process

differences in the manufacture of this

device, this device may have different

performan ce c harac teristi cs than it s ea rlier

version. These differences may cause this

device to perform differently in your

application than the earlier version of this

device.

 2009 Microchip Technology Inc. DS41190F-page 127

PIC12F629/675

INDEX

A/D......................................................................................43

Acquisition Requirements...........................................47

Block Dia g r a m............... ............... .......... ........... ..........43

Calculating Acquisition Time .......................................47

Configuration and Operation..................... .... . .. .. .... .. ...43

Effects of a Reset........................................................48

Internal Sampling Switch (Rss) Impedance.. . .. .. .. .. .. ...47

Operation During Sleep ..............................................48

PIC12F675 Converter Characteristics......................101

Source Impedance......................................................47

Summary o f Re g isters ........ ........... .......... ........... ........4 8

Absolute Maximum Ratings................................................83

AC Characteristics

Industrial and Extended......... .. . .. .... .. .... .... .. ................94

Additional Pin Functions .....................................................21

Interrupt-on-Change....................................................23

Weak Pull-up...............................................................21

Analog Input Connection Considerations............ ................40

Analog-to-Digital Converter. See A/ D

Assembler

MPASM Assembler.....................................................80

Block Diagram

TMR0/WDT Prescaler.................................................29

Block Diagrams

Analog Input Mode............. .. .... . .. .. .... .... .. .... ................40

Analog Input Model...... .... .. .... ................... .. ................47

Com p ar a tor Output....... .......... ........... .......... ........... ....4 0

Comparator Voltage Reference ..................................41

GP0 and GP1 Pins......................................................24

GP2.............................................................................25

GP3.............................................................................25

GP4.............................................................................26

GP5.............................................................................26

On-C h i p R es e t Circ u it... ...... ........... .......... ........... ........5 8

RC Oscillator Mode.....................................................57

Timer1.........................................................................32

Watchdog Timer..........................................................68

Brown-out

Asso ciated Reg i st e rs.... ...... ........... .............. ........... ....6 1

Brown-out Detect (BOD).....................................................60

Brown-out Detect Timing and Characteristics.....................97

C Compiler s

MPLAB C18. ........... .......... ........... .......... ........... ..........80

Calibrated Internal RC Frequencies.............. .. .... .. ............. .95

CLKOUT .............................................................................57

Code Examples

Changing Prescaler ....................................................31

Dat a E EPROM Read.. ...... ........... .......... ........... ..........51

Dat a E EPROM W r ite........ ........... ...... .......... ........... ....5 1

Initializing GPIO..........................................................21

Saving ST ATUS a n d W Re g isters in RAM .................67

Write Verify.................................................................51

Code Protection ........ .. . .. .. .... .. .. .... .. .. . .. .. .... .. .. .... .. .. . .. .. .... .. .. .70

Comparator.........................................................................37

Asso ciated Reg i st e rs........ .. ........... .............. ........... ....42

Configuration...............................................................39

Effects of a RESET.....................................................41

I/O Operating Modes...................................................39

Interrupts.....................................................................42

Operation....................................................................38

Operation During SLEEP............................................41

Output......................................................................... 40

Reference................................................................... 41

Response Time .......................................................... 41

Compa r a tor Spe c ificatio n s.... ........... ...... ........... ...... .......... 10 0

Comparator Voltage Reference Specific ations................. 100

Configuration Bits............................................................... 54

Configuring the Voltage Reference..................................... 41

Crystal Operation................................................................ 56

Customer Change Notification Service............................. 131

Cus to mer Notifica tio n Se r vice................... ....... .......... ...... 131

Customer Support............................................................. 131

Data EEPROM Memory

Asso ciated Reg i st e rs/Bits.............. ........... .......... ........ 52

Code Protection. .. .. .. .... .. .. . .. .. .... .. .. .... .. .. . .. .. .... .. .. .... .. .. . 52

EEADR Register......................................................... 49

EECO N 1 R eg iste r .......... ........... .......... ........... ............ 49

EECO N 2 R eg iste r .......... ........... .......... ........... ............ 49

EEDATA Register....................................................... 49

Data Memory Organization................................................... 9

DC Characteristi cs

Extended and Industrial.................. .. .... . .. .... .. .... .... .. ... 91

Industrial..................................................................... 86

Development Support......................................................... 79

Device Differences............................................................ 125

Device Migrations............................................................. 126

Device Overview................................................................... 7

EEPROM Data Memory

Reading...................................................................... 51

Spu ri o us Write........ ........... ...... .......... ........... .......... .... 51

Write Verify................................................................. 51

Writing ........................................................................ 51

Electrical Specifications...................................................... 83

Errata.................................................................................... 5

Firmware Instructions ......................................................... 71

General Purpose Register File ............................................. 9

GPIO

Asso ciated Reg i st e rs............... .......... ........... .......... .... 27

GPIO Port........ ........... .......... ........... .......... ........... .......... .... 21

GPIO, TRISIO Registers..................................................... 21

ID Locations........................................................................ 70

In-Circuit Debugger.. .... .. .. .... .. .. . .. .. .... .. .. .... .. .. . .. .. .... .. .. .... .. .. . 70

In-Circuit Serial Programming............................................. 70

Indirect Addressing, INDF and FSR Registers........ .. .. .. .. .. . 20

Instruction Format............................................................... 71

Instruction Set..................................................................... 71

ADDLW....................................................................... 73

ADDWF ...................................................................... 73

ANDLW....................................................................... 73

ANDWF ...................................................................... 73

BCF ............................................................................ 73

BSF............................................................................. 73

BTFSC........................................................................ 74

BTFSS........................................................................ 73

CALL........................................................................... 74

CLRF.......................................................................... 74

CLRW......................................................................... 74

CLRWDT.................................................................... 75

COMF......................................................................... 75

DECF.......................................................................... 75

PIC12F629/675

DS41190F-page 128  2009 Microchip Technol ogy Inc.

DECFSZ......................................................................75

GOTO .........................................................................75

INCF............................................................................75

INCFSZ.......................................................................76

IORLW ........................................................................76

IORWF........................................................................76

RETURN.....................................................................77

RLF.............................................................................77

RRF.............................................................................77

SLEEP ........................................................................77

SUBLW.......................................................................77

SUBWF.......................................................................77

SWAPF.......................................................................78

XORLW.......................................................................78

XORWF.......................................................................78

Summary Ta b le...... ....... .......... ........... .......... ...... .........72

Internal 4 MHz Oscillator.....................................................57

Internal Sampling Switch (Rss) Impedance.... .... .. .. .. .. .. . .. .. .47

Inte r n e t Ad d r e ss............. ........... .......... ........... .......... .........131

Interrupts.............................................................................64

A/D C on v e r te r........ ....... .......... ........... .......... ........... ....66

Comparator.................................................................66

Context Saving ............................................................67

GP2/INT......................................................................66

GPIO...........................................................................66

Summary o f Re g isters .... .. .............. ........... .......... .......67

TMR0 ..........................................................................66

MCLR..................................................................................59

Dat a E EPROM Me mory...... .......... ........... .......... .........49

....................................................131, 126, 80, 79, 82, 81, 80

OPC ODE Fiel d Descriptions... ...... ...... ....... ...... .......... ....... ..71

Oscillator Config urations.....................................................56

Oscilla t o r Sta r t- u p Time r ( O ST) .............. ....... ...... ...... ....... ..59

Packaging .........................................................................115

Details.......................................................................116

Marking.....................................................................115

PCL and PCLATH............. .. . .. .... .. .... .... .. ................... .. ........19

Computed GOTO........................................................19

Stack...........................................................................19

Pin Descriptions and Diagrams.............. .. . .. .. .. .. .. .. .... .. .. ......24

Pinout Descriptions

PIC12F629....................................................................8

PIC12F675....................................................................8

Pow e r C ontro l/Sta tu s Regis t e r (PCON )..... .. .............. .........60

Power-Down Mode (SLEEP) .. .. .. .... .. .. .... .. . .. .. .. .... .. .. .... .. . .. .. .69

Pow e r- on Res et (POR)................. ............... .......... .............59

Pow e r- u p Timer (PWRT)....... .. .......... ........... .......... ........... ..59

Prescaler.............................................................................31

Switc h in g Pr e scaler Assig n me n t........ .......... ...... .........31

Program Memory Organization.......... .. .... ............. .... .. ..........9

Programming, Device Instructions......................................71

RC Oscillator.......................................................................57

Reader Response..... .... .. .. .. . .. .. .... .. .. .. .... .. . .. .. .. .. .... .. .. .... ....132

READ-MODIFY-WRITE OPERATIONS..............................71

Registers

ADCON0 (A/D Control)...............................................45

ANSEL (Analog Select)...............................................46

CMCON (Comparator Control) ...................................37

CONF IG (Co n figur ation W o rd )........... .............. ...........54

EEADR (EEPROM Address) ......................................49

EECO N 1 (EEPR O M Contr o l)...... ...... .......... ........... .... 50

EEDAT (EEPROM Data)............................................49

INTCON (Interrupt Control).........................................15

IOCB (Interrupt-on-Change GPIO)............................. 23

MapsPIC12F629 ......................................................... 10

PIC12F675 ......................................................... 10

OPTI O N _ R EG ( O p tio n )............. .......... ........... ...... 14, 30

OSCCAL (Oscillator Calibration) ................................ 18

PCON (Power Control)............................................... 18

PIE1 (Peripheral Interrupt Enable 1)..... .... .. ................ 16

PIR1 (Peripheral Interrupt 1).... . .. .. .. .... .. .. .... .. . .. .. .. .... .. . 17

STATUS ..................................................................... 13

T1CON ( T im e r1 C o n tr o l)...... ....... ...... ...... ........... ...... ..34

VRCON (Voltage Reference Control). .. .... .. .. . .. .. .. .. .... . 42

WPU (Weak Pull-up)................................................... 22

RESET................................................................................ 58

Revision History................................................................ 125

Soft wa re Sim u la tor (MPLAB SIM) .. ... .......... ........... .......... ..81

Spe cial Featu r e s o f th e CP U................. ...... ........... .......... ..53

Special Function Registers................................................. 10

Special Functions Registers Summary............................... 11

Time-out Sequence ............................................................ 60

Timer0................................................................................. 29

Asso ciated Reg i st e rs............ ............... ........... .......... ..31

External Clock............................................................. 30

Interrupt ...................................................................... 29

Operation.................................................................... 29

T0CKI ......................................................................... 30

Timer1

Asso ciated Reg i st e rs............ ............... ........... .......... ..35

Asynchronous Counter Mode....... .. .. .... .. .. .. ............... . 35

Reading and Writing............. .... .. .... .. .... . .. .. .... .. ... 35

Interrupt ...................................................................... 33

Mod es o f O p e rations.......... ........... .......... ....... .......... ..33

Operation During SLEEP ............................................ 35

Oscillator..................................................................... 35

Prescaler .................................................................... 33

Timer1 Module with Gate Control............. .. .... .. .... . .. .. .... .. ... 32

Timing Diagrams

CLKOUT and I/O ....... .... .. .. .... .. ............. .... .. .. . .. .. .. .... .. . 96

External Clock............................................................. 94

INT Pin Interrupt......................................................... 66

PIC12F675 A/D Conversion (Normal Mode) ............ 102

PIC12F675 A/D Conversion Timing (SLEEP Mode). 103

RESET, Watchdog Timer, Oscillator Start-up Timer

and Power-up Timer.. .. .... .. .. .... ............... .. .... .............. 97

Time-out Sequence on Power-up (MCLR not Tied to

VDD)/Case 1................................................................ 63

Case 2................................................................ 63

Time-out Sequence on Power-up

(MCLR Tied to VDD).................................................... 63

Timer0 and Timer1 External Clock............................. 99

Timer1 Incrementing Edge......................................... 33

Timing Pa r a me ter Symbol o g y ...... ........... ...... ........... ...... .... 93

Voltage Reference Accuracy/Error..................................... 41

 2009 Microchip Technology Inc. DS41190F-page 129

PIC12F629/675

Watchdog Timer

Summary o f Re g isters ........ ........... .......... ........... ........68

Watchdog Timer (WDT)......................................................67

WWW Address..................................................................131

WWW, On-Line Support .................. . .. .... .... .. .... .... . .. .... .... .... .5

PIC12F629/675

DS41190F-page 130  2009 Microchip Technol ogy Inc.

NOTES:

 2009 Microchip Technology Inc. DS41190F-page 131

PIC12F629/675

THE MICROCHIP WEB SITE

Microc hip pro vides onl ine s upport v ia our W WW site at

www.microc hi p.c om . Thi s web si te i s us ed as a m ean s

to make files and information easily available to

customers. Accessible by using your favorite Internet

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resources, user’s guides and hardware support

documents, latest software releases and archived

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Questions (FAQ), technical support requests,

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•Business of Microchip – Product selector and

ordering guides, latest Microchip press releases,

listing of seminars and events, listings of

Microchip sales offices, distributors and factory

representatives

CUSTOMER CHANGE NOTIFICATION

SERVICE

Microchip’s customer notification service helps keep

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changes, updates, revisions or errata related to a

specif ied produ ct family or develo pment tool of interes t.

To register, access the Microchip web site at

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CUSTOMER SUPP ORT

Users of Microchip products can receive assistance

through several channels:

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Customers should contact their distributor,

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customers. A listing of sales offices and locations is

included in the back of this document.

Technic al suppo rt is avail able throug h the we b site

at: http://support.microchip.com

PIC12F629/675

DS41190F-page 132  2009 Microchip Technology Inc.

READER RESP ONSE

It is ou r intention to pro vi de you w it h th e best do cu menta t ion po ss ib le to e ns ure suc c es sfu l u se of y ou r Mic r oc hip pro d-

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DS41190FPIC12F629/675

1. What ar e the best features of t his document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

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7. How would you improve this document?

 2009 Microchip Technology Inc. DS41190F-page 133

PIC12F629/675

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factor y or the listed sales office .

* JW Devices are UV er asable and can be pro grammed to any device conf iguration. JW Devi ces meet the electr ical requirement of

each oscillator type.

PART NO. X/XX XXX

PatternPackageTemperature

Range

Device

Device: PIC12F6XX: Standard VDD range

PIC12F6XXT: (Tape and Reel )

Temperature

Range: I= -40C to +85C (Industrial)

E= -40C to +125C (Extended)

Package: P=PDIP

SN = SOIC (Gull wing, 3.90 mm body)

MF = MLF-S

MD = 8-Lead Plastic Dual Flat, No Lead (4X4) (DFN)

Pattern: 3-Digit Pattern Code for QTP (blank otherwise)

Examples:

a) PIC12F629 - E/P 301 = Extended T emp., PDIP

package, 20 MHz, QTP patter n #301 .

b) PIC12F675 - I/SN = Industrial temp., SOIC

package, 20 MHz.

DS41190F-page 134  2009 Microchip Technology Inc.

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03/26/09