UDG-01063
1
OUTA
ENBA
2INA
3GND
7
ENBB8
INVERTING
NON-INVERTING
OUTB
4
5
INVERTING
NON-INVERTING
INB
6 VDD
VDD
UCC27423, UCC27424, UCC27425
www.ti.com
SLUS545C –NOVEMBER 2002–REVISED JULY 2011
Dual 4-A High Speed Low-Side MOSFET Drivers With Enable
Check for Samples: UCC27423,UCC27424,UCC27425
1FEATURES DESCRIPTION
The UCC27423/4/5 family of high-speed dual
2•Industry-Standard Pin-Out MOSFET drivers can deliver large peak currents into
•Enable Functions for Each Driver capacitive loads. Three standard logic options are
•High Current Drive Capability of ±4A offered –dual-inverting, dual-noninverting and
•Unique BiPolar and CMOS True Drive Output one-inverting and one-noninverting driver. The
Stage Provides High Current at MOSFET Miller thermally enhanced 8-pin PowerPAD™MSOP
Thresholds package (DGN) drastically lowers the thermal
resistance to improve long-term reliability. It is also
•TTL/CMOS Compatible Inputs Independent of offered in the standard SOIC-8 (D) or PDIP-8 (P)
Supply Voltage packages.
•20ns Typical Rise and 15ns Typical Fall Times
with 1.8nF Load Using a design that inherently minimizes
•Typical Propagation Delay Times of 25ns with shoot-through current, these drivers deliver 4A of
Input Falling and 35ns with Input Rising current where it is needed most at the Miller plateau
region during the MOSFET switching transition. A
•4V to 15V Supply Voltage unique BiPolar and MOSFET hybrid output stage in
•Dual Outputs Can Be Paralleled for Higher parallel also allows efficient current sourcing and
Drive Current sinking at low supply voltages.
•Available in Thermally Enhanced MSOP The UCC27423/4/5 provides enable (ENBL) functions
PowerPAD™Package with 4.7°C/W θJC to have better control of the operation of the driver
•Rated From –40°C to 125°Capplications. ENBA and ENBB are implemented on
pins 1 and 8 which were previously left unused in the
APPLICATIONS industry standard pin-out. They are internally pulled
•Switch Mode Power Supplies up to Vdd for active high logic and can be left open
for standard operation.
•DC/DC Converters
•Motor Controllers BLOCK DIAGRAM
•Line Drivers
•Class D Switching Amplifiers
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Copyright ©2002–2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
D, DGN, OR P PACKAGE
(TOP VIEW) D, DGN, OR P PACKAGE
(TOP VIEW) D, DGN, OR P PACKAGE
(TOP VIEW)
ENBA
INA
GND
INB
ENBB
OUTA
VDD
OUTB
8
7
6
5
1
2
3
4
ENBA
INA
GND
INB
ENBB
OUTA
VDD
OUTB
8
7
6
5
1
2
3
4
ENBA
INA
GND
INB
ENBB
OUTA
VDD
OUTB
8
7
6
5
1
2
3
4
(DUAL INVERTING) (DUAL NON-INVERTING) (ONE INVERTING AND
ONE NON-INVERTING)
UCC27423 UCC27424 UCC27425
UCC27423, UCC27424, UCC27425
SLUS545C –NOVEMBER 2002–REVISED JULY 2011
www.ti.com
ORDERING INFORMATION PACKAGED DEVICES
OUTPUT TEMPERATURE RANGE SOIC-8 MSOP-8 PowerPAD PDIP-8
CONFIGURATION TA= TJ(D)(1) (DGN)(2) (P)
Dual inverting –40°C to 125°C UCC27423D UCC27423DGN UCC27423P
Dual nonInverting –40°C to 125°C UCC27424D UCC27424DGN UCC27424P
One inverting, one –40°C to 125°C UCC27425D UCC27425DGN UCC27425P
noninverting
(1) D (SOIC-8) and DGN (PowerPAD-MSOP) packages are available taped and reeled. Add R suffix to device type (e.g. UCC27423DR,
UCC27424DGNR) to order quantities of 2,500 devices per reel for D or 1,000 devices per reel for DGN package.
(2) The PowerPAD™is not directly connected to any leads of the package. However, it is electrically and thermally connected to the
substrate which is the ground of the device.
POWER DISSIPATION RATING TABLE
DERATING FACTOR
POWER RATING (mW)
PACKAGE SUFFIX θJC (°C/W) θJA (°C/W) ABOVE
TA= 70°C(1) 70°C (mW/°C)(1)
SOIC-8 D 42 84 - 160‡344–655(2) 6.25–11.9(2)
PDIP-8 P 49 110 500 9
MSOP PowerPAD-8(3) DGN 4.7 50 - 59‡1370 17.1
(1) 125°C operating junction temperature is used for power rating calculations
(2) The range of values indicates the effect of pc-board. These values are intended to give the system designer an indication of the best
and worst case conditions. In general, the system designer should attempt to use larger traces on the pc-board where possible in order
to spread the heat away form the device more effectively. For information on the PowerPAD™package, refer to Technical Brief,
PowerPad Thermally Enhanced Package, Texas Instruments (SLMA002) and Application Brief, PowerPad Made Easy, Texas
Instruments (SLMA004).
(3) The PowerPAD™is not directly connected to any leads of the package. However, it is electrically and thermally connected to the
substrate which is the ground of the device.
Table 1. Input/Output Table
INPUTS (VIN_L, VIN_H) UCC27423 UCC27424 UCC27425
ENBA ENBB INA INB OUTA OUTB OUTA OUTB OUTA OUTB
H H L L H H L L H L
H H L H H L L H H H
H H H L L H H L L L
H H H H L L H H L H
L L X X L L L L L L
2Copyright ©2002–2011, Texas Instruments Incorporated
UCC27423, UCC27424, UCC27425
www.ti.com
SLUS545C –NOVEMBER 2002–REVISED JULY 2011
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) VALUE UNIT
VDD Supply voltage -0.3 to 16 V
IOUT_DC Output current (OUTA, OUTB) DC 0.2 A
IOUT_PULSED Pulsed, (0.5μs) 4.5 A
VIN Input voltage (INA, INB) -5 to 6 or VDD+0.3 (whichever is larger) V
Enable voltage (ENBA, ENBB) –0.3 V to 6 V or VDD+0.3 (whichever is larger)
DGN package 3 W
Power dissipation at TA= 25°C D package 650 mW
P package 350
TJJunction operating temperature –55 to 150
Tstg Storage temperature –65 to 150 °C
Lead temperature (soldering, 10 sec) 300
ELECTRICAL CHARACTERISTICS
VDD = 4.5V to 15V, TA=–40°C to 125°C ,TA= TJ, (unless otherwise noted)
PARAMETER TEST CONDITION MIN TYP MAX UNIT
INPUT (INA, INB)
VIN_H Logic 1 input threshold 2 V
VIN_L Logic 0 input threshold 1
Input current 0 V ≤VIN ≤VDD –10 0 10 μA
OUTPUT (OUTA, OUTB)
Output current VDD = 14 V (1) 4 A
VOH High-level output voltage VOH = VDD –VOUT, IOUT =–10 mA 330 450 mV
VOL Low-level output level IOUT = 10 mA 22 45
TA= 25°C, IOUT =–10 mA, VDD = 14 V(2) 25 30 35
Output resistance high TA= full range, IOUT =–10 mA, VDD = 14 V(2) 18 45 Ω
TA= 25°C, IOUT = 10 mA, VDD = 14 V(2) 1.9 2.2 2.5
Output resistance low TA= full range IOUT = 10 mA, VDD = 14 V(2) 1.2 4.0
Latch-up protection 500 mA
SWITCHING TIME
trRise time (OUTA, OUTB) CLOAD = 1.8 nF 20 40
tfFall time (OUTA, OUTB) CLOAD = 1.8 nF 15 40 ns
td1 Delay, IN rising (IN to OUT) CLOAD = 1.8 nF 25 40
td2 Delay, IN falling (IN to OUT) CLOAD = 1.8 nF 35 50
(1) The pullup / pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The pulsed output current rating is the
combined current from the bipolar and MOSFET transistors.
(2) The pullup / pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The output resistance is the Rds(on) of the
MOSFET transistor when the voltage on the driver output is less than the saturation voltage of the bipolar transistor.
Copyright ©2002–2011, Texas Instruments Incorporated 3
+5V
INPUT
16V
OUTPUT
0V
0V
10%
90%
10%
90%
(a)
90%
90%
10%
90%
(b)
INPUT
OUTPUT
10%
tD1 tD2
tFtf
tD1
tFtF
tD2
UCC27423, UCC27424, UCC27425
SLUS545C –NOVEMBER 2002–REVISED JULY 2011
www.ti.com
ELECTRICAL CHARACTERISTICS (Continued)
VDD = 4.5V to 15 V, TA=–40°C to 125°C,TA= TJ(unless otherwise noted) (1) (2)
PARAMETER TEST CONDITION MIN TYP MAX UNITS
ENABLE (ENBA, ENBB)
VIN_H High-level input voltage LO to HI transition 1.7 2.4 2.9
VIN_L Low-level input voltage HI to LO transition 1.1 1.8 2.2 V
Hysteresis 0.15 0.55 0.90
RENBL Enable impedance VDD = 14 V, ENBL = GND 75 100 140 kΩ
tD3 Propagation delay time (see Figure 2) CLOAD = 1.8 nF 30 60 ns
tD4 Propagation delay time (see Figure 2) CLOAD = 1.8 nF 100 150
OVERALL
INA = 0 V, INB = 0 V 900 1350
INA = 0 V, INB = HIGH 750 1100
UCC27423 μA
INA = HIGH, INB = 0 V 750 1100
INA = HIGH, INB = HIGH 600 900
INA = 0 V, INB = 0 V 300 450
Static operating current, INA = 0 V, INB = HIGH 750 1100
IDD VDD = 15 V, UCC27424 μA
INA = HIGH, INB = 0 V 750 1100
ENBA = ENBB = 15 V INA = HIGH, INB = HIGH 1200 1800
INA = 0 V, INB = 0 V 600 900
INA = 0 V, INB = HIGH 1050 1600
UCC27425 μA
INA = HIGH, INB = 0 V 450 700
INA = HIGH, INB = HIGH 900 1350
INA = 0 V, INB = 0 V 300 450
INA = 0 V, INB = HIGH 450 700
Disabled, VDD = 15 V,
IDD All μA
ENBA = ENBB = 0 V INA = HIGH, INB = 0 V 450 700
INA = HIGH, INB = HIGH 600 900
(1) The pullup / pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The peak output current rating is the
combined current from the bipolar and MOSFET transistors.
(2) The pullup / pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The output resistance is the Rds(on) of the
MOSFET transistor when the voltage on the driver output is less than the saturation voltage of the bipolar transistor.
Figure 1. Switching Waveforms for (a) Inverting Driver and (b) Noninverting Driver
4Copyright ©2002–2011, Texas Instruments Incorporated
10%
90% 90%
VIN_H VIN_L
tD3 tD4
tRtF
0V
5V
0V
OUTx
VDD
ENBx
UCC27423, UCC27424, UCC27425
www.ti.com
SLUS545C –NOVEMBER 2002–REVISED JULY 2011
NOTE: The 10% and 90% thresholds depict the dynamics of the BiPolar output devices that dominate the power MOSFET
transition through the Miller regions of operation.
Figure 2. Switching Waveform for Enable to Output
Terminal Functions
TERMINAL I/O FUNCTION
NO. NAME
1 ENBA I Enable input for the driver A with logic compatible threshold and hysteresis. The driver output can be enabled and disabled with
this pin. It is internally pulled up to VDD with 100kΩresistor for active high operation. The output state when the device is
disabled will be low regardless of the input state.
2 INA I Input A. Input signal of the A driver which has logic compatible threshold and hysteresis. If not used, this input should be tied to
either VDD or GND. It should not be left floating.
3 GND Common ground. This ground should be connected very closely to the source of the power MOSFET which the driver is driving.
4 INB I Input B. Input signal of the A driver which has logic compatible threshold and hysteresis. If not used, this input should be tied to
either VDD or GND. It should not be left floating.
5 OUTB O Driver output B. The output stage is capable of providing 4A drive current to the gate of a power MOSFET.
6 VDD I Supply. Supply voltage and the power input connection for this device.
7 OUTA O Driver output A. The output stage is capable of providing 4A drive current to the gate of a power MOSFET.
8 ENBB I Enable input for the driver B with logic compatible threshold and hysteresis. The driver output can be enabled and disabled with
this pin. It is internally pulled up to VDD with 100kΩresistor for active high operation. The output state when the device is
disabled will be low regardless of the input state.
Copyright ©2002–2011, Texas Instruments Incorporated 5
UCC27423, UCC27424, UCC27425
SLUS545C –NOVEMBER 2002–REVISED JULY 2011
www.ti.com
APPLICATION INFORMATION
General Information
High frequency power supplies often require high-speed, high-current drivers such as the UCC27423/4/5 family.
A leading application is the need to provide a high power buffer stage between the PWM output of the control IC
and the gates of the primary power MOSFET or IGBT switching devices. In other cases, the driver IC is utilized
to drive the power device gates through a drive transformer. Synchronous rectification supplies also have the
need to simultaneously drive multiple devices which can present an extremely large load to the control circuitry.
Driver ICs are utilized when it is not feasible to have the primary PWM regulator IC directly drive the switching
devices for one or more reasons. The PWM IC may not have the brute drive capability required for the intended
switching MOSFET, limiting the switching performance in the application. In other cases there may be a desire to
minimize the effect of high frequency switching noise by placing the high current driver physically close to the
load. Also, newer ICs that target the highest operating frequencies may not incorporate onboard gate drivers at
all. Their PWM outputs are only intended to drive the high impedance input to a driver such as the
UCC27423/4/5. Finally, the control IC may be under thermal stress due to power dissipation, and an external
driver can help by moving the heat from the controller to an external package.
Input Stage
The input thresholds have a 3.3V logic sensitivity over the full range of VDD voltages; yet it is equally compatible
with 0 to VDD signals. The inputs of UCC27423/4/5 family of drivers are designed to withstand 500-mA reverse
current without either damage to the IC for logic upset. The input stage of each driver should be driven by a
signal with a short rise or fall time. This condition is satisfied in typical power supply applications, where the input
signals are provided by a PWM controller or logic gates with fast transition times (<200 ns). The input stages to
the drivers function as a digital gate, and they are not intended for applications where a slow changing input
voltage is used to generate a switching output when the logic threshold of the input section is reached. While this
may not be harmful to the driver, the output of the driver may switch repeatedly at a high frequency.
Users should not attempt to shape the input signals to the driver in an attempt to slow down (or delay) the signal
at the output. If limiting the rise or fall times to the power device is desired, limit the rise or fall times to the power
device, then an external resistance can be added between the output of the driver and the load device, which is
generally a power MOSFET gate. The external resistor may also help remove power dissipation from the devoce
package, as discussed in the section on Thermal Considerations.
Output Stage
Inverting outputs of the UCC27423 and OUTA of the UCC27425 are intended to drive external P-channel
MOSFETs. Noninverting outputs of the UCC27424 and OUTB of the UCC27425 are intended to drive external
N-channel MOSFETs.
Each output stage is capable of supplying ±4A peak current pulses and swings to both VDD and GND. The
pullup/pulldown circuits of the driver are constructed of bipolar and MOSFET transistors in parallel. The peak
output current rating is the combined current from the bipolar and MOSFET transistors. The output resistance is
the RDS(on) of the MOSFET transistor when the voltage on the driver output is less than the saturation voltage of
the bipolar transistor. Each output stage also provides a very low impedance to overshoot and undershoot due to
the body diode of the external MOSFET. This means that in many cases, external-schottky-clamp diodes are not
required.
The UCC27423 family delivers 4A of gate drive where it is most needed during the MOSFET switching
transition –at the Miller plateau region –providing improved efficiency gains. A unique BiPolar and MOSFET
hybrid output stage in parallel also allows efficient current sourcing at low supply voltages.
Source/Sink Capabilities During Miller Plateau
Large power MOSFETs present a large load to the control circuitry. Proper drive is required for efficient, reliable
operation. The UCC27423/4/5 drivers have been optimized to provide maximum drive to a power MOSFET
during the Miller plateau region of the switching transition. This interval occurs while the drain voltage is swinging
between the voltage levels dictated by the power topology, requiring the charging/discharging of the drain-gate
capacitance with current supplied or removed by the driver device. [1]
6Copyright ©2002–2011, Texas Instruments Incorporated
UDG-01065
UCC27423
GND
1
2
3
4INB
INA 7
6
5
8
OUTA
VDD
OUTB
INPUT
1µF
CER
100 µF
AL EL
DSCHOTTKY
VDD
C2
1µF
VSNS
RSNS
0.1 Ω
C3
100 µF
10 Ω
+VSUPPLY
5.5 V
ENBB
ENBA
UCC27423, UCC27424, UCC27425
www.ti.com
SLUS545C –NOVEMBER 2002–REVISED JULY 2011
Two circuits are used to test the current capabilities of the UCC27423 driver. In each case external circuitry is
added to clamp the output near 5 V while the IC is sinking or sourcing current. An input pulse of 250 ns is
applied at a frequency of 1 kHz in the proper polarity for the respective test. In each test there is a transient
period where the current peaked up and then settled down to a steady-state value. The noted current
measurements are made at a time of 200 ns after the input pulse is applied, after the initial transient.
The first circuit in Figure 2 is used to verify the current sink capability when the output of the driver is clamped
around 5V, a typical value of gate-source voltage during the Miller plateau region. The UCC27423 is found to
sink 4.5A at VDD = 15V and 4.28A at VDD = 12V.
The circuit shown in Figure 3 is used to test the current source capability with the output clamped to around 5 V
with a string of Zener diodes. The UCC27423 is found to source 4.8 A at VDD = 15 V and 3.7 A at VDD = 12 V.
Figure 3.
It should be noted that the current sink capability is slightly stronger than the current source capability at lower
VDD. This is due to the differences in the structure of the bipolar-MOSFET power output section, where the
current source is a P-channel MOSFET and the current sink has an N-channel MOSFET.
In a large majority of applications it is advantageous that the turn-off capability of a driver is stronger than the
turn-on capability. This helps to ensure that the MOSFET is held OFF during common power supply transients
which may turn the device back ON.
Parallel Outputs
The A and B drivers may be combined into a single driver by connecting the INA/INB inputs together and the
OUTA/OUTB outputs together. Then, a single signal can control the paralleled combination as shown in Figure 4.
Copyright ©2002–2011, Texas Instruments Incorporated 7
UDG-01066
UCC27423
GND
1
2
3
4INB
INA 7
6
5
8
OUTA
VDD
OUTB
INPUT
1µF
CER
100µF
AL EL
DSCHOTTKY
VDD
C2
1µF
VSNS
RSNS
0.1Ω
C3
100µF
10Ω
+D
ADJ
5.5 V
ENBB
ENBA
UDG-01067
UCC27423
GND
1
2
3
4INB
INA 7
6
5
8
OUTA
VDD
OUTB
INPUT
1µF
CER 2.2µF
VDD
ENBB
ENBA
CLOAD
UCC27423, UCC27424, UCC27425
SLUS545C –NOVEMBER 2002–REVISED JULY 2011
www.ti.com
Figure 4.
Operational Waveforms and Circuit Layout
Figure 5 shows the circuit performance achievable with a single driver (1/2 of the 8-pin IC) driving a 10-nF load.
The input pulsewidth (not shown) is set to 300ns to show both transitions in the output waveform. Note the linear
rise and fall edges of the switching waveforms. This is due to the constant output current characteristic of the
driver as opposed to the resistive output impedance of traditional MOSFET-based gate drivers.
Figure 5.
8Copyright ©2002–2011, Texas Instruments Incorporated
E+1
2CV2
UCC27423, UCC27424, UCC27425
www.ti.com
SLUS545C –NOVEMBER 2002–REVISED JULY 2011
Figure 6.
In a power driver operating at high frequency, it is a significant challenge to get clean waveforms without much
overshoot/undershoot and ringing. The low output impedance of these drivers produces waveforms with high
di/dt. This tends to induce ringing in the parasitic inductances. Utmost care must be used in the circuit layout. It is
advantageous to connect the driver IC as close as possible to the leads. The driver IC layout has ground on the
opposite side of the output, so the ground should be connected to the bypass capacitors and the load with
copper trace as wide as possible. These connections should also be made with a small enclosed loop area to
minimize the inductance.
VDD
Although quiescent VDD current is very low, total supply current will be higher, depending on OUTA and OUTB
current and the programmed oscillator frequency. Total VDD current is the sum of quiescent VDD current and the
average OUT current. Knowing the operating frequency and the MOSFET gate charge (Qg), average OUT
current can be calculated from:
IOUT = Qg ×f, where f is frequency
For the best high-speed circuit performance, two VDD bypass capacitors are recommended tp prevent noise
problems. The use of surface mount components is highly recommended. A 0.1μF ceramic capacitor should be
located closest to the VDD to ground connection. In addition, a larger capacitor (such as 1μF) with relatively low
ESR should be connected in parallel, to help deliver the high current peaks to the load. The parallel combination
of capacitors should present a low impedance characteristic for the expected current levels in the driver
application.
Drive Current and Power Requirements
The UCC27423/4/5 family of drivers are capable of delivering 4A of current to a MOSFET gate for a period of
several hundred nanoseconds. High peak current is required to turn the device ON quickly. Then, to turn the
device OFF, the driver is required to sink a similar amount of current to ground. This repeats at the operating
frequency of the power device. A MOSFET is used in this discussion because it is the most common type of
switching device used in high frequency power conversion equipment.
References 1 and 2 discuss the current required to drive a power MOSFET and other capacitive-input switching
devices. Reference 2 includes information on the previous generation of bipolar IC gate drivers.
When a driver IC is tested with a discrete, capacitive load it is a fairly simple matter to calculate the power that is
required from the bias supply. The energy that must be transferred from the bias supply to charge the capacitor
is given by:
, where C is the load capacitor and V is the bias voltage feeding the driver.
Copyright ©2002–2011, Texas Instruments Incorporated 9
I+P
V+0.432 W
12 V +0.036 A
P+C V2 f+Qg f
UCC27423, UCC27424, UCC27425
SLUS545C –NOVEMBER 2002–REVISED JULY 2011
www.ti.com
There is an equal amount of energy transferred to ground when the capacitor is discharged. This leads to a
power loss given by the following:
, where f is the switching frequency.
This power is dissipated in the resistive elements of the circuit. Thus, with no external resistor between the driver
and gate, this power is dissipated inside the driver. Half of the total power is dissipated when the capacitor is
charged, and the other half is dissipated when the capacitor is discharged. An actual example using the
conditions of the previous gate drive waveform should help clarify this.
With VDD = 12V, CLOAD = 10nF, and f = 300kHz, the power loss can be calculated as:
P = 10nF ×(12)2×(300kHz) = 0.432W
With a 12V supply, this would equate to a current of:
(1)
The actual current measured from the supply was 0.037A, and is very close to the predicted value. But, the IDD
current that is due to the IC internal consumption should be considered. With no load the IC current draw is
0.0027A. Under this condition the output rise and fall times are faster than with a load. This could lead to an
almost insignificant, yet measurable current due to cross-conduction in the output stages of the driver. However,
these small current differences are buried in the high frequency switching spikes, and are beyond the
measurement capabilities of a basic lab setup. The measured current with 10nF load is reasonably close to that
expected.
The switching load presented by a power MOSFET can be converted to an equivalent capacitance by examining
the gate charge required to switch the device. This gate charge includes the effects of the input capacitance plus
the added charge needed to swing the drain of the device between the ON and OFF states. Most manufacturers
provide specifications that provide the typical and maximum gate charge, in nC, to switch the device under
specified conditions. Using the gate charge Qg, one can determine the power that must be dissipated when
charging a capacitor. This is done by using the equivalence Qg = CeffV to provide the following equation for
power:
(2)
This equation allows a power designer to calculate the bias power required to drive a specific MOSFET gate at a
specific bias voltage.
ENABLE
UCC27423/4/5 provides dual Enable inputs for improved control of each driver channel operation. The inputs
incorporate logic compatible thresholds with hysteresis. They are internally pulled up to VDD with 100kΩresistor
for active high operation. When ENBA and ENBB are driven high, the drivers are enabled and when ENBA and
ENBB are low, the drivers are disabled. The default state of the Enable pin is to enable the driver and therefore
can be left open for standard operation. The output states when the drivers are disabled is low regardless of the
input state. See the truth table of Table 1 for the operation using enable logic.
Enable input are compatible with both logic signals and slow changing analog signals. They can be directly
driven or a power-up delay can be programmed with a capacitor between ENBA, ENBB and AGND. ENBA and
ENBB control input A and input B respectively.
10 Copyright ©2002–2011, Texas Instruments Incorporated
UCC27423, UCC27424, UCC27425
www.ti.com
SLUS545C –NOVEMBER 2002–REVISED JULY 2011
Thermal Information
The useful range of a driver is greatly affected by the drive power requirements of the load and the thermal
characteristics of the IC package. In order for a power driver to be useful over a particular temperature range the
package must allow for the efficient removal of the heat produced while keeping the junction temperature within
rated limits. The UCC27423/4/5 family of drivers is available in three different packages to cover a range of
application requirements.
As shown in the power dissipation rating table, the SOIC-8 (D) and PDIP-8 (P) packages each have a power
rating of around 0.5W with TA= 70°C. This limit is imposed in conjunction with the power derating factor also
given in the table. Note that the power dissipation in our earlier example is 0.432W with a 10nF load, 12VDD,
switched at 300kHz. Thus, only one load of this size could be driven using the D or P package, even if the two
onboard drivers are paralleled. The difficulties with heat removal limit the drive available in the older packages.
The MSOP PowerPAD-8 (DGN) package significantly relieves this concern by offering an effective means of
removing the heat from the semiconductor junction. As illustrated in Reference 3, the PowerPAD packages offer
a leadframe die pad that is exposed at the base of the package. This pad is soldered to the copper on the PC
board directly underneath the IC package, reducing the θjc down to 4.7°C/W. Data is presented in Reference 3
to show that the power dissipation can be quadrupled in the PowerPAD configuration when compared to the
standard packages. The PC board must be designed with thermal lands and thermal vias to complete the heat
removal subsystem, as summarized in Reference 4. This allows a significant improvement in heatsinking over
that available in the D or P packages, and is shown to more than double the power capability of the D and P
packages. Note that the PowerPAD™is not directly connected to any leads of the package. However, it is
electrically and thermally connected to the substrate which is the ground of the device.
References
1. Power Supply Seminar SEM-1400 Topic 2: Design And Application Guide For High Speed MOSFET Gate
Drive Circuits, by Laszlo Balogh, Texas Instruments (SLUP133).
2. Application Note, Practical Considerations in High Performance MOSFET, IGBT and MCT Gate Drive
Circuits, by Bill Andreycak, Texas Instruments ( SLUA105)
3. Technical Brief, PowerPad Thermally Enhanced Package, Texas Instruments (SLMA002)
4. Application Brief, PowerPAD Made Easy, Texas Instruments (SLMA004)
Related Products
PRODUCT DESCRIPTION PACKAGES
UCC37323/4/5 Dual 4-A Low-Side Drivers MSOP-8 PowerPAD, SOIC-8, PDIP-8
UCC37321/2 Single 9-A Low-Side Driver with Enable MSOP-8 PowerPAD, SOIC-8, PDIP-8
TPS2811/12/13 Dual 2-A Low-Side Drivers with Internal Regulator TSSOP-8, SOIC-8, PDIP-8
TPS2814/15 Dual 2-A Low-Side Drivers with Two Inputs per Channel TSSOP-8, SOIC-8, PDIP-8
TPS2816/17/18/19 Single 2-A Low-Side Driver with Internal Regulator 5-Pin SOT-23
TPS2828/29 Single 2-A Low-Side Driver 5-Pin SOT-23
Copyright ©2002–2011, Texas Instruments Incorporated 11
0
20
40
60
80
100
IDD -SupplyCurrent-mA
f- Frequency -Hz
10nF
4.7nF
2.2nF
1nF
470pF
0 1M 2M500K 1.5M
0
20
40
60
80
100
IDD -SupplyCurrent-mA
f- Frequency -Hz
10nF
4.7nF
2.2nF
1nF
470pF
0 1M 2M500K 1.5M
0
50
100
150
200
IDD -SupplyCurrent-mA
f- Frequency -Hz
10nF 4.7nF
2.2nF
1nF
470pF
0 1M 2M500K 1.5M
UCC27423, UCC27424, UCC27425
SLUS545C –NOVEMBER 2002–REVISED JULY 2011
www.ti.com
TYPICAL CHARACTERISTICS
SUPPLY CURRENT SUPPLY CURRENT
vs vs
FREQUENCY (VDD = 4.5V) FREQUENCY (VDD = 8.0V)
Figure 7. Figure 8.
SUPPLY CURRENT SUPPLY CURRENT
vs vs
FREQUENCY (VDD = 12V) FREQUENCY (VDD = 15V)
Figure 9. Figure 10.
12 Copyright ©2002–2011, Texas Instruments Incorporated
4 10 16
0
10
30
50
60
80
90
20
40
70
6 8 12 14
IDD -SupplyCurrent-mA
VDD -SupplyVoltage-V
2MHz
1MHz
500kHz
200kHz
100/50kHz
VDD -SupplyVoltage-V
4 9 19
0
20
40
80
120
140
160
14
60
100
IDD -SupplyCurrent-mA
2MHz
1MHz
500kHz
200kHz
50/20kHz
100kHz
UCC27423, UCC27424, UCC27425
www.ti.com
SLUS545C –NOVEMBER 2002–REVISED JULY 2011
TYPICAL CHARACTERISTICS (continued)
SUPPLY CURRENT SUPPLY CURRENT
vs vs
SUPPLY VOLTAGE (CLOAD = 2.2nF) SUPPLY VOLTAGE (CLOAD = 4.7nF)
Figure 11. Figure 12.
SUPPLY CURRENT SUPPLY CURRENT
vs vs
SUPPLY VOLTAGE (UCC27423) SUPPLY VOLTAGE (UCC27424)
Figure 13. Figure 14.
Copyright ©2002–2011, Texas Instruments Incorporated 13
0.65
0.70
0.30
0.35
0.40
0.45
0.50
0.55
0.60
0.75
410 1686 12 14
VDD -SupplyVoltage-V
IDD -SupplyCurrent-mA
Input=VDD
Input=0V
-50 50 150
0
5
10
15
20
25
1000
TJ-Temperature- °C
tr/tf-Rise/FallTime-ms
tr
tf
UCC27423, UCC27424, UCC27425
SLUS545C –NOVEMBER 2002–REVISED JULY 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
SUPPLY CURRENT RISE TIME/FALL TIME
vs vs
SUPPLY VOLTAGE (UCC27425) TEMPERATURE (UCC27423)
Figure 15. Figure 16.
RISE TIME FALL TIME
vs vs
SUPPLY VOLTAGE SUPPLY VOLTAGE
Figure 17. Figure 18.
14 Copyright ©2002–2011, Texas Instruments Incorporated
tD2-DelayT
ime-ns
VDD -SupplyVoltage-V
20
22
24
26
32
34
38
28
30
36
1nF
4.7nF
2.2nF
10nF
470pF
4 10 1686 12 14
12
14
16
18
20
22
30
24
26
28
VDD -SupplyVoltage-V
tD1-DelayT
ime-ns
1nF
4.7nF
2.2nF
10nF
470pF
4 10 1686 12 14
W
1.0
1.5
2.0
2.5
3.0
0
0.5
-50 125-25 0 25 50 10075
TJ-Temperature- °C
Enablethresholdandhysteresis-V
ENBL-ON
ENBL-OFF
ENBL-HYSTERESIS
UCC27423, UCC27424, UCC27425
www.ti.com
SLUS545C –NOVEMBER 2002–REVISED JULY 2011
TYPICAL CHARACTERISTICS (continued)
DELAY TIME (fD1) DELAY TIME (fD2)
vs vs
SUPPLY VOLTAGE (UCC27423) SUPPLY VOLTAGE (UCC27423)
Figure 19. Figure 20.
ENABLE THRESHOLD AND HYSTERESIS ENABLE RESISTANCE
vs vs
TEMPERATURE TEMPERATURE
Figure 21. Figure 22.
Copyright ©2002–2011, Texas Instruments Incorporated 15
50 s/divm
50 s/divm
10 nFBetweenOutputandGND
VDD -SupplyV
oltage-V
1V/div
OUT
VDD
0V
IN=VDD
ENBL=VDD
50 s/divm
50 s/divm
UCC27423, UCC27424, UCC27425
SLUS545C –NOVEMBER 2002–REVISED JULY 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
OUTPUT BEHAVIOR OUTPUT BEHAVIOR
vs vs
SUPPLY VOLTAGE (INVERTING) SUPPLY VOLTAGE (INVERTING)
Figure 23. Figure 24.
OUTPUT BEHAVIOR OUTPUT BEHAVIOR
vs vs
VDD (INVERTING) VDD (INVERTING)
Figure 25. Figure 26.
16 Copyright ©2002–2011, Texas Instruments Incorporated
50 s/divm
50 s/divm
50 s/divm
10 nFBetweenOutputandGND
VDD -SupplyV
oltage-V
1V/div
0V
VDD
OUT
IN=GND
ENBL=VDD
50 s/divm
UCC27423, UCC27424, UCC27425
www.ti.com
SLUS545C –NOVEMBER 2002–REVISED JULY 2011
TYPICAL CHARACTERISTICS (continued)
OUTPUT BEHAVIOR OUTPUT BEHAVIOR
vs vs
VDD (NON-INVERTING) VDD (NON-INVERTING)
Figure 27. Figure 28.
OUTPUT BEHAVIOR OUTPUT BEHAVIOR
vs vs
VDD (NON-INVERTING) VDD (NON-INVERTING)
Figure 29. Figure 30.
Copyright ©2002–2011, Texas Instruments Incorporated 17
-50
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
125-25 0 25 50 10075
VON -InputThresholdV
oltage-V
TJ-Temperature- °C
VDD =15V
VDD =10V
VDD =4.5V
UCC27423, UCC27424, UCC27425
SLUS545C –NOVEMBER 2002–REVISED JULY 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
INPUT THRESHOLD
vs
TEMPERATURE
Figure 31.
REVISION HISTORY
Changes from Revision B (November 2004) to Revision C Page
•Changed temperature rating. ................................................................................................................................................ 1
•Changed ORDERING INFORMATION temperature range, three instances. ...................................................................... 2
•Changed Output current (OUTA, OUTB) DC from 0.3 A to 0.2 A. ....................................................................................... 3
•Changed ELECTRICAL CHARACTERISTICS temperature rating. ...................................................................................... 3
•Changed Low-level output level from 40 mV max to 45 mV max. ....................................................................................... 3
18 Copyright ©2002–2011, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com 18-Apr-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
UCC27423D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC27423DG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC27423DGN ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM
UCC27423DGNG4 ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM
UCC27423DGNR ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM
UCC27423DGNRG4 ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM
UCC27423DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC27423DRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC27423P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
UCC27423PE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
UCC27424D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC27424DG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC27424DGN ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM
UCC27424DGNG4 ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM
UCC27424DGNR ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM
UCC27424DGNRG4 ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM
UCC27424DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC27424DRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 18-Apr-2011
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
UCC27424P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
UCC27424PE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
UCC27425D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC27425DG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC27425DGN ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM
UCC27425DGNG4 ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM
UCC27425DGNR ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM
UCC27425DGNRG4 ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM
UCC27425DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC27425DRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC27425P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
UCC27425PE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
PACKAGE OPTION ADDENDUM
www.ti.com 18-Apr-2011
Addendum-Page 3
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF UCC27423, UCC27424, UCC27425 :
•Automotive: UCC27423-Q1, UCC27424-Q1, UCC27425-Q1
•Enhanced Product: UCC27423-EP, UCC27424-EP
NOTE: Qualified Version Definitions:
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•Enhanced Product - Supports Defense, Aerospace and Medical Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
UCC27423DGNR MSOP-
Power
PAD
DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
UCC27423DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
UCC27424DGNR MSOP-
Power
PAD
DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
UCC27424DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
UCC27425DGNR MSOP-
Power
PAD
DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
UCC27425DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 15-Sep-2011
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
UCC27423DGNR MSOP-PowerPAD DGN 8 2500 364.0 364.0 27.0
UCC27423DR SOIC D 8 2500 340.5 338.1 20.6
UCC27424DGNR MSOP-PowerPAD DGN 8 2500 364.0 364.0 27.0
UCC27424DR SOIC D 8 2500 340.5 338.1 20.6
UCC27425DGNR MSOP-PowerPAD DGN 8 2500 364.0 364.0 27.0
UCC27425DR SOIC D 8 2500 340.5 338.1 20.6
PACKAGE MATERIALS INFORMATION
www.ti.com 15-Sep-2011
Pack Materials-Page 2
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