UCC27423, UCC27424, UCC27425 SLUS545C - NOVEMBER 2002 - REVISED JULY 2011 www.ti.com Dual 4-A High Speed Low-Side MOSFET Drivers With Enable Check for Samples: UCC27423, UCC27424, UCC27425 FEATURES DESCRIPTION * * * * The UCC27423/4/5 family of high-speed dual MOSFET drivers can deliver large peak currents into capacitive loads. Three standard logic options are offered - dual-inverting, dual-noninverting and one-inverting and one-noninverting driver. The thermally enhanced 8-pin PowerPADTM MSOP package (DGN) drastically lowers the thermal resistance to improve long-term reliability. It is also offered in the standard SOIC-8 (D) or PDIP-8 (P) packages. 1 2 * * * * * * * Industry-Standard Pin-Out Enable Functions for Each Driver High Current Drive Capability of 4A Unique BiPolar and CMOS True Drive Output Stage Provides High Current at MOSFET Miller Thresholds TTL/CMOS Compatible Inputs Independent of Supply Voltage 20ns Typical Rise and 15ns Typical Fall Times with 1.8nF Load Typical Propagation Delay Times of 25ns with Input Falling and 35ns with Input Rising 4V to 15V Supply Voltage Dual Outputs Can Be Paralleled for Higher Drive Current Available in Thermally Enhanced MSOP PowerPADTM Package with 4.7C/W JC Rated From -40C to 125C APPLICATIONS * * * * * Switch Mode Power Supplies DC/DC Converters Motor Controllers Line Drivers Class D Switching Amplifiers Using a design that inherently minimizes shoot-through current, these drivers deliver 4A of current where it is needed most at the Miller plateau region during the MOSFET switching transition. A unique BiPolar and MOSFET hybrid output stage in parallel also allows efficient current sourcing and sinking at low supply voltages. The UCC27423/4/5 provides enable (ENBL) functions to have better control of the operation of the driver applications. ENBA and ENBB are implemented on pins 1 and 8 which were previously left unused in the industry standard pin-out. They are internally pulled up to Vdd for active high logic and can be left open for standard operation. BLOCK DIAGRAM 8 ENBB 7 OUTA 6 VDD 5 OUTB ENBA 1 INVERTING INA 2 VDD NON-INVERTING INVERTING GND 3 INB 4 NON-INVERTING UDG-01063 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2002-2011, Texas Instruments Incorporated UCC27423, UCC27424, UCC27425 SLUS545C - NOVEMBER 2002 - REVISED JULY 2011 www.ti.com ORDERING INFORMATION (1) (2) OUTPUT CONFIGURATION TEMPERATURE RANGE TA = TJ PACKAGED DEVICES SOIC-8 (D) (1) MSOP-8 PowerPAD (DGN) (2) PDIP-8 (P) Dual inverting -40C to 125C UCC27423D UCC27423DGN UCC27423P Dual nonInverting -40C to 125C UCC27424D UCC27424DGN UCC27424P One inverting, one noninverting -40C to 125C UCC27425D UCC27425DGN UCC27425P D (SOIC-8) and DGN (PowerPAD-MSOP) packages are available taped and reeled. Add R suffix to device type (e.g. UCC27423DR, UCC27424DGNR) to order quantities of 2,500 devices per reel for D or 1,000 devices per reel for DGN package. The PowerPADTM is not directly connected to any leads of the package. However, it is electrically and thermally connected to the substrate which is the ground of the device. D, DGN, OR P PACKAGE (TOP VIEW) D, DGN, OR P PACKAGE (TOP VIEW) D, DGN, OR P PACKAGE (TOP VIEW) UCC27425 UCC27424 UCC27423 ENBA 1 8 ENBB ENBA 1 8 ENBB ENBA 1 8 ENBB INA 2 7 OUTA INA 2 7 OUTA INA 2 7 OUTA 6 VDD GND 3 GND 3 5 OUTB INB 4 6 VDD INB 4 (DUAL INVERTING) 6 VDD GND 3 5 OUTB 5 OUTB INB 4 (DUAL NON-INVERTING) (ONE INVERTING AND ONE NON-INVERTING) POWER DISSIPATION RATING TABLE (1) (2) (3) PACKAGE SUFFIX JC (C/W) JA (C/W) POWER RATING (mW) TA = 70C (1) DERATING FACTOR ABOVE 70C (mW/C) (1) SOIC-8 D 42 84 - 160 344-655 (2) 6.25-11.9 (2) PDIP-8 P 49 110 500 9 MSOP PowerPAD-8 (3) DGN 4.7 50 - 59 1370 17.1 125C operating junction temperature is used for power rating calculations The range of values indicates the effect of pc-board. These values are intended to give the system designer an indication of the best and worst case conditions. In general, the system designer should attempt to use larger traces on the pc-board where possible in order to spread the heat away form the device more effectively. For information on the PowerPADTM package, refer to Technical Brief, PowerPad Thermally Enhanced Package, Texas Instruments (SLMA002) and Application Brief, PowerPad Made Easy, Texas Instruments (SLMA004). The PowerPADTM is not directly connected to any leads of the package. However, it is electrically and thermally connected to the substrate which is the ground of the device. Table 1. Input/Output Table INPUTS (VIN_L, VIN_H) 2 UCC27423 UCC27424 UCC27425 ENBA ENBB INA INB OUTA OUTB OUTA OUTB OUTA OUTB H H L L H H L L H L H H L H H L L H H H H H H L L H H L L L H H H H L L H H L H L L X X L L L L L L Copyright (c) 2002-2011, Texas Instruments Incorporated UCC27423, UCC27424, UCC27425 SLUS545C - NOVEMBER 2002 - REVISED JULY 2011 www.ti.com ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) VALUE UNIT VDD Supply voltage -0.3 to 16 V IOUT_DC Output current (OUTA, OUTB) DC 0.2 A IOUT_PULSED Pulsed, (0.5s) 4.5 A VIN Input voltage (INA, INB) -5 to 6 or VDD+0.3 (whichever is larger) V -0.3 V to 6 V or VDD+0.3 (whichever is larger) Enable voltage (ENBA, ENBB) DGN package Power dissipation at TA = 25C 3 D package 650 P package 350 W mW TJ Junction operating temperature -55 to 150 Tstg Storage temperature -65 to 150 Lead temperature (soldering, 10 sec) C 300 ELECTRICAL CHARACTERISTICS VDD = 4.5V to 15V, TA = -40C to 125C ,TA = TJ, (unless otherwise noted) PARAMETER TEST CONDITION MIN TYP MAX UNIT INPUT (INA, INB) VIN_H Logic 1 input threshold VIN_L Logic 0 input threshold Input current 2 1 0 V VIN VDD -10 0 10 V A OUTPUT (OUTA, OUTB) (1) Output current VDD = 14 V VOH High-level output voltage VOH = VDD - VOUT, IOUT = -10 mA VOL Low-level output level IOUT = 10 mA Output resistance high Output resistance low 4 TA = 25C, IOUT = -10 mA, VDD = 14 V (2) 25 TA = full range, IOUT = -10 mA, VDD = 14 V (2) 18 TA = 25C, IOUT = 10 mA, VDD = 14 V (2) 1.9 TA = full range IOUT = 10 mA, VDD = 14 V (2) Latch-up protection A 330 450 22 45 30 35 2.2 2.5 45 1.2 mV 4.0 500 mA SWITCHING TIME tr Rise time (OUTA, OUTB) CLOAD = 1.8 nF 20 40 tf Fall time (OUTA, OUTB) CLOAD = 1.8 nF 15 40 td1 Delay, IN rising (IN to OUT) CLOAD = 1.8 nF 25 40 td2 Delay, IN falling (IN to OUT) CLOAD = 1.8 nF 35 50 (1) (2) ns The pullup / pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The pulsed output current rating is the combined current from the bipolar and MOSFET transistors. The pullup / pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The output resistance is the Rds(on) of the MOSFET transistor when the voltage on the driver output is less than the saturation voltage of the bipolar transistor. Copyright (c) 2002-2011, Texas Instruments Incorporated 3 UCC27423, UCC27424, UCC27425 SLUS545C - NOVEMBER 2002 - REVISED JULY 2011 www.ti.com ELECTRICAL CHARACTERISTICS (Continued) VDD = 4.5V to 15 V, TA = -40C to 125C,TA = TJ (unless otherwise noted) PARAMETER (1) (2) TEST CONDITION MIN TYP MAX 2.9 UNITS ENABLE (ENBA, ENBB) VIN_H High-level input voltage LO to HI transition 1.7 2.4 VIN_L Low-level input voltage HI to LO transition 1.1 1.8 2.2 0.15 0.55 0.90 75 Hysteresis RENBL Enable impedance VDD = 14 V, ENBL = GND 100 140 tD3 Propagation delay time (see Figure 2) CLOAD = 1.8 nF 30 60 tD4 Propagation delay time (see Figure 2) CLOAD = 1.8 nF 100 150 INA = 0 V, INB = 0 V 900 1350 INA = 0 V, INB = HIGH 750 1100 INA = HIGH, INB = 0 V 750 1100 INA = HIGH, INB = HIGH 600 900 INA = 0 V, INB = 0 V 300 450 INA = 0 V, INB = HIGH 750 1100 INA = HIGH, INB = 0 V 750 1100 1200 1800 600 900 INA = 0 V, INB = HIGH 1050 1600 INA = HIGH, INB = 0 V 450 700 INA = HIGH, INB = HIGH 900 1350 INA = 0 V, INB = 0 V 300 450 INA = 0 V, INB = HIGH 450 700 INA = HIGH, INB = 0 V 450 700 INA = HIGH, INB = HIGH 600 900 V k ns OVERALL UCC27423 Static operating current, VDD = 15 V, ENBA = ENBB = 15 V IDD UCC27424 INA = HIGH, INB = HIGH INA = 0 V, INB = 0 V UCC27425 Disabled, VDD = 15 V, ENBA = ENBB = 0 V IDD (1) (2) All A A A A The pullup / pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The peak output current rating is the combined current from the bipolar and MOSFET transistors. The pullup / pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The output resistance is the Rds(on) of the MOSFET transistor when the voltage on the driver output is less than the saturation voltage of the bipolar transistor. (a) (b) +5V 90% 90% INPUT INPUT 10% 10% 0V tD1 tf tD2 tF tF tF 16V 90% 90% tD1 OUTPUT 90% tD2 OUTPUT 10% 10% 0V Figure 1. Switching Waveforms for (a) Inverting Driver and (b) Noninverting Driver 4 Copyright (c) 2002-2011, Texas Instruments Incorporated UCC27423, UCC27424, UCC27425 SLUS545C - NOVEMBER 2002 - REVISED JULY 2011 www.ti.com 5V ENBx VIN_L VIN_H 0V tD3 tD4 VDD 90% OUTx 90% tR tF 10% 0V NOTE: The 10% and 90% thresholds depict the dynamics of the BiPolar output devices that dominate the power MOSFET transition through the Miller regions of operation. Figure 2. Switching Waveform for Enable to Output Terminal Functions TERMINAL I/O FUNCTION NO. NAME 1 ENBA I Enable input for the driver A with logic compatible threshold and hysteresis. The driver output can be enabled and disabled with this pin. It is internally pulled up to VDD with 100k resistor for active high operation. The output state when the device is disabled will be low regardless of the input state. 2 INA I Input A. Input signal of the A driver which has logic compatible threshold and hysteresis. If not used, this input should be tied to either VDD or GND. It should not be left floating. 3 GND 4 INB I Input B. Input signal of the A driver which has logic compatible threshold and hysteresis. If not used, this input should be tied to either VDD or GND. It should not be left floating. 5 OUTB O Driver output B. The output stage is capable of providing 4A drive current to the gate of a power MOSFET. 6 VDD I Supply. Supply voltage and the power input connection for this device. 7 OUTA O Driver output A. The output stage is capable of providing 4A drive current to the gate of a power MOSFET. 8 ENBB I Enable input for the driver B with logic compatible threshold and hysteresis. The driver output can be enabled and disabled with this pin. It is internally pulled up to VDD with 100k resistor for active high operation. The output state when the device is disabled will be low regardless of the input state. Common ground. This ground should be connected very closely to the source of the power MOSFET which the driver is driving. Copyright (c) 2002-2011, Texas Instruments Incorporated 5 UCC27423, UCC27424, UCC27425 SLUS545C - NOVEMBER 2002 - REVISED JULY 2011 www.ti.com APPLICATION INFORMATION General Information High frequency power supplies often require high-speed, high-current drivers such as the UCC27423/4/5 family. A leading application is the need to provide a high power buffer stage between the PWM output of the control IC and the gates of the primary power MOSFET or IGBT switching devices. In other cases, the driver IC is utilized to drive the power device gates through a drive transformer. Synchronous rectification supplies also have the need to simultaneously drive multiple devices which can present an extremely large load to the control circuitry. Driver ICs are utilized when it is not feasible to have the primary PWM regulator IC directly drive the switching devices for one or more reasons. The PWM IC may not have the brute drive capability required for the intended switching MOSFET, limiting the switching performance in the application. In other cases there may be a desire to minimize the effect of high frequency switching noise by placing the high current driver physically close to the load. Also, newer ICs that target the highest operating frequencies may not incorporate onboard gate drivers at all. Their PWM outputs are only intended to drive the high impedance input to a driver such as the UCC27423/4/5. Finally, the control IC may be under thermal stress due to power dissipation, and an external driver can help by moving the heat from the controller to an external package. Input Stage The input thresholds have a 3.3V logic sensitivity over the full range of VDD voltages; yet it is equally compatible with 0 to VDD signals. The inputs of UCC27423/4/5 family of drivers are designed to withstand 500-mA reverse current without either damage to the IC for logic upset. The input stage of each driver should be driven by a signal with a short rise or fall time. This condition is satisfied in typical power supply applications, where the input signals are provided by a PWM controller or logic gates with fast transition times (<200 ns). The input stages to the drivers function as a digital gate, and they are not intended for applications where a slow changing input voltage is used to generate a switching output when the logic threshold of the input section is reached. While this may not be harmful to the driver, the output of the driver may switch repeatedly at a high frequency. Users should not attempt to shape the input signals to the driver in an attempt to slow down (or delay) the signal at the output. If limiting the rise or fall times to the power device is desired, limit the rise or fall times to the power device, then an external resistance can be added between the output of the driver and the load device, which is generally a power MOSFET gate. The external resistor may also help remove power dissipation from the devoce package, as discussed in the section on Thermal Considerations. Output Stage Inverting outputs of the UCC27423 and OUTA of the UCC27425 are intended to drive external P-channel MOSFETs. Noninverting outputs of the UCC27424 and OUTB of the UCC27425 are intended to drive external N-channel MOSFETs. Each output stage is capable of supplying 4A peak current pulses and swings to both VDD and GND. The pullup/pulldown circuits of the driver are constructed of bipolar and MOSFET transistors in parallel. The peak output current rating is the combined current from the bipolar and MOSFET transistors. The output resistance is the RDS(on) of the MOSFET transistor when the voltage on the driver output is less than the saturation voltage of the bipolar transistor. Each output stage also provides a very low impedance to overshoot and undershoot due to the body diode of the external MOSFET. This means that in many cases, external-schottky-clamp diodes are not required. The UCC27423 family delivers 4A of gate drive where it is most needed during the MOSFET switching transition - at the Miller plateau region - providing improved efficiency gains. A unique BiPolar and MOSFET hybrid output stage in parallel also allows efficient current sourcing at low supply voltages. Source/Sink Capabilities During Miller Plateau Large power MOSFETs present a large load to the control circuitry. Proper drive is required for efficient, reliable operation. The UCC27423/4/5 drivers have been optimized to provide maximum drive to a power MOSFET during the Miller plateau region of the switching transition. This interval occurs while the drain voltage is swinging between the voltage levels dictated by the power topology, requiring the charging/discharging of the drain-gate capacitance with current supplied or removed by the driver device. [1] 6 Copyright (c) 2002-2011, Texas Instruments Incorporated UCC27423, UCC27424, UCC27425 SLUS545C - NOVEMBER 2002 - REVISED JULY 2011 www.ti.com Two circuits are used to test the current capabilities of the UCC27423 driver. In each case external circuitry is added to clamp the output near 5 V while the IC is sinking or sourcing current. An input pulse of 250 ns is applied at a frequency of 1 kHz in the proper polarity for the respective test. In each test there is a transient period where the current peaked up and then settled down to a steady-state value. The noted current measurements are made at a time of 200 ns after the input pulse is applied, after the initial transient. The first circuit in Figure 2 is used to verify the current sink capability when the output of the driver is clamped around 5V, a typical value of gate-source voltage during the Miller plateau region. The UCC27423 is found to sink 4.5A at VDD = 15V and 4.28A at VDD = 12V. The circuit shown in Figure 3 is used to test the current source capability with the output clamped to around 5 V with a string of Zener diodes. The UCC27423 is found to source 4.8 A at VDD = 15 V and 3.7 A at VDD = 12 V. VDD UCC27423 ENBA INPUT 1 2 3 4 ENBB INA OUTA GND INB VDD OUTB 8 DSCHOTTKY 10 7 C2 1 F 6 5 C3 100 F + VSUPPLY 5.5 V VSNS 1 F CER 100 F AL EL RSNS 0.1 UDG-01065 Figure 3. It should be noted that the current sink capability is slightly stronger than the current source capability at lower VDD. This is due to the differences in the structure of the bipolar-MOSFET power output section, where the current source is a P-channel MOSFET and the current sink has an N-channel MOSFET. In a large majority of applications it is advantageous that the turn-off capability of a driver is stronger than the turn-on capability. This helps to ensure that the MOSFET is held OFF during common power supply transients which may turn the device back ON. Parallel Outputs The A and B drivers may be combined into a single driver by connecting the INA/INB inputs together and the OUTA/OUTB outputs together. Then, a single signal can control the paralleled combination as shown in Figure 4. Copyright (c) 2002-2011, Texas Instruments Incorporated 7 UCC27423, UCC27424, UCC27425 SLUS545C - NOVEMBER 2002 - REVISED JULY 2011 www.ti.com VDD UCC27423 ENBA 1 ENBB 8 INPUT 2 INA 3 GND 4 INB OUTA DSCHOTTKY C2 1 F VDD 6 OUTB 10 7 5 C3 100F + DADJ 5.5 V VSNS 1 F CER 100F AL EL RSNS 0.1 UDG-01066 Figure 4. Operational Waveforms and Circuit Layout Figure 5 shows the circuit performance achievable with a single driver (1/2 of the 8-pin IC) driving a 10-nF load. The input pulsewidth (not shown) is set to 300ns to show both transitions in the output waveform. Note the linear rise and fall edges of the switching waveforms. This is due to the constant output current characteristic of the driver as opposed to the resistive output impedance of traditional MOSFET-based gate drivers. VDD INPUT UCC27423 ENBA 1 ENBB 2 INA 3 GND 4 INB OUTA 8 7 VDD 6 OUTB CLOAD 5 1 F CER 2.2 F UDG-01067 Figure 5. 8 Copyright (c) 2002-2011, Texas Instruments Incorporated UCC27423, UCC27424, UCC27425 SLUS545C - NOVEMBER 2002 - REVISED JULY 2011 www.ti.com Figure 6. In a power driver operating at high frequency, it is a significant challenge to get clean waveforms without much overshoot/undershoot and ringing. The low output impedance of these drivers produces waveforms with high di/dt. This tends to induce ringing in the parasitic inductances. Utmost care must be used in the circuit layout. It is advantageous to connect the driver IC as close as possible to the leads. The driver IC layout has ground on the opposite side of the output, so the ground should be connected to the bypass capacitors and the load with copper trace as wide as possible. These connections should also be made with a small enclosed loop area to minimize the inductance. VDD Although quiescent VDD current is very low, total supply current will be higher, depending on OUTA and OUTB current and the programmed oscillator frequency. Total VDD current is the sum of quiescent VDD current and the average OUT current. Knowing the operating frequency and the MOSFET gate charge (Qg), average OUT current can be calculated from: IOUT = Qg x f, where f is frequency For the best high-speed circuit performance, two VDD bypass capacitors are recommended tp prevent noise problems. The use of surface mount components is highly recommended. A 0.1F ceramic capacitor should be located closest to the VDD to ground connection. In addition, a larger capacitor (such as 1F) with relatively low ESR should be connected in parallel, to help deliver the high current peaks to the load. The parallel combination of capacitors should present a low impedance characteristic for the expected current levels in the driver application. Drive Current and Power Requirements The UCC27423/4/5 family of drivers are capable of delivering 4A of current to a MOSFET gate for a period of several hundred nanoseconds. High peak current is required to turn the device ON quickly. Then, to turn the device OFF, the driver is required to sink a similar amount of current to ground. This repeats at the operating frequency of the power device. A MOSFET is used in this discussion because it is the most common type of switching device used in high frequency power conversion equipment. References 1 and 2 discuss the current required to drive a power MOSFET and other capacitive-input switching devices. Reference 2 includes information on the previous generation of bipolar IC gate drivers. When a driver IC is tested with a discrete, capacitive load it is a fairly simple matter to calculate the power that is required from the bias supply. The energy that must be transferred from the bias supply to charge the capacitor is given by: E + 1 CV 2 , where C is the load capacitor and V is the bias voltage feeding the driver. 2 Copyright (c) 2002-2011, Texas Instruments Incorporated 9 UCC27423, UCC27424, UCC27425 SLUS545C - NOVEMBER 2002 - REVISED JULY 2011 www.ti.com There is an equal amount of energy transferred to ground when the capacitor is discharged. This leads to a power loss given by the following: P + 2 1 CV 2f , where f is the switching frequency. 2 This power is dissipated in the resistive elements of the circuit. Thus, with no external resistor between the driver and gate, this power is dissipated inside the driver. Half of the total power is dissipated when the capacitor is charged, and the other half is dissipated when the capacitor is discharged. An actual example using the conditions of the previous gate drive waveform should help clarify this. With VDD = 12V, CLOAD = 10nF, and f = 300kHz, the power loss can be calculated as: P = 10nF x (12)2 x (300kHz) = 0.432W With a 12V supply, this would equate to a current of: I + P + 0.432 W + 0.036 A V 12 V (1) The actual current measured from the supply was 0.037A, and is very close to the predicted value. But, the IDD current that is due to the IC internal consumption should be considered. With no load the IC current draw is 0.0027A. Under this condition the output rise and fall times are faster than with a load. This could lead to an almost insignificant, yet measurable current due to cross-conduction in the output stages of the driver. However, these small current differences are buried in the high frequency switching spikes, and are beyond the measurement capabilities of a basic lab setup. The measured current with 10nF load is reasonably close to that expected. The switching load presented by a power MOSFET can be converted to an equivalent capacitance by examining the gate charge required to switch the device. This gate charge includes the effects of the input capacitance plus the added charge needed to swing the drain of the device between the ON and OFF states. Most manufacturers provide specifications that provide the typical and maximum gate charge, in nC, to switch the device under specified conditions. Using the gate charge Qg, one can determine the power that must be dissipated when charging a capacitor. This is done by using the equivalence Qg = CeffV to provide the following equation for power: P + C V2 f + Q g f (2) This equation allows a power designer to calculate the bias power required to drive a specific MOSFET gate at a specific bias voltage. ENABLE UCC27423/4/5 provides dual Enable inputs for improved control of each driver channel operation. The inputs incorporate logic compatible thresholds with hysteresis. They are internally pulled up to VDD with 100k resistor for active high operation. When ENBA and ENBB are driven high, the drivers are enabled and when ENBA and ENBB are low, the drivers are disabled. The default state of the Enable pin is to enable the driver and therefore can be left open for standard operation. The output states when the drivers are disabled is low regardless of the input state. See the truth table of Table 1 for the operation using enable logic. Enable input are compatible with both logic signals and slow changing analog signals. They can be directly driven or a power-up delay can be programmed with a capacitor between ENBA, ENBB and AGND. ENBA and ENBB control input A and input B respectively. 10 Copyright (c) 2002-2011, Texas Instruments Incorporated UCC27423, UCC27424, UCC27425 SLUS545C - NOVEMBER 2002 - REVISED JULY 2011 www.ti.com Thermal Information The useful range of a driver is greatly affected by the drive power requirements of the load and the thermal characteristics of the IC package. In order for a power driver to be useful over a particular temperature range the package must allow for the efficient removal of the heat produced while keeping the junction temperature within rated limits. The UCC27423/4/5 family of drivers is available in three different packages to cover a range of application requirements. As shown in the power dissipation rating table, the SOIC-8 (D) and PDIP-8 (P) packages each have a power rating of around 0.5W with TA = 70C. This limit is imposed in conjunction with the power derating factor also given in the table. Note that the power dissipation in our earlier example is 0.432W with a 10nF load, 12VDD, switched at 300kHz. Thus, only one load of this size could be driven using the D or P package, even if the two onboard drivers are paralleled. The difficulties with heat removal limit the drive available in the older packages. The MSOP PowerPAD-8 (DGN) package significantly relieves this concern by offering an effective means of removing the heat from the semiconductor junction. As illustrated in Reference 3, the PowerPAD packages offer a leadframe die pad that is exposed at the base of the package. This pad is soldered to the copper on the PC board directly underneath the IC package, reducing the jc down to 4.7C/W. Data is presented in Reference 3 to show that the power dissipation can be quadrupled in the PowerPAD configuration when compared to the standard packages. The PC board must be designed with thermal lands and thermal vias to complete the heat removal subsystem, as summarized in Reference 4. This allows a significant improvement in heatsinking over that available in the D or P packages, and is shown to more than double the power capability of the D and P packages. Note that the PowerPADTM is not directly connected to any leads of the package. However, it is electrically and thermally connected to the substrate which is the ground of the device. References 1. Power Supply Seminar SEM-1400 Topic 2: Design And Application Guide For High Speed MOSFET Gate Drive Circuits, by Laszlo Balogh, Texas Instruments (SLUP133). 2. Application Note, Practical Considerations in High Performance MOSFET, IGBT and MCT Gate Drive Circuits, by Bill Andreycak, Texas Instruments ( SLUA105) 3. Technical Brief, PowerPad Thermally Enhanced Package, Texas Instruments (SLMA002) 4. Application Brief, PowerPAD Made Easy, Texas Instruments (SLMA004) Related Products PRODUCT DESCRIPTION PACKAGES UCC37323/4/5 Dual 4-A Low-Side Drivers MSOP-8 PowerPAD, SOIC-8, PDIP-8 UCC37321/2 Single 9-A Low-Side Driver with Enable MSOP-8 PowerPAD, SOIC-8, PDIP-8 TPS2811/12/13 Dual 2-A Low-Side Drivers with Internal Regulator TSSOP-8, SOIC-8, PDIP-8 TPS2814/15 Dual 2-A Low-Side Drivers with Two Inputs per Channel TSSOP-8, SOIC-8, PDIP-8 TPS2816/17/18/19 Single 2-A Low-Side Driver with Internal Regulator 5-Pin SOT-23 TPS2828/29 Single 2-A Low-Side Driver 5-Pin SOT-23 Copyright (c) 2002-2011, Texas Instruments Incorporated 11 UCC27423, UCC27424, UCC27425 SLUS545C - NOVEMBER 2002 - REVISED JULY 2011 www.ti.com TYPICAL CHARACTERISTICS SUPPLY CURRENT vs FREQUENCY (VDD = 8.0V) 100 100 80 80 10 nF IDD - Supply Current - mA IDD - Supply Current - mA SUPPLY CURRENT vs FREQUENCY (VDD = 4.5V) 60 40 4.7 nF 2.2 nF 20 10 nF 4.7 nF 60 40 2.2 nF 1 nF 20 1 nF 470 pF 470 pF 0 0 500 K 1M 1.5 M 0 2M 0 500 K f - Frequency - Hz 1M 1.5 M 2M f - Frequency - Hz Figure 7. Figure 8. SUPPLY CURRENT vs FREQUENCY (VDD = 12V) SUPPLY CURRENT vs FREQUENCY (VDD = 15V) IDD - Supply Current - mA 200 150 10 nF 4.7 nF 100 2.2 nF 50 1 nF 470 pF 0 0 500 K 1M 1.5 M 2M f - Frequency - Hz Figure 9. 12 Figure 10. Copyright (c) 2002-2011, Texas Instruments Incorporated UCC27423, UCC27424, UCC27425 SLUS545C - NOVEMBER 2002 - REVISED JULY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) SUPPLY CURRENT vs SUPPLY VOLTAGE (CLOAD = 2.2nF) SUPPLY CURRENT vs SUPPLY VOLTAGE (CLOAD = 4.7nF) 160 90 80 140 70 120 IDD - Supply Current - mA IDD - Supply Current - mA 2 MHz 60 50 1 MHz 40 30 500 kHz 20 2 MHz 100 1 MHz 80 60 500 kHz 40 200 kHz 200 kHz 20 10 0 100 kHz 100/50 kHz 4 6 8 12 10 VDD - Supply Voltage - V 14 16 0 50/20 kHz 4 9 14 Figure 11. Figure 12. SUPPLY CURRENT vs SUPPLY VOLTAGE (UCC27423) SUPPLY CURRENT vs SUPPLY VOLTAGE (UCC27424) Figure 13. Figure 14. Copyright (c) 2002-2011, Texas Instruments Incorporated 19 VDD - Supply Voltage - V 13 UCC27423, UCC27424, UCC27425 SLUS545C - NOVEMBER 2002 - REVISED JULY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) SUPPLY CURRENT vs SUPPLY VOLTAGE (UCC27425) RISE TIME/FALL TIME vs TEMPERATURE (UCC27423) 0.75 25 0.70 tr/tf - Rise/Fall Time - ms IDD - Supply Current - mA tr 20 0.65 Input = VDD 0.60 0.55 0.50 Input = 0 V 0.45 0.40 15 tf 10 5 0.35 0 0.30 4 6 8 10 12 VDD - Supply Voltage - V 14 14 16 -50 0 50 100 150 TJ - Temperature - C Figure 15. Figure 16. RISE TIME vs SUPPLY VOLTAGE FALL TIME vs SUPPLY VOLTAGE Figure 17. Figure 18. Copyright (c) 2002-2011, Texas Instruments Incorporated UCC27423, UCC27424, UCC27425 SLUS545C - NOVEMBER 2002 - REVISED JULY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) DELAY TIME (fD1) vs SUPPLY VOLTAGE (UCC27423) 30 38 28 36 26 24 22 4.7 nF 20 18 2.2 nF 16 32 4.7 nF 30 28 2.2 nF 26 470 pF 24 1 nF 470 pF 14 12 10 nF 34 10 nF tD2 - Delay Time - ns tD1 - Delay Time - ns DELAY TIME (fD2) vs SUPPLY VOLTAGE (UCC27423) 22 1 nF 4 6 8 10 12 20 14 16 4 VDD - Supply Voltage - V 6 8 10 12 VDD - Supply Voltage - V Figure 19. Figure 20. ENABLE THRESHOLD AND HYSTERESIS vs TEMPERATURE ENABLE RESISTANCE vs TEMPERATURE 14 16 3.0 W Enable threshold and hysteresis - V ENBL - ON 2.5 2.0 1.5 1.0 ENBL - OFF 0.5 ENBL - HYSTERESIS 0 -50 -25 0 25 50 75 TJ - Temperature - C Figure 21. Copyright (c) 2002-2011, Texas Instruments Incorporated 100 125 Figure 22. 15 UCC27423, UCC27424, UCC27425 SLUS545C - NOVEMBER 2002 - REVISED JULY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) OUTPUT BEHAVIOR vs SUPPLY VOLTAGE (INVERTING) OUTPUT BEHAVIOR vs SUPPLY VOLTAGE (INVERTING) 50 ms/div 50 ms/div Figure 23. Figure 24. OUTPUT BEHAVIOR vs VDD (INVERTING) OUTPUT BEHAVIOR vs VDD (INVERTING) VDD - Supply Voltage - V 1 V/div IN = VDD ENBL = VDD VDD OUT 0V 50 ms/div Figure 25. 16 10 nF Between Output and GND 50 ms/div Figure 26. Copyright (c) 2002-2011, Texas Instruments Incorporated UCC27423, UCC27424, UCC27425 SLUS545C - NOVEMBER 2002 - REVISED JULY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) OUTPUT BEHAVIOR vs VDD (NON-INVERTING) OUTPUT BEHAVIOR vs VDD (NON-INVERTING) 50 ms/div 50 ms/div Figure 27. Figure 28. OUTPUT BEHAVIOR vs VDD (NON-INVERTING) OUTPUT BEHAVIOR vs VDD (NON-INVERTING) VDD - Supply Voltage - V 1 V/div IN = GND ENBL = VDD VDD OUT 0V 50 ms/div Figure 29. Copyright (c) 2002-2011, Texas Instruments Incorporated 10 nF Between Output and GND 50 ms/div Figure 30. 17 UCC27423, UCC27424, UCC27425 SLUS545C - NOVEMBER 2002 - REVISED JULY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) INPUT THRESHOLD vs TEMPERATURE 2.0 VON - Input Threshold Voltage - V 1.9 VDD = 15 V 1.8 1.7 1.6 1.5 VDD = 10 V VDD = 4.5 V 1.4 1.3 1.2 -50 -25 0 25 50 75 100 125 TJ - Temperature - C Figure 31. REVISION HISTORY Changes from Revision B (November 2004) to Revision C Page * Changed temperature rating. ................................................................................................................................................ 1 * Changed ORDERING INFORMATION temperature range, three instances. ...................................................................... 2 * Changed Output current (OUTA, OUTB) DC from 0.3 A to 0.2 A. ....................................................................................... 3 * Changed ELECTRICAL CHARACTERISTICS temperature rating. ...................................................................................... 3 * Changed Low-level output level from 40 mV max to 45 mV max. ....................................................................................... 3 18 Copyright (c) 2002-2011, Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 18-Apr-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp UCC27423D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM UCC27423DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM UCC27423DGN ACTIVE MSOPPowerPAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM UCC27423DGNG4 ACTIVE MSOPPowerPAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM UCC27423DGNR ACTIVE MSOPPowerPAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM UCC27423DGNRG4 ACTIVE MSOPPowerPAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM UCC27423DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM UCC27423DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM UCC27423P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type UCC27423PE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type UCC27424D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM UCC27424DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM UCC27424DGN ACTIVE MSOPPowerPAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM UCC27424DGNG4 ACTIVE MSOPPowerPAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM UCC27424DGNR ACTIVE MSOPPowerPAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM UCC27424DGNRG4 ACTIVE MSOPPowerPAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM UCC27424DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM UCC27424DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Addendum-Page 1 (3) Samples (Requires Login) PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 18-Apr-2011 Status (1) UCC27424P ACTIVE UCC27424PE4 ACTIVE UCC27425D ACTIVE UCC27425DG4 ACTIVE UCC27425DGN Package Type Package Drawing PDIP Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ACTIVE MSOPPowerPAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM UCC27425DGNG4 ACTIVE MSOPPowerPAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM UCC27425DGNR ACTIVE MSOPPowerPAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM UCC27425DGNRG4 ACTIVE MSOPPowerPAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM UCC27425DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM UCC27425DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM UCC27425P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type UCC27425PE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type (3) Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) Addendum-Page 2 PACKAGE OPTION ADDENDUM www.ti.com (3) 18-Apr-2011 MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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OTHER QUALIFIED VERSIONS OF UCC27423, UCC27424, UCC27425 : * Automotive: UCC27423-Q1, UCC27424-Q1, UCC27425-Q1 * Enhanced Product: UCC27423-EP, UCC27424-EP NOTE: Qualified Version Definitions: * Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects * Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 15-Sep-2011 TAPE AND REEL INFORMATION *All dimensions are nominal Device UCC27423DGNR Package Package Pins Type Drawing MSOPPower PAD SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 UCC27423DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 UCC27424DGNR MSOPPower PAD DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 UCC27424DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 UCC27425DGNR MSOPPower PAD DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 UCC27425DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 15-Sep-2011 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) UCC27423DGNR MSOP-PowerPAD DGN 8 2500 364.0 364.0 27.0 UCC27423DR SOIC D 8 2500 340.5 338.1 20.6 UCC27424DGNR MSOP-PowerPAD DGN 8 2500 364.0 364.0 27.0 UCC27424DR SOIC D 8 2500 340.5 338.1 20.6 UCC27425DGNR MSOP-PowerPAD DGN 8 2500 364.0 364.0 27.0 UCC27425DR SOIC D 8 2500 340.5 338.1 20.6 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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