LS844 MONOLITHIC DUAL N-CHANNEL JFET Linear Systems Ultra Low Leakage Low Drift Monolithic Dual JFET The LS844 is a high-performance monolithic dual JFET featuring extremely low noise, tight offset voltage and low drift over temperature specifications, and is targeted for use in a wide range of precision instrumentation applications. The LS844 features a 5mV offset and 10-V/C drift. The 8 Pin P-DIP and 8 Pin SOIC provide ease of manufacturing, and the symmetrical pinout prevents improper orientation. (See Packaging Information). LS844 Applications: Wideband Differential Amps High-Speed,Temp-Compensated SingleEnded Input Amps High-Speed Comparators Impedance Converters and vibrations detectors. FEATURES LOW DRIFT | V GS12 / T| 10V/C LOW LEAKAGE IG = 15pA TYP. LOW NOISE en = 3nV/Hz TYP. LOW OFFSET VOLTAGE | V GS12| 5mV ABSOLUTE MAXIMUM RATINGS @ 25C (unless otherwise noted) Maximum Temperatures Storage Temperature 65C to +150C Operating Junction Temperature +150C Maximum Voltage and Current for Each Transistor - Note 1 VGSS Gate Voltage to Drain or Source 60V VDSO Drain to Source Voltage 60V IG(f) Gate Forward Current 50mA Maximum Power Dissipation Device Dissipation @ Free Air - Total 400mW @ +125C MATCHING CHARACTERISTICS @ 25C UNLESS OTHERWISE NOTED SYMBOL CHARACTERISTICS VALUE UNITS CONDITIONS | V GS12 / T| max. DRIFT VS. 10 V/C VDG=10V, ID=500A TEMPERATURE TA=55C to +125C | V GS12 | max. OFFSET VOLTAGE 5 mV VDG=10V, ID=500A ELECTRICAL CHARACTERISTICS @ 25C (unless otherwise noted) SYMBOL CHARACTERISTICS MIN. TYP. BVGSS Breakdown Voltage 60 BVGGO GateToGate Breakdown 60 TRANSCONDUCTANCE YfSS Full Conduction 1500 YfS Typical Operation 1000 1500 |YFS12 / Y FS| Mismatch 0.6 DRAIN CURRENT IDSS Full Conduction 1.5 5 |IDSS12 / IDSS| Mismatch at Full Conduction 1 GATE VOLTAGE VGS(off) or Vp Pinchoff voltage 1 VGS(on) Operating Range 0.5 GATE CURRENT IGmax. Operating 15 IGmax. High Temperature IGmax. Reduced VDG 5 IGSSmax. At Full Conduction OUTPUT CONDUCTANCE YOSS Full Conduction YOS Operating 0.2 |YOS12| Differential 0.02 COMMON MODE REJECTION CMR 20 log | V GS12/ V DS| 90 110 20 log | V GS12/ V DS| 85 NOISE NF Figure en Voltage CAPACITANCE CISS Input CRSS Reverse Transfer CDD DraintoDrain 0.5 MAX. UNITS V V CONDITIONS VDS = 0 ID=1nA I G= 1nA ID= 0 I S= 0 3 mho mho % VDG= 15V VDG= 15V 15 5 mA % VDG= 15V VGS= 0V 3.5 3.5 V V VDS= 15V VDS=15V ID= 1nA ID=500A 50 50 30 100 pA nA pA pA 20 2 0.2 mho mho mho dB 0.5 7 11 dB nV/Hz VGS= 0V f = 1kHz ID= 500A Click To Buy Note 1 - These ratings are limiting values above which the serviceability of any semiconductor may be impaired 8 3 VDG= 15V ID= 500A TA= +125C VDG = 3V ID= 500A VDG= 15V , VDS =0 VDG= 15V VDG= 15V VGS= 0V ID= 500A VDS = 10 to 20V ID=500A VDS = 5 to 10V ID=500A VDS= 15V VGS= 0V RG= 10M f= 100Hz NBW= 6Hz VDS=15V ID=500A f=1KHz NBW=1Hz VDS=15V ID=500A f=10Hz NBW=1Hz VDS= 15V, ID=500A pF VDG= 15V, ID=500A PDIP & SOIC (Top View) Available Packages: LS844 / LS844 in PDIP & SOIC LS844 / LS844 available as bare die Please contact Micross for full package and die dimensions Tel: +44 1603 788967 Email: chipcomponents@micross.com Web: http://www.micross.com/distribution Information furnished by Linear Integrated Systems and Micross Components is believed to be accurate and reliable. However, no responsibility is assumed for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Linear Integrated Systems.