SNAU118
LMK01801BEVAL Evaluation Board Operating Instructions
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LMK01801
Dual Clock Divider Buffer
Evaluation Board Operating Instructions
7 December 2011
LMK01801 EVAL
Texas Instruments, Inc.
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LMK01801BEVAL Evaluation Board Operating Instructions
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Table of Contents
TABLE OF CONTENTS ....................................................................................................................... 2
TABLE OF FIGURES........................................................................................................................... 3
GENERAL DESCRIPTION ................................................................................................................... 4
Block Diagram ........................................................................................................................................................... 4
Evaluation Board Kit Contents ................................................................................................................................... 5
Quick Start – Code Loader Mode ............................................................................................................................... 6
Quick Start – Pin Control Mode ................................................................................................................................. 7
Pin Control Modes ...................................................................................................................................................... 8
Using CodeLoader to Program the LMK01801 ......................................................................................................... 9
Evaluation Board Inputs/Out puts ............................................................................................................................. 12
RECOMMENDED TEST EQUIPMENT ................................................................................................. 14
APPENDIX A: CODELOADER USAGE .............................................................................................. 15
APPENDIX B: TYPICAL PHASE NOISE PERFORMANCE PLOTS ......................................................... 19
LMK01801 Sample Output Wavef orms ................................................................................................................... 25
LMK01801 Analog Delay Sample Data................................................................................................................... 26
APPENDIX C: SCHEMATICS ............................................................................................................ 28
Power ........................................................................................................................................................................ 28
Main ......................................................................................................................................................................... 29
Inputs ........................................................................................................................................................................ 30
Inputs Page 2 ............................................................................................................................................................ 31
Clock Outputs Page 1 ............................................................................................................................................... 32
Clock Outputs Page 2 ............................................................................................................................................... 33
Clock Outputs Page 3 ............................................................................................................................................... 34
APPENDIX D: BILL OF MATERIALS ................................................................................................ 35
Common Bill of Materials for Evaluation Boards .................................................................................................... 35
APPENDIX E: BALUN INFORMATION .............................................................................................. 38
Typical Balun Frequency Response ......................................................................................................................... 38
APPENDIX F: PROPERLY CONFIGURING LPT PORT ........................................................................ 39
LPT Driver Loading ................................................................................................................................................. 39
Correct LPT Port/Address ........................................................................................................................................ 39
Correct LPT Mode .................................................................................................................................................... 40
APPENDIX G: DIFFERENTIAL VOLTAGE MEASUREMENT TERMINOLOGY ....................................... 41
APPENDIXHI: TROUBLESHOOTING INFORMATION .......................................................................... 42
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Table of Figures
Figure 1 - LMK01801 Block Diagram ........................................................................................... 4
Figure 2 - Quick Start Diagram ...................................................................................................... 6
Figure 3 - Pin Control Mode Quick Start Diagram......................................................................... 7
Figure 4 – Selecting the LMK01801 .............................................................................................. 9
Figure 6 – Setting the 122.88 MHz VCXO Default mode ........................................................... 10
Figure 5 - Loading the Device ...................................................................................................... 10
Figure 7 - Setting Divide, CLKout_TYPE, Enabled for CLKout1 on "Clock Outputs" tab. ....... 11
Figure 8 - Setting LVCMOS modes. ............................................................................................ 11
Figure 9 - Port Setup tab ............................................................................................................... 15
Figure 10 - Clock Outputs tab ....................................................................................................... 16
Figure 11 - Bits/Pins tab. .............................................................................................................. 17
Figure 12 - LMK01801 Phase Noise @ 100 MHz with Output Divider = 1 ................................ 20
Figure 13 - LMK01801 Phase Noise @ 100 MHz with Output Divider = 4 ................................ 21
Figure 14 - LMK01801 Phase Noise @ 983.04 MHz with Output Divider = 1 ........................... 22
Figure 15 - LMK01801 Phase Noise @ 983.04 MHz with Output Divider = 4 ........................... 23
Figure 16 - Phase Noise Measurement Set-Up ............................................................................. 24
Figure 17 - Noisy vs. Clean Phase Noise ...................................................................................... 24
Figure 18 - LMK01801 Sample Clock Output Waveforms .......................................................... 25
Figure 19 - CLKout12 and CLKout13 No Analog Delay............................................................. 26
Figure 20 - CLKout12 with 100 pSec of delay relative to CLKout13.......................................... 27
Figure 21 - Typical Balun Frequency Response ........................................................................... 38
Figure 22 - Successfully Opened LPT Driver ............................................................................... 39
Figure 23 - Selecting the LPT Port ............................................................................................... 40
Figure 24 - Two Different Definitions .......................................................................................... 41
Figure 25 - Two Different Definitions .......................................................................................... 41
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LMK01801BEVAL Evaluation Board Operating Instructions
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General Description
The LMK01801 Evaluation Board simplifies evaluation of the LMK01801 Dual Clock Buffer
Divider. Configuring and controlling the board is accomplished using Texas Instrument’s
CodeLoader software, which can be downloaded from: http://www.ti.com/tool/codeloader. The
LMK01801 can also be configured to operate in a pin control mode via headers on the PCB.
Block Diagram
The block diagram in Figure 1 illustrates the functional architecture of the LMK01801 clock
divider buffer. The LMK01801 is a very low noise solution for clocking systems that require
distribution and frequency division of precision clocks. The LMK01801 features extremely low
residual noise, frequency division, digital and analog delay adjustments, and fourteen (14)
programmable differential outputs: LVPECL, LVDS and LVCMOS (2 outputs per differential
output). The LMK01801 features two independent inputs that can be driven differentially or in
single-ended mode. The first input drives output Bank A consisting of eight (8) outputs. The
second input drives output Bank B consisting of six (6) outputs.
Figure 1 - LMK01801 Block Diagram
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Evaluation Board Kit Contents
The evaluation board kit contains…
An LMK01801 Evaluation board.
LMK01801 Family quick start guide.
o Evaluation board instructions are downloadable from the product folder on Texas
Instument’s website, www.ti.com/.
CodeLoader uWire cable (LPT --> uWire).
A USB interface board can be purchased separately under NSID USB2UWIRE_IFACE.
The CodeLoader software will run on a Windows 2000 or Windows XP PC. The CodeLoader
software is used to program the internal registers of the LMK01801 device through a
MICROWIRETM interface.
Clock output configuration:
Clock Output Type Output Connector Installed
0 LVPECL Yes
1 LVPECL No
2 LVPECL Yes
3 LVPECL No
4 LVPECL Yes
5 LVPECL No
6 LVPECL Yes
7 LVPECL No
8 LVPECL Yes
9 LVPECL Yes
10 LVPECL Yes
11 LVPECL Yes
12 LVPECL Yes
13 LVPECL Yes
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Quick Start – Code Loader Mode
1. Connect a voltage of 3.3 volts to either the Vcc SMA connector or the alternate terminal
block.
2. Connect a reference clock from a signal generator or other source. Exact frequency
depends on programming.
3. Connect the uWire header to a computer parallel port with the CodeLoader cable. A
USB communication option is available, search at www.ti.com/ for: USB2UWIRE-
IFACE.
4. Install jumpers on TYPE0, TYPE1, TYPE2, DivVal0, DivVal1, DivVal2 in the middle
‘uWire’ (pins 3,5) position but NOT on EN_PIN_CTRL.
5. Program the device with CodeLoader. Ctrl-L m ust be pressed at least once to load all
registers once after CodeLoader is started or after restoring a Mode. CodeLoader is
available for download at www.ti.com/tool/codeloader.
6. Measurements may be made at any clock output if enabled by programming.
Figure 2 - Quick Start Dia gr am
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Quick Start – Pin Control Mode
1. Connect a voltage of 3.3 volts to either the Vcc SMA connector or the alternate connector.
2. Connect a reference clock from a signal generator or other source. Exact frequency
depends on programming.
3. Install a jumper on EN_PIN_CTRL header in either the High or Low position.
4. Install other jumpers on Type0, Type1, Type2, DivVal0, DivVal1, and DivVal2 headers
based on the configurations shown in Table 1 and Table 2.
Figure 3 - Pin Control Mo de Quick Start Diagram
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Pin Control Modes
For the following tables, Low is defined as installing a jumper between pins 5 and 6 on the
desired header. A HIGH is defined as installing a jumper between pins 1 and 2 on the desired
header.
If EN_PIN_CTRL = LOW (jumper installed between header positions 5 and 6) then the
following table describes possible output configurations:
Header Output Groups Header = Low Header = Middle Header = High
Type0 CLKout0 – CLKout3 LVDS Powerdown LVPECL
Type1 CLKout4 – CLKout7 LVDS LVCMOS (Norm/Inv) LVPECL
Type2 CLKout8 – CLKout13 LVDS LVCMOS (Norm/Inv) LVPECL
DivVal0 CLKout0-3 Divider ÷1 ÷4 ÷2
DivVal1 CLKout4-7 Divider ÷1 ÷4 ÷2
DivVal2 CLKout8-11 Divider ÷1 ÷4 ÷2
CLKout12-13 Divider ÷8 ÷512 ÷16
Table 1 - EN_PIN_CTRL = LOW Configuration
If EN_PIN_CTRL = HIGH (jumper installed between header positions 1 and 2) then the
following table describes possible output configurations:
Header Output Groups Header = Low Header = Middle Header = High
Type0
CLKout0 – CLKout3 LVDS
LVPECL LVPECL
CLKout4 – CLKout7 LVCMOS (Norm/Inv)
Type1 CLKout8 – CLKout11 LVDS LVCMOS (Norm/Inv) LVPECL
Type2 CLKout12-13 LVDS LVCMOS (Norm/Inv) LVPECL
DivVal0 CLKout0-7 Divider ÷1 ÷4 ÷2
DivVal1 CLKout8-11 Divider ÷1 ÷4 ÷2
DivVal2 CLKout12-13 Divider ÷4 ÷512 ÷16
Table 2 - EN_PIN_CTRL = HIGH Configuration
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Using CodeLoader to Program the LMK01801
The purpose of this section is to walk the user through using CodeLoader to make some
measurements with the LMK01801 device. For more information on CodeLoader refer to
Appendix A: CodeLoader Usage or the CodeLoader 4 instructions located at
http://www.ti.com/tool/codeloader/.
Before proceeding, be sure to follow the Quick Start section above to ensure proper connections.
1. Start CodeLoader 4 Application
Click “Start” “Programs” “CodeLoader 4” “CodeLoader 4”
The CodeLoader 4 program is installed by default to the CodeLoader 4 application group.
2. Select Device
Click “Select Device” “Clock Conditioners” “LMK01801A1”
Once started CodeLoader 4 will load the last used device. To load a new device click “Select
Device” from the menu bar, then select the subgroup and finally device to load. For this
example, the LMK01800A1 is chosen.
Selecting the device does cause the device to
be programmed. However, it is advisable to
do CTRL-L to ensure programming.
Fi
g
ure 4 – Selectin
g
the LMK01801
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3. Program/Load Device
Press “Ctrl – L”
Assuming the Port Settings are correct, it is now
possible to click “Keyboard Controls” “Load
Device” from the menu to program the device to the
current state of the newly loaded LMK01801 file. Ctrl-
L is the accelerator assigned to the Load Device option
and is very convenient.
Once the device has been loaded, by default
CodeLoader will automatically program changed
registers, so it is not necessary to load the device
again completely. It is possible to disable this functionality by ensuring there is no checkmark
by the “Options” “AutoReload with Changes.”
Since a default mode will be restored in the next step, th is step isn’t really needed but included to
emphasize the importance of pressing “Ctrl-L” to load the device at least once after starting
CodeLoader, restoring a mode, or restoring a saved setup using the File menu.
See Appendix A: CodeLoader Usage or the CodeLoader 4 instructions located at
http://www.ti.com/tool/codeloader for more information on port setup. Appendix H:
Troubleshooting Information contains information on troubleshooting communications.
4. Restoring a Defa ult Mode
Click “Mode” “122.88 MHz VCXO Default”; then
Press “Ctrl – L”
Figure 6 – Setting the 122.88 MHz VCXO Default mode
For the purposes of this walkthrough a default mode will be loaded to ensure a common starting
point. This is important because when CodeLoader is closed, it remembers the last settings used
for a particular device. By loading the default mode a common starting point is ensured.
Loading a mode does not automatically program the device so it is necessary to press
“Ctrl – L” again to program the device.
Figure 5 - Loading the Devi ce
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5. Enable Clock Outputs
To measure phase noise at the clock outputs,
1. Click on the “Bank A” tab,
2. Enable an output,
3. Then set the
a. CLKout Type,
b. divide value
Figure 7 - Setting Divide, CLKout_TYPE , Ena bl e d for CL Kout1 on "Clock Outp u ts" t ab.
4. Connect the clock output SMAs to a spectrum analyzer or signal source analyzer.
a. For LVDS, a balun is recommended such as the ADT2-1T (for frequency range of
0.4 MHz to 450 MHz).
b. For LVPECL,
i. A balun can be used, or
ii. One side of the LVPECL signal can be terminated with a 50 ohm load and
the other side can be run to the test equipment
single ended.
c. For LVCMOS,
i. One side of the LVCMOS signal can be
terminated with a 50 ohm load and the other
side can be run to the test equipment single
ended.
5. The phase noise may be measured with a spectrum analyzer
or signal source analyzer.
See Appendix B: Typical Phase Noise Performance Plots for phase noise plots of the clock
outputs.
Figure 8 - Setting
LVCMOS modes.
This CLKoutX frequency value is only valid if
the correct clock in value is specified. It may
not necessarily represent the actual frequency
unless manually entered. This is a
mathematical calculation only, not a measured
value.
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Evaluation Board Inputs/Outputs
The following table contains descriptions of the various inputs and outputs for the evaluation
board.
Table 3. LMK01801 Evaluation Board I/O
Connector Name Input/Output Description
CLKout0 /
CLKout0*,
CLKout2 /
CLKout2*,
CLKout4 /
CLKout4*,
CLKout6 /
CLKout6*,
CLKout8 /
CLKout8*,
CLKout9/
CLKout9*,
CLKout10 /
CLKout10*,
CLKout11/
CLKout11*,
CLKout12 /
CLKout12*,
CLKout13 /
CLKout13*
Output
Populated connectors.
Differential clock output pairs. All outputs are configured
in LVPECL mode.
On the evaluation board, all clock outputs are AC-coupled
to allow safe testing with RF test equipment.
All LVPECL/2VPECL clock outputs are
terminated to GND with a 240 ohm resistor, one on
each output pin of the pair.
Vcc Input
Populated connector.
DC power supply for the PCB. Removing R1, R2, or R3
allow for splitting the power to various devices on the
board.
Note: The LMK01801 Family contains internal voltage
regulators for the VCO, PLL and related circuitry. The
clock outputs do not have an internal regulator. A clean
power supply is required for best performance.
Vcc2 Input
Unpopulated connector.
Vcc input to power the output planes separately from the
Aux Plane. Refer to schematics for more information.
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Connector Name Input/Output Description
CLKin0/CLKin0*,
CLKin1/CLKin1* Input
Populated connectors.
The default board configuration is setup for a single-ended
reference source at CLKin0* (CLKin0 pin is AC-coupled
to ground).
If a DC-coupled clock is used to drive either of the inputs,
the high voltage level must be at least 2 volts and the low
voltage no greater than 0.4 volts.
uWire Input/Output
Populated connector.
10-pin header programming interface for the board. Of
Most important are the CLKuWi re, DATAuWire, and
LEuWire programming lines from this header. Each of
these signals, TEST, and SYNC0, and SYNC1 can be
monitored through test points on the board.
SYNC0,
SYNC1 Input Unpopulated connector.
Access to SYNC0 or SYNC1 of device.
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Recommended Test Equipment
Power Supply
The Power Supply should be a low noise power supply.
Phase Noise / Spectrum Analyzer
For measuring phase noise an Agilent E5052A Signal Source Analyzer is recommended. An
Agilent E4445A PSA Spectrum Analyzer with the Phase Noise option is also usable although the
architecture of the E5052A is superior for phase noise measurements. At frequencies less than
100 MHz the local oscillator noise of the E4445A is too high and measurements will reflect the
E4445A’s internal local oscillator performance, not the device under test.
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Appendix A: CodeLoader Usage
CodeLoader is used to program the evaluation board with either an LPT port using the included
CodeLoader cable or with a USB port using the optional USB <--> uWire cable available from
http://www.ti.com/. The part number is USB2UWIRE-IFACE.
Port Setup Tab
Figure 9 - Port Setup tab
On the Port Setup tab, the user may select the type of communication port (USB or Parallel) that
will be used to program the device on the evaluation board. If parallel port is selected, the user
should ensure that the correct port address is entered.
The Pin Configuration field is hardware dependent and normally SHOULD NOT be changed by
the user. Figure 9 shows the default settings.
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Clock Outputs Tab
Figure 10 - Clock Outputs tab
The clock outputs tab allows the user to Enable/Disable individual clock outputs, select the clock
mode (Bypass/Divided/Delayed/Divided & Delayed – for outputs 12 and 13), set the clock
output delay value (if delay is enabled for outputs 12 and 13 only), and the clock output divider
value (2, 4, 6, …, 510 for clock outputs 12 and 13 or 1-8 for clock outputs 0 - 11).
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Bits/Pins Tab
Figure 11 - Bits/Pins tab.
The Bits/Pins tab allows the user to program bits directly. Many of which are not available on
other tabs. Refer to the datasheet for more detailed information. The bits available are:
Common Box
o RESET - Set the reset bit. This will reset the device. In a normal application it is
not necessary to program this bit clear since it is auto-clearing. However in the
CodeLoader software, RESET must be clicked again (cleared) to not cause a reset
every time R7 is programmed.
o POWERDOWN - Place the device in powerdown mode.
Program Pins Box – These pins only have effect if the PWB headers are in the uWire
position (3-5). See Figure 2 - Quick Start Diagram for the correct configuration.
o EN_PIN_CTRL – Sets the control of the output via uWire or pins
o SYNC0 – Set high or low voltage on SYNC0 pin. Checked is high voltage.
o TRIGGER – Set high or low voltage on pin 10 of uWire header.
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Registers Tab
The registers tab shows the value of each register. This is convenient for programming the
device to the desired settings, then recording the hex values for programming in your own
application. The “Export register values in hex to text file” button will allow these register
values to be saved to a text file.
By clicking in the “bit field” it is possible to manually change the value of registers by typing ‘1’
and ‘0.’
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Appendix B: Typical Phase Noise Performance Plots
Clock Outputs
The LMK01801 Family features LVDS, LVPECL, 2VPECL, and LVCMOS types of outputs.
Include are the phase noise plots for the following outputs.
Device CLKoutX Output Divide Output Type
LMK01801A1 8 1 LVPECL
LMK01801A1 8 4 LVPECL
LMK01801A1 8 1 2VPECL
LMK01801A1 8 4 2VPECL
LMK01801A1 4 1 LVDS
LMK01801A1 4 4 LVDS
LMK01801A1 4 1 LVCMOS(Norm/Inv)
LMK01801A1 4 4 LVCMOS(Norm/Inv)
Table 4 - Phase Noise Output Test Co nfiguration
Clock Output Measurement Technique
The measurement technique for each output type varies.
LVPECL/2VPECL – Measured by using an Minicircuits ADT2-1T balun on the input and on the
output.
LVCMOS and LVDS – Measured by using an Minicircuits ADT2-1T balun on the output and
single ended input.
Parameter Test Case 1 Test Case 2 Test Case 3 Test Case 4
Input Source Wenzel XTAL Wenzel XTAL SMHU Rohde&Schwarz
SMHU
Input Frequency 100 MHz 100 MHz 983.04 MHz 983.04 MHz
Input Power 0 dBm 0 dBm 0 dBm 0 dBm
Output Divider 1 4 1 4
Figure Figure 12 Figure 13 Figure 14 Figure 15
Table 5 - LMK01801 test conditions
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LMK01801 Phase Noise, CLKin = 100 MHz, Output Divider = 1
Figure 12 - LMK01801 Phase Noise @ 100 MH z with Output Divider = 1
‐180
‐170
‐160
‐150
‐140
‐130
‐120
‐110
‐100
‐90
‐80
10.0E+0 1.0E+3 100.0E+3 10.0E+6
PhaseNoisewithOutputDivider=1
Wenzel100MHzXTAL
CLKout8_2VPECL
CLKout8_LVPECL
CLKout4_LVDS
CLKout4_LVCMOS(NORM/INV)
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LMK01801 Phase Noise, CLKin = 100 MHz, Output Divider = 4
Figure 13 - LMK01801 Phase Noise @ 100 MH z with Output Divider = 4
‐180
‐170
‐160
‐150
‐140
‐130
‐120
‐110
‐100
‐90
‐80
10.0E+0 100.0E+0 1.0E+3 10.0E+3 100.0E+3 1.0E+6
PhaseNoisewithOutputDivider=4
Wenzel100MHzXTAL
CLKout8_2VPECL
CLKout8_LVPECL
CLKout4_LVDS
CLKout4_LVCMOS(NORM/INV)
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LMK01801 Phase Noise, CLKin = 983.04 MHz, Output Divider = 1
Figure 14 - LMK01801 Phase Noise @ 983.04 MHz with Output Divider = 1
‐180
‐160
‐140
‐120
‐100
‐80
‐60
10.0E+0 100.0E+0 1.0E+3 10.0E+3 100.0E+3 1.0E+6 10.0E+6
PhaseNoisewithDivider=1
LVDS/1
LVCMOS/1
2VPECL/1
LVPECL/1
SMHU
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LMK01801 Phase Noise, CLKin = 983.04 MHz, Output Divider = 4
Figure 15 - LMK01801 Phase Noise @ 983.04 MHz with Output Divider = 4
‐180
‐160
‐140
‐120
‐100
‐80
‐60
10.0E+0 100.0E+0 1.0E+3 10.0E+3 100.0E+3 1.0E+6 10.0E+6
PhaseNoisewithDivider=4
LVDS/4
LVCMOS/4
2VPECL/4
LVPECL/4
SMHU
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Phase Noise Measurement
Si gnal
Source LMK01801 Agilent
5052A
RF Output @
1 GHz, 0dBm CL Kin0 or
CLKin1 CLKoutX /
CLKoutX*
!
Power
Supply
Figure 16 - Phase Noise Measurement Set-Up
The phase noise of the signal source will impact the measured phase noise of the LMK01801.
Figure 17 - Noisy vs. Clean Phase Noise
Noisy Signal
Source!
Clean Signal
Source!