LC2MOS 8-/16-Channel
High Performance Analog Multiplexers
ADG406/ADG407/ADG426
Rev. B
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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Fax: 781.461.3113 ©1994–2010 Analog Devices, Inc. All rights reserved.
FEATURES
44 V supply maximum ratings
VSS to VDD analog signal range
Low on resistance (80 Ω maximum)
Low power
Fast switching
tON < 160 ns
tOFF < 150 ns
Break-before-make switching action
APPLICATIONS
Audio and video routing
Automatic test equipment
Data acquisition systems
Battery powered systems
Sample hold systems
Communication systems
Avionics
PRODUCT HIGHLIGHTS
1. Extended Signal Range.
2. The ADG406/ADG407/ADG426 are fabricated on an
enhanced LC2MOS process giving an increased signal
range which extends to the supply rails.
3. Low Power Dissipation.
4. Low RON.
5. Single/Dual Supply Operation.
6. Single Supply Operation.
7. For applications where the analog signal is unipolar, the
ADG406/ADG407/ADG426 can be operated from a single
rail power supply. The parts are fully specified with a single
+12 V power supply and remain functional with single
supplies as low as +5 V.
FUNCTIONAL BLOCK DIAGRAMS
00026-001
S1
S16
A0
D
A3
ADG406
A1 A2 EN
1 OF 16
DECODER
Figure 1.
00026-002
S1A
S8B
DA
ADG407
S8A
S1B
DB
ENA0 A1 A2
1 OF 8
DECODER
Figure 2.
00026-003
S1
S16
A0
D
A3
ADG426
A1 A2 EN
DECODER/
LATCHES
WR
RS
Figure 3.
ADG406/ADG407/ADG426
Rev. B | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Product Highlights ........................................................................... 1
Functional Block Diagrams ............................................................. 1
Revision History ............................................................................... 2
General Description ......................................................................... 3
Specifications ..................................................................................... 4
Dual Supply ................................................................................... 4
Single Supply ................................................................................. 6
ADG426 Timing Diagrams ..........................................................7
Absolute Maximum Ratings ............................................................8
ESD Caution...................................................................................8
Pin Configurations and Function Descriptions ............................9
Typical Performance Characteristics ........................................... 12
Test Circuits ..................................................................................... 15
Terminology .................................................................................... 18
Outline Dimensions ....................................................................... 19
Ordering Guide .......................................................................... 20
REVISION HISTORY
5/10—Rev. A to Rev. B
Changes to Ordering Guide .......................................................... 20
6/09—Rev. 0 to Rev. A
Updated Format .................................................................. Universal
Removed T Grade ............................................................... Universal
Added Table 4 .................................................................................... 9
Added Table 6 .................................................................................. 10
Added Table 8 .................................................................................. 11
Updated Outline Dimensions ....................................................... 18
Changes to Ordering Guide .......................................................... 19
4/94—Revision 0: Initial Version
ADG406/ADG407/ADG426
Rev. B | Page 3 of 20
GENERAL DESCRIPTION
The ADG406, ADG407, and ADG426 are monolithic CMOS
analog multiplexers. The ADG406 and ADG426 switch one of
sixteen inputs to a common output as determined by the 4-bit
binary address lines: A0, A1, A2, and A3. The ADG426 has
on-chip address and control latches that facilitate microprocessor
interfacing. The ADG407 switches one of eight differential
inputs to a common differential output as determined by the
3-bit binary address lines A0, A1 and A2. An EN input on all
devices is used to enable or disable the device. When disabled,
all channels are switched off.
The ADG406/ADG407/ADG426 are designed on an enhanced
LC2MOS process that provides low power dissipation yet gives
high switching speed and low on resistance. These features make
the parts suitable for high speed data acquisition systems and
audio signal switching. Low power dissipation makes the parts
suitable for battery powered systems. Each channel conducts
equally well in both directions when on and has an input signal
range which extends to the supplies. In the off condition, signal
levels up to the supplies are blocked. All channels exhibit break-
before-make switching action preventing momentary shorting
when switching channels. Inherent in the design is low charge
injection for minimum transients when switching the digital
inputs.
ADG406/ADG407/ADG426
Rev. B | Page 4 of 20
SPECIFICATIONS
DUAL SUPPLY
VDD = +15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted.
Table 1.
Parameter1 +25°C −40°C to +85°C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range VSS to VDD V
RON 50 Ω typ VD = ±10 V, IS = −1 mA
80 125 Ω max VDD = +13.5 V, VSS = −13.5 V
RON Match 4 Ω typ VD = 0 V, IS = −1 mA
LEAKAGE CURRENTS VDD = +16.5 V, VSS = −16.5 V
Source Off Leakage IS (Off) ±0.5 ±20 nA max VD = ±10 V, VS = +10 V, see Figure 26
Drain Off Leakage ID (Off) VD = ±10 V, VS = +10 V; see Figure 27
ADG406, ADG426 ±1 ±20 nA max
ADG407 ±1 ±20 nA max
Channel On Leakage ID, IS (On) VS = VD = ±10 V; see Figure 28
ADG406, ADG426 ±1 ±20 nA max
ADG407 ±1 ±20 nA max
DIGITAL INPUTS
Input High Voltage, VINH 2.4 V min
Input Low Voltage, VINL 0.8 V max
Input Current
IINL or IINH ±1 A max VIN = 0 or VDD
CIN, Digital Input Capacitance 8 pF typ f = 1 MHz
DYNAMIC CHARACTERISTICS2
tTRANSITION 120 ns typ RL = 300 Ω, CL = 35 pF; V1 = ±10 V, V2 = +10 V; see Figure 29
150 250 ns max
Break Before Make Delay, tOPEN 10 10 ns min RL = 300 Ω, CL = 35 pF; VS = +5 V, see Figure 30
tON (EN, WR) 120 175 ns typ RL = 300 Ω, CL = 35 pF; VS = 5 V, see Figure 31
160 225 ns max
tOFF (EN, RS) 110 130 ns typ RL = 300 Ω, CL = 35 pF; VS = 5 V, see Figure 31
150 180 ns max
ADG426 Only
tW, Write Pulse Width 100 ns min
tS, Address, Enable Setup Time 100 ns min
tH, Address, Enable Hold Time 10 ns min
tRS, Reset Pulse Width 100 ns min VS = +5 V
Charge Injection 8 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF;
See Figure 34
Off Isolation −75 dB typ RL = 1 k Ω, f = 100 kHz;
V
EN = 0 V, see Figure 35
Channel-to-Channel Crosstalk 85 dB typ RL = 1 k Ω, f = 100 kHz, see Figure 36
CS (Off) 5 pF typ f = 1 MHz
CD (Off) f = 1 MHz
ADG406, ADG426 50 pF typ
ADG407 25 pF typ
CD, CS (On) f = 1 MHz
ADG406, ADG426 60 pF typ
ADG407 40 pF typ
ADG406/ADG407/ADG426
Rev. B | Page 5 of 20
Parameter1 +25°C −40°C to +85°C Unit Test Conditions/Comments
POWER REQUIREMENTS VDD = +16.5 V, VSS = −16.5 V
IDD 1 A typ VIN = 0 V, VEN = 0 V
5 A max
ISS 1 A typ
5 A max
IDD 100 A typ VIN = 0 V, VEN = 2.4 V
200 500 A max
ISS 1 A typ
5 A max
1 Temperature ranges is −40°C to +85°C.
2 Guaranteed by design, not subject to production test.
ADG406/ADG407/ADG426
Rev. B | Page 6 of 20
SINGLE SUPPLY
VDD = +12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 2.
Parameter1 +25°C −40°C to +85°C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range 0 to VDD V
RON 90 Ω typ VD = +3 V, +8.5 V, IS = −1 mA;
125 200 Ω max VDD = +10.8 V
LEAKAGE CURRENTS VDD = +13.2 V
Source Off Leakage IS (Off) ±0.5 ±20 nA max VD = 8 V/0.1 V, VS = 0.1 V/8 V; see Figure 26
Drain Off Leakage ID (Off) VD = 8 V/0.1 V, VS = 0.1 V/8 V; see Figure 27
ADG406, ADG426 ±1 ±20 nA max
ADG407 ±1 ±20 nA max
Channel On Leakage ID, IS (On) VS = VD = 8 V/0.1 V, see Figure 28
ADG406, ADG426 ±1 ±20 nA max
ADG407 ±1 ±20 nA max
DIGITAL INPUTS
Input High Voltage, VINH 2.4 V min
Input Low Voltage, VINL 0.8 V max
Input Current
IINL or IINH ±1 µA max VIN = 0 or VDD
CIN, Digital Input Capacitance 8 pF typ f = 1 MHz
DYNAMIC CHARACTERISTICS2
tTRANSITION 180 ns typ RL = 300 Ω, CL = 35 pF; V1 = 8 V/0 V, V2 = 0 V/8 V; see Figure 29
220 350 ns max
Break Before Make Delay, tOPEN 10 ns typ RL = 300 Ω, CL = 35 pF; VS = 5 V, see Figure 30
tON (EN, WR) 180 ns typ RL = 300 Ω, CL = 35 pF;
240 350 ns max VS = +5 V, see Figure 31
tOFF (EN, RS) 135 ns typ RL = 300 Ω, CL = 35 pF; VS = 5 V, see Figure 31
180 220 ns max
ADG426 Only
tW, Write Pulse Width 100 ns min
tS, Address, Enable Setup Time 100 ns min
tH, Address, Enable Hold Time 10 ns min
tRS, Reset Pulse Width 100 ns min VS = +5 V
Charge Injection 5 pC typ VS = 6 V, RS = 0 Ω, CL = 1 nF; see Figure 34
Off Isolation −75 dB typ RL = 1 kΩ, f = 100 kHz; see Figure 35
Channel-to-Channel Crosstalk 85 dB typ RL = 1 kΩ, f = 100 kHz; see Figure 36
CS (Off) 8 pF typ f = 1 MHz
CD (Off) f = 1 MHz
ADG406, ADG426 80 pF typ
ADG407 40 pF typ f = 1 MHz
CD, CS (On)
ADG406, ADG426 100 pF typ
ADG407 50 pF typ
POWER REQUIREMENTS VDD = +13.2 V
IDD 1 µA typ VIN = 0 V, VEN = 0 V
5 µA max
IDD 100 µA typ VIN = 0 V, VEN = 2.4 V
200 500 µA max
1 Temperature range is −40°C to +85°C.
2 Guaranteed by design, not subject to production test.
ADG406/ADG407/ADG426
Rev. B | Page 7 of 20
ADG426 TIMING DIAGRAMS
00026-009
50% 50%
2V
0.8V
3
V
0V
3V
A
0, A1, A2, (A3)
EN 0V
t
W
t
S
t
H
WR
Figure 4. Timing Sequence for Latching the Switch Address and Enable Inputs
Figure 4 shows the timing sequence for latching the switch
address and enable inputs. The latches are level sensitive;
therefore, while WR is held low, the latches are transparent and
the switches respond to the address and enable inputs. This
input data is latched on the rising edge of WR.
00026-010
3
V
0V
0V
50% 50%
t
W
RS
t
OFF
(RS)
SWITCH
OUTPUT
V
0
0.8V
0
Figure 5. Reset Pulse Width and Reset Turn Off Time
Figure 5 shows the reset pulse width, trs, and the reset turn off
time, tOFF (RS).
Note that all digital input signals rise and fall times are
measured from 10% to 90% of 3 V; tR = tF = 20 ns.
ADG406/ADG407/ADG426
Rev. B | Page 8 of 20
ABSOLUTE MAXIMUM RATINGS
TA = 25°C unless otherwise noted.
Table 3.
Parameter Rating
VDD to VSS 44 V
VDD to GND −0.3 V to +25 V
VSS to GND +0.3 V to −25 V
Analog, Digital Inputs1 VSS − 2 V to VDD + 2 V or 20 mA,
whichever occurs first
Continuous Current, S or D 20 mA
Peak Current, S or D 40 mA
(Pulsed at 1 ms, 10% duty
cycle max)
Operating Temperature Range
Industrial (B Version) −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
Plastic Package
θJA, Thermal Impedance 75°C/W
Lead Temperature, Soldering
(10 sec)
260°C
PLCC Package
θJA, Thermal Impedance 80°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C
SSOP Package
θJA, Thermal Impedance 122°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C
1 Overvoltages at A, S, D, WR, or RS will be clamped by internal diodes. Current
should be limited to the maximum ratings given.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ADG406/ADG407/ADG426
Rev. B | Page 9 of 20
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
V
DD
NC
NC
S16
D
28
V
SS
27
S8
26
S7
25
S15
S14
S13
S6
24
S5
23
S4
22
S12 S3
21
S11 S2
20
S10 S1
19
S9 EN
18
GND A0
17
NC A1
16
A3 A2
15
NC = NO CONNECT
ADG406
TOP VIEW
(Not to Scale)
00026-004
1
2
5
6
7
8
9
10
11
12
14
13
3
4
Figure 6. 28-Lead PDIP
1282726234
5
6
7
8
9
10
11
25
24
23
22
21
20
19
NC = NO CONNECT
S15
S14
S13
S12
S11
S10
S9
S7
S6
S5
S4
S3
S2
S1
S16
NC
NC
V
DD
D
V
SS
S8
GND
NC
A3
A2
A1
A0
EN
PIN 1
INDENTFIER
ADG406
TOP VIEW
(Not to scale)
12 13 14 15 16 17 18
00026-005
Figure 7. 28-Lead PLCC
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 VDD Most Positive Power Supply Potential.
2, 3, 13 NC No Connect.
4 to 11 S16 to S9 Source Terminal 16 to Source Terminal 9. These pins can be inputs or outputs.
12 GND Ground (0 V) Reference.
14 to 17 A3 to A0 Logic Control Input.
18 EN Active High Digital Input. When this pin is low, the device is disabled and all switches are turned off. When this pin
is high, the Ax logic inputs determine which switch is turned on.
19 to 26 S1 to 8 Source Terminal 1 to Source Terminal 8. These pins can be inputs or outputs.
27 VSS Most Negative Power Supply Potential. In single-supply applications, this pin can be connected to ground.
28 D Drain Terminal. This pin can be an input or an output.
Table 5. Truth Table (ADG406)
A3 A2 A1 A0 EN On Switch
X X X X 0 None
0 0 0 0 1 1
0 0 0 1 1 2
0 0 1 0 1 3
0 0 1 1 1 4
0 1 0 0 1 5
0 1 0 1 1 6
0 1 1 0 1 7
0 1 1 1 1 8
1 0 0 0 1 9
1 0 0 1 1 10
1 0 1 0 1 11
1 0 1 1 1 12
1 1 0 0 1 13
1 1 0 1 1 14
1 1 1 0 1 15
1 1 1 1 1 16
ADG406/ADG407/ADG426
Rev. B | Page 10 of 20
VDD 1
DB 2
NC 3
S8B 4
DA28
VSS
27
S8A26
S7A25
S7B 5
S6B 6
S5B 7
S6A
24
S5A23
S4A22
S4B 8S3A
21
S3B 9S2A20
S2B 10 S1A19
S1B 11 EN18
GND 12 A0
17
NC 13 A1
16
NC 14 A2
15
NC = NO CONNECT
ADG407
TOP VIEW
(Not to Scale)
00026-006
Figure 8. 28-Lead PDIP
1282726234
5
6
7
8
9
10
11
25
24
23
22
21
20
19
NC = NO CONNECT
S7B
S6B
S5B
S4B
S3B
S2B
S1B
S7A
S6A
S5A
S4A
S3A
S2A
S1A
S8B
NC
DB
VDD
DA
VSS
S8A
GND
NC
NC
A2
A1
A0
EN
PIN 1
INDENTFIER
ADG407
TOP VIEW
(Not to scale)
12 13 14 15 16 17 18
00026-007
Figure 9. 28-Lead PLCC
Table 6. Pin Function Descriptions
Pin No. Mnemonic Description
1 VDD Most Positive Power Supply Potential.
2 DB Drain Terminal B. This pin can be an input or an output.
3, 13, 14 NC No Connect.
4 to 11 S8B to S1B Source Terminal 8B to Source Terminal 1B. These pins can be inputs or outputs.
12 GND Ground (0 V) Reference.
15 to 17 A2 to A0 Logic Control Input.
18 EN Active High Digital Input. When this pin is low, the device is disabled and all switches are turned off. When this pin
is high, the Ax logic inputs determine which switch is turned on.
19 to 26 S1A to S8A Source Terminal 1A to Source Terminal 8A. These pins can be inputs or outputs.
27 VSS Most Negative Power Supply Potential. In single-supply applications, this pin can be connected to ground.
28 DA Drain Terminal A. This pin can be an input or an output.
Table 7. Truth Table (ADG407)
A2 A1 A0 EN On Switch Pair
X X X 0 None
0 0 0 1 1
0 0 1 1 2
0 1 0 1 3
0 1 1 1 4
1 0 0 1 5
1 0 1 1 6
1 1 0 1 7
1 1 1 1 8
ADG406/ADG407/ADG426
Rev. B | Page 11 of 20
00026-008
V
DD 1
NC
2
3
S16
4
D
28
V
SS
27
S8
26
S7
25
S15
5
S14
6
S13
7
S6
24
S5
23
S4
22
S12
8
S3
21
S11
9
S2
20
S10
10
S1
19
S9
11
EN
18
GND
12
A0
17
A1
16
13
A3
14
A2
15
NC = NO CONNECT
ADG426
TOP VIEW
(Not to Scale)
WR
RS
Figure 10. 28-Lead PDIP/SSOP
Table 8. Pin Function Descriptions
Pin No. Mnemonic Description
1 VDD Most Positive Power Supply Potential.
2 NC No Connect.
3 RS Active Low Logic Input. When this pin is low, all switches are open, and address and enable latches registers are
cleared to 0.
4 to 11 S16 to S9 Source Terminal 16 to Source Terminal 9. These pins can be inputs or outputs.
12 GND Ground (0 V) Reference.
13 WR The rising edge of the WR signal latches the state of the address control lines and the enable line.
14 to 17 A3 to A0 Logic Control Input.
18 EN Active High Digital Input. When this pin is low, the device is disabled and all switches are turned off. When this pin
is high, the Ax logic inputs determine which switch is turned on.
19 to 26 S1 to S8 Source Terminal 1 to Source Terminal 8. These pins can be inputs or outputs.
27 VSS Most Negative Power Supply Potential. In single-supply applications, this pin can be connected to ground.
28 D Drain Terminal. This pin can be an input or an output.
Table 9. Truth Table (ADG426)
A3 A2 A1 A0 EN WR RS On switch
X X X X X 1 Retains previous switch condition
X X X X X X 0 None (address and enable latches cleared)
X X X X 0 0 1 None
0 0 0 0 1 0 1 1
0 0 0 1 1 0 1 2
0 0 1 0 1 0 1 3
0 0 1 1 1 0 1 4
0 1 0 0 1 0 1 5
0 1 0 1 1 0 1 6
0 1 1 0 1 0 1 7
0 1 1 1 1 0 1 8
1 0 0 0 1 0 1 9
1 0 0 1 1 0 1 10
1 0 1 0 1 0 1 11
1 0 1 1 1 0 1 12
1 1 0 0 1 0 1 13
1 1 0 1 1 0 1 14
1 1 1 0 1 0 1 15
1 1 1 1 1 0 1 16
ADG406/ADG407/ADG426
Rev. B | Page 12 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
150
0
–15 15–10–50 510
120
90
60
30
00026-011
R
ON
(Ω)
V
D
(V
S
) (V)
V
DD
= +15V
V
SS
= –15V
V
DD
= +10V
V
SS
= –10V
V
DD
= +12V
V
SS
= –12V
V
DD
= +5V
V
SS
=–5V
T
A
= 25°C
Figure 11. RON as a Function of VD (VS): Dual Supplies
100
0
–15 15–10–50 510
80
60
40
20
00026-012
R
ON
(Ω)
V
D
(V
S
) (V)
V
DD
= +15V
V
SS
= –15V
25°C
125°C
85°C
Figure 12. RON as a Function of VD (VS) for Different Temperatures
0.10
–0.02
–15 15–10–50 510
0.06
0.08
0.04
0.02
0
00026-013
LEAKAGE CURRENT (nA)
V
D
(V
S
) (V)
V
DD
= +15V
V
SS
= –15V
T
A
=+25°C
I
D
(OFF)
I
S
(OFF)
I
D
(ON)
Figure 13. Leakage Currents as a Function of VD (VS)
400
0012.5 5.0 7.5 10 12.5
200
250
300
350
150
100
50
00026-014
R
ON
(Ω)
V
D
(V
S
) (V)
5
T
A
= 25°C
V
DD
= +5V
V
SS
=0V
V
DD
= +10V
V
SS
=0V
V
DD
= +15V
V
SS
= 0V
V
DD
= +12V
V
SS
=0V
Figure 14. RON as a Function of VD (VS): Single Supplies
150
001246810
120
90
60
30
00026-015
R
ON
(Ω)
V
D
(V
S
) (V)
2
V
DD
= 12V
V
SS
=0V
25°C
125°C
85°C
Figure 15. RON as a Function of VD (VS) for Different Temperatures
0.02
–0.02 01246810
0.01
0
–0.01
00026-016
LEAKAGE CURRENT (nA)
V
D
(V
S
) (V)
2
V
DD
= +12V
V
SS
=0V
T
A
=+25°C
I
S
(OFF)
I
D
(OFF)
I
D
(ON)
Figure 16. Leakage Currents as a Function of VD (VS)
ADG406/ADG407/ADG426
Rev. B | Page 13 of 20
100
0.1
100 1k 10k 100k 1M 10M
10
1
00026-017
I
DD
(mA)
FREQUENCY (Hz)
V
DD
= +15V
V
SS
= –15V
EN = 2.4V
EN = 0V
Figure 17. Positive Supply Current vs. Switching Frequency
160
60
1357911131
100
120
140
80
00026-018
t
(ns)
V
IN
(V)
5
V
DD
= +15V
V
SS
= –15V
t
TRANSITION
t
ON
t
OFF
Figure 18. Switching Time vs. VIN (Bipolar Supply)
300
0
±5 ±7 ±9 ±11 ±13 ±15 ±17 ±19 ±21
200
100
00026-019
t
(ns)
SUPPLY VOLTAGE (V)
V
IN
= +5V
t
TRANSITION
t
ON
t
OFF
Figure 19. Switching Time vs. Bipolar Supply
100
0.0001
100 1k 10k 100k 1M 10M
0.01
0.1
1
10
0.001
00026-020
I
SS
(mA)
FREQUENCY (Hz)
V
DD
= +15V
V
SS
= –15V
EN = 2.4V
EN = 0V
Figure 20. Negative Supply Current vs. Switching Frequency
220
80
246810
120
140
160
180
200
100
00026-021
t
(ns)
V
IN
(V)
12
V
DD
= +12V
V
SS
=0V
t
TRANSITION
t
ON
t
OFF
Figure 21. Switching Time vs. VIN (Single Supply)
500
05 7 9 11 13 15
200
300
400
100
00026-022
t
(ns)
SUPPLY VOLTAGE (V)
V
IN
= +5V
t
TRANSITION
t
ON
t
OFF
Figure 22. Switching Time vs. Single Supply
ADG406/ADG407/ADG426
Rev. B | Page 14 of 20
140
40
100 1k 10k 100k 1M 10M
80
100
120
60
00026-023
OFF ISOLATION (dB)
FREQUENCY (Hz)
V
DD
= +15V
V
SS
= –15V
Figure 23. Off Isolation vs. Frequency
140
40
100 1k 10k 100k 1M 10M
80
100
120
60
00026-024
CROSSTALK (dB)
FREQUENCY (Hz)
V
DD
= +15V
V
SS
= –15V
Figure 24. Crosstalk vs. Frequency
ADG406/ADG407/ADG426
Rev. B | Page 15 of 20
TEST CIRCUITS
00026-025
S D
V
S
V1
I
DS
R
ON
= V1/I
DS
Figure 25. On Resistance
00026-026
S2 D
V
D
S1
S16
EN
V
DD
V
SS
V
DD
V
SS
A
V
S
+0.8V
I
S
(OFF)
Figure 26. IS (Off)
00026-027
S2 D
V
S
S1
S16
EN
V
DD
V
SS
V
DD
V
SS
A
V
D
+0.8V
I
D
(OFF)
Figure 27. ID (Off)
00026-028
D
V
S
S1
S16
EN
V
DD
V
SS
V
DD
V
SS
A
V
D
+2.4V
I
D
(ON)
Figure 28. ID (On)
00026-029
S1
D
VDD VSS
GND
V1
A3
A2
A1
EN
ADG426
1
1SIMILAR CONNECTION FOR ADG406/ADG407
S16
RL
300Ω
CL
35pF
S2 THRU S15
V2
VOUT
2.4V
50Ω
VIN
V
SS
V
DD
WR
A0
RS
50% 50%
90%
90%
t
TRANSITION
3V
ADDRESS
DRIVE (VIN)
t
TRANSITION
VOUT
Figure 29. Switching Time of Multiplexer, tTRANSITION
00026-030
S1
D
V
DD
V
SS
GND
A3
A2
A1
EN
ADG426
1
1
SIMILAR CONNECTION FOR ADG406/ADG407
S16
R
L
300Ω
C
L
35pF
S2 THRU S15
2.4V
50Ω
V
IN
V
SS
V
DD
WR
A0
RS
V
S
0V
OUTPUT
3V
ADDRESS
DRIVE (V
IN
)
t
OPEN
80% 80%
V
OUT
Figure 30. Break-Before-Make Delay, tOPEN
ADG406/ADG407/ADG426
Rev. B | Page 16 of 20
00026-031
S1
D
V
DD
V
SS
GND
A3
A2
A1
EN
ADG426
1
1
SIMILAR CONNECTION FOR ADG406/ADG407
R
L
300Ω
C
L
35pF
S2 THRU S16
2.4V
50Ω
V
IN
V
SS
V
DD
WR
A0
RS
V
S
V
OUT
90% 90%
3V
t
ON
(EN)
ENABLE
DRIVE (V
IN
)50%
OUTPUT
50%
0V
0V
t
OFF
(EN)
V
O
Figure 31. Enable Delay, tON (EN), tOFF (EN)
00026-032
S1
D
V
DD
V
SS
GND
A3
A2
A1
EN
ADG426
R
L
300Ω
C
L
35pF
S2 THRU S16
2.4V
V
SS
V
DD
WR
A0
RS
V
S
V
OUT
V
WR
V
RS
0V
3V
50%
0V
V
0
OUTPUT 0.2V
0
WR
t
ON
(WR)
Figure 32. Write Turn-On Time, tON (WR)
00026-033
S1
D
V
DD
V
SS
GND
A3
A2
A1
EN
ADG426
R
L
300Ω
C
L
35pF
S2 THRU S16
2.4V
V
SS
V
DD
A0
RS
V
S
V
OUT
0V
3V
50%
0V
V
0
OUTPUT
0.8V
0
RS
t
OFF
(RS)
WR
V
IN
Figure 33. Reset Turn-Off Time, tOFF (RS)
ADG406/ADG407/ADG426
Rev. B | Page 17 of 20
00026-034
D
VDD VSS
GND
A3
A2
A1
EN
ADG426
1
CL
1nF
V
SS
V
DD
A0
RS
VOUT
WR
3V
LOGIC
INPUT
(VIN)
VOUT
RS
2.4V
VIN
S
VSΔVOUT
QINJ = CL×ΔVOUT
1SIMILAR CONNECTION FOR ADG406/ADG407.
Figure 34. Charge Injection
00026-035
S1
D
V
DD
V
SS
GND
A3
A2
A1
EN
ADG426
1
1
SIMILAR CONNECTION FOR ADG406/ADG407.
R
L
1kΩ
S16
2.4V
V
DD
WR
A0
RS V
OUT
V
SS
V
IN
Figure 35. Off Isolation
00026-036
D
V
DD
V
SS
GND
A0
A1
A2
EN
ADG426
1
1
SIMILAR CONNECTION FOR ADG406/ADG407.
1kΩ
2.4V
V
DD
WR
A3
RS
V
OUT
V
SS
S1
S16
V
IN
S2
1kΩ
Figure 36. Crosstalk
ADG406/ADG407/ADG426
Rev. B | Page 18 of 20
TERMINOLOGY
VDD
Most positive power supply potential.
VSS
Most negative power supply potential in dual supplies. In single
supply applications, it may be connected to ground.
GND
Ground (0 V) reference.
RON
Ohmic resistance between the D and S terminals.
RON Match
Difference between the RON of any two channels.
IS (Off)
Source leakage current when the switch is off.
ID (Off)
Drain leakage current when the switch is off.
ID, IS (On)
Channel leakage current when the switch is on.
VD (VS)
Analog voltage on Terminal D, Terminal S.
CS (Off)
Channel input capacitance for off condition.
CD (Off)
Channel output capacitance for off condition.
CD, CS (ON)
On switch capacitance.
CIN
Digital input capacitance.
tON (EN)
Delay time between the 50% and 90% points of the digital input
and switch on condition.
tOFF (EN)
Delay time between the 50% and 90% points of the digital input
and switch off condition.
tTRANSITION
Delay time between the 50% and 90% points of the digital
inputs and the switch on condition when switching from
one address state to another.
tOPEN
Off time measured between 80% points of both switches when
switching from one address state to another.
VINL
Maximum input voltage for Logic 0.
VINH
Minimum input voltage for Logic 1.
IINL (IINH)
Input current of the digital input.
Crosstalk
A measure of unwanted signal which is coupled through from
one channel to another as a result of parasitic capacitance.
Off Isolation
A measure of unwanted signal coupling through an off channel.
Charge Injection
A measure of the glitch impulse transferred from the digital
input to the analog output during switching.
IDD
Positive supply current.
ISS
Negative supply current.
ADG406/ADG407/ADG426
Rev. B | Page 19 of 20
OUTLINE DIMENSIONS
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE LEADS.
COMPLIANT TO JEDEC STANDARDS MS-0 11
071006-A
0.100 (2.54)
BSC
1.565 (39.75)
1.380 (35.05)
0.580 (14.73)
0.485 (12.31)
0.022 (0.56)
0.014 (0.36)
0.200 (5.08)
0.115 (2.92)
0.070 (1.78)
0.050 (1.27)
0.250 (6.35)
MAX
SEATING
PLANE
0.015
(0.38)
MIN
0.005 (0.13)
MIN
0.700 (17.78)
MAX
0.015 (0.38)
0.008 (0.20)
0.625 (15.88)
0.600 (15.24)
0.015 (0.38)
GAUGE
PLANE
0.195 (4.95)
0.125 (3.17)
28
114
15
Figure 37. 28-Lead Plastic Dual In-Line Package {PDIP}
Wide Body
(N-28-2)
Dimensions shown in inches and (millimeters)
COMPLIANT TO JEDEC STANDARDS MO-047-AB
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
4
5
26
25
11
12
19
18
TOP VIEW
(PINS DOWN)
SQ
0.456 (11.582)
0.450 (11.430)
0.050
(1.27)
BSC
0.048 (1.22)
0.042 (1.07)
0.048 (1.22)
0.042 (1.07)
0.495 (12.57)
0.485 (12.32) SQ
0.021 (0.53)
0.013 (0.33)
0.430 (10.92)
0.390 (9.91)
0.032 (0.81)
0.026 (0.66)
0.120 (3.04)
0.090 (2.29)
0.056 (1.42)
0.042 (1.07) 0.020 (0.51)
MIN
0.180 (4.57)
0.165 (4.19)
BOTTOM
VIEW
(PINS UP)
0.045 (1.14)
0.025 (0.64) R
PIN 1
IDENTIFIER
042508-A
Figure 38. 28-Lead Plastic Leaded Chip Carrier [PLCC]
(P-28)
Dimensions shown in inches and (millimeters)
ADG406/ADG407/ADG426
Rev. B | Page 20 of 20
COMPLIANT TO JEDEC STANDARDS MO-150-AH
060106-A
28 15
14
1
10.50
10.20
9.90
8.20
7.80
7.40
5.60
5.30
5.00
SEATING
PLANE
0.05 MIN
0.65 BSC
2.00 MAX
0.38
0.22
COPLANARITY
0.10
1.85
1.75
1.65
0.25
0.09
0.95
0.75
0.55
8°
4°
0°
Figure 39. 28-Lead Shrink Small Outline Package [SSOP]
(RS-28)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option2
ADG406BN −40°C to +85°C 28-Lead PDIP N-28-2
ADG406BNZ −40°C to +85°C 28-Lead PDIP N-28-2
ADG406BP −40°C to +85°C 28-Lead PLCC P-28
ADG406BP-REEL −40°C to +85°C 28-Lead PLCC P-28
ADG406BPZ −40°C to +85°C 28-Lead PLCC P-28
ADG406BPZ-REEL −40°C to +85°C 28-Lead PLCC P-28
ADG407BN −40°C to +85°C 28-Lead PDIP N-28-2
ADG407BNZ −40°C to +85°C 28-Lead PDIP N-28-2
ADG407BP −40°C to +85°C 28-Lead PLCC P-28
ADG407BP-REEL −40°C to +85°C 28-Lead PLCC P-28
ADG407BPZ −40°C to +85°C 28-Lead PLCC P-28
ADG407BPZ-RL −40°C to +85°C 28-Lead PLCC P-28
ADG407BCHIPS −40°C to +85°C DIE
ADG426BN −40°C to +85°C 28-Lead PDIP N-28-2
ADG426BNZ −40°C to +85°C 28-Lead PDIP N-28-2
ADG426BRS −40°C to +85°C 28-Lead SSOP RS-28
ADG426BRS-REEL −40°C to +85°C 28-Lead SSOP RS-28
ADG426BRS-REEL7 −40°C to +85°C 28-Lead SSOP RS-28
ADG426BRSZ −40°C to +85°C 28-Lead SSOP RS-28
ADG426BRSZ-REEL −40°C to +85°C 28-Lead SSOP RS-28
1 Z = RoHS Compliant Part.
2 N = Plastic DIP, P = Plastic Leaded Chip Carrier (PLCC), RS = Shrink Small Outline Package (SSOP).
©1994–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00026-0-5/10(B)
