PRODUCT SPECIFICATION
Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +47 72898989
Revision: 1.0
3DJHRI
Janu ary 2004
nRF9E5 Evaluation Board
*(1(5$/'(6&5,37,21
This document describes the Q5)((9%2$5' and its use with the Nordic VLSI
Q5)( Single Chip 433/868/915MHz RF Transceiver with embedded 8051 compatible
microcontroller and 4 input 10 bit ADC. Q5)((9%2$5'V for operation at 433MHz and
868/915MHz are available. This document covers both versions.
Figure 1: The Q5)((9%2$5'
Q5)((9%2$5'
PRODUCT SPECIFICATION
Q5)((YDOXDWLRQ%RDUG
Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +47 72898989
Revision: 1.0
3DJHRI
Janu ary 2004
,1752'8&7,21
The Evaluation Board for the Q5)( Single Chip 433/868/915MHz RF Transceiver with
embedded 8051 compatible microcontroller and 4 input 10 bit ADC has been developed to
enable customers to test functionality, develop firmware, run communication and verify the
performance parameters of the device. This document describes the usage of the Q5)(
(9%2$5'.
The Q5)((9%2$5'is intended for evaluation and development purposes only. It is
not intended for incorporation into an end product.
*(77,1*67$57('
The Q5)((9%2$5' is shipped with an((3520SURJUDPPHUDQGHPXODWRUGRQJOH
The ((3520SURJUDPPHUDQGHPXODWRUGRQJOH enables you to emulate a 4k serial SPI
EEPROM and program the Q5)((9%2$5' on board SPI EEPROM through PC
software.
The following equipment is needed to work efficiently with the Q5)((9%2$5':
PC with 2 free USB ports, running (supplied) Q5)352* PC software
2 ((3520SURJUDPPHUDQGHPXODWRUGRQJOHV (supplied)
A DC voltage supply (+4.5V to +12V)
2 standard male USB A/B cables (supplied)
To evaluate the performance of the device the following instrumentation should be available:
Logic anal yzer
Ampere meter
RF signal generator with GFSK modulation capability
RF spectrum analyzer
Low frequency, high accuracy signal generator (ADC tests)
PRODUCT SPECIFICATION
Q5)((YDOXDWLRQ%RDUG
Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +47 72898989
Revision: 1.0
3DJHRI
Janu ary 2004
((3520352*5$00(5$1'(08/$725'21*/(
'(6&5,37,21
The ((3520SURJUDPPHUDQGHPXODWRUGRQJOH is fitted ‘on-top’ of the Q5)(
(9%2$5' as shown in (Figure 2). This interface enables you to:
Emulate the external 4k serial SPI EEPROM needed by Q5)( through the
Q5)352* PC software.
Program the EEPROM included on the Q5)((9%2$5'.
The Q5)352* software is documented in Q5)352**(77,1*67$57(' [1].
PC
USB Link
SPI Lin k
nRF9E5
EEPROM
2XX320
(+4. 5 – 12v)
MCU
USB
ADC input
Ant enna
Parallel int erf ace
RS232 SW4
SW3
SW2
SW1
LED4LED3LED2LED1
S205
S206
J2
JP2
J3
J1
RESET
S102
Q5)((9%2$5'
J101
S101
OFF/ON
D101
Suppl y level
adjust
R114
JP1J4
S1
Figure 2: Q5)((9%2$5' with programming dongle
Emulating the external EEPROM needed by the Q5)( will increase the flexibility and
speed of SW development and de-bugging. When a program is running well, the EEPROM
included on the Q5)((9%2$5' can be programmed, enabling the Q5)(
(9%2$5' to run stand-alone.
3RZHUVXSSO\
Main power supply to the ((3520SURJUDPPHUDQGHPXODWRUGRQJOH is fed through the
USB interface (J101) from the PC. Supply voltage to the Q5)((9%2$5' interface
stage runs through J102 from the Q5)((9%2$5'.The ((3520SURJUDPPHUDQG
PRODUCT SPECIFICATION
Q5)((YDOXDWLRQ%RDUG
Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +47 72898989
Revision: 1.0
3DJHRI
Janu ary 2004
HPXODWRUGRQJOH must hence be plugged in the Q5)((9%2$5'connector JP2 in order
to have proper signal levels on J102
Q5)((9%2$5'LQWHUIDFH
The pin-out of the interface (J102) to the Q5)((9%2$5'can be found in Table 2
under the chapter Q5)((9%2$5''(6&5,37,21 (EVBOARD connector JP2). The
PC interface (J101) is a standard USB B-connector interface.
86%DGGUHVVLQJ6
If both of the supplied ((3520SURJUDPPHUDQGHPXODWRUGRQJOHV are connected to the
same USB HUB (same PC), they need a unique USB address each.
On the ((3520SURJUDPPHUDQGHPXODWRUGRQJOH, switch S101 can be set to USB address
1 or 2, both to give the two boards a unique USB address for the HUB and an easy way to
visually identify the two Q5)((9%2$5'V.
Remember that the address must be set prior to attaching the ((3520SURJUDPPHUDQG
HPXODWRUGRQJOHVto the USB HUB. This USB address will also be shown in the Q5)352*
user interface to identify the two Q5)((9%2$5'V.
PRODUCT SPECIFICATION
Q5)((YDOXDWLRQ%RDUG
Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +47 72898989
Revision: 1.0
3DJHRI
Janu ary 2004
Q5)((9%2$5''(6&5,37,21
Appendix 1 shows the Q5)((9%2$5' circuit diagrams. The PCB layout and
component placement is shown in Appendix 2. The component list is given in Appendix 3.
Figure 3 shows the block diagram of the Q5)((9%2$5'.
Q5)(
3DUDOOHOLQWHUIDFH
5),2
$'&LQSXW
86%GRQJOH56
((3520
-
-3
-3
-
-
56
FRQY
6
-3
-
95(*
12
4
2
5
5(6(7
95(*
5
9
*1'
7HPS
VHQVRU
-3
[[
4
4
9''BQ5)
9&&
5
Figure 3: Block diagram of the Q5)((9%2$5'
3RZHUVXSSO\-
Power supply and ground is applied to the Q5)((9%2$5'via connector J101. Two on
board adjustable voltage regulators (U102 and U103) are included, allowing an input voltage
range from 9WR9 at connector J101. The output voltages from the voltage
regulators (VDD_nRF and VCC) are simultaneously adjusted from +1.8V to +3.6V by the
use of the dual gang potentiometer R114, and the voltage levels can be measured on header
JP101. There is one voltage regulator (U102) for the Q5)( device, and one voltage
regulator (U103) for the rest of the circuitry on the board.
Power switch S101 turns the Q5)((9%2$5' main power on and of. The green LED
D101 is lit when power is on. Note that if the output voltages from the voltage regulators are
adjusted to a low voltage level, the light from the LED will be weak.
PRODUCT SPECIFICATION
Q5)((YDOXDWLRQ%RDUG
Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +47 72898989
Revision: 1.0
3DJHRI
Janu ary 2004
'LJLWDO,2SRUWV
All signals in digital I/O ports 0 and 1 of the 8051 controller can be accessed through JP1
(Parallel Interface). The pin-out is listed in Table 1.
JP1 pin # Q5)( port# Signal name Functionality
1-GND
2 P1.3 EECSN (P1.3) GPIO / EEPROM CSN
3 P1.0 SCK (P1.0) SPI clock / T2
4 P1.2 MISO (P1.2) SPI datain / GPIO
5 P1.1 MOSI (P1.1) SPI dataout / GPIO
6 P0.7 P07 GPIO / PWM
7 P0.6 P06 GPIO / T1
8 P0.5 P05 GPIO / T0
9 P0.4 P04 GPIO / INT1_N
10 P0.3 P03 GPIO / INT0_N
11 P0.2 P02 GPIO / TXD (UART)
12 P0.1 P01 GPIO / RXD (UART)
13 P0.0 P00 GPIO / GTIMER
14 - VCC Output voltage from regulator
U103
Table 1: Q5)((9%2$5', JP1 pin-out
These signals are also available for measurements on header J4. The signal names are found
on the PCB silkscreen.
8$5756-
The Q5)( UART is fed to an on board RS232 converter in addition to the parallel
interface connector JP1.
The converted RS232 signal is available at connector J2, which is a standard 9-pin female
DSUB for connection to PC or other equipment.
Switch S1 disables the RS232 converter and tri-states its outputs. This enables the Q5)(
UART to be accessed through JP1.
127(
The RS232 converter will also shut down and tri-state the outputs if a RS232 plug is
not present in J2.
((3520
The Q5)((9%2$5' is fitted with a standard 2xx320 SPI EEPROM for program code
(U2). The EEPROM is accessed through the Q5)( SPI master found on digital I/O port 1
(P1).
On the Q5)((9%2$5' the SPI and control signals are all buffered (U5-U8). This
buffering is not needed in a final application, but utilized on the Q5)((9%2$5' to
PRODUCT SPECIFICATION
Q5)((YDOXDWLRQ%RDUG
Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +47 72898989
Revision: 1.0
3DJHRI
Janu ary 2004
avoid overloading the P1 port and enabling in circuit programming of the on board
EEPROM.
As the Q5)( features an SPI master it must be overridden by the ((3520SURJUDPPHU
DQGHPXODWRUGRQJOH when the Q5)((9%2$5' on board EEPROM is to be
programmed.
JP2 interfaces the programming ((3520SURJUDPPHUDQGHPXODWRUGRQJOH that is shipped
with the Q5)((9%2$5'V. This external EEPROM emulator and programmer eases the
development of firmware, and enables the user to download new firmware trough an USB
interface.
If it is desirable to program the external EEPROM from the Q5)( a jumper must be
mounted on header JP3. The ((3520SURJUDPPHUDQGHPXODWRUGRQJOH must be removed
from JP2 when doing this.
The pin out of JP2 is listed in Table 2.
Pin number Pin name Comment
1 VCC / VL Output voltage from regulator U103
2VERQ5)((9%2$5' rev. code
3 CSCTRL CS override for EEPROM
programming
4 CSN Chip select from Q5)(
5 SO SPI data out
6 WPN On board EEPROM write protect
7SI SPI data in
8SCK SPI clock
9 RESET Q5)( reset
10 GN D Sys te m GN D
Table 2 Q5)((9%2$5' JP2 pin out
5),2-
For convenient connection of the differential antenna output/input pins to a single ended
antenna or 50 test equipment, a differential to single ended matching network is included.
This network matches the 50VLQJOHHQGHGDQWHQQDRU test equipment impedance at the
SMA connector J1 to the recommended differential load impedance at the Q5)(’s RF I/O
stage (pins ANT1 & ANT2). The employed matching network introduces an insertion loss of
approximately 1-2dB at 433/868/915MHz. The components utilized in the single ended
matching network on the Q5)((9%2$5'have the tightest tolerances available. This is
done to minimize the influence of component variations in the matching network during
Q5)( RF performance tests. In a final application less accurate and hence lower cost
components can be utilized if some variation in output power and sensitivity can be accepted.
$'LQSXW-
The 4 external ADC inputs and the external ADC reference voltage (AREF) are fed through
header J3. The signals are single ended, and in header J3 each input is paired with a GND.
PRODUCT SPECIFICATION
Q5)((YDOXDWLRQ%RDUG
Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +47 72898989
Revision: 1.0
3DJHRI
Janu ary 2004
All inputs are low pass filtered through first order RC units, the cut off is 3.2 MHz. The
AREF is similarly filtered with a cut of frequency of 1.5 kHz.
5(6(7
Since the Q5)( device has no external reset pin, the separate voltage regulator (U102) for
the Q5)( device has a shut-down feature to ensure a controlled shut-off of VDD_nRF and
hence reset, during firmware debugging.
A Q5)( reset is generated either by pressing the RESET push-button (S102) on the board,
manually through the PC software or by downloading new software to the EEPROM
emulator.
This external reset circuitry is not necessary in a final application since the Q5)( then will
be the system master and features power on, watch dog and interrupt reset routines.
Q5)(YROWDJHDQGFXUUHQWPHDVXUHPHQWV-3
To enable measurement of Q5)( current consumption a header JP101 is put on the
Q5)( supply line. The jumper on this header is never to be removed, except when
replaced by an ampere meter for measurements. The exact supply voltage (VDD_nRF) to the
Q5)( can also be measured on JP101.
7HPSHUDWXUH6HQVRU
The Q5)((9%2$5' includes a National Semiconductor LM35DZ temperature sensor.
This sensor can be connected to the AIN3 input of the ADC by mounting a jumper on header
JP4.
The temperature sensor has an output voltage that is linearly proportional to the Celsius
(Centigrade) temperature. Output voltage level is VOUT = 0mV + 10mV/°C in the operating
temperature range 0°C to +100°C of the sensor.
8VHU/('V
The Q5)((9%2$5' includes 4 yellow LEDs (LED1-LED4). The LEDs can be
connected to the Q5)( digital I/O port P0 (P0.0, P0.2, P0.4 and P0.6) by the use of the
four positions DIP switch S206.
127(
Each pin in digital I/O port P0 may sink or source a high current. Even numbered bits
will sink high current when the corresponding bit in P0_DRV is set, whereas odd
numbered bits will source high current when the corresponding bit in P0_DRV is set.
For further details, please see the Q5)( Product Specification.
PRODUCT SPECIFICATION
Q5)((YDOXDWLRQ%RDUG
Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +47 72898989
Revision: 1.0
3DJHRI
Janu ary 2004
8VHU3XVKEXWWRQV
The Q5)((9%2$5' includes 4 push-button switches (SW1-SW4). The push-buttons
can be connected to the Q5)( digital I/O port P0 (P0.1, P0.3, P0.5 and P0.7) by the use of
the four positions DIP switch S205.
5()(5(1&(6
[1] nRFPROG GETTING STARTED, Nordic VLSI document, http://www.nvlsi.no
PRODUCT SPECIFICATION
$SSHQGL[Q5)((YDOXDWLRQ%RDUG&LUFXLWGLDJUDP
Nordic VLSI ASA Vestre Rosten 81, N-7075 Tiller, Norway Phone +4772898900 Fax +4772 898989
Revision: 1.0
3DJHRI
Janu ary 2004
P01
1VSS 24
VSS 18
VDD 17
VSS
16
P02
2
P03
3
VDD
4
VSS
5
P04
6
P05
7
P06
8
P07
9
MOSI
10
MISO
11
SCK
12
XC2
15 XC1
14 EECSN
13
VDD_PA 19
ANT1 20
ANT2 21
VSS 22
IREF 23
Q5)(
VDD 25
AIN3 26
AIN2 27
AIN1 28
AIN0 29
AREF 30
DVDD_1V2 31
P00 32
U1
NRF9E5
1
2
3
4
5
6
7
8
9
10
J3
CON18
$',QSXW
R15
220
0603
R16
220
0603
R17
220
0603
R18
220
0603
C20
220pF
0603
C19
220pF
0603
C24
220pF
0603
C23
220pF
0603
C21
1nF
0603
R14
1K
0603
C22
100nF
0603
xxx
CS
1
SO
2
WP
3
VSS
4SI 5
SCK 6
HOLD 7
VCC 8
U2
25XX320
C14
10nF
0603
R3
10K
0603
R6
100K
0603
P03
P04
P05
P06
P07
MOSI (P1.1)
MISO (P1.2)
P02
P01
R5
100K
0603
5
6
P00
1
2
3
4
5
6
7
8
9
10
11
12
13
14
J4
IDC12
1
2
3
4
5
6
7
8
9
10
JP2
IDC10
VCC
S1
SW SPDT
VCC_RS232
1
2
3
4
5
6
7
8
9
10
11
12
13
14
JP1
CON14
VCC
U4
74LVC1G32
VCC
R4
33K
0603
VCC
VCC
R9
100K
0603
TxD
RxD
RESET
D1
BD6050
VCC
LX 1
INVALID 2
FORCEON 3
FORCEOFF 4
GND 5
VCC 6
T1IN 7
T2IN 8
R1OUT 9
R2OUT 10
R2IN
11 R1IN
12 T2OUT
13 T1OUT
14 V-
15 C1-
16 GND
17 C1+
18 V+
19 GND
20 U3
MAX3218CAP
+
C15
1uF/20V
3216
L4
15uH
1812 +C18
100u/6.3V
3216
+
C16
1uF/20V
3216
C17
0.47uF/25V
3216
VCC_RS232
1
2 4
U5
74LVC1G125
1
2 4
U6
74LVC1G125
1
24
U7
74LVC1G125
1
2 4
U8
74LVC1G125
R7
Not fitted
0603
R8
0 ohm
0603
VCC
1
2 4
U9
74LVC1G125
R10
100K
0603
,
Q
F
L
U
F
X
L
W
S
U
R
J
U
D
P
P
H
U
3
D
U
D
O
O
H
O
,
Q
W
H
U
I
D
F
H
VL
VER
CSCTRL
CSN
SO
WPN
SI
SCK
RESET
GND
C2
15pF
0603
C6
4.7nF
0603
C5
33pF
0603
R2
22K
0603
C7
10nF
0603
VDD_nRF
C1
15pF
0603
R1
1M
J1
SMA
X1
16 MHz
XC1 XC2
VDD_nRF
L1
0603
C3
0603
C11
Not fitted
0603
C12
0603
L3
0603
L2
0603
C9
0603
C10
0603
C4
3.3nF
0603
C8
33pF
0603
VDD_nRF
SCK (P1.0)
EECSN (P1.3)
L5
15uH
1812
RESET
1
6
2
7
3
8
4
9
5
J2
DB9
5),2
C13
0603
R12
100
0603
R13
100
0603
VCC
1
2
JP3
JUMPER
R11
10K
0603
VCC_RS232
+Vs 3
GND
1
Vout
2U10
LM35DZ
VDD
1
2
JP4
JUMPER
7HPSHUDWXUH6HQVRU
C25
100nF
C3
C9
C10
C11
C12
C13
L1
L2
L3
868/915MHz 433MHz
33pF, ±5%
3.9pF, ±0.25pF
3.9pF, ±0.25pF
Not fi tted Not fi tted
33pF, ±5%
Not fitted
12nH, 2%
12nH, 2%
12nH, 2%
180pF, ±5%
18pF, ±5%
18pF, ±5%
6.8pF, ±5%
Not fitted
12nH, 2%
39nH, 5%
39nH, 5%
56(QDEOH'LVDEOH
R19
10K
0603
VCC
xxx
xxx
xxx
Figure A.1.1. Q5)((9%2$5', Main circuitry
PRODUCT SPECIFICATION
$SSHQGL[Q5)((YDOXDWLRQ%RDUG&LUFXLWGLDJUDP
Nordic VLSI ASA Vestre Rosten 81, N-7075 Tiller, Norway Phone +4772898900 Fax +4772 898989
Revision: 1.0
3DJHRI
Janu ary 2004
1
J102
1
2
J101
4.5-12V
GND C103
10nF
OUT 1
ADJ 2
GND
3
BYP 4
SHDN
5
GND
6GND
7
IN
8
U102
LT1763CS8
+ C104
10uF/6V
1 2
S101
Power on/off
VDD
+C101
2.2uF/20V C105
100nF/16V
VDD_nRF
C106
10nF
OUT 1
ADJ 2
GND
3
BYP 4
SHDN
5
GND
6GND
7
IN
8
U103
LT1763CS8
+ C107
10uF/6V
R110
5.6K
C108
100nF/16V
VCC
RESET
D101
Power LED
R115
39ohm
0603
R104
10K
0603
R112
4.7K
0603
Q101
FDV303N
MOSFET N
RESET
C102
100nF/50V
0805
(VC C = 1.8V - 3.6V)
(VDD_nRF = 1.8V - 3.6V)
Q102
FDV303N
MOSFET N
R105
1K
S102
RESET
1
2
JP101
JUMPER
R103
10K
R101
1K
R111
7.5K
0603
R113
82K
0603
13
2
6 4
5
R114
0-10K
R108
4.7K
0603
R107
7.5K
0603
R109
82K
0603
R106
5.6K
R102
1K
Supply Lev e l Adjust, 1.8V - 3.6V
xxx
xxx
xxx
xxx
Figure A.1.2. Q5)((9%2$5', Power supply and RESET.
PRODUCT SPECIFICATION
$SSHQGL[Q5)((YDOXDWLRQ%RDUG&LUFXLWGLDJUDP
Nordic VLSI ASA Vestre Rosten 81, N-7075 Tiller, Norway Phone +4772898900 Fax +4772 898989
Revision: 1.0
3DJHRI
Janu ary 2004
D201
LED1
VCC
D202
LED2
VCC
D203
LED3
VCC
D204
LED4
VCC
LED1 LED2 LED3 LED4
S201
SW1 S202
SW2 S203
SW3 S204
SW4
R201
10K R202
10K R203
10K R204
10K
VCC VCC VCC VCC
SW1 SW2 SW3 SW4
SW1
SW2
SW3
SW4
LED1
LED2
LED3
LED4
1
2
3
4
8
7
6
5
S206
SW DIP-4
1
2
3
4
8
7
6
5
S205
SW DIP-4
P00
P02
P04
P06
P00
P02
P04
P06
P01
P03
P05
P07
P01
P03
P05
P07
xxx
xxx
xxx
xxx
Figure A.1.3. Q5)((9%2$5', LEDs and Switches
PRODUCT SPECIFICATION
$SSHQGL[Q5)((YDOXDWLRQ%RDUG3&%OD\RXW
Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +47 72898989
Revision: 1.0
3DJHRI
Janu ary 2004
a) Top silk screen
a) Top view
a) Bottom view
Figure A.2.1. Q5)((9%2$5' PCB layout
The Q5)((9%2$5' is manufactured on a 1.6mm thick, 2 layer FR4 substrate.
PRODUCT SPECIFICATION
$SSHQGL[Q5)((YDOXDWLRQ%RDUG&RPSRQHQWOLVW
Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +47 72898989
Revision: 1.0
3DJHRI
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C1 Capacitor Ceramic 15pF, +/-5%, 50V, NP0 0603
C2 Capacitor Ceramic 15pF, +/-5%, 50V, NP0 0603
C3 Capacitor Ceramic
@ 433MHz
@ 868/915MHz 180pF, +/-5%, 50V, NP0
33pF, +/-5%, 50V, NP0
0603
C4 Capacitor Ceramic 3.3nF, +/-10%, 50V, X7R 0603
C5 Capacitor Ceramic 33pF, +/-5%, 50V, NP0 0603
C6 Capacitor Ceramic 4.7nF, +/-10%, 50V, X7R 0603
C7 Capacitor Ceramic 10nF, +/-10%, 50V, X7R 0603
C8 Capacitor Ceramic 33pF, +/-5%, 50V, NP0 0603
C9 Capacitor Ceramic
@ 433MHz
@ 868/915MHz 18pF, +/-5%, 50V, NP0
3.9pF, ±0.25pF, 50V, NP0
0603
C10 Capacitor Ceramic
@ 433MHz
@ 868/915MHz 18pF, +/-5%, 50V, NP0
3.9pF, ±0.25pF, 50V, NP0
0603
C11 0603 Not fitted
C12 Capacitor Ceramic
@ 433MHz
@ 868/915MHz 6.8pF, +/-5%, 50V, NP 0
33pF, +/-5%, 50V, NP0
0603
C13 Capacitor Ceramic
@ 433MHz
@ 868/915MHz Not fitted
Not fitted
0603
C14 Capacitor Ceramic 10nF, +/-10%, 50V, X7R 0603
C15 Capacitor Tantalu m 1.0µF, +/-20%, 20V 3216
C16 Capacitor Tantalu m 1.0µF, +/-20%, 20V 3216
C17 Capacitor Tantalu m 0.47µF, +/-20%, 35V 3216
C18 Capacitor Electrolytic 100µF, +/-20%, 6.3V SMD
C19 Capacitor Ceramic 220pF, +/-5%, 50V, NP0 0603
C20 Capacitor Ceramic 220pF, +/-5%, 50V, NP0 0603
C21 Capacitor Ceramic 1nF, +/-10%, 50V, X7R 0603
C22 Capacitor Ceramic 100nF, +/-10%, 50V, X7R 0603
C23 Capacitor Ceramic 220pF, +/-5%, 50V, NP0 0603
C24 Capacitor Ceramic 220pF, +/-5%, 50V, NP0 0603
C25 Capacitor Ceramic 100nF, +/-10%, 50V, X7R 0603
C101 Capacitor Tantalum 2.2µF, +/-20%, 20V 3216
C102 Capacitor Ceramic 100nF, +/-10%, 50V, X7R 0805
C103 Capacitor Ceramic 10nF, +/-10%, 50V, X7R 0603
C104 Capacitor Tantalum 10µF, +/-20%, 6V 3216
C105 Capacitor Ceramic 100nF, +/-10%, 50V, X7R 0603
C106 Capacitor Ceramic 10nF, +/-10%, 50V, X7R 0603
C107 Capacitor Tantalum 10µF, +/-20%, 6V 3216
C108 Capacitor Ceramic 100nF, +/-10%, 50V, X7R 0603
D1 Shottky diode BD6050 SOT-23D
D101 LED, Green 1206
D201 LED, Yellow 1206
D202 LED, Yellow 1206
D203 LED, Yellow 1206
D204 LED, Yellow 1206
J1 RF I/O SMA th rough-hole
J2 RS232 connector 9 pin DSUB through-hole
J3 ADC input 2x5 pin header through-hole
PRODUCT SPECIFICATION
$SSHQGL[Q5)((YDOXDWLRQ%RDUG&RPSRQHQWOLVW
Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +47 72898989
Revision: 1.0
3DJHRI
Janu ary 2004
'HVLJQDWRU 'HVFULSWLRQ 3DUW7\SH )RRWSULQW &RPPHQW
J4 Test connector 2x7 pin header through-hole
J101 Power supply connector through-hole
J102 Test point through-hole GND for test equipment
JP1 Parall el int erface connector Flat cable connector 14 pin through-hole
JP2 In circuit prog. connector Flat cable connector 10 pin through-hole
JP3 Jumper connection 2 pin header through-hole
JP4 Jumper connection 2 pin header through-hole
JP101 Jumper connection 2 pin header through-hole
L1 Wire wound chip inductor
@ 433MHz: SRF>433MHz
@ 868/915MHz: SRF>915MHz 12nH, +/-2%
12nH, +/-2%
0603
L2 Wire wound chip inductor
@ 433MHz: SRF>433MHz
@ 868/915MHz: SRF>915MHz 39nH, +/-5%
12nH, +/-2%
0603
L3 Wire wound chip inductor
@ 433MHz: SRF>433MHz
@ 868/915MHz: SRF>915MHz 39nH, +/-5%
12nH, +/-2%
0603
L4 Inductor 15uH 1812 Saturation current > 350 mA,
R < 1 ohm
L5 Inductor 15uH 1812 Saturation current > 350 mA,
R < 1 ohm
Q101 DMOS N-Channel FDV303N SOT-23
Q102 DMOS N-Channel FDV303N SOT-23
R1 Resistor 1M 0603 1%
R2 Resistor 22k 0603 1%
R3 Resistor 10k 0603 1%
R4 Resistor 33k 0603 1%
R5 Resistor 100k 0603 1%
R6 Resistor 100k 0603 1%
R7 Resistor 0603 Not fitted
R8 Resistor 0 ohm 0603 1%
R9 Resistor 100k 0603 1%
R10 Resistor 100k 0603 1%
R11 Resistor 10k 0603 1%
R12 Resistor 100 0603 1%
R13 Resistor 100 0603 1%
R14 Resistor 1k 0603 1%
R15 Resistor 220 0603 1%
R16 Resistor 220 0603 1%
R17 Resistor 220 0603 1%
R18 Resistor 220 0603 1%
R19 Resistor 10k 0603 1%
R101 Resistor 1k 0603 1%
R102 Resistor 1k 0603 1%
R103 Resistor 10k 0603 1%
R104 Resistor 10k 0603 1%
R105 Resistor 1k 0603 1%
R106 Resistor 5.6k 0603 1%
R107 Resistor 7.5k 0603 1%
R108 Resistor 4.7k 0603 1%
R109 Resistor 82k 0603 1%
PRODUCT SPECIFICATION
$SSHQGL[Q5)((YDOXDWLRQ%RDUG&RPSRQHQWOLVW
Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +47 72898989
Revision: 1.0
3DJHRI
Janu ary 2004
'HVLJQDWRU 'HVFULSWLRQ 3DUW7\SH )RRWSULQW &RPPHQW
R110 Resistor 5.6k 0603 1%
R111 Resistor 7.5k 0603 1%
R112 Resistor 4.7k 0603 1%
R113 Resistor 82k 0603 1%
R114 Dual gang potentiometer 0-10k through-hole
R115 Resistor 39 0603 1%
R201 Resistor 10k 0603 1%
R202 Resistor 10k 0603 1%
R203 Resistor 10k 0603 1%
R204 Resistor 10k 0603 1%
S1 Slide switch, RS232 Enable/Disable through-hole
S101 Slide switc h, Power on/of f throug h-h ole
S102 Tact switch, RESET SMD
S201 Keyboard switch, SW1 SMD
S202 Keyboard switch, SW2 SMD
S203 Keyboard switch, SW3 SMD
S204 Keyboard switch, SW4 SMD
S205 Four positions DIP switch SMD
S206 Four positions DIP switch SMD
U1 Nordic VLSI, 433/868/915MHz RF
Transceiver with MCU an d ADC Q5)( QFN32L/5x5
U2 4 kbyte serial EEP ROM with SPI interface 25XX320 SO-8
U3 M a xim, RS-232 Transceiver MAX3218CAP SSO-20
U4 OR gate 74LVC1G32 SOT353-5
U5 Bus buffer/line driver 74LVC1G125 SOT353-5
U6 Bus buffer/line driver 74LVC1G125 SOT353-5
U7 Bus buffer/line driver 74LVC1G125 SOT353-5
U8 Bus buffer/line driver 74LVC1G125 SOT353-5
U9 Bus buffer/line driver 74LVC1G125 SOT353-5
U10 National Semiconductor, temperature
sensor LM35DZ TO-92
U102 Linear Technology, adjustable LDO
voltage regulator LT1763CS8 SO-8
U103 Linear Technology, adjustable LDO
voltage regulator LT1763CS8 SO-8
X1 Toyocom Devices, 16MHz crystal TSX-10A SMD LxWxH = 4.0x2.5x0.8mm,
CL=9pF, ESR < 100 ohm,
toleran ce + temperature drift <
+/- 30 ppm
Jumper Short circuit for JP3
Jumper Short circuit for JP4
Jumper Short circuit for JP101
Table A.3.1: Q5)((9%2$5' Component list
PRODUCT SPECIFICATION
Q5)((YDOXDWLRQ%RDUG
Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +47 72898989
Revision: 1.0
3DJHRI
Janu ary 2004
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This Evaluation Board documentation contains final product specifications. Nordic VLSI ASA reserves the right
to make changes at any time without notice in order to improve design and supply the best possible product.
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Stress above one or more of the limiting values may cause permanent damage to the device. These are stress
ratings only and operation of the device at these or at any other conditions above those given in the
Specifications sections of the specification is not implied. Exposure to limiting values for extended periods may
affect device reliability.
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Where application information is given, it is advisory and does not form part of the specification.
Table 3: Definitions
Nordic VLSI ASA reserves the right to make changes without further notice to the product to
improve reliability, function or design. Nordic VLSI does not assume any liability arising out
of the application or use of any product or circuits described herein.
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These products are not designed for use in life support appliances, devices, or systems where
malfunction of these products can reasonably be expected to result in personal injury. Nordic
VLSI ASA customers using or selling these products for use in such applications do so at
their own risk and agree to fully indemnify Nordic VLSI ASA for any damages resulting
from such improper use or sale.
Product specification, revision date : 30.01.2004
All rights reserved ®. Reproduction in whole or in part is prohibited without the prior written
permission of the copyright holder.
PRODUCT SPECIFICATION
Q5)((YDOXDWLRQ%RDUG
Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +47 72898989
Revision: 1.0
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PRODUCT SPECIFICATION
Q5)((YDOXDWLRQ%RDUG
Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +47 72898989
Revision: 1.0
3DJHRI
Janu ary 2004
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Vestre Rosten 81, N-7075 Tiller, Norway
Phone: +47 72 89 89 00, Fax: +47 72 89 89 89
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