LXT901/907
Universal 10BASE-T and AUI Transceivers
Datasheet
The LXT901 and LXT907 Universal 10BASE-T and AUI Tran sceive rs are designed for IEEE
802.3 ph ysical laye r appli catio ns. They p rovid e all the act ive circu itry t o inter face most standard
IEEE 802.3 controllers to either the 10 BAS E-T me dia or Attachment Unit Interface (AUI). In
add ition to standard 10 Mbps E thernet, the y a lso su pport full-d uplex operation at 20 Mbps.
The LXT 901 and LXT907 a re identical except for the fu nc tion of one pin. The LXT901 off e rs
selectable termination im pedance to allow the use of either shielded or unshiel ded twisted-pair
cable. The LXT907 offers a signal quality error (SQE) disable function.
Common LXT901 and LXT907 functions include Manchester encod ing /decoding, receiver
sque lch an d t ran smit puls e sha ping, jab ber, link test ing, an d r evers ed po lit y det ecti on/ cor rec tion.
Int e gr a ted fil t e rs simpli fy the de si g n wo rk re qu ir e d fo r FC C -c o mp lia n ce E M I pe rf or ma n ce.
Applications
Product Features
■Access devices (DSL, Cable Modems, and
Set-Top Boxes).
■Routers/Bridges/Switches/Hubs
■Telecom Backplane
■USB to Ethernet Conve rters
Functional Features
■Integrated Manchester Encoder/ Decoder
■10BASE-T Transceiver
■AUI Tran sceiver
■Full-Duplex Capab l e (20 Mbps)
Diagnostic Features
■Four LED Drivers
■AUI/RJ-45 Loopback
■Remote Signaling of Link-Down and
Jabber conditions
Convenience Features
■Automatic/Manual AUI/RJ-45 Selection
■Automatic Polarity Correction
■SQE Disable function (LXT90 7 on ly )
■Programm a ble Impe dance Driver (LXT901
only)
■Power-Down Mode and four loopback
modes
■LXT901 available in 64-pin LQFP and 44-
pin PLCC
■LXT907 availa ble in 44- pin PLCC
For technical assistance on this product, please call 1-800-628-8686, Order Number: 249097-002
or send an e-mail to support@mailbox.intel.com. June 2001
2 Datashe et
Docu men t #: 249097
Revision #: 002
Rev. D ate: June 19, 2001
Information in this document is provided in connection with I ntel® products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this docum ent. E xcept as prov ide d in Intel’s Te rms and Co ndi tions of Sale for such pr oducts, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpos e, merch antability, or infringement of any patent, copyright or other intellect ual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make cha nges to speci ficatio ns and prod uct descript io ns at any time, without noti ce.
Designer s mus t not rely on the absen ce or charact erist ic s of any featu res or instruc tions m ark ed "res erved" or "undefined." In tel reserves these for
future definition and shall have no responsibi lity wha tsoeve r for conf licts or incompatibil ities arisi ng from futu re chang es to them .
The LXT901/907 may contain design defects or errors known as errata which may cause the product to deviate from published specifica tions . Curr ent
characterized errata are available on request.
Contact your local Intel sale s office or your distributor to obtain the latest specificat ion s and befo re placing your product order.
Copies of documents which have an ordering numb er and are referenc ed in this docume nt, or other Intel literature may be obtained by call ing
1-800-548-4725 or by visiting Intel’s website at http://www.intel .co m.
Copyrigh t © Intel Corpor at ion, 2001
*Third-party brands and nam es are the propert y of their respect ive owne rs.
Datasheet 3
Docu me nt #: 249097
Revision #: 002
Rev. D ate: June 19, 2001
Contents
Contents
1.0 Pin Assignments and Signal Des criptions ....................................................................8
2.0 Functional Descriptio n ..................................................................................................11
2.1 Controller Compatibility Modes ...........................................................................12
2.2 Transmit Function................................................................................................12
2.2.1 Jabber Control Function.........................................................................13
2.2.2 SQE Function.........................................................................................13
2.2.2.1 SQE Disable Function (LXT907 only) .......................................14
2.3 Receive Function.................................................................................................14
2.3.1 Polarity Reverse Function......................................................................15
2.3.2 Collision Detection Function...................................................................15
2.4 Loopback Functions............................................................................................16
2.4. 1 Standar d Twisted-Pair Loopba ck........................... ... .............. ... ............16
2.4. 2 Extern al Loo pbac k....... ...... .... ............. ... .............. ... ............. .... ............. ..16
2.4.3 Forced Twisted-Pair Loopback...............................................................17
2.4.4 AUI Loopback.........................................................................................17
2.5 Link Integ r ity T es t Functi o n...................... .... ............. ... .............. ... ............. .... .....17
2.5.1 Remote Signaling...................................................................................19
3.0 Application In format i on.................................................................................................19
3.1 Twisted-Pair Impedance Matching......................................................................19
3.2 Cryst al In fo rma tio n............... .... ............. ... .............. ... ............. .... ............. ... .........20
3.3 Magnetics Information.........................................................................................21
3.4 Typical Applications.............................................................................................21
3.4.1 Auto Port Select with External Loopback Control...................................21
3.4.2 Full-Duplex Support................................................................................24
3.4.3 Dual Network Support - 10Base-T and Token Ring...............................25
3.4.4 Manual Port Select with Link Test Function ...........................................26
3.4.5 Three Media Application.........................................................................28
3.4.6 AUI Encoder/Decoder ONLY..................................................................29
3.4.7 150Ω Shie ld ed Twiste d-Pa i r Only (LXT90 1 only).......... ............. ... .........30
4.0 T est Specifications.........................................................................................................31
4.1 Timi ng Diagr am s for Mode 1 (MD1 = Low, MD 0 = L o w)
Fi gu res 17 - 22....................................................................................................35
4.2 Timi ng Diagr am s for Mode 2 (MD1=Low, M D0=High)
Fi gu res 23 - 28....................................................................................................37
4.3 Timi ng Diagr am s for Mode 3 (MD1 = High, MD 0 = Low)
Fi gu res 29 - 36....................................................................................................39
4.4 Timi ng Diagrams for M ode 4 (MD1 = High, MD 0 = H i gh)
Fi gu res 37 - 42....................................................................................................42
5.0 M echani cal Specifi cation s.............................................................................................44
A Ordering Inf ormation .....................................................................................................45
Contents
4 Datashe et
Docu men t #: 249097
Revision #: 002
Rev. D ate: June 19, 2001
Figures 1 LXT901/907 Block Diagram..................................................................................7
2 LXT901/907 Pin Assignments...............................................................................8
3 LXT901/907 TPO Output Waveform ..................................................................12
4 Jabber Control Function .....................................................................................13
5 SQE Function .....................................................................................................1 4
6 Collision Detection Function ...............................................................................1 6
7 Link Integrity Test Function ................................................................................18
8 Remote Signa lin g Lin k Integ ri ty Pulse Timing ...... .................... .... ............. ... ......19
9 LAN Adapter Board - Auto Port Select with External LPBK Control ..................23
10 Full-Duplex Operation ........................................................................................2 4
11 380C26 Interface for Dual Network Support of 10BASE-T and Token Ring ......25
12 LAN Adap ter Board - Manual Port Sele ct wi th Link Test Func ti on ..... .............. ..26
13 Manual Port Select with Seeq 8005 Controller ..................................................27
14 Three Medi a Applic at ion ............ ... ............. .... ............. ... .............. ... ...................28
15 AUI Encoder/Decoder Only Application .............................................................29
16 150 Ω Shi eld ed Twi sted -Pa ir Only Ap plication (LXT9 01) .......................... ... ......30
17 Mode 1 RCLK/Start-of-Frame Timing ................................................................3 5
18 Mode 1 RCLK/End-of-Frame Timing ..................................................................3 5
19 Mode 1 Transmit Timing ....................................................................................36
20 Mode 1 Collision Detect Timing .........................................................................36
21 Mode 1 COL/CI Output Timing ...........................................................................36
22 Mode 1 Loopback Timing ...................................................................................3 6
23 Mode 2 RCLK/Start-of-Frame Timing ................................................................3 7
24 Mode 2 RCLK/End-of-Frame Timing ..................................................................3 7
25 Mode 2 Transmit Timing ....................................................................................38
26 Mode 2 Collision Detect Timing .........................................................................38
27 Mode 2 COL/CI Output Timing ...........................................................................38
28 Mode 2 Loopback Timing ...................................................................................3 8
29 Mode 3 RCLK/Start-of-Frame Timing (LXT901 only) .........................................3 9
30 Mode 3 RCLK/End-of-Frame Timing (LXT901 only) ..........................................39
31 Mode 3 RCLK/Start-of-Frame Timing (LXT907 only) .........................................4 0
32 Mode 3 RCLK/End-of-Frame Timing (LXT907 only) ..........................................40
33 Mode 3 Transmit Timing ....................................................................................41
34 Mode 3 Collision Detect Timing .........................................................................41
35 Mode 3 COL/CI Output Timing ...........................................................................41
36 Mode 3 Loopback Timing ...................................................................................4 1
37 Mode 4 RCLK/Start-of-Frame Timing ................................................................4 2
38 Mode 4 RCLK/End-of-Frame Timing ..................................................................4 2
39 Mode 4 Transmit Timing ....................................................................................43
40 Mode 4 Collision Detect Timing .........................................................................43
41 Mode 4 COL/CI Output Timing ...........................................................................43
42 Mode 4 Loopback Timing ...................................................................................4 3
43 LXT901/907 Package Specifications ..................................................................44
44 Ordering Information - Sample............................................................................45
Datasheet 5
Docu me nt #: 249097
Revision #: 002
Rev. D ate: June 19, 2001
Contents
Tables 1 LXT9 0 1/90 7 Sign a l Desc rip tio ns........ ...... .... ............. ... ....... ... .............. ... ............. .9
2 Controller Compatibility Modes ...........................................................................12
3 Cr yst al Spe cificatio ns........ ... ....... ... .............. ... ............. .... ............. ... .............. ... ..20
4 Suitable Crystals .................................................................................................20
5 Suitable Magnetics..............................................................................................21
6 Absolute Maximum Ratings.................................................................................31
7 Recommended Operating Conditions.................................................................31
8 I/O Electrical Characteristics...............................................................................31
9 AUI Electrical Characteristics..............................................................................32
10 Twisted-Pair Electrical Characteristics................................................................32
11 Switching Characteristics....................................................................................33
12 RC LK/ S ta rt -of- F ram e Timi ng................. ... .............. ... ....... ... ............. .... ............. ..33
13 RCLK/End-of-Frame Timing................................................................................34
14 Transmit Timing...................................................................................................34
15 Collision, COL/CI Output and Loopback Timing..................................................34
16 Product Information.............................................................................................45
Contents
6 Datashe et
Docu men t #: 249097
Revision #: 002
Rev. D ate: June 19, 2001
Revision History
Date Revision Page # Description
June 2001 002
20 Table 3: Changed Nom frequency from “25.0” to “20.0.”
23 Added 0.1 µF label to capacitor at bottom of Figure 9 graphic.
24 Added 0.1 µF label to capacitor at bottom of Figure 10
graphic.
25 Added 0.1 µF label to cap acitor at bottom of Figure 11 graphic
26 Added 0.1 µF l abel to cap aci tor at bottom of Figure 12 gr ap hic
27 Added 0.1 µF l abel to cap aci tor at bottom of Figure 13 gr ap hic
31 Added 2nd para under “Test Specifications”: Quality &
Reliability issues.
31 Removed “Ambient operating temperature” from Abso lute
Maximum Ratings table.
45 Added Appendix: Product Ordering Information
Universal 10BASE-T and AUI Transceivers — LXT901/907
Datasheet 7
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
Figure 1. LX T90 1/90 7 Block Diagra m
MODE SELECT LOGIC
Controller Compatibility
Port Select
Loopback
Link test
SQUELCH / LINK
DETECT
MANCHESTER
DECODER
COLLISION LOGIC
WATCHDOG
TIMER
XTAL
OSC
MANCHESTER
ENCODER
Select:
PLS Only
or
PLS / MAU
DO
MD0
TPOPA
TPONA
TPONB
TPIP
TPIN
PULSE SHAPER
AND FILTER
TWISTED PAIR
INTERFACE
COLLISION/
POLARITY
DETECT
CORRECT
RC
RC
DI
LPBK
COLLISION
RECEIVER
CI
MD1
TPOPB
DOP
DON
DIP
DIN
CIP
CIN
LEDR LEDT/PDN LEDC/FDE NTH JAB PLR
+
-
DROP CABLE
INTERFACE
ECL
TX
AMP
RX
SLICER
CMOS
TX
AMP
*DSQE
*(LXT907 only)
*STP
REMOTE SIGNALING
*(LXT901 only)
AUTOSEL
PAUI
LBK
LI
TCLK
CLKO
CLKI
TEN
TXD
CD
LEDL
RXD
RCLK
COL
RLD
RJAB
RCMPT
RX
SLICER
LXT901/907 — Universal 10BASE-T and AU I Tra nsceivers
8Datasheet
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
1.0 Pin Assignments and Signal Descriptions
Figure 2. LX T901/907 Pin Assignments
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
n/c
n/c
PAUI
DIP
DIN
n/c
DOP
DON
VCCA
VCC1
CIP
CIN
NTH
MD0
MD1
n/c
n/c
n/c
TPIN
TPIP
n/c
DSQE (907) or STP (901)
TPONB
TPONA
VCC2
GND2
TPOPA
TPOPB
PLR
RJAB
n/c
n/c
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
n/c
RLD
LI
n/c
JAB
TEST
TCLK
TXD
TEN
CLKO
CLKI
COL
AUTOSEL
n/c
n/c
n/c
n/c
RCLK
CD
RXD
RCMPT
n/c
RBIAS
n/c
GNDA
GND1
LBK
LEDC/FDE
LEDL
LEDT/PDN
LEDR
n/c
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
7
8
9
10
11
12
13
14
15
16
17
RLD
LI
JAB
TEST
TCLK
TXD
TEN
CLKO
CLKI
COL
AUTOSEL
TPIN
TPIP
DSQE (907) or STP (901)
TPONB
TPONA
VCC2
GND2
TPOPA
TPOPB
PLR
RJAB
39
38
37
36
35
34
33
32
31
30
29
18
19
20
21
22
23
24
25
26
27
28
LEDR
LEDT/PDN
LEDL
LEDC/FDE
LBK
GND1
RBIAS
RCMPT
RXD
CD
RCLK
MD1
MD0
NTH
CIN
CIP
VCC1
DON
DOP
DIN
DIP
PAUI
6
5
4
3
2
1
44
43
42
41
40
LXT901/907PC XX
XXXXXX
XXXXXXXX
Part #
LOT #
FPO #
Rev #
LXT901LC XX
XXXXXX
XXXXXXXX
Part #
LOT #
FPO #
Rev #
Universal 10BASE -T and AUI Trans cei vers — LXT901 /907
Datasheet 9
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
Table 1. LXT901/907 Signal Descriptions
PLCC LQFP Symbol I/O Description
1
34
-
10
56
9
VCC1
VCC2
VCCA
I
I
I
Power Inputs. Power supply inputs of +5 volts.
(LQFP Only)
2
311
12 CIP
CIN I
IAUI Collision Pair . Differ enti al input to the AU I transceiv er CI circuit. The input is
collision signaling or SQE.
413NTHI
Normal Threshold. Selects normal or reduced threshold.
When NTH is High, the normal twisted-pair squelch threshold is in effect.
When NTH is Lo w , the normal twisted- p air sq uelch thr es hold is reduced by 4.5 dB.
5
614
15 MD0
MD1 I
IMode Select 0 (MD0), Mode Select 1 (MD1). Mode select pins determine the
controller compatibility mode in accordance with Table 2.
718RLDO
Remote Link Down. O utput goes high to signal to the controller that the remote
port is in link down condition.
819 LI1
Link Test E nable. Controls Link Integrity Test; enabled when LI = High, disabled
when LI = Low
921JABOJabber Indicator. Output goes High to indicate Jabber state.
10 22 TEST I Test. For Intel inter nal use only. It is recommended to tie this pin High externally.
11 23 TCLK O Transmit Clock. A 10 MHz clock output. This clock signal should be directly
connected to the transmit clock input of the controller.
12 24 TXD I Transmit Data . Input signal containing NRZ data to be transmitted on the
network. Connect TXD dir ectly to the transmit data output of the controller.
13 25 TEN I Tr an smit Enable. Enables data transmission and starts the watchdog timer.
Synchronous to TCLK (see Test Specifications for details).
14
15 26
27 CLKO
CLKI O
ICrystal Oscillator. A 20 MHz crystal m ust be connected across these pins, or a
20 MHz clock applied at CLKI with CLKO left open.
16 28 COL O Collision Detect. Output which drives the collision detect input of the controller.
17 29 AUTOSEL I
Automatic Port Select.
When High, automatic port selection is enabled (the 901/907 defaults to the AUI
port only if twisted-pair link integrity = Fail).
When Low, manual port selection is enabled (the PAUI pin determines the active
port).
18 34 LEDR OD Receive LED. Open drain driver for the receive indicator LED. Output is pulled
Low during receive.
19 35 LEDT/
PDN OD
I
Transm it LED (LEDT)/Pow er-Down (PDN). Open drain driver for the transmit
indicator. Output is pulled Low during transmit. Do not allow this pin to float. If
unused, tie High.
If externally pulled Low, the LXT901/907 goes to power-down state.
20 36 LEDL OD
I
Link LED. Open drai n driv er for li nk i ntegrity indic ator. Output is pull ed Low during
link test pass.
If externally tied Low, internal circuitry is forced to “Link Pass” state and the 901/
907 will transmit link test pulses continuously.
1. I/O Column Coding: I = Input, O = Output, OD = Open Drain
LXT901/907 — Un iversal 10BASE-T and AU I Tra nsceivers
10 Datasheet
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
21 37 LEDC/
FDE OD
I
Collision LED (LEDC )/Full Duplex Enable (FDE). Open drain driver for the
collision indicator pulls Low during collision. LED “On”(i.e., Low output) time is
extended by approximately 100 ms.
If externally tied Low, the LXT901/907 enables full duplex operation by disabling
the internal twisted-pair loopback and collision detection circuits in anticipation of
external twisted-pair loopback or full duplex operation.
If this pin is not used, tie high or directly to VCC.
22 38 LBK I Loopback. Enables internal loopback mode.
Refer to Functional Descriptions for details.
23
33
–
39
55
40
GND1
GND2
GNDA
–
–
–
Ground Returns. Grounds
(LQFP Only)
24 42 RBIAS I Bias Control. A 12.4 kΩ 1% resistor to ground at this pin controls operating
circuit bias.
25 44 RCMPT O Remote Compatibility. Output goes High to signal the controller that the remote
port is compatible with the LXT901/LXT907 remote signaling features.
26 45 RXD O Receive Data. Connect RXD directly to the receive data input of the controller.
27 46 CD O Carrier Detect. An output to notify the controller of acti vity on the network.
28 47 RCLK O Receive Clock. A recovered 10 MHz clock which is synchronous to the received
data. Connect to the controller receive clock input.
29 51 RJAB O Remote Jabber. Output goes High to indicate the remote port is in Jabber
condition.
30 52 PLR O Polarity Reverse. Output goes High to indicate reversed polarity at the twisted-
pair input.
31
36
32
35
53
58
54
57
TPOPB
TPONB
TPOPA
TPONA
O
O
O
O
Twisted-Pair T ransmit Pair s A & B. Two differ enti al driv er p air outp uts (A and B)
to the twisted-pair cable. The outputs are pre-equalized. Each pair must be
shorted together and tied to the transformer with a 24.9Ω 1% series resistor to
match impedance of 100Ω.
Refer to Figure 16 in the Applications Section for information on 150Ω
configurations.
37 59 STP
(LXT901) I
STP Select (LXT901 only).
When STP is Low, 150Ω termination for shielded twisted-pair is selected.
When STP is High, 100Ω termination for unshielded twisted-pair is selected.
LXT907 is designed for 100Ω UTP termination (not selectable).
DSQE
(LXT907) I
Disable SQE (LXT907 only).
When DSQE is High, the SQE function is disabled.
When DSQE is Low, the SQE function is enabled.
SQE must be disabled for normal operation in Hub/Switch applications.
LXT901operates with SQE enabled (not selectable).
38
39 61
62 TPIP
TPIN I
ITwisted-Pair Receive Pair. A differential input pair from the twisted-pair cable.
Receive filter is integrated on-chip. No external filters are required.
40 3 PAUI I
Port/AUI Select. In Manual Port Select mode (AUTOSEL Low), PAUI selects the
active port.
When PAUI is High, the AUI port is selected.
When PAUI is Low, the tw isted-pair port is selected.
In Auto Port Select mode, PAUI must be tied to ground.
Table 1. LXT901 /907 Signal De sc rip tions (Continue d)
PLCC LQFP Symbol I/O Description
1. I/O Column Coding: I = Input, O = Output, OD = Open Drain
Universal 10BASE -T and AUI Trans cei vers — LXT901 /907
Datasheet 11
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
2.0 Function al Description
The LXT901/9 07 Univer sal 10BA SE-T and AU I T r ansceiver s perform t he physi cal l ayer sig naling
(PLS) and Media Attachment Unit (MAU) functions as defined by the IEEE 802.3 specif ication.
Th ey fun ctio n as PLS- onl y devi ces ( fo r us e with 1 0BA SE-2 o r 10 BASE-5 coa xia l c ab le networ ks),
or as Integrat ed PLS/MAU devic es (for use with 10BASE-T twisted-p air networks). In addition to
standard 10 Mbps operation, they a lso sup port full-duplex 20 Mb ps o pe rati on. Unle ss other wise
noted, all the information in this dat a sh eet applies to b oth the LXT901 and LXT907.
The LXT901/90 7 interfaces a back-end cont ro ller to either an AUI drop cab le or a twisted-pair
cable. The contro ller in terfac e includ es tr ansmit an d recei ve clocks an d NRZ dat a channel s, as well
as mode control logic and signaling. The AUI int erf ace com pr ises three circuits: Data Outp ut
(DO), Data Input (DI), a nd Col lision (CI). The t wisted-pair interface compris es two circuits:
Twisted-Pair Input (TPI) and Twisted-Pair Output (TPO). In addition to the three basic interfaces,
the LXT901/907 co ntains an internal crystal oscillator and four LED driver s for visual status
reporting.
Functions are defined f rom the back-end controller side of the interface. The Transm it function
ref ers to dat a trans mitted by the back-end to th e AUI cable (PL S-on ly mode ), or to the twist ed- pair
network (Integrated PLS/M AU mode ). The Receive function refers to dat a recei ved by the back-
en d from the AUI cable (PLS-only), or from the twisted- pa ir network (Integr a te d PLS/MAU
mode). In the integrate d PLS/ MAU mode, the LXT9 01/907 perf orms all required MAU functions
defined by the I EEE 802.3 10BASE–T sp ecification, such as col lision detection, link integrity
tes ting, signal quality error messaging, jabber control, and lo opb ack. In the PLS-only mode, the
LXT901 /907 recei ves i ncoming signa ls f rom the AUI DI ci rcuit with ± 18 ns o f jit ter an d dri ves t he
AUI DO ci rc u it.
41
42 4
5DIP
DIN I
IAUI Receive Pair. Differential input pair from the AUI transceiver DI cir cuit. The
input is Manchester encoded.
43
44 7
8DOP
DON O
OAUI Transmit Pair. A differential output driver pair for the AUI transceiver cable.
The output is Manchester encoded.
–
1, 2, 6,
16, 17,
20, 30,
31, 32,
33, 41,
43, 48,
49, 50,
60, 63,
64
N/C –No Connect (Internally tied to ground).
Table 1. LXT901/907 Signal Descriptions (Continued)
PLCC LQFP Symbol I/O Description
1. I/O Column Coding: I = Input, O = Output, OD = Open Drain
LXT901/907 — Un iversal 10BASE-T and AU I Tra nsceivers
12 Datasheet
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
2.1 Controller Compatibility Modes
The LXT90 1/907 ia comp atible with most indus try standard contro llers, including devices
produ ced by Motor ola, AM D, I ntel, F ujitsu, Natio nal S emiconduc tor , Seeq, an d Texas I nstrum ents.
Four d ifferent control signal timing and pola rity schemes (Modes 1 through 4) are require d to
achieve this compatibility. Mode select pins (MD0 and MD1) determine controller compatibility
mode s as listed in Table 2 . Refer to Test Specifications for a complete set of timing diagrams for
each mode.
2.2 Transmit Function
The LXT901/907 receives NRZ data from th e controller at the TXD input, as shown in Figu re 1,
“LXT901/907 Block Diagram” on page 7 , and passes it through a Manchester encoder. The
encoded data is then transferred to either the AUI cable (DO cir c uit) or the t wis ted-pair networ k
(TPO circui t). The advanced inte gr ated pulse shaping and fi ltering network pr odu ces the output
signal on TP ON and TPOP, a s show n in Figure 3. The TP O output is pre-dist orted an d pre-filter e d
to meet th e 10BASE-T jitter template. An internal co ntinuous resistor-cap acitor filt er is used to
remove any high-freque ncy clocking noise from the pulse shaping c i rcuit ry. Integrate d filt e rs
sim plify the de sign work required for FCC co mpliant EMI performance. During idle periods, the
LXT901/907 transmits link integrity tes t pulses on the TPO circuit (if LI is enabled and integr ated,
PLS/ MAU mode is sel ected). External resis tors control the terminatio n im pedance for the
LXT907. External resistors and the STP pin contr ol terminat ion impedance on the LXT901.
Tabl e 2. Con t rol ler Compati b i lity Modes
Controller Mode Setting
MD1 MD0
Mode 1
For Motorola 68EN360, MPC860, Advanced Micro Devices AM7990, or compatible
controllers Low Low
Mode 2
For Intel 82596 or compatible controllers1Low High
Mode 3
For Fujitsu MB86950, MB86960 or compatible controllers (Seeq 8005)2High Low
Mode 4
For National Semiconductor 8390 or compatible controllers (TI TMS380C26) High High
1. R efer to Intel Application Note 51 when designing with Intel controllers.
2. SEEQ controllers require inverters on CLKI, LBK, RCLK and COL.
Figure 3. LX T901/907 TPO O utput Wavef orm
Universal 10BASE -T and AUI Trans cei vers — LXT901 /907
Datasheet 13
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
2.2.1 Jabber Control Function
Figure 4 is a stat e diagr a m of the LXT901/907 Jabb e r control funct ion. The on-chip watch dog
timer prevents the DTE from locking into a continuous tr ansmit mode. When a transmission
exceeds the time limit, the watchdog timer disables the tran smit and loopback functions, and
activates the JAB pin. Once th e LXT901/907 is in the jabber state, the TXD cir cuit must remain
idle fo r a peri od of 25 0 to 75 0 m s be f o re it wi ll exi t th e ja bbe r s t at e .
2.2.2 SQE Function
In the integ rated P LS/ MAU mode, the LX T901/907 supports the s i gnal quality error (SQE)
function, as shown in Fi gu re 5 on pa ge 14. After every successful transmi s si on on the 10 BASE -T
netwo rk when S QE is en able d, the L XT901 /90 7 tran smit s the S QE sig nal fo r 10BT ± 5BT over the
inter nal CI circui t which is i ndicated on the COL pin of the device. When u sing th e 10BAS E-2 port
of th e LX T 901/907, t he SQ E function is determined by the exter nal MAU attached.
Figure 4. Ja bber C ontrol Function
No Output
Nonjabber Output
Start_XMIT_MAX_Timer
Power On
DO=Active
Jab
XMIT=Disable
LPBK=Disable
CI=SQE
Unjab Wait
Start_Unjab_Timer
XMIT=Disable
LPBK=Disable
CI=SQE
DO=Active*
XMIT_Max_Timer_Done
DO=Idle
DO=Idle
Unjab_ Timer_Done DO=Active*
Unjab_Timer_Not_Done
LXT901/907 — Un iversal 10BASE-T and AU I Tra nsceivers
14 Datasheet
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
2.2.2.1 SQE Disable Function (LXT907 only)
SQE mus t be disa bled f or normal ope ra tion i n hub and switch a pplications. The LXT907 offe rs an
SQE disable function. The SQE function is disabled when DSQE is set High, and enabled when
DSQE is Low.
2.3 Receive Function
The LXT901/907 receiv e function acq uires timin g and data f rom the twist ed-pair net work (the TPI
circuit) or from the AUI (the DI circuit). Valid received signal s are pass e d thro ugh the on- chip
filters and Manchester decoder, then output as decod ed NRZ dat a and r eceive timing on the RXD
an d R C L K pi ns, re s pe c t i ve l y.
An inter nal RC filter and an intelligent sq uelch function dis c riminate n ois e from link test pulses
and valid data streams. The receive function is activated only by valid data streams above the
squel c h level and with proper tim ing. If the differe ntial signal at the TPI or the DI circui t inputs
fal l s below 75 percent of the threshold level (uns quelched) for 8 bit ti mes (typical ), the LXT901/
907 receive funct ion enters the Idle state. If the polari ty of the TPI cir cuit is reversed, LXT901/
907 dete cts the polari ty reverse and reports it via the PLR output. The L XT 901/907 a utomatically
corrects reversed polarity.
Figure 5. S QE Function
Output Idle
Output Detected
Power On
DO=Active
SQE Wait Test
Start_SQE_Test__Wait_Timer
SQE T e st
Start_SQE_Test_Timer
CI=SQE
SQE_Test__Wait_Timer_Done∗
XMIT=Enable
DO=Idle
SQE_Test_Timer_Done
XMIT=Disable
Universal 10BASE -T and AUI Trans cei vers — LXT901 /907
Datasheet 15
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
2.3.1 Polarity Reverse Function
Th e LX T901/907 polarity re ve rse fun c tion uses both link pulses and End-of-Frame d a ta to
deter mine th e polar ity of the rece ived s ignal . If Link Int egrity Testing is dis able d, p olarit y dete ction
is based only on received data. A reversed polarity condition is detected wh en eight opposi te
receive link pulses are detected without receipt of a link pulse of the exp ected polarity. Reversed
polarity is also detected if four frames are received with a reversed start-of-idle. Whenever a
correct polari ty f rame or a cor rect link puls e is rec eived, these two counters are reset to zero. If the
LX T9 01/907 e nter s the link fail stat e and no valid da ta or link pulses are rec e ived wi thin 9 6 to 1 28
ms, th e polarity is reset to the default non-fl ipped condition. P olarity cor rection is always enabled .
2.3.2 Collision Detection Function
The collision detect ion function ope rates on the twisted pair side of the interf ace. For standar d
(hal f- duplex) 10BASE-T operation, a collis ion is defined as th e si mu ltaneous presence of valid
sig nals on both the TPI circ uit and the TPO cir cuit. The LXT9 01/907 repo rts col lisio ns to the back-
end via the COL pin. If the TPI ci rcuit becomes active while there is activity on the TPO circuit,
the TPI da ta is pa ssed to t he ba ck- end o ver the RXD cir cuit , d isabl ing nor mal lo opb ack. Fi gure 6 is
a stat e diagram of the LXT901/907 collision detection function. Refer to Test Specifications for
collision detection and COL /CI output timing .
Note: For full- duplex o pe ration on twisted-pair and AUI port s, the collision d e te c t ion circuitry must be
disabled.)
LXT901/907 — Un iversal 10BASE-T and AU I Tra nsceivers
16 Datasheet
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
2.4 Loopback Functions
2.4.1 Standard Twis ted-Pair Loopback
The LXT901/907 provides the standard loopba c k fu nction defined by the 10 BASE-T specification
for the twi sted-pai r port. The loopb ack function oper ates in conjun ction with the tran smit function .
Data transmitted by the back- e nd is internally looped back within the LXT901/907 from the TXD
pin through the Manchester encoder/decoder to t he RXD pin and re turned to the ba ck- e nd. This
standard loop back function is disa bled when a data collision occurs, clearing the RXD circuit for
the TPI da ta. Standa rd loopba ck is a lso disabled during li nk fail an d ja bber states. T he
LXT901/907 als o provides thr e e additional loopback func tion s.
2.4.2 External Loopback
An external lo opback mode, useful for sy st em -level testing , is controlled by the LEDC pin. When
LEDC is tied Low, the LXT901/907 disables the collision detection and inter nal loopback circuits
to allow ex ternal loop back. External loopback mode can be set on either twis ted-pair or AUI ports.
Figure 6. Collision Detectio n Function
Idle
Power On
A
Collision
TPO=DO
DI=TPI
CI=SQE
Output
TPO=DO
DI=DO
Input
DI=TPI
DO=Active∗
TPI=Idle∗
XMIT=Enable
DO=Active∗
TPI=Active∗
XMIT=Enable
A A
DO=Active∗
TPI=Active∗
XMIT=Enable
DO=Active∗
TPI=Idle
DO=Idle+
XMIT=Disable
DO=Idle
TPI=Idle
TPI=Active
Universal 10BASE -T and AUI Trans cei vers — LXT901 /907
Datasheet 17
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
2.4.3 Forced Twisted-Pair Loopback
“Forced” t wis ted-pair loopback is controlled by the L BK pin. Whe n the twisted-pair port is
selected and LBK is High, twis ted-pair loopback is “forced”, overriding collisions on the twisted-
pair circuit. When LBK is Low, normal loopback is in effec t.
2.4.4 AUI Loopback
AUI loopback is also controlled by the LBK pin. When the AUI port is selected and LBK is High,
data tr ans mitted by the back -end is internally looped back from the TXD pin th rou gh t he
Ma nc heste r e ncoder/dec oder to the RXD pin. When LBK is Low, no AUI loopback occu rs.
2.5 Link Integrity Test Function
Figur e 7 on pa ge 18 is a sta te dia gram of the LXT901/ 907 Link Integrity test function. The link
integrity test is used to determine the status of the receive side twisted-pair cable. Link integ rity
tes ting i s enabled when the LI pi n is tied H igh. When enab led , the receiv er reco gnizes l ink in teg rity
pulses wh ich are t ransmitted in the absence of receive traffic. If no serial data strea m or link
integrity pulses are detected within 50 - 150 ms, the chip enters a link fail st ate and disables the
transmit and norm a l loopba c k functions . T he L XT901/907 ignores any link integrity pu lse with
inter val les s than 2 - 7 ms. The LXT9 01/ 907 wil l remain in th e link fai l state unti l it d etects ei ther a
serial data packet or two or more link integrity pulses.
LXT901/907 — Un iversal 10BASE-T and AU I Tra nsceivers
18 Datasheet
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
Figure 7. Li nk Integrity Test Function
Idle Test
Start_Link_Loss_Timer
Start_Link_Test_Min_Timer
Pow e r On
Link Test Fail Reset
Link_Count=0
XMIT=Disable
RCVR=Disable
LPBK=Disable
Link_Loss_Timer_Done
∗TPI=Idle
∗Link_Test_Rcvd=False
TPI=Active+
(Link_Test_Rcvd=True
∗Link_Test_Min_Timer_Done)
Link Test Fail Wait
XMIT=Disable
RCVR=Disable
LPBK=Disable
Link_Count=Link_Count + 1
Link Test Fail
Start_Link_Test_Min_Timer
Start_Link_Test_Max_Timer
XMIT=Disable
RCVR=Disable
LPBK=Disable
Link_Test_Rcvd=False
∗TPI=Idle
TPI=Active
TPI=Active Link_Test_Rcvd=Idle
∗TPI=Idle
Link Test Fail Extended
XMIT=Disable
RCVR=Disable
LPBK=Disable
TPI=Active +
Link_Count=LC_Max Link_Test_Min_Timer_Done
∗Link_Test_Rcvd=True
(TPI=Idle∗ Link_Test_Max_Timer_Done) +
(Link_Test_Min_Timer_Not_Done
∗Link_Test_Rcvd=True)
TPI=Idle∗
DO=Idle
Universal 10BASE -T and AUI Trans cei vers — LXT901 /907
Datasheet 19
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
2.5.1 Remote Signaling
The LXT901/907 transmits standard link pulses which meet the IEEE 802.3 10BASE-T
specifica t ion. However, the LXT 901/ 907 encodes additiona l status information into the link pulse
by varying the l ink pulse ti ming. This is referred to a s re mote signaling. Us ing alternate pulse
intervals, the LX T901/90 7 can signal th ree local conditions: link down, ja bber, and r emote
signaling compatibility. Figure 8 sho ws the interval variations used to signal local status to the
other end of the line. The LXT901/907 also recognizes these alternate pulse intervals when
received from a remot e unit. Remote status conditions are reported to the controller over the RLD,
RJA B a nd RCMPT output pins.
3.0 A pplication Information
3.1 Twisted-Pair Impedance Matching
Resi stors must be in stall ed on each i nput an d output pai r to m atch impe dance of the netw ork media
being used. The LXT907 is configured with 100Ω t erminatio n for Unshiel ded T wis ted-Pair (UTP).
In this case, the positive and negative sides of both output pairs are shorted together (TPOPA/
TPOPB and TPONA/TPONB) and tied to the trans former through a 24.9Ω 1% serie s res ist o r.
Figure 8. Re m ote Signali ng Link Integr ity Pulse Timing
10 ms 20
ms 10
ms 20 ms 10
ms
10
ms 20 ms 20 ms 10
ms
10 ms 15 ms 20 ms 10
ms 20 ms 10
ms
15 ms 15 ms 20 ms
20 ms 10
ms
15 ms 20 ms 10
ms
15 ms 20 ms 15 ms 10
ms
LI-RLD
(note 1)
(note 2)
(note 3)
LI-RJAB
LI-RCMPT
907F07.VSD
NOTES:
1. For Remote Link-Down (RLD) signaling, the interval between LI pulses increments from 10 ms to 15 ms, and then the cycle
starts over.
2. For Remote Jabber (R JAB) s ignal ing, the interval betw een LI pulses decrem ents from 20 ms to 15 m s to 10 ms, and then the
cycle starts over.
3. For Remote Compatib ility (RCMPT) signal ing, the in ter val between LI puls es conti nually swi tches bet ween 10 ms and 20 ms.
LXT901/907 — Un iversal 10BASE-T and AU I Tra nsceivers
20 Datasheet
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
The LXT901 is designed with an STP Select pin that allo ws the device to match both 100Ω and
150Ω media. A dual resistor combination can be configured to ac com mo date either line
termination, as shown in Figure 16 on page 30. Whe n 100Ω termination is selected, both A and B
pairs ar e driven in parall el. When 150 Ω termin ation is selected, the B pair is tri-stated and only th e
A pai r is driven .
3.2 Crystal Information
Desig ners shoul d tes t and validate crystals to sy stem requir ements befor e c om mitting to a specific
component. Crystal specifications for the LXT901/907 are show n in Table 3. Based on limited
evaluation, Table 4 lists some suitable crys tals.
Tabl e 3. Cry stal Speci ficatio n s
Parameter Min Nom Max Units
Frequency –20.0 –MHz
Frequency1 Stability ––+/-80 ppm
1. Test condition = -40 - 85oC
Tabl e 4. Sui table Crystals
Manufacturer Part Number
MTRON MP-1
MP-2
Universal 10BASE -T and AUI Trans cei vers — LXT901 /907
Datasheet 21
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
3.3 Magneti cs Information
The LXT901 and LXT907 require a 1:1 ratio for th e recei ve transformer and a 1:√2 ratio for the
transmit transformer on the twisted-pair interface. The AUI Interface requires a 1:1 ratio for both
the tr ans m it and receive transformers. Designers should test and validate magnetics for system
requirements before committing to a speci fic compon ent. Table 5 lists s om e su itable magnetics.
3.4 Typic al Ap plica tions
Figur e 9 on pa ge 23 throu gh Figu re 16 on page 30 show typical LXT901/907 a pplications.
3.4.1 Auto Port Select with External Loopback Control
Fig ure 9 on pa ge 23 is a ty pica l LXT 901/9 07 ap pli catio n. T he dia gra m is arra nged to gr ou p simi lar
pins tog ether; it does not represent the actual LXT901/907 pino ut. The controller interface pin s
(trans mit data, clock and enable; receiv e data and clock; and the collision detect, car rier detect and
loop back control pins) are sho wn at th e top left.
Table 5. Su itable Magnetics
Manufacturer Part Number
Twisted-Pair
Fil-Mag 23Z128
23Z128SM
Valor PT4069
ST7011
Belfuse A553-0716
S553-0716
HALO TD42-2006Q
TG42-1406N1
AUI
Fil-Mag 23Z90
23Z90SM
Valor LT6032
ST7032
HALO TD01-0756K
TG01-0756N
LXT901/907 — Un iversal 10BASE-T and AU I Tra nsceivers
22 Datasheet
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
Programma ble option pins a re groupe d c e nter le ft. The PA UI pin is tied Low and all ot he r option
pi ns a re ti e d High . T hi s se t-up sel e c t s the fo ll owi n g op tio n s :
•Autom a tic Port Selection
(PAUI Low and AUT OSEL High)
•Normal Receive Thres hold (NTH Hi gh)
•Mode 4, compatible with National NS8390 co ntrolle rs (MD0 Hi gh, MD1 High)
•SQE Disabled (DSQE High on LXT907 only)
•100Ω termination UTP cable (STP Hi gh on LXT901 only)
•Lin k Testing Enabled (LI High)
Status outputs are groupe d a t lower left. Lo c a l status outputs drive LED indica tors and remote
status in dicators are ava ilable as required.
Power and ground pi ns are shown at the bottom of the diagra m. A single power supply is used for
both VCC1 and VCC2 with a decoupli ng capacito r installed between the power and ground busses.
The twisted-pair and AUI interfaces are shown at uppe r and lower right, respectively. Impedance
matching resistors for 100Ω UTP are install e d in each I/O pair but no exte rnal filte rs are required.
Universal 10BASE -T and AUI Trans cei vers — LXT901 /907
Datasheet 23
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
Figure 9. LAN Ada pte r Board - Auto Port Select with Ext erna l LPBK C ontrol
LXT901/907
20 MHz
20 pF 20 pF
CLKI
TXD TPIN 50 Ω
50 Ω
TPIP
1 : 1116
14
6
5
4
3
2
1
11
0.1 µF
9
RJ45
3
6
8
To 10 BASE -T TWISTED-
PAIR NETWORK
1
2
4
5
7
89
10
12
13
15
16 1
2
3
4
5
6
7
8
15
14
13
12
9
10
11
+ 12 V
CIN
CIP
DON
DOP
DIN
DIP
RBIAS
GND2
GND1
TEN
D - CONNE CTOR to
AUI DROP CABLE
Chassis
Gnd
Fuse
78 Ω
78 Ω
78 Ω
12.4 kΩ 1%
TCLK
RCLK
RXD
CD
COL
LBK
PAUI
AUTOSEL
NTH
MD0
MD1
DSQE (907)
STP (901)
LI
JAB
PLR
TXD
TXE
TXC
RXC
RXD
CRS
COL
LBK
Green Red Red Red
NS8390 BACK -END
CONTROLLER
INTERFACE
LOOPBACK
ENABLE
PROGRAMMING
OPTIONS
LINE STATUS
+5 V
LEDC/FDE
LEDR
LEDT/PDN
LEDL
VCC1
VCC2
2
CLKO
330 330 330330
TEST
TPONA
TPONB
TPOPA
TPOPB
24.9 Ω 1%
24.9 Ω 1%
Bias resistor RBIAS should be located close to the pin and isolated from other signals.
Optional: Centertap capacitor may improve EMC depending on board layout and system design.
2
1
1
1 : 2
1 : 1
RJAB
RLD
RCMPT
REMOTE
STATUS
1 : 1
0.1 µF
LXT901/907 — Un iversal 10BASE-T and AU I Tra nsceivers
24 Datasheet
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
3.4.2 Full-Duplex Support
Figure 10 shows the LXT907 with a Texas Instruments 380C24 CommProcessor. The 380C24 is
compatibl e with Mode 4 (MD0 and MD1 both High). Whe n used with the 380C24 or ot he r full -
duplex-capable controll e rs, the LXT907 supports full-dupl e x Ethernet, effectively doubl ing the
avai la ble bandwidth of the ne twork. In this application, the SQE func tion is enable d (DSQE is tied
Low) a nd the AUI port is not used.
Figure 10. Ful l -Dupl ex Operation
LXT907
CLKI
TXD TPIN 50 Ω
50 Ω
TPIP
1 : 1116
14
6
5
4
3
2
1
11
0.1 µF
9
RJ45
3
6
8
CIN
CIP
DON
DOP
DIN
DIP
RBIAS
GND2
GND1
TEN
2
12.4 kΩ
TCLK
RCLK
RXD
CD
COL
LBK
LEDC/FDE
TXD
TXEN
TXC
RXC
RXD
CSN
COLL
LPBK
1 %
+5 V VCC1
VCC2
CLKO
TMS380C24
1 : 2
To 10 BASE-T TWISTED-
PAIR NETWORK
20 MHz 20 pF20 pF
*TEST0 1N914
10 KΩ
4
Bias resistor RBIAS should be located close to the pin
and isolated from other signal s.
1
2
3
4
Half/Full Duplex Selection con tr olled by TMS380C24 Pins
Test0 and OUTSEL0 .
AUTOSEL
NTH
MD0
MD1
LI
JAB
PLR
Green Red Red
PROGRAMMING
OPTIONS
LINE STATUS
LEDR
LEDT/PDN
LEDL
330 330
OUTSEL0
PAUI
330
1
4.7 KΩ
TEST
DSQE (907)
*Open Collector
Driver
TPONA
TPONB
TPOPA
TPOPB
24.9 Ω 1%
24.9 Ω 1%
The TMS380 C2 6 m ay be s ub s ti tu t e d for dual network
sup por t of 10 BASE -T and Tok en Ring.
Opt io na l: Cen ter tap cap ac i to r m ay impr ov e EM C
depending on board layout and system design.
3
RJAB
RLD
RCMPT
REMOTE
STATUS
0.1 µF
Universal 10BASE -T and AUI Trans cei vers — LXT901 /907
Datasheet 25
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
3.4.3 Dual Network Support - 10Base-T and Token Ring
Figure 1 1 shows the LXT901/907 with a Texas Instruments 380C26 CommProcessor. The 380C26
is compatible with Mode 4 (MD 0 a nd MD1 both High). When us e d with the 380C26, both the
LXT901/907 and a TMS38054 Token Ring transceiver can be tied to a single RJ-45 allowing dual
network support from a single connector. The LXT901/907 AUI port is not used. The LXT901
STP is High and t he LXT9 07 DSQE is Low.
Figure 11. 380C26 Interface fo r Dual Netw ork Support of 10BASE-T and Token Ring
LXT901/907
20 MHz
20 pF 20 pF
CLKI
TXD TPIN 50 Ω
50 Ω
TPIP
1 : 1116
14
6
5
4
3
2
1
11
0.1 µF
9
2
TPONA
TPONB
TPOPB
TPOPA
RJ45
3
6
8
From TI TMS38054 Token
Ring Transceiver
CIN
CIP
DON
DOP
DIN
DIP
RBIAS
GND2
GND1
TEN
1
12.4 kΩ 1%
TCLK
RCLK
RXD
CD
COL
LBK
PAUI
AUTOSEL
NTH
MD0
MD1
LI
JAB
PLR
TXD
TXE
TXC
RXC
RXD
CRS
COL
LBK
Green Red Red Red
PROGRAMMING
OPTIONS
LINE STATUS
+5 V
LEDC/FDE
LEDR
LEDT/PDN
LEDL
VCC1
VCC2
3
CLKO
330 330 330330
380C26
To TI TMS38054 Token Ring
Transceiver
1 : 2
To 10 BASE-T TWISTED-
PAIR NET WORK
Bias resistor RBIAS should be located close to the pin
and isolated from other signals.
1
2
3
Additional magnetics and switchin g logic (not shown)
are required to implement the dual network solution.
24.9 Ω 1%
24.9 Ω 1%
TEST
Optional: Centertap capacitor may improve EMC
depending on board layout and system design.
DSQE (LXT907)
STP (LXT901)
RJAB
RLD
RCMPT
REMOTE
STATUS
0.1 µF
LXT901/907 — Un iversal 10BASE-T and AU I Tra nsceivers
26 Datasheet
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
3.4.4 Manual Port Select with Link Test Function
With MD0 tied Low a nd MD1 tied High, the L XT 901/907 logic an d framing are set to Mode 3
(compatible with Fujitsu MB86950 a nd MB8696 0, and See q 8005 co ntrolle rs ). Fig ur e 12 sho ws
the s etup for Fujit su co ntrol lers. F igur e 13 on p age 27 s hows the four in vert ers re quire d to in ter fac e
with the S eeq 8005 controller. As in Fig ure 9 on page 23, both these Mode 3 applicat ion s show the
LI pi n tie d High, enabli ng L i nk Testing; an d the STP (LXT901 only) and NTH pins a re both t ie d
High, selecting the standard receiver threshold and 100Ω termination for unshiel ded twi sted-pa ir
cable. However, in these appl ications, AUTOSEL is tied Low, allowing exte rnal port selection
through th e PAUI pin. The remote status outputs are inverted to drive LED indicators.
Figure 12. LA N A dapt er Bo ard - Manual Po rt Selec t with Link Test Funct ion
LXT901/907
20 MHz
20 pF 20 pF
CLKI
TXD TPIN 50 Ω
50 Ω
TPIP
1 : 1116
14
6
5
4
3
2
1
11
0.1 µF
9
2
TPONA
TPONB
TPOPB
TPOPA
RJ45
3
6
8
To 10 BASE-T TWISTED-
PAIR NETWORK
1
2
4
5
7
89
10
12
13
15
16 1
2
3
4
5
6
7
8
15
14
13
12
9
10
11
+ 12 V
CIN
CIP
DON
DOP
DIN
DIP
RBIAS
GND2
GND1
TEN
D - CONNECTOR to
AUI DROP CABLE
Chassis
Gnd
Fuse
1
78 Ω
78 Ω
78 Ω
12.4 kΩ
TCLK
RCLK
RXD
CD
COL
LBK
AUTOSEL
NTH
MD0
MD1
DSQE (907)
STP (901)
LI
JAB
PLR
TXD
TEN
TCKN
RCKN
RXD
XCD
LBC
Red Red Red
MB86950 or MB86960
BACK-END/
CONTROLLER
INTERFACE
REMOTE & LINE
STATUS
1 %
+5 V
LEDC/FDE
LEDR
LEDT/PDN
LEDL
VCC1
VCC2
CLKO
330 330 330
Green
330
Bias res istor RBIAS s hould be located clo s e to the pin and is olat ed from othe r signa ls .
2
1
TEST
24.9 Ω 1%
24.9 Ω 1%
XCOL
Option al: Centert ap c apac it or m ay im pr ove EMC depending on boar d lay out and system design.
1 : 1
1 : 2
RJAB
RLD
RCMPT
PAUI
Port Selection
PROGRAMMING
OPTIONS
330 330
Amber
330
Amber Amber
1 : 1
0.1 µF
Universal 10BASE -T and AUI Trans cei vers — LXT901 /907
Datasheet 27
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
Figure 13. Manual Port Select with Seeq 8005 Controller
LXT901/907
CLKI
LBK TPIN 50 Ω
50 Ω
TPIP
1 : 1116
14
6
5
4
3
2
1
11
0.1 µF
9
1
TPONA
TPONB
TPOPB
TPOPA
RJ45
3
6
8
To 10 BASE-T TWISTED-
PAIR NETWORK
1
2
4
5
7
89
10
12
13
15
16 1
2
3
4
5
6
7
8
15
14
13
12
9
10
11
+ 12 V
CIN
CIP
DON
DOP
DIN
DIP
RBIAS
GND2GND1
CD
D - CONNECTO R to
AUI DROP CABLE
Chassis
Gnd
Fuse
78 Ω
78 Ω
78
>
12.4 kΩ
RXD
RCLK
COL
TEN
TCLK
TXD
PAUI
AUTOSEL
NTH
MD0
MD1
DSQE (907)
STP (901)
JAB
PLR
Red Red Red
REMOTE & LINE
STATUS
1 %
+5 V
LEDC/FDE
LEDR
LEDT/PDN
LEDL
VCC1
VCC2
330 330 330
1 : 2
Green
330
Port Selection
CLKO
8005
CLKI
LPBK
CSN
RxD
RxC
COLL
TxEN
TxC
TxD
External
20 MHz
Source Left Open
Bias resistor RBIAS should be located close to the pin and isolated from other signals.
TEST
24.9 Ω 1%
24.9 Ω 1%
Optional: Centertap capacitor may improve EMC depending on board layout and system design.
2
2
1
1 : 1
1 : 1
LI
RJAB
RLD
RCMPT
330 330
Amber
330
Amber Amber
0.1 µF
LXT901/907 — Un iversal 10BASE-T and AU I Tra nsceivers
28 Datasheet
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
3.4.5 Three Media Application
Figure 14 shows the LXT907 in Mode 2 (c ompatible with Intel 82596 controller s) with additional
media options for the AUI port. Two transformers are used to couple the AUI port to either a D-
connector or a BNC con nector. (A DP8 392 coax tr ansc eiver with PM6044 pow er supply is
requir ed to drive th e thin coax network through the BNC.)
Figure 14. Thre e Media Applicat io n
CLKI
TXD TPIN
50 Ω
TPIP
1 : 1116
14
6
5
4
3
2
1
11
9
TPONA
TPONB
TPOPB
TPOPA
RJ45
3
6
8
To 10BASE-T
TWISTED-
PAIR
NETWORK
1
2
3
4
5
6
7
8
15
14
13
12
9
10
11
+ 12 V
CIN
CIP
DON
DOP
DIP
RBIAS GND2
GND1
TEN
D - CONNECTOR to
AUI DROP CABLE
(Thick Co ax)
Chassis
Gnd
Fuse
1
78 Ω
78 Ω
12.4 Ω
TCLK
RCLK
RXD
CD
COL
LBK
PAUI
AUTOSEL
NTH
LI
MD1
MD0
JAB
PLR
TXD
RTS
TXC
RXC
RXD
CRS
CDT
LBK
82596 BACK-END/
CONTROLLER
INTERFACE
PROGRAMMING
OPTIONS
MODE SELECT
LI N E ST ATUS
1 %
+5 V
LEDC/FDE
LEDR
LEDT/PDN
LEDL
VCC1
VCC2
CLKO
1 : 2
20 M Hz
System
Clock
CLK
LinkTest
Enable
Power Down
1
2
4
5
7
89
10
12
13
15
16
78 Ω
1
2
4
5
7
89
10
12
13
15
16
DIN
CD-
CD+
TX-
VEE
TX+
RX-
RX+
VEE
CDS
TXD
RXI
VEE
RR-
RR+
GND
HBE
1N916
0V
BNC to THIN
COAX
NETWORK
1 kΩ 1%
-9V
V+
N/C
V-
5V
5V
EN
GND
GND
12
13
9
1+5 V
2
3
23
1 MΩ
1/2 W
24
TEST
1.5 kΩ
0.01 µF75µF / 1 kV
2
1
Bias resistor RBIAS should be located close to the pin and isolated
from other signals.
PM6044
DP8392
10 k Ω
DSQE (907)
10 k Ω
LXT907
F0.1 µ
50 Ω
2
Optional: Centertap capacitor may improve EMC depending on board
layout and system design.
24.9 Ω 1%
24.9 Ω 1%
1:1
1:1
0.1 µF
Universal 10BASE -T and AUI Trans cei vers — LXT901 /907
Datasheet 29
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
3.4.6 AUI Encoder/Decoder ONLY
In Figure 15, the DTE is connected to a coaxial network through th e AUI. AUTOSEL is tied Low
and PAUI is tied High, manually selecting the AUI port. The twi sted-pair port is not us e d. With
MD1 and MD0 both tied Low, the logic and fra ming are set to Mode 1 (compatible with AMD
AM79 90 cont ro ller s). The LI p in is ti ed L ow, disa blin g t he l ink test fu ncti on. The DS QE p in i s als o
tied Low, enabling t he SQE function on the LXT907. The LBK inpu t controls loop back. A
20 MHz system clock is supplied at CLK1, with CLK0 left open.
Figure 15. AUI Enco der/ De coder Only Application
LXT907
TXD
RBIAS
GND2
GND1
TEN
TCLK
RCLK
RXD
CD
COL
LBK
AUTOSEL
NTH
MD0
MD1
DSQE (907)
LI
JAB
PLR
TX
TENA
TCLK
RCLK
RX
RENA
CLSN
LBK
Red Red Red
AM7990 B ACK- EN D/
CONTROLLER
INTERFACE
LOOPBACK
CONTROL
PROGRAMMING
OPTIONS
LINE STATUS
GREEN
+5 V
LEDC/FDE
LEDR
LEDT/PDN
LEDL
VCC1
VCC2
CLKI
330 330 330330
1
2
4
5
7
89
1
10
12
13
15
16 1
2
3
4
5
6
7
8
15
14
13
12
9
10
11
+ 12 V
CIN
CIP
DON
DOP
DIN
DIP
D - CONNECTOR to
AUI DROP CABLE
Chassis
Gnd
Fuse
78 Ω
78 Ω
78 Ω
12.4 Ω 1%
CLKO
PAUI
B i as resist or RBIAS should be located close to th e pi n and i solated from the other signal s.
20 MHz Left Open
SYSTEM
CLOCK
TEST
1
RJAB
RLD
RCMPT
REMOTE
STATUS
1:1
1:1
LXT901/907 — Un iversal 10BASE-T and AU I Tra nsceivers
30 Datasheet
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
3.4.7 150Ω Shi elded Twi s te d - Pair On ly (L XT901 on ly )
Figure 16 shows the LXT901 in a typical twis ted-pair only application. The DTE is connect ed to a
10BASE-T network through the twisted-pa ir RJ-45 conne c tor. (The AUI por t is n ot used). With
MD0 tied High and MD1 tied Low, the LXT901 logic and framing are set to Mod e 2 (comp atible
with Intel 82596 controlle rs).
A 20 MHz system clock input at CLK1 is used in place of the cryst a l oscillator. (CLK0 is left
ope n). The L1 pin externally controls the link test functi on. The UTP/ST P and NTH pins are both
tied Low, selecting the reduced receiver threshold and 150Ω ter mination for shielded twisted-pair
cable. The switch at LEDT/PDN manually controls th e power-down mode.
Figure 16. 15 0 Ω Shielded Twisted-Pair Only Application (LXT901)
LXT901
TPIN 75 Ω
75 Ω
TPIP
1 : 1116
14
6
5
4
3
2
1
11
0.1 µF
9
TPONA
TPONB
TPOPB
TPOPA
RJ45
3
6
8
To 10 BASE- T TWI STED-
PAIR NETWORK
RBIAS
GND2GND1
PAUI
AUTOSEL
NTH
MD0
MD1
JAB
PLR
LEDC/
FDE
LEDR
LEDT/PDN
LEDL
VCC1
VCC2
1 : 2
TEST
75 Ω 1%
37.5 Ω 1%
12.4 kΩ
20 MHz
SYSTEM
CLOCK
82596
BACK-END/
CONTROLLER
INTERFACE
CLK0
RCLK
75 Ω 1%
37.5 Ω 1%
+5 V
Bias r esistor RBIAS should b e locat ed cl ose t o th e pin and isolated from other sig nal s.
2
1
10K
LINE STAT US
10K
PROGRAMMING
OPTIONS STP
CLK
TXD
RTS
TXC
RXC
RXD
CRS
CDT
LBK
CLK1
TXD
TEN
TCLK
RCLK
RXD
CD
COL
LBK
Left Open 2
Optiona l: Centertap capa citor ma y improve EMC depe ndin g on boa rd la y out a nd system design.
1
LI
Link Test Enable
RJAB
RLD
RCMPT
REMOTE
STATUS
Universal 10BASE -T and AUI Trans cei vers — LXT901 /907
Datasheet 31
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
4.0 Test Specifications
Note: Table 6 thr oug h Table 15 and Figur e 1 7 th ro ugh Figu re 42 rep resent th e p erforma nce specif ication s
of the LXT901/907. These specificat ions are guaranteed by test except where noted “by design.”
Minimum and maximum va lue s list e d in Table 8 through Table 15 app ly ov er th e recommended
oper ating conditions specified in Table 7.
For all Quality and Reliability issues (for example, parts packaging and t hermal specif ications),
pleas e send your ques tions to Intel at the following e-m a il address: qr.requests@intel.com.
Table 6. Absolute Maximum Ratings
Parameter Symbol Min Max Units
Supply voltage VCC -0.3 6 V
Storage temperature TSTG -65 +150 ºC
Caution: Exceeding these values may cause permanent damage. Functional operation under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may affect
device reliability.
Table 7. Recommended Operating Conditions
Parameter Symbol Min Typ Max Units
Recommended supply voltage1VCC 4.75 5.0 5.25 V
Recommended operating temperature TOP 0–70 ºC
1. Voltages with respect to ground unless otherwise specified. Power supply should be filtered to suppress
high frequency transients, consistent with good PCB design.
Tabl e 8. I/O Electrical Characteri stics
Parameter Sym Min Typ1Max Units Test Conditions
Input low
voltage2VIL ––0.8 V –
Input high
voltage2VIH 2.0 ––V–
Output low voltage VOL ––0.4 V IOL = 1.6 mA
VOL ––10 %VCC IOL < 10 µA
Output low
voltage
(Open drain LE D
driver)
VOLL ––0.7 %VCC IOLL = 10 mA
Output high voltage VOH 2.4 ––VIOH = 40 µA
VOH 90 ––%VCC IOH < 10 µA
1. Typical values are at 25°C and are for design aid only, are not guaranteed, and are not subject to
production testing.
2. Limited functional tests are performed at these input levels. The majority of functional tests are performed
at levels of 0V and 3V.
LXT901/907 — Un iversal 10BASE-T and AU I Tra nsceivers
32 Datasheet
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
Output rise time
TCLK & RCLK CMOS ––312nsC
LOAD = 20 pF
TTL ––28ns –
Output fall time
TCLK & RCLK CMOS ––312nsC
LOAD= 20 pF
TTL ––28ns –
CLKI rise time (externally driven) –––10 ns –
CLKI duty cycle (exter nally driven) ––50/50 40/60 % –
Supply current Normal Mode
ICC –65 85 mA Idle Mode
ICC –90 110 mA Transmitting on
twisted-pair
ICC –70 90 mA Transmitting on
AUI
Power-Down
Mode ICC –0.75 2 mA –
Table 9. AUI Electrical Characteristics
Parameter Symbol Min Typ1Ma x Units Test C onditions
Input Low current IIL ––-700 µA–
Input High curr ent IIH ––500 µA–
Differential output voltage VOD ±550 –±1200 mV –
Differential squelch threshold VDS 150 250 350 mV 5 MHz square wave
input
1. Typical values are at 25°C and are for design aid only, are not guaranteed, and are not subject to
production testing.
Tabl e 10 . Twis ted-Pai r El ectr i c al Ch arac teri s tics
Parameter Symbol Min Typ1Max Units Test Conditions
Transmit output impedance ZOUT –5– Ω–
Transmit timing jitter addition ––±3.3 ±10 ns 0 line length for internal
MAU
Transmit timing jitter added by
the MAU and PLS sections ––±3.3 ±5.5 ns After line model
specified by IEEE 802.3
for 10BASE-T internal
MAU
1. Typical values are at 25°C and are for design aid only, are not guaranteed, and are not subject to
production testing.
Table 8. I/O Electrical Characteristics (Continu ed )
Parameter Sym Min Typ1Max Units Test Conditions
1. Typical values are at 25°C and are for design aid only, are not guaranteed, and are not subject to
production testing.
2. Limited functional tests are performed at these input levels. The majority of functional tests are performed
at levels of 0V and 3V.
Universal 10BASE -T and AUI Trans cei vers — LXT901 /907
Datasheet 33
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
Receive input impedance ZIN –20 –kΩBetween TPIP/TPIN,
CIP/CIN & DIP/DIN
Differential
Squelch
Threshold
Normal
Threshold;
NT H =
High VDS 300 400 585 mV 5 MHz square wave
input
Reduced
Threshold;
NT H =
Low VDS 180 250 345 mV 5 MHz square wave
input
Tabl e 11. Switching Chara cterist ics
Parameter Symbol Minimum Typical1Maximum Units
Jabber Timing Maximum transmit time –20 –150 ms
Unjab time –250 –750 ms
Link Integrity
Timing
Time link loss receive –50 –150 ms
Link min receive –2–7ms
Link max receive –50 –150 ms
Link transmit period –81024ms
1. Typical values are at 25°C and are for design aid only, are not guaranteed, and are not subject to
production testing.
Table 12. RCLK/Start-of-Frame Timing
Parameter Symbol Minimum Typical1Maximum Units
Decoder acquisition time AUI tDATA –900 1100 ns
Twisted-Pair tDATA –1200 1500 ns
CD turn-on delay AUI tCD –25 200 ns
Twisted-Pair tCD –425 550 ns
Receive data setup from
RCLK Mode 1 tRDS 60 70 –ns
Modes 2, 3 and 4 tRDS 30 45 –ns
Receive data hold from
RCLK Mode 1 tRDH 10 20 –ns
Modes 2, 3 and 4 tRDH 30 45 –ns
RCLK shut off delay from CD assert
(LXT907 only; Mode 3) tsws –±90 –ns
1. Typical values are at 25°C and are for design aid only, are not guaranteed, and are not subject to
production testing.
Table 10. Twisted-P ai r E lectrical Charac teristics (Continued)
Parameter Symbol Min Typ1Max Units Test Conditions
1. Typical values are at 25°C and are for design aid only, are not guaranteed, and are not subject to
production testing.
LXT901/907 — Un iversal 10BASE-T and AU I Tra nsceivers
34 Datasheet
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
Table 13. RCLK/End-of-Frame Timing
Parameter Type Sym Mode 1 Mode 2 Mode 3 Mode 4 Units
RCLK after CD off Min tRC 51275bt
Rcv data throughput delay Max tRD 400 375 375 375 ns
CD turn off delay2Max tCDOFF 500 475 475 475 ns
Receive block out after TEN off Typ1tIFG 550––bt
RCLK switching delay after CD
off (LXT907 only; Mode 3) Typ1tSWE ––120(±80) –ns
1. Typical values are at 25° C and are for design aid only, are not guaranteed, and are not subject to
production testing.
2. CD turn- of f dela y meas ured fr om mi ddle of last bit: tim ing sp ecific ation i s unaf fec t ed by the val ue of the last
bit.
Tabl e 14. Tra n sm it Timing
Parameter Symbol Minimum Typical1Maximum Units
TEN setup from TCLK tEHCH 22 ––ns
TXD setup from TCLK tDSCH 22 ––ns
TEN hold after TCLK tCHEL 5––ns
TXD hold after TCLK tCHDU 5––ns
Transmit start-up delay - AUI tSTUD –220 450 ns
Transmit start-up delay -
Twisted-Pair tSTUD –430 450 ns
Transmit through-put delay -
AUI tTPD ––300 ns
Transmit through-put delay -
Twisted-Pair tTPD –300 350 ns
1. Typical values are at 25° C and are for design aid only, are not guaranteed, and are not subject to
production testing.
Table 15. Collision, COL/CI Output and Loopback Timi ng
Parameter Symbol Minimum Typical1Maximum Units
COL turn-on delay tCOLD –40 500 ns
COL turn-off delay tCOLOFF –420 500 ns
COL (SQE) Delay after TEN off tSQED 0.65 1.2 1.6 µs
COL (SQE) Pulse Duration tSQEP 500 1000 1500 ns
LBK setup from TEN tKHEH 10 25 –ns
LBK hold after TEN tKHEL 10 0 –ns
1. Typical values are at 25° C and are for design aid only, are not guaranteed, and are not subject to
production testing.
Universal 10BASE -T and AUI Trans cei vers — LXT901 /907
Datasheet 35
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
4.1 Timing Diagrams for Mode 1 (MD1 = Low, MD0 = Low)
Figures 17 - 22
Figure 17. Mode 1 RCLK/St a rt-of-Frame Timing
Figure 18. Mode 1 RCLK/ End -of -Frame Timing
11 0 1 0 1 0 1 0 1 1
1 0 1 0 1 0 1 1 1 01 0 1
tCD
tDATA
TPIP/TPIN
or DIP/DIN
CD
RCLK
RXD
tRDS tRDH
0 1 0 0 0 1 0 1 0
101010100
1 01 0 1 0 1 00
t
RD
t
CDOFF
TPIP/TPIN
or DIP/DIN
CD
RCLK
RXD
t
RC
LXT901/907 — Un iversal 10BASE-T and AU I Tra nsceivers
36 Datasheet
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
Figure 19. Mode 1 Transmit Timing
Figure 20. Mode 1 Collisio n Detec t Timing
Figure 21. Mode 1 COL/CI Output Timing
Figure 22. Mode 1 Loopback Timing
tCHEL
tEHCH
tCHDU
TEN
TCLK
TXD
TPO
tTPD
tDSCH
tSTUD
t
COLOFF
t
COLD
CI
COL
tSQEP
tSQED
TEN
COL
tKHEL
tKHEH
LBK
TEN
Universal 10BASE -T and AUI Trans cei vers — LXT901 /907
Datasheet 37
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
4.2 Timing Diagrams for Mode 2 (MD1=Low, MD0=High)
Figures 23 - 28
Figure 23. Mode 2 RCLK/St a rt-of-Frame Timing
Figure 24. Mode 2 RCLK/ End -of -Frame Timing
1 0 1 0 1 0 1 1 1 01 0 1
tCD
tRDS tRDH
CD
RCLK
RXD
tDATA
TPIP/TPIN
o r DI P /DIN
11 0 1 0 1 0 1 0 1 1 0 1 0 0 0 1 0 1 0
NOTE:
1. RXD changes at the rising edge of RCLK. The controller is sampled at the falling edge.
1 0 1 0 1 0 1 0 0
tRD
TPIP/TPIN
or DIP/DIN
CD
RCLK
RXD
1 01 0 1 0 1 00
tCDOFF
NOTE:
1. RXD changes at the rising edge of RCLK. The controller is sampled at the falling edge.
LXT901/907 — Un iversal 10BASE-T and AU I Tra nsceivers
38 Datasheet
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
Figure 25. Mode 2 Transmit Timing
Figure 26. Mode 2 Collisio n Detec t Timing
Figure 27. Mode 2 COL/CI Output Timing
Figure 28. Mode 2 Loopback Timing
tCHEL
tEHCH
tCHDU
TEN
TCLK
TXD
TPO
tDSCH
tTPDtSTUD
tCOLOFFtCOLD
CI
COL
tSQED
TEN
COL
tIFG
tSQEP
tKHELtKHEH
LBK
TEN
Universal 10BASE -T and AUI Trans cei vers — LXT901 /907
Datasheet 39
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
4.3 Timing Diagrams for Mode 3 (MD1 = High, MD0 = Low)
Figures 29 - 36
Figure 29. Mode 3 RCLK/St a rt-of-Frame Timing (LXT901 only)
Figure 30. Mode 3 RCLK/ End -of -Frame Timing (LXT901 only)
1 0 1 0 1 0 1 1 1 01 0 1
tRDS tRDH
tDATA
CD
RCLK
RXD
TPIP/TPIN
or DIP/DIN
11 0 1 0 1 0 1 0 1 1 0 1 0 0 0 1 0 1
tCD
NOTE:
1. RXD changes at the rising edge of RCLK. The controller is sampled at the falling edge.
tRD
tCDOFF
CD
RCLK
RXD
101010100
TPIP/TPIN
or DIP/ D IN
1 01 0 1 0 1 00
27 bits
NOTE:
1. RXD changes at the rising edge of RCLK. The controller is sampled at the falling edge.
LXT901/907 — Un iversal 10BASE-T and AU I Tra nsceivers
40 Datasheet
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
Figure 31. Mode 3 RCL K/Sta rt-of-Frame Tim ing (LX T 907 only)
Figure 32. Mode 3 RCLK/End-of-Frame Timing (LXT907 only)
1010101110101
tRDS tRDH
tDATA
CD
RCLK
RXD
TPIP/TPIN
or DIP/DIN
11 0 1 0 1 0 1 0 1 1 0 1 0 0 0 1 0 1
tCD
tSWS Recovered from Input Data Stream
Generated from TCLK
NOTE:
1. R XD changes at the rising edge of RCLK. The controller is sampled at the falling edge.
tRD
tCDOFF
CD
RCLK
RXD
tSWE
Recov ered Clock Generated from TCLK
1 0 1 0 1 0 1 0 0
TPIP/TPIN
or DIP/DIN
1 01 0 1 0 1 00
NOTE:
1. RXD changes at the rising edge of RCLK. The controller is sampled at the falling edge.
Universal 10BASE -T and AUI Trans cei vers — LXT901 /907
Datasheet 41
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
Figure 33. Mode 3 Transmit Timing
Figure 34. Mode 3 Collision Dete ct Timing
Figure 35. Mode 3 COL/CI Output Tim ing
Figure 36. Mode 3 Loopback Timing
tCHEL
tEHCH
tCHDU
TEN
TCLK
TXD
TPO
tSTUD
tDSCH
tTPD
tCOLOFF
tCOLD
CI
COL
tSQED
TEN
COL
tSQEP
NOTE:
1. RXD changes at the rising edge of RCLK. The controller is sampled at the falling edge.
tKHEL
tKHEH
LBK
TEN
LXT901/907 — Un iversal 10BASE-T and AU I Tra nsceivers
42 Datasheet
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
4.4 Timing Diagrams for Mode 4 (MD1 = High, MD0 = High)
Figur es 37 - 42
Figure 37. Mode 4 RCLK/Start-of-Fram e Timing
Figure 38. Mode 4 RCLK/End-of-Frame Timing
1 0 1 0 1 0 1 1 1 01 0 1
t
CD
t
DATA
CD
RCLK
RXD
TPIP/TPIN
or DIP/DIN
t
RDS
t
RDH
11 0 1 0 1 0 1 0 1 1 0 1 0 0 0 1 0 1
NOTE:
1. RXD changes at the rising edge of RCLK. The controller is sampled at the falling edge.
101010100
1 01 0 1 0 1 00
t
RD
TPIP/TPIN
or DIP/DIN
CD
RCLK
RXD
t
CDOFF
NOTE:
1. RXD changes at the rising edge of RCLK. The controller is sampled at the falling edge.
Universal 10BASE -T and AUI Trans cei vers — LXT901 /907
Datasheet 43
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
Figure 39. Mode 4 Transmit Timing
Figure 40. Mode 4 Collision Dete ct Timing
Figure 41. Mode 4 COL/CI Output Tim ing
Figure 42. Mode 4 Loopback Timing
tCHEL
tEHCH
tCHDU
TEN
TCLK
TXD
TPO
tDSCH
tSTUD tTPD
t
COLOFF
t
COLD
CI
COL
tSQEP
tSQED
TEN
COL
tKHEL
tKHEH
LBK
TEN
LXT901/907 — Un iversal 10BASE-T and AU I Tra nsceivers
44 Datasheet
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
5.0 Mechanical Specifications
Figu re 43. L X T 901/907 Packag e Specificati o n s
Dim Inches Millimeters
Min Max Min Max
A 0.165 0.180 4.191 4.572
A10.090 0.120 2.286 3.048
A20.062 0.083 1.575 2.108
B 0.050 –1.270 –
C 0.026 0.032 0.660 0.813
D 0.685 0.695 17.399 17.653
D10.650 0.656 16.510 16.662
F 0.013 0.021 0.330 0.533
44-Pin PLCC
•Part Number LXT901PC and LXT907PC
•Commercial Tem p Range (0oC to 70oC)
64-Pin LQFP
•Part Number LXT901LC
•Commercial Temp Range (0oC to 70oC)
Dim Inches Millimeters
Min Max Min Max
A–0.063 –1.60
A1 0.002 0.006 0.05 0.15
A2 0.053 0.057 1.35 1.45
B 0.007 .011 0.17 0.27
D 0.472 BSC 12.00 BSC
D1 0.394 BSC 10.00 BSC
E 0.472 BS C 12.00 BSC
E1 0.394 BSC 10.00 BSC
e 0.020 BSC 0.50 BSC
L 0.018 0.030 0.45 0.75
L1 0.039 REF 1.00 REF
θ311
o13o11o13o
θ0o7o0o7o
A
2
A
D
F
A
1
C
B
D
1
D
C
L
D
D
1
for sides with
even
number of pins
e
/
2
for sides with odd
number of pins
e
A
1
A
2
L
A
B
L
1
θ
3
θ
3
θ
E
E
1
Universal 10BASE -T and AUI Trans cei vers — LXT901/907
Datasheet 45
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
Appendix A Ordering Info rmatio n
Table 16. P roduct Inform at io n
Number Revision Qualification Tray MM Tape & Reel MM
DJLXT901LC.E2 E2 S 831686 831803
NLXT901PC.E2 E2 S 831657 831813
NLXT907PC.E2 E2 S 831666 831822
Figure 44. Ordering Information - Sample
Temperature Range
A
C
E
= Ambient (0 - 55° C)
= Com me rcial (0 - 70° C)
= Exte nded (- 40 - +85° C)
Product Revision
xn = 2 Alphan um eric chara cter s
Buil d F ormat
E000
E001 = Tr ay
= Tape and reel
DJ SE2CL901
LXT E001
Internal Pac kage Desi gnator
L
P
N
Q
H
T
B
E
K
= LQFP
= PLCC
= DIP
= PQFP
= QFP with heat sprea der
= TQFP
= BGA
= TBGA
= HSBGA (BG A with heat slug )
Qualification
Q
S= Pre-produ ctio n mater ial
= Production material
IXA Product Prefix
LXT
IXE
IXF
IXP
= PHY la yer device
= Switching engine
= Formatting dev ice ( M AC )
= Network processor
Intel Package Designator
DJ
FA
FL
FW
HB
HD
HG
S
GC
N
= LQFP
= TQFP
= PBGA (<1 .0 mm pitch)
= P BGA ( 1.2 7 mm pit ch)
= QFP with heat sprea der
= QFP with heat slug
= SOIC
= QFP
= TBGA
= PLCC
xxxx = 3-5 Digit Al phanumeric Product Code
