December 2008 Rev 4 1/60
1
M25PX80
Features
SPI bus compatible serial interface
75 MHz (maximum) clock frequency
2.3 V to 3.6 V single supply voltage
Dual input/output instructions resulting in an
equivalent clock frequency of 150 MHz:
– Dual Output Fast Read instruction
– Dual Input Fast Program instruction
8 Mbit Flash memory
– Uniform 4-Kbyte subsectors
– Uniform 64-Kbyte sectors
Additional 64-byte user-lockable, one-time
programmable (OTP) area
Erase capability
– Subsector (4-Kbyte) granularity
– Sector (64-Kbyte) granularity
– Bulk Erase (8 Mbit) in 8 s (typical)
Write protections
– Software write protection applicable to
every 64-Kbyte sector (volatile lock bit)
– Hardware write protection: protected area
size defined by three non-volatile bits (BP0,
BP1 and BP2)
Deep Power-down mode: 5 μA (typical)
Electronic signature
– JEDEC standard two-byte signature
(7114h)
– Unique ID code (UID) with16 bytes read-
only, available upon customer request
More than 100 000 write cycles per sector
More than 20 year data retention
Packages
– RoHS compliant
VFQFPN8 (MP)
6 × 5 mm
SO8W (MW)
208 mils
SO8N (MN)
150 mils
PDIP8 (BA)
300 mils width
www.Numonyx.com
8-Mbit, dual I/O, 4-Kbyte subsector erase,
serial Flash memory with 75 MHz SPI bus interface
Contents M25PX80
2/60
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 Serial Data output (DQ1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 Serial Data input (DQ0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.5 Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.6 Write Protect/Enhanced Program supply voltage (W/VPP) . . . . . . . . . . . . . 8
2.7 VCC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.8 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3 SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4 Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1 Page programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2 Dual Input Fast Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3 Subsector Erase, Sector Erase and Bulk Erase . . . . . . . . . . . . . . . . . . . . 12
4.4 Polling during a Write, Program or Erase cycle . . . . . . . . . . . . . . . . . . . . 12
4.5 Active Power, Standby Power and Deep Power-down modes . . . . . . . . . 13
4.6 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.7 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.7.1 Protocol-related protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.7.2 Specific hardware and software protection . . . . . . . . . . . . . . . . . . . . . . 14
4.8 Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.1 Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.2 Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.3 Read Identification (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
M25PX80 Contents
3/60
6.4 Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.4.1 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.4.2 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.4.3 BP2, BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.4.4 TB bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.4.5 SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.5 Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.6 Read Data Bytes (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.7 Read Data Bytes at higher speed (FAST_READ) . . . . . . . . . . . . . . . . . . 28
6.8 Dual Output Fast Read (DOFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.9 Read Lock Register (RDLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.10 Read OTP (ROTP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.11 Page Program (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.12 Dual Input Fast Program (DIFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.13 Program OTP instruction (POTP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.14 Write to Lock Register (WRLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.15 Subsector Erase (SSE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.16 Sector Erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.17 Bulk Erase (BE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.18 Deep Power-down (DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6.19 Release from Deep Power-down (RDP) . . . . . . . . . . . . . . . . . . . . . . . . . 41
7 Power-up and power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
10 DC and AC p arameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
11 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
12 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
List of tables M25PX80
4/60
List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2. Software protection truth table (Sectors 0 to 63, 64 Kbyte granularity) . . . . . . . . . . . . . . . 15
Table 3. Protected area sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 4. Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 5. Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 6. Read Identification (RDID) data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 7. Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 8. Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 9. Lock Register out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 10. Lock Register in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 11. Power-up timing and VWI threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 12. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 13. Operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 14. AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 15. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 16. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 17. AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 18. AC characteristics (50 MHz operation). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 19. VFQFPN8 (MLP8) 8-lead very thin fine pitch dual flat package no lead,
6 × 5 mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 20. SO8W 8-lead plastic small outline, 208 mils body width, package
mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 21. SO8N – 8 lead plastic small outline, 150 mils body width, package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 22. PDIP8 – 8 lead Plastic Small Outline, 300 mils body width, package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 23. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 24. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
M25PX80 List of figures
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List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 2. VFQFPN, SO8, and PDIP8 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. Bus Master and memory devices on the SPI bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 4. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 5. Hold condition activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 6. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 7. Write Enable (WREN) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 8. Write Disable (WRDI) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 9. Read Identification (RDID) instruction sequence and data-out sequence . . . . . . . . . . . . . 23
Figure 10. Read Status Register (RDSR) instruction sequence and data-out sequence . . . . . . . . . . 25
Figure 11. Write Status Register (WRSR) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 12. Read Data Bytes (READ) instruction sequence and data-out sequence . . . . . . . . . . . . . . 28
Figure 13. Read Data Bytes at higher speed (FAST_READ) instruction sequence
and data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 14. Dual Output Fast Read instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 15. Read Lock Register (RDLR) instruction sequence and data-out sequence . . . . . . . . . . . . 31
Figure 16. Read OTP (ROTP) instruction and data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 17. Page Program (PP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 18. Dual Input Fast Program (DIFP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 19. Program OTP (POTP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 20. How to permanently lock the 64 OTP bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 21. Write to Lock Register (WRLR) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 22. Subsector Erase (SSE) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 23. Sector Erase (SE) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 24. Bulk Erase (BE) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 25. Deep Power-down (DP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 26. Release from Deep Power-down (RDP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . 42
Figure 27. Power-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 28. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 29. Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 30. Write Protect Setup and Hold timing during WRSR when SRWD=1 . . . . . . . . . . . . . . . . . 51
Figure 31. Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 32. Output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 33. VPPH timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 34. VFQFPN8 (MLP8) 8-lead very thin fine pitch dual flat package no lead,
6 × 5 mm, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 35. SO8W 8-lead plastic small outline, 208 mils body width, package outline . . . . . . . . . . . . . 56
Figure 36. SO8N – 8 lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 57
Figure 37. PDIP8 – 8 lead Plastic Small Outline, 300 mils body width, package outline. . . . . . . . . . . 58
Description M25PX80
6/60
1 Description
The M25PX80 is a 8 Mbit (1 Mb x 8) serial Flash memory, with advanced write protection
mechanisms, accessed by a high speed SPI-compatible bus.
The M25PX80 supports two new, high-performance dual input/output instructions:
Dual Output Fast Read (DOFR) instruction used to read data at up to 75 MHz(1) by
using both pin DQ1 and pin DQ0 as outputs
Dual Input Fast Program (DIFP) instruction used to program data at up to 75 MHz(1) by
using both pin DQ1 and pin DQ0 as inputs
These new instructions double the transfer bandwidth for read and program operations.
The memory can be programmed 1 to 256 bytes at a time, using the Page Program
instruction.
The memory is organized as 16 sectors that are further divided into 16 subsectors each
(256 subsectors in total).
The memory can be erased a 4-Kbyte subsector at a time, a 64-Kbyte sector at a time, or as
a whole. It can be Write Protected by software using a mix of volatile and non-volatile
protection features, depending on the application needs. The protection granularity is of 64
Kbytes (sector granularity).
The M25PX80 has 64 one-time-programmable bytes (OTP bytes) that can be read and
programmed using two dedicated instructions, Read OTP (ROTP) and Program OTP
(POTP), respectively. These 64 bytes can be permanently locked by a particular Program
OTP (POTP) sequence. Once they have been locked, they become read-only and this state
cannot be reverted.
Further features are available as additional security options. More information on these
security features is available, upon completion of an NDA (nondisclosure agreement), and
are, therefore, not described in this datasheet. For more details of this option contact your
nearest Numonyx Sales office.
1. 75 MHz operation is available only in VCC range 2.7 V - 3.6 V.
M25PX80 Description
7/60
Figure 1. Logic diagram
Figure 2. VFQFPN, SO8, and PDIP8 connections
1. There is an exposed central pad on the underside of the VFQFPN package. This is pulled, internally, to
VSS, and must not be allowed to be connected to any other voltage or signal line on the PCB.
2. See Package mechanical section for package dimensions, and how to identify pin-1.
Table 1. Signal nam es
Signal name Function Direction
C Serial Clock Input
DQ0 Serial Data input I/O(1)
1. Serves as an output during Dual Output Fast Read (DOFR) instructions.
DQ1 Serial Data output I/O(2)
2. Serves as an input during Dual Input Fast Program (DIFP) instructions.
SChip Select Input
W/VPP Write Protect/Enhanced Program supply voltage Input
HOLD Hold Input
VCC Supply voltage
VSS Ground
AI14228
S
VCC
M25PX80
HOLD
VSS
DQ1
C
DQ0
W/V
PP
1
AI13720b
2
3
4
8
7
6
5DQ0VSS C
HOLDDQ1
SV
CC
M25PX80
W/VPP
Signal descriptions M25PX80
8/60
2 Signal descriptions
2.1 Serial Dat a output (DQ1)
This output signal is used to transfer data serially out of the device. Data are shifted out on
the falling edge of Serial Clock (C).
During the Dual Input Fast Program (DIFP) instruction, pin DQ1 is used as an input. It is
latched on the rising edge of the Serial Clock (C).
2.2 Serial Data input (DQ0)
This input signal is used to transfer data serially into the device. It receives instructions,
addresses, and the data to be programmed. Values are latched on the rising edge of Serial
Clock (C).
During the Dual Output Fast Read (DOFR) instruction, pin DQ0 is used as an output. Data
are shifted out on the falling edge of the Serial Clock (C).
2.3 Serial Clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data
present at Serial Data input (DQ0) are latched on the rising edge of Serial Clock (C). Data
on Serial Data output (DQ1) changes after the falling edge of Serial Clock (C).
2.4 Chip Select (S)
When this input signal is High, the device is deselected and Serial Data output (DQ1) is at
high impedance. Unless an internal Program, Erase or Write Status Register cycle is in
progress, the device will be in the Standby Power mode (this is not the Deep Power-down
mode). Driving Chip Select (S) Low enables the device, placing it in the Active Power mode.
After power-up, a falling edge on Chip Select (S) is required prior to the start of any
instruction.
2.5 Hold (HOLD)
The Hold (HOLD) signal is used to pause any serial communications with the device without
deselecting the device.
During the Hold condition, the Serial Data output (DQ1) is high impedance, and Serial Data
input (DQ0) and Serial Clock (C) are Don’t care.
To start the Hold condition, the device must be selected, with Chip Select (S) driven Low.
2.6 Write Protect/Enhanced Program supply voltage (W/VPP)
W/VPP is both a control input and a power supply pin. The two functions are selected by the
voltage range applied to the pin.
M25PX80 Signal descript ion s
9/60
If the W/VPP input is kept in a low voltage range (0 V to VCC) the pin is seen as a control
input. This input signal is used to freeze the size of the area of memory that is protected
against program or erase instructions (as specified by the values in the BP2, BP1 and BP0
bits of the Status Register. See Table 9).
If VPP is in the range of VPPH (as defined in Table 14) it acts as an additional power
supply.(2)
2.7 VCC supply voltage
VCC is the supply voltage.
2.8 VSS ground
VSS is the reference for the VCC supply voltage.
2. Avoid applying VPPH to the W/VPP pin during Bulk Erase.
SPI modes M25PX80
10/60
3 SPI modes
These devices can be driven by a microcontroller with its SPI peripheral running in either of
the two following modes:
CPOL=0, CPHA=0
CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).
The difference between the two modes, as shown in Figure 4, is the clock polarity when the
bus master is in Standby mode and not transferring data:
C remains at 0 for (CPOL=0, CPHA=0)
C remains at 1 for (CPOL=1, CPHA=1)
Figure 3. Bus Master and memory devices on the SPI bus
1. The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.
Figure 3 shows an example of three devices connected to an MCU, on an SPI bus. Only
one device is selected at a time, so only one device drives the Serial Data output (DQ1) line
at a time, the other devices are high impedance. Resistors R (represented in Figure 3)
ensure that the M25PX80 is not selected if the Bus Master leaves the S line in the high
impedance state. As the Bus Master may enter a state where all inputs/outputs are in high
impedance at the same time (for example, when the Bus Master is reset), the clock line (C)
must be connected to an external pull-down resistor so that, when all inputs/outputs become
high impedance, the S line is pulled High while the C line is pulled Low (thus ensuring that S
and C do not become High at the same time, and so, that the tSHCH requirement is met).
The typical value of R is 100 kΩ, assuming that the time constant R*Cp (Cp = parasitic
capacitance of the bus line) is shorter than the time during which the Bus Master leaves the
SPI bus in high impedance.
AI13725b
SPI Bus Master
SPI memory
device
SDO
SDI
SCK
C
DQ1DQ0
S
SPI memory
device
C
DQ1 DQ0
S
SPI memory
device
C
DQ1DQ0
S
CS3 CS2 CS1
SPI interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
WHOLD HOLD WHOLD
RRR
VCC
VCC VCC VCC
VSS
VSS VSS VSS
R
W
M25PX80 SPI modes
11/60
Example: Cp = 50 pF, that is R*Cp = 5 μs <=> the application must ensure that the Bus
Master never leaves the SPI bus in the high impedance state for a time period shorter than
5μs.
Figure 4. SPI modes supported
AI1373
0
C
MSB
CPHA
DQ0
0
1
CPOL
0
1
DQ1
C
MSB
Ope rating featu r es M25PX80
12/60
4 Operating features
4.1 Page programming
To program one data byte, two instructions are required: Write Enable (WREN), which is
one byte, and a Page Program (PP) sequence, which consists of four bytes plus data. This
is followed by the internal Program cycle (of duration tPP).
To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to be
programmed at a time (changing bits from 1 to 0), provided that they lie in consecutive
addresses on the same page of memory.
For optimized timings, it is recommended to use the Page Program (PP) instruction to
program all consecutive targeted bytes in a single sequence versus using several Page
Program (PP) sequences with each containing only a few bytes (see Page Program (PP)
and Table 17: A C char acteri sti cs).
4.2 Dual Input Fast Program
The Dual Input Fast Program (DIFP) instruction makes it possible to program up to 256
bytes using two input pins at the same time (by changing bits from 1 to 0).
For optimized timings, it is recommended to use the Dual Input Fast Program (DIFP)
instruction to program all consecutive targeted bytes in a single sequence rather to using
several Dual Input Fast Program (DIFP) sequences each containing only a few bytes (see
Section 6 .1 2: Du al Inpu t Fast Pr ogram (DIF P )).
4.3 Subsector Erase, Sector Erase and Bulk Erase
The Page Program (PP) instruction allows bits to be reset from 1 to 0. Before this can be
applied, the bytes of memory need to have been erased to all 1s (FFh). This can be
achieved either a subsector at a time, using the Subsector Erase (SSE) instruction, a sector
at a time, using the Sector Erase (SE) instruction, or throughout the entire memory, using
the Bulk Erase (BE) instruction. This starts an internal Erase cycle (of duration tSSE, tSE or
tBE).
The Erase instruction must be preceded by a Write Enable (WREN) instruction.
4.4 Polling during a Write, Program or Erase cycle
A further improvement in the time to Write Status Register (WRSR), Program OTP (POTP),
Program (PP), Dual Input Fast Program (DIFP) or Erase (SSE, SE or BE) can be achieved
by not waiting for the worst case delay (tW, tPP
, tSSE, tSE, or tBE). The Write In Progress
(WIP) bit is provided in the Status Register so that the application program can monitor its
value, polling it to establish when the previous Write cycle, Program cycle or Erase cycle is
complete.
M25PX80 O p er atin g fe at u res
13/60
4.5 Active Power, Standby Power and Deep Power-down modes
When Chip Select (S) is Low, the device is selected, and in the Active Power mode.
When Chip Select (S) is High, the device is deselected, but could remain in the Active
Power mode until all internal cycles have completed (Program, Erase, Write Status
Register). The device then goes in to the Standby Power mode. The device consumption
drops to ICC1.
The Deep Power-down mode is entered when the specific instruction (the Deep Power-
down (DP) instruction) is executed. The device consumption drops further to ICC2. The
device remains in this mode until another specific instruction (the Release from Deep
Power-down (RDP) instruction) is executed.
While in the Deep Power-down mode, the device ignores all Write, Program and Erase
instructions (see Deep Power-down (DP)), this can be used as an extra software protection
mechanism, when the device is not in active use, to protect the device from inadvertent
Write, Program or Erase instructions.
4.6 Status Register
The Status Register contains a number of status and control bits that can be read or set (as
appropriate) by specific instructions. See Section 6.4: Read Status Register (RDSR) for a
detailed description of the Status Register bits.
4.7 Protection modes
There are protocol-related and specific hardware and software protection modes. They are
described below.
Ope rating featu r es M25PX80
14/60
4.7.1 Protocol-related protections
The environments where non-volatile memory devices are used can be very noisy. No SPI
device can operate correctly in the presence of excessive noise. To help combat this, the
M25PX80 features the following data protection mechanisms:
Power On Reset and an internal timer (tPUW) can provide protection against
inadvertent changes while the power supply is outside the operating specification
Program, Erase and Write Status Register instructions are checked that they consist of
a number of clock pulses that is a multiple of eight, before they are accepted for
execution
All instructions that modify data must be preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state
by the following events:
– Power-up
– Write Disable (WRDI) instruction completion
– Write Status Register (WRSR) instruction completion
– Write to Lock Register (WRLR) instruction completion
– Program OTP (POTP) instruction completion
– Page Program (PP) instruction completion
– Dual Input Fast Program (DIFP) instruction completion
– Subsector Erase (SSE) instruction completion
– Sector Erase (SE) instruction completion
– Bulk Erase (BE) instruction completion
In addition to the low power consumption feature, the Deep Power-down mode offers
extra software protection, as all Write, Program and Erase instructions are ignored.
4.7.2 Specific hardware and sof tware protecti o n
There are two software protected modes, SPM1 and SPM2, that can be combined to protect
the memory array as required. The SPM2 can be locked by hardware with the help of the W
input pin.
SPM1 and SPM2
The first software protected mode (SPM1) is managed by specific Lock Registers
assigned to each 64 Kbyte sector.
The Lock Registers can be read and written using the Read Lock Register (RDLR) and
Write to Lock Register (WRLR) instructions.
In each Lock Register two bits control the protection of each sector: the Write Lock bit
and the Lock Down bit.
– Write Lock bit:
The Write Lock bit determines whether the contents of the sector can be modified
(using the Write, Program or Erase instructions). When the Write Lock bit is set to
‘1’, the sector is write protected – any operations that attempt to change the data
in the sector will fail. When the Write Lock bit is reset to ‘0’, the sector is not write
protected by the Lock Register, and may be modified.
– Lock Down bit:
The Lock Down bit provides a mechanism for protecting software data from simple
hacking and malicious attack. When the Lock Down bit is set, ‘1’, further
M25PX80 O p er atin g fe at u res
15/60
modification to the Write Lock and Lock Down bits cannot be performed. A power-
up, is required before changes to these bits can be made. When the Lock Down
bit is reset, ‘0’, the Write Lock and Lock Down bits can be changed.
The definition of the Lock Register bits is given in Table 9: Lock Register out.
the second software protected mode (SPM2) uses the Block Protect bits (see
Section 6. 4.3: BP2, BP1 , BP0 bits ) and the Top/Bottom bit (see Section 6.4.4: TB bit) to
allow part of the memory to be configured as read-only.
Table 2. So ftware pro tectio n truth table (Sectors 0 to 63, 64 Kbyt e g r anularity)
Sect or Lock
Register Protection status
Lock
Down bit Write
Lock bit
00
Sector unprotected from Program/Erase/Write operations, protection status
reversible
01
Sector protected from Program/Erase/Write operations, protection status
reversible
10
Sector unprotected from Program/Erase/Write operations,
Sector protection status cannot be changed except by a power-up.
11
Sector protected from Program/Erase/Write operations,
Sector protection status cannot be changed except by a Power-up.
Table 3. Pro tect ed area si z es
St atus Register
contents Memory content
TB
bit BP
bit 2 BP
bi t 1 BP
bit 0 Pr o t ec t ed ar ea Un pr o t ec t ed ar ea
0 0 0 0 none All sectors(1) (16 sectors: 0 to 15)
0 0 0 1 Upper 16th (Sector 15) Lower 15/16ths (15 sectors: 0 to 14)
0 0 1 0 Upper 8th (2 sectors: 14 and 15) Lower 7/8ths (14 sectors: 0 to 13)
0 0 1 1 Upper 4th (4 sectors: 12 to 15) Lower 3/4ths (12 sectors: 0 to 11)
0 1 0 0 Upper half (8 sectors: 8 to 15) Lower half (8 sectors: 0 to 7)
0 1 0 1 All sectors (16 sectors: 0 to 15) none
0 1 1 0 All sectors (16 sectors: 0 to 15) none
0 1 1 1 All sectors (16 sectors: 0 to 15) none
1 0 0 0 none All sectors(1) (16 sectors: 0 to 15)
1 0 0 1 Lower 16th (sector 0) Upper 15/16ths (15 sectors: 1 to 15)
1 0 1 0 Lower 8th (two sectors: 0 and 1) Upper 7/8ths (14 sectors: 2 to 15)
1 0 1 1 Lower 4th (four sectors: 0 to 3) Upper 3/4ths (12 sectors: 4 to 15)
1 1 0 0 Lower half (eight sectors: 0 to 7) Upper half (8 sectors: 8 to 15)
1 1 0 1 All sectors (16 sectors: 0 to 15) none
Ope rating featu r es M25PX80
16/60
As a second level of protection, the Write Protect signal (applied on the W/VPP pin) can
freeze the Status Register in a read-only mode. In this mode, the Block Protect bits (BP2,
BP1, BP0) and the Status Register Write Disable bit (SRWD) are protected. For more
details, see Secti on 6 .5: Writ e Stat u s Re gi ster (W RS R ).
4.8 Hold condition
The Hold (HOLD) signal is used to pause any serial communications with the device without
resetting the clocking sequence. However, taking this signal Low does not terminate any
Write Status Register, Program or Erase cycle that is currently in progress.
To enter the Hold condition, the device must be selected, with Chip Select (S) Low.
The Hold condition starts on the falling edge of the Hold (HOLD) signal, provided that this
coincides with Serial Clock (C) being Low (as shown in Figure 5).
The Hold condition ends on the rising edge of the Hold (HOLD) signal, provided that this
coincides with Serial Clock (C) being Low.
If the falling edge does not coincide with Serial Clock (C) being Low, the Hold condition
starts after Serial Clock (C) next goes Low. Similarly, if the rising edge does not coincide
with Serial Clock (C) being Low, the Hold condition ends after Serial Clock (C) next goes
Low. (This is shown in Figure 5).
During the Hold condition, the Serial Data output (DQ1) is high impedance, and Serial Data
input (DQ0) and Serial Clock (C) are Don’t care.
Normally, the device is kept selected, with Chip Select (S) driven Low, for the whole duration
of the Hold condition. This is to ensure that the state of the internal logic remains unchanged
from the moment of entering the Hold condition.
If Chip Select (S) goes High while the device is in the Hold condition, this has the effect of
resetting the internal logic of the device. To restart communication with the device, it is
necessary to drive Hold (HOLD) High, and then to drive Chip Select (S) Low. This prevents
the device from going back to the Hold condition.
1 1 1 0 All sectors (16 sectors: 0 to 15) none
1 1 1 1 All sectors (16 sectors: 0 to 15) none
1. The device is ready to accept a Bulk Erase instruction if, and only if, all Block Protect (BP2, BP1, BP0) are
0.
Table 3. Pro tect ed area si z es
St atus Register
contents Memory content
TB
bit BP
bit 2 BP
bi t 1 BP
bit 0 Pr o t ec t ed ar ea Un pr o t ec t ed ar ea
M25PX80 O p er atin g fe at u res
17/60
Figure 5. Hold conditi on activat ion
AI02029D
HOLD
C
Hold
Condition
(standard use)
Hold
Condition
(non-standard use)
Memory organization M25PX80
18/60
5 Memory organization
The memory is organized as:
1 048 576 bytes (8 bits each)
256 subsectors (4 Kbytes each)
16 sectors (64 Kbytes each)
4096 pages (256 bytes each)
64 OTP bytes located outside the main memory array
Each page can be individually programmed (bits are programmed from 1 to 0). The device is
Subsector, Sector or Bulk Erasable (bits are erased from 0 to 1) but not Page Erasable.
Figure 6. Block diagram
AI13722a
HOLD
S
W/VPP Control Logic High Voltage
Generator
I/O Shift Register
Address Register
and Counter
256 Byte
Data Buer
256 bytes (page size)
X Decoder
Y Decoder
C
DQ0
DQ1
Status
Register
00000h
0FFFFFh
000FFh
64 OTP bytes
M25PX80 Memory orga ni za tion
19/60
Table 4. Memory organization
Sector Subsector Address range Sector Subsector Address range
15
255 FF000h FFFFFh
5
95 5F000h 5FFFFh
...
...
...
...
...
...
240 F0000h F0FFFh 80 50000h 50FFFh
14
239 EF000h EFFFFh
4
79 4F000h 4FFFFh
...
...
...
...
...
...
224 E0000h E0FFFh 64 40000h 40FFFh
13
223 DF000h DFFFFh
3
63 3F000h 3FFFFh
...
...
...
...
...
...
208 D0000h D0FFFh 48 30000h 30FFFh
12
207 CF000h CFFFFh
2
47 2F000h 2FFFFh
...
...
...
...
...
...
192 C0000h C0FFFh 32 20000h 20FFFh
11
191 BF000h BFFFFh
1
31 1F000h 1FFFFh
...
...
...
...
...
...
176 B0000h B0FFFh 16 10000h 10FFFh
10
175 AF000h AFFFFh
0
15 0F000h 0FFFFh
...
...
...
160 A0000h A0FFFh 4 04000h 04FFFh
9
159 9F000h 9FFFFh 3 03000h 03FFFh
...
...
...
2 02000h 02FFFh
144 90000h 90FFFh 1 01000h 01FFFh
8
143 8F000h 8FFFFh 0 00000h 00FFFh
...
...
...
128 80000h 80FFFh
7
127 7F000h 7FFFFh
...
...
...
112 70000h 70FFFh
6
111 6F000h 6FFFFh
...
...
...
96 60000h 60FFFh
Instructions M25PX80
20/60
6 Instructions
All instructions, addresses and data are shifted in and out of the device, most significant bit
first.
Serial Data input(s) DQ0 (DQ1) is (are) sampled on the first rising edge of Serial Clock (C)
after Chip Select (S) is driven Low. Then, the one-byte instruction code must be shifted in to
the device, most significant bit first, on Serial Data input(s) DQ0 (DQ1), each bit being
latched on the rising edges of Serial Clock (C).
The instruction set is listed in Table 5.
Every instruction sequence starts with a one-byte instruction code. Depending on the
instruction, this might be followed by address bytes, or by data bytes, or by both or none.
In the case of a Read Data Bytes (READ), Read Data Bytes at higher speed (FAST_READ),
Dual Output Fast Read (DOFR), Read OTP (ROTP), Read Lock Registers (RDLR), Read
Status Register (RDSR), Read Identification (RDID) or Release from Deep Power-down
(RDP) instruction, the shifted-in instruction sequence is followed by a data-out sequence.
Chip Select (S) can be driven High after any bit of the data-out sequence is being shifted
out.
In the case of a Page Program (PP), Program OTP (POTP), Dual Input Fast Program
(DIFP), Subsector Erase (SSE), Sector Erase (SE), Bulk Erase (BE), Write Status Register
(WRSR), Write to Lock Register (WRLR), Write Enable (WREN), Write Disable (WRDI) or
Deep Power-down (DP) instruction, Chip Select (S) must be driven High exactly at a byte
boundary, otherwise the instruction is rejected, and is not executed. That is, Chip Select (S)
must driven High when the number of clock pulses after Chip Select (S) being driven Low is
an exact multiple of eight.
All attempts to access the memory array during a Write Status Register cycle, Program
cycle or Erase cycle are ignored, and the internal Write Status Register cycle, Program
cycle or Erase cycle continues unaffected.
Table 5. Instr u ction set (pag e 1 o f 2)
Instruction Description One-byte instruction
code Address
bytes Dummy
bytes Data
bytes
WREN Write Enable 0000 0110 06h 0 0 0
WRDI Write Disable 0000 0100 04h 0 0 0
RDID Read Identification
1001 1111 9Fh 0 0 1 to 20
1001 1110 9Eh 0 0 1 to 3
RDSR Read Status Register 0000 0101 05h 0 0 1 to ∞
WRSR Write Status Register 0000 0001 01h 0 0 1
WRLR Write to Lock Register 1110 0101 E5h 3 0 1
RDLR Read Lock Register 1110 1000 E8h 3 0 1
READ Read Data Bytes 0000 0011 03h 3 0 1 to ∞
FAST_READ Read Data Bytes at higher
speed 0000 1011 0Bh 3 1 1 to ∞
M25PX80 Instructions
21/60
6.1 Write Enable (WREN)
The Write Enable (WREN) instruction (Figure 7) sets the Write Enable Latch (WEL) bit.
The Write Enable Latch (WEL) bit must be set prior to every Page Program (PP), Dual Input
Fast Program (DIFP), Program OTP (POTP), Write to Lock Register (WRLR), Subsector
Erase (SSE), Sector Erase (SE), Bulk Erase (BE) and Write Status Register (WRSR)
instruction.
The Write Enable (WREN) instruction is entered by driving Chip Select (S) Low, sending the
instruction code, and then driving Chip Select (S) High.
Figu r e 7. Writ e E n ab l e (WR EN ) i n structio n seq uence
DOFR Dual Output Fast Read 0011 1011 3Bh 3 1 1 to ∞
ROTP Read OTP (Read 64 bytes of
OTP area) 0100 1011 4Bh 3 1 1 to 65
POTP Program OTP (Program 64
bytes of OTP area) 0100 0010 42h 3 0 1 to 65
PP Page Program 0000 0010 02h 3 0 1 to 256
DIFP Dual Input Fast Program 1010 0010 A2h 3 0 1 to 256
SSE Subsector Erase 0010 0000 20h 3 0 0
SE Sector Erase 1101 1000 D8h 3 0 0
BE Bulk Erase 1100 0111 C7h 0 0 0
DP Deep Power-down 1011 1001 B9h 0 0 0
RDP Release from Deep Power-
down 1010 1011 ABh 0 0 0
Table 5. Instr u ction set (pag e 2 o f 2)
Instruction Description One-byte instruction
code Address
bytes Dummy
bytes Data
bytes
C
DQ0
AI13731
S
DQ1
21 34567
High Impedance
0
Instruction
Instructions M25PX80
22/60
6.2 Write Disable (WRDI)
The Write Disable (WRDI) instruction (Figure 8) resets the Write Enable Latch (WEL) bit.
The Write Disable (WRDI) instruction is entered by driving Chip Select (S) Low, sending the
instruction code, and then driving Chip Select (S) High.
The Write Enable Latch (WEL) bit is reset under the following conditions:
Power-up
Write Disable (WRDI) instruction completion
Write Status Register (WRSR) instruction completion
Write lo Lock Register (WRLR) instruction completion
Page Program (PP) instruction completion
Dual Input Fast Program (DIFP) instruction completion
Program OTP (POTP) instruction completion
Subsector Erase (SSE) instruction completion
Sector Erase (SE) instruction completion
Bulk Erase (BE) instruction completion
Fig u re 8. Wr it e Disa b le (W RDI ) instructi o n sequenc e
6.3 Read Identification (RDID)
The Read Identification (RDID) instruction allows to read the device identification data:
Manufacturer identification (1 byte)
Device identification (2 bytes)
A Unique ID code (UID) (17 bytes, of which 16 available upon customer request).
The manufacturer identification is assigned by JEDEC, and has the value 20h for Numonyx.
The device identification is assigned by the device manufacturer, and indicates the memory
type in the first byte (71h), and the memory capacity of the device in the second byte (14h).
The UID contains the length of the following data in the first byte (set to 10h) and 16 bytes of
the optional Customized Factory Data (CFD) content. The CFD bytes are read-only and can
be programmed with customers data upon their demand. If the customers do not make
requests, the devices are shipped with all the CFD bytes programmed to zero (00h).
C
DQ0
AI13732
S
DQ1
21 34567
High Impedance
0
Instruction
M25PX80 Instructions
23/60
See Sec tion 12: Or dering info rm ation on page 59 for CFD programmed devices.
Any Read Identification (RDID) instruction while an Erase or Program cycle is in progress, is
not decoded, and has no effect on the cycle that is in progress.
The Read Identification (RDID) instruction should not be issued while the device is in Deep
Power-down mode.
The device is first selected by driving Chip Select (S) Low. Then, the 8-bit instruction code
for the instruction is shifted in. After this, the 24-bit device identification, stored in the
memory, the 8-bit CFD length followed by 16 bytes of CFD content will be shifted out on
Serial Data output (DQ1). Each bit is shifted out during the falling edge of Serial Clock (C).
The instruction sequence is shown in Figure 9.
The Read Identification (RDID) instruction is terminated by driving Chip Select (S) High at
any time during data output.
When Chip Select (S) is driven High, the device is put in the Standby Power mode. Once in
the Standby Power mode, the device waits to be selected, so that it can receive, decode and
execute instructions.
Figure 9. Read Identifi catio n (RDID ) instruction sequenc e and da ta-out se quenc e
6.4 Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows the Status Register to be read. The
Status Register may be read at any time, even while a Program, Erase or Write Status
Register cycle is in progress. When one of these cycles is in progress, it is recommended to
check the Write In Progress (WIP) bit before sending a new instruction to the device. It is
also possible to read the Status Register continuously, as shown in Figure 10.
Table 6. Read Identification (RDID) dat a-out sequence
Manufacturer id en tificati on Device identification UID
Memory type Memory capacity CFD l ength CFD content
20h 71h 14h 10h 16 bytes
C
DQ0
S
213456789101112131415
Instruction
0
AI06809d
DQ1
Manufacturer identification
High Impedance
MSB
Device identification
MSB
15 14 13 3 2 1 0
16 17 18 28 29 30 31
MSB
UID
Instructions M25PX80
24/60
The status and control bits of the Status Register are as follows:
6.4.1 WIP bit
The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status
Register, Program or Erase cycle. When set to 1, such a cycle is in progress, when reset to
0 no such cycle is in progress.
6.4.2 WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable
Latch is reset and no Write Status Register, Program or Erase instruction is accepted.
6.4.3 BP2, BP1, BP0 bits
The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size of the area to
be software protected against Program and Erase instructions. These bits are written with
the Write Status Register (WRSR) instruction. When one or more of the Block Protect (BP2,
BP1, BP0) bits is set to 1, the relevant memory area (as defined in Table 3) becomes
protected against Page Program (PP) and Sector Erase (SE) instructions. The Block Protect
(BP2, BP1, BP0) bits can be written provided that the Hardware Protected mode has not
been set. The Bulk Erase (BE) instruction is executed if, and only if, all Block Protect (BP2,
BP1, BP0) bits are 0.
6.4.4 TB bit
The Top/Bottom (TB) bit is non-volatile. It can be set and reset with the Write Status Register
(WRSR) instruction provided that the Write Enable (WREN) instruction has been issued.
The Top/Bottom (TB) bit is used in conjunction with the Block Protect (BP0, BP1, BP2) bits
to determine if the protected area defined by the Block Protect bits starts from the top or the
bottom of the memory array:
When TB is reset to ‘0’ (default value), the area protected by the Block Protect bits
starts from the top of the memory array (see Table 3: Protected area sizes)
When TB is set to ‘1’, the area protected by the Block Protect bits starts from the
bottom of the memory array (see Table 3: Protected area sizes)
The TB bit cannot be written when the SRWD bit is set to ‘1’ and the W pin is driven Low.
Table 7. Status Re g iste r fo rma t
b7 b0
SRWD 0 TB BP2 BP1 BP0 WEL WIP
Status Register Write Protect
Top/Bottom bit
Block Protect bits
Write Enable Latch bit
Write In Progress bit
M25PX80 Instructions
25/60
6.4.5 SRWD bit
The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write
Protect (W/VPP) signal. The Status Register Write Disable (SRWD) bit and the Write Protect
(W/VPP) signal allow the device to be put in the hardware protected mode (when the Status
Register Write Disable (SRWD) bit is set to ‘1’, and Write Protect (W/VPP) is driven Low). In
this mode, the non-volatile bits of the Status Register (SRWD, BP2, BP1, BP0) become
read-only bits and the Write Status Register (WRSR) instruction is no longer accepted for
execution.
Figure 10. Read Status Regist er (R D SR) inst ructi on sequence and data-out
sequence
6.5 Write Stat us Registe r (WRSR )
The Write Status Register (WRSR) instruction allows new values to be written to the Status
Register. Before it can be accepted, a Write Enable (WREN) instruction must previously
have been executed. After the Write Enable (WREN) instruction has been decoded and
executed, the device sets the Write Enable Latch (WEL).
The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) Low,
followed by the instruction code and the data byte on Serial Data input (DQ0).
The instruction sequence is shown in Figure 11.
The Write Status Register (WRSR) instruction has no effect on b6, b1 and b0 of the Status
Register. b6 is always read as ‘0’.
Chip Select (S) must be driven High after the eighth bit of the data byte has been latched in.
If not, the Write Status Register (WRSR) instruction is not executed. As soon as Chip Select
(S) is driven High, the self-timed Write Status Register cycle (whose duration is tW) is
initiated. While the Write Status Register cycle is in progress, the Status Register may still
be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP)
bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed.
When the cycle is completed, the Write Enable Latch (WEL) is reset.
The Write Status Register (WRSR) instruction allows the user to change the values of the
Block Protect (BP2, BP1, BP0) bits, to define the size of the area that is to be treated as
read-only, as defined in Table 3. The Write Status Register (WRSR) instruction also allows
the user to set and reset the Status Register Write Disable (SRWD) bit in accordance with
C
DQ0
S
21 3456789101112131415
Instruction
0
AI13734
DQ1 76543210
Status Register Out
High Impedance
MSB
76543210
Status Register Out
MSB
7
Instructions M25PX80
26/60
the Write Protect (W/VPP) signal. The Status Register Write Disable (SRWD) bit and Write
Protect (W/VPP) signal allow the device to be put in the hardware protected mode (HPM).
The Write Status Register (WRSR) instruction is not executed once the hardware protected
mode (HPM) is entered.
Figure 11. Write Status Regist er (W RSR) instruction seque nce
The protection features of the device are summarized in Table 8.
When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial
delivery state), it is possible to write to the Status Register provided that the Write Enable
Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless
of the whether Write Protect (W/VPP) is driven High or Low.
Table 8. Protection modes
W/VPP
signal SRWD
bit Mode Write Pro tection
of the St atus
Register
Memory content
Pr o t ec t ed ar ea (1)
1. As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in
Table 3.
Un pro t ec ted ar ea(1)
10
Software
protected
(SPM)
Status Register is
Writable (if the
WREN instruction
has set the WEL
bit)
The values in the
SRWD, BP2, BP1
and BP0 bits can be
changed
Protected against
Page Program,
Sector Erase and
Bulk Erase
Ready to accept
Page Program and
Sector Erase
instructions
00
11
01
Hardware
protected
(HPM)
Status Register is
hardware write
protected
The values in the
SRWD, BP2, BP1
and BP0 bits
cannot be changed
Protected against
Page Program,
Sector Erase and
Bulk Erase
Ready to accept
Page Program and
Sector Erase
instructions
C
DQ0
AI13735
S
DQ1
21 3456789101112131415
High Impedance
Instruction Status
Register In
0
765432 0
1
MSB
M25PX80 Instructions
27/60
When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two
cases need to be considered, depending on the state of Write Protect (W/VPP):
If Write Protect (W/VPP) is driven High, it is possible to write to the Status Register
provided that the Write Enable Latch (WEL) bit has previously been set by a Write
Enable (WREN) instruction.
If Write Protect (W/VPP) is driven Low, it is not possible to write to the Status Register
even if the Write Enable Latch (WEL) bit has previously been set by a Write Enable
(WREN) instruction. (Attempts to write to the Status Register are rejected, and are not
accepted for execution). As a consequence, all the data bytes in the memory area that
are software protected (SPM) by the Block Protect (BP2, BP1, BP0) bits of the Status
Register, are also hardware protected against data modification.
Regardless of the order of the two events, the Hardware Protected mode (HPM) can be
entered:
by setting the Status Register Write Disable (SRWD) bit after driving Write Protect
(W/VPP) Low
or by driving Write Protect (W/VPP) Low after setting the Status Register Write Disable
(SRWD) bit.
The only way to exit the Hardware Protected mode (HPM) once entered is to pull Write
Protect (W/VPP) High.
If Write Protect (W/VPP) is permanently tied High, the Hardware Protected mode (HPM) can
never be activated, and only the Software Protected mode (SPM), using the Block Protect
(BP2, BP1, BP0) bits of the Status Register, can be used.
6.6 Read Data Bytes (READ)
The device is first selected by driving Chip Select (S) Low. The instruction code for the Read
Data Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being
latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that
address, is shifted out on Serial Data output (DQ1), each bit being shifted out, at a
maximum frequency fR, during the falling edge of Serial Clock (C).
The instruction sequence is shown in Figure 12.
The first byte addressed can be at any location. The address is automatically incremented
to the next higher address after each byte of data is shifted out. The whole memory can,
therefore, be read with a single Read Data Bytes (READ) instruction. When the highest
address is reached, the address counter rolls over to 000000h, allowing the read sequence
to be continued indefinitely.
The Read Data Bytes (READ) instruction is terminated by driving Chip Select (S) High. Chip
Select (S) can be driven High at any time during data output. Any Read Data Bytes (READ)
instruction, while an Erase, Program or Write cycle is in progress, is rejected without having
any effects on the cycle that is in progress.
Instructions M25PX80
28/60
Fig u re 12. Read Data Byte s (RE AD) i nst ruct ion seque nce and data-out sequence
1. Address bits A23 to A22 are Don’t care.
6.7 Read Data Bytes at higher speed (FAST_READ)
The device is first selected by driving Chip Select (S) Low. The instruction code for the Read
Data Bytes at higher speed (FAST_READ) instruction is followed by a 3-byte address (A23-
A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C).
Then the memory contents, at that address, are shifted out on Serial Data output (DQ1) at a
maximum frequency fC, during the falling edge of Serial Clock (C).
The instruction sequence is shown in Figure 13.
The first byte addressed can be at any location. The address is automatically incremented
to the next higher address after each byte of data is shifted out. The whole memory can,
therefore, be read with a single Read Data Bytes at higher speed (FAST_READ) instruction.
When the highest address is reached, the address counter rolls over to 000000h, allowing
the read sequence to be continued indefinitely.
The Read Data Bytes at higher speed (FAST_READ) instruction is terminated by driving
Chip Select (S) High. Chip Select (S) can be driven High at any time during data output. Any
Read Data Bytes at higher speed (FAST_READ) instruction, while an Erase, Program or
Write cycle is in progress, is rejected without having any effects on the cycle that is in
progress.
C
DQ0
AI13736
S
DQ1
23
21 345678910 2829303132333435
2221 3210
36 37 38
76543 1 7
0
High Impedance Data Out 1
Instruction 24-bit address
0
MSB
MSB
2
39
Data Out 2
M25PX80 Instructions
29/60
Fig u re 13. Read Data Byte s at higher sp eed (FAST_ REA D) instruction sequenc e
and data-out sequence
1. Address bits A23 to A22 are Don’t care.
6.8 Dual Out put Fast Read (DOFR)
The Dual Output Fast Read (DOFR) instruction is very similar to the Read Data Bytes at
higher speed (FAST_READ) instruction, except that the data are shifted out on two pins (pin
DQ0 and pin DQ1) instead of only one. Outputting the data on two pins instead of one
doubles the data transfer bandwidth compared to the Read Data Bytes at higher speed
(FAST_READ) instruction.
The device is first selected by driving Chip Select (S) Low. The instruction code for the Dual
Output Fast Read instruction is followed by a 3-byte address (A23-A0) and a dummy byte,
each bit being latched-in during the rising edge of Serial Clock (C). Then the memory
contents, at that address, are shifted out on DQ0 and DQ1 at a maximum frequency fC,
during the falling edge of Serial Clock (C).
The instruction sequence is shown in Figure 14.
The first byte addressed can be at any location. The address is automatically incremented
to the next higher address after each byte of data is shifted out on DQ0 and DQ1. The whole
memory can, therefore, be read with a single Dual Output Fast Read (DOFR) instruction.
C
DQ0
AI13737
S
DQ1
23
21 345678910 28293031
2221 3210
High Impedance
Instruction 24-bit address
0
C
DQ0
S
DQ1
32 33 34 36 37 38 39 40 41 42 43 44 45 46
765432 0
1
DATA OUT 1
Dummy byte
MSB
76543210
DATA OUT 2
MSB MSB
7
47
765432 0
1
35
Instructions M25PX80
30/60
When the highest address is reached, the address counter rolls over to 00 0000h, so that
the read sequence can be continued indefinitely.
Figure 14. Dual Output Fast Read in stru ction sequence
1. A23 to A22 are Don't care.
6.9 Read Lock Register (RDLR)
The device is first selected by driving Chip Select (S) Low. The instruction code for the Read
Lock Register (RDLR) instruction is followed by a 3-byte address (A23-A0) pointing to any
location inside the concerned sector. Each address bit is latched-in during the rising edge of
Serial Clock (C). Then the value of the Lock Register is shifted out on Serial Data output
(DQ1), each bit being shifted out, at a maximum frequency fC, during the falling edge of
Serial Clock (C).
The instruction sequence is shown in Figure 15.
The Read Lock Register (RDLR) instruction is terminated by driving Chip Select (S) High at
any time during data output.
Any Read Lock Register (RDLR) instruction, while an Erase, Program or Write cycle is in
progress, is rejected without having any effects on the cycle that is in progress.
21 345678910 282930310
23 22 21 3 2 1 0
Mode 3
Mode 2
C
DQ0
S
DQ1 High Impedance
Instruction 24-bit address
C
DQ0
S
DQ1
32 33 34 36 37 38 39 40 41 42 43 44 45 46
753175 1
3
DATA OUT 1
Dummy byte
MSB
7531 7531
MSB MSB
47
6420 64 02
35
642064 02
MSB MSB
DATA OUT 2 DATA OUT 3 DATA OUT n
ai13574
M25PX80 Instructions
31/60
Figure 15. Read Lock Register (RDLR) inst ruct ion sequence and data-out sequence
6.10 Read OTP (ROTP )
The device is first selected by driving Chip Select (S) Low. The instruction code for the Read
OTP (ROTP) instruction is followed by a 3-byte address (A23- A0) and a dummy byte. Each
bit is latched in on the rising edge of Serial Clock (C).
Then the memory contents at that address are shifted out on Serial Data output (DQ1).
Each bit is shifted out at the maximum frequency, fCmax, on the falling edge of Serial Clock
(C). The instruction sequence is shown in Figure 16.
The address is automatically incremented to the next higher address after each byte of data
is shifted out.
There is no rollover mechanism with the Read OTP (ROTP) instruction. This means that the
Read OTP (ROTP) instruction must be sent with a maximum of 65 bytes to read, since once
the 65th byte has been read, the same (65th) byte keeps being read on the DQ1 pin.
The Read OTP (ROTP) instruction is terminated by driving Chip Select (S) High. Chip
Select (S) can be driven High at any time during data output. Any Read OTP (ROTP)
Table 9. Lock Register out (1)
1. Values of (b1, b0) after power-up are defined in Section 7: Power-up and power-down.
Bit Bit name Value Function
b7-b2 Reserved
b1 Sector Lock Down
‘1’
The Write Lock and Lock Down bits cannot be changed.
Once a ‘1’ is written to the Lock Down bit it cannot be cleared
to ‘0’, except by a power-up.
‘0’ The Write Lock and Lock Down bits can be changed by
writing new values to them.
b0 Sector Write Lock
‘1’ Write, Program and Erase operations in this sector will not be
executed. The memory contents will not be changed.
‘0’ Write, Program and Erase operations in this sector are
executed and will modify the sector contents.
C
D
Q0
AI13738
S
DQ1
23
21 345678910 2829303132333435
2221 3210
36 37 38
76543 10
High Impedance Lock Register Out
Instruction 24-bit address
0
MSB
MSB
2
39
Instructions M25PX80
32/60
instruction issued while an Erase, Program or Write cycle is in progress, is rejected without
having any effect on the cycle that is in progress.
Figure 16. Read OTP (ROTP) instruc tion and da ta-out sequence
1. A23 to A7 are Don't care.
2. 1 ≤ n ≤ 65.
6.11 Page Program (PP)
The Page Program (PP) instruction allows bytes to be programmed in the memory
(changing bits from 1 to 0). Before it can be accepted, a Write Enable (WREN) instruction
must previously have been executed. After the Write Enable (WREN) instruction has been
decoded, the device sets the Write Enable Latch (WEL).
The Page Program (PP) instruction is entered by driving Chip Select (S) Low, followed by
the instruction code, three address bytes and at least one data byte on Serial Data input
(DQ0). If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that
goes beyond the end of the current page are programmed from the start address of the
same page (from the address whose 8 least significant bits (A7-A0) are all zero). Chip
Select (S) must be driven Low for the entire duration of the sequence.
The instruction sequence is shown in Figure 17.
C
DQ0
AI13573
S
DQ1
23
21 345678910 28293031
2221 3210
High Impedance
Instruction 24-bit address
0
C
DQ0
S
DQ1
32 33 34 36 37 38 39 40 41 42 43 44 45 46
765432 0
1
DATA OUT 1
Dummy byte
MSB
76543210
DATA OUT n
MSB MSB
7
47
765432 0
1
35
M25PX80 Instructions
33/60
If more than 256 bytes are sent to the device, previously latched data are discarded and the
last 256 data bytes are guaranteed to be programmed correctly within the same page. If less
than 256 data bytes are sent to device, they are correctly programmed at the requested
addresses without having any effects on the other bytes of the same page.
For optimized timings, it is recommended to use the Page Program (PP) instruction to
program all consecutive targeted bytes in a single sequence versus using several Page
Program (PP) sequences with each containing only a few bytes (see Table 17: AC
characteristics).
Chip Select (S) must be driven High after the eighth bit of the last data byte has been
latched in, otherwise the Page Program (PP) instruction is not executed.
As soon as Chip Select (S) is driven High, the self-timed Page Program cycle (whose
duration is tPP) is initiated. While the Page Program cycle is in progress, the Status Register
may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress
(WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At
some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is
reset.
A Page Program (PP) instruction applied to a page which is protected by the Block Protect
(BP2, BP1, BP0) bits (see Table 3 and Table 4) is not executed.
Figure 17. Page Program (PP ) inst ruct ion s equence
1. Address bits A23 to A22 are Don’t care.
C
DQ0
AI13739
S
4241 43 44 45 46 47 48 49 50 52 53 54 5540
C
DQ0
S
23
21 345678910 2829303132333435
2221 3210
36 37 38
Instruction 24-bit address
0
765432 0
1
Data byte 1
39
51
765432 0
1
Data byte 2
765432 0
1
Data byte 3 Data byte 256
2079
2078
2077
2076
2075
2074
2073
765432 0
1
2072
MSB MSB
MSB MSB MSB
Instructions M25PX80
34/60
6.12 Dual Input Fast Program (DIFP)
The Dual Input Fast Program (DIFP) instruction is very similar to the Page Program (PP)
instruction, except that the data are entered on two pins (pin DQ0 and pin DQ1) instead of
only one. Inputting the data on two pins instead of one doubles the data transfer bandwidth
compared to the Page Program (PP) instruction.
The Dual Input Fast Program (DIFP) instruction is entered by driving Chip Select (S) Low,
followed by the instruction code, three address bytes and at least one data byte on Serial
Data input (DQ0).
If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes
beyond the end of the current page are programmed from the start address of the same
page (from the address whose 8 least significant bits (A7-A0) are all zero). Chip Select (S)
must be driven Low for the entire duration of the sequence.
The instruction sequence is shown in Figure 18.
If more than 256 bytes are sent to the device, previously latched data are discarded and the
last 256 data bytes are guaranteed to be programmed correctly within the same page. If less
than 256 data bytes are sent to device, they are correctly programmed at the requested
addresses without having any effects on the other bytes in the same page.
For optimized timings, it is recommended to use the Dual Input Fast Program (DIFP)
instruction to program all consecutive targeted bytes in a single sequence rather to using
several Dual Input Fast Program (DIFP) sequences each containing only a few bytes (see
Table 17: A C c harac teris tics ).
Chip Select (S) must be driven High after the eighth bit of the last data byte has been
latched in, otherwise the Dual Input Fast Program (DIFP) instruction is not executed.
As soon as Chip Select (S) is driven High, the self-timed Page Program cycle (whose
duration is tPP) is initiated. While the Dual Input Fast Program (DIFP) cycle is in progress,
the Status Register may be read to check the value of the Write In Progress (WIP) bit. The
Write In Progress (WIP) bit is 1 during the self-timed Page Program cycle, and 0 when it is
completed. At some unspecified time before the cycle is completed, the Write Enable Latch
(WEL) bit is reset.
A Dual Input Fast Program (DIFP) instruction applied to a page that is protected by the
Block Protect (BP2, BP1, BP0) bits (see Table 2 and Table 3) is not executed.
M25PX80 Instructions
35/60
Figure 18. Dual Input Fast Program (D IF P) instruction se quenc e
1. A23 to A22 are Don't care.
6.13 Program OTP instruction (POTP)
The Program OTP instruction (POTP) is used to program at most 64 bytes to the OTP
memory area (by changing bits from 1 to 0, only). Before it can be accepted, a Write Enable
(WREN) instruction must previously have been executed. After the Write Enable (WREN)
instruction has been decoded, the device sets the Write Enable Latch (WEL) bit.
The Program OTP instruction is entered by driving Chip Select (S) Low, followed by the
instruction opcode, three address bytes and at least one data byte on Serial Data input
(DQ0).
Chip Select (S) must be driven High after the eighth bit of the last data byte has been
latched in, otherwise the Program OTP instruction is not executed.
There is no rollover mechanism with the Program OTP (POTP) instruction. This means that
the Program OTP (POTP) instruction must be sent with a maximum of 65 bytes to program,
once all 65 bytes have been latched in, any following byte will be discarded.
The instruction sequence is shown in Figure 19.
As soon as Chip Select (S) is driven High, the self-timed Page Program cycle (whose
duration is tPP) is initiated. While the Program OTP cycle is in progress, the Status Register
C
DQ0
S
21 345678910 28293031
22 21 3 2 1 0
Instruction 24-bit address
0
C
DQ0
S
3433 35 36 37 38 39 40 41 42 44 45 46 4732 43
642064 0
2642064 0
26420
MSB MSB MSB
DQ1 High Impedance
6420
DQ1 7531 1753 753
75
MSB
31 1
MSB
7531 7531
MSB
DATA IN 1 DATA IN 4 DATA IN 5 DATA IN 256DATA IN 3DATA IN 2
23
Instructions M25PX80
36/60
may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress
(WIP) bit is 1 during the self-timed Program OTP cycle, and it is 0 when it is completed. At
some unspecified time before the cycle is complete, the Write Enable Latch (WEL) bit is
reset.
To lock the OTP memory:
Bit 0 of the OTP control byte, that is byte 64, (see Figure 20) is used to permanently lock the
OTP memory array.
When bits 3, 2, 1, and 0 of byte 64 = ’1’, the 64 bytes of the OTP memory array can be
programmed.
When bits 3, 2, 1, and 0 of byte 64 = ‘0’, the 64 bytes of the OTP memory array are
read-only and cannot be programmed anymore.
Once a bit of the OTP memory has been programmed to ‘0’, it can no longer be set to ‘1’.
Therefore, as soon as bit 0 of byte 64 (control byte) is set to ‘0’, the 64 bytes of the OTP
memory array become read-only in a permanent way.
Any Program OTP (POTP) instruction issued while an Erase, Program or Write cycle is in
progress is rejected without having any effect on the cycle that is in progress.
Figure 19. Program OT P (PO TP) i nst ruct ion sequence
1. A23 to A7 are Don't care.
2. 1 ≤ n ≤ 65
C
DQ0
AI13575
S
4241 43 44 45 46 47 48 49 50 52 53 54 5540
C
DQ0
S
23
21 345678910 2829303132333435
2221 3210
36 37 38
Instruction 24-bit address
0
765432 0
1
Data byte 1
39
51
765432 0
1
Data byte 2
765432 0
1
Data byte 3 Data byte n
765432 0
1
MSB MSB
MSB MSB MSB
M25PX80 Instructions
37/60
Figure 20. How to permanently lock the 64 OTP bytes
6.14 Write to Lock Register (WRLR)
The Write to Lock Register (WRLR) instruction allows bits to be changed in the Lock
Registers. Before it can be accepted, a Write Enable (WREN) instruction must previously
have been executed. After the Write Enable (WREN) instruction has been decoded, the
device sets the Write Enable Latch (WEL).
The Write to Lock Register (WRLR) instruction is entered by driving Chip Select (S) Low,
followed by the instruction code, three address bytes (pointing to any address in the
targeted sector and one data byte on Serial Data input (DQ0). The instruction sequence is
shown in Figure 21. Chip Select (S) must be driven High after the eighth bit of the data byte
has been latched in, otherwise the Write to Lock Register (WRLR) instruction is not
executed.
Lock Register bits are volatile, and therefore do not require time to be written. When the
Write to Lock Register (WRLR) instruction has been successfully executed, the Write
Enable Latch (WEL) bit is reset after a delay time less than tSHSL minimum value.
Any Write to Lock Register (WRLR) instruction, while an Erase, Program or Write cycle is in
progress, is rejected without having any effects on the cycle that is in progress.
Figure 21. Write to Lock Register (W RLR) inst ruct ion sequence
Byte
0
Byte
1
Byte
2
Byte
64
Byte
63
X X X X bit 3 bit 2 bit 1 bit 0
OTP Control byte64 data bytes
Bit 4 to bit 7 are NOT
programmable
When bits 3, 2, 1, and 0 = 0,
the 64 OTP bytes become
READ only
ai13587
AI13740
C
DQ0
S
23
21 345678910 2829303132333435
2221 3210
36 37 38
Instruction 24-Bit Address
0
765432 0
1
Lock Register
In
39
MSB MSB
Instructions M25PX80
38/60
6.15 Subsector Erase (SSE)
The Subsector Erase (SSE) instruction sets to 1 (FFh) all bits inside the chosen subsector.
Before it can be accepted, a Write Enable (WREN) instruction must previously have been
executed. After the Write Enable (WREN) instruction has been decoded, the device sets the
Write Enable Latch (WEL).
The Subsector Erase (SSE) instruction is entered by driving Chip Select (S) Low, followed
by the instruction code, and three address bytes on Serial Data input (DQ0). Any address
inside the Subsector (see Table 4) is a valid address for the Subsector Erase (SSE)
instruction. Chip Select (S) must be driven Low for the entire duration of the sequence.
The instruction sequence is shown in Figure 22.
Chip Select (S) must be driven High after the eighth bit of the last address byte has been
latched in, otherwise the Subsector Erase (SSE) instruction is not executed. As soon as
Chip Select (S) is driven High, the self-timed Subsector Erase cycle (whose duration is tSSE)
is initiated. While the Subsector Erase cycle is in progress, the Status Register may be read
to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1
during the self-timed Subsector Erase cycle, and is 0 when it is completed. At some
unspecified time before the cycle is complete, the Write Enable Latch (WEL) bit is reset.
A Subsector Erase (SSE) instruction issued to a sector that is hardware or software
protected, is not executed.
Any Subsector Erase (SSE) instruction, while an Erase, Program or Write cycle is in
progress, is rejected without having any effects on the cycle that is in progress.
Figure 22. Subsector Erase (SSE) instruction sequence
1. Address bits A23 to A22 are Don’t care.
Table 10. Lock Re gister in (1)
1. Values of (b1, b0) after power-up are defined in Section 7: Power-up and power-down.
Sector Bit Value
All sectors
b7-b2 ‘0’
b1 Sector Lock Down bit value (refer to Table 9)
b0 Sector Write Lock bit value (refer to Table 9)
24 Bit Address
C
DQ0
AI13741
S
21 3456789 293031
Instruction
0
23 22 20
1
MSB
M25PX80 Instructions
39/60
6.16 Sector Erase (SE)
The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector. Before it
can be accepted, a Write Enable (WREN) instruction must previously have been executed.
After the Write Enable (WREN) instruction has been decoded, the device sets the Write
Enable Latch (WEL).
The Sector Erase (SE) instruction is entered by driving Chip Select (S) Low, followed by the
instruction code, and three address bytes on Serial Data input (DQ0). Any address inside
the Sector (see Table 4) is a valid address for the Sector Erase (SE) instruction. Chip Select
(S) must be driven Low for the entire duration of the sequence.
The instruction sequence is shown in Figure 23.
Chip Select (S) must be driven High after the eighth bit of the last address byte has been
latched in, otherwise the Sector Erase (SE) instruction is not executed. As soon as Chip
Select (S) is driven High, the self-timed Sector Erase cycle (whose duration is tSE) is
initiated. While the Sector Erase cycle is in progress, the Status Register may be read to
check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1
during the self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified
time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
A Sector Erase (SE) instruction applied to a page which is protected by the Block Protect
(BP2, BP1, BP0) bits (see Table 3 and Table 4) is not executed.
Fig ur e 23. Sector E r ase (SE) instruction sequence
1. Address bits A23 to A22 are Don’t care.
6.17 Bulk Erase (BE)
The Bulk Erase (BE) instruction sets all bits to 1 (FFh). Before it can be accepted, a Write
Enable (WREN) instruction must previously have been executed. After the Write Enable
(WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL).
The Bulk Erase (BE) instruction is entered by driving Chip Select (S) Low, followed by the
instruction code on Serial Data input (DQ0). Chip Select (S) must be driven Low for the
entire duration of the sequence.
The instruction sequence is shown in Figure 24.
24 Bit Address
C
DQ1
AI13742
S
21 3456789 293031
Instruction
0
23 22 2 0
1
MSB
Instructions M25PX80
40/60
Chip Select (S) must be driven High after the eighth bit of the instruction code has been
latched in, otherwise the Bulk Erase instruction is not executed. As soon as Chip Select (S)
is driven High, the self-timed Bulk Erase cycle (whose duration is tBE) is initiated. While the
Bulk Erase cycle is in progress, the Status Register may be read to check the value of the
Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Bulk
Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset.
The Bulk Erase (BE) instruction is executed only if all Block Protect (BP2, BP1, BP0) bits
are 0. The Bulk Erase (BE) instruction is ignored if one, or more, sectors are protected.
Figure 24. Bulk Erase (BE) instruction sequence
6.18 Deep Power-down (DP)
Executing the Deep Power-down (DP) instruction is the only way to put the device in the
lowest consumption mode (the Deep Power-down mode). It can also be used as a software
protection mechanism, while the device is not in active use, as in this mode, the device
ignores all Write, Program and Erase instructions.
Driving Chip Select (S) High deselects the device, and puts the device in the Standby Power
mode (if there is no internal cycle currently in progress). But this mode is not the Deep
Power-down mode. The Deep Power-down mode can only be entered by executing the
Deep Power-down (DP) instruction, subsequently reducing the standby current (from ICC1 to
ICC2, as specified in Table 16).
To take the device out of Deep Power-down mode, the Release from Deep Power-down
(RDP) instruction must be issued. No other instruction must be issued while the device is in
Deep Power-down mode.
The Deep Power-down mode automatically stops at power-down, and the device always
powers up in the Standby Power mode.
The Deep Power-down (DP) instruction is entered by driving Chip Select (S) Low, followed
by the instruction code on Serial Data input (DQ0). Chip Select (S) must be driven Low for
the entire duration of the sequence.
The instruction sequence is shown in Figure 25.
Chip Select (S) must be driven High after the eighth bit of the instruction code has been
latched in, otherwise the Deep Power-down (DP) instruction is not executed. As soon as
C
DQ0
AI13743
S
21 345670
Instruction
M25PX80 Instructions
41/60
Chip Select (S) is driven High, it requires a delay of tDP before the supply current is reduced
to ICC2 and the Deep Power-down mode is entered.
Any Deep Power-down (DP) instruction, while an Erase, Program or Write cycle is in
progress, is rejected without having any effects on the cycle that is in progress.
Figure 25. Deep Powe r-down (DP) instruction se quence
6.19 Release from Deep Power-down (RDP)
Once the device has entered the Deep Power-down mode, all instructions are ignored
except the Release from Deep Power-down (RDP) instruction. Executing this instruction
takes the device out of the Deep Power-down mode.
The Release from Deep Power-down (RDP) instruction is entered by driving Chip Select (S)
Low, followed by the instruction code on Serial Data input (DQ0). Chip Select (S) must be
driven Low for the entire duration of the sequence.
The instruction sequence is shown in Figure 26.
The Release from Deep Power-down (RDP) instruction is terminated by driving Chip Select
(S) High. Sending additional clock cycles on Serial Clock (C), while Chip Select (S) is driven
Low, cause the instruction to be rejected, and not executed.
After Chip Select (S) has been driven High, followed by a delay, tRDP
, the device is put in the
Standby mode. Chip Select (S) must remain High at least until this period is over. The
device waits to be selected, so that it can receive, decode and execute instructions.
Any Release from Deep Power-down (RDP) instruction, while an Erase, Program or Write
cycle is in progress, is rejected without having any effects on the cycle that is in progress.
C
DQ0
AI13744
S
21 345670t
DP
Deep Power-down mode
Standby mode
Instruction
Instructions M25PX80
42/60
Figure 26. Release from Deep Power-down (RDP) i nstruction se quenc e
C
DQ0
AI13745
S
21 345670tRDP
Standby mode
Deep Power-down mode
DQ1 High Impedance
Instruction
M25PX80 Power-up and power-down
43/60
7 Power-up and power-down
At power-up and power-down, the device must not be selected (that is Chip Select (S) must
follow the voltage applied on VCC) until VCC reaches the correct value:
VCC(min) at power-up, and then for a further delay of tVSL
VSS at power-down
A safe configuration is provided in Sec tio n 3: SPI modes.
To avoid data corruption and inadvertent write operations during power-up, a Power On
Reset (POR) circuit is included. The logic inside the device is held reset while VCC is less
than the Power On Reset (POR) threshold voltage, VWI – all operations are disabled, and
the device does not respond to any instruction.
Moreover, the device ignores all Write Enable (WREN), Page Program (PP), Dual Input Fast
Program (DIFP), Program OTP (POTP), Subsector Erase (SSE), Sector Erase (SE), Bulk
Erase (BE), Write Status Register (WRSR) and Write to Lock Register (WRLR) instructions
until a time delay of tPUW has elapsed after the moment that VCC rises above the VWI
threshold. However, the correct operation of the device is not guaranteed if, by this time,
VCC is still below VCC(min). No Write Status Register, Program or Erase instructions should
be sent until the later of:
tPUW after VCC has passed the VWI threshold
tVSL after VCC has passed the VCC(min) level.
These values are specified in Table 11.
If the time, tVSL, has elapsed, after VCC rises above VCC(min), the device can be selected
for READ instructions even if the tPUW delay has not yet fully elapsed.
After power-up, the device is in the following state:
The device is in the Standby Power mode (not the Deep Power-down mode).
The Write Enable Latch (WEL) bit is reset.
The Write In Progress (WIP) bit is reset.
The Lock Registers are configured as: (Write Lock bit, Lock Down bit) = (0,0)
Normal precautions must be taken for supply line decoupling, to stabilize the VCC supply.
Each device in a system should have the VCC line decoupled by a suitable capacitor close
to the package pins (generally, this capacitor is of the order of 100 nF).
At power-down, when VCC drops from the operating voltage, to below the Power On Reset
(POR) threshold voltage, VWI, all operations are disabled and the device does not respond
to any instruction. (The designer needs to be aware that if power-down occurs while a Write,
Program or Erase cycle is in progress, some data corruption may result.)
VPPH must be applied only when VCC is stable and in the VCCmin to VCCmax voltage
range.
Power-up and power- down M25PX80
44/60
Figure 27. Powe r-up timi ng
Table 11. P ower-up timing and VWI threshold
Symbol Parameter Min Max Unit
tVSL(1)
1. These parameters are characterized only.
VCC(min) to S low 30 μs
tPUW(1) Time delay to write instruction 1 10 ms
VWI(1) Write Inhibit voltage 1.5 2.1 V
VCC
AI04009C
VCC(min)
VWI
Reset state
of the
device
Chip Selection not allowed
Program, Erase and Write commands are rejected by the device
tVSL
tPUW
tim
e
Read Access allowed Device fully
accessible
V
CC(max)
M25PX80 Ini tial d elivery sta te
45/60
8 Initial delivery state
The device is delivered with the memory array erased: all bits are set to 1 (each byte
contains FFh). The Status Register contains 00h (all Status Register bits are 0).
Maximum rating M25PX80
46/60
9 Maximum rating
Stressing the device outside the ratings listed in Tabl e 1 2: Absol ute maximu m rati ngs may
cause permanent damage to the device. These are stress ratings only, and operation of the
device at these, or any other conditions outside those indicated in the operating sections of
this specification, is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. Refer also to the Numonyx SURE program
and other relevant quality documents.
Table 12. Absolute maximu m ratings
Symbol Parameter Min Max Unit
TSTG Storage temperature –65 150 °C
TLEAD Lead temperature during soldering see(1)
1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the Numonyx RoHS
compliant 7191395 specification, and the European directive on Restrictions on Hazardous Substances
(RoHS) 2002/95/EU.
°C
VIO Input and output voltage (with respect to ground) –0.6 VCC+0.6 V
VCC Supply voltage –0.6 4.0 V
VPP Fast Program/Erase voltage(2)
2. Avoid applying VPPH to the W/VPP pin during Bulk Erase.
–0.2 10.0 V
VESD Electrostatic discharge voltage (Human Body model)(3)
3. JEDEC Std JESD22-A114A (C1 = 100 pF, R1 = 1500 Ω, R2 = 500 Ω).
–2000 2000 V
M25PX80 DC and AC parameters
47/60
10 DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC Characteristic tables that
follow are derived from tests performed under the measurement conditions summarized in
the relevant tables. Designers should check that the operating conditions in their circuit
match the measurement conditions when relying on the quoted parameters.
1. Output Hi-Z is defined as the point where data out is no longer driven.
Fig u re 28. AC meas u reme n t I/ O waveform
Table 13. Operating condi tions
Symbol Parameter Min Typ Max Unit
VCC Supply voltage 2.3 3.6 V
VPPH Supply voltage on VPP pin 8.5 9.5 V
TAAmbient operating temperature –40 85 °C
Table 14. AC me asureme n t co n dit ions
Symbol Parameter Min Max Unit
CL
Load capacitance 30 pF
Input rise and fall times 5 ns
Input pulse voltages 0.2VCC to 0.8VCC V
Input timing reference voltages 0.3VCC to 0.7VCC V
Output timing reference voltages VCC / 2 V
Table 15. Capacitance(1)
1. Sampled only, not 100% tested, at TA=25 °C and a frequency of 33 MHz.
Symbol P arameter Test condition Min Max Unit
CIN/OUT Input/output capacitance (DQ0/DQ1) VOUT = 0 V 8 pF
CIN Input capacitance (other pins) VIN = 0 V 6 pF
AI07455
0.8VCC
0.2VCC
0.7VCC
0.3VCC
Input and output
timing reference levels
Input levels
0.5VCC
DC and AC parameters M25PX8 0
48/60
Table 16. DC character istics
Symbol Parameter Test condition (in addition
to tho s e i n Table 13)Min Max Unit
ILI Input leakage current ± 2 μA
ILO Output leakage current ± 2 μA
ICC1 Standby current S = VCC, VIN = VSS or VCC 50 μA
ICC2 Deep Power-down current S = VCC, VIN = VSS or VCC 10 μA
ICC3
Operating current (READ)
C = 0.1VCC / 0.9VCC at
75 MHz, DQ1 = open 12 mA
C = 0.1VCC / 0.9VCC at
33 MHz, DQ1 = open 4mA
Operating current (DOFR) C = 0.1VCC / 0.9VCC at
75 MHz, DQ1 = open 15 mA
ICC4
Operating current (PP) S = VCC 15 mA
Operating current (DIFP) S = VCC 15 mA
ICC5 Operating current (WRSR) S = VCC 15 mA
ICC6 Operating current (SE) S = VCC 15 mA
ICC7 Operating current (BE) S = VCC 15 mA
VIL Input low voltage – 0.5 0.3VCC V
VIH Input high voltage 0.7VCC VCC+0.4 V
VOL Output low voltage IOL = 1.6 mA 0.4 V
VOH Output high voltage IOH = –100 μAV
CC–0.2 V
Table 17. AC character istics(1)
Test conditions specified in Table 13 and Table 14
Symbol Alt. Parameter Min Typ(2) Max Unit
fCfC
Clock frequency for the following
instructions: DOFR, DIFP, FAST_READ,
SSE, SE, BE, DP, WREN, WRDI, RDID,
RDSR, WRSR, ROTP, PP, POTP,
WRLR, RDLR, RDP
D.C. 75 MHz
fRClock frequency for READ instructions D.C. 33 MHz
tCH(3) tCLH Clock High time 6 ns
tCL(2) tCLL Clock Low time 6 ns
tCLCH(4) Clock rise time(5) (peak to peak) 0.1 V/ns
tCHCL(4) Clock fall time(5) (peak to peak) 0.1 V/ns
tSLCH tCSS S active setup time (relative to C) 5 ns
tCHSL S not active hold time (relative to C) 5 ns
tDVCH tDSU Data In setup time 2 ns
tCHDX tDH Data In hold time 5 ns
M25PX80 DC and AC parameters
49/60
tCHSH S active hold time (relative to C) 5 ns
tSHCH S not active setup time (relative to C) 5 ns
tSHSL tCSH S deselect time 80 ns
tSHQZ(4) tDIS Output Disable time 8 ns
tCLQV tV
Clock Low to Output valid under 30 pF 8 ns
Clock Low to Output valid under 10 pF 6 ns
tCLQX tHO Output hold time 0 ns
tHLCH HOLD setup time (relative to C) 5 ns
tCHHH HOLD hold time (relative to C) 5 ns
tHHCH HOLD setup time (relative to C) 5 ns
tCHHL HOLD hold time (relative to C) 5 ns
tHHQX(4) tLZ HOLD to Output Low-Z 8 ns
tHLQZ(4) tHZ HOLD to Output High-Z 8 ns
tWHSL(6) Write Protect setup time 20 ns
tSHWL(6) Write Protect hold time 100 ns
tVPPHSL
(7)
Enhanced Program supply voltage High
(VPPH) to Chip Select Low 200 ns
tDP(4) S High to Deep Power-down mode 3 μs
tRDP(4) S High to Standby mode 30 μs
tWWrite Status Register cycle time 1.3 15 ms
tPP(8)
Page Program cycle time (256 bytes) 0.8
5
ms
Page Program cycle time (n bytes) int(n/8) ×
0.025(9)
Program OTP cycle time (64 bytes) 0.2 ms
tSSE Subsector Erase cycle time 70 150 ms
tSE Sector Erase cycle time 0.6 3 s
tBE Bulk Erase cycle time 8 80 s
1. 75 MHz operations are allowd only on the VCC range 2.7 V - 3.6 V.
2. Typical values given for TA = 25° C.
3. tCH + tCL must be greater than or equal to 1/ fC.
4. Value guaranteed by characterization, not 100% tested in production.
5. Expressed as a slew-rate.
6. Only applicable as a constraint for a WRSR instruction when SRWD is set at ‘1’.
7. VPPH should be kept at a valid level until the program or erase operation has completed and its result
(success or failure) is known. Avoid applying VPPH to the W/VPP pin during Bulk Erase.
Table 17. AC character istics(1) (continued)
Test conditions specified in Table 13 and Table 14
Symbol Alt. Parameter Min Typ(2) Max Unit
DC and AC parameters M25PX8 0
50/60
8. When using the Page Program (PP) instruction to program consecutive bytes, optimized timings are
obtained with one sequence including all the bytes versus several sequences of only a few bytes (1 ≤ n ≤
256).
9. int(A) corresponds to the upper integer part of A. For example, int(12/8) = 2, int(32/8) = 4 int(15.3) =16.
Table 18. AC characteristics (50 MHz operation)(1)
Test conditions specified in Table 13 and Tabl e 14 .
Symbol Alt. Parameter Min Typ Max Unit
fCfC
Clock frequency(1) for the following instructions: DOFR, DIFP,
FAST_READ, PP, SE, BE, DP, RES, WREN, WRDI, RDID,
RDSR, WRSR
D.C. 50 MHz
fRClock frequency for read instructions D.C. 25 MHz
tCH(2) tCLH Clock high time 9 ns
tCL(2) tCLL Clock low time 9 ns
tCLCH(3) Clock rise time(4) (peak to peak) 0.1 V/ns
tCHCL(3) Clock fall time(4) (peak to peak) 0.1 V/ns
tSLCH tCSS S active setup time (relative to C) 5 ns
tCHSL S not active hold time (relative to C) 5 ns
tDVCH tDSU Data in setup time 2 ns
tCHDX tDH Data in hold time 5 ns
tCHSH S active hold time (relative to C) 5 ns
tSHCH S not active setup time (relative to C) 5 ns
tSHSL tCSH S deselect time 100 ns
tSHQZ(3) tDIS Output disable time 8 ns
tCLQV tVClock Low to Output Valid 8 ns
tCLQX tHO Output hold time 0 ns
tHLCH HOLD setup time (relative to C) 5 ns
tCHHH HOLD hold time (relative to C) 5 ns
tHHCH HOLD setup time (relative to C) 5 ns
tCHHL HOLD hold time (relative to C) 5 ns
tHHQX(3) tLZ HOLD to Output Low-Z 8 ns
tHLQZ(3) tHZ HOLD to Output High-Z 8 ns
tWHSL(5) Write protect setup time 20 ns
tSHWL(5) Write protect hold time 100 ns
tDP(3) S High to deep power-down mode 3 μs
tRES1(3) S High to standby mode without electronic signature read 30 μs
tRES2(3) S High to standby mode with electronic signature read 30 μs
1. 50 MHz operation is also available on the VCC range 2.3 - 2.7 V.
2. tCH + tCL must be greater than or equal to 1/ fC.
3. Value guaranteed by characterization, not 100% tested in production.
M25PX80 DC and AC parameters
51/60
Figure 29. Serial input timi ng
Figure 30. Write Protect Setup and Hold timing during W RSR when SRWD=1
4. Expressed as a slew-rate.
5. Only applicable as a constraint for a WRSR instruction when SRWD is set to ‘1’.
C
DQ0
AI13728
S
MSB IN
DQ1
tDVCH
High Impedance
LSB IN
tSLCH
tCHDX
tCHCL
tCLCH
tSHCH
tSHSL
tCHSHtCHSL
C
DQ0
S
DQ1
High Impedance
W/VPP
tWHSL tSHWL
AI07439c
DC and AC parameters M25PX8 0
52/60
Figure 31. Hold timing
Figure 32. Output timing
C
DQ1
AI13746
S
DQ0
HOLD
tCHHL
tHLCH
tHHCH
tCHHH
tHHQXtHLQZ
C
DQ1
AI13729
S
LSB OUT
DQ0 ADDR.
LSB IN
tSHQZ
tCH
tCL
tQLQH
tQHQL
tCLQX
tCLQV
tCLQX
tCLQV
M25PX80 DC and AC parameters
53/60
Figure 33. VPPH timin g
S
C
DQ0
VPP
VPPH
ai13726-b
tVPPHSL
End of comma nd
( ide nti ed by W I P polling)
Package mechanical M25PX80
54/60
11 Package mechanical
In order to meet environmental requirements, Numonyx offers these devices in RoHS
compliant packages that have have a Lead-free second level interconnect. The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. RoHS compliant specifications are
available at: www.numonyx.com.
Figure 34. VFQFPN8 (MLP8) 8-lead very thin fine pitch dual flat package no lead,
6 × 5 mm, package outline
1. Drawing is not to scale.
Table 19. VFQFPN8 (MLP8 ) 8-lead ve ry thin fine pitch dual flat package no lead,
6 × 5 m m , package mec h an i cal data
Symbol Millimeters Inches
Typ Min Max Typ Min Max
A 0.85 0.80 1.00 0.0335 0.0315 0.0394
A1 0.00 0.05 0.0000 0.0020
A2 0.65 0.0256
A3 0.20 0.0079
b 0.40 0.35 0.48 0.0157 0.0138 0.0189
D 6.00 0.2362
D1 5.75 0.2264
D2 3.40 3.20 3.60 0.1339 0.1260 0.1417
E 5.00 0.1969
E1 4.75 0.1870
E2 4.00 3.80 4.30 0.1575 0.1496 0.1693
e 1.27 – – 0.0500 – –
D
E
70-M
E
A2
AA3
A1
E1
D1
eE2
D2
L
b
θ
R1
ddd
bbb
C
CAB
aaa CAA
B
aaa CB
M
0.10 CA
0.10 CB
2x
M25PX80 Packag e me ch ani cal
55/60
R1 0.10 0.00 0.0039 0.0000
L 0.60 0.50 0.75 0.0236 0.0197 0.0295
Θ12° 12°
aaa 0.15 0.0059
bbb 0.10 0.0039
ddd 0.05 0.0020
Table 19. VFQFPN8 (MLP8 ) 8-lead ve ry thin fine pitch dual flat package no lead,
6 × 5 m m , package mec h an i cal data
Symbol Millimeters Inches
Typ Min Max Typ Min Max
Package mechanical M25PX80
56/60
Fig ur e 35. SO 8W 8-lead p last ic small outline , 208 mils bod y width, package o u tline
1. Drawing is not to scale.
Table 20. S O8W 8-l ead p l astic small outline, 208 m ils b o d y wi dth, packag e
mechanical data
Symbol Millimeters Inches
Typ Min Max Typ Min Max
A 2.50 0.098
A1 0.00 0.25 0.000 0.010
A2 1.51 2.00 0.059 0.079
b 0.40 0.35 0.51 0.016 0.014 0.020
c 0.20 0.10 0.35 0.008 0.004 0.014
CP 0.10 0.004
D 6.05 0.238
E 5.02 6.22 0.198 0.245
E1 7.62 8.89 0.300 0.350
e 1.27 – – 0.050 – –
k 0° 10° 0° 10°
L 0.50 0.80 0.020 0.031
N8 8
6L_ME
E
N
CP
be
A2
D
c
LA1 k
E1
A
1
M25PX80 Packag e me ch ani cal
57/60
Figure 36. SO8N – 8 lead plastic small outline, 150 mils body width, package outli ne
1. Drawing is not to scale.
Table 21. SO8N – 8 lead plastic small outline, 150 mil s body width, pac kage
mechani cal data
Symbol millimeters inches
Typ Min Max Typ Min Max
A 1.75 0.069
A1 0.10 0.25 0.004 0.010
A2 1.25 0.049
b 0.28 0.48 0.011 0.019
c 0.17 0.23 0.007 0.009
ccc 0.10 0.004
D 4.90 4.80 5.00 0.193 0.189 0.197
E 6.00 5.80 6.20 0.236 0.228 0.244
E1 3.90 3.80 4.00 0.154 0.150 0.157
e 1.27 – – 0.050 – –
h 0.25 0.50 0.010 0.020
k0°8°0°8°
L 0.40 1.27 0.016 0.050
L1 1.04 0.041
SO-A
E1
8
ccc
be
A
D
c
1E
h x 45˚
A2
k
0.25 mm
L
L1
A1
GAUGE PLANE
Package mechanical M25PX80
58/60
Figure 37. PDIP8 – 8 lead Plastic Smal l Outlin e, 300 mils body width, pa ck age
outline
1. Package is not to scale.
Table 22. PDIP8 – 8 lead Plastic Small Outlin e, 300 mils body width, pa ck age
mechani cal data
Symbol millimeters inches
Typ Min Max Typ Min Max
A 4.80 0.188
A1 0.50 0.019
A2 3.10 3.30 3.50 0.122 0.129 0.137
b 0.38 0.55 0.014 0.021
b2 1.47 1.52 1.57 0.057 0.059 0.061
c 0.21 0.35 0.008 0.013
D 9.10 9.20 9.30 0.358 0.362 0.366
E 7.62 7.87 8.25 0.300 0.309 0.324
E1 6.25 6.35 6.45 0.246 0.250 0.253
e2.54 0.100
eA 7.62 0.300
eB 7.62 8.80 10.90 0.300 0.346 0.429
L 2.92 3.30 3.81 0.114 0.122 0.150
PDIP-B
A2
A1
A
L
be
D
E1
8
1
c
eA
b2
eB
E
M25PX80 Ordering information
59/60
12 Ordering information
Note: For a list of available options (speed, package, etc.) or for further information on any aspect
of t hi s devi ce, pl ease contac t y our nea rest Numonyx Sales Office.
Table 23. Ordering inform at io n scheme
Example: M25PX80 – V MW 6 T P
Device type
M25PX = serial Flash memory, 4-Kbyte and 64-Kbyte
erasable sectors, dual input/output
Device function
80 = 8 Mbit (1 Mb × 8)
Secu rity feat ures(1)
1. Secure options are available upon customer request.
– = no extra security
SO = OTP configurable
ST = OTP configurable + protection at power_up
S = CFD programmed with UID
O per a t in g vo l tag e
V = VCC = 2.3 V to 3.6 V
Package
MW = SO8W (208 mils width)
MN = SO8N (150 mils width)
MP = VFQFPN 6 × 5 mm (MLP8)
BA = PDIP8 (300 mils width)
Device grade
6 = Industrial temperature range, –40 to 85 °C.
Device tested with standard test flow
3(2) = Automotive temperature range, –40 to 125 °C.
2. Grade 3 is available only in devices delivered in SO8N packages.
Device tested with High Reliability Certified Flow
Option
blank = standard packing
T = tape and reel packing
Plating technology
P or G = RoHS compliant
Revisio n h istory M25PX80
60/60
13 Revision history
Table 24. Doc um ent revis ion history
Date Revision Changes
12-Aug-2008 01 Initial release.
27-Aug-2008 02
Corrected bulk erase specifications on the cover page;
Deleted sector 16 from the memory map;
Changed Vwi from 2.5 V to 2.1 V in Table 11: Powe r-up timing and VWI
threshold on page 44 due to 2.3 V operations;
Corrected the programmable bit range in Table 20: How to permanently
lock the 64 OTP bytes on page 37.
24-Sept-2008 03 Added the following information regarding Bulk Erase: Avoid applying
VPPH to the W/VPP pin during Bulk Erase.
5-Dec-2008 04 Added the PDIP8 (BA), 300 mils width package information.
M25PX80
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Please Read Carefully:
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