2002 Microchip Technology Inc. DS21456B-page 1
TC7109/A
Features
• Zero Integrator Cycle for Fast Recovery from
Input Overloads
• Eliminates Cross-Talk in Multiplexed Systems
• 12-Bit Plus Sign Integrating A/D Converter with
Over Range Indication
• Sign Magnitude Coding Format
• True Differential Signal Input and Differential
Reference Input
• Low Noise: 15µVP-P Typ.
• Input Current: 1pA Typ.
• No Zero Adjustment needed
• TTL Compatible, Byte Organized Tri-State
Outputs
• UART Handshake Mode for simple Serial Data
Transmissions
Device Selection Table
*The “A” version has a higher IOUT on the digital lines.
General Description
The TC7109A is a 12-bit plus sign, CMOS low power
analog-to-digital converter (ADC). Only eight passive
components and a crystal are required to form a
complete dual slope integrating ADC.
TheimprovedV
OH source current and other TC7109A
features make it an attractive per-channel alternative to
analog multiplexing for many data acquisition applica-
tions. These features include typical input bias current
of 1pA, drift of less than 1µV/°C, input noise typically
15µVP-P, and auto-zero. True differential input and ref-
erence allow measurement of bridge type transducers,
such as load cells, strain gauges, and temperature
transducers.
The TC7109A provides a versatile digital interface. In
the Direct mode, chip select and HIGH/LOW byte
enable control parallel bus interface. In the Handshake
mode, the TC7109A will operate with industry standard
UARTs in controlling serial data transmission – ideal for
remote data logging. Control and monitoring of conver-
sion timing is provided by the RUN/HOLD input and
STATUS output.
For applications requiring more resolution, see the
TC500, 15-bit plus sign ADC data sheet. The TC7109A
has improved over range recovery performance and
higher output drive capability than the original TC7109.
All new (or existing) designs should specify the
TC7109A wherever possible.
Part Number
(TC7109X)* Package Temperature
Range
TC7109CKW 44-Pin PQFP 0°C to +70°C
TC7109CLW 44-Pin PLCC 0°C to +70°C
TC7109CPL 40-Pin PDIP 0°C to +70°C
TC7109IJL 40-Pin CERDIP -25°C to +85°C
12-Bit µA-Compatible Analog-to-Digital Converters
TC7109/A
DS21456B-page 2
2002 Microchip Technology Inc.
Package Type
NC = No internal connection
TC7109A
TC7109
1
2
3
4
5
6
7
8
9
10
11
12
STATUS
13
14
15
16
17
18
19
20
POL
OR
TEST
LBEN
HBEN
CE/LOAD
REF OUT
IN HI
IN LO
COMMON
V+
SEND
RUN/HOLD
BUFF OSC OUT
OSC SEL
OSC IN
MODE
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
GND
OSC OUT
V-
BUFF
AZ
INT
REF IN+
REF CAP+
REF CAP-
REF IN-
B
12
B
11
B
10
B
9
B
8
B
7
B
6
B
5
B
4
B
3
B
2
B
1
27
28
29
30
31
32
33
7
4
3
2
1
INT
IN HI
12 13 14 15 17 18
BUFF
OSC OUT
AZ
NC
BUFF
44 43 42 41 39 3840
GND
16
37 36 35 34
19 20 21 22
268 REF OUT
259
2410 SEND
2311
NC
5
6
B
1
TC7109ACKW
TC7109CKW
44-Pin PQFP 44-Pin PLCC
40-Pin PDIP/CERDIP
RUN/HOLD
V-
COMMON
IN LO
REF IN+
REF CAP+
REF CAP-
REF IN-
V+
STATUS
POL
OR
B
9
B
11
B
10
B
8
B
7
NC
B
6
B
5
B
4
B
3
B
2
OSC SEL
OSC OUT
OSC IN
MODE
NC
CE/LOAD
HBEN
LBEN
TEST
B
12
33
34
35
36
37
38
39
13
10
9
8
7
INT
IN HI
18 19 20 21 23 24
BUFF
OSC OUT
AZ
NC
BUFF
6543 1442
GND
22
43 42 41 40
25 26 27 28
3214 REF OUT
3115
3016 SEND
2917
NC
11
12
B
1
TC7109ACLW
TC7109CLW
RUN/HOLD
V-
COMMON
IN LO
REF IN+
REF CAP+
REF CAP-
REF IN-
V+
STATUS
POL
OR
B
9
B
11
B
10
B
8
B
7
NC
B
6
B
5
B
4
B
3
B
2
OSC SEL
OSC OUT
OSC IN
MODE
NC
CE/LOAD
HBEN
LBEN
TEST
B
12
2002 Microchip Technology Inc. DS21456B-page 3
TC7109/A
Typical Application
Input
High
AZ
BUFF
C
AZ
INT
Buffer Integrator
AZ
ZI
AZ
ZI
DE
(+)
AZ
INT
AZ
Comparator
Comp
Out
35
3130
CREF
AZ
DE (±)
ZI
33
34
Common
Input Low
INT
37 36
REF
IN+
DE
(–)
DE
(–)
DE
(+)
R
INT
C
INT
3839
REF
CAP-
REF
CAP+
ZI
6.2V
10µA
28 40
V+
V-
29
REF
OUT
17 3 4 5 6 7 8 9 10 11 12 13 14
22622
23 24 25 21
To Analog
Section
Comp Out
AZ
INT
DE (±)
ZI
Conversion
Control Logic
Oscillator and
Clock Circuitry
Handshake
Logic
15 16
27
18
19
20
LBEN
HBEN
CE/LOAD
1
GND
14 Latches
12-Bit Counter
16 Three-State Outputs
Send
Mode
BUFF
OSC
OUT
OSC
SEL
OSC
OUT
OSC
IN
RUN/
HOLD
Status
POL
OR
TEST
High Order
Byte Inputs
Low Order
Byte Inputs
TC7109A
REF
IN-
B
12
B
11
B
10
B
9
B
8
B
7
B
6
B
5
B
4
B
3
B
2
B
1
Latch
Clock
32
+
+–
–
+
–
TC7109/A
DS21456B-page 4
2002 Microchip Technology Inc.
1.0 ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings*
Positive Supply Voltage (GND to V+)..................+6.2V
Negative Supply Voltage (GND to V-) .....................-9V
Analog Input Voltage (Low to High)
(Note 1)
....V+ to V-
Reference Input Voltage:
(Low to High) (Note 1) ............................. V+ to V-
Digital Input Voltage:
(Pins 2-27) (Note 2) ...........................GND – 0.3V
Power Dissipation,TA<70°C (Note 3)
CerDIP ........................................................2.29W
Plastic DIP ..................................................1.23W
PLCC ..........................................................1.23W
PQFP ..........................................................1.00W
Operating Temperature Range
Plastic Package (C) .........................0°C to +70°C
Ceramic Package (I) .....................-25°C to +85°C
Storage Temperature Range..............-65°C to +150°C
*Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. These
are stress ratings only and functional operation of the device
at these or any other conditions above those indicated in the
operation sections of the specifications is not implied.
Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability.
TC7109/TC7109A ELECTRICAL SPECIFICATIONS
Electrical Characteristics: All parameters with V+ = +5V, V- = -5V, GND = 0V, TA= +25°C, unless otherwise indicated.
Symbol Parameter Min Typ Max Unit Test Conditions
Analog
Overload Recovery Time (TC7109A) — 0 1 Measurement
Cycle
Zero Input Reading -00008±00008+00008Octal Reading VIN = 0V; Full Scale = 409.6mV
Ratio Metric Reading 3777837778
40008
40008Octal Reading VIN =V
REF
VREF =204.8mV
NL Non-Linearity (Max Deviation
from Best Straight Line Fit) -1 ±0.2 +1 Count Full Scale = 409.6mV to 2.048V
Over Full Operating
Temperature Range
Rollover Error (Difference in Reading for
Equal Positive and Inputs near
(Full Scale)
-1 ±0.02 +1 Count Full Scale = 409.6mV to
2.048V Over Full Operating
Temperature Range
CMRR Input Common Mode
Rejection Ratio —50 — µV/V VCM ±1V, VIN =0V
Full Scale = 409.6mV
VCMR Common Mode Voltage Range V- +1.5 — V+ -1.5 V Input High, Input Low and
Common Pins
eNNoise (P-P Value Not
Exceeded 95% of Time) —15 — µVV
IN = 0V, Full Scale = 409.6mV
IIN Leakage Current at Input — 1 10 pA VIN, All Packages: +25°C
— 20 100 pA C Device: 0°C ≤TA≤+70°C
— 100 250 pA I Device: -25°C ≤TA≤+85°C
TCZS Zero Reading Drift — 0.2 1 µV/°C VIN =0V
TCFS Scale Factor Temperature Coefficient — 1 5 µV/°C VIN = 408.9mV = >77708
Reading, Ext Ref = 0ppm/°C
Note 1: Input voltages may exceed supply voltages if input current is limited to ±100µA.
2: Connecting any digital inputs or outputs to voltages greater than V+ or less than GND may cause destructive device
latchup. Therefore, it is recommended that inputs from sources other than the same power supply should not be applied
to the TC7109A before its power supply is established. In multiple supply systems, the supply to the device should be
activated first.
3: This limit refers to that of the package and will not occur during normal operation.
2002 Microchip Technology Inc. DS21456B-page 5
TC7109/A
I+Supply Current (V+ to GND) — 700 1500 µAV
IN = 0V, Crystal Oscillator
3.58MHz Test Circuit
ISSupply Current (V+ to V-) — 700 1500 µA Pins 2-21, 25, 26, 27, 29 Open
VREF Reference Out Voltage -2.4 -2.8 -3.2 V Referenced to V+, 25kΩ
Between V+ and Ref Out
TCREF Ref Out Temperature Coefficient — 80 — ppm/°C 25kΩBetween V+ and Ref Out
0°C ≤ TA≤+70°C
Digital
VOH Output High Voltage
IOUT =700µA3.5 4.3 — V TC7109: IOUT =100µA
Pins 3 -16, 18, 19, 20
TC7109A: IOUT =700µA
VOL Output Low Voltage — 0.2 0.4 µAI
OUT =1.6mA
Output Leakage Current — ±0.01 ±1 µA Pins 3 -16 High Impedance
Control I/O Pull-up Current — 5 — µF Pins 18, 19, 20 VOUT =V+–3V
Mode Input at GND
Control I/O Loading — — 50 pF HBEN,Pin19;LBEN,Pin18
VIH Input High Voltage 2.5 — — V Pins 18 -21, 26, 27
Referenced to GND
VIL Input Low Voltage — — 1 V Pins 18-21, 26, 27
Referenced to GND
Input Pull-up Current —
—5
25 —
—µA
µAPins 26, 27; VOUT =V+–3V
Pins 17, 24; VOUT =V+– 3V
Input Pull-down Current — 1 — µAPins21,V
OUT =GND=+3V
Oscillator Output Current, High — 1 — mA VOUT –2.5V
Oscillator Output Current, Low — 1.5 — mA VOUT –2.5V
Buffered Oscillator Output Current High — 2 — mA VOUT –2.5V
Buffered Oscillator Output Current Low — 5 — mA VOUT –2.5V
tWMode Input Pulse Width 60 — — nsec
HANDLING PRECAUTIONS: These devices are CMOS and must be handled correctly to prevent damage. Package
and store only in conductive foam, antistatic tubes, or other conducting material. Use proper antistatic handling pro-
cedures. Do not connect in circuits under "power-on" conditions, as high transients may cause permanent damage.
TC7109/TC7109A ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: All parameters with V+ = +5V, V- = -5V, GND = 0V, TA= +25°C, unless otherwise indicated.
Symbol Parameter Min Typ Max Unit Test Conditions
Note 1: Input voltages may exceed supply voltages if input current is limited to ±100µA.
2: Connecting any digital inputs or outputs to voltages greater than V+ or less than GND may cause destructive device
latchup. Therefore, it is recommended that inputs from sources other than the same power supply should not be applied
to the TC7109A before its power supply is established. In multiple supply systems, the supply to the device should be
activated first.
3: This limit refers to that of the package and will not occur during normal operation.
TC7109/A
DS21456B-page 6
2002 Microchip Technology Inc.
2.0 PIN DESCRIPTIONS
ThedescriptionsofthepinsarelistedinTable2-1.
TABLE 2-1: PIN FUNCTION TABLE
Pin Number
(40-Pin PDIP) Symbol Description
1 GND Digital ground, 0V, ground return for all digital logic.
2 STATUS Output HIGHduring integrate and de-integrate until data is latched. Output LOW when
analog section is in auto-zero or zero integrator configuration.
3 POL Polarity - High for positive input.
4 OR Over Range - High if over ranged (Three-State Data bit).
5B
12 Bit 12 (Most Significant bit) (Three-State Data bit).
6B
11 Bit 11 (Three-State Data bit).
7B
10 Bit10(Three-StateDatabit).
8B
9Bit 9 (Three-State Data bit).
9B
8Bit 8 (Three-State Data bit).
10 B7Bit 7 (Three-State Data bit).
11 B6Bit 6 (Three-State Data bit).
12 B5Bit 5 (Three-State Data bit).
13 B4Bit 4 (Three-State Data bit).
14 B3Bit 3 (Three-State Data bit).
15 B2Bit 2 (Three-State Data bit).
16 B1Bit 1 (Least Significant bit) (Three-State Data bit).
17 TEST Input High - Normal operation. Input LOW - Forces all bit outputs HIGH.
Note: This input is used for test purposes only.
18 LBEN Low Byte Enable - with MODE (Pin 21) LOW, and CE/LOAD (Pin 20) LOW, taking this pin
LOW activates low order byte outputs, B1–B8. With MODE (Pin 21) HIGH, this pin serves as
low byte flag output used in Handshake mode. (See Figure 3-7, Figure 3-8, and Figure 3-9.)
19 HBEN High Byte Enable - with MODE (Pin 21) LOW, and CE/LOAD (Pin 20) LOW, taking this pin
LOW activates high order byte outputs, B9–B12, POL, OR. With MODE (Pin 21) HIGH, this
pin serves as high byte flag output used in Handshake mode. See Figures 3-7, 3-8, and 3-9.
20 CE/LOAD Chip Enable/Load - with MODE (Pin 21) LOW, CE/LOAD serves as a master output enable.
When HIGH, B1–B12, POL, OR outputs are disabled. When MODE (Pin 21) is HIGH, a load
strobe is used in handshake mode. (See Figure 3-7, Figure 3-8, and Figure 3-9.)
21 MODE Input LOW - Direct Output mode where CE/LOAD (Pin 20), HBEN (Pin 19), and LBEN (Pin
18) act as inputs directly controlling byte outputs. Input Pulsed HIGH- Causes immediate
entry into Handshake mode and output of data as in Figure 3-9.
Input HIGH - enables CE/LOAD (Pin 20), HBEN (Pin 19), and LBEN (Pin 18) as outputs,
Handshake mode will be entered and data output as in Figure 3-7 and Figure 3-9
at conversions completion.
22 OSC IN Oscillator Input.
23 OSC OUT Oscillator Output.
24 OSC SEL Oscillator Select - Input HIGH configures OSC IN, OSC OUT, BUFF OSC OUT as RC
oscillator - clock will be same phase and duty cycle as BUFF OSC OUT. Input LOW
configures OSC IN, OSC OUT for crystal oscillator - clock frequency will be 1/58 of frequency
at BUFF OSC OUT.
25 BUFF OSC OUT Buffered Oscillator Output.
26 RUN/HOLD Input HIGH - Conversions continuously performed every 8192 clockpulses.
Input LOW -Conversion in progress completed; converterwill stop in auto-zero seven counts
before integrate.
27 SEND Input - Used in Handshake mode to indicate ability of an external device to accept data.
Connect to V+ if not used.
28 V- Analog Negative Supply - Nominally -5V with respect to GND (Pin 1).
29 REF OUT Reference Voltage Output - Nominally 2.8V down from V+ (Pin 40).
2002 Microchip Technology Inc. DS21456B-page 7
TC7109/A
Note: All Digital levels are positive true.
3.0 DETAILED DESCRIPTION
(All Pin Designations Refer to 40-Pin DIP.)
3.1 Analog Section
The Typical Application diagram on page 3 shows a
block diagram of the analog section of the TC7109A.
The circuit will perform conversions at a rate deter-
mined by the clock frequency (8192 clock periods per
cycle), when the RUN/HOLD input is left open or con-
nected to V+. Each measurement cycle is divided into
four phases, as shown in Figure 3-1. They are:
(1) Auto-Zero (AZ), (2) Signal Integrate (INT), (3) Ref-
erence De-integrate (DE), and (4) Zero Integrator (ZI).
3.1.1 AUTO-ZERO PHASE
The buffer and the integrator inputs are disconnected
from input high and input low and connected to analog
common. The reference capacitor is charged to the ref-
erence voltage. A feedback loop is closed around the
system to charge the auto-zero capacitor, CAZ,tocom-
pensate for offset voltage in the buffer amplifier, inte-
grator, and comparator. Since the comparator is
included in the loop, the AZ accuracy is limited only by
the noise of the system. The offset referred to the input
is less than 10µV.
3.1.2 SIGNAL INTEGRATE PHASE
The buffer and integrator inputs are removed from com-
mon and connected to input high and input low. The
auto-zero loop is opened. The auto-zero capacitor is
placed in series in the loop to provide an equal and
opposite compensating offset voltage. The differential
voltage between input high and input low is integrated
for a fixed time of 2048 clock periods. At the end of this
phase, the polarity of the integrated signal is deter-
mined. If the input signal has no return to the con-
verter's power supply, input low can be tied to analog
common to establish the correct Common mode
voltage.
3.1.3 DE-INTEGRATE PHASE
Input high is connected across the previously charged
reference capacitor and input low is internally con-
nected to analog common. Circuitry within the chip
ensuresthe capacitor will be connected with the correct
polarity to cause the integrator output to return to the
zero crossing (established by auto-zero), with a fixed
slope. The time, represented by the number of clock
periods counted for the output to return to zero, is
proportional to the input signal.
30 BUFF Buffer Amplifier Output.
31 AZ Auto-Zero Node - Inside foil of CAZ.
32 INT Integrator Output - Outside foil of CINT.
33 COMMON Analog Common - System is auto-zeroed to COMMON.
34 IN LO Differential Input Low Side.
35 IN HI Differential Input High Side.
36 REF IN+ Differential Reference Input Positive.
37 REF CAP+ Reference Capacitor Positive.
38 REF CAP- Reference Capacitor Negative.
39 REF IN- Differential Reference Input Negative.
40 V+ Positive Supply Voltage - Nominally +5V with respect to GND (Pin 1).
TABLE 2-1: PIN FUNCTION TABLE (CONTINUED)
Pin Number
(40-Pin PDIP) Symbol Description
TC7109/A
DS21456B-page 8
2002 Microchip Technology Inc.
3.1.4 ZERO INTEGRATOR PHASE
The ZI phase only occurs when an input over range
condition exists. The function of the ZI phase is to elim-
inate residual charge onthe integrator capacitor after an
overrange measurement.Unless removed, the residual
charge will betransferred tothe auto-zero capacitorand
cause an error in the succeeding conversion.
The ZI phase virtually eliminates hysteresis, or "cross-
talk" in multiplexed systems. An over range input on
one channel will not cause an error on the next channel
measured. This feature is especially useful in thermo-
couple measurements, where unused (or broken ther-
mocouple) inputs are pulled to the positive supply rail.
During ZI, the reference capacitor is charged to the ref-
erence voltage. The signal inputs are disconnected
from the buffer and integrator. The comparatoroutput is
connected to the buffer input, causing the integrator
output to be driven rapidly to 0V (Figure 3-1). The ZI
phase only occurs following an over range and lasts for
a maximum of 1024 clock periods.
3.1.5 DIFFERENTIAL INPUT
The TC7109A has been optimized for operation with
analog common near digital ground. With +5V and -5V
power supplies, a full ±4V full scale integrator swing
maximizes the analog section's performance.
A typical CMRR of 86dB is achieved for input differen-
tial voltages anywhere within the typical Common
mode range of 1V below the positive supply, to 1.5V
above the negative supply. However, for optimum per-
formance, the IN HI and IN LO inputs should not come
within 2V of either supply rail. Since the integrator also
swings with the Common mode voltage, care must be
exercised to ensure the integrator output does not sat-
urate. A worst case condition is near a full scale nega-
tive differential input voltage with a large positive
Common mode voltage. The negative input signal
drives the integrator positive when most of its swing
has been used up by the positive Common mode volt-
age. In such cases, the integrator swing can be
reduced to less than the recommended ±4V full scale
value, with some loss of accuracy. The integrator out-
put can swing to within 0.3V of either supply without
loss of linearity.
3.1.6 DIFFERENTIAL REFERENCE
The reference voltage can be generated anywhere
within the power supply voltage of the converter. Roll-
over voltage is the main source of Common mode
error, caused by the reference capacitor losing or gain-
ing charge, due to stray capacity on its nodes. With a
large Common mode voltage, the reference capacitor
can gain charge (increase voltage) when called upon to
de-integrate a positive signal and lose charge
(decrease voltage) when called upon to de-integrate a
negative input signal. This difference in reference for
(+) or (–) input voltages will cause a rollover error. This
error can be held to less than 0.5 count, worst case, by
using a large reference capacitor in comparison to the
stray capacitance. To minimize rollover error from
these sources, keep the reference Common mode
voltage near or at analog common.
3.2 Digital Section
The digital section is shown in Figure 3-2 and includes
the clock oscillator and scaling circuit, a 12-bit binary
counter with output latches and TTL compatible three-
state output drivers, UART handshake logic, polarity,
over range, and control logic. Logic levels are referred
to as LOW or HIGH.
Inputs driven from TTL gates should have 3kΩto 5kΩ
pull-up resistors added for maximum noise immunity.
For minimum power consumption, all inputs should
swing from GND (LOW) to V+ (HIGH).
3.2.1 STATUS OUTPUT
During a conversion cycle, the STATUS output goes
high at the beginning of signal integrate and goes low
one-half clock period after new data from the conver-
sion has been stored in the output latches (see
Figure 3-1). The signal may be used as a "data valid"
flag to drive interrupts, or for monitoring the status of
the converter. (Data will notchange while statusis low.)
3.2.2 MODE INPUT
The Output mode of the converter is controlled by the
MODE input. The converter is in its "Direct" Output
mode, when the MODE input is LOW or left open. The
output data is directly accessible under the control of
the chip and byte enable inputs (this input is provided
with a pull-down resistor to ensure a LOW level when
the pin is left open). When the MODE input is pulsed
high, the converter enters the UART Handshake mode
and outputs the data in 2 bytes, then returns to "Direct"
mode. When the MODE input is kept HIGH, the con-
verter will output data in the Handshake mode at the
end of every conversion cycle. With MODE = 0 (direct
bus transfer), the send input should be tied to V+. (See
"Handshake Mode".)
2002 Microchip Technology Inc. DS21456B-page 9
TC7109/A
3.2.3 RUN/HOLD INPUT
With the RUN/HOLD input high, or open, the circuit
operates normally as a dual slope ADC, as shown in
Figure 3-1. Conversion cycles operate continuously
with the output latches updated after zero crossing in
the De-integrate mode. An internal pull-up resistor is
provided to ensure a HIGH level with an open input.
The RUN/HOLD input may be used to shorten conver-
sion time. If RUN/HOLD goes LOW any time after zero
crossing in the De-integrate mode, the circuit will jump
to auto-zero and eliminate that portion of time normally
spent in de-integrate.
If RUN/HOLD stays or goes LOW, the conversion will
complete with minimum time in de-integrate. It will stay
in auto-zero for the minimum time and wait in auto-zero
for a HIGH at the RUN/HOLD input. As shown in
Figure 3-3, the STATUS output will go HIGH, 7 clock
periods after RUN/HOLD is changed to HIGH, and the
converter will begin the integrate phase of the next
conversion.
The RUN/HOLD input allows controlled conversion
interface. The converter may be held at IDLE in auto-
zero with RUN/HOLD LOW.Theconversionisstarted
when RUN/HOLD goes HIGH, and the new data is
valid when the STATUS output goes LOW (or is trans-
ferred to the UART; see "Handshake Mode"). RUN/
HOLD may now go LOW, terminating de-integrate and
ensuring a minimum auto-zero time before stopping to
wait for the next conversion. Conversion time can be
minimized by ensuring RUN/HOLD goes LOW during
de-integrate, after zero crossing, and goes HIGH after
the hold point is reached.
The required activity on the RUN/HOLD input can be
provided by connecting it to the buffered oscillator out-
put. In this mode, the input value measured determines
the conversion time.
FIGURE 3-1: CONVERSION TIMING (RUN/HOLD PIN HIGH
Internal Clock
Integrator Output
for Normal Input
Integrator
Saturates
Internal Latch
Integrator Output
for Over Range Input No Zero Crossing
ZI
AZ
Zero Integrator
Phase forces
Integrator Outpu
t
to 0V
Zero Crossing
Occurs
Zero Crossing
Detected
INT
Phase II
Status Output
AZ
Phase I
DE
Phase III AZ
Fixed
2048
Counts
2048
Counts
Min.
4096
Counts
Max
Number of Counts to Zero Crossing
Proportional to VIN
After Zero Crossing, Analog section will
be in Auto-Zero Configuration
TC7109/A
DS21456B-page 10
2002 Microchip Technology Inc.
FIGURE 3-2: DIGITAL SECTION
FIGURE 3-3: TC7109A RUN/HOLD OPERATION
TEST
17
POL
3
OR
4
B
12
5
B
11
6
B
10
7
B
9
8
B
8
9
B
7
10
B
6
11
B
5
12
B
4
13
B
3
14
2262223242521
STATUS RUN/
HOLD
OSC
IN
OSC
OUT
OSC
SEL
BUFF
OSC
OUT
MODE
To
Analog
Section
COMP OUT
AZ
INT
DE (±)
ZI
Conversion
Control Logic
Oscillator and
Clock Circuitry
High Order
Byte Outputs
Low Order
Byte Outputs
Handshake
Logic
B
2
15
B
1
16
27
SEND
18
19
20
LBEN
HBEN
CE/LOAD
1
GND
14 Latches
12-Bit Counter
14 Three-State Outputs
Latch
Clock
Integrator Output
Internal Clock
Determinated at
Zero Crossing
Detection
Auto-Zero Phase I
Min 1790 Counts
Max 2041 Counts Static in
Hold State
INT
Phase II
RUN/HOLD input is i
g
nored until end of auto-zero phase.*Note:
*
Internal Latch
Status Output
RUN/HOLD Input
7 Counts
2002 Microchip Technology Inc. DS21456B-page 11
TC7109/A
3.2.4 DIRECT MODE
The data outputs (bits 1 through 8, low order bytes; bits
9 through 12, polarity and over range high order bytes)
are accessible under control of the byte and chip
enable terminals as inputs, with the MODE pin at a
LOW level. These three inputs are all active LOW.
Internal pull-up resistors are provided for an inactive
HIGH level when left open. When chip enable is LOW,
a byte enable input LOW will allow the outputs of the
byte to become active. A variety of parallel data
accessing techniques may be used, as shown in the
"Interfacing" section. (See Figure 3-4 and Table 3-1.)
The access of data should be synchronized with the
conversion cycle by monitoring the STATUS output.
This prevents accessing data while it is being updated
and eliminates the acquisition of erroneous data.
FIGURE 3-4: TC7109A DIRECT MODE
OUTPUT TIMING
TABLE 3-1: TC7109A DIRECT MODE
TIMING REQUIREMENTS
3.2.5 HANDSHAKE MODE
An alternative means of interfacing the TC7109A to
digital systems is provided when the Handshake Out-
put mode ofthe TC7109A becomes active in controlling
the flow of data, instead of passively responding to chip
and byte enable inputs. This mode allows a direct inter-
face between the TC7109A and industry standard
UARTs with no external logic required. The TC7109A
provides all the control and flag signals necessary to
sequence the two bytes of data into the UART and ini-
tiate their transmission in serial form when triggered
into the Handshake mode. The cost of designing
remote data acquisition stationsis reduced using serial
data transmission to minimize the number of lines to
the central controlling processor.
The MODE input controls the Handshake mode. When
the MODE input is held HIGH, the TC7109A enters the
Handshake mode after new data has been stored in the
output latches at the end of every conversion per-
formed (see Figure 3-7 and Figure 3-8). Entry into the
Handshake mode may be triggered on demand by the
MODE input. At any time during the conversion cycle,
the LOW-to-HIGH transition of a short pulse at the
MODE input will cause immediate entry into the Hand-
shake mode. If this pulse occurs while new data is
being stored, the entry into Handshake mode is
delayed until the data is stable. The MODE input is
ignored in the Handshake mode, and until the con-
verter completes the output cycle and clears the Hand-
shake mode, data updating will be inhibited (see
Figure 3-9).
When the MODE input is HIGH, or when the converter
enters the Handshake mode, the chip and byte enable
inputs become TTL compatible outputs, which provide
the output cycle control signals (see Figure 3-7,
Figure 3-8 and Figure 3-9). The SEND input is used by
the converter as an indication of the ability of the
receiving device (such as a UART) to accept data in the
Handshake mode. The sequence of the output cycle
with SEND held HIGH is shown in Figure 3-7. The
Handshake mode (internal MODE HIGH) is entered
after the data latch pulse (the CE/LOAD, LBEN and
HBEN terminals are active as outputs, since MODE
remains HIGH).
The HIGH level at the SEND input is sensed on the
same HIGH-to-LOW internal clock edge. On the next
LOW-to-HIGH internal clock edge, the high order byte
(bits 9 through 12, POL, and OR) outputs are enabled
and the CE/LOAD and the HBEN outputs assume a
LOW level. The CE/LOAD output remains LOW for one
full internal clock period only; the data outputs remain
active for 1-1/2 internal clock periods; and the high byte
enable remains LOW for 2 clock periods.
Symbol Description Min Typ Max Units
tBEA Byte Enable Width 200 500 — nsec
tDAB Data Access Time
from Byte Enable — 150 300 nsec
tDHB DataHold Time from
Byte Enable — 150 300 nsec
tCEA Chip Enable Width 300 500 nsec
tDAC Data Access Time
from Chip Enable — 200 400 nsec
tDHC DataHold Time from
Chip Enable — 200 400 nsec
= Hi
g
h Impedance
CE/LOAD
As Input
t
CEA
t
BEA
HBEN
As Input
t
DAB
t
DAB
LBEN
As Input
High Byte
Data
Low Byte
Data
Data
Valid
t
DAC
t
DHC
Data
Valid
Data
Valid
TC7109/A
DS21456B-page 12
2002 Microchip Technology Inc.
The CE/LOAD output LOW level, or LOW-to-HIGH
edge, maybe used asa synchronizing signal to ensure
valid data, and the byte enable as an output may be
used as a byte identification flag. With SEND remaining
HIGH, the converter completes the output cycle using
CE/LOAD and LBEN, while the low order byte outputs
(bits 1 through 8) are activated. When both bytes are
sent, the Handshake mode is terminated. The typical
UART interfacing timing is shown in Figure 3-8.
The SEND input is used to delay portions of the
sequence, or handshake, to ensure correct data trans-
fer. This timing diagram shows an industry standard
HD6403 or CDP1854 CMOS UART to interface to
serial data channels. The SEND input to the TC7109A
is driven by the TBRE (Transmitter Buffer Register
Empty) output of the UART, and the CE/LOAD input of
the TC7109A drives the TBRL (Transmitter Buffer Reg-
ister Load) input to the UART. The eight transmitter
buffer register inputs accept the parallel data outputs.
With the UART transmitter buffer register empty, the
SEND input will be HIGH when the Handshake mode is
entered, after new data is stored. The high order byte
outputs become active and the CE/LOAD and HBEN
inputs will go LOW after SEND is sensed. When CE/
LOAD goes HIGH at the end of one clock period, the
high order byte data is clocked into the UART transmit-
ter buffer register. TheUART TBREoutput will go LOW,
which halts the output cycle with the HBEN output
LOW, and the high orderbyte outputs active. When the
UART has transferred the data to the transmitter regis-
ter and cleared the transmitter buffer register, the
TBRE returns HIGH. The high order byte outputs are
disabled on the next TC7109A internal clock HIGH-to-
LOW edge, and one-half internal clock later, the HBEN
output returns HIGH. The CE/LOAD and LBEN outputs
go LOW at the same time asthe low orderbyte outputs
become active. When the CE/LOAD returns HIGH at
the end of one clock period, the low order data is
clocked into the UART transmitter buffer register, and
TBRE again goes LOW. The next TC7109A internal
clock HIGH-to-LOW edge will sense when TBRE
returns to a HIGH, disabling the data inputs. One-half
internal clock later, the Handshake mode is cleared,
and the CE/LOAD, HBEN and LBEN terminals return
HIGH and stay active, if MODE still remains HIGH.
Handshake output sequences may be performed on
demand by triggering the converter into Handshake
mode with a LOW-to-HIGH edge on the MODE input. A
handshake output sequence triggered is shown in
Figure 3-9. The SEND input is LOW when the con-
verter enters Handshake mode. The whole output
sequence is controlled by the SEND input, and the
sequence for the first (high order) byte is similar to the
sequence for the second byte.
Figure 3-9 also shows that the output sequence can
take longer than a conversion cycle. New data will not
be latched when the Handshake mode is still in
progress and is, therefore, lost.
3.3 Oscillator
The oscillator may be over driven, or may be operated
as an RC or crystal oscillator. The OSCILLATOR
SELECT input optimizes the internal configuration of
the oscillator for RC or crystal operation. The OSCIL-
LATOR SELECT input is provided with a pull-up resis-
tor. When the OSCILLATOR SELECT input is HIGH or
left open, the oscillator is configured for RC operation.
The internal clock will be the same frequency and
phase as the signal at the BUFFERED OSCILLATOR
OUTPUT. Connect the resistor and capacitor as in
Figure 3-5. The circuitwilloscillate at afrequency given
by f = 0.45/RC. A 100kΩresistor is recommended for
useful ranges of frequency. The capacitor value should
be chosen such that2048 clock periods are closeto an
integral multiple of the 60Hz period for optimum 60Hz
line rejection.
FIGURE 3-5: TC7109A RC
OSCILLATOR
With OSCILLATOR SELECT input LOW, two on-chip
capacitors and a feedback device are added to the
oscillator. In this configuration, the oscillator will oper-
ate with most crystals in the 1MHz to 5MHz range, with
no external components (Figure 3-6). The OSCILLA-
TOR SELECT input LOW inserts a fixed 458 divider cir-
cuit between the BUFFERED OSCILLATOR OUTPUT
and the internal clock. A 3.58MHz TV crystal gives a
division ratio, providing an integration time given by:
EQUATION 3-1:
23
OSC
OUT
25
Buffered
OSC OUT
24
OSC
SEL
V+ or Open
22
OSC
IN
R
C
FOSC = 0.45/RC
t = (2048 clock periods) = 33.18msec
58
3.58MHz
2002 Microchip Technology Inc. DS21456B-page 13
TC7109/A
FIGURE 3-6: CRYSTAL OSCILLATOR The error is less than 1% from two 60Hz periods, or
33.33msec, which will give better than 40dB, 60Hz
rejection. The converter will operate reliably at conver-
sion rates up to 30 per second, corresponding to a
clock frequency of 245.8kHz.
When the oscillator is to be over driven, the OSCILLA-
TOR OUTPUT should be left open, and the over driving
signal should be applied at the OSCILLATOR INPUT.
The internal clock will be of the same duty cycle, fre-
quency and phase as the input signal. When the
OSCILLATOR SELECT is at GND, the clock will be
1/58 of the input frequency.
FIGURE 3-7: TC7109A HANDSHAKE WITH SEND INPUT HELD POSITIVE
23
OSC
OUT
25
Buffered
OSC OUT
24
OSC
SEL
GND
V+
22
OSC
IN
58
Clock
Crystal
÷
= Three-State
Hi
g
h Impendance
Integrator Output
Data Invalid
Data Valid
Internal Clock
Internal Latch
Status Output
Mode Input
Internal Mode
Send Input
CE/LOAD
HBEN
High Byte Data
LBEN
Low Byte Data
= Don't Care = Three-State
will Pull-up
UART
Norm
Terminates
UART Mode
Zero Crossing Detected
Zero Crossing Occurs
Send Sensed Send Sensed
Mode Low, not
in Handshake Mode
Disables Outputs
CE/LOAD,
HBEN,
LBEN
Mode High Activates
CE/LOAD, HBEN, LBEN
TC7109/A
DS21456B-page 14
2002 Microchip Technology Inc.
FIGURE 3-8: TC7109A HANDSHAKE - TYPICAL UART INTERFACE TIMING
FIGURE 3-9: TC7109A HANDSHAKE TRIGGERED BY MODE INPUT
= Three-State High Impedance
Integrator Output
Data Valid
Internal Clock
Internal Latch
Status Output
Mode Input
Internal Mode
Send Input (UART TBRE)
CE/LOAD Output (UART TBRL)
HBEN
High Byte Data
LBEN
Low Byte Data
= Don't Care
UART
Norm
Terminates
UART Mode
Zero Crossing Detected
Zero Crossing Occurs
Send
Sensed Send
Sensed
Send
Sensed
Data Valid
Data Valid
Data Valid
Terminates
UART Mode
= Three-State
Hi
g
h Impedance
Internal Clock
Internal Latch
Status Output
Mode Input
Internal Mode
Send Input
CE/LOAD as Output
HBEN
High Byte Data
LBEN
Low Byte Data
= Don't Care = Three-State
with Pull-up
UART
Norm Send
Sensed
Send
Sensed
Zero Crossing Detected
Zero Crossing Occurs
Status Output unchanged
in UART Mode
Latch Pulse inhibited in UART Mod
e
Positive Transiton causes
Entry into UART Mode
DE Phase III
Send
Sensed
2002 Microchip Technology Inc. DS21456B-page 15
TC7109/A
3.4 Test Input
The counter and its outputs may be tested easily. When
the TEST input is connected to GND, the internal clock
is disabled and the counter outputs are all forced into
the HIGH state. When the input returns to the 1/2
(V+ – GND) voltage or to V+ andone clockis input, the
counter outputs will all be clocked to the LOW state.
The counter output latches are enabled when the TEST
input is taken to a level halfway between V+ and GND,
allowingthecountercontents to be examined any time.
3.5 Component Value Selection
The integrator output swing for full scale should be as
large as possible. For example, with ±5V supplies and
COMMON connected to GND, the nominal integrator
output swing at full scale is ±4V. Since the integrator
output can go to 0.3V from either supply without signif-
icantly effecting linearity, a 4V integrator output swing
allows 0.7V for variations in output swing, due to com-
ponent value and oscillator tolerances. With ±5V sup-
plies and a Common mode voltage range of ±1V
required, the component values should be selected to
provide ±3V integrator output swing. Noise and roll-
over errors will be slightly worse than in the ±4V case.
For large Common mode voltage ranges, the integrator
output swing must be reduced further. This will
increase both noise and rollover errors. To improve
performance, ±6V supplies may be used.
3.5.1 INTEGRATING CAPACITOR
The integrating capacitor, CINT, should be selected to
give the maximum integrator output voltage swing that
will not saturate the integrator to within 0.3V from either
supply. A ±3.5V to ±4V integrator output swing is nom-
inal for the TC7109A, with ±5V supplies and analog
common connected to GND. For 7-1/2 conversions per
second (61.72kHz internal clock frequency), nominal
values CINT and CAZ are 0.15µF and 0.33µF, respec-
tively. These values should be changed if different
clock frequencies are used to maintain the integrator
output voltage swing. The value of CINT is given by:
EQUATION 3-2:
The integrating capacitor must have low dielectric
absorption to prevent rollover errors. Polypropylene
capacitors give undetectable errors, at reasonable
cost, up to +85°C.
3.5.2 INTEGRATING RESISTOR
The integrator and buffer amplifiers have a class A out-
put stage with 100µA of quiescent current. They supply
20µA of drive current with negligible non-linearity. The
integrating resistor should be large enough to remain in
this very linear region over the input voltage range, but
small enough that undue leakage requirements are not
placed on the PC board. For 2.048V full scale, a 100kΩ
resistor is recommended and for 409.6mV full scale, a
20k resistor is recommended. RINT may be selected for
other values of full scale by:
EQUATION 3-3:
3.5.3 AUTO-ZERO CAPACITOR
As the auto-zero capacitor is made large, the system
noise is reduced. Since the TC7109A incorporates a
zero integrator cycle, the size of the auto-zero capaci-
tor does not affect overload recovery. Theoptimal value
of the auto-zero capacitor is between 2 and 4 times
CINT. A typical value for CAZ is 0.33µF.
The inner foilof CAZ should be connected to Pin 31 and
the outer foil to the RC summing junction. The inner foil
of CINT should be connected to the RC summing junc-
tion and the outer foil to Pin 32, for best rejection of
stray pickups.
3.5.4 REFERENCE CAPACITOR
A1µF capacitor is recommended for most circuits.
However, where a large Common mode voltage exists,
a larger value is required to prevent rollover error (e.g.,
the reference low is not analog common), and a
409.6mV scale is used. The rollover error will be held
to 0.5 count with a 10µF capacitor.
3.5.5 REFERENCE VOLTAGE
To generate full scale output of 4096 counts, the analog
input required is VIN =2V
REF. For 409.6mV full scale,
use a reference of 204.8mV. In many applications,
where the ADC is connected to a transducer, a scale
factor will exist between the inputvoltage and the digital
reading. For instance, in a measuring system, the
designer might like to have a full scale reading when
the voltage for the transducer is 700mV. Instead of
dividing the input down to 409.6mV, the designer
should use the input voltage directly and select
VREF = 350mV. Suitable values for integrating resistor
and capacitor would be 34kΩand 0.15µF. This makes
the system slightly quieter and also avoids a divider
network on the input. Another advantage of this system
occurs when temperature and weight measurements,
with an offset or tare, are desired for non-zero input.
The offset may be introduced by connecting the voltage
output of the transducer between common and analog
high,and the offset voltage between common andana-
log low, observing polarities carefully. In processor
based systems using the TC7109A, it may be more
desirable to use software and perform this type of scal-
ing or tare subtraction digitally.
(2048 Clock Period) (20µA)
Integrator Output Voltage Swings
CINT =
Full Scale Voltage
20µA
RINT =
TC7109/A
DS21456B-page 16
2002 Microchip Technology Inc.
3.5.6 REFERENCE SOURCES
A major factor in the absolute accuracy of the ADC is
the stability of the reference voltage. The 12-bit resolu-
tion of the TC7109A is one part in 4096, or 244 ppm.
Thus, for the on-board reference temperature coeffi-
cient of 70ppm/°C, a temperature difference of 3°C will
introduce a one-bit absolute error. Where the ambient
temperature is not controlled, or where high accuracy
absolute measurements are being made, it is recom-
mended that an external high quality reference be
used.
A reference output (Pin 29) is provided, which may be
used with a resistive divider to generate a suitable ref-
erence voltage (20mA may be sunk without significant
variation in output voltage). A pull-up bias device is pro-
vided,which sourcesabout 10µA. The output voltage is
nominally 2.8V below V+. When using the on-board ref-
erence, REF OUT (Pin 29) should be connected to
REF IN-(pin 39), and REF IN+ should be connected to
the wiper of a precision potentiometer between REF
OUT and V+. The test circuit shows the circuit for a
204.8mV reference, generated by a 2kΩprecision
potentiometer in series with a 24kΩfixed resistor.
4.0 INTERFACING
4.1 Direct Mode
Combinations of chip enable and byte enable control
signals, which may be used when interfacing the
TC7109A to parallel data lines, are shown in Figure 4-1.
The CE/LOAD input may be tied low, allowing either byte
to be controlled by its own enable (see Figure 4-1(A)).
Figure 4-1(B) shows the HBEN and LBEN as flag
inputs, and CE/LOAD as a master enable, which could
be the READ strobe available from most microproces-
sors. Figure 4-1(C) shows a configuration where the
two byte enables are connected together. The CE/
LOAD is a chip enable, and the HBEN and LBEN may
be used as a second chip enable, or connected to
ground. The 14 data outputs will be enabled at the
same time. In the direct MODE, SEND should be tied
to V+.
Figure 4-2 shows interfacing several TC7109A's to a
bus, ganging the HBEN and LBEN signals to several
converters together, and using the CE/LOAD input to
select the desired converter.
Figure 4-3 through Figure 4-5 give practical circuits uti-
lizing the parallel three-state output capabilities of the
TC7109A. Figure 4-3 shows parallel interface to the
8748/49 systems via an 8255 PPI, where the TC7109A
data outputs are active at all times. This interface can
be used in a read-after-update sequence, as shown in
Figure 4-4. The data is accessed by the high-to-low
transition of the STATUS driving an interrupt to the
microcontroller.
The RUN/HOLD input is also used to initiate conver-
sions under software control.
Direct interfacing to most microcontroller busses is
easily accomplished through the three-state output of
the TC7109A.
Figure 4-8 is a typical connection diagram. To ensure
requirements for setup and hold times, minimum pulse
widths, and the drive limitations on long busses are
met, it is necessary to carefully consider the system
timing in this type of interface. This type of interface is
used when the memory peripheral address density is
low, providing simple address decoding. Interrupt han-
dling can be simplified by using an interface to reduce
the component count.
FIGURE 4-1: DIRECT MODE CHIP AND BYTE ENABLE COMBINATION
TC7109A
MODE CE/LOAD
B9 - B12
POL, OR
B1 - B8
LBENHBEN
GND
8
Analog In
6
Convert
Control
RUN/HOLD
TC7109A
MODE CE/LOAD
B1 - B12
POL, OR
LBENHBEN
GND
Analog In
Convert
RUN/HOLD
TC7109A
MODE CE/LOAD
B9 - B12
POL, OR
B1 - B8
LBENHBEN
8
Analog In
6
Convert
RUN/HOLD
Chip Select 1
GND or
Chip Select 2
14
B
y
te Fla
g
s
GND Chip Select
A. B. C.
2002 Microchip Technology Inc. DS21456B-page 17
TC7109/A
FIGURE 4-2: THREE-STATING SEVERAL TC7109ASTO A SMALL BUS
FIGURE 4-3: FULL TIME PARALLEL INTERFACE TO µPD8748H/494 MICROCONTROLLERS
TC7109A
MODE CE/LOAD
B
9
- B
12
POL, OR
B
1
- B
8
LBENHBEN
GND
8
Analog In
6
RUN/HOLD +5V
Converter Select Converter Select Converter Select
TC7109A
MODE CE/LOAD
B
9 -
B
12
POL, OR
B
1
- B
8
LBENHBEN
GND
8
Analog In
6
RUN/HOLD +5V
TC7109A
MODE CE/LOAD
B
9
- B
12
POL, OR
B
1
- B
8
LBENHBEN
GND
8
Analog In
6
RUN/HOLD +5V
Byte Select Flags
TC7109A
MODE CE/LOAD
B9 - B12
POL, OR
B1 - B8
STATUS
RUN/HOLD
LBENHBEN
GND
GND
8
6
See Text
µPD8255A
(Mode 0)
RD WR D7 - D0 A0 - A1
CS
PA5 - PA0
PB7 - PB0
PC5
µPD8748H/49H
Data Bus
Control Bus
Address Bus
Analog In
+5V
TC7109/A
DS21456B-page 18
2002 Microchip Technology Inc.
FIGURE 4-4: FULL TIME PARALLEL INTERFACE TO µPD8748H/494 MICROCONTROLLERS
FIGURE 4-5: TC7109A HANDSHAKE INTERFACE TO µPD8748H/494 MICROCONTROLLERS
TC7109A
MODE CE/LOAD
B
9
- B
12
POL, OR
B
1
- B
8
STATUS
RUN/HOLD
LBENHBEN
GND
GND
8
6
+5V
(See Text)
1µF
µPD8255A
RD WR D7 - D0
PC6
A0 - A1
CS
PA5 - PA0
PB7 - PB0
PC4
STB
A
PC6 INTR
µPD8748H/49H
Data Bus
Control Bus
Address Bus
INTR
A
Analog In
10kΩ
TC7109A
B
9
- B
12
POL, OR
B
1
- B
8
CE/LOAD
SEND
RUN/HOLD
MODE
8
6
µPD8255A
(Mode 1)
RD WR D7 - D0
PC
A0 - A1
CS
PA7 - PA0
PC4
PC5
PC6
PC7 INTR
µPD8748H/49H
Data Bus
Control Bus
Address Bus
Analog In
STB
A
PC3
IBF
A
2002 Microchip Technology Inc. DS21456B-page 19
TC7109/A
4.2 Handshake Mode
The Handshake mode provides an interface to a wide
variety of external devices. The byte enables may be
used as byte identification flags, or as load enables,
and external latches may be clocked by the rising edge
of CE/LOAD. A handshake interface to Intel®micropro-
cessors using an 8255 PPI is shown in Figure 4-5. The
handshake operation with the 8255 is controlled by
inverting its Input Buffer Full (IBF) flag to drive the
SEND input to the TC7109A, and using the CE/LOAD
to drive the 8255 strobe. The internal control register of
the PPI should be set in MODE 1 for the port used. If
the 8255 IBF flag is LOW and the TC7109A is in Hand-
shake mode, the next word will be strobed into the port.
The strobe will cause IBF to go HIGH (SEND goes
LOW), which will keep the enabled byte outputs active.
The PPI will generate an interrupt which, when exe-
cuted, will result in the data being read. The IBF will be
reset LOW when the byte is read, causing the
TC7109A to sequence into the next byte. The MODE
input to the TC7109A is connected to the controlline on
the PPI.
The data from every conversion will be sequenced in
two bytes in the system, if this output is left HIGH, or
tied HIGH separately. (The data access must take less
time than a conversion.) The output sequence can be
obtained on demand if this output is made to go from
LOW to HIGH and the interrupt may be used to reset
the MODE bit.
Conversions may be obtained on command under soft-
ware control by driving the RUN/HOLD input to the
TC7109A by a bit of the 8255. Another peripheral
devicemay be serviced by the unusedportof the8255.
The Handshake mode is particularly useful for directly
interfacing to industrystandard UARTs (such as Intersil
HD-6402), providing a means of serially transmitting
converted data with minimum component count.
A typical UART connection is shown in Figure 4-6. In
this circuit, any word received by the UART causes the
UART DR (Data Ready) output to goHIGH. The MODE
input to the TC7109A goes HIGH, triggering the
TC7109A into Handshake mode. The high order byte is
output to the UART and when the UART has trans-
ferred the data to the Transmitter register, TBRE
(SEND) goes HIGH again, LBEN will go HIGH, driving
the UART DRR (Data Ready Reset), which will signal
the end of the transfer of data from the TC7109A to the
UART.
An extension of the typical connection to several
TC7109A's with one UART is shown in Figure 4-7. In
this circuit, the word received by the UART (available at
the RBR outputs when DR is HIGH) is used to select
which converter will handshake with the UART. Up to
eight TC7109A's may interface with one UART, with no
external components. Up to 256 converters may be
accessed on one serial line with additional
components.
FIGURE 4-6: TC7109 TYPICAL UART INTERFACE
1
25
2
19
17
18
21
20
27
GND
BUFF OSC OUT
STATUS
HBEN
B
1
- B
8
TEST
LBEN
MODE
CE/LOAD
SEND
V+ 40
39
38
37
36
35
34
33
32
31
30
29
28
26
24
23
22
TC7109A
CLK
Q3
RESET
1
3
4
5–12
13
14
15
16
V
GND
RRD
RBR1–8
PE
FE
OE
SFD
RR1
TRO
TRC
RRC
EPE
CLS1
CLS2
SBS
PI
CRL
*TBR1–8
TRE
DRR
DR
TBRL
TBRE
MR
40
17
39
38
37
36
35
34
24
18
19
23
22
21
HD-640R
CMOS UART
+5V
GND
+5V
GND
25
Serial
Input
20
Serial
Output
15
1011
GND
GND
+5V
+5V
GND
+5V
-5V
+5V or Open
GND
3.58MHz
Crystal
Analog GND
External
Reference
+
+
–Input
C
AZ
0.33µF
C
INT
0.15µF
0.01µF
1MΩ
1µF
6
8
3–8
9–16
B
9
- B
12
,
POL, OR
26–33
For lowest power consumption, TBR1-TBR8 inputs should have 100kΩ pull-up resistors to +5V.
Send an
y
word to UART to transmit latest result.
R
INT
20kΩ
100kΩ
0.2V
REF
1V
REF
CD4060B
REF IN-
REF CAP-
REF CAP+
REF IN+
IN HI
IN LO
COM
INT
AZ
REF OUT
BUFF
V-
RUN/HOLD
OSC SEL
OSC OUT
OSC IN
8
–
*Note:
TC7109/A
DS21456B-page 20
2002 Microchip Technology Inc.
FIGURE 4-7: HANDSHAKE INTERFACE FOR MULTIPLEXED CONVERTERS
FIGURE 4-8:
TC7109A
B
9
- B
12
POL, OR
B
1
- B
8
LBENHBEN
8
6
Analog In
RUN/HOLD
SENDMODE CE/
LOAD
+5V
TC7109A
B
9
- B
12
POL, OR
B
1
- B
8
LBENHBEN
8
6
8-Bit Data Bus
Analog In
RUN/HOLD
SENDMODE CE/
LOAD
+5V
TC7109A
B
9
- B
12
POL, OR
B
1
- B
8
LBENHBEN
8
6
Analog In
RUN/HOLD
SENDMODE CE/
LOAD
+5V
TBRL DRR
GND
TBRE RBR1 - RBR8 SFD TBR1 - TBR8
Serial Output
Serial Input
6402 CMOS UART
23
40
1
17
V+
GND
TEST
RUN/HOLD
STATUS
LBEN
HBEN
39
38
37
36
35
34
33
32
31
30
29
28
27
25
24
23
22
21
TC7109A
1
4
5
6
7
10
9
11
25
26
39
40
20
T0
RESET
SS
INT
EA
WR
PSEN
ALE
PROG
V
DD
T1
V
CC
GND
P20 - P27
2
µPD8748H/49H
CMOS
Microcomputer
+5V
Other I/O
+5V
GND
-5V
GND
3.58MHz
Crystal
Analog
GND
External
Reference
+
+
–Input
C
AZ
0.33µF
R
INT
20k
10 k
Ω
Ω
0.2 V
REF
1 V
REF
XTAL2XTAL1
8
5
P14 - P17
P13
P12
P11
P10
DB0 - DB7
RD
30
29
28
27
B
9
- B
12
,
POL, OR
B
1
- B
8
CE/LOAD
21-24,
35-38
12-19
8
31-34
26
2
18
19
C
INT
0.15µF
0.01µF
1MΩ
1µF
GND
+5V
+5V
+5V
+5V
GND
23
6
8
3-8
9-16
20
REF IN-
REF CAP-
REF CAP+
REF IN+
IN HI
HI LO
COM
INT
AZ
BUFF
REF OUT
V-
OSC SEL
OSC OUT
OSC IN
SEND
BUFF OSC OUT
MODE
8
–
2002 Microchip Technology Inc. DS21456B-page 21
TC7109/A
5.0 INTEGRATING CONVERTER
FEATURES
The output of integrating ADCs represents the integral,
or average, of an input voltage over a fixed period of
time. Compared with techniques in which the input is
sampled and held, the integrating converter averages
the effects of noise. A second important characteristic
is that time is used to quantize the answer, resulting in
extremely small non-linearity errors and no missing
output codes. The integrating converter also has very
good rejection of frequencies whose periods are an
integral multiple of the measurement period. This fea-
ture can be used to advantage in reducing line
frequency noise (Figure 5-1).
FIGURE 5-1: NORMAL MODE
REJECTION OF DUAL
SLOPE CONVERTER AS
A FUNCTION OF
FREQUENCY
30
20
10
0
0.1/t 1/t 10/t
Input Frequenc
y
Normal Mode Rejection Plan
t = Measurement
Period
TC7109/A
DS21456B-page 22
2002 Microchip Technology Inc.
6.0 PACKAGING INFORMATION
6.1 Package Marking Information
Package marking data not available at this time.
6.2 Taping Form
Component Taping Orientation for 44-Pin PQFP Devices
User Direction of Feed
PIN 1
Standard Reel Component Orientation
for TR Suffix Device
W
P
Package Carrier Width (W) Pitch (P) Part Per Full Reel Reel Size
44-Pin PQFP 24 mm 16 mm 500 13 in
Carrier Tape, Number of Components Per Reel and Reel Size
Note: Drawing does not represent total number of pins.
PIN 1
Component Taping Orientation for 44-Pin PLCC Devices
User Direction of Feed
Standard Reel Component Orientation
for TR Suffix Device
Note: Drawing does not represent total number of pins.
W
P
Package Carrier Width (W) Pitch (P) Part Per Full Reel Reel Size
44-Pin PLCC 32 mm 24 mm 500 13 in
Carrier Tape, Number of Components Per Reel and Reel Size
2002 Microchip Technology Inc. DS21456B-page 23
TC7109/A
6.3 Package Dimensions
Dimension: inches (mm)
2.065 (52.45)
2.027 (51.49)
.200 (5.08)
.140 (3.56)
.150 (3.81)
.115 (2.92)
.070 (1.78)
.045 (1.14)
.022 (0.56)
.015 (0.38)
.110 (2.79)
.090 (2.29)
.555 (14.10)
.530 (13.46)
.610 (15.49)
.590 (14.99)
.015 (0.38)
.008 (0.20)
.700 (17.78)
.610 (15.50)
.040 (1.02)
.020 (0.51)
40-Pin PDIP (Wide) PIN 1
3° MIN.
Dimension: inches (mm)
.015 (0.38)
.008 (0.20)
.620 (15.75)
.590 (15.00)
.700 (17.78)
.620 (15.75)
.540 (13.72)
.510 (12.95)
2.070 (52.58)
2.030 (51.56)
.210 (5.33)
.170 (4.32)
.020 (0.51)
.016 (0.41)
.110 (2.79)
.090 (2.29)
.065 (1.65)
.045 (1.14)
.200 (5.08)
.125 (3.18)
.098 (2.49) MAX. .030 (0.76) MIN.
.060 (1.52)
.020 (0.51)
.150 (3.81)
MIN.
40-Pin CERDIP (Wide)
PIN 1
3° MIN.
TC7109/A
DS21456B-page 24
2002 Microchip Technology Inc.
6.3 Package Dimensions (Continued)
Dimension: inches (mm)
.557 (14.15)
.537 (13.65)
.398 (10.10)
.390 (9.90)
.031 (0.80) TYP.
.018 (0.45)
.012 (0.30) .398 (10.10)
.390 (9.90)
.010 (0.25) TYP.
.096
(
2.45
)
MAX.
.557 (14.15)
.537 (13.65)
.083 (2.10)
.075 (1.90)
.041 (1.03)
.026 (0.65)
7° MAX.
.009 (0.23)
.005 (0.13)
44-Pin PQFP
PIN 1
Dimension: inches (mm)
.695 (17.65)
.685 (17.40)
.656 (16.66)
.650 (16.51)
.656 (16.66)
.650 (16.51)
.021 (0.53)
.013 (0.33)
.032 (0.81)
.026 (0.66)
.630 (16.00)
.591 (15.00)
.120 (3.05)
.090 (2.29)
.180 (4.57)
.165 (4.19)
.695 (17.65)
.685 (17.40)
.050 (1.27) TYP.
.020 (0.51) MIN.
PIN 1
44-Pin PLCC
2002 Microchip Technology Inc. DS21456B-page 25
TC7109/A
NOTES:
TC7109/A
DS21456B-page 26
2002 Microchip Technology Inc.
SALES AND SUPPORT
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277
3. The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
2002 Microchip Technology Inc. DS21456B-page 27
TC7109/A
Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical com-
ponents in life support systems is not authorized except with
express written approval by Microchip. No licenses are con-
veyed, implicitly or otherwise, under any intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, FilterLab,
KEELOQ,microID,MPLAB,PIC,PICmicro,PICMASTER,
PICSTART, PRO MATE, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip Tech-
nologyIncorporated in the U.S.A. and other countries.
dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, microPort,
Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,
MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode
and Total Endurance are trademarks of Microchip Technology
Incorporated in the U.S.A.
Serialized Quick Turn Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2002, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999
and Mountain View, California in March 2002.
The Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro®8-bit MCUs, KEELOQ®code hopping
devices, Serial EEPROMs, microperipherals,
non-volatile memory and analog products. In
addition, Microchip’s quality system for the
design and manufacture of development
systems is ISO 9001 certified.
DS21456B-page 28
2002 Microchip Technology Inc.
AMERICAS
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200 Fax: 480-792-7277
Technical Support: 480-792-7627
Web Address: http://www.microchip.com
Rocky Mountain
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Tel: 480-792-7966 Fax: 480-792-7456
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Tel: 770-640-0034 Fax: 770-640-0307
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Tel: 630-285-0071 Fax: 630-285-0075
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Detroit
Tri-Atria Office Building
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Los Angeles
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Tel: 949-263-1888 Fax: 949-263-1338
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Microchip Technology Inc.
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Tel: 61-2-9868-6733 Fax: 61-2-9868-6755
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Tel: 86-10-85282100 Fax: 86-10-85282104
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Rm. 2401, 24th Floor,
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Tel: 86-28-6766200 Fax: 86-28-6766599
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Taiwan
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Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
EUROPE
Denmark
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Tel: 45 4420 9895 Fax: 45 4420 9910
France
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Germany
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Italy
Microchip Technology SRL
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Tel: 44 118 921 5869 Fax: 44-118 921-5820
03/01/02
*DS21456B*
WORLDWIDE SALES AND SERVICE
