SG
S
S S
D DD D
D DD D
S GS S
Gate
Source
BottomView
Drain
TopView
Qg GateCharge nC
0
1
4
7
0 5 10 15 20 25 30
VG GateVoltage V
G003
3
2
5
6
8
9
10
35
ID=25A
V =12.5V
DS
VGS GatetoSourceVoltage V
0
1
2
5
0 3 4 7 8 9 10
RDS(on) On-StateResistance mW
G006
5 61 2
6
4
3
TC=125 C°
TC=25 C°
ID=25A
CSD16321Q5C
www.ti.com
SLPS242B DECEMBER 2009REVISED MAY 2010
DualCool™ N-Channel NexFET™ Power MOSFETs
Check for Samples: CSD16321Q5C
1FEATURES PRODUCT SUMMARY
2 DualCool™ Package SON 5×6mm VDS Drain to Source Voltage 25 V
Optimized for Two Sided Cooling QgGate Charge Total (4.5V) 14 nC
Optimized for 5V Gate Drive Qgd Gate Charge Gate to Drain 2.5 nC
Ultralow Qgand Qgd VGS = 3V 2.8 m
RDS(on) Drain to Source On Resistance VGS = 4.5V 2.1 m
Low Thermal Resistance VGS = 8V 1.9 m
Avalanche Rated VGS(th) Threshold Voltage 1.1 V
Pb Free Terminal Plating
RoHS Compliant and Halogen Free ORDERING INFORMATION
Device Package Media Qty Ship
APPLICATIONS SON 5×6-mm Plastic 13-Inch Tape and
CSD16321Q5C 2500
Point-of-Load Synchronous Buck in Package Reel Reel
Networking, Telecom and Computing Systems
Optimized for Synchronous FET Applications ABSOLUTE MAXIMUM RATINGS
TA= 25°C unless otherwise stated VALUE UNIT
DESCRIPTION VDS Drain to Source Voltage 25 V
VGS Gate to Source Voltage +10 / –8 V
The NexFET™ power MOSFET has been designed Continuous Drain Current, TC= 25°C 100 A
to minimize losses in power conversion applications ID
and optimized for 5V gate drive applications. Continuous Drain Current(1) 31 A
IDM Pulsed Drain Current, TA= 25°C(2) 200 A
PDPower Dissipation(1) 3.1 W
TJ, Operating Junction and Storage –55 to 150 °C
TSTG Temperature Range
Avalanche Energy, single pulse
EAS 218 mJ
ID= 66A, L = 0.1mH, RG= 25
(1) Typical RqJA = 39°C/W on 1-in2Cu (2-oz.) on a 0.060" thick
FR4 PCB
(2) Pulse duration 300ms, duty cycle 2%
RDS(on) vs VGS Gate Charge
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2DualCool, NexFET are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Copyright © 2009–2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
CSD16321Q5C
SLPS242B DECEMBER 2009REVISED MAY 2010
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ELECTRICAL CHARACTERISTICS
(TA= 25°C unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Static Characteristics
BVDSS Drain to Source Voltage VGS = 0V, ID= 250mA 25 V
IDSS Drain to Source Leakage VGS = 0V, VDS = 20V 1 mA
IGSS Gate to Source Leakage VDS = 0V, VGS = +10/–8V 100 nA
VGS(th) Gate to Source Threshold Voltage VDS = VGS, ID= 250mA 0.9 1.1 1.4 V
VGS = 3V, ID= 25A 2.8 3.8 m
RDS(on) Drain to Source On Resistance VGS = 4.5V, ID= 25A 2.1 2.6 m
VGS = 8.0V, ID= 25A 1.9 2.4 m
gfs Transconductance VDS = 12.5V, ID= 25A 150 S
Dynamic Characteristics
Ciss Input Capacitance 2360 3100 pF
VGS = 0V, VDS = 12.5V,
Coss Output Capacitance 1700 2200 pF
f = 1MHz
Crss Reverse Transfer Capacitance 115 150 pF
RGSeries Gate Resistance 1.5 3
QgGate Charge Total (4.5V) 14 19 nC
Qgd Gate Charge Gate to Drain 2.5 nC
VDS = 12.5V,
IDS = 25A
Qgs Gate Charge Gate to Source 4 nC
Qg(th) Gate Charge at Vth 2.1 nC
Qoss Output Charge VDS = 13.3V, VGS = 0V 36 nC
td(on) Turn On Delay Time 9 ns
trRise Time 15 ns
VDS = 12.5V, VGS = 4.5V,
IDS = 25A, RG=2
td(off) Turn Off Delay Time 27 ns
tfFall Time 17 ns
Diode Characteristics
VSD Diode Forward Voltage IDS = 25A, VGS = 0V 0.8 1 V
Qrr Reverse Recovery Charge 33 nC
VDD = 13.3V, IF= 25A,
di/dt = 300A/ms
trr Reverse Recovery Time 32 ns
THERMAL CHARACTERISTICS
(TA= 25°C unless otherwise stated) PARAMETER MIN TYP MAX UNIT
RqJC Thermal Resistance Junction to Case (Top Source)(1) 1.2 °C/W
RqJC Thermal Resistance Junction to Case (Bottom drain)(1) 1.1 °C/W
RqJA Thermal Resistance Junction to Ambient(1)(2) 48 °C/W
(1) RqJC is determined with the device mounted on a 1-inch22-oz. Cu pad on a 1.5 × 1.5-inch 0.060-inch thick FR4 board. RqJC is specified
by design, whereas RqCA is determined by the user’s board design.
(2) Device mounted on FR4 material with 1-inch2of 2-oz. Cu.
2Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): CSD16321Q5C
GATE Source
DRAIN
N-Chan5x6QFNTTAMINRev3
M0137-02
GATE Source
DRAIN
N-Chan5x6QFNTTAMAXRev3
M0137-01
tP PulseDuration–s
ZqJA NormalizedThermalImpedance
G012
0.01
1
10
0.001
0.01 0.1 1 10 1000.001 1k
0.1
0.05
0.01
0.5
0.02
0.3
SinglePulse
DutyCycle=t /t
1 2
TypicalR JAq=93 C/W(minCu)
o
TJ=P xZq qJA JA
xR
t1
t2
P
0.1
CSD16321Q5C
www.ti.com
SLPS242B DECEMBER 2009REVISED MAY 2010
Max RqJA = 115°C/W
Max RqJA = 48°C/W when mounted on
when mounted on 1 in2minimum pad area of
of 2-oz. Cu. 2-oz.Cu.
Text and br Added for Spacing
Text and br Added for Spacing
Text and br Added for Spacing
Text and br Added for Spacing
TYPICAL MOSFET CHARACTERISTICS
(TA= 25°C unless otherwise stated)
Figure 1. Transient Thermal Impedance
Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): CSD16321Q5C
VDS DraintoSourceVoltage V
0
50
60
70
80
0.0 1.25 1.5
ID DrainCurrent A
G001
0.25 0.75
30
20
10
40
0.5 1
VGS =3V
VGS =2V
VGS =2.5V
VGS =8V
VGS =4.5V
VGS GatetoSourceVoltage V
20
40
60
70
1.5 1.75 2
ID DrainCurrent A
G002
80
1 1.25 2.5
0
10
30
50
2.25
VDS =5V
TC=125 C°
TC=25 C°
TC= −55 C°
Qg GateCharge nC
0
1
4
7
0 5 10 15 20 25 30
VG GateVoltage V
G003
3
2
5
6
8
9
10
35
ID=25A
V =12.5V
DS
VDS DraintoSourceVoltage V
0
1
2
3
4
5
0 5 10 15 20 25
C Capacitance nF
G004
6
Crss gd
=C
Coss ds gd
=C +C
Ciss sd gs
=C +C
f=1MHz
V =0V
GS
TC Case Temperature C°
0.2
0.4
0.6
1.0
1.4
−75 −25 25 75 125 175
VGS(th) ThresholdVoltage V
G005
0.8
1.2
ID=250 Am
0.0
VGS GatetoSourceVoltage V
0
1
2
5
0 3 4 7 8 9 10
RDS(on) On-StateResistance mW
G006
5 61 2
6
4
3
TC=125 C°
TC=25 C°
ID=25A
CSD16321Q5C
SLPS242B DECEMBER 2009REVISED MAY 2010
www.ti.com
TYPICAL MOSFET CHARACTERISTICS (continued)
(TA= 25°C unless otherwise stated)
TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING
Figure 2. Saturation Characteristics Figure 3. Transfer Characteristics
TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING
Figure 4. Gate Charge Figure 5. Capacitance
TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING
Figure 6. Threshold Voltage vs. Temperature Figure 7. On Resistance vs. Gate Voltage
4Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): CSD16321Q5C
TC Case Temperature C°
0.0
0.2
0.4
0.6
0.8
1.0
1.4
1.6
−75 −25 25 75 125 175
NormalizedOn-StateResistance
G007
ID
GS
=25A
V =4.5V
1.2
VD DrainVoltage V G009
1k
10
0.01
1
100
ID DrainCurrent A
0.1
0.01 0.1 10 1001
SinglePulse
Typical R =93 C/W(minCu)
qJA °
1ms
10ms
1s
DC
AreaLimited
byRDS(on)
100ms
t(AV) Timein Avalanche ms G010
10
1
100
I(AV) Peak AvalancheCurrent A
0.01 0.1 10 1001
1k
TC=25 C°
TC=125 C°
TC Case Temperature C°
0
20
40
80
60
120
−50 −25 0 25 50 75 100 125 150 175
ID DrainCurrent A
G011
100
CSD16321Q5C
www.ti.com
SLPS242B DECEMBER 2009REVISED MAY 2010
TYPICAL MOSFET CHARACTERISTICS (continued)
(TA= 25°C unless otherwise stated)
TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING
Figure 8. On Resistance vs. Temperature Figure 9. Typical Diode Forward Voltage
TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING
Figure 10. Maximum Safe Operating Area Figure 11. Single Pulse Unclamped Inductive Switching
TEXT ADDED FOR SPACING
Figure 12. Maximum Drain Current vs. Temperature
Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): CSD16321Q5C
M0162-01
E1
M
E
q
A
c
1234
5
6
7
8
L
K
b
M1
L
E1
e
E2
D2
TopView
Drain
iew
FrontView
SideView
1
2
3
4
5678
qc1N1
D1
N
Exposed
Pin9
BottomV
DualCool Pinout
TM
5,6,7,8
LabelPin#
Source1,2,3,9
Gate4
HeatSlug
CSD16321Q5C
SLPS242B DECEMBER 2009REVISED MAY 2010
www.ti.com
MECHANICAL DATA
Q5C Package Dimensions
MILLIMETERS INCHES
DIM MIN MAX MIN MAX
A 0.950 1.050 0.037 0.039
b 0.360 0.460 0.014 0.018
c 0.150 0.250 0.006 0.010
c1 0.150 0.250 0.006 0.010
D1 4.900 5.100 0.193 0.201
D2 4.320 4.520 0.170 0.178
E 4.900 5.100 0.193 0.201
E1 5.900 6.100 0.232 0.240
E2 3.920 4.12 0.154 0.162
e 1.27 TYP 0.050
L 0.510 0.710 0.020 0.028
q––––
K 0.760 0.030
M 3.260 3.460 0.128 0.136
M1 0.520 0.720 0.020 0.028
N 2.720 2.920 0.107 0.115
N1 1.227 1.427 0.048 0.056
6Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): CSD16321Q5C
F10
F11
F6 F7
F5
F9
F4
F8
14
5
8
M0139-01
F2
F3
F1
Ø 1.50 +0.10
–0.00
4.00 ±0.10 (See Note 1)
1.75 ±0.10
R 0.30 TYP
Ø 1.50 MIN
A0
K0
0.30 ±0.05
R 0.30 MAX
A0 = 6.50 ±0.10
B0 = 5.30 ±0.10
K0 = 1.40 ±0.10
M0138-01
2.00 ±0.05
8.00 ±0.10
B0
12.00 ±0.30
5.50 ±0.05
CSD16321Q5C
www.ti.com
SLPS242B DECEMBER 2009REVISED MAY 2010
MILLIMETERS INCHES
Recommended PCB Pattern DIM MIN MAX MIN MAX
F1 6.205 6.305 0.244 0.248
F2 4.46 4.56 0.176 0.18
F3 4.46 4.56 0.176 0.18
F4 0.65 0.7 0.026 0.028
F5 0.62 0.67 0.024 0.026
F6 0.63 0.68 0.025 0.027
F7 0.7 0.8 0.028 0.031
F8 0.65 0.7 0.026 0.028
F9 0.62 0.67 0.024 0.026
F10 4.9 5 0.193 0.197
F11 4.46 4.56 0.176 0.18
For recommended circuit layout for PCB designs, see application note SLPA005 Reducing Ringing Through
PCB Layout Techniques.
Q5C Tape and Reel Information
Notes:
1. 10-sprocket hole-pitch cumulative tolerance ±0.2
2. Camber not to exceed 1mm in 100mm, noncumulative over 250mm
3. Material: black static-dissipative polystyrene
4. All dimensions are in mm, unless otherwise specified.
5. A0 and B0 measured on a plane 0.3mm above the bottom of the pocket
6. MSL1 260°C (IR and convection) PbF reflow compatible
Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): CSD16321Q5C
CSD16321Q5C
SLPS242B DECEMBER 2009REVISED MAY 2010
www.ti.com
REVISION HISTORY
Changes from Original (December 2009) to Revision A Page
Changed the Mechanical Data dimensions table. Added dimensions for M, M1, N and N1 ................................................ 6
Changes from Revision A (January 2010) to Revision B Page
Changed RDS(on) - VGS = 3V, ID= 25A MAX value From: 3.5 To: 3.8 ................................................................................... 2
Deleted the Package Marking Information section ............................................................................................................... 7
8Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): CSD16321Q5C
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
CSD16321Q5C SON DQU 8 2500 330.0 12.8 6.5 5.3 1.4 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 21-Jan-2011
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CSD16321Q5C SON DQU 8 2500 335.0 335.0 32.0
PACKAGE MATERIALS INFORMATION
www.ti.com 21-Jan-2011
Pack Materials-Page 2
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