®
Data Device Corporation
105 Wilbur Place
Bohemia, New York 11716
631-567-5600 Fax: 631-567-7358
www.ddc-web.com
FOR MORE INFORMATION CONTACT:
Technical Support:
1-800-DDC-5757 ext. 7771
FEATURES
• Fully Integrated MIL-STD-1553
Interface Terminal
• Flexible Processor/Memory Interface
• Standard 4K x 16 RAM and Optional
12K x 16 or 8K x 17 RAM Available
• Optional RAM Parity Generation/
Checking
• Automatic BC Retries
• Programmable BC Gap Times
• BC Frame Auto-Repeat
• Flexible RT Data Buffering
• Programmable Illegalization
• Selective Message Monitor
• Simultaneous RT/Monitor Mode
DESCRIPTION
DDC's BU-65170, BU-61580 and BU-61585 Bus Controller / Remote
Terminal / Monitor Terminal (BC/RT/MT) Advanced Communication
Engine (ACE) terminals comprise a complete integrated interface
between a host processor and a MIL-STD-1553 A and B or STANAG
3838 bus.
The ACE series is packaged in a 1.9 -square-inch, 70-pin, low-profile,
cofired MultiChip Module (MCM) ceramic package that is well suited
for applications with stringent height requirements.
The BU-61585 ACE integrates dual transceiver, protocol, memory
management, processor interface logic, and a total of 12K words of
RAM in a choice of DIP or flat pack packages. The BU-61585 requires
+5 V power and either -15 V or -12 V power.
The BU-61585 internal RAM can be configured as 12K x 16 or 8K x
17. The 8K x 17 RAM feature provides capability for memory integrity
checking by implementing RAM parity generation and verification on
all accesses. To minimize board space and “glue” logic, the ACE pro-
vides ultimate flexibility in interfacing to a host processor and internal/
external RAM.
The advanced functional architecture of the ACE terminals provides
software compatibility to DDC's Advanced Integrated Multiplexer
(AIM) series hybrids, while incorporating a multiplicity of architectural
enhancements. It allows flexible operation while off-loading the host
processor, ensuring data sample consistency, and supports bulk data
transfers.The ACE hybrids may be operated at either 12 or 16 MHz.
Wire bond options allow for programmable RT address (hardwired is
standard) and external transmitter inhibit inputs.
BU-65170/61580 AND BU-61585
MIL-STD-1553A/B NOTICE 2 RT
AND BC/RT/MT, ADVANCED
COMMUNICATION ENGINE (ACE)
Make sure the next
Card you purchase
has...
© 1992, 1999 Data Device Corporation
All trademarks are the property of their respective owners.
2
Data Device Corporation
www.ddc-web.com
BU-65170/61580/61585
T-6/09-0
FIGURE 1. ACE BLOCK DIAGRAM
TRANSCEIVER
A
CH. A
TRANSCEIVER
B
CH. B
DUAL
ENCODER/DECODER,
MULTIPROTOCOL
AND
MEMORY
MANAGEMENT
RT ADDRESS
SHARED
RAM
ADDRESS BUS
PROCESSOR
AND
MEMORY
INTERFACE
LOGIC
DATA BUS D15-D0
A15-A0
DATA
BUFFERS
ADDRESS
BUFFERS
PROCESSOR
DATA BUS
PROCESSOR
ADDRESS BUS
MISCELLANEOUS
INCMD
CLK_IN, TAG_CLK,
MSTCLR,SSFLAG/EXT_TRG
RTAD4-RTAD0, RTADP
TRANSPARENT/BUFFERED, STRBD, SELECT,
RD/WR, MEM/REG, TRIGGER_SEL/MEMENA-IN,
MSB/LSB/DTGRT
IOEN, MEMENA-OUT, READYD
ADDR_LAT/MEMOE, ZERO_WAIT/MEMWR,
8/16-BIT/DTREQ, POLARITY_SEL/DTACK
INT
PROCESSOR
AND
MEMORY
CONTROL
INTERRUPT
REQUEST
TX/RX_A
TX/RX_A
TX/RX_B
TX/RX_B
*
* SEE ORDERING INFORMATION FOR AVAILABLE MEMORY
3
Data Device Corporation
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BU-65170/61580/61585
T-6/09-0
TABLE 1. “ACE” SERIES SPECIFICATIONS
PARAMETER MIN TYP MAX UNITS
ABSOLUTE MAXIMUM RATING
Supply Voltage
Logic +5V
Transceiver +5V
-15V
-12V
Logic
Voltage Input Range
-0.3
-0.3
-18.0
-18.0
-0.3
7.0
7.0
0.3
0.3
Vcc+0.3
V
V
V
V
V
RECEIVER
Differential Input Resistance
(BU-65170/61580/61585X1,
BU-65170/61580/61585X2)
(Notes 1-7)
(BU-65170/61580/61585X3,
BU-65170/61580/61585X6)
(Notes 1-7)
Differential Input Capacitance
(BU-65170/61580/61585X1,
BU-65170/61580/61585X2)
(Notes 1-7)
(BU-65170/61580/61585X3,
BU-65170/61580/61585X6)
(Notes 1-7)
Threshold Voltage, Transformer
Coupled, Measured on Stub
Common Mode Voltage (Note 7)
11
2.5
0.200
10
5
0.860
10
kΩ
kΩ
pF
pF
Vp-p
Vpeak
6
20
18
-250
100
7
150
9
27
27
10
250
300
Vp-p
Vp-p
Vp-p
mVp-p,
diff
mV
nsec
LOGIC
VIH
VIL
IIH (Vcc=5.5V, VIN=Vcc)
IIH (Vcc=5.5V, VIN=2.7V)
SSFLAG/EXT_TRIG
All Other Inputs
IIL (Vcc=5.5V, VIN=0.4V)
SSFLAG/EXT_TRIG
All Other Inputs
VOH (Vcc=4.5V, VIH=2.7V,
V
IL=0.2V, IOH=max)
VOL (Vcc=4.5V, VIH=2.7V,
V
IL=0.2V, IOL=max)
IOL
DB15-DB0, A15-A0, MEMOE/
ADDR_LAT, MEMWR/
ZEROWAIT, DTREQ/16/8,
DTACK/POLARITY_SEL
2.0
-10
-692
-346
-794
-397
2.4
6.4
0.8
10
-84
-42
-100
-50
0.4
V
V
µA
µA
µA
µA
µA
V
V
mA
V
V
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
5.5
5.5
-14.25
5.5
5.5
-11.4
5.5
5.25
190
60
108
160
255
190
60
120
185
305
160
265
370
580
240
60
108
160
255
4.5
4.5
-15.75
4.5
4.5
-12.6
4.5
4.75
POWER SUPPLY REQUIREMENTS
Voltages/Tolerances
BU-65170/61580/61585X1
• +5V (Logic)
• +5V (Ch. A, Ch. B)
• -15V (Ch. A, Ch. B)
BU-65170/61580/61585X2
• +5V (Logic)
• +5V (Ch. A, Ch. B)
• -12V (Ch. A, Ch. B)
BU-65170/61580/61585X3,
BU-65170/61580/61585X6
• +5V (Logic)
• +5V (Ch. A, Ch. B)
Current Drain (Total Hybrid)
BU-65170/61580X1
• +5V (Logic, Ch. A, Ch. B)
• -15V (Ch. A, Ch. B)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
BU-65170/61580X2
• +5V (Logic, Ch. A, Ch. B)
• -12V (Ch. A, Ch. B)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
BU-65170/61580X3,
BU-65170/61580X6
• +5V (Logic, Ch. A, Ch. B)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
BU-61585X1
• +5V (Logic, Ch. A, Ch. B)
• -15V (Ch. A, Ch. B)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
mA
mA
mA
pF
pF
-6.4
-3.2
50
50
3.2
UNITSMAXTYPMINPARAMETER
TABLE 1. “ACE” SERIES SPECIFICATIONS (CONTD)
TRANSMITTER
Differential Output Voltage
Direct Coupled Across 35 Ω,
Measured on Bus
Transformer Coupled Across
70 Ω, Measured on Bus
•(BU-65170/61580/61585X1)
•(BU-65170/61580/61585X2,X3, X6)
Output Noise, Differential (Direct
Coupled)
Output Offset Voltage, Transformer
Coupled Across 70 ohms
Rise/Fall Time
LOGIC (cont’d)
INCMD, INT MEMENA_OUT,
READYD, IOEN, TXA, TXA,
TXB, TXB, TX_INH_OUT_A,
TX_INH_OUT_B,
IOH
DB15-DB0, A15-A0, MEMOE/
ADDR_LAT, MEMWR/
ZEROWAIT, DTREQ/16/8,
DTACK/POLARITY_SEL
INCMD, INT, MEMENA_OUT,
READYD, IOEN, TXA, TXA,
TXB, TXB, TX_INH_OUT_A,
TX_INH_OUT_B,
CI (Input Capacitance)
CIO (Bi-directional signal input
capacitance)
5.0
5.0
-15.0
5.0
5.0
-12.0
5.0
5.0
95
30
68
105
180
95
30
80
130
230
116
222
328
540
105
30
68
105
180
4
Data Device Corporation
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BU-65170/61580/61585
T-6/09-0
mA
mA
mA
mA
mA
mA
mA
mA
mA
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
240
60
120
185
305
170
275
380
590
1.85
2.25
2.72
3.52
1.67
2.10
2.59
3.46
0.88
1.11
1.33
1.97
2.10
2.50
2.97
3.77
1.92
2.35
2.84
3.71
0.93
1.16
1.38
2.02
0.68
1.06
1.45
2.23
0.59
0.92
1.36
2.16
0.28
0.51
0.75
1.22
105
30
80
130
230
126
232
338
550
BU-61585X2
• +5V (Logic, Ch. A, Ch. B)
• -12V (Ch. A, Ch. B)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
BU-61585X3,
BU-61585X6
• +5V (Logic, Ch. A, Ch. B)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
POWER DISSIPATION
Total Hybrid
BU-65170/61580X1
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
BU-65170/61580X2
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
BU-65170/61580X3,
BU-65170/61580X6
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
BU-61585X1
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
BU-61585X2
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
BU-61585X3,
BU-61585X6
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
Hottest Die
BU-65170/61580X1
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
BU-65170/61580X2
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
BU-65170/61580X3,
BU-65170/61580X6
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
UNITSMAXTYPMINPARAMETER
TABLE 1. “ACE” SERIES SPECIFICATIONS (CONTD)
oz (g)0.6 (17)
in.
(mm)
in.
(mm)
W
W
W
W
W
W
W
W
W
W
W
W
1.9 X 1.0 X 0.165
(48.3 x 25.4 x 4.19)
1.9 X 1.0 X 0.150
(48.3 x 25.4 x 3.81)
PHYSICAL CHARACTERISTICS
Size
BU-65170/61580/61585 S
BU-65170/61580/61585 V
Weight
BU-65170/61580/61585 S/V
°C/W
°C/W
°C
°C
6.99
6.8
150
+300
-65
THERMAL
Thermal Resistance, Junction-to-Case,
Hottest Die (θJC)
BU-65170/61580/61585X1,
BU-65170/61580/61585X2,
BU-65170/61580/61585X3,
BU-65170/61580/61585X6
Storage Temperature
Lead Temperature (soldering, 10 sec.)
MHz
MHz
%
%
%
%
%
%
µs
µs
µs
µs
µs
µs
µs
µs
0.01
0.1
0.001
0.01
67
60
19.5
23.5
51.5
131
7
16.0
12.0
2.5
9.5
18.5
22.5
50.5
129.5
668
33
40
17.5
21.5
49.5
127
4
CLOCK INPUT
Frequency
Nominal Value (programmable)
• Default Mode
• Software Programmable Option
Long Term Tolerance
• 1553A Mode
• 1553B Mode
Short Term Tolerance, 1 second
• 1553A Mode
• 1553B Mode
Duty Cycle
• 16 MHz
• 12 MHz
1553 MESSAGE TIMING
Completion of CPU Write (BC Start)-
to-Start of Next Message
BC Intermessage Gap (Note 8)
BC/RT/MT Response Timeout (Note 9)
18.5 nominal
22.5 nominal
50.5 nominal
128.0 nominal
RT Response Timeout (Note 11)
Transmitter Watchdog Timeout
UNITSMAXTYPMINPARAMETER
0.68
1.06
1.45
2.23
0.59
0.92
1.36
2.16
0.28
0.51
0.75
1.22
0.335
0.600
0.860
1.385
0.290
0.590
0.890
1.490
0.18
0.42
0.66
1.14
BU-61585X1
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
BU-61585X2
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
BU-61585X3,
BU-61585X6
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
TABLE 1. “ACE” SERIES SPECIFICATIONS (CONTD)
0.850
1.195
1.450
1.975
0.835
1.135
1.435
2.035
0.64
0.93
1.22
1.81
0.900
1.245
1.500
2.025
0.885
1.185
1.485
2.085
0.69
0.98
1.27
1.86
0.335
0.600
0.860
1.385
0.290
0.590
0.890
1.490
0.18
0.42
0.66
1.14
5
Data Device Corporation
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BU-65170/61580/61585
T-6/09-0
INTRODUCTION
DDC's ACE series of Integrated BC/RT/MT hybrids provide a
complete, flexible interface between a microprocessor and a
MIL-STD-1553A, B Notice 2, McAir, or STANAG 3838 bus,
implementing Bus Controller, Remote Terminal (RT) and Monitor
Terminal (MT) modes. Packaged in a single 1.9-square-inch,
70-pin DIP or surface mountable flatpack or J-lead package, the
ACE series contains dual low-power transceivers and encoder/
decoders, complete BC/RT/MT multi-protocol logic, memory
management and interrupt logic, 4K x 16 of shared static RAM
and a direct, buffered interface to a host processor bus.
The BU-65170/61580 contains internal address latches and bidi-
rectional data buffers to provide a direct interface to a host pro-
cessor bus. The BU-65170/61580 may be interfaced directly to
both 16-bit and 8-bit microprocessors in a buffered shared RAM
configuration. In addition, the ACE may connect to a 16-bit pro-
cessor bus via a Direct Memory Access (DMA) interface. The
BU-65170/61580 includes 4K words of buffered RAM.
Alternatively, the ACE may be interfaced to as much as 64K
words of external RAM in either the shared RAM or DMA con-
figurations.
The ACE RT mode is multiprotocol, supporting MIL-STD-1553A,
MIL-STD-1553B Notice 2, STANAG 3838 (including EFAbus),
and the McAir A3818, A5232, and A5690 protocols. Full compli-
ance to the McAir specs, however, requires the use of a sinusoi-
dal transceiver (transceiver option 5). Refer to the BU-61590
data sheet for additional information on McAir terminals.
The memory management scheme for RT mode provides an
option for separation of broadcast data, in compliance with
1553B Notice 2. Both double buffer and circular buffer options
are programmable by subaddress. These features serve to
ensure data consistency and to off-load the host processor for
bulk data transfer applications.
The ACE series implements three monitor modes: a word moni-
tor, a selective message monitor, and a combined RT/selective
monitor. Other features include options for automatic retries and
programmable intermessage gap for BC mode, an internal Time
Tag Register, an Interrupt Status Register and internal command
illegalization for RT mode.
FUNCTIONAL OVERVIEW
TRANSCEIVERS
The transceivers in the BU-65170/61580X3(X6) are fully mono-
lithic, requiring only a +5 volt power input. Besides eliminating
the need for an additional power supply, the use of a 5 volt (only)
transceiver requires the use of step-up, rather than step-down,
isolation transformers. This provides the advantage of a higher
terminal input impedance than is possible for a 15 volt or 12 volt
transmitter. As a result, there is greater margin for the input
impedance test, mandated for 1553 validation testing. This
allows for longer cable lengths between an LRU's system con-
nector and the isolation transformers of an embedded 1553 ter-
minal.
For the +5 V and -15 V/-12 V front end, the BU-65170/
61580X1(X2) uses low-power bipolar analog monolithic and
thick-film hybrid technology. The transceiver requires +5 V and
-15 V (-12 V) only (requiring no +15 V/+12 V) and includes volt-
age source transmitters. The voltage source transmitters provide
superior line driving capability for long cables and heavy amounts
of bus loading. In addition, the monolithic transceivers in the
BU-65170/61580X1 provide a minimum stub voltage level of 20
volts peak-to-peak transformer coupled, making them suitable
for MIL-STD-1760 applications.
The receiver sections of the BU-65170/61580 are fully compliant
with MIL-STD-1553B in terms of front end overvoltage protec-
tion, threshold, common mode rejection, and word error rate. In
addition, the receiver filters have been designed for optimal
operation with the J´ chip's Manchester II decoders.
J´ DIGITAL MONOLITHIC
The J´ digital monolithic represents the cornerstone element of
the ACE family of terminals. The development of the J´ chip rep-
resents the fifth generation of 1553 protocol and interface design
for DDC. Over the years, DDC's 1553 protocol and interface
design has evolved from: (1) discrete component sets, consisting
of multiple hybrids (with large numbers of chips inside the indi-
vidual hybrids) and programmable logic devices, to (2) multiple
custom ASICs to perform the functions of encoder/decoder and
Notes for Table 1: Notes 1 through 6 are applicable to the Receiver
Differential Resistance and Differential Capacitance specifications:
(1) Specifications include both transmitter and receiver (tied together
internally).
(2) Measurement of impedance is directly between pins TX/RX A(B)
and TX/RX A(B) of the BU-65170/61580XX hybrid.
(3) Assuming the connection of all power and ground inputs to the
hybrid.
(4) The specifications are applicable for both unpowered and powered
conditions.
(5) The specifications assume a 2 volt rms balanced, differential, sinu-
soidal input. The applicable frequency range is 75 kHz to 1 MHz.
(6) Minimum resistance and Typical capacitance parameters are
guaranteed,but not tested, over the operating range.
(7) Assumes a common mode voltage within the frequency range of dc
to 2MHz, applied to pins of the isolation transformer on the stub
side (either direct or transformer coupled), referenced to hybrid
ground. Use a DDC recommended transformer or other transformer
that provides an equivalent minimum CMRR.
(8) Typical value for minimum intermessage gap time. Under software
control, may be lengthened to (65,535µs minus message time), in
increments of 1µs.
(9) Software programmable (4 options). Includes RT-to-RT Timeout
(Mid-Parity of Transmit Command to Mid-Sync of Transmitting RT
Status).
(10) For both +5V logic and transceiver. +5V for channels A and B.
(11) Measured from mid-parity crossing of Command Word to mid-sync
crossing of RT's Status Word.
(12) Specifications for BU-65171, BU-61581, and BU-61586 are identi-
cal to the specifications for the BU-65170, BU-61580, and
BU-61585 respectively.
6
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BU-65170/61580/61585
T-6/09-0
RT protocol within a single hybrid, to (3) the BUS-61553
Advanced Integrated Mux Hybrid (AIM-HY) series, containing, in
addition to a dual monolithic/thick-film transceiver and discrete
RAM chips, a custom protocol chip and a separate custom
memory management/processor interface chip, to (4) the BUS-
61559 Advanced Integrated Mux Hybrids with Enhanced RT
Features (AIM-HY'er — the AIM-HY'er series includes memory
management and processor interface functions beyond those of
the AIM-HY series) , to (5) the full integration of the J´ chip.
The J´ chip consists of a dual encoder/decoder, complete proto-
col for Bus Controller (BC), 1553A/B/McAir Remote Terminal
(RT), and Monitor (MT) modes; memory management and inter-
rupt logic; a flexible, buffered interface to a host processor bus
and optional external RAM; and 4K words of on-chip RAM.
Reference the region within the dotted line of FIGURE 1. Besides
realizing all the protocol, memory management, and interface
functions of the earlier AIM-HY'er series, the J´ chip includes a
large number of enhancements to facilitate hardware and soft-
ware design, and to further off-load the 1553 terminal's host
processor.
DECODERS
The default mode of operation for the BU-65170 RT and
BU-61580 BC/RT/MT requires a 16 MHz clock input. If needed,
a software programmable option allows the device to be operat-
ed from a 12 MHz clock input. Most current 1553 decoders
sample using a 10 MHz or 12 MHz clock. In the 16 MHz mode
(default following a hardware or software reset), the ACE decod-
ers sample 1553 serial data using the 16 MHz clock. In the 12
MHz mode, the decoders sample using both clock edges; this
provides a sampling rate of 24 MHz. The faster sampling rate for
the J´ chip’s Manchester II decoders provides superior perfor-
mance in terms of bit error rate and zero-crossing distortion tol-
erance.
For interfacing to fiber optic transceivers for MIL-STD-1773 appli-
cations, a transceiverless version of the J´ chip, the BU-65620,
can be used. These versions provide a pin-programmable option
for a direct interface to the single-ended outputs of a fiber optic
receiver. No external logic is needed.
TIME TAGGING
The ACE includes an internal read/writable Time Tag Register.
This register is a CPU read/writable 16-bit counter with a pro-
grammable resolution of either 2, 4, 8, 16, 32, or 64 µs per LSB.
Also, the Time Tag Register may be clocked from an external
oscillator. Another option allows software-controlled increment-
ing of the Time Tag Register. This supports self-testing for the
Time Tag Register. For each message processed, the value of
the Time Tag register is loaded into the second location of the
respective descriptor stack entry (“TIME TAG WORD”) for both
BC and RT modes.
Additional provided options will: clear the Time Tag Register fol-
lowing a Synchronize (without data) mode command or load the
Time Tag Register following a Synchronize (with data) mode
command; enable an interrupt request and a bit setting in the
Interrupt Status Register when the Time Tag Register rolls over
from 0000 to FFFF. Assuming the Time Tag Register is not
loaded or reset, this will occur at approximately 4-second time
intervals, for 64 µs/LSB resolution, down to 131 ms intervals, for
2 µs/LSB resolution.
Another programmable option for RT mode is the automatic
clearing of the Service Request Status Word bit following the
ACE's response to a Transmit Vector Word mode command.
INTERRUPTS
The ACE series components provide many programmable
options for interrupt generation and handling. The interrupt out-
put pin (INT) has three software programmable modes of opera-
tion: a pulse, a level output cleared under software control, or a
level output automatically cleared following a read of the Interrupt
Status Register.
Individual interrupts are enabled by the Interrupt Mask Register.
The host processor may easily determine the cause of the inter-
rupt by using the Interrupt Status Register. The Interrupt Status
Register provides the current state of the interrupt conditions.
The Interrupt Status Register may be updated in two ways. In the
standard interrupt handling mode, a particular bit in the Interrupt
Status Register will be updated only if the condition exists and
the corresponding bit in the Interrupt Mask Register is enabled.
In the enhanced interrupt handling mode, a particular bit in the
Interrupt Status Register will be updated if the condition exists
regardless of the contents of the corresponding Interrupt Mask
Register bit. In any case, the respective Interrupt Mask Register
bit enables an interrupt for a particular condition.
ADDRESSING, INTERNAL REGISTERS, AND
MEMORY MANAGEMENT
The software interface of the BU-65170/61580 to the host pro-
cessor consists of 17 internal operational registers for normal
operation, an additional 8 test registers, plus 64K x 16 of shared
memory address space. The BU-65170/61580's 4K x 16 of inter-
nal RAM resides in this address space. Reference TABLE 2 and
24.
Definition of the address mapping and accessibility for the ACE's
17 non-test registers, and the test registers, is as follows:
Interrupt Mask Register is used to enable and disable interrupt
requests for various conditions.
Configuration Registers #1 and #2 are used to select the
BU-61580's mode of operation, and for software control of RT
Status Word bits, Active Memory Area, BC Stop-on-Error, RT
Memory Management mode selection, and control of the Time
Tag operation.
Start/Reset Register is used for “command” type functions,
such as software reset, BC/MT Start, Interrupt Reset, Time Tag
Reset, and Time Tag Register Test. The Start/Reset Register
includes provisions for stopping the BC in its auto-repeat mode,
either at the end of the current message or at the end of the cur-
rent BC frame.
7
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BC/RT Command Stack Pointer Register allows the host CPU
to determine the pointer location for the current or most recent
message when the BU-61580 is in BC or RT modes.
BC Control Word/RT Subaddress Control Word Register: In
BC mode, it allows host access to the current, or most recent BC
Control Word. The BC Control Word contains bits that select the
active bus and message format, enable off-line self-test, mask-
ing of Status Word bits, enable retries and interrupts, and speci-
fy MIL-STD-1553A or -1553B error handling. In RT mode, this
register allows host access to the current or most recent
Subaddress Control Word. The Subaddress Control Word is
used to select the memory management scheme and enable
interrupts for the current message. The read/write accessibility
can be used as an aid for testing the ACE.
Time Tag Register maintains the value of a real-time clock. The resolu-
tion of this register is programmable from among 2, 4, 8, 16, 32, and 64
µs/LSB. The TAG_CLK input signal also may cause an external oscillator
to clock the Time Tag Register. Start-of-Message (SOM) and End-of-
Message (EOM) sequences in BC, RT, and Message Monitor modes
cause a write of the current value of the Time Tag Register to the stack
area of RAM.
Interrupt Status Register mirrors the Interrupt Mask Register and con-
tains a Master Interrupt bit. It allows the host processor to determine the
cause of an interrupt request by means of a single READ operation.
Configuration Registers #3, #4, and #5 are used to enable many of the
BU-61580's advanced features. These include all the enhanced mode
features; that is, all the functionality beyond that of the previous genera-
tion product, the BUS-61559 Advanced Integrated Mux Hybrid with
Enhanced RT Features (AIM-HY'er). For all three modes, use of the
Enhanced Mode enables the various read-only bits in Configuration
Register #1. For BC mode, the enhanced mode features include the
expanded BC Control Word and BC Block Status Word, additional Stop-
On-Error and Stop-On-Status Set functions, frame auto-repeat, pro-
grammable intermessage gap times, automatic retries, expanded Status
Word Masking, and the capability to generate interrupts following the
completion of any selected message. For RT mode, the enhanced mode
features include the expanded RT Block Status Word, the combined RT/
Selective Message Monitor mode, internal wrapping of the RTFAIL out-
put signal (from the J´ chip) to the RTFLAG RT Status Word bit, the
double buffering scheme for individual receive (broadcast) subaddress-
es, and the alternate (fully software programmable) RT Status Word. For
MT mode, use of the enhanced mode enables use of the Selective
Message Monitor, the combined RT/Selective Monitor modes, and the
monitor triggering capability.
Data Stack Address Register is used to point to the current address
location in shared RAM used for storing message words (second
Command Words, Data Words, RT Status Words) in the Selective Word
Monitor mode.
Frame Time Remaining Register provides a read only indication of the
time remaining in the current BC frame. The resolution of this register is
100 µs/LSB.
Message Time Remaining Register provides a read only indication of
the time remaining before the start of the next message in a BC frame.
The resolution of this register is 1 µs/LSB.
BC Frame/RT Last Command/MT Trigger Word Register: In BC
mode, it programs the BC frame time, for use in the frame auto-repeat
mode. The resolution of this register is 100 µs/LSB, with a range of 6.55
seconds; in RT mode, this register stores the current (or most previous)
1553 Command Word processed by the ACE RT; in the Word Monitor
mode, this register specifies a 16-bit Trigger (Command) Word. The
Trigger Word may be used to start or stop the monitor, or to generate
interrupts.
Status Word Register and BIT Word Registers provide read-only
indications of the BU-65170/61580's RT Status and BIT Words.
Test Mode Registers 0-7: These registers may be used to facilitate
production or maintenance testing of the BU-65170/61580 and systems
incorporating the BU-65170/61580.
TABLE 2. ADDRESS MAPPING
ADDRESS LINES REGISTER
DESCRIPTION/ACCESSIBILITY
HEX A4 A3 A2 A1 A0
00 0 0 0 0 0 Interrupt Mask Register (RD/WR)
01 0 0 0 0 1 Configuration Register #1 (RD/WR)
02 0 0 0 1 0 Configuration Register #2 (RD/WR)
03 0 0 0 1 1 Start/Reset Register (WR)
03 0 0 0 1 1 BC/RT Command Stack Pointer Register
(RD)
04 0 0 1 0 0 BC Control Word*/RT Subaddress Control
Word Register (RD/WR)
05 0 0 1 0 1 Time Tag Register (RD/WR)
06 0 0 1 1 0 Interrupt Status Register (RD)
07 0 0 1 1 1 Configuration Register #3 (RD/WR)
08 0 1 0 0 0 Configuration Register #4 (RD/WR)
09 0 1 0 0 1 Configuration Register #5 (RD/WR)
0A 0 1 0 1 0 Data Stack Address Register (RD)*
0B 0 1 0 1 1 BC Frame Time Remaining Register (RD)*
0C 0 1 1 0 0 BC Time Remaining to Next Message
Register (RD)*
0D 0 1 1 0 1 BC Frame Time*/RT Last Command/MT
Trigger Word* Register (RD/WR)
0E 0 1 1 1 0 RT Status Word Register (RD)
0F 0 1 1 1 1 RT BIT Word Register (RD)
10 1 000 0 Test Mode Register 0
•
•
17 1 0 1 1 1 Test Mode Register 7
18 1 1 0 0 0 reserved
•
•
1F 1 1 1 1 1 reserved
* Not applicable to BU-65170/61571
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TABLE 3. INTERRUPT MASK REGISTER (READ/WRITE 00h)
BIT DESCRIPTION
15(MSB) RESERVED
14 RAM PARITY ERROR
13 BC/RT TRANSMITTER TIMEOUT
12 BC/RT COMMAND STACK ROLLOVER
11 MT COMMAND STACK ROLLOVER
10 MT DATA STACK ROLLOVER
9 HS FAIL
8 BC RETRY
7 RT ADDRESS PARITY ERROR
6 TIME TAG ROLLOVER
5 RT CIRCULAR BUFFER ROLLOVER
4BC CONTROL WORD/RT SUBADDRESS CONTROL WORD EOM
3 BC END OF FRAME
2FORMAT ERROR
1BC STATUS SET/RT MODE CODE/MT PATTERN TRIGGER
0(LSB) END OF MESSAGE
TABLE 4. CONFIGURATION REGISTER #1 (READ/WRITE 01H)
BIT BC FUNCTION (Bits
11-0 Enhanced Mode Only)
RT WITHOUT ALTERNATE
STATUS
RT WITH ALTERNATE
STATUS (Enhanced Only)
MONITOR FUNCTION
(Enhanced mode only bits 12-0)
15 (MSB) RT/BC-MT (logic 0) (logic 1) (logic 1) (logic 0)
14 MT/BC-RT (logic 0) (logic 0) (logic 0) (logic 1)
13 CURRENT AREA B/A CURRENT AREA B/A CURRENT AREA A/B CURRENT AREA B/A
12 MESSAGE STOP-ON-ERROR MESSAGE MONITOR ENABLED
(MMT)
MESSAGE MONITOR
ENABLED (MMT)
MESSAGE MONITOR ENABLED
(MMT)
11 FRAME STOP-ON-ERROR S10 TRIGGER ENABLED WORD
10 STATUS SET STOP-ON-MESSAGE BUSY S09 START-ON-TRIGGER
9 STATUS SET STOP-ON-FRAME SERVICE REQUEST S08 STOP-ON-TRIGGER
8 FRAME AUTO-REPEAT SUBSYSTEM FLAG S07 NOT USED
7 EXTERNAL TRIGGER ENABLED RTFLAG (Enhanced Mode Only) S06 EXTERNAL TRIGGER ENABLED
6 INTERNAL TRIGGER ENABLED NOT USED S05 NOT USED
5 INTERMESSAGE GAP TIMER
ENABLED
NOT USED S04 NOT USED
4 RETRY ENABLED NOT USED S03 NOT USED
3DOUBLED/SINGLE RETRY NOT USED S02 NOT USED
2 BC ENABLED (Read Only) NOT USED S01 MONITOR ENABLED(Read Only)
1 BC FRAME IN PROGRESS (Read
Only)
NOT USED S00 MONITOR TRIGGERED
(Read Only)
0 (LSB) BC MESSAGE IN PROGRESS
(Read Only)
RT MESSAGE IN PROGRESS
(Enhanced mode only,Read Only)
RT MESSAGE IN
PROGRESS (Read Only)
MONITOR ACTIVE
(Read Only)
DYNAMIC BUS CONTROL
ACCEPTANCE
SEPARATE BROADCAST DATA0(LSB)
ENHANCED RT MEMORY MANAGEMENT1
CLEAR SERVICE REQUEST2
LEVEL/PULSE INTERRUPT REQUEST
3
INTERRUPT STATUS AUTO CLEAR4
LOAD TIME TAG ON SYNCHRONIZE5
CLEAR TIME TAG ON SYNCHRONIZE6
TIME TAG RESOLUTION 0 (TTR0)7
TIME TAG RESOLUTION 1 (TTR1)8
TIME TAG RESOLUTION 2(TTR2)9
256-WORD BOUNDARY DISABLE10
OVERWRITE INVALID DATA11
RX SA DOUBLE BUFFER ENABLE12
BUSY LOOKUP TABLE ENABLE
13
RAM PARITY ENABLE (BU-61585/6 AND BU-65621 ONLY)
14
ENHANCED INTERRUPTS
15(MSB)
DESCRIPTIONBIT
TABLE 5. CONFIGURATION REGISTER #2 (READ/WRITE 02h)
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TABLE 6. START/RESET REGISTER (WRITE 03H)
BIT DESCRIPTION
15(MSB) RESERVED
• •
• •
• •
7 RESERVED
6 BC/MT STOP-ON-MESSAGE
5 BC STOP-ON-FRAME
4 TIME TAG TEST CLOCK
3 TIME TAG RESET
2 INTERRUPT RESET
1 BC/MT START
0(LSB) RESET
COMMAND STACK POINTER 00(LSB)
• •
• •
• •
COMMAND STACK POINTER 15
15(MSB)
DESCRIPTIONBIT
TABLE 7. BC/RT COMMAND STACK POINTER REG. (READ 03H)
RT-RT FORMAT
BROADCAST FORMAT
MODE CODE FORMAT
1553A/B SELECT
0(LSB)
1
2
3
EOM INTERRUPT ENABLE4
MASK BROADCAST BIT5
OFF LINE SELF TEST6
BUS CHANNEL A/B7
RETRY ENABLED8
RESERVED BITS MASK9
SUBSYS FLAG BIT MASK
TERMINAL FLAG BIT MASK
11
10
SUBSYS BUSY BIT MASK12
SERVICE REQUEST BIT MASK13
M.E. MASK14
RESERVED
15(MSB)
DESCRIPTIONBIT
TABLE 8. BC CONTROL WORD REGISTER
READ/WRITE 04H, (BU-61580 ONLY)
BCST: MEMORY MANAGEMENT 0 (MM0)0(LSB)
BCST: MEMORY MANAGEMENT 1 (MM1)1
BCST:MEMORY MANAGEMENT 2 (MM2)2
TX: MEMORY MANAGEMENT 1 (MM1)
BCST: CIRC BUF INT3
BCST: EOM INT4
RX: MEMORY MANAGEMENT 0 (MM0)5
RX: MEMORY MANAGEMENT 1 (MM1)6
RX: MEMORY MANAGEMENT 2 (MM2)7
RX: CIRC BUF INT8
RX: EOM INT9
TX: MEMORY MANAGEMENT 0 (MM0)10
TX: MEMORY MANAGEMENT 2 (MM2)12
TX: CIRC BUF INT13
TX: EOM INT14
RX: DOUBLE BUFFER ENABLE
15(MSB)
DESCRIPTIONBIT
11
TABLE 9. RT SUBADDRESS CONTROL WORD
(READ/WRITE 04H)
TIME TAG 00(LSB)
• •
• •
• •
TIME TAG 15
15(MSB)
DESCRIPTIONBIT
TABLE 10. TIME TAG REGISTER (READ/WRITE 05H)
END OF MESSAGE0(LSB)
BC STATUS SET/RT MODE CODE/MT PATTERN
TRIGGER
1
FORMAT ERROR2
MT COMMAND STACK ROLLOVER
BC END OF FRAME3
BC CONTROL WORD/RT SUBADDRESS CONTROL WORD EOM
4
RT CIRCULAR BUFFER ROLLOVER5
TIME TAG ROLLOVER6
RT ADDRESS PARITY ERROR7
BC RETRY8
HS FAIL9
MT DATA STACK ROLLOVER10
BC/RT COMMAND STACK ROLLOVER12
BC/RT TRANSMITTER TIMEOUT13
RAM PARITY ERROR14
MASTER INTERRUPT
15(MSB)
DESCRIPTIONBIT
11
TABLE 11. INTERRUPT STATUS REGISTER (READ 06H)
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ENHANCED MODE CODE HANDLING0(LSB)
1553A MODE CODES ENABLE1
RTFAIL-FLAG WRAP ENABLE2
MT COMMAND STACK SIZE 0
BUSY RX TRANSFER DISABLE3
ILLEGAL RX TRANSFER DISABLE4
ALTERNATE STATUS WORD ENABLE
5
OVERRIDE MODE T/R ERROR6
ILLEGALIZATION DISABLED7
MT DATA STACK SIZE 08
MT DATA STACK SIZE 19
MT DATA STACK SIZE 210
MT COMMAND STACK SIZE 112
BC/RT COMMAND STACK SIZE 013
BC/RT COMMAND STACK SIZE 114
ENHANCED MODE ENABLE
15(MSB)
DESCRIPTIONBIT
11
TABLE 12. CONFIGURATION REGISTER #3 (READ/WRITE 07H)
TEST MODE 00(LSB)
TEST MODE 11
TEST MODE 22
BROADCAST MASK ENABLE/XOR
LATCH RT ADRRESS WITH CONFIG #53
MT TAG GAP OPTION4
VALID BUSY/NO DATA5
VALID M.E./NO DATA6
2ND RETRY ALT/SAME BUS7
1ST RETRY ALT/SAME BUS8
RETRY IF STATUS SET9
RETRY IF -A AND M.E.10
EXPANDED BC CONTROL WORD ENABLE12
MODE COMMAND OVERRIDE BUSY13
INHIBIT BIT WORD IF BUSY14
EXTERNAL BIT WORD ENABLE
15(MSB)
DESCRIPTIONBIT
11
TABLE 13. CONFIGURATION REGISTER #4 (READ/WRITE 08H)
RT ADDRESS PARITY0(LSB)
RT ADDRESS 01
RT ADDRESS 12
EXPANDED CROSSING ENABLED
RT ADDRESS 23
RT ADDRESS 34
RT ADDRESS 45
RT ADDRESS LATCH/TRANSPARENT (see NOTE)6
BROADCAST DISABLED7
GAP CHECK ENABLED8
RESPONSE TIMEOUT SELECT 09
RESPONSE TIMEOUT SELECT 110
EXTERNAL TX INHIBIT B, read only BU-65170/61580X612
EXTERNAL TX INHIBIT A, read only BU-65170/61580X613
LOGIC “0”14
12MHZ CLOCK SELECT
15(MSB)
DESCRIPTIONBIT
11
TABLE 14. CONFIGURATION REGISTER #5 (READ/WRITE 09H)
Notes for TABLE 14: Read only, logic “0” for 65170/61580, logic “1” for
65171/61581/61586.
MONITOR DATA STACK ADDRESS 00(LSB)
• •
• •
• •
MONITOR DATA STACK ADDRESS 15
15(MSB)
DESCRIPTIONBIT
TABLE 15. MONITOR DATA STACK ADDRESS REGISTER
(READ/WRITE 0AH)
BC FRAME TIME REMAINING 00(LSB)
• •
• •
• •
BC FRAME TIME REMAINING 15
15(MSB)
DESCRIPTIONBIT
TABLE 16. BC FRAME TIME REMAINING REGISTER
(READ/WRITE 0BH)
Note: resolution = 1 µs per LSB
BC MESSAGE TIME REMAINING 00(LSB)
• •
• •
• •
BC MESSAGE TIME REMAINING 15
15(MSB)
DESCRIPTION
BIT
TABLE 17. BC MESSAGE TIME REMAINING REGISTER
(READ/WRITE 0CH)
Note: resolution = 1 µs per LSB
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BIT 00(LSB)
• •
• •
• •
BIT 15
15(MSB)
DESCRIPTIONBIT
TABLE 18. BC FRAME TIME/RT LAST COMMAND/T TRIGGER
REGISTER (READ/WRITE 0DH)
TABLE 19. RT STATUS WORD REGISTER (READ/WRITE 0EH)
11
BIT DESCRIPTION
15(MSB) LOGIC “0”
12 LOGIC “0”
14 LOGIC “0”
13 LOGIC “0”
10 MESSAGE ERROR
9 INSTRUMENTATION
8 SERVICE REQUEST
7 RESERVED
6 RESERVED
5 RESERVED
4 BROADCAST COMMAND RECEIVED
3 BUSY
LOGIC “0”
2 SUBSYSTEM FLAG
1 DYNAMIC BUS CONTROL ACCEPT
0(LSB) TERMINAL FLAG
COMMAND WORD CONTENTS ERROR0(LSB)
RT-RT 2ND COMMAND WORD ERROR1
RT-RT NO RESPONSE ERROR2
TRANSMITTER SHUTDOWN B
RT-RT GAP/SYNCH/ADDRESS ERROR3
PARITY/MANCHESTER ERROR RECEIVED
4
INCORRECT SYNC RECEIVED5
LOW WORD COUNT6
HIGH WORD COUNT7
CHANNEL B/A8
TERMINAL FLAG INHIBITED
9
TRANSMITTER SHUTDOWN A
10
HANDSHAKE FAILURE12
LOOP TEST FAILURE A13
LOOP TEST FAILURE B14
TRANSMITTER TIMEOUT
15(MSB)
DESCRIPTIONBIT
11
TABLE 20. RT BIT WORD REGISTER (READ 0FH)
INVALID WORD0(LSB)
INCORRECT SYNC TYPE1
WORD COUNT ERROR2
STATUS SET
WRONG STATUS ADDRESS/NO GAP3
GOOD DATA BLOCK TRANSFER4
RETRY COUNT 05
RETRY COUNT 16
MASKED STATUS SET7
LOOP TEST FAIL8
NO RESPONSE TIMEOUT9
FORMAT ERROR 10
ERROR FLAG12
CHANNEL B/A13
SOM14
EOM
15(MSB)
DESCRIPTIONBIT
11
TABLE 21. BC MODE BLOCK STATUS WORD
NOTE:
TABLES 21 TO 24 ARE NOT REGISTERS, BUT
THEY ARE WORDS STORED IN RAM.
COMMAND WORD CONTENTS ERROR0(LSB)
RT-RT 2ND COMMAND ERROR1
RT-RT GAP/SYNC/ADDRESS ERROR2
RT-RT FORMAT
INVALID WORD3
INCORRECT SYNC4
WORD COUNT ERROR5
ILLEGAL COMMAND WORD
6
DATA STACK ROLLOVER7
LOOP TEST FAIL8
NO RESPONSE TIMEOUT9
FORMAT ERROR 10
ERROR FLAG12
CHANNEL B/A
13
SOM14
EOM
15(MSB)
DESCRIPTIONBIT
11
TABLE 22. RT MODE BLOCK STATUS WORD
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GAP TIME
MODE CODE
0(LSB)
CONTIGUOUS DATA/GAP1
CHANNEL B/A2
COMMAND/DATA3
ERROR4
BROADCAST5
THIS RT6
WORD FLAG7
• •
• •
• •
GAP TIME
15(MSB)
DESCRIPTION
BIT
8
TABLE 23. WORD MONITOR IDENTIFICATION WORD
RT-RT 2ND COMMAND ERROR1
RT-RT GAP/SYNC/ADDRESS ERROR2
RT-RT TRANSFER
INVALID WORD3
INCORRECT SYNC4
WORD COUNT ERROR5
RESERVED6
DATA STACK ROLLOVER
7
GOOD DATA BLOCK TRANSFER8
NO RESPONSE TIMEOUT9
FORMAT ERROR 10
ERROR FLAG12
CHANNEL B/A13
SOM14
EOM
15(MSB)
DESCRIPTIONBIT
11
TABLE 24. MESSAGE MONITOR MODE BLOCK STATUS WORD
BUS CONTROLLER (BC) ARCHITECTURE
The BC protocol of the BU-61580 implements all MIL-STD-
1553B message formats. Message format is programmable on a
message-by-message basis by means of bits in the BC Control
Word and the T/R bit of the Command Word for the respective
message. The BC Control Word allows 1553 message format,
1553A/B type RT, bus channel, self-test, and Status Word mask-
ing to be specified on an individual message basis. In addition,
automatic retries and/or interrupt requests may be enabled or
disabled for individual messages. The BC performs all error
checking required by MIL-STD-1553B. This includes validation of
response time, sync type and sync encoding, Manchester II
encoding, parity, bit count, word count, Status Word RT Address
field, and various RT-to-RT transfer errors. The BU-61580's BC
response timeout value is programmable with choices of 18, 22,
50, and 130 µs. The longer response timeout values enable
operation over long buses and/or the use of repeaters.
FIGURE 2 illustrates BC intermessage gap and frame timing.
The BU-61580 may be programmed to process BC frames of up
to 512 messages with no processor intervention. It is possible to
program for either single frame or frame auto-repeat operation.
In the auto-repeat mode, the frame repetition rate may be con-
trolled either internally, using a programmable BC frame timer, or
from an external trigger input. The internal BC frame time is pro-
grammable up to 6.55 seconds in increments of 100 µs. In addi-
tion to BC frame time, intermessage gap time, measured from
the start of the current message to the start of the subsequent
message, is programmable on an individual message basis. The
time between individual successive messages is programmable
up to 65.5 ms, in increments of 1 µs.
Stack B
Not Used
Message Block 93
0F00-0FFF
0EFC-0EFF
0ED6-0EFB
••
••
Initial Message Count A (see note)
(Auto-Frame Repeat Mode)
••
Message Block 2
0154-0179
Message Block 1
012E-0153
Message Block 0
0108-012D
Initial Message Count B (see note)
(Auto-Frame Repeat Mode)
0107
Initail Stack Pointer B (see note)
(Auto-Frame Repeat Mode)
0106
Message Count B0105
Stack Pointer B0104
Initial Stack Pointer A (see note) (Auto-Frame Repeat
Mode)
0102
Message Count A (fixed location)0101
Stack Pointer A (fixed location)
Stack A
DESCRIPTION
ADDRESS
(HEX)
0103
Note: Used only in the Enhanced BC mode with Frame Auto-Repeat enabled.
0000-00FF
TABLE 25. TYPICAL BC MEMORY ORGANIZATION
(SHOWN FOR 4K RAM)
0100
BC MEMORY ORGANIZATION
TABLE 25 illustrates a typical memory map for BC mode. It is
important to note that the only fixed locations for the BU-61580
in the Standard BC mode are for the two Stack Pointers (address
locations 0100 (hex) and 0104) and for the two Message Count
locations (0101 and 0105). Enabling the Frame Auto-Repeat
mode will reserve four more memory locations for use in the
Enhanced BC mode; these locations are for the two Initial Stack
Pointers (address locations 102 (hex) and 106) and for the Initial
Message Count locations (103 and 107). The user is free to
locate the Stack and BC Message Blocks anywhere else within
the 64K (4K internal) shared RAM address space.
For simplicity of illustration, assume the allocation of the maxi-
mum length of a BC message for each message block in the
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typical BC memory map of TABLE 25. The maximum size of a BC
message block is 38 words, for an RT-to-RT transfer of 32 Data
Words (Control + 2 Commands + Loopback + 2 Status Words +
32 Data Words). Note, however, that this example assumes the
disabling of the 256-word boundaries.
BC MEMORY MANAGEMENT
FIGURE 3 illustrates the BU-61580's BC memory management
scheme. One of the BC memory management features is the
global double buffering mechanism. This provides for two sets of
the various BC mode data structures: Stack Pointer and Message
Counter locations, Descriptor Stack areas, and BC message
blocks. Bit 13 of Configuration Register #1 selects the current
active area. At any point in time, the BU-61580's internal 1553
memory management logic may access only the various data
structures within the “active” area. FIGURE 3 delineates the
“active” and “inactive” areas by the nonshaded and shaded
areas, respectively; however, at any point in time, both the
“active” and “nonactive” areas are accessible by the host
processor. In most applications, the host processor will access
the “nonactive” area, while the 1553 bus processes the “active”
area messages.
The BC may be programmed to transmit multimessage frames of
up to 512 messages. The number of messages to be processed
is programmable by the Active Area Message Count location in
the shared RAM, initialized by the host processor. In addition, the
host processor must initialize another location, the Active Area
Stack Pointer. The Stack Pointer references the four-word mes-
sage block descriptor in the Stack area of shared RAM for each
message to be processed. The BC Stack size is programmable
with choices of 256, 512, 1024, and 2048 words.
In the BC Frame Auto-Repeat mode, the Initial Stack Pointer and
Initial Message Counter locations must be loaded by the host
prior to the processing of the first frame. The single frame mode
does not use these two locations.
The third and fourth words of the BC block descriptor are the
Intermessage Gap Time and the Message Block Address for the
respective message. These two memory locations must be writ-
ten by the host processor prior to the start of message process-
ing. Use of the Intermessage Gap Time is optional. The Block
Address pointer specifies the starting location for each message
block. The first word of each BC message block is the BC Control
Word.
At the start and end of each message, the Block Status and Time
Tag Words write to the message block descriptor in the stack.
The Block Status Word includes indications of message in pro-
FIGURE 2. BC MESSAGE GAP AND FRAME TIMING
MESSAGE NO. 1 MESSAGE NO. 2 MESSAGE NO. 1
MESSAGE
GAP TIME
FOR MESSAGE NO. 1
BC FRAME TIME
INTERMESSAGE GAP TIME
cess or message completion, bus channel, status set, response
timeout, retry count, status address mismatch, loop test (on-line
self-test) failure, and other error conditions. TABLE 21 illustrates
the bit mapping of the BC Block Status word. The 16-bit Time Tag
Word will reflect the current contents of the internal Time Tag
Register. This read/writable register, which operates for all three
modes, has programmable resolution of from 2 to 64 µs/LSB. In
addition, the Time Tag register may be clocked from an external
source.
BC MESSAGE BlOCk FORMATS ANd BC CONTROl
WORd
In BC mode, the BU-61580 supports all MIL-STD-1553 message
formats. For each 1553 message format, the BU-61580 man-
dates a specific sequence of words within the BC Message
Block. This includes locations for the Control, Command and
(transmitted) Data Words that are to be read from RAM by the
BC protocol logic. In addition, subsequent contiguous locations
must be allocated for storage of received Loopback, RT Status
and Data Words. FIGURE 4 illustrates the organization of the BC
message blocks for the various MIL-STD-1553 message for-
mats. Note that for all of the message formats, the BC Control
Word is located in the first location of the message block.
For each of the BC Message Block formats, the first word in the
block is the BC Control Word. The BC Control Word is not trans-
mitted on the 1553 bus. Instead, it contains bits that select the
active bus and message format; enable off-line self-test; mask-
ing of Status Word bits; enable retries and interrupts; and speci-
fies MIL-STD-1553A or -1553B error handling. The bit mapping
and definitions of the BC Control Word are illustrated in
TABLE 8.
The BC Control Word is followed by the Command Word to be
transmitted, and subsequently by a second Command Word (for
an RT-to-RT transfer), followed by Data Words to be transmitted
(for Receive commands). The location after the last word to be
transmitted is reserved for the Loopback Word. The Loopback
Word is an on-line self-test feature. The subsequent locations
after the Loopback Word are reserved for received Status Words
and Data Words (for Transmit commands).
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AUTOMATIC RETRIES
The BU-61580 BC implements automatic message retries. When
enabled, retries will occur, following response timeout or format
error conditions. As additional options, retries may be enabled
when the Message Error Status Word bit is set by a 1553A RT
or following a ”Status Set” condition. For a failed message, either
one or two message retries will occur, the bus channel (same or
alternate) is independently programmable for the first and sec-
ond retry attempts. Retries may be enabled or disabled on an
individual message basis.
BC INTERRUPTS
BC interrupts may be enabled by the Interrupt Mask Register for
Stack Rollover, Retry, End-of-Message (global), End-of-Message
(in conjunction with the BC Control Word for individual messag-
es), response timeout, message error, end of BC frame, and
Status Set conditions. The definition of “Status Set” is program-
mable on an individual message basis, by means of the BC
Control Word. This allows for masking (“care/don't care”) of the
individual RT Status Word bits.
REMOTE TERMINAL (RT) ARCHITECTURE
The RT protocol design of the BU-65170/61580 represents
DDC's fifth generation implementation of a 1553 RT. One of the
salient features of the ACE's RT architecture is its true multipro-
tocol functionality. This includes programmable options for sup-
port of MIL-STD-1553A, the various McAir protocols, and MIL-
STD-1553B Notice 2. The BU-65170/61580 RT response time is
2 to 5 µs dead time (4 to 7 µs per 1553B), providing compliance
to all the 1553 protocols. Additional multiprotocol features of the
BU-65170/61580 include options for full software control of RT
Status and Built-in-Test (BIT) words. Alternatively, for 1553B
applications, these words may be formulated in real time by the
BU-65170/61580 protocol logic.
The BU-65170/61580 RT protocol design implements all the
MIL-STD-1553B message formats and dual redundant mode
15 13 0
CURRENT
AREA B/A
CONFIGURATION
REGISTER 1
INITIAL STACK
POINTERS (NOTE)
INITIAL MESSAGE
COUNTERS (NOTE)
MESSAGE
COUNTERS
STACK
POINTERS
BLOCK STATUS WORD
TIME TAG WORD
MESSAGE
GAP TIME WORD
MESSAGE
BLOCK ADDR
DESCRIPTOR
STACKS
MESSAGE
BLOCKS
MESSAGE
BLOCK
MESSAGE
BLOCK
NOTE:
INITIAL STACK POINTERS AND INITIAL
MESSAGE COUNTERS USED ONLY IN
BC FRAME AUTO-REPEAT MODE.
FIGURE 3. BC MODE MEMORY MANAGEMENT
codes. This design is based largely on previous generation prod-
ucts that have passed SEAFAC testing for MIL-STD-1553B
compliance. The ACE RT performs comprehensive error check-
ing, word and format validation, and checks for various RT-to-RT
transfer errors. Other key features of the BU-65170/61580 RT
include a set of interrupt conditions, internal command illegaliza-
tion, and programmable busy by subaddress.
RT MEMORY ORGANIZATION
TABLE 26 illustrates a typical memory map for the BU-61580 in
RT mode. As in BC mode, the two Stack Pointers reside in fixed
locations in the shared RAM address space: address 0100 (hex)
for the Area A Stack Pointer and address 0104 for the Area B
Stack Pointer. Besides the Stack Pointer, for RT mode there are
several other areas of the ACE address space designated as
fixed locations. All RT modes of operation require the Area A and
Area B Lookup Tables. Also allocated are several fixed locations
for optional features: Command Illegalization Lookup Table,
Mode Code Selective Interrupt Table, Mode Code Data Table,
and Busy Bit Lookup Table. It should be noted that any unen-
abled optional fixed locations may be used for general purpose
storage (data blocks).
The RT Lookup tables, which provide a mechanism for mapping
data blocks for individual Tx/Rx/Bcst-subaddresses to areas in
the RAM, occupy address range locations are 0140 to 01BF for
Area A and 01C0 to 023F for Area B. The RT lookup tables
include Subaddress Control Words and the individual Data Block
Pointers. If used, address range 0300-03FF will be dedicated as
the illegalizing section of RAM. The actual Stack RAM area and
the individual data blocks may be located in any of the nonfixed
areas in the shared RAM address space.
15
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BC-to-RT Transfer
Control Word
Receive Command Word
Data Word #1
Data Word #2
.
.
.
Last Data Word
Last Data Word Looped Back
Status Received Last Data Word
.
.
.
Data Word #2
Data Word #1
Status Received
Transmit Command Looped Back
Transmit Command Word
Control Word
RT-to-BC Transfer
Transmit Command
Looped Back
Rx RT Status Word
Last Data
.
.
.
Data #2
Data #1
Tx RT Status Word
Transmit Command
Receive Command
Control Word
RT-to-RT Transfer
Mode Command
Looped Back
Status Received
Mode Command
Control Word
Mode Code;
No Data
Mode Command
Looped Back
Data Word
Status Received
Tx Mode Command
Control Word
Tx Mode Code;
With Data
Tx Command
Looped Back
Last Data
.
.
.
Data #2
Data #1
Tx RT Status Word
Tx Command
Rx Broadcast Command
Control Word
RT-to-RTs (Broadcast)
Transfer
Last Data Status
Word
Last Data
.
.
.
Data #2
Data #1
Broadcast Command
Control Word
Broadcast
Data Word
Data Word Looped
Back
Status Received
Rx Mode Command
Control Word
Rx Mode Code;
With Data
Broadcast Mode Command
Looped Back
Broadcast Mode Command
Control Word
Broadcast Mode Code;
No Data
Data Word Looped Back
Data Word
Broadcast Mode Command
Control Word
Broadcast Mode Code;
With Data
FIGURE 4. BC MESSAGE BLOCK FORMATS
RT MEMORY MANAGEMENT
One of the salient features of the ACE series products is the flex-
ibility of its RT memory management architecture. The RT archi-
tecture allows the memory management scheme for each trans-
mit, receive, or broadcast subaddress to be programmable on a
subaddress basis. Also, in compliance with MIL-STD-1553B
Notice 2, the BU-65170/61580 provides an option to separate
data received from broadcast messages from nonbroadcast
received data.
Besides supporting a global double buffering scheme (as in BC
mode), the ACE RT provides a pair of 128-word Lookup Tables
for memory management control. They are programmable on a
subaddress basis (refer to TABLE 27). These 128-word tables
include 32-word tables for transmit message pointers and
receive message pointers. There is also a third, optional Lookup
Table for broadcast message pointers, providing Notice 2 compli-
ance, if necessary.
The fourth section of each of the RT Lookup Tables stores the 32
Subaddress Control Words (refer to TABLE 9 and 28). The indi-
vidual Subaddress Control Words may be used to select the RT
memory management option and interrupt scheme for each
transmit, receive, and (optionally) broadcast subaddress.
For each transmit subaddress, there are two possible memory
management schemes: (1) single message; and (2) circular buf-
fer. For each receive (and optionally broadcast) subaddress,
there are three possible memory management schemes: (1)
single message; (2) double buffered; and (3) circular buffer. For
each transmit, receive and broadcast subaddress, there are two
interrupt conditions that are programmable by the respective
Subaddress Control Word: (1) after every message to the subad-
dress; (2) after a circular buffer rollover. An additional table in
RAM may be used to enable interrupts following selected mode
code messages.
When using the circular buffer scheme for a given subaddress,
the size of the circular buffer is programmable by three bits of the
Subaddress Control Word (see TABLE 28). The options for circu-
lar buffer size are 128, 256, 512, 1024, 2048, 4096, and 8192
Data Words.
SINGLE MESSAGE MODE
FIGURE 5 illustrates the RT Single Message memory manage-
ment scheme. When operating the BU-65170/61580 in its “AIM-
HY” (default) mode, the Single Message scheme is implemented
for all transmit, receive, and broadcast subaddresses. In the
Single Message mode (also in the Double Buffer and Circular
Buffer modes), there is a global double buffering scheme, con-
trolled by bit 13 of Configuration Register #1. This selects from
between the two sets of the various data structures shown in the
figure: the Stack Pointers (fixed addresses), Descriptor Stacks
(user defined addresses), RT Lookup Tables (fixed addresses),
and RT Data Word blocks (user defined addresses). FIGURES
5, 6, and 7 delineate the “active” and “nonactive” areas by the
nonshaded and shaded areas, respectively.
As shown, the ACE stores the Command Word from each mes-
sage received, in the fourth location within the message descrip-
tor (in the stack) for the respective message. The T/R bit, subad-
dress field, and (optionally) broadcast/own address, index into
the active area Lookup Table, to locate the data block pointer for
the current message. The BU-65170/61580 RT memory man-
agement logic then accesses the data block pointer to locate the
starting address for the Data Word block for the current mes-
sage. The maximum size for an RT Data Word block is 32
words.
16
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For a particular subaddress in the Single Message mode, there
is overwriting of the contents of the data blocks for receive/broad-
cast subaddresses — or overreading, for transmit subaddresses.
In the single message mode, it is possible to access multiple
data blocks for the same subaddress. This, however, requires the
intervention of the host processor to update the respective
Lookup Table pointer.
To implement a data wraparound subaddress, as required by
Notice 2 of MIL-STD-1553B, the Single Message scheme should
be used for the wraparound subaddress. Notice 2 recommends
subaddress 30 as the wraparound subaddress.
Data Block 100
•
•
0FE0-0FFF
•
•
•
·•
Data Block 60420-043F
Data Block 50400-041F
Command Illegalizing Table (fixed area)0300-03FF
RESERVED
Data Block 1-40280-02FF
Data Block 00260-027F
(not used)0248-025F
Busy Bit Lookup Table (fixed area)0240-0247
Lookup Table B (fixed area)01C0-023F
Lookup Table A (fixed area)0140-01BF
Mode Code Data (fixed area)0110-013F
Mode Code Selective Interrupt Table (fixed area)0108-010F
Stack Pointer B (fixed location)0104
RESERVED0101-0103
Stack Pointer A (fixed location)0100
Stack A0000-00FF
DESCRIPTION
ADDRESS
(HEX)
0105-0107
TABLE 26. TYPICAL RT MEMORY MAP (SHOWN FOR 4K RAM)
TABLE 27. LOOK-UP TABLES
AREA A AREA B DESCRIPTION COMMENT
01C0
.
.
.
01DF
Rx(/Bcst)_SA0
.
.
.
Rx(/Bcst)_SA31
Receive
(/Broadcast)
Lookup Table
01E0
.
.
.
01FF
Tx_SA0
.
.
.
Tx_SA31
Transmit
Lookup Table
0200
.
.
.
021F
Bcst_SA0
.
.
.
Bcst_SA31
Broadcast
Lookup Table
Optional
0220
.
.
.
023F
SACW_SA0
.
.
.
SACW_SA31
Subaddress
Control Word
Lookup Table
(Optional)
0140
.
.
.
015F
0160
.
.
.
017F
0180
.
.
.
019F
01A0
.
.
.
01BF
MM2 MM1 MM0 COMMENT
000 Single Message or Double Buffered
0 0 1 128-Word
0 1 0 256-Word
0 1 1 512-Word
1
1
1
1
1
1
0
0
1
0
1
0
8192-Word
4096-Word
2048-Word
1024-Word
Circular Buffer of
Specified Size
DESCRIPTION
TABLE 28. SUBADDRESS CONTROL WORD
Memory Management Subaddress Buffer Scheme
CIRCUlAR BUFFER MOdE
FIGURE 6 illustrates the RT circular buffer memory management
scheme. The circular buffer mode facilitates bulk data transfers.
The size of the RT circular buffer, shown on the right side of the
figure, is programmable from 128 to 8192 words (in even powers
of 2) by the respective Subaddress Control Word. As in the single
message mode, the host processor initially loads the individual
Lookup Table entries. At the start of each message, the ACE
stores the Lookup Table entry in the third position of the respec-
tive message block descriptor in the stack area of RAM, as in the
Single Message mode. The ACE transfers Receive or Transmit
Data Words to (from) the circular buffer, starting at the location
referenced by the Lookup Table pointer.
At the end of a valid (or optionally invalid) message, the value of
the Lookup Table entry updates to the next location after the last
address accessed for the current message. As a result, Data
Words for the next message directed to the same Tx/RX(/Bcst)
subaddress will be accessed from the next contiguous block of
address locations within the circular buffer. As a recommended
option, the Lookup Table pointers may be programmed to not
update following an invalid receive (or broadcast) message. This
allows the 1553 bus controller to retry the failed message, result-
ing in the valid (retried) data overwriting the invalid data. This
eliminates overhead for the RT's host processor. When the
pointer reaches the lower boundary of the circular buffer (located
at 128, 256, . . . 8192-word boundaries in the BU-65170/61580
address space), the pointer moves to the top boundary of the
circular buffer, as FIGURE 6 shows.
Implementing Bulk Data Transfers
The use of the Circular Buffer scheme is ideal for bulk data trans-
fers; that is, multiple messages to/from the same subaddress.
The recommendation for such applications is to enable the circu-
lar buffer interrupt request. By so doing, the routine transfer of
multiple messages to the selected subaddress, including errors
and retries, is transparent to the RT's host processor. By strate-
gically initializing the subaddresses' Lookup Table pointer prior to
the start of the bulk transfer, the BU-65170/61580 may be con-
figured to issue an interrupt request only after it has received the
anticipated number of valid Data Words to the designated subad-
dress.
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SUBADDRESS DOUBLE BUFFERING MODE
For receive (and broadcast) subaddresses, the BU-65170/61580
RT offers a third memory management option, Subaddress
Double Buffering. Subaddress Double Buffering provides a
means of ensuring data consistency. FIGURE 7 illustrates the RT
Subaddress Double Buffering scheme. Like the Single Message
and Circular Buffer modes, the Double Buffering mode may be
selected on a subaddress basis by means of the Subaddress
Control Word. The purpose of the Double Buffering mode is to
provide the host processor a convenient means of accessing the
most recent, valid data received to a given subaddress. This
serves to ensure the highest possible degree of data consistency
by allocating two 32-bit Data Word blocks for each individual
receive (and/or broadcast) subaddress.
At a given point in time, one of the two blocks will be designated
as the “active” 1553 data block while the other will be designated
as the “inactive” block. The Data Words from the next receive
message to that subaddress will be stored in the “active” block.
Upon completion of the message, provided that the message
was valid and Subaddress Double Buffering is enabled, the
BU-65170/61580 will automatically switch the “active” and “inac-
tive” blocks for the respective subaddress. The ACE accom-
plishes this by toggling bit 5 of the subaddress's Lookup Table
Pointer and rewriting the pointer. As a result, the most recent
valid block of received Data Words will always be readily acces-
sible to the host processor.
As a means of ensuring data consistency, the host processor is
able to reliably access the most recent valid, received Data Word
block by performing the following sequence:
15 13 0
CURRENT
AREA B/A
CONFIGURATION
REGISTER 1
INITIAL STACK
POINTERS (NOTE)
INITIAL MESSAGE
COUNTERS (NOTE)
MESSAGE
COUNTERS
STACK
POINTERS
BLOCK STATUS WORD
TIME TAG WORD
MESSAGE
GAP TIME WORD
MESSAGE
BLOCK ADDR
DESCRIPTOR
STACKS
MESSAGE
BLOCKS
MESSAGE
BLOCK
MESSAGE
BLOCK
NOTE:
INITIAL STACK POINTERS AND INITIAL
MESSAGE COUNTERS USED ONLY IN
BC FRAME AUTO-REPEAT MODE.
FIGURE 5. RT MEMORY MANAGEMENT: SINGLE MESSAGE MODE
CIRCULAR
BUFFER
ROLLOVER
15 13 0
RECEIVED
(TRANSMITTED)
MESSAGE
DATA
(NEXT LOCATION)
128,
256
8192
WORDS
POINTER TO
CURRENT
DATA BLOCK
POINTER TO
NEXT DATA
BLOCK
LOOK-UP TABLE
ENTRY
CIRCULAR
DATA
BUFFER
LOOK-UP TABLES
LOOK-UP
TABLE
ADDRESS
BLOCK STATUS WORD
TIME TAG WORD
DATA BLOCK POINTER
RECEIVED COMMAND
WORD
CONFIGURATION
REGISTER
STACK
POINTERS
DESCRIPTOR
STACK
CURRENT
AREA B/A
TX/RS/BCST_SA LOOK-UP TABLE ENTRY IS UPDATED
FOLLOWING VALID RECEIVE (BROADCAST) MESSAGE OR
FOLLOWING COMPLETION OF TRANSIT MESSAGE.
*
*
FIGURE 6. RT MEMORY MANAGEMENT: CIRCULAR BUFFER MODE
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15 13 0
BLOCK STATUS WORD
TIME TAG WORD
DATA BLOCK POINTER
RECEIVED COMMAND
WORD
CONFIGURATION
REGISTER
STACK
POINTERS
DESCRIPTOR
STACK
CURRENT
AREA B/A
DATA
BLOCKS
DATA
BLOCK 1
DATA
BLOCK 0
X..X 0 YYYYY
X..X 1 YYYYY
RECEIVE DOUBLE
BUFFER ENABLE
SUBADDRESS
CONTROL WORD
MSB
DATA BLOCK POINTER
LOOK-UP
TABLES
FIGURE 7. RT MEMORY MANAGEMENT: SUBADDRESS DOUBLE BUFFERING MODE
(1) Disable the double buffering for the respective subad-
dress by the Subaddress Control Word. That is, temporarily
switch the subaddress' memory management scheme to the
Single Message mode.
(2) Read the current value of the receive (or broadcast) sub-
address's Lookup Table pointer. This points to the current
“active” Data Word block. By inverting bit 5 of this pointer
value, it is possible to locate the start of the “inactive” Data
Word block. This block will contain the Data Words received
during the most recent valid message to the subaddress.
(3) Read out the words from the “inactive” (most recent) Data
Word Block.
(4) Re-enable the Double Buffering mode for the respective
subaddress by the Subaddress Control Word.
RT INTERRUPTS
As in BC mode, the BU-65170/61580 RT provides many mask-
able interrupts. RT interrupt conditions include End of (every)
Message, Message Error, Selected Subaddress (Subaddress
Control Word) Interrupt, Circular Buffer Rollover, Selected Mode
Code Interrupt, and Stack Rollover.
DESCRIPTOR STACK
At the beginning and end of each message, the BU-65170/61580
RT stores a four-word message descriptor in the active area
stack. The RT stack size is programmable, with choices of 256,
512, 1024, and 2048 words. FIGURES 5, 6 and 7 show the four
words: Block Status Word, Time Tag Word, Data Block Pointer,
and the 1553 received Command Word. The RT Block Status
Word includes indications of message in-progress or message
complete, bus channel, RT-to-RT transfer and RT-to-RT transfer
errors, message format error, loop test (self-test) failure, circular
buffer rollover, illegal command, and other error conditions.
TABLE 22 shows the bit mapping of the RT Block Status Word.
As in BC mode, the Time Tag Word stores the current contents
of the BU-65170/61580's read/writable Time Tag Register. The
resolution of the Time Tag Register is programmable from among
2, 4, 8, 16, 32, and 64 µs/LSB. Also, incrementing of the Time
Tag counter may be from an external clock source or via software
command.
The ACE stores the contents of the accessed Lookup Table loca-
tion for the current message, indicating the starting location of
the Data Word block, as the Data Block Pointer. This serves as a
convenience in locating stored message data blocks. The ACE
stores the full 16-bit 1553 Command Word in the fourth location
of the RT message descriptor.
RT COMMAND ILLEGALIZATION
The BU-65170/61580 provides an internal mechanism for RT
command illegalization. In addition, the Busy Status Word bit
can be set so that it is only a programmed subset of the transmit/
receive/broadcast subaddresses.
The illegalization scheme uses a 256-word area in the
BU-65170/61580's address space. A benefit of this feature is the
reduction of printed circuit board requirements, by eliminating
the need for an external PROM, PLD, or RAM device that does
the illegalizing function. The BU-J1165170/61580's illegalization
scheme provides maximum flexibility, allowing any subset of the
4096 possible combinations of broadcast/own address, T/R bit,
subaddress, and word count/mode code to be illegalized.
Another advantage of the RAM-based illegalization technique is
that it provides for a high degree of self-testability.
Addressing the Illegalization Table
TABLE 29 illustrates the addressing scheme of the illegalization
RAM. As shown, the base address of the illegalizing RAM is
0300 (hex). The ACE formulates the index into the Illegalizing
Table based on the values of BROADCAST/OWN ADDRESS,
T/R bit, Subaddress, and the MSB of the Word Count/Mode
Code field (WC/MC4) of the current Command Word.
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The internal RAM has 256 words reserved for command illegal-
ization. Broadcast commands may be illegalized separately from
nonbroadcast receive commands and mode commands.
Commands may be illegalized down to the word count level. For
example, a one-word receive command to subaddress 1 may be
legal, while a two-word receive command to subaddress 1 may
be illegalized.
The first 64 words of the Illegalization Table refer to broadcast
receive commands (two words per subaddress). The next 64
words refer to broadcast transmit commands. Since nonmode
code broadcast transmit commands are by definition invalid, this
section of the table (except for subaddresses 0 and 31) does not
need to be initialized by the user. The next 64 words correspond
to nonbroadcast receive commands. The final 64 words refer to
nonbroadcast transmit commands. Messages with Word Count/
Mode Code (WC/MC) fields between 0 and 15 may be illegalized
by setting the corresponding data bits for the respective even-
numbered address locations in the illegalization table. Likewise,
messages with WC/MC fields between 16 and 31 may be illegal-
ized by setting the corresponding data bits for the respective
odd-numbered address locations in the illegalization table.
The following should be noted with regards to command illegal-
ization:
(1) To illegalize a particular word count for a given broadcast/
own address-T/R subaddress, the appropriate bit position in
the respective illegalization word should be set to logic 1. A bit
value of logic 0 designates the respective Command Word as
a legal command. The ACE will respond to an illegalized non-
broadcast command with the Message Error bit set in its RT
Status Word.
(2) For subaddresses 00001 through 11110, the “WC/MC”
field specifies the Word Count field of the respective Command
Word. For subaddresses 00000 and 11111, the “WC/MC” field
specifies the Mode Code field of the respective Command
Word.
(3) Since nonmode code broadcast transmit messages are
not defined by MIL-STD-1553B, the sixty (60) words in the
illegalization RAM, addresses 0342 through 037D, corre-
sponding to these commands do not need to be initialized.
The ACE will not respond to a nonmode code broadcast trans-
mit command, but will automatically set the Message Error bit
in its internal Status Register, regardless of whether or not
corresponding bit in the illegalization RAM has been set. If the
next message is a Transmit Status or Transmit Last Command
mode code, the ACE will respond with its Message Error bit
set.
PROGRAMMABLE BUSY
As a means of providing compliance with Notice 2 of MIL-STD-
1553B, the BU-65170/61580 RT provides a software controllable
means for setting the Busy Status Word bit as a function of sub-
address. By a Busy Lookup Table in the BU-65170/61580
address space, it is possible to set the Busy bit based on com-
mand broadcast/own address, T/R bit, and subaddress. Another
programmable option, allows received Data Words to be either
stored or not stored for messages, when the Busy bit is set.
OTHER RT FUNCTIONS
The BU-65170/61580 allows the hardwired RT Address to be
read by the host processor. Also, there are options for the RT
FLAG Status Word bit to be set under software control and/or
automatically following a failure of the loopback self-test. Other
software controllable RT options include software programmable
RT Status and RT BIT words, automatic clearing of the Service
Request Status Word bit following a Transmit Vector Word mode
command, capabilities to clear and/or load the Time Tag Register
following receipt of Synchronize mode commands, options
regarding Data Word transfers for the Busy and/or Message
Error (Illegal) Status Word bits, and for handling of 1553A and
reserved mode codes.
MONITOR (MT) ARCHITECTURE
The BU-61580 provides three bus monitor (MT) modes:
(1) The “AIM-HY” (default) or “AIM-HY'er” Word Monitor mode.
(2) A Selective Message Monitor mode.
(3) A Simultaneous Remote Terminal/Selective Message Monitor
mode.
WC4/MC40(LSB)
SA01
SA12
0
SA23
SA34
SA45
T/R6
BROADCAST/OWN_ADDRESS7
18
19
010
012
013
014
0
15(MSB)
DESCRIPTIONBIT
11
TABLE 29. ILLEGALIZATION RAM ADDRESS DEFINITION
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The strong recommendation for new applications is the use of
the Selective Message Monitor, rather than the Word Monitor.
Besides providing monitor filtering based on RT Address, T/R bit,
and Subaddress, the Message Monitor eliminates the need to
determine the start and end of messages by software. The devel-
opment of such software tends to be a tedious task. Moreover, at
run time, it tends to entail a high degree of CPU overhead.
WORD MONITOR
In the Word Monitor mode, the BU-61580 monitors both 1553
buses. After initializing the Word Monitor and putting it on-line the
BU-61580 stores all Command, Status, and Data Words received
from both buses. For each word received from either bus, the
BU-61580 stores a pair of words in RAM. The first word is the 16
bits of data from the received word. The second word is the
Monitor Identification (ID), or “Tag” word. The ID Word contains
information relating to bus channel, sync type, word validity, and
interword time gaps. The BU-61580 stores data and ID words in
a circular buffer in the shared RAM address space. TABLE 23
shows the bit mapping for the Monitor ID word.
MONITOR TRIGGER WORD
There is a Trigger Word Register that provides additional flexibil-
ity for the Word Monitor mode. The BU-61580 stores the value of
the 16-bit Trigger Word in the MT Trigger Word Register. The
contents of this register represent the value of the Trigger
Command Word. The BU-61580 has programmable options to
start or stop the Word Monitor, and/or to issue an interrupt
request following receipt of the Trigger Command Word from the
1553 bus.
SELECTIVE MESSAGE MONITOR MODE
The BU-61580 Selective Message Monitor provides features to
greatly reduce the software and processing burden of the host
CPU. The Selective Message Monitor implements selective
monitoring of messages from a dual 1553 bus, with the monitor
filtering based on the RT Address, T/R bit, and Subaddress fields
of received 1553 Command Words. The Selective Message
Monitor mode greatly simplifies the host processor software by
distinguishing between Command and Status Words. The
Selective Message Monitor maintains two stacks in the BU-61580
RAM: a Command Stack and a Data Stack.
Simultaneous RT/Message Monitor Mode
The Selective Message Monitor may function as a purely passive
monitor or may be programmed to function as a simultaneous
RT/Monitor. The RT/Monitor mode provides complete Remote
Terminal (RT) operation for the BU-61580's strapped RT address
and bus monitor capability for the other 30 nonbroadcast RT
addresses. This allows the BU-61580 to simultaneously operate
as a full function RT and “snoop” on all or a subset of the bus
activity involving the other RTs on a bus. This type of operation
is sometimes needed to implement a backup bus controller. The
combined RT/Selective Monitor maintains three stack areas in
the BU-61580 address space: an RT Command Stack, a Monitor
Command Stack, and a Monitor Data Stack. The pointers for the
various stacks have fixed locations in the BU-61580 address
space.
Selective Message Monitor Memory Organization
TABLE 30 illustrates a typical memory map for the ACE in the
Selective Message Monitor mode. This mode of operation
defines several fixed locations in the RAM. These locations allo-
cate in a manner that is compatible with the combined RT/
Selective Message Monitor mode. Refer to TABLE 30 for an
example of a typical Selective Message Monitor Memory Map.
The fixed memory map consists of two Monitor Command Stack
Pointers (location 102h and 106h), two Monitor Data Stack
Pointers (locations 103h and 107h), and a Selective Message
Monitor Lookup Table (0280-02FFh) based on RT Address, T/R,
and subaddress. Assume a Monitor Command Stack size of 1K
words, and a Monitor Data Stack size of 2K words.
Refer to FIGURE 8 for an illustration of the Selective Message
Monitor operation. Upon receipt of a valid Command Word, the
BU-61580 will reference the Selective Monitor Lookup Table (a
fixed block of addresses) to check for the condition (disabled/
enabled) of the current command. If disabled, the BU-61580 will
ignore (and not store) the current message; if enabled, the
BU-61580 will create an entry in the Monitor Command Stack at
the address location referenced by the Monitor Command Stack
Pointer.
Similar to RT mode, The ACE stores a Block Status Word, 16-bit
Time Tag Word, and Data Block Pointer in the Message
Descriptor, along with the received 1553 Command Word follow-
ing reception of the Command Word. The ACE writes the Block
Status and Time Tag Words at both the start and end of the mes-
sage. The Monitor Block Status Word contains indications of
message in-progress or message complete, bus channel,
Monitor Data Stack Rollover, RT-to-RT transfer and RT-to-RT
transfer errors, message format error, and other error conditions.
TABLE 24 shows the Message Monitor Block Status Word. The
Data Block Pointer references the first word stored in the Monitor
Data Stack (the first word following the Command Word) for the
current message. The BU-61580 will then proceed to store the
subsequent words from the message (possible second Command
Word, Data Word(s), Status Word(s)) into consecutive locations
in the Monitor Data Stack.
The size of the Monitor Command Stack is programmable to
256, 1K, 4K, or 16K words. The Monitor Data Stack size is pro-
grammable to 512, 1K, 2K, 4K, 8K, 16K, 32K, or 64K words.
Monitor interrupts may be enabled for Monitor Command Stack
Rollover, Monitor Data Stack Rollover, and/or End-of-Message
conditions. In addition, in the Word Monitor mode there may be
an interrupt enabled for a Monitor Trigger condition.
21
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Monitor Command Stack Pointer B (fixed location)
Monitor Data Stack A0800-0FFF
Monitor Command Stack A0400-07FF
Not Used0300-03FF
Selective Monitor Lookup Table (fixed area)0280-02FF
Not Used0108-027F
Monitor Data Stack Pointer B (fixed location)0107
Not Used0104-0105
Monitor Data Stack Pointer A (fixed location)0103
Monitor Command Stack Pointer A (fixed location)
0102
Not Used
0000-0101
DESCRIPTION
0106
TABLE 30. TYPICAL SELECTIVE MESSAGE MONITOR
MEMORY MAP (SHOWN FOR 4K RAM)
ADDRESS
(HEX)
PROCESSOR AND MEMORY INTERFACE
The ACE terminals provide much flexibility for interfacing to a
host processor and optional external memory. FIGURE 1 shows
that there are 14 control signals, 6 of which are dual purpose, for
the processor/memory interface. FIGURES 9 through 14 illus-
trate six of the configurations that may be used for interfacing a
BU-65170 or BU-61580 to a host processor bus. The various
possible configurations serve to reduce to an absolute minimum
the amount of glue logic required to interface to 8-, 16-, and
32-bit processor buses. Also included are features to facilitate
interfacing to processors that do not have a “wait state” type of
handshake acknowledgement. Finally, the ACE supports a reli-
able interface to an external dual port RAM. This type of interface
minimizes the portion of the available processor bandwidth
required to access the 1553 RAM.
The 16-bit buffered mode (FIGURE 9) is the most common con-
figuration used. It provides a direct, shared RAM interface to a
16-bit or 32-bit microprocessor. In this mode, the ACE's internal
address and data buffers provide the necessary isolation
between the host processor's address and data buses and the
corresponding internal memory buses. In the buffered mode, the
1553 shared RAM address space limit is the BU-65170/61580's
4K words of internal RAM. The 16-bit buffered mode provides a
pair of pin-programmable options:
15 13 0
BLOCK STATUS WORD
TIME TAG WORD
DATA BLOCK POINTER
RECEIVED COMMAND
WORD
CONFIGURATION
REGISTER #1
MONITOR COMMAND
STACK POINTERS
MONITOR
COMMAND STACKS
CURRENT
AREA B/A
MONITOR DATA
STACKS
MONITOR DATA
BLOCK #N + 1
MONITOR DATA
BLOCK #N
CURRENT
COMMAND WORD
MONITOR DATA
STACK POINTERS
IF THIS BIT IS "0" (NOT SELECTED)
NO WORDS ARE STORED IN EITHER
THE COMMAND STACK OR DATA STACK.
IN ADDITION, THE COMMAND AND DATA
STACK POINTERS WILL NOT BE UPDATED.
NOTE
SELECTIVE MONITOR
LOOKUP TABLES
SELECTIVE MONITOR
ENABLE
(SEE NOTE)
OFFSET BASED ON
RTA4-RTA0, T/R, SA4
FIGURE 8. SELECTIVE MESSAGE MONITOR MEMORY MANAGEMENT
22
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(1) The logic sense of the RD/WR control input is selectable
by the POLARITY_SEL input: For example, write when RD/
WR is low for Motorola 680X0 processors; write when RD/
WR is high for the Intel i960 series microprocessors.
(2) By strapping the input signal ZERO_WAIT to logic "1,"
the ACE terminals may interface to processors that have an
acknowedge type of handshake input to accommodate hard-
ware controlled wait states; most current processor chips
have such an input. In this case, the BU-65170/61580 will
assert its READYD output low only after it has latched
WRITE data internally or has presented READ data on D15-
D0.
By strapping ZERO_WAIT to logic "0," it is possible to easily
interface the BU-65170/61580 to processors that do not have an
acknowledge type of handshake input. An example of such a
processor is Analog Device's ADSP2101 DSP chip. In this con-
figuration, the processor can clear its strobe output before the
completion of access to the BU-65170/61580 internal RAM or
register. In this case, READYD will go high following the rising
edge of STRBD and will stay high until completion of the transfer.
READYD will normally be low when ZERO_WAIT is low.
Similar to the 16-bit buffered mode, the 16-bit transparent mode
(FIGURE 10) supports a shared RAM interface to a host CPU.
The transparent mode offers the advantage of allowing the buffer
RAM size to be expanded to up to 64K words, using external
RAM. A disadvantage of the transparent mode is that it requires
external address and data buffers to isolate the processor buses
from the memory/BU-65170/61580 buses.
A modified version of the transparent mode involves the use of
dual port RAM, rather than conventional static RAM. Refer to
FIGURE 11. This allows the host to access RAM very quickly, the
only limitation being the access time of the dual port RAM. This
configuration eliminates the BU-65170/61580 arbitration delays
for memory accesses. The worst case delay time occurs only
during a simultaneous access by the host and the BU-65170/61580
1553 logic to the same memory address. In general, this will
occur very rarely and the ACE limits the delay to approximately
250 ns.
FIGURE 12 illustrates the connections for the 16-bit Direct
Memory Access (DMA) mode. In this configuration the host pro-
cessor, rather than the ACE terminal, arbitrates the use of the
address and data buses. The arbitration involves the two DMA
output signals Request (DTREQ) and Acknowledge (DTACK),
and the input signal Grant (DTGRT). The DMA interface allows
the ACE components to interface to large amounts of system
RAM while eliminating the need for external buffers. For system
address spaces larger than 64K words, it is necessary for the
host processor to provide a page register for the upper address
bits (above A15) when the BU-65170/61580 accesses the RAM
(while asserting DTACK low).
The internal RAM is accessible through the standard ACE inter-
face (SELECT, STRBD, READYD, etc). The host CPU may
access external RAM by the ACE's arbitration logic and output
control signals, as illustrated in FIGURE 12. Alternatively, control
of the RAM may be shared by both the host processor and the
ACE, as illustrated in FIGURE 13. The latter requires the use of
external logic, but allows the processor to access the RAM
directly at the full access speed of the RAM, rather than waiting
for the ACE handshake acknowledge output (READYD).
FIGURE 14 illustrates the 8-bit buffered mode. This interface
allows a direct connection to 8-bit microprocessors and 8-bit
microcontrollers. As in the 16-bit buffered configuration, the buf-
fer RAM limit is the BU-65170/61580's 4K words of internal RAM.
In the 8-bit mode, the host CPU accesses the BU-65170/61580's
internal registers and RAM by a pair of 8-bit registers embedded
in the ACE interface. The 8-bit interface may be further config-
ured by three strappable inputs: ZERO_WAIT, POLARITY_SEL,
and TRIGGER_SEL. By connecting ZERO_WAIT to logic "0," the
BU-65170/61580 may be interfaced with minimal "glue" logic to
8-bit microcontrollers, such as the Intel 8051 series, that do not
have an Acknowledge type of handshake input. The program-
mable inputs POLARITY_SEL and TRIGGER_SEL allow the
BU-65170/61580 to accommodate the different byte ordering
conventions and "A0" logic sense utilized by different 8-bit pro-
cessor families.
PROCESSOR INTERFACE TIMING
FIGURES 15 and 16 illustrate the timing for the host processor
to access the ACE's internal RAM or registers in the 16-bit, buff-
ered, non-zero, wait-mode. FIGURE 15 illustrates the 16-bit
buffered, nonzero wait mode read cycle timing while FIGURE 16
shows the 16-bit, buffered, nonzero wait mode write cycle tim-
ing.
During a CPU transfer cycle, the signals STRBD and SELECT
must be sampled low on the rising edge of the system clock to
request access to the BU-65170/61580's internal shared RAM.
The transfer will begin on the first rising system clock edge when
(SELECT and STRBD) is low and the 1553 protocol/memory
management unit is not accessing the internal RAM. The falling
edge of the output signal IOEN indicates the start of the transfer.
The ACE latches the signals MEM/REG and RD/WR internally
on the first falling clock edge after the start of the transfer cycle.
The address inputs latch internally on the first rising clock edge
after the signal IOEN goes low. Note that the address lines may
be latched at any time using the ADDR_LAT input signal.
23
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The output signal READYD will be asserted low on the third ris-
ing system clock edge after IOEN goes low. The assertion of
READYD low indicates to the host processor that read data is
available on the parallel data bus, or that write data has been
stored. At this time, the CPU should bring the signal STRBD
high, completing the transfer cycle.
Address Latch Timing
FIGURE 17 illustrates the operation and timing of the address
input latches for the buffered interface mode. In the transparent
mode, the address buffers are always transparent. Since the
transparent mode requires the use of external buffers, external
address latches would be required to demultiplex a multiplexed
address bus. In the buffered mode, however, the ACE's internal
address latches may be used to perform the demultiplexing func-
tion.
The ADDR_LAT input signal controls address latch operation.
When ADDR_LAT is high, the outputs of the latch (which drive
the ACE's internal memory bus) track the state of address inputs
A15 – A00. When it is low, the internal memory bus remains
latched at the state of A15 – A00 just prior to the falling edge of
ADDR_LAT.
MISCELLANEOUS
SElF-TEST
The BU-65170/61580 products incorporate several self-test fea-
tures. These features include an on-line wraparound self-test for
all messages in BC and RT modes, an off-line wraparound self-
test for BC mode, and several other internal self-test features.
The BC/RT on-line loop test involves a wraparound test of the
encoder/decoder and transceiver. The BC off-line self-test
involves the encoder/decoder, but not the transceiver. These
tests entail checking the received version of every transmitted
word for validity (sync, encoding, bit count, parity) and checking
the received version of the last transmitted word for a bit-by-bit
comparison with the encoded word. The loopback test also fails
if there is a timeout of the internal transmitter watchdog timer.
Note that the timeout value of the watchdog timer depends on
the mode of operation selected (1553A or 1553B). A failure of the
loop test results in setting a bit in the message's Block Status
Word and, if enabled, will result in an interrupt request. With
appropriate host processor software, the BC off-line test is able
to exercise the parallel and serial data paths, encoder, decoder,
and a substantial portion of the BC protocol and memory man-
agement logic.
There are additional built-in self-test features, that involve the
use of three configuration register bits and the eight test regis-
ters. This allows a test of approximately 99% of the J’ chip's
internal logic. These tests include an encoder test, a decoder
test, a register test, a protocol test, and a test of the fail-safe
(transmitter timeout) timer.
There is also a test mode. In the test mode, the host processor
can emulate arbitrary activity on the 1553 buses by writing to a
pair of test registers. The test mode can be operated in conjunc-
tion with the Word Monitor mode to facilitate end-to-end self-
tests.
RAM PARITY GENERATION AND CHECKING
The architecture of the J’ monolithic is such that the amount of
buffered RAM may be extended beyond the 4K words of on-chip
J’ RAM. For this off-chip buffered RAM, the J’ chip includes provi-
sions to implement parity generation and checking. Parity gen-
eration and checking provides a mechanism for checking the
data integrity of the internal, buffered memory. Furthermore,
17-bit, rather than 16-bit, wide buffered RAM would be used. For
this RAM, the J’ chip will generate the 17th bit (parity bit) for all
(host and 1553) write accesses and check the parity bit for all
read accesses. If a parity error occurs, an interrupt request may
be issued, and the corresponding bit in the Interrupt Status
Register would be set. The BU-61585 incorporates an additional
8K x 17 RAM chip.
24
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HOST ACE
55
55
8
7
5
4
1
2
3
CH. A
TX/RXA
TX/RXA
55
55
8
7
5
4
1
2
3
CH. B
TX/RXB
TX/RXB
RTAD4-RTAD0 RT
ADDRESS,
PARITY
RTADP
D15-D0
+5V+15V
CLK IN
16 MHz
CLOCK
OSCILLATOR
N/C
N/C
POLARITY_SEL
(NOTE 2)
ZERO_WAIT
(NOTE 3)
ADDRESS
DECODER
SELECT
MEM/REG
RD/WR
STRBD
READYD
TAG_CLK
RD/WR
CPU STROBE
CPU ACKNOWLEDGE (NOTE 4)
RESET
NOTES:
+5V
MSTCLR
SSFLAG/EXT_TRIG
INT
CPU INTERRUPT REQUEST
3. ZERO_WAIT SHOULD BE STRAPPED TO
LOGIC "1" FOR NON-ZERO WAIT INTERFACE
AND TO LOGIC "0" FOR ZERO WAIT INTERFACE.
4. CPU ACKNOWLEDGE PROCESSOR INPUT ONLY
FOR NON-ZERO WAIT TYPE OF INTERFACE.
1. CPU ADDRESS LATCH SIGNAL PROVIDED BY
PROCESSORS WITH MULTIPLEXED ADDRESS/DATA
BUSES.
2. IF POLARITY_SEL = "1", RD/WR IS HIGH TO READ,
LOW TO WRITE.
IF POLARITY_SEL = "0", RD/WR IS LOW TO READ,
HIGH TO WRITE.
A15-A12
A11-A0
N/C
ADDR_LAT
TRANSPARENT/BUFFERED
CPU ADDRESS LATCH (NOTE 1)
+5V
16/8_BIT
TRIGGER_SEL
MSB/LSB
+5V
FIGURE 9. 16-BIT BUFFERED MODE
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FIGURE 10. 16-BIT TRANSPARENT MODE
HOST ACE
55
55
8
7
5
4
1
2
3
CH. A
TX/RXA
TX/RXA
55
55
8
7
5
4
1
2
3
CH. B
TX/RXB
TX/RXB
RTAD4-RTAD0 RT
ADDRESS,
PARITY
RTADP
D15-D0
+5V+15V
CLK IN
16 MHz
CLOCK
OSCILLATOR
RD/WR
STRBD
READYD
TAG_CLK
CPU STROBE
CPU ACKNOWLEDGE
RESET
+5V
MSTCLR
SSFLAG/EXT_TRIG
INT
CPU INTERRUPT REQUEST
'245
DIR EN
CPU D15-D0
RAM
64K x 16 MAX
WR
OE
CS
MEMWR
MEMOE
IOEN
DTREQ
DTGRT
'244
EN
ADDRESS
DECODER
EN
ADDRESS
DECODER
MEMENA-IN
A15-A0
CPU A15-A0
MEMENA-OUT
SELECT
MEM/REG
TRANSPARENT/BUFFERED
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FIGURE 11. 16-BIT TRANSPARENT MODE USING DUAL PORT RAM
HOST ACE
DUAL
PORT
RAM
CS-L
WR-L
OE-L
CS-R
WR-R
OE-R
MEMENA-OUT
MEMWR
MEMOE
BUSY-L BUSY-R N/C
CPU D15-D0
CPU ADDRESS
DIR
'245
EN
'244
EN
D15-D0
A15-A0
CPU A4-A0 A4-A0
RD/WR RD/WR
ADDRESS
DECODER
1553 RAM SELECT
1553 REG SELECT
MEM/REG
IOEN
DTREQ
DTGRT
DTACK
N/C
SELECT
STRBD
CPU DATA STROBE
TRANSPARENT/BUFFERED
+5V
INT
CPU INTERRUPT REQUEST
READYD
RESET
+5V
MSTCLR
CPU READY
MEMENA-IN
+5V
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FIGURE 12. 16-BIT DIRECT MEMORY ACCESS (DMA) MODE
HOST ACE
55
55
8
7
5
4
1
2
3
CH. A
TX/RXA
TX/RXA
55
55
8
7
5
4
1
2
3
CH. B
TX/RXB
TX/RXB
RTAD4-RTAD0 RT
ADDRESS,
PARITY
RTADP
D15-D0
+5V+15V
CLK IN
16 MHz
CLOCK
OSCILLATOR
ADDRESS
DECODER
SELECT
MEM/REG
RESET
+5V
MSTCLR
SSFLAG/EXT_TRIG
INT
CPU INTERRUPT REQUEST
CPU D15-D0
RAM
64K x 16 MAX
WR
OE
CS
MEMWR
MEMOE
RD/WRRD/WR
DTREQ
DTGRT
DTACK
A15-A0
ADDRESS
DECODER MEMENA-IN
EN
MEMENA-OUT
TRANSPARENT/BUFFERED
+5V
STRBD
READYD
TAG_CLK
CPU STROBE
CPU ACKNOWLEDGE
CPU A15-A0
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FIGURE 13. 16-BIT DMA MODE WITH EXTERNAL LOGIC TO REDUCE
PROCESSOR ACCESS TIME TO EXTERNAL RAM
HOST ACE
55
55
8
7
5
4
1
2
3
CH. A
TX/RXA
TX/RXA
55
55
8
7
5
4
1
2
3
CH. B
TX/RXB
TX/RXB
RTAD4-RTAD0 RT
ADDRESS,
PARITY
RTADP
D15-D0
+5V+15V
CLK IN
16 MHz
CLOCK
OSCILLATOR
ADDRESS
DECODER
RESET
+5V
MSTCLR
SSFLAG/EXT_TRIG
INT
CPU INTERRUPT REQUEST
CPU D15-D0
RAM
64K x 16 MAX
WR
OE
CS
RD/WR
RD/WR
DTREQ
DTGRT
DTACK
A15-A0
MEMENA-IN
MEMENA-OUT
TRANSPARENT/BUFFERED
+5V
STRBD
READYD
TAG_CLK
MEMWR
MEMOE
CPU A15-A0
+5V
1553 RAM SELECT
1553 REG SELECT
MEM/REG
SELECT
CPU STROBE
CPU ACKNOWLEDGE
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HOST ACE
55
55
8
7
5
4
1
2
3
CH. A
TX/RXA
TX/RXA
55
55
8
7
5
4
1
2
3
CH. B
TX/RXB
TX/RXB
RTAD4-RTAD0 RT
ADDRESS,
PARITY
RTADP
D15-D8
+5V+15V
CLK IN
16 MHz
CLOCK
OSCILLATOR
POLARITY_SEL
(NOTE 3)
ZERO_WAIT
(NOTE 4)
ADDRESS
DECODER
SELECT
MEM/REG
RD/WR
STRBD
READYD
TAG_CLK
RD/WR
CPU STROBE
CPU ACKNOWLEDGE (NOTE 6)
RESET
NOTES:
+5V
MSTCLR
SSFLAG/EXT_TRIG
INT
CPU INTERRUPT REQUEST
TRANSFERS ARE TRIGGERED BY THE MOST SIGNIFICANT
BYTE TRANSFER READ ACCESSES AND BY THE
LEAST SIGNIFICANT BYTE TRANSFER FOR WRITE ACCESSES.
IF TRIGGER_SEL = "0", THEN INTERNAL 16-BIT
TRANSFERS ARE TRIGGERED BY THE LEAST SIGNIFICANT
BYTE TRANSFER FOR READ ACESSES AND BY THE MOST
SIGNIFICANT BYTE TRANSFER FOR WRITE ACCESSES.
FOR ZERO WAIT INTERFACE (ZERO WAIT = "0"):
IF TRIGGER_SEL = "1", THEN INTERNAL 16-BIT
TRANSFERS ARE TRIGGERED BY THE LEAST SIGNIFICANT
BYTE TRANSFER, FOR BOTH READ AND WRITE ACCESSES.
IF TRIGGER_SEL = "0", THEN INTERNAL 16-BIT
TRANSFERS ARE TRIGGERED BY THE MOST SIGNIFICANT
BYTE TRANSFER, FOR BOTH READ AND WRITE ACCESSES.
6. CPU ACKNOWLEDGE PROCESSOR INPUT ONLY FOR NON-ZERO
WAIT TYPE OF INTERFACE.
1. CPU D7-D0 CONNECTS TO BOTH D15-D8 AND
D7-D0.
2. CPU ADDRESS LATCH SIGNAL PROVIDED BY PROCESSORS
WITH MULTIPLEXED ADDRESS/DATA BUFFERS.
3. IF POLARITY_SEL = "1", THEN MSB/LSB SELECTS THE MOST
SIGNIFICANT BYTE WHEN LOW, AND THE LEAST
SIGNIFICANT BYTE WHEN HIGH.
IF POLARITY_SEL = "0", THEN MSB/LSB SELECTS THE LEAST
SIGNIFICANT BYTE WHEN LOW, AND THE MOST
SIGNIFICANT BYTE WHEN HIGH.
4. ZERO WAIT SHOULD BE STRAPPED TO LOGIC "1" FOR
NON-ZERO WAIT INTERFACE AND TO LOGIC "0" FOR
ZERO WAIT INTERFACE.
5. OPERATION OF TRIGGER_SELECT INPUT IS AS FOLLOWS:
FOR NON-ZERO WAIT INTERFACE (ZERO WAIT = "1"):
IF TRIGGER_SEL = "1", THEN INTERNAL 16-BIT
A15-A12
A11-A0
N/C
ADDR_LAT
CPU ADDRESS LATCH
(NOTE 1)
16/8_BIT
TRANSPARENT/BUFFERED
+5V
CPU D7-D0
(NOTE 2)
A12-A1CPU A12-A0
MSB/LSB
CPU A0
TRIGGER_SEL
(NOTE 5)
D7-D0
FIGURE 14. 8-BIT BUFFERED MODE
* Additional address lines A12 and A13 are required with the BU-61585.
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CLOCK IN
VALID
t7
t3 t8
t11
t13 t15
VALID
t10
t4 t9 t12
t19
VALID
t16
t17
SELECT
(Note 2,7)
(Note 2)
(Note 3,4,7)
(Note 4,5)
STRBD
MEM/REG
RD/WR
IOEN
(Note 2,6)
(Note 6)
(Note 6)
(Note 7,8,9)
READYD
A15-A0
D15-D0
t5
t1
t2 t6 t14 t18
FIGURE 15. CPU READING RAM (SHOWN FOR 16-BIT, BUFFERED, NON-ZERO WAIT MODE)
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REF DESCRIPTION MIN TYP MAX UNITS NOTE REFERENCE
t1 SELECT and STRBD low setup time prior to clock rising edge 10 ns notes 2, 10
t2 107.5 ns notes 2, 6
t2
t2
t2
3.7
128.3
2.8
µs
ns
µs
notes 2, 6
notes 2, 6
notes 2, 6
t3 10 ns notes 3, 4, 5, 7
t3 20 ns notes 3, 4, 5, 7
t4
t4
Address valid setup time following SELECT and STRBD low (@ 12 MHz)
Address valid setup time following SELECT and STRBD low (@ 16 MHz)
50
30
ns
ns
t6
t5
SELECT hold time following IOEN falling
CLOCK IN rising edge delay to IOEN falling edge
0
35
ns
ns
note 2
note 6
t9
t8
t7
Address valid setup time prior to CLOCK IN rising edge
MEM/REG, RD/WR hold time prior to CLOCK IN falling edge
MEM/REG, RD/WR setup time prior to CLOCK IN falling edge
30
30
10
ns
ns
ns
notes 7, 8, 9
notes 3, 4, 5, 7
notes 3, 4, 5, 7
t12
t12
t11
t11
t11
t11
t10
Output Data valid prior to READYD falling (@ 12 MHz)
Output Data valid prior to READYD falling (@ 16 MHz)
IOEN falling delay to READYD falling (reading registers @ 12 MHz)
IOEN falling delay to READYD falling (reading registers @ 16 MHz)
IOEN falling delay to READYD falling (reading RAM @ 12 MHz)
IOEN falling delay to READYD falling (reading RAM @ 16 MHz)
Address hold time following CLOCK IN rising edge
54
33
235
170
235
170
30
250
187.5
250
187.5
265
205
265
205
ns
ns
ns
ns
ns
ns
ns
note 6
note 6
notes 6, 10
notes 6, 10
notes 6, 10
notes 6, 10
notes 7, 8, 9, 10
SELECT and STRBD low delay to IOEN low (uncontended access @ 16 MHz)
SELECT and STRBD low delay to IOEN low (contended access @ 16 MHz)
SELECT and STRBD low delay to IOEN low (contended access @ 12 MHz)
SELECT and STRBD low delay to IOEN low (uncontended access @ 12 MHz)
MEM/REG, RD/WR setup time following SELECT and STRBD low(@ 12 MHz)
TABLE FOR FIGURE 15. CPU READING RAM OR REGISTERS (SHOWN FOR 16-BIT, BUFFERED, NONZERO WAIT MODE)
MEM/REG, RD/WR setup time following SELECT and STRBD low(@ 16 MHz)
note 6ns35CLOCK IN rising edge delay to READYD fallingt13
ns∞READYD falling to STRBD rising release timet14
note 6ns30STRBD rising edge delay to IOEN rising edge and READYD rising edget15
note 6ns0Output Data hold time following STRBD rising edget16
ns40STRBD rising delay to output Data tri-statet17
ns0STRBD high hold time from READYD risingt18
ns60CLOCK IN rising edge delay to Output Data validt19
Notes for FIGURE 15 and associated table.
1. For the 16-bit buffered nonzero wait configuration, TRANSPA-
RENT/BUFFERED must be connected to logic "0". ZERO_WAIT
and DTREQ/16/8 must be connected to logic "1". The inputs
TRIGGER_SEL and MSB/LSB may be connected to either +5 V or
ground.
2. SELECT and STRBD may be tied together. IOEN goes low on
the first rising CLK edge when SELECT· STRBD is sampled low
(satisfying t1) and the BU-65170/61580's protocol/memory manage-
ment logic is not accessing the internal RAM. When this occurs,
IOEN goes low, starting the transfer cycle. After IOEN goes low,
SELECT may be released high.
3. MEM/REG must be presented high for memory access, low for
register access.
4. MEM/REG and RD/WR are buffered transparently until the first
falling edge of CLK after IOEN goes low. After this CLK edge,
MEM/REG and RD/WR become latched internally.
5. The logic sense for RD/WR in the diagram assumes that
POLARITY_SEL is connected to logic "1." If POLARITY_SEL is
connected to logic "0," RD/WR must be asserted low to read.
6. The timing for IOEN, READYD and D15-D0 assumes a 50 pf
load. For loading above 50 pf, the validity of IOEN, READYD, and
D15-D0 is delayed by an additional 0.14 ns/pf typ, 0.28 ns/pf max.
7. Timing for A15-A0, MEM/REG and SELECT assumes ADDR-LAT
is connected to logic "1." Refer to Address Latch timing for addition-
al details.
8. Internal RAM is accessed by A11 through A0 (A13 through A0 for
61585 and 61586). Registers are accessed by A4 through A0.
9. The address bus A15-A0 is internally buffered transparently until
the first rising edge of CLK after IOEN goes low. After this CLK
edge, A15-A0 become latched internally.
10. Setup time given for use in worst case timing calculations.
None of the ACE input signals are required to be synchronized to
the system clock. For ACE applications only, where SELECT and
STRBD do not meet the setup time of t1, but occur during the setup
window of an internal flip-flop, an additional clock cycle will be
inserted between the falling clock edge that latches MEM/REG and
RD/WR and the rising clock edge that latches the Address (A15-
A0). When this occurs, the pulse width of IOEN falling to READYD
falling (t11) increases by one clock cycle and the address hold time
(t10) must be increased be one clock cycle.
32
Data Device Corporation
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CLOCK IN
t1
t6
t7
t2
t3
t18
t16
VALID
t8 t9
t14
t15 t17
VALID
t12
t10
t4
t11
t5
VALID
t13
SELECT
(Note 2,7)
(Note 2)
(Note 3,4,7)
(Note 4,5)
STRBD
MEM/REG
RD/WR
IOEN
(Note 2,6)
(Note 6)
(Note 9,10)
(Note 7,8,9,10)
READYD
A15-A0
D15-D0
FIGURE 16. CPU WRITING RAM (SHOWN FOR 16-BIT, BUFFERED, NON-ZERO WAIT MODE)
33
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ns0STRBD valid high hold time from READYD rising edget18
note 6ns30STRBD rising edge delay to IOEN rising edge and READYD rising edget17
ns∞READYD falling to STRBD rising edge release timet16
note 6ns35CLOCK IN rising edge delay to READYD fallingt15
note 2ns0SELECT hold time following IOEN fallingt7
ns50Address valid setup time following SELECT and STRBD low (@ 12 MHz)t4
notes 2, 6
notes 2, 6ns128.3SELECT and STRBD low delay to IOEN low (uncontended access @ 12 MHz)t2
notes 7, 8, 9ns30Address valid setup time prior to CLOCK IN rising edget10
ns10Input Data valid setup time prior to CLOCK IN rising edget11
notes 9, 10ns30Input Data valid hold time following CLOCK IN rising edget13
notes 7, 8, 9, 10ns30Address valid hold time following to CLOCK IN rising edget12
notes 3, 4, 5, 7ns30MEM/REG, RD/WR hold time prior to CLOCK IN falling edget9
notes 6, 10
notes 6, 10
ns
ns
265
205
250
187.5
235
170
IOEN falling delay to READYD falling (@ 16 MHz)
IOEN falling delay to READYD falling (@ 16 MHz)
t14
t14
notes 3, 4, 5, 7ns10MEM/REG, RD/WR setup time prior to CLOCK IN falling edget8
note 6ns
ns
ns
35
70
50
CLOCK IN rising edge delay to IOEN falling edge
Input Data valid setup time following SELECT and STRBD low (@ 12 MHz)
Input Data valid setup time following SELECT and STRBD low (@ 16 MHz)
t6
t5
t5
ns30Address valid setup time following SELECT and STRBD low (@ 16 MHz)t4
notes 3, 4, 5, 7ns20MEM/REG, RD/WR setup time following SELECT and STRBD low(@ 12 MHz)t3
notes 3, 4, 5, 7ns10MEM/REG, RD/WR setup time following SELECT and STRBD low(@ 16 MHz)t3
notes 2, 6µs2.8SELECT and STRBD low delay to IOEN low (contended access @ 16 MHz)t2
notes 2, 6ns107.5SELECT and STRBD low delay to IOEN low (uncontended access @ 16 MHz)t2
notes 2, 10ns10
SELECT and STRBD low setup time prior to CLOCK IN rising edget1
NOTE REFERENCEUNITSMAXTYP
MIN
DESCRIPTIONREF
µs3.7SELECT and STRBD low delay to IOEN low (contended access @ 12 MHz)t2
TABLE FOR FIGURE 16. CPU WRITING RAM OR REGISTERS (SHOWN FOR 16-BIT, BUFFERED, NONZERO WAIT MODE)
Notes for FIGURE 16 and associated table.
1. For the 16-bit buffered nonzero wait configuration, TRANSPA-
RENT/BUFFERED must be connected to logic "0". ZERO_WAIT
and DTREQ/16/8 must be connected to logic "1". The inputs
TRIGGER_SEL and MSB/LSB may be connected to either +5 V or
ground.
2. SELECT and STRBD may be tied together. IOEN goes low on
the first rising CLK edge when SELECT·STRBD is sampled low
(satisfying t1) and the BU-65170/61580's protocol/memory manage-
ment logic is not accessing the internal RAM. When this occurs,
IOEN goes low, starting the transfer cycle. After IOEN goes low,
SELECT may be released high.
3. MEM/REG must be presented high for memory access, low for
register access.
4. MEM/REG and RD/WR are buffered transparently until the first
falling edge of CLK after IOEN goes low. After this CLK edge,
MEM/REG and RD/WR become latched internally.
5. The logic sense for RD/WR in the diagram assumes that
POLARITY_SEL is connected to logic "1." If POLARITY_SEL is
connected to logic "0," RD/WR must be asserted high to write.
6. The timing for IOEN, READYD and D15-D0 assumes a 50 pf
load. For loading above 50 pf, the validity of IOEN, READYD, and
D15-D0 is delayed by an additional 0.14 ns/pf typ, 0.28 ns/pf max.
7. Timing for A15-A0, MEM/REG and SELECT assumes ADDR-LAT
is connected to logic "1." Refer to Address Latch timing for addition-
al details.
8. Internal RAM is accessed by A11 through A0 (A13 through A0 for
61585 and 61586). Registers are accessed by A4 through A0.
9. The address bus A15-A0 is internally buffered transparently until
the first rising edge of CLK after IOEN goes low. After this CLK
edge, A15-A0 become latched internally.
10. Setup time given for use in worst case timing calculations.
None of the ACE input signals are required to be synchronized to
the system clock. For ACE applications only, where SELECT and
STRBD do not meet the setup time of t1, but occur during the setup
window of an internal flip-flop, an additional clock cycle will be
inserted between the falling clock edge that latches MEM/REG and
RD/WR and the rising clock edge that latches the Address (A15-A0)
and data (D15-D0). When this occurs, the pulse width of IOEN fall-
ing to READYD falling (t14) increases by one clock cycle and the
address hold time (t12 + t13) must be increased be one clock cycle.
34
Data Device Corporation
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T-6/09-0
SELECT
MSB/LSB
MEM/REG
(1) (2) (3) (4) (5)
(1) (2) (3) (4)
t4
t5
A15-A0
ADDR_LAT
SELECT
MSB/LSB
MEM/REG
A15-A0
INPUT
SIGNALS
INTERNAL
VALUES
t1
t3
t2
FIGURE 17. ADDRESS LATCH TIMING
Notes for FIGURE 17 and associated table.
1. Applicable to buffered mode only. Address SELECT AND MEM/REG latches are always transparent in the transparent mode of operation.
2. Latches are transparent when ADDR_LAT is high. Internal values do not update when ADDR_LAT is low.
3. MSB/LSB input signal is applicable to 8-bit mode only (16/8 input = logic “0”). MSB/LSB input is a “don’t care” for 16-bit operation.
TABLE FOR FIGURE 17. ADDRESS LATCH TIMING
REF DESCRIPTION MIN TYP MAX UNITS
t1 ADDR_LAT pulse width 20 ns
t2 ADDR_LAT high delay to internal signals valid 10 ns
t3 Propagation delay from external input signals to internal signals valid 10 ns
t5
t4
Input hold time following falling edge of ADDR_LAT
Input setup time prior to falling edge of ADDR_LAT
20
10
ns
ns
35
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INTERFACE TO MIL-STD-1553 BUS
FIGURE 18 illustrates the interface from the various versions of
the ACE series terminals to a 1553 bus. The figure also indicates
connections for both direct (short stub) and transformer (long
stub) coupling, plus the peak-to-peak voltage levels that appear
at various points (when transmitting).
TABLE 31 lists the characteristics of the required isolation trans-
formers for the various ACE terminals, the DDC and Beta
Transformer Technology Corporation corresponding part num-
ber, and the MIL (DESC) drawing number (if applicable). Beta
Transformer Technology is a direct subsidiary of DDC.
For both coupling configurations, the isolation transformer is the
transformer that interfaces directly to the ACE component. For
the transformer (long stub) coupling configuration, the trans-
former that interfaces the stub to the bus is the coupling trans-
former. The turns ratio of the isolation transformer varies,
depending upon the peak-to-peak output voltage of the specific
ACE terminal.
The transmitter voltage of each model of the BU-65170/61580
varies directly as a function of the power supply voltage. The
turns ratios of the respective transformers will yield a secondary
voltage of approximately 28 volts peak-to-peak on the outer taps
(used for direct coupling) and 20 volts peak-to-peak on the inner
taps (used for stub coupling).
In accordance with MIL-STD-1553B, the turns ratio of the cou-
pling transformer is 1.0 to 1.4. Both coupling configurations
require an isolation resistor to be in series with each leg connect-
ing to the 1553 bus; this protects the bus against short circuit
conditions in the transformers, stubs, or terminal components.
TABLE 31. ISOLATION TRANSFORMER GUIDE
RECOMMENDED XFORMER
TURNS RATIO
ACE PART
NUMBER SURFACE
MOUNT
PLUG-INXFORMER
COUPLED
DIRECT
COUPLED
BUS-25679,
B-2203,
M21038/27
-03
2:11.41:1
LPB-5001
LPB-5008
LPB-6001
LPB-6008
BUS-29854
B-2204,
M21038/27
-03
1:0.61.20:1
1.25:1
(Note 5)
See Table 32
1:1.791:2.5
BU-65170X1
BU-65171X1
BU-61580X1
BU-61581X1
BU-61585X1
BU-61586X1
BU-65170X3
BU-65171X3
BU-61580X3
BU-61581X3
BU-61585X3
BU-61586X3
BU-65170X6
BU-65171X6
BU-61580X6
BU-61581X6
BU-61585X6
BU-61586X6
BU-65170X2
BU-65171X2
BU-61580X2
BU-61581X2
BU-61585X2
BU-61586X2
B-2387
M21038/27
-12,
M21038/27
-17
LPB-5002
LPB-5009
LPB-6002
LPB-6009
B-2388
M21038/27
-13,
B-2334,
M21038/27
-18
Notes for TABLE 31 and FIGURE 18:
(1) Shown for one of two redundant buses that interface to the BU-65170 or
BU-61580.
(2) Transmitted voltage level on 1553 bus is 6 Vp-p min, 7 Vp-p nominal, 9 Vp-p
max.
(3) Required tolerance on isolation resistors is 2%. Instantaneous power dissipa-
tion (when transmitting) is approximately 0.5 W (typ), 0.8 W (max).
(4) Transformer pin numbering is correct for the DDC (e.g., BUS-25679) trans-
formers. For the Beta transformers (e.g., B-2203) or the QPL-21038-31 transform-
ers (e.g., M21038/27-02), the winding sense and turns ratio are mechanically the
same, but with reversed pin numbering; therefore, it is necessary to reverse pins
8 and 4 or pins 7 and 5 for the Beta or QPL transformers (Note: DDC transformer
part numbers begin with a BUS- prefix, while Beta transformer part numbers
begin with a B- prefix).
(5)The B-2204, B-2388, and B-2344 transformers have a slightly different turns
ratio on the direct coupled taps then the turns ratio of the BUS-29854 direct cou-
pled taps. They do, however, have the same transformer coupled ratio. For trans-
former coupled applications, either transformer may be used. The transcevier in
the BU-65170X2 and the BU-61580X2 was designed to work with a 1:0.83 ratio
for direct coupled applictions. For direct coupled applications, the 1.20:1 turns
ration is recommended, but the 1.25:1 may be used. The 1.25:1 turns ratio will
result in a slightly lower transmitter amplitude. (Approximateley 3.6% lower) and a
slight shift in the ACE's receiver threshold.
36
Data Device Corporation
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TRANSFORMERS
In selecting isolation transformers to be used with the X3, X6
ACE, there is a limitation on the maximum amount of leakage
inductance. If this limit is exceeded, the transmitter rise and fall
times may increase, possibly causing the bus amplitude to fall
below the minimum level required by MIL-STD-1553. In addition,
an excessive leakage imbalance may result in a transformer
dynamic offset that exceeds 1553 specifications.
The maximum allowable leakage inductance is 6.0 µH, and
is measured as follows:
The side of the transformer that connects to the ACE is defined
as the “primary” winding. If one side of the primary is shorted to
the primary center-tap, the inductance should be measured
across the “secondary” (stub side) winding. This inductance
must be less than 6.0 µH. Similarly, if the other side of the pri-
mary is shorted to the primary center-tap, the inductance mea-
sured across the “secondary” (stub side) winding must also be
less than 6.0 µH.
The difference between these two measurements is the
“differential” leakage inductance. This value must be less than
1.0 µH.
Beta Transformer Technology Corporation (BTTC), a subsidiary
of DDC, manufactures transformers in a variety of mechanical
configurations with the required turns ratios of 1:2.5 direct cou-
pled, and 1:1.79 transformer coupled. Table 32 provides a listing
of many of these transformers.For further information, contact
BTTC at 631-244-7393 or at www.bttc-beta.com.
Notes:
1. All Transformers in the table above can be used with BU-6XXXXX3/6 (1553B transceivers).
2. Transformers identified with "#" in the table above are not recommended for use with the BU-6XXXXX4 (McAir-Compatable transceivers)
TABLE 32. BTTC TRANSFORMERS FOR USE WITH X3, X6 ACE
BTTC PART
NUMBER
# OF CHANNELS,
CONFIGURATION
COUPLING RATIO
DESCRIPTION
COUPLING
RATIO (1:X) MOUNTING MAX HEIGHT
WIDTH
(INCLUDING
LEADS)
LENGTH
(INCLUDING
LEADS)
MLP-2005 Single Direct (1:2.5) SMT 0.185" 0.4" 0.52"
MLP-3005 Single Direct (1:2.5) Through Hole 0.185" 0.4" 0.4"
B-3230 (-30) # Single Direct (1:2.5) Through Hole 0.25" 0.35" 0.5"
MLP-2205 Single Transformer (1:1.79) SMT 0.185" 0.4" 0.52"
MLP-3205 Single Transformer (1:1.79) Through Hole 0.185" 0.4" 0.4"
B-3229 (-29) # Single Transformer (1:1.79) Through Hole 0.25" 0.35" 0.5"
HLP-6015 # Single Direct & Transformer (1:2.5) &
(1:1.79) SMT 0.19" 0.63" 1.13"
B-3227 (-27) # Single Direct & Transformer (1:2.5) &
(1:1.79) SMT 0.29" 0.63" 1.13"
MLP-3305 Single Direct & Transformer (1:2.5) &
(1:1.79) Through Hole 0.185" 0.4" 0.4"
B-3226 (-26) # Single Direct & Transformer (1:2.5) &
(1:1.79) Through Hole 0.25" 0.625" 0.625"
HLP-6014 # Single Direct & Transformer (1:2.5) &
(1:1.79) Flat Pack 0.19" 0.63" 1.13"
B-3231 (-31) # Single Direct & Transformer (1:2.5) &
(1:1.79) Flat Pack 0.29" 0.63" 1.13"
DSS-2005 Dual (Side-by-Side) Direct (1:2.5) SMT 0.13" 0.72" 0.96"
DSS-2205 Dual (Side-by-Side) Transformer (1:1.79) SMT 0.13" 0.72" 0.96"
DSS-1005 Dual (Side-by-Side) Direct & Transformer (1:2.5) &
(1:1.79) SMT 0.165" 0.72" 0.96"
TSM-2005 Dual (Stacked) Direct (1:2.5) SMT 0.32" 0.4" 0.52"
TSM-2205 Dual (Stacked) Transformer (1:1.79) SMT 0.32" 0.4" 0.52"
TST-9117 # Dual (Stacked) Direct & Transformer (1:2.5) &
(1:1.79) SMT 0.335" 1.125" 1.125"
TST-9107 # Dual (Stacked) Direct & Transformer (1:2.5) &
(1:1.79) Through Hole 0.335" 0.625" 0.625"
TST-9127 # Dual (Stacked) Direct & Transformer (1:2.5) &
(1:1.79) Flat Pack 0.335" 0.625" 0.625"
37
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T-6/09-0
BU-61580X1
55
1
2
3
8
4
1.4:1
39 VPP 28 VPP
1 FT MAX
1
2
3
7
5
2:1
20 VPP
1
8
3
1:1.4
COUPLING
TRANSFORMER
ISOLATION
TRANSFORMER
ISOLATION
TRANSFORMER
TRANSFORMER COUPLED (LONG STUB)
20 FT MAX
28 VPP
DIRECT COUPLED (SHORT STUB)
OR
COUPLING
TRANSFORMER
ISOLATION
TRANSFORMER
ISOLATION
TRANSFORMER
DIRECT COUPLED (SHORT STUB)
BU-61580X2
1
2
3
8
4
1:0.83
28 VPP
1 FT MAX
1
2
3
7
5
1:0.6
33 VPP 20 VPP
1
8
3
4
1:1.4
TRANSFORMER COUPLED (LONG STUB)
20 FT MAX
28 VPP
OR
COUPLING
TRANSFORMER
ISOLATION
TRANSFORMER
ISOLATION
TRANSFORMER
DIRECT COUPLED (SHORT STUB)
BU-61580X3
BU-61580X6
1
2
3
8
4
1:2.5
11.6 VPP 28 VPP
1
2
3
7
5
1:1.79
11.6 VPP 20 VPP
1
8
3
4
1:1.4
TRANSFORMER COUPLED (LONG STUB)
20 FT MAX
28 VPP
OR
55
Z0 (70 to 85 )
39 VPP
4
0.75 Z0
0.75 Z0
33 VPP
55
55
55
55
Z0 (70 to 85 )
0.75 Z0
0.75 Z0
0.75 Z0
0.75 Z0
1 FT MAX
FIGURE 18. BU-65170/61580 INTERFACE TO A 1553 BUS
Note: The BU-65170XX, BU-65171XX, BU-61581XX, BU-61585XX and BU-61586XX models are interfaced the same as the corresponding BU-61580XX model is shown
(i.e. The BU-65170X1 is interfaced the same as the BU-61580X1).
38
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TABLE 33. SIGNAL DESCRIPTIONS FOR BU-65170/61571, BU-61580/61585, BU-61586
(G, S or V PACKAGE)
PROCESSOR/MEMORY INTERFACE AND CONTROL (15)
SIGNAL NAME PIN DESCRIPTION
TRANSPARENT/
BUFFERED (1) 64 Used to select between the Transparent/ DMA mode (when strapped to logic 1) and the Buffered mode (when
strapped to logic 0) for the host processor interface.
STRBD (1) 4Strobe Data. Used with SELECT to initiate and control the data transfer cycle between the host processor and
the BU-65170/61580.
SELECT (1) 3Generally connected to a CPU address decoder output to select the BU-65170/61580 for a transfer to/from
either RAM or register. May be tied to STRBD.
MEM/REG (1) 5Memory/Register. Generally connected to either a CPU address line or address decoder output. Selects
between memory access (MEM/REG = 1 ) or register access (MEM/REG = 0 ).
RD/WR (1)
6
Read/Write. For host processor access, selects either reading or writing. In the 16-bit buffered mode, if polari-
ty select is logic ), then RD/WR is low (logic 0 ) for read accesses and high (logic 1 ) for write accesses. If
polarity select is logic 1 or the configuration of the interface is a mode other than 16-bit buffered mode, then
RD/WR is high (logic 1 ) for read accesses and low (logic 0 ) for write accesses.
IOEN (0) 67 Tri-state control for external address and data buffers. Generally not needed in the buffered mode. When low,
external buffers should be to allow the host processor access to the BU-65170/61580’s RAM and registers.
READYD (0)
66
Handshake output to host processor. For a nonzero wait state read access, signals that data ia available to be
read on D15 through D0. For a nonzero wait state write cycle, signals the completion of data transfer to a reg-
ister or RAM location In the buffered zero wait state mode, active high output signal (following the rising edge
of STRBD) used to indicate the latching of address and data (write only) and that an internal transfer between
the address/data latches and the RAM/registers is on-going.
INT (O)
65
Interrupt request output. If the LEVEL/PULSE interrupt bit (bit 3) of Configuration Register #2 is low, a negative
pulse of approximately 500 ns in width is output on INT. If bit 3 is high, a low level interrupt request output will
be asserted on INT.
DTREQ (O)
/16/8 (I) 31
Data Transfer Request or 16-bit/8-bit Transfer Mode Select. In transparent mode, active low output signal used
to request access to the processor interface bus (address,data, and control buses). In buffered mode, input sig-
nal used to select between the 16-bit data transfer mode (16/8 = logic 1) and the 8 bit data transfer mode (16/8
= logic 0).
DTGRT (I) /MSB/LSB (I)
26
Data Transfer Grant or Most Significant Byte/Least Significant Byte. In transparent mode, active low input signal
asserted, in response to the DTREQ output, to indicate that access to the processor buses has been granted
to the BU-65170/61580. In 8-bit buffered mode, input signal used to indicate which byte is being transferred
(MSB or LSB). The POLARITY_SEL input controls the logic sense of MSB/LSB. (Note: only the 8-bit buffered
mode uses MSB/LSB.) See description of POLARITY_SEL signal. N/C in 16-bit buffered mode.
DTACK (O)/
POLARITY_SEL (I)
32
Data Transfer Acknowledge or Polarity Select. In transparent mode, active low output signal used to indicate
acceptance of the processor interface bus in response to a data transfer grant (DTGRT).In 16-bit buffered
mode (TRANSPARENT/ BUFFERED = logic 0 and 16/8 = logic 1), input signal used to control the logic sense
of the RD/WR signal. When POLARITY_SEL is logic 1, RD/WR must be asserted high (logic 1) for a read
operation and low (logic 0) for a write operation. When POLARITY_SEL is logic 0, RD/WR must be asserted
low (logic 0) for a read operation and high (logic 1) for a write operation.In 8-bit buffered mode
(TRANSPARENT/BUFFERED = logic 0 and 16/8 = logic 0), input signal used to control the logic sense of the
MSB/LSB signal. When POLARITY_SEL is logic 0, MSB/LSB must be asserted low (logic 0) to indicate the
transfer of the least significant byte and high (logic 1) to indicate the transfer of the most significant byte. When
POLARITY_SEL is logic 1, MSB/LSB must be asserted high (logic 1) to indicate the transfer of the least signifi-
cant byte and low (logic 0) to indicate the transfer of the most significant byte.
MEMENA-OUT (O) 28 Memory Enable Output. Asserted low during both host processor and 1553 protocol/memory management
memory transfer cycles. Used as a memory chip select (CS) signal for external RAM in the transparent mode.
MEMENA-IN (I)
/TRIGGER_SEL (I)
33
Memory Enable Input or Trigger Select. In transparent mode, MEMENA-IN is an active low Chip Select (CS)
input to the 4K x 16 of internal shared RAM. When only using internal RAM, connect directly to MEMENA-OUT.
In 8-bit buffered mode, the input signal (TRIGGER_SEL) indicates the order of byte pairs transfer to or from the
BU-65170/61580 by the host processor. This signal has no operation (can be N/C) in the 16-bit buffered mode.
In the 8-bit buffered mode, TRIGGER_SEL should be asserted high (logic 1) if the byte order for both read
operations and write operations is MSB followed by LSB. TRIGGER_SEL should be asserted low (logic 0) if the
byte order for both read operations and write operations is LSB followed by MSB.
MEMOE (O)/ ADDR_
LAT (I) 29
Memory Output Enable or Address Latch. In transparent mode, MEMOE output will be used to enable data out-
puts for external RAM read cycles (normally connected to the OE signal on external RAM chips). In buffered
mode, ADDR_LAT input will be used to configure the internal address latches in latched mode (when low) or
transparent mode (when high).
MEMWR (O) /ZERO_
WAIT (I) 30
Memory Write or Zero Wait State. In transparent mode, active low output signal (MEMWR ) will be asserted low
during memory write transfers to strobe data into internal or external RAM (normally connected to the WR sig-
nal on external RAM chips). In buffered mode, input signal (ZERO_WAIT) will be used to select between the
zero wait mode (ZERO_WAIT = logic 0) and the nonzero wait mode (ZERO_WAIT = logic 1).
39
Data Device Corporation
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BU-65170/61580/61585
T-6/09-0
TABLE 33. SIGNAL DESCRIPTIONS FOR BU-65170/61571, BU-61580/61585, BU-61586
(G, S or V PACKAGE) (CONTINUED)
MISCELLANEOUS (7)
Option for BU-65170/61580X6 and the BU-61585X6. Inhibits (disables) the respective (A/B) MIL-STD-1553 transmitter
when asserted to logic “1.”
36
70TX_INH_A (I)
External Time Tag Clock input. Use may be designated by bits 7, 8, and 9 of Configuration Register #2. When used it
increments the internal Time Tag Register/Counter. If not used, should be connected to +5V or ground.
63
TAG_CLK (I)
27
SSFLAG (I)/
EXT_TRIG (I)
45
INCMD (O)
Master Clear. Negative true Reset input, normally asserted low following power turn-on. Requires a minimum 100ns nega-
tive pulse to reset all internal logic to its “power turn-on” state.
7
MSTCLR (I)
16MHz (or 12MHz) clock input.19CLOCK IN (I)
DESCRIPTIONPINSIGNAL NAME
In Command. In BC mode, asserted low throughout processing cycle for each message. In RT mode or Message Monitor
mode, asserted low following receipt of Command Word and kept low until completion of current message sequence. In
Word Monitor mode, goes low following MONITOR START command, kept low while monitor is on-line, goes high follow-
ing RESET command.
Subsystem Flag or External Trigger input. In the Remote Terminal mode, asserting this input , will set the Subsystem Flag
bit in the BU-65170/61580's RT Status Word. A low on the SSFLAG input overrides a logic “1" of the respective bit (bit 8)
of Configuration Register #1. In the Bus Controller mode, an enabled external BC Start option (bit 7 of Configuration
Register #1) and a low-to-high transition on this input will issue a BC Start command, starting execution of the current BC
frame. In the Word Monitor mode, an enabled external trigger (bit 7 of Configuration Register #1) and a low-to-high transi-
tion on this input will issue a monitor trigger.
TX_INH_B (I)
POWER AND GROUND (8)
-15(-12)VB
CH. B Transceiver Ground37GNDB
CH. B +5V Supply38
CH. B -15V(-12V) Supply*36
+5VB
CH. A Transceiver Ground69GNDA
CH. A +5V Supply68+5VA
CH. A -15V(-12V) Supply*70-15(-12)VA
Logic Ground18LOGIC GND
Logic +5V Supply54+5V LOGIC
DESCRIPTIONPINSIGNAL NAME
RT ADDRESS (6)
RTADP (I) 44
39RTAD0 (LSB) (I)
40RTAD1 (I)
Remote Terminal Address Inputs
41RTAD2 (I)
42RTAD3 (I)
43RTAD4 (MSB) (I)
DESCRIPTIONPINSIGNAL NAME
NOTE: * No Connects (N/Cs) for BU-65170/61580 and TX_INH input for BU-65170/61580X6.
Remote Terminal Address Parity. Must provide odd parity sum with RTAD4-RTAD0 in order for the RT to respond to non-
broadcast commands.
1553 ISOLATION TRANSFORMER INTERFACE (4)
Analog Transmit/Receive Input/Outputs. Connect directly to 1553 isolation transformers.
35TX/RX-B (I/O)
34TX/RX-B (I/O)
2TX/RX-A (I/O)
1TX/RX-A (I/O)
DESCRIPTIONPINSIGNAL NAME
40
Data Device Corporation
www.ddc-web.com
BU-65170/61580/61585
T-6/09-0
TABLE 33. SIGNAL DESCRIPTIONS FOR BU-65170/61571, BU-61580/61585, BU-61586
(G, S or V PACKAGE) (CONTINUED)
ADDRESS BUS (16)
A04
A10
21
13
16-bit bidirectional address bus. In both the buffered and transparent modes, the host CPU accesses the BU-65170/61580
registers and 4K words of internal RAM by A11 through A0 (BU-61585 uses A13 through A0). The host CPU performs regis-
ter selection by A4 through A0.In the buffered mode, A15-A0 are inputs only. In the transparent mode, A15-A0 are inputs dur-
ing CPU accesses and drive outward (towards the CPU) when the 1553 protocol/memory management logic accesses up to
64K x 16 of external RAM. The address bus drives outward only in the transparent when the signal DTACK is low (indicating
that the 61580 has control of the processor interface bus) and IOEN is high (indicating that this is not a CPU access). Most of
the time, including immediately after power turn-on RESET, the A15-A0 outputs will be in their disabled (high impedance)
state.
25
20
12
A00
A05
A11
24
17
11
A01
A06
A12
23
16
10
A02
A07
A13
22
15
9
A03
A08
A14
14
8
A09
A15 (MSB)
DESCRIPTION
16-bit bidirectional data bus. This bus interfaces the host processor to the internal registers and 4K words of RAM(12K of
RAM for the BU-61585). In addition, in the transparent mode, this bus allows data transfers to take place between the
internal protocol/memory management logic and up to 64K x 16 of external RAM. Most of the time, the outputs for D15
through D0 are in their high impedance state. They drive outward in the buffered or transparent mode when the host
CPU reads the internal RAM or registers. Or, in the trasparent mode, when the protocol/memory management logic is
accessing (either reading or writing) internal RAM or writing to external RAM.
46
D10
D00
47D01
48D02
49D03
D04 50
51D05
52D06
53D07
55D08
56
57
D09
58D11
59D12
60D13
61D14
62D15 (MSB)
DATA BUS (16)
DESCRIPTION
PINSIGNAL NAME
SIGNAL NAME PIN
41
Data Device Corporation
www.ddc-web.com
BU-65170/61580/61585
T-6/09-0
TX/RX-B -VA (see note)
TX/RX-B GNDA34 69
+5VA33 68
DTACK/POLARITY_SEL IOEN32 67
DTREQ/16/8 READYD31 66
MEMWR/ZERO_WAIT INT30 65
MEMOE/ADDR_LAT TRANSPARENT/BUFFERED29 64
MEMENA_OUT TAG_CLK28 63
SSFLAG/EXT_TRIG D1527 62
DTGRT/MSB/LSB D1426 61
A00 D1325 60
A01 D1224 59
A02 D1123 58
A03 D1022 57
A04 D0921 56
A05 D0820 55
CLK +5V Logic19 54
GND D0718 53
A06 D0617 52
A07 D0516 51
D04A0815 50
A09 D0314 49
A10 D0213 48
A11 D0112 47
A12 D0011 46
A13 INCMD10 45
A14 RTADP9 44
A15 RTAD48 43
MSTCLR RTAD37 42
RD/WR RTAD26 41
MEM/REG RTAD15 40
STRBD RTAD04 39
SELECT +5VB3 38
TX/RX-A GNDB2 37
TX/RX-A -VB (see note)1 36
NAME NAMEPIN
35 70
Notes:
-15V for BU-65170/61580X1.
-12V for BU-65170/61580X2.
N/C for BU-65170/61580X3.
For BU-65170/61580X6.
pin 36 is TX_INH_B
pin 70 is TX_INH_A
MEMENA_IN/TRIGGER_SEL
PIN
TABLE 34. BU-65170/65171, BU-61580/61581/61585/61586
PIN LISTINGS
(G, S or V PACKAGE)
42
Data Device Corporation
www.ddc-web.com
BU-65170/61580/61585
T-6/09-0
1.000 MAX
(25.4)
0.400
(10.16)
1.700 (43.18)
INDEX
DENOTES
PIN 1
0.215 (5.46) MAX FOR "D" PACKAGE
0.165 (4.19) MAX FOR "S" PACKAGE
NOTES:
1. DIMENSIONS ARE IN INCHES (MILLIMETERS).
2. PACKAGE MATERIAL: ALUMINA (AL2O3).
3. LEAD MATERIAL: KOVAR, PLATED BY 150 MINIMUM NICKEL, PLATED BY 50 MINIMUM GOLD.
1.900 MAX
(48.26)
0.180 ±0.010 TYP
(4.57 ±0.25)
0.100 (2.54)
0.100 (2.54) TYP
0.050 (1.27) TYP
0.600
(15.24)
0.018 ±0.002 DIA TYP
(0.46 ±0.05)
34
35
36
37 69
70
2
TOP VIEW
BOTTOM VIEW
INDEX
DENOTES
PIN 1
1.900 (48.26) MAX
SIDE VIEW
FIGURE 19. BU-65170/65171/61580/61581/61585/61586S MECHANICAL OUTLINE
43
Data Device Corporation
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BU-65170/61580/61585
T-6/09-0
70 36
351
0.018 0.002 TYP
(0.46 0.05)
1.900 MAX
(48.26)
34 EQ SP @ 0.050 = 1.700
(43.18) (1.27) TOL NONCUM
0.050 TYP
(1.27)
0.400 MIN TYP
(10.18)
INDEX DENOTES PIN 1 1.000 MAX
(25.4)
0.215 (5.46) MAX
For "F" Package
0.150 (3.81) MAX
For "V" Package
0.010 0.002 TYP
(0.254 0.051)
0.070 0.010
(1.78)
PIN NUMBERS
FOR REF ONLY
TOP VIEW SIDE VIEW
NOTES:
1. DIMENSIONS ARE IN INCHES (MILLIMETERS).
2. PACKAGE MATERIAL: ALUMINA (AL2O3).
3. LEAD MATERIAL: KOVAR, PLATED BY 150 MINIMUM NICKEL, PLATED BY 50 MINIMUM GOLD.
FIGURE 20. BU-65170/65171/61580/61581/61585/61586V MECHANICAL OUTLINE
44
Data Device Corporation
www.ddc-web.com
BU-65170/61580/61585
T-6/09-0
70
3635
1
1.000 (MAX)
1.900 MAX
0.018 0.002
PIN 1 DENOTED BY
INDEX MARK
0.050 TYP
34 EQ. SP. @
0.050 = 1.700
(TOL. NONCUM)
PIN NUMBERS ARE
FOR REF. ONLY
0.080 MIN
0.190 0.010
0.040 TYP
0.050 MIN
0.012 MAX
1.024 MAX
1.38 0.02
0.065 (REF)
0.010 0.002
0.150 MAX
VIEW "A"
VIEW "A"
0.006 -0.004,+0.010
(0.152 +0.10,-0.254)
FIGURE 21. BU-65170/65171/61580/61581/61585/61586G MECHANICAL OUTLINE
45
Data Device Corporation
www.ddc-web.com
BU-65170/61580/61585
T-6/09-0
ORDERING INFORMATION
BU-XXXXXXX-XXXX
Supplemental Process Requirements:
S = Pre-Cap Source Inspection
L = 100% Pull Test
Q = 100% Pull Test and Pre-Cap Source Inspection
K = One Lot Date Code
W = One Lot Date Code and Pre-Cap Source Inspection
Y = One Lot Date Code and 100% Pull Test
Z = One Lot Date Code, Pre-Cap Source Inspection and 100% Pull Test
Blank = None of the Above
Test Criteria:
0 = Standard Testing
1 = X-Ray
2 = MIL-STD-1760 Amplitude Compliant - Applies to +5 Volt Transceiver Option Only
3 = MIL-STD-1760 and X-Ray
Process Requirements:
0 = Standard DDC practices, no Burn-In (See following page.)
1 = MIL-PRF-38534 Compliant (See Note 4)
2 = B (See Note 2)
3 = MIL-PRF-38534 Compliant (See Note 4) with PIND Testing
4 = MIL-PRF-38534 Compliant (See Note 4) with Solder Dip
5 = MIL-PRF-38534 Compliant (See Note 4) with PIND Testing and Solder Dip
6 = B (See Note 2) with PIND Testing
7 = B (See Note 2) with Solder Dip
8 = B (See Note 2) with PIND Testing and Solder Dip
9 = Standard DDC Processing with Solder Dip, no Burn-In (See following page.)
Temperature Range/Data Requirements:
1 = -55°C to +125°C
2 = -40°C to +85°C
3 = 0°C to +70°C
4 = -55°C to +125°C with Variables Test Data
5 = -40°C to +85°C with Variables Test Data
8 = 0°C to +70°C with Variables Test Data
Voltage/Transceiver Option:
0 = Transceiverless
1 = +5 Volts and -15 Volts (1760 Compliant - Standard Configuration)
2 = +5 Volts and -12 Volts
3 = +5 Volts only ( See Test Criteria - 1760 Compliant with option -XX2)
6 = +5 Volts only with TX Inhibit inputs brought out on negative supply pins
Package Type:
G = “Gull Wing” (Formed Lead)
J = J Lead
P = PGA
S = Small DIP
V = Very Small Flat Pack
Product Type:
65170 = 70-pin RT
65171 = 70-pin RT with Latchable RT Address Option
61580 = 70-pin BC/RT/MT
61581 = 70-pin BC/RT/MT with Latchable RT address Option
61585 = 70-pin BC/RT/MT 8K x 17 with RAM
61586 = 70-pin BC/RT/MT 8K x 17 with RAM and RT Address Option
Notes:
(1) The ACE series is also available to DESC drawing number 5962-93065.
(2) Standard DDC Processing with burn-in and full temperature test, see table on following page.
(3) The above products contain tin-lead solder finish as applicable to solder dip requirements.
(4) MIL-PRF-38534 product grading is designated with the following dash numbers:
Class H is a -11X, 13X, 14X, 15X, 41X, 43X, 44X, 45X
Class G is a -21X, 23X, 24X, 25X, 51X, 53X, 54X, 55X
Class D is a -31X, 33X, 34X, 35X, 81X, 83X, 84X, 85X
46
T-6/09-0 PRINTED IN THE U.S.A.
DA T A DEVICE CORPORATION
REGISTERED T O ISO 9001:2000
FILE NO . A5976
R
E
G
I
S
T
E
R
E
D
F
I
R
M
®
U
The information in this data sheet is believed to be accurate; however, no responsibility is
assumed by Data Device Corporation for its use, and no license or rights are
granted by implication or otherwise in connection therewith.
Specifications are subject to change without notice.
Please visit our Web site at www.ddc-web.com for the latest information.
105 Wilbur Place, Bohemia, New York, U.S.A. 11716-2426
For Technical Support - 1-800-DDC-5757 ext. 7771
Headquarters, N.Y., U.S.A. - Tel: (631) 567-5600, Fax: (631) 567-7358
United Kingdom - Tel: +44-(0)1635-811140, Fax: +44-(0)1635-32264
France - Tel: +33-(0)1-41-16-3424, Fax: +33-(0)1-41-16-3425
Germany - Tel: +49-(0)8141-349-087, Fax: +49-(0)8141-349-089
Japan - Tel: +81-(0)3-3814-7688, Fax: +81-(0)3-3814-7689
World Wide Web - http://www.ddc-web.com
TABLE 11015 (note 1), 1030 (note 2)
BURN-IN
Notes:
1. For Process Requirement "B*" (refer to ordering information), devices may be non-compliant with MIL-
STD-883, Test Method 1015, Paragraph 3.2. Contact factory for details.
2. When applicable.
3000g2001CONSTANT ACCELERATION
C1010TEMPERATURE CYCLE
A and C1014SEAL
—2009, 2010, 2017, and 2032INSPECTION
CONDITION(S)METHOD(S)
MIL-STD-883
TEST
STANDARD DDC PROCESSING
FOR HYBRID AND MONOLITHIC HERMETIC PRODUCTS
RECORD OF CHANGE
For BU-65170/61580 Data Sheet
Revision Date Pages Description
P 4/2009 3
Moved Differential Input Capacitance value from
Max to Typ in Spec Table
R 5/2009 5
Change in note 6, Maximum Capacitance changed
to Typical Capacitance
T 6/2009 36 Replaced Table 32
