DAC7617
Quad, Serial Input, 12-Bit, Voltage Output
DIGITAL-TO-ANALOG CONVERTER
FEATURES
● LOW POWER: 3mW
●SETTLING TIME: 10µs to 0.012%
● 12-BIT LINEARITY AND MONOTONICITY:
–40°C to +85°C
● DOUBLE-BUFFERED DATA INPUTS
● SO-16 or SSOP-20 PACKAGES
● SINGLE-SUPPLY +3V OPERATION
APPLICATIONS
● PROCESS CONTROL
● ATE PIN ELECTRONICS
● CLOSED-LOOP SERVO-CONTROL
● MOTOR CONTROL
● DATA ACQUISITION SYSTEMS
● DAC-PER-PIN PROGRAMMERS
DESCRIPTION
The DAC7617 is a quad, serial input, 12-bit, voltage
output Digital-to-Analog Converter (DAC) with guar-
anteed 12-bit monotonic performance over the –40°C
to +85°C temperature range. An asynchronous reset
clears all registers to either mid-scale (800H) or zero-
scale (000H), selectable via the RESETSEL pin. The
individual DAC inputs are double buffered to allow
for simultaneous update of all DAC outputs. The
device is powered from a single +3V supply.
Low power and small size makes the DAC7617 ideal
for automatic test equipment, DAC-per-pin program-
mers, data acquisition systems, and closed-loop servo-
control. The device is available in SO-16 and
SSOP-20 packages and is guaranteed over the
–40°C to +85°C temperature range.
DAC A
DAC
Register A
Input
Register A
DAC B
DAC
Register B
Input
Register B
DAC C
DAC
Register C
Input
Register C
DAC D
DAC
Register D
Input
Register D
V
REFH
V
DD
AGND
V
OUTD
V
OUTC
V
OUTB
V
OUTA
V
REFL
LDAC
GND
CLK
CS
12
SDI
RESETRESETSELLOADREG
Serial-to-
Parallel
Shift
Register
DAC
Select
DAC7617
®
DAC7617
Copyright © 2001, Texas Instruments Incorporated SBAS185 Printed in U.S.A. February, 2001
www.ti.com
2DAC7617
SBAS185
SPECIFICATIONS
At TA = –40°C to +85°C, VDD = +3V, VREFH = +1.25V, and VREFL = 0V, unless otherwise noted.
✻ Specification same as DAC7617E, U.
NOTES: (1) Specification applies at code 00AH and above. (2) LSB means Least Significant Bit, with VREFH equal to +1.25V and VREFL equal to 0V, one LSB
is 0.305mV. (3) All DAC outputs will match within the specified error band. (4) Ideal output voltage does not take into account zero or full-scale error.
DAC7617E, U DAC7617EB, UB
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
ACCURACY
Linearity Error(1) ±2±1 LSB(2)
Linearity Matching(3) ±2±1 LSB
Differential Linearity Error ±1±1 LSB
Monotonicity 12 ✻Bits
Zero-Scale Error Code = 00AH±2.4 ✻mV
Zero-Scale Drift 510 ✻✻ppm/°C
Zero-Scale Matching(3) ±1±2✻±1.2 mV
Full-Scale Error Code = FFFH±2.4 ✻mV
Full-Scale Matching(3) ±1±2✻±1.2 mV
Power Supply Rejection 30 ✻ppm/V
ANALOG OUTPUT
Voltage Output(4) VREFL VREFH ✻✻V
Output Current –625 +625 ✻✻µA
Load Capacitance No Oscillation 100 ✻pF
Short-Circuit Current +8, –2 ✻mA
Short-Circuit Duration
Indefinite
✻
REFERENCE INPUT
VREFH Input Range 0 +1.25 ✻✻V
VREFL Input Range 0 ✻V
DYNAMIC PERFORMANCE
Settling Time To ±0.012% 5 10 ✻✻ µs
Channel-to-Channel Crosstalk Full-Scale Step 0.1 ✻LSB
On Any Other DAC
Output Noise Voltage Bandwidth: 0Hz to 1MHz 65 ✻nV/√Hz
DIGITAL INPUT/OUTPUT
Logic Family CMOS ✻
Logic Levels
VIH | IIH | ≤ 10µAV
DD • 0.7 VDD ✻✻V
VIL | IIL | ≤ 10µA –0.3 VDD • 0.3 ✻✻V
Data Format Straight Binary ✻
POWER SUPPLY REQUIREMENTS
VDD 3.0 3.3 3.6 ✻✻✻ V
IDD 0.8 1 ✻✻ mA
Power Dissipation 2.4 3 ✻✻ mW
TEMPERATURE RANGE
Specified Performance –40 +85 ✻✻°C
3
DAC7617
SBAS185
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
ABSOLUTE MAXIMUM RATINGS(1)
VDD to GND ........................................................................ –0.3V to +5.5V
VREFL to GND ........................................................... –0.3V to (VDD + 0.3V)
VDD to VREFH .......................................................................... –0.3V to VDD
VREFH to VREFL ........................................................................–0.3V to VDD
Digital Input Voltage to GND...................................... –0.3V to VDD + 0.3V
Maximum Junction Temperature ................................................... +150°C
Operating Temperature Range ......................................... –40°C to +85°C
Storage Temperature Range .......................................... –65°C to +150°C
Lead Temperature (soldering, 10s) ............................................... +300°C
NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
PACKAGE/ORDERING INFORMATION
MAXIMUM MAXIMUM
LINEARITY DIFFERENTIAL PACKAGE SPECIFICATION
ERROR LINEARITY DRAWING TEMPERATURE ORDERING TRANSPORT
PRODUCT (LSB) (LSB) PACKAGE NUMBER RANGE NUMBER(1) MEDIA
DAC7617U ±2±1 SO-16 211 –40°C to +85°C DAC7617U Rails
"" """ "DAC7617U/1K Tape and Reel
DAC7617UB ±1±1 SO-16 211 –40°C to +85°C DAC7617UB Rails
"" """ "DAC7617UB/1K Tape and Reel
DAC7617E ±2±1 SSOP-20 334 –40°C to +85°C DAC7617E Rails
"" """ "DAC7617E/1K Tape and Reel
DAC7617EB ±1±1 SSOP-20 334 –40°C to +85°C DAC7617EB Rails
"" """ "DAC7617EB/1K Tape and Reel
NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces
of “DAC7617EB/1K” will get a single 1000-piece Tape and Reel.
4DAC7617
SBAS185
PIN CONFIGURATION—U Package
Top View SO
PIN CONFIGURATION—E Package
Top View SSOP
PIN DESCRIPTIONS—E Package
PIN LABEL DESCRIPTION
1V
DD Positive Analog Supply Voltage, +3V nominal.
2V
OUTD DAC D Voltage Output
3V
OUTC DAC C Voltage Output
4V
REFL Reference Input Voltage Low. Sets minimum out-
put voltage for all DACs.
5 NIC Not Internally Connected.
6 NIC Not Internally Connected.
7V
REFH Reference Input Voltage High. Sets maximum out-
put voltage for all DACs.
8V
OUTB DAC B Voltage Output
9V
OUTA DAC A Voltage Output
10 AGND Analog Ground
11 GND Ground
12 SDI Serial Data Input
13 CLK Serial Data Clock
14 CS Chip Select Input
15 NIC Not Internally Connected.
16 NIC Not Internally Connected.
17 LDAC All DAC registers becomes transparent when LDAC
is LOW. They are in the latched state when LDAC
is HIGH.
18 LOADREG The selected input register becomes transparent
when LOADREG is LOW. It is in the latched state
when LOADREG is HIGH.
19 RESET Asynchronous Reset Input. Sets all DAC registers
to either zero-scale (000H) or mid-scale (800H)
when LOW. RESETSEL determines which code is
active.
20 RESETSEL When LOW, a LOW on RESET will cause all DAC
registers to be set to code 000H. When RESETSEL
is HIGH, a LOW on RESET will set the registers to
code 800H.
PIN DESCRIPTIONS—U Package
PIN LABEL DESCRIPTION
1V
DD Positive Analog Supply Voltage, +3V nominal.
2V
OUTD DAC D Voltage Output
3V
OUTC DAC C Voltage Output
4V
REFL Reference Input Voltage Low. Sets minimum out-
put voltage for all DACs.
5V
REFH Reference Input Voltage High. Sets maximum out-
put voltage for all DACs.
6V
OUTB DAC B Voltage Output
7V
OUTA DAC A Voltage Output
8 AGND Analog Ground
9 GND Ground
10 SDI Serial Data Input
11 CLK Serial Data Clock
12 CS Chip Select Input
13 LDAC All DAC registers become transparent when LDAC
is LOW. They are in the latched state when LDAC
is HIGH.
14 LOADREG The selected input register becomes transparent
when LOADREG is LOW. It is in the latched state
when LOADREG is HIGH.
15 RESET Asynchronous Reset Input. Sets DAC and input
registers to either zero-scale (000H) or mid-scale
(800H) when LOW. RESETSEL determines which
code is active.
16 RESETSEL When LOW, a LOW on RESET will cause the DAC
and input registers to be set to code 000H. When
RESETSEL is HIGH, a LOW on RESET will set the
registers to code 800H.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DD
V
OUTD
V
OUTC
V
REFL
V
REFH
V
OUTB
V
OUTA
AGND
RESETSEL
RESET
LOADREG
LDAC
CS
CLK
SDI
GND
DAC7617U
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
DD
V
OUTD
V
OUTC
V
REFL
NIC
NIC
V
REFH
V
OUTB
V
OUTA
AGND
RESETSEL
RESET
LOADREG
LDAC
NIC
NIC
CS
CLK
SDI
GND
DAC7617E
5
DAC7617
SBAS185
TYPICAL PERFORMANCE CURVES
At TA = +25°C, VDD = +3V, VREFH = +1.25V, and VREFL = 0V, representative unit, unless otherwise specified.
0.50
0.25
0
–0.25
–0.50
0.50
0.25
0
–0.25
–0.50
LE (LSB)DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, +25°C)
000
H
200
H
400
H
600
H
800
H
Digital Input Code
A00
H
C00
H
E00
H
FFF
H
0.50
0.25
0
–0.25
–0.50
0.50
0.25
0
–0.25
–0.50
LE (LSB)DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, +85°C)
000
H
200
H
400
H
600
H
800
H
Digital Input Code
A00
H
C00
H
E00
H
FFF
H
0.50
0.25
0
–0.25
–0.50
0.50
0.25
0
–0.25
–0.50
LE (LSB)DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, –40°C)
000
H
200
H
400
H
600
H
800
H
Digital Input Code
A00
H
C00
H
E00
H
FFF
H
0.50
0.25
0
–0.25
–0.50
0.50
0.25
0
–0.25
–0.50
LE (LSB)DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC B, +25°C)
000
H
200
H
400
H
600
H
800
H
Digital Input Code
A00
H
C00
H
E00
H
FFF
H
0.50
0.25
0
–0.25
–0.50
0.50
0.25
0
–0.25
–0.50
LE (LSB)DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC B, +85°C)
000
H
200
H
400
H
600
H
800
H
Digital Input Code
A00
H
C00
H
E00
H
FFF
H
0.50
0.25
0
–0.25
–0.50
0.50
0.25
0
–0.25
–0.50
LE (LSB)DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC B, –40°C)
000
H
200
H
400
H
600
H
800
H
Digital Input Code
A00
H
C00
H
E00
H
FFF
H
6DAC7617
SBAS185
TYPICAL PERFORMANCE CURVES
At TA = +25°C, VDD = +3V, VREFH = +1.25V, and VREFL = 0V, representative unit, unless otherwise specified.
0.50
0.25
0
–0.25
–0.50
0.50
0.25
0
–0.25
–0.50
LE (LSB)DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC C, +25°C)
000
H
200
H
400
H
600
H
800
H
Digital Input Code
A00
H
C00
H
E00
H
FFF
H
0.50
0.25
0
–0.25
–0.50
0.50
0.25
0
–0.25
–0.50
LE (LSB)DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC C, +85°C)
000
H
200
H
400
H
600
H
800
H
Digital Input Code
A00
H
C00
H
E00
H
FFF
H
0.50
0.25
0
–0.25
–0.50
0.50
0.25
0
–0.25
–0.50
LE (LSB)DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC C, –40°C)
000
H
200
H
400
H
600
H
800
H
Digital Input Code
A00
H
C00
H
E00
H
FFF
H
0.50
0.25
0
–0.25
–0.50
0.50
0.25
0
–0.25
–0.50
LE (LSB)DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC D, +25°C)
000
H
200
H
400
H
600
H
800
H
Digital Input Code
A00
H
C00
H
E00
H
FFF
H
0.50
0.25
0
–0.25
–0.50
0.50
0.25
0
–0.25
–0.50
LE (LSB)DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC D, +85°C)
000
H
200
H
400
H
600
H
800
H
Digital Input Code
A00
H
C00
H
E00
H
FFF
H
0.50
0.25
0
–0.25
–0.50
0.50
0.25
0
–0.25
–0.50
LE (LSB)DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC D, –40°C)
000
H
200
H
400
H
600
H
800
H
Digital Input Code
A00
H
C00
H
E00
H
FFF
H
7
DAC7617
SBAS185
TYPICAL PERFORMANCE CURVES
At TA = +25°C, VDD = +3V, VREFH = +1.25V, and VREFL = 0V, representative unit, unless otherwise specified.
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
Temperature (°C)
–40 –30 –10 0–20 10 20 40 5030 70 80 9060
NEGATIVE FULL-SCALE ERROR vs TEMPERATURE
Negative Full-Scale Error (mV)
DAC A
DAC D
DAC C
DAC B
Code (0040
H
)Code (000
H
)2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
Temperature (°C)
–40 –30 –10 0–20 10 20 40 5030 70 80 9060
POSITIVE FULL-SCALE ERROR vs TEMPERATURE
Positive Full-Scale Error (mV)
DAC A
DAC D
DAC C
DAC B
Code (0040
H
)Code (FFF
H
)
0.000
0.050
–0.100
–0.150
–0.200
Digital Input Code
000
H
400
H
200
H
600
H
A00
H
800
H
E00
H
FFF
H
C00
H
V
REFL
CURRENT vs CODE
V
REF
Current (mA)
0.200
0.150
0.100
0.050
0.000
Digital Input Code
000
H
400
H
200
H
600
H
A00
H
800
H
E00
H
FFF
H
C00
H
V
REFH
CURRENT vs CODE
V
REF
Current (mA)
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
Digital Input Code
000
H
400
H
200
H
600
H
800
H
C00
H
A00
H
E00
H
FFF
H
SUPPLY CURRENT vs DIGITAL INPUT CODE
I
DD
(mA)
No Load
10
8
6
4
2
0
–2
–4
Input Code
000
H
400
H
200
H
600
H
800
H
C00
H
A00
H
E00
H
FFF
H
SUPPLY CURRENT LIMIT vs INPUT CODE
I
OUT
(mA)
Short to V
DD
Short to Ground
8DAC7617
SBAS185
1000
900
800
700
600
500
400
300
200
100
0
Temperature (°C)
–40 0–20 20 40 60 80 100
POWER SUPPLY CURRENT vs TEMPERATURE
Quiescent Current (uA)
3.0
2.5
2.0
1.5
1.0
0.5
0.0
R
LOAD
(kΩ)
0.01 0.1 1 10 100
OUTPUT VOLTAGE vs R
LOAD
V
OUT
(V)
Source
Sink
Time (2µs/div)
OUTPUT VOLTAGE vs SETTLING TIME
(0V to +1.25V)
Large-Signal Output (0.5V/div)
Small-Signal Error (1mV/div)
LDAC (5.0V/div)
Time (2µs/div)
OUTPUT VOLTAGE vs SETTLING TIME
(+1.25V to 0V)
Large-Signal Output (0.5V/div)
Small-Signal Error (1mV/div)
LDAC (5.0V/div)
Time (1µs/div)
MID-SCALE GLITCH PERFORMANCE
(CODE 7FF
H
to 800
H
)
LDAC (5.0V/div)
Glitch Waveform (20mV/div)
Time (1µs/div)
MID-SCALE GLITCH PERFORMANCE
(CODE 800
H
to 7FF
H
)
LDAC (5.0V/div)
Glitch Waveform (20mV/div)
TYPICAL PERFORMANCE CURVES
At TA = +25°C, VDD = +3V, VREFH = +1.25V, and VREFL = 0V, representative unit, unless otherwise specified.
9
DAC7617
SBAS185
120
100
80
60
40
20
0
Frequency (Hz)
100 1k 10k 100k 1M
OUTPUT NOISE VOLTAGE vs FREQUENCY
Noise (nV/√Hz)
Code FFF
H
TYPICAL PERFORMANCE CURVES
At TA = +25°C, VDD = +3V, VREFH = +1.25V, and VREFL = 0V, representative unit, unless otherwise specified.
Time (100µs/div)
WIDEBAND NOISE
(Bandwidth = 10kHz)
Noise Voltage (20µV/div)
10 DAC7617
SBAS185
THEORY OF OPERATION
The DAC7617 is a quad, serial input, 12-bit, voltage output
DAC. The architecture is a classic R-2R ladder configuration
followed by an operational amplifier that serves as a buffer.
Each DAC has its own R-2R ladder network and output op
amp, but all share the reference voltage inputs. The minimum
voltage output (“zero-scale”) and maximum voltage output
(“full-scale”) are set by external voltage references (VREFL
and VREFH, respectively). The digital input is a 16-bit serial
word that contains the 12-bit DAC code and a 2-bit address
code that selects one of the four DACs (the two remaining
bits are unused). The converter can be powered from a single
+3V supply. Each device offers a reset function which imme-
diately sets all DAC output voltages and internal registers to
either zero-scale (code 000H) or mid-scale (code 800H). The
reset code is selected by the state of the RESETSEL pin
(LOW = 000H, HIGH = 800H). See Figure 1 for the basic
operation of the DAC7617.
ANALOG OUTPUTS
The output of the DAC7617 can swing to ground. Note that
the settling time of the output op amp will be longer with
voltages very near ground. Additionally, care must be taken
when measuring the zero-scale error. If the output amplifier
has a negative offset, the output voltage may not change for
the first few digital input codes (000H, 001H, 002H, etc.)
since the output voltage cannot swing below ground.
The behavior of the output amplifier can be critical in some
applications. Under short-circuit conditions (DAC output
shorted to VDD), the output amplifier can sink a great deal
more current than it can source. See the Specifications Table
for more details concerning short-circuit current.
FIGURE 1. Basic Single-Supply Operation of the DAC7617.
NOTE: (1) U package pin configuration shown. (2) As configured, RESET LOW sets all internal registers
to code 000
H
(0V). If RESETSEL is HIGH, RESET LOW sets all internal registers to code 800
H
(1.25V).
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DD
V
OUTD
V
OUTC
V
REFL
V
REFH
V
OUTB
V
OUTA
AGND
RESETSEL
RESET
LOADREG
LDAC
CS
CLK
SDI
GND
Reset DACs
(2)
Update Selected Register
Update All DAC Registers
Chip Select
Clock
Serial Data In
DAC7617
(1)
0.1µF
0.1µF
0V to +1.25V
1µF to 10µF
+3V
+
0V to +1.25V
0V to +1.25V
0V to +1.25V
+1.25V
11
DAC7617
SBAS185
REFERENCE INPUTS
The minimum output of each DAC is equal to VREFL plus
a small offset voltage (essentially, the offset of the output
op amp). The maximum output is equal to VREFH – 1LSBplus
a similar offset voltage.
The current into the reference inputs depends on the DAC
output voltages and can vary from a few microamps to
approximately 0.4 milliamp. Bypassing the reference volt-
age or voltages with a 0.1µF capacitor placed as close as
possible to the DAC7617 package is strongly recommended.
DIGITAL INTERFACE
Figure 2 and Table I provide the basic timing for the
DAC7617. The interface consists of a serial clock (CLK),
serial data (SDI), a load register signal (LOADREG), and a
“load all DAC registers” signal (LDAC). In addition, a chip
select (CS) input is available to enable serial communication
when there are multiple serial devices. An asynchronous
reset input (RESET) is provided to simplify start-up condi-
tions, periodic resets, or emergency resets to a known state.
SYMBOL DESCRIPTION MIN TYP MAX UNITS
tDS
Data Valid to CLK Rising
25 ns
tDH
Data Held Valid after CLK Rises
20 ns
tCH
CLK HIGH
30 ns
tCL
CLK LOW
50 ns
tCSS
CS LOW to CLK Rising
55 ns
tCSH
CLK HIGH to CS Rising
15 ns
tLD1
LOADREG HIGH to CLK Rising
40 ns
tLD2
CLK Rising to LOADREG LOW
15 ns
tLDRW
LOADREG LOW Time
45 ns
tLDDW
LDAC LOW Time
45 ns
tRSSH
RESETSEL Valid to RESET LOW
25 ns
tRSTW
RESET LOW Time
70 ns
tS
Settling Time
10 µs
FIGURE 2. DAC7617 Timing.
The DAC code and address are provided via a 16-bit serial
interface, as shown in Figure 2. The first two bits select the
input register that will be updated when LOADREG goes
LOW (see Table II). The next two bits are not used. The last
12 bits are the DAC code which is provided, most significant
bit first.
TABLE I. Timing Specifications (TA = –40°C to +85°C).
A1
(MSB) (LSB)
SDI
CLK
CS
LOADREG
A0 X X D11 D10 D9 D3 D2 D1 D0
SDI
CLK
LDAC
RESET
V
OUT
tcss
t
LD1
t
CL
t
CH
t
DS
t
DH
t
LD2
t
LDRW
t
LDDW
t
S
t
RSTW
t
RSSH
t
CSH
t
S
1 LSB
ERROR BAND 1 LSB
ERROR BAND
RESETSEL
12 DAC7617
SBAS185
If both CS and CLK are used, then CS should rise only when
CLK is HIGH. If not, then either CS or CLK can be used to
operate the shift register. See Table III for more information.
The digital data into the DAC7617 is double-buffered. This
allows new data to be entered for each DAC without disturb-
ing the analog outputs. When the new settings have been
entered into the device, all of the DAC outputs can be
updated simultaneously. The transfer from the input regis-
ters to the DAC registers is accomplished with a HIGH to
LOW transition on the LDAC input. It is possible to keep
this pin LOW and update each DAC via LOADREG be-
cause the DAC registers become transparent when LDAC is
LOW. However, as each new data word is entered into the
device, the corresponding output will update immediately
when LOADREG is taken LOW.
Digital Input Coding
The DAC7617 input data is in Straight Binary format. The
output voltage is given by the following equation:
where N is the digital input code (in decimal). This equation
does not include the effects of offset (zero-scale) or gain
(full-scale) errors.
STATE OF
SELECTED SELECTED STATE OF
INPUT INPUT ALL DAC
A1 A0 LOADREG LDAC RESET REGISTER REGISTER REGISTERS
L(1) LLH
(2) H A Transparent Latched
L H L H H B Transparent Latched
H L L H H C Transparent Latched
H H L H H D Transparent Latched
X(3) X H L H NONE (All Latched) Transparent
X X H H H NONE (All Latched) Latched
X X X X L ALL Reset(4) Reset(4)
NOTES: (1) L = Logic LOW. (2) H = Logic HIGH. (3) X = Don’t Care. (4) Resets to either 000H or 800H, per the RESETSEL state (LOW = 000H, HIGH = 800H).
When RESET rises, all registers that are in their latched state retain the reset value.
CS(1) CLK(1) LOADREG RESET SERIAL SHIFT REGISTER
H(2) X(3) H H No Change
L(4) L H H No Change
L↑(5) H H Advanced One Bit
↑L H H Advanced One Bit
H(6) XL
(7) H No Change
H(6) XHL
(8) No Change
NOTES: (1) CS and CLK are interchangeable. (2) H = Logic HIGH. (3) X
= Don’t Care. (4) L = Logic LOW (5) = Positive Logic Transition. (6) A HIGH
value is suggested in order to avoid a “false clock” from advancing the shift
register and changing the shift register. (7) If data is clocked into the serial
register while LOADREG is LOW, the selected input register will change
as the shift register bits “flow” through A1 and A0. This will corrupt the data
in each input register that has been erroneously selected. (8) RESET LOW
causes no change in the contents of the serial shift register.
TABLE II. Control Logic Truth Table.
TABLE III. Serial Shift Register Truth Table.
Note that CS and CLK are combined with an OR gate and
the output controls the serial-to-parallel shift register inter-
nal to the DAC7617 (see the block diagram on the front of
this data sheet). These two inputs are completely inter-
changeable. In addition, care must be taken with the state of
CLK when CS rises at the end of a serial transfer. If CLK is
LOW when CS rises, the OR gate will provide a rising edge
to the shift register, shifting the internal data one additional
bit. The result will be incorrect data and possible selection of
the wrong input register.
(VREFH – VREFL) • N
4096
VOUT = VREFL +
13
DAC7617
SBAS185
LAYOUT
A precision analog component requires careful layout, ad-
equate bypassing, and clean, well-regulated power supplies.
As the DAC7617 offers single-supply operation, it will often
be used in close proximity with digital logic, microcontrollers,
microprocessors, and digital signal processors. The more
digital logic present in the design and the higher the switch-
ing speed, the more difficult it will be to keep digital noise
from appearing at the converter output.
Due to the DAC7617’s single ground pin, all return currents,
including digital and analog return currents, must flow
through the GND pin. Ideally, GND would be connected
directly to an analog ground plane. This plane would be
separate from the ground connection for the digital compo-
nents until they were connected at the power entry point of
the system (see Figure 3).
The power applied to VDD should be well regulated and low
noise. Switching power supplies and DC/DC converters will
often have high-frequency glitches or spikes riding on the
output voltage. In addition, digital components can create
similar high-frequency spikes as their internal logic switches
states. This noise can easily couple into the DAC output
voltage through various paths between the power connec-
tions and analog output.
As with the GND connection, VDD should be connected to
a +3V power supply plane or trace that is separate from the
connection for digital logic until they are connected at the
power entry point. In addition, the 1µF to 10µF and 0.1µF
capacitors shown in Figure 3 are strongly recommended. In
some situations, additional bypassing may be required, such
as a 100µF electrolytic capacitor or even a π filter made up
of inductors and capacitors—all designed to essentially low-
pass filter the +3V supply, removing the high-frequency
noise (see Figure 3).
FIGURE 3. Suggested Power and Ground Connections for a DAC7617 Sharing a +3V Supply with a Digital System.
+3V
Power Supply
Optional
Digital Circuits
DAC7617
Other
Analog
Components
+3V
100µF1µF to
10µF
Ground
+3V
Ground
V
DD
AGND
0.1µF
++
PACKAGE OPTION ADDENDUM
www.ti.com 30-Jul-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
DAC7617E ACTIVE SSOP DB 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
DAC7617E/1K ACTIVE SSOP DB 20 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
DAC7617E/1KG4 ACTIVE SSOP DB 20 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
DAC7617EB ACTIVE SSOP DB 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
DAC7617EB/1K ACTIVE SSOP DB 20 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
DAC7617EB/1KG4 ACTIVE SSOP DB 20 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
DAC7617EBG4 ACTIVE SSOP DB 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
DAC7617EG4 ACTIVE SSOP DB 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
DAC7617U ACTIVE SOIC DW 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
DAC7617UB ACTIVE SOIC DW 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
DAC7617UBG4 ACTIVE SOIC DW 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
DAC7617UG4 ACTIVE SOIC DW 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
PACKAGE OPTION ADDENDUM
www.ti.com 30-Jul-2011
Addendum-Page 2
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
DAC7617E/1K SSOP DB 20 1000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1
DAC7617EB/1K SSOP DB 20 1000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DAC7617E/1K SSOP DB 20 1000 367.0 367.0 38.0
DAC7617EB/1K SSOP DB 20 1000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All
semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time
of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components which meet ISO/TS16949 requirements, mainly for automotive use. Components which
have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such
components to meet such requirements.
Products Applications
Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive
Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications
Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers
DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps
DSP dsp.ti.com Energy and Lighting www.ti.com/energy
Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial
Interface interface.ti.com Medical www.ti.com/medical
Logic logic.ti.com Security www.ti.com/security
Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense
Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video
RFID www.ti-rfid.com
OMAP Mobile Processors www.ti.com/omap TI E2E Community e2e.ti.com
Wireless Connectivity www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2012, Texas Instruments Incorporated
