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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

AM4372, AM4376, AM4377, AM4378, AM4379

SPRS851D –JUNE 2014–REVISED SEPTEMBER 2016

AM437x Sitara™ Processors

1 Device Overview

1.1 Features

• Highlights

– Sitara™ ARM®Cortex®-A9 32-Bit RISC

Processor With Processing Speed up to

1000 MHz

• NEON™ SIMD Coprocessor and Vector

Floating Point (VFPv3) Coprocessor

• 32KB of Both L1 Instruction and Data Cache

• 256KB of L2 Cache or L3 RAM

– 32-Bit LPDDR2, DDR3, and DDR3L Support

– General-Purpose Memory Support (NAND,

NOR, SRAM) Supporting up to 16-Bit ECC

– SGX530 Graphics Engine

– Display Subsystem

– Programmable Real-Time Unit Subsystem and

Industrial Communication Subsystem (PRU-

ICSS)

– Real-Time Clock (RTC)

– Up to Two USB 2.0 High-Speed Dual-Role

(Host or Device) Ports With Integrated PHY

– 10, 100, and 1000 Ethernet Switch Supporting

up to Two Ports

– Serial Interfaces:

• Two Controller Area Network (CAN) Ports

• Six UARTs, Two McASPs, Five McSPIs,

Three I2C Ports, One QSPI, and One HDQ

or 1-Wire

– Security

• Crypto Hardware Accelerators (AES, SHA,

RNG, DES, and 3DES)

• Secure Boot (Avaliable Only on AM437x

High-Security [AM437xHS] Devices)

– Two 12-Bit Successive Approximation Register

(SAR) ADCs

– Up to Three 32-Bit Enhanced Capture (eCAP)

Modules

– Up to Three Enhanced Quadrature Encoder

Pulse (eQEP) Modules

– Up to Six Enhanced High-Resolution PWM

(eHRPWM) Modules

• MPU Subsystem

– ARM Cortex-A9 32-Bit RISC Microprocessor

With Processing Speed up to 1000 MHz

– 32KB of Both L1 Instruction and Data Cache

– 256KB of L2 Cache (Option to Configure as L3

RAM)

– 256KB of On-Chip Boot ROM

– 64KB of On-Chip RAM

– Secure Control Module (SCM) (Avaliable Only

on AM437xHS Devices)

– Emulation and Debug

• JTAG

• Embedded Trace Buffer

– Interrupt Controller

• On-Chip Memory (Shared L3 RAM)

– 256KB of General-Purpose On-Chip Memory

Controller (OCMC) RAM

– Accessible to All Masters

– Supports Retention for Fast Wakeup

– Up to 512KB of Total Internal RAM

(256KB of ARM Memory Configured as L3 RAM

+ 256KB of OCMC RAM)

• External Memory Interfaces (EMIFs)

– DDR Controllers:

• LPDDR2: 266-MHz Clock (LPDDR2-533

Data Rate)

• DDR3 and DDR3L: 400-MHz Clock (DDR-

800 Data Rate)

• 32-Bit Data Bus

• 2GB of Total Addressable Space

• Supports One x32, Two x16, or Four x8

Memory Device Configurations

• General-Purpose Memory Controller (GPMC)

– Flexible 8- and 16-Bit Asynchronous Memory

Interface With up to Seven Chip Selects (NAND,

NOR, Muxed-NOR, and SRAM)

– Uses BCH Code to Support 4-, 8-, or 16-Bit

ECC

– Uses Hamming Code to Support 1-Bit ECC

• Error Locator Module (ELM)

– Used With the GPMC to Locate Addresses of

Data Errors From Syndrome Polynomials

Generated Using a BCH Algorithm

– Supports 4-, 8-, and 16-Bit Per 512-Byte Block

Error Location Based on BCH Algorithms

• Programmable Real-Time Unit Subsystem and

Industrial Communication Subsystem (PRU-ICSS)

– Supports Protocols such as EtherCAT®,

PROFIBUS®, PROFINET®, and EtherNet/IP™,

EnDat 2.2, and More

– Two Programmable Real-Time Units (PRUs)

Subsystems With Two PRU Cores Each

• Each Core is a 32-Bit Load and Store RISC

Processor Capable of Running at 200 MHz

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• 12KB (PRU-ICSS1), 4KB (PRU-ICSS0) of

Instruction RAM With Single-Error Detection

(Parity)

• 8KB (PRU-ICSS1), 4KB (PRU-ICSS0) of

Data RAM With Single-Error Detection

(Parity)

• Single-Cycle 32-Bit Multiplier With 64-Bit

Accumulator

• Enhanced GPIO Module Provides Shift-In

and Shift-Out Support and Parallel Latch on

External Signal

– 12KB (PRU-ICSS1 Only) of Shared RAM With

Single-Error Detection (Parity)

– Three 120-Byte Register Banks Accessible by

Each PRU

– Interrupt Controller Module (INTC) for Handling

System Input Events

– Local Interconnect Bus for Connecting Internal

and External Masters to the Resources Inside

the PRU-ICSS

– Peripherals Inside the PRU-ICSS

• One UART Port With Flow Control Pins,

Supports up to 12 Mbps

• One eCAP Module

• Two MII Ethernet Ports that Support

Industrial Ethernet, such as EtherCAT

• One MDIO Port

– Industrial Communication is Supported by Two

PRU-ICSS Subsystems

• Power, Reset, and Clock Management (PRCM)

Module

– Controls the Entry and Exit of Deep-Sleep

Modes

– Responsible for Sleep Sequencing, Power

Domain Switch-Off Sequencing, Wake-Up

Sequencing, and Power Domain Switch-On

Sequencing

– Clocks

• Integrated High-Frequency Oscillator Used

to Generate a Reference Clock (19.2, 24, 25,

and 26 MHz) for Various System and

Peripheral Clocks

• Supports Individual Clock Enable and

Disable Control for Subsystems and

Peripherals to Facilitate Reduced Power

Consumption

• Five ADPLLs to Generate System Clocks

(MPU Subsystem, DDR Interface, USB, and

Peripherals [MMC and SD, UART, SPI, I2C],

L3, L4, Ethernet, GFX [SGX530], and LCD

Pixel Clock)

– Power

• Two Nonswitchable Power Domains (RTC

and Wake-Up Logic [WAKE-UP])

• Three Switchable Power Domains (MPU

Subsystem, SGX530 [GFX], Peripherals and

Infrastructure [PER])

• Dynamic Voltage Frequency Scaling (DVFS)

• Real-Time Clock (RTC)

– Real-Time Date (Day, Month, Year, and Day of

Week) and Time (Hours, Minutes, and Seconds)

Information

– Internal 32.768-kHz Oscillator, RTC Logic, and

1.1-V Internal LDO

– Independent Power-On-Reset

(RTC_PWRONRSTn) Input

– Dedicated Input Pin (RTC_WAKEUP) for

External Wake Events

– Programmable Alarm Can Generate Internal

Interrupts to the PRCM for Wakeup or Cortex-

A9 for Event Notification

– Programmable Alarm Can Be Used With

External Output (RTC_PMIC_EN) to Enable the

Power-Management IC to Restore Non-RTC

Power Domains

• Peripherals

– Up to Two USB 2.0 High-Speed Dual-Role

(Host or Device) Ports With Integrated PHY

– Up to Two Industrial Gigabit Ethernet MACs

(10, 100, and 1000 Mbps)

• Integrated Switch

• Each MAC Supports MII, RMII, and RGMII

and MDIO Interfaces

• Ethernet MACs and Switch Can Operate

Independent of Other Functions

• IEEE 1588v2 Precision Time Protocol (PTP)

– Up to Two CAN Ports

• Supports CAN Version 2 Parts A and B

– Up to Two Multichannel Audio Serial Ports

(McASPs)

• Transmit and Receive Clocks up to 50 MHz

• Up to Four Serial Data Pins Per McASP Port

With Independent TX and RX Clocks

• Supports Time Division Multiplexing (TDM),

Inter-IC Sound (I2S), and Similar Formats

• Supports Digital Audio Interface

Transmission (SPDIF, IEC60958-1, and

AES-3 Formats)

• FIFO Buffers for Transmit and Receive

(256 Bytes)

– Up to Six UARTs

• All UARTs Support IrDA and CIR Modes

• All UARTs Support RTS and CTS Flow

Control

• UART1 Supports Full Modem Control

– Up to Five Master and Slave McSPIs

• McSPI0–McSPI2 Support up to Four Chip

Selects

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• McSPI3 and McSPI4 Support up to Two

Chip Selects

• Up to 48 MHz

– One Quad-SPI

• Supports eXecute In Place (XIP) from Serial

NOR FLASH

– One Dallas 1-Wire®and HDQ Serial Interface

– Up to Three MMC, SD, and SDIO Ports

• 1-, 4-, and 8-Bit MMC, SD, and SDIO Modes

• 1.8- or 3.3-V Operation on All Ports

• Up to 48-MHz Clock

• Supports Card Detect and Write Protect

• Complies With MMC4.3 and SD and SDIO

2.0 Specifications

– Up to Three I2C Master and Slave Interfaces

• Standard Mode (up to 100 kHz)

• Fast Mode (up to 400 kHz)

– Up to Six Banks of General-Purpose I/O (GPIO)

• 32 GPIOs per Bank (Multiplexed With Other

Functional Pins)

• GPIOs Can be Used as Interrupt Inputs (up

to Two Interrupt Inputs per Bank)

– Up to Three External DMA Event Inputs That

Can Also be Used as Interrupt Inputs

– Twelve 32-Bit General-Purpose Timers

• DMTIMER1 is a 1-ms Timer Used for

Operating System (OS) Ticks

• DMTIMER4–DMTIMER7 are Pinned Out

– One Public Watchdog Timer

– One Free-Running, High-Resolution 32-kHz

Counter (synctimer32K)

– One Secure Watchdog Timer (Avaliable Only on

AM437xHS Devices)

– SGX530 3D Graphics Engine

• Tile-Based Architecture Delivering up to 20M

Poly/sec

• Universal Scalable Shader Engine is a

Multithreaded Engine Incorporating Pixel and

Vertex Shader Functionality

• Advanced Shader Feature Set in Excess of

Microsoft VS3.0, PS3.0, and OGL2.0

• Industry Standard API Support of Direct3D

Mobile, OGL-ES 1.1 and 2.0, and OpenVG

1.0

• Fine-Grained Task Switching, Load

Balancing, and Power Management

• Advanced Geometry DMA-Driven Operation

for Minimum CPU Interaction

• Programmable High-Quality Image Anti-

Aliasing

• Fully Virtualized Memory Addressing for OS

Operation in a Unified Memory Architecture

– Display Subsystem

• Display Modes

– Programmable Pixel Memory Formats

(Palletized: 1-, 2-, 4-, and 8-Bits Per

Pixel; RGB 16- and 24-Bits Per Pixel; and

YUV 4:2:2)

– 256- × 24-Bit Entries Palette in RGB

– Up to 2048 × 2048 Resolution

• Display Support

– Four Types of Displays Are Supported:

Passive and Active Colors; Passive and

Active Monochromes

– 4- and 8-Bit Monochrome Passive Panel

Interface Support (15 Grayscale Levels

Supported Using Dithering Block)

– RGB 8-Bit Color Passive Panel Interface

Support (3,375 Colors Supported for

Color Panel Using Dithering Block)

– RGB 12-, 16-, 18-, and 24-Bit Active

Panel Interface Support (Replicated or

Dithered Encoded Pixel Values)

– Remote Frame Buffer (Embedded in the

LCD Panel) Support Through the RFBI

Module

– Partial Refresh of the Remote Frame

Buffer Through the RFBI Module

– Partial Display

– Multiple Cycles Output Format on 8-, 9-,

12-, and 16-Bit Interface (TDM)

• Signal Processing

– Overlay and Windowing Support for One

Graphics Layer (RGB or CLUT) and Two

Video Layers (YUV 4:2:2, RGB16, and

RGB24)

– RGB 24-Bit Support on the Display

Interface, Optionally Dithered to RGB

18‑Bit Pixel Output Plus 6-Bit Frame Rate

Control (Spatial and Temporal)

– Transparency Color Key (Source and

Destination)

– Synchronized Buffer Update

– Gamma Curve Support

– Multiple-Buffer Support

– Cropping Support

– Color Phase Rotation

– Two 12-Bit SAR ADCs (ADC0, ADC1)

• 867K Samples Per Second

• Input Can Be Selected from Any of the Eight

Analog Inputs Multiplexed Through an 8:1

Analog Switch

• ADC0 Can Be Configured to Operate as a

4‑, 5-, or 8-Wire Resistive Touch Screen

Controller (TSC)

– Up to Three 32-Bit eCAP Modules

• Configurable as Three Capture Inputs or

Three Auxiliary PWM Outputs

– Up to Six Enhanced eHRPWM Modules

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• Dedicated 16-Bit Time-Base Counter With

Time and Frequency Controls

• Configurable as Six Single-Ended, Six Dual-

Edge Symmetric, or Three Dual-Edge

Asymmetric Outputs

– Up to Three 32-Bit eQEP Modules

• Device Identification

– Factory Programmable Electrical Fuse Farm

(FuseFarm)

• Production ID

• Device Part Number (Unique JTAG ID)

• Device Revision (Readable by Host ARM)

• Security Keys (Avaliable Only on AM437xHS

Devices)

• Feature Identification

• Debug Interface Support

– JTAG and cJTAG for ARM (Cortex-A9 and

PRCM) and PRU-ICSS Debug

– Supports Real-Time Trace Pins (for Cortex-A9)

– 64-KB Embedded Trace Buffer (ETB)

– Supports Device Boundary Scan

– Supports IEEE 1500

• DMA

– On-Chip Enhanced DMA Controller (EDMA) Has

Three Third-Party Transfer Controllers (TPTCs)

and One Third-Party Channel Controller

(TPCC), Which Supports up to 64

Programmable Logical Channels and Eight

QDMA Channels

– EDMA is Used for:

• Transfers to and from On-Chip Memories

• Transfers to and from External Storage

(EMIF, GPMC, and Slave Peripherals)

• InterProcessor Communication (IPC)

– Integrates Hardware-Based Mailbox for IPC and

Spinlock for Process Synchronization Between

the Cortex-A9, PRCM, and PRU-ICSS

• Boot Modes

– Boot Mode is Selected Through Boot

Configuration Pins Latched on the Rising Edge

of the PWRONRSTn Reset Input Pin

• Camera

– Dual Port 8- and 10-Bit BT656 Interface

– Dual Port 8- and 10-Bit Including External Syncs

– Single Port 12-Bit

– YUV422/RGB422 and BT656 Input Format

– RAW Format

– Pixel Clock Rate up to 75 MHz

• Package

– 491-Pin BGA Package (17-mm × 17-mm) (ZDN

Suffix), 0.65-mm Ball Pitch With Via Channel

Array Technology to Enable Low-Cost Routing

1.2 Applications

• Patient Monitoring

• Navigation Equipment

• Industrial Automation

• Portable Data Terminals

• Bar Code Scanners

• Point of Service

• Portable Mobile Radios

• Test and Measurement

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(1) For more information, see Section 7,Mechanical, Packaging, and Orderable Information.

1.3 Description

The TI AM437x high-performance processors are based on the ARM Cortex-A9 core.

The processors are enhanced with 3D graphics acceleration for rich graphical user interfaces, as well as a

coprocessor for deterministic, real-time processing including industrial communication protocols, such as

EtherCAT, PROFIBUS, EnDat, and others. The devices support high-level operating systems (HLOS).

Linux®is available free of charge from TI. Other HLOSs are available from TI's Design Network and

ecosystem partners.

These devices offer an upgrade to systems based on lower performance ARM cores and provide updated

peripherals, including memory options such as QSPI-NOR and LPDDR2.

The processors contain the subsystems shown in Figure 1-1, and a brief description of each follows.

The processor subsystem is based on the ARM Cortex-A9 core, and the PowerVR SGX™ graphics

accelerator subsystem provides 3D graphics acceleration to support display and advanced user interfaces.

The programmable real-time unit subsystem and industrial communication subsystem (PRU-ICSS) is

separate from the ARM core and allows independent operation and clocking for greater efficiency and

flexibility. The PRU-ICSS enables additional peripheral interfaces and real-time protocols such as

EtherCAT, PROFINET, EtherNet/IP, PROFIBUS, Ethernet Powerlink, Sercos, EnDat, and others. The

PRU-ICSS enables EnDat and another industrial communication protocol in parallel. Additionally, the

programmable nature of the PRU-ICSS, along with their access to pins, events and all system-on-chip

(SoC) resources, provides flexibility in implementing fast real-time responses, specialized data handling

operations, custom peripheral interfaces, and in off-loading tasks from the other processor cores of the

SoC.

High-performance interconnects provide high-bandwidth data transfers for multiple initiators to the internal

and external memory controllers and to on-chip peripherals. The device also offers a comprehensive

clock-management scheme.

One on-chip analog to digital converter (ADC0) can couple with the display subsystem to provide an

integrated touch-screen solution. The other ADC (ADC1) can combine with the pulse width module to

create a closed-loop motor control solution.

The RTC provides a clock reference on a separate power domain. The clock reference enables a battery-

backed clock reference.

The camera interface offers configuration for a single- or dual-camera parallel port.

Cryptographic acceleration is available in every AM437x device. Secure boot is available only on

AM437xHS devices for anticloning and illegal software update protection. For more information about

secure boot and HS devices, contact your TI sales representative.

Table 1-1. Device Information(1)

PART NUMBER PACKAGE BODY SIZE

AM4372ZDN NFBGA (491) 17.0 mm × 17.0 mm

AM4376ZDN NFBGA (491) 17.0 mm × 17.0 mm

AM4377ZDN NFBGA (491) 17.0 mm × 17.0 mm

AM4378ZDN NFBGA (491) 17.0 mm × 17.0 mm

AM4379ZDN NFBGA (491) 17.0 mm × 17.0 mm

ARM

Cortex-A9

Up to 1000 MHz

32KB, 32KB L1

256KB L2, L3 RAM

64KB RAM

Graphics

PowerVR

SGX

3D GFX

20 MTri/s

Crypto

256KB

L3 RAM

Touch Screen Controller (TSC)(A)

Display

Quad Core

PRU-ICSS

EtherCAT,

PROFINET,

EtherNet/IP,

EnDat

and more

L3 and L4 Interconnect

I C x3

UART x6

System Interface

EDMA

Timers x12

WDT

RTC

eHRPWM x6

eQEP, eCAP x3

JTAG, ETB

EMAC

2-port switch

10, 100, 1G

with 1588

(MII, RMII,

RGMII

and MDIO)

32b LPDDR2, DDR3, DDR3L(B)

NAND, NOR, Async

(16-bit ECC)

Memory Interface

Processing: Overlay,

Resizing,Color Space

Conversion, and more

SPI x5

QSPI

CAN x2

HDQ, 1-Wire

ADC0 (8 inputs)

12-bit SAR(A)

GPIO

Camera Interface

(2x Parallel)

MMC, SD,

SDIO x3

USB 2.0 Dual-Role

+ PHY x2

McASP x2

(4ch)

24-bit LCDCtrl (WXGA)

Simplified Power

Sequencing

ADC1 (8 inputs)

12-bit SAR

Secure Boot

(HS device only)

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1.4 Functional Block Diagram

A. Use of TSC limits available ADC0 inputs.

B. Maximum clock: LPDDR2 = 266 MHz; DDR3/DDR3L = 400 MHz.

Figure 1-1. Functional Block Diagram

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Table of Contents

1 Device Overview ......................................... 1

1.1 Features .............................................. 1

1.2 Applications........................................... 4

1.3 Description............................................ 5

1.4 Functional Block Diagram ............................ 6

2 Revision History ......................................... 8

3 Device Comparison ..................................... 9

3.1 Related Products.................................... 10

4 Terminal Configuration and Functions ............ 11

4.1 Pin Diagrams........................................ 11

4.2 Pin Attributes........................................ 21

4.3 Signal Descriptions.................................. 65

5 Specifications ......................................... 103

5.1 Absolute Maximum Ratings........................ 103

5.2 ESD Ratings ....................................... 105

5.3 Power-On Hours (POH) ........................... 105

5.4 Operating Performance Points .................... 106

5.5 Recommended Operating Conditions ............. 107

5.6 Power Consumption Summary .................... 109

5.7 DC Electrical Characteristics ...................... 110

5.8 ADC0: Touch Screen Controller and Analog-to-

Digital Subsystem Electrical Parameters .......... 113

5.9 ADC1: Analog-to-Digital Subsystem Electrical

Parameters......................................... 115

5.10 VPP Specifications for One-Time Programmable

(OTP) eFuses...................................... 118

5.11 Thermal Resistance Characteristics............... 119

5.12 External Capacitors ................................ 121

5.13 Timing and Switching Characteristics.............. 124

5.14 Emulation and Debug.............................. 254

6 Device and Documentation Support.............. 255

6.1 Device Nomenclature.............................. 255

6.2 Tools and Software ................................ 256

6.3 Documentation Support............................ 258

6.4 Related Links ...................................... 260

6.5 Community Resources............................. 260

6.6 Trademarks ........................................ 260

6.7 Electrostatic Discharge Caution ................... 260

6.8 Glossary............................................ 260

7 Mechanical, Packaging, and Orderable

Information............................................. 261

7.1 Via Channel........................................ 261

7.2 Packaging Information ............................. 261

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2 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision C (April 2015) to Revision D Page

• Added AM4372 device information to document ................................................................................. 1

• Added AM4372ZDN Part Number to Table 1-1, Device Information .......................................................... 5

• Added Table 3-1, Device Features Comparison ................................................................................. 9

• Added AM4372 Device and 600-MHz Device Speed Range to Figure 6-1, Device Nomenclature .................... 256

• Updated Design Kits and Evaluation Modules list in Section 6.2, Tools and Software................................... 256

• Updated notification alert paragraph in Section 6.3, Documentation Support............................................. 258

• Added AM4372 part number information to Table 6-1, Related Links...................................................... 260

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3 Device Comparison

Table 3-1 shows the features supported across different AM437x devices.

Table 3-1. Device Features Comparison

FUNCTION AM4372 AM4376 AM4377 AM4378 AM4379

ARM Cortex-A9 Yes Yes Yes Yes Yes

Frequency 600 MHz

800 MHz

300 MHz

800 MHz

1000 MHz

800 MHz

1000 MHz 800 MHz

1000 MHz

MIPS 1500

2000

750

2000

2500

2000

2500 2000

2500

On-chip L1 cache 64KB 64KB 64KB 64KB 64KB

On-chip L2 cache 256KB 256KB 256KB 256KB 256KB

Graphics accelerator (SGX530) — — — 3D 3D

Hardware acceleration Crypto accelerator Crypto accelerator Crypto accelerator Crypto accelerator Crypto accelerator

Programmable real-time unit

subsystem and industrial

communication subsystem (PRU-

ICSS)

—Features including

basic Industrial

protocols

Features including all

Industrial protocols

Features including

basic Industrial

protocols

Features including all

Industrial protocols

On-chip memory 256KB 256KB 256KB 256KB 256KB

Display options DSS DSS DSS DSS DSS

General-purpose memory 1 16-bit (GPMC,

NAND flash, NOR

flash, SRAM)

1 16-bit (GPMC,

NAND flash, NOR

flash, SRAM)

1 16-bit (GPMC,

NAND flash, NOR

flash, SRAM)

1 16-bit (GPMC,

NAND flash, NOR

flash, SRAM)

1 16-bit (GPMC,

NAND flash, NOR

flash, SRAM)

DRAM(1) 1 32-bit (DDR3-800,

DDR3L-800,

LPDDR2-532)

1 32-bit (DDR3-800,

DDR3L-800,

LPDDR2-532)

1 32-bit (DDR3-800,

DDR3L-800,

LPDDR2-532)

1 32-bit (DDR3-800,

DDR3L-800,

LPDDR2-532)

1 32-bit (DDR3-800,

DDR3L-800,

LPDDR2-532)

Universal serial bus (USB) 2 ports 2 ports 2 ports 2 ports 2 ports

Ethernet media access controller

(EMAC) with 2-port switch 10/100/1000

2 ports 10/100/1000

2 ports

Multimedia card (MMC) 3 3 3 3 3

Controller-area network (CAN) 2 2 2 2 2

Universal asynchronous receiver

and transmitter (UART) 6 6 6 6 6

Analog-to-digital converter (ADC) 2 8-ch 12-bit 2 8-ch 12-bit 2 8-ch 12-bit 2 8-ch 12-bit 2 8-ch 12-bit

Enhanced high-resolution PWM

modules (eHRPWM) 6 6 6 6 6

Enhanced capture modules (eCAP) 3 3 3 3 3

Enhanced quadrature encoder

pulse (eQEP) 3 3 3 3 3

Real-time clock (RTC) 1 1 1 1 1

Inter-integrated circuit (I2C) 3 3 3 3 3

Multichannel audio serial port

(McASP) 2 2 2 2 2

Multichannel serial port interface

(McSPI) 5 5 5 5 5

Enhanced direct memory access

(EDMA) 64-Ch 64-Ch 64-Ch 64-Ch 64-Ch

Camera (VPFE) 12-bit 12-bit 12-bit 12-bit 12-bit

Sync timer (32K) 1 1 1 1 1

HDQ/1-Wire 1 1 1 1 1

QSPI 1 1 1 1 1

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Table 3-1. Device Features Comparison (continued)

FUNCTION AM4372 AM4376 AM4377 AM4378 AM4379

Timers 12 12 12 12 12

DEV_FEATURE register value(2) 0x020000EF 0x020000EF 0x020300EF 0x220000EF 0x220300EF

Input/output (I/O) supply 1.8 V, 3.3 V 1.8 V, 3.3 V 1.8 V, 3.3 V 1.8 V, 3.3 V 1.8 V, 3.3 V

Operating temperature range 0 to 90°C

–40 to 105°C

0 to 90°C

–40 to 105°C

–40 to 90°C

–40 to 105°C

–40 to 90°C

0 to 90°C

–40 to 105°C

–40 to 90°C –40 to 105°C

(1) DRAM speeds listed are data rates.

(2) For more details about the DEV_FEATURE register, see the AM437x Sitara Processors Technical Reference Manual.

3.1 Related Products

For information about other devices in this family of products or related products, see the following links:

Sitara Processors Scalable processors based on ARM Cortex-A cores with flexible peripherals,

connectivity and unified software support – perfect for sensors to servers.

Sitara AM437x Processors Scalable ARM Cortex-A9 from 300 MHz up to 1 GHz. 3D graphics option for

enhanced user interface. Quad core PRU-ICSS for industrial Ethernet protocols and position

feedback control. Dual camera support for barcode scanning, preview and still pictures.

Customer programmable secure boot option.

Companion Products for AM437x Devices Review products that are frequently used in conjunction with

this product.

Reference Designs for AM437x Devices TI Designs Reference Design Library is a robust reference

design library spanning analog, embedded processor and connectivity. Created by TI experts

to help you jump start your system design, all TI Designs include schematic or block

diagrams, BOMs and design files to speed your time to market. Search and download

designs at ti.com/tidesigns.

AM4372, AM4376, AM4377, AM4378, AM4379

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4 Terminal Configuration and Functions

4.1 Pin Diagrams

NOTE

The terms "ball", "pin", and "terminal" are used interchangeably throughout the document. An

attempt is made to use "ball" only when referring to the physical package.

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Table 4-1. ZDN Ball Map [Section Top Left - Top View]

A B C D E F G H

25 VSS XTALOUT XTALIN gpio5_8 gpio5_12 USB1_DRVVBUS EXTINTn uart3_rxd

24 dss_ac_bias_en VSS_OSC xdma_event_intr1 xdma_event_intr0 gpio5_13 gpio5_9 eCAP0_in_PWM0_o

ut uart3_txd

23 dss_hsync dss_vsync VDDS_OSC VDDS_CLKOUT gpio5_11 mcasp0_axr0

22 dss_pclk dss_data0 VDDSHV5 WARMRSTn uart3_ctsn

21 dss_data1 dss_data2 dss_data3 USB0_DRVVBUS Reserved

20 dss_data4 dss_data5 dss_data6 vdd_mpu_mon VDDS gpio5_10 clkreq

19 dss_data8 dss_data9 dss_data12 dss_data13 dss_data7 CAP_VBB_MPU Reserved

18 dss_data10 dss_data11 VSS

Ball Map Position

123

456

789

AM4372, AM4376, AM4377, AM4378, AM4379

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Table 4-2. ZDN Ball Map [Section Top Middle - Top View]

J K L M N P R T

25 uart0_rtsn uart0_rxd uart0_ctsn mcasp0_axr1 spi4_cs0 spi4_sclk spi0_cs1 USB1_VBUS

24 uart0_txd uart3_rtsn mcasp0_ahclkx mcasp0_ahclkr mcasp0_aclkx spi4_d1 spi4_d0 EMU1

23 mcasp0_fsr mcasp0_aclkr EMU0 spi0_sclk spi2_cs0

22 uart1_ctsn uart1_rtsn mcasp0_fsx spi2_d0 spi0_d0

21 uart1_rxd uart1_txd VDDS_PLL_CORE_

LCD VPP spi0_d1

20 VDD_MPU VDD_MPU spi2_sclk spi2_d1 spi0_cs0

19 VDD_MPU VDD_MPU VDDSHV3 VDDS VDD_CORE

18 VDDSHV3 VDDSHV3 VSS VDD_MPU VDDSHV3 VDDSHV3 VSS VDD_CORE

Ball Map Position

123

456

789

AM4372, AM4376, AM4377, AM4378, AM4379

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Table 4-3. ZDN Ball Map [Section Top Right - Top View]

U V W Y AA AB AC AD AE

25 USB1_ID USB1_DM USB0_DP nTRST TCK cam1_wen cam1_field cam1_hd VSS

24 USB0_ID USB1_DP USB0_DM TMS TDO I2C0_SDA cam1_data9 cam1_data8 cam1_data7

23 USB0_VBUS VSSA_USB PWRONRSTn VSS cam1_vd cam1_data6 cam1_data5

22 USB1_CE USB0_CE I2C0_SCL cam1_data4 cam1_data3

21 VDDA1P8V_USB1 VDDA1P8V_USB0 cam1_data1 cam1_data2 cam1_pclk

20 VDDA3P3V_USB1 VDDA3P3V_USB0 TDI cam1_data0 cam0_pclk cam0_data7 cam0_data6

19 VSS VDDS cam0_data9 cam0_data8 cam0_data5 cam0_data4

18 VSS VSS VDDSHV3 cam0_data2 cam0_data3 cam0_data1 cam0_field cam0_vd cam0_data0

Ball Map Position

123

456

789

AM4372, AM4376, AM4377, AM4378, AM4379

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Table 4-4. ZDN Ball Map [Section Middle Left - Top View]

A B C D E F G H

17 mdio_data mdio_clk dss_data14 dss_data15 VDDS_PLL_MPU mii1_rxd0 VDDSHV6 VDDSHV6

16 rmii1_ref_clk mii1_rxd1 mii1_txd3 mii1_col mii1_rxd2 VDDSHV7 VDDSHV6 VDD_MPU

15 mii1_rx_dv mii1_txd0 VSS

14 mii1_txd1 mii1_crs mii1_rxd3 mii1_tx_clk CAP_VDD_SRAM_

MPU VDDS_SRAM_MPU

_BB VDDSHV8 VDD_MPU

13 mii1_tx_en mii1_rx_er mii1_txd2 mii1_rx_clk CAP_VDD_SRAM_C

ORE VDDS_SRAM_COR

E_BG VDDSHV8 VDD_MPU

12 gpmc_clk gpmc_csn3 VDDS

11 gpmc_ad15 gpmc_ad14 gpmc_ad13 gpmc_ad11 gpmc_ad12 gpmc_ad10 VDDSHV9 VDDSHV9

10 gpmc_ad9 gpmc_ad8 gpmc_be0n_cle gpmc_wen gpmc_oen_ren gpmc_csn2 VDDSHV10 VDDSHV10

Ball Map Position

123

456

789

AM4372, AM4376, AM4377, AM4378, AM4379

SPRS851D –JUNE 2014–REVISED SEPTEMBER 2016

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Table 4-5. ZDN Ball Map [Section Middle Middle - Top View]

J K L M N P R T

17 VSS VDDSHV3 VSS VDD_MPU VDD_CORE VDD_CORE VSS VSS

16 VDD_MPU VSS VDD_CORE VDD_CORE

15 VSS VSS VSS VSS VSS VSS VSS VSS

14 VDD_MPU VSS VDD_CORE VDD_CORE VSS VSS VDD_CORE VDD_CORE

13 VDD_MPU VSS VSS VSS

12 VSS VSS VDD_CORE VDD_CORE VSS VSS VSS VSS

11 VDD_CORE VSS VSS VSS VSS VSS VDD_CORE VDD_CORE

10 VDD_CORE VSS VSS VSS

Ball Map Position

123

456

789

AM4372, AM4376, AM4377, AM4378, AM4379

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Table 4-6. ZDN Ball Map [Section Middle Right - Top View]

U V W Y AA AB AC AD AE

17 VSS VDDSHV2 cam0_wen cam0_hd

16 VSS VDDSHV2 VDDSHV2 VDDA_ADC1 ADC1_AIN2 ADC1_AIN1 ADC1_AIN0 ADC1_AIN7 ADC1_AIN6

15 VDD_CORE VDD_CORE VDDS ADC1_AIN5 ADC1_AIN4 ADC1_AIN3 VSSA_ADC ADC1_VREFN ADC1_VREFP

14 VSS VSS ADC0_VREFP ADC0_VREFN

13 VSS VSS VDD_CORE ADC0_AIN2 ADC0_AIN3 ADC0_AIN4 ADC0_AIN5 ADC0_AIN6 ADC0_AIN7

12 VSS VSS VDD_CORE ADC0_AIN1 ADC0_AIN0 VDDA_ADC0 Reserved VDDS Reserved

11 VSS VSS Reserved Reserved

10 VSS VSS Reserved Reserved Reserved Reserved Reserved Reserved VSS

Ball Map Position

123

456

789

AM4372, AM4376, AM4377, AM4378, AM4379

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Table 4-7. ZDN Ball Map [Section Bottom Left - Top View]

A B C D E F G H

9gpmc_advn_ale gpmc_csn1 VDDSHV11

8gpmc_csn0 gpmc_ad7 gpmc_ad6 gpmc_a11 gpmc_a6 VDDS3P3V_IOLDO gpmc_a10 VDDSHV11

7gpmc_ad5 gpmc_ad4 gpmc_a4 gpmc_a5 gpmc_a8

6gpmc_ad3 gpmc_ad2 gpmc_a2 CAP_VDDS1P8V_IO

LDO gpmc_a7 VDDS

5gpmc_ad1 gpmc_ad0 gpmc_a1 VDDS_PLL_DDR

4gpmc_a3 gpmc_a9 ddr_dqm0 ddr_d4

3gpmc_be1n gpmc_wpn gpmc_a0 ddr_d0 ddr_d3 ddr_d5

2gpmc_wait0 mmc0_dat2 mmc0_dat1 mmc0_cmd ddr_d1 ddr_dqs0 ddr_d6 ddr_dqm1

1VSS mmc0_dat3 mmc0_dat0 mmc0_clk ddr_d2 ddr_dqsn0 ddr_d7 ddr_d8

Ball Map Position

123

456

789

AM4372, AM4376, AM4377, AM4378, AM4379

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Table 4-8. ZDN Ball Map [Section Bottom Middle - Top View]

J K L M N P R T

9VSS VSS VSS VDD_CORE VDD_CORE VSS VDD_CORE VDD_CORE

8VDDSHV1 VDDS_DDR VSS VDDS_DDR VDDS_DDR VSS VDDS_DDR VDDS_DDR

7VDDSHV1 VDDS_DDR VDDS_DDR VDDS_DDR VDDS_DDR VDDS_DDR

6ddr_d9 ddr_d13 ddr_a10 ddr_cke1 VDDS_DDR ddr_vref

5ddr_d10 ddr_d14 ddr_csn0 ddr_a13 ddr_a5 ddr_a11

4ddr_d11 ddr_d15 ddr_csn1 ddr_wen ddr_a6 ddr_a12

3ddr_d12 ddr_ba2 ddr_cke0 ddr_casn ddr_a7 ddr_a14

2ddr_dqs1 ddr_ba1 ddr_a2 ddr_ck ddr_rasn ddr_a3 ddr_a8 ddr_a15

1ddr_dqsn1 ddr_ba0 ddr_a1 ddr_nck ddr_a0 ddr_a4 ddr_a9 ddr_resetn

Ball Map Position

123

456

789

AM4372, AM4376, AM4377, AM4378, AM4379

SPRS851D –JUNE 2014–REVISED SEPTEMBER 2016

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Table 4-9. ZDN Ball Map [Section Bottom Right - Top View]

U V W Y AA AB AC AD AE

9VSS VSS Reserved Reserved Reserved VDD_CORE Reserved

8VSS VDDS_DDR VDDS VSS

7VDDS_DDR Reserved Reserved Reserved Reserved Reserved VSS

6ddr_dqm2 ddr_d23 Reserved Reserved Reserved RTC_PMIC_EN RTC_PWRONRST

5ddr_d16 ddr_d22 Reserved VDDS_RTC RTC_XTALIN

4ddr_d17 ddr_d21 ddr_d26 VSS_RTC RTC_XTALOUT

3ddr_d18 ddr_d25 ddr_d27 ddr_vtp CAP_VDD_RTC RTC_WAKEUP

2ddr_odt1 ddr_d19 ddr_dqsn2 ddr_d24 ddr_dqsn3 ddr_d28 ddr_d31 Reserved RTC_KALDO_EN

1ddr_odt0 ddr_d20 ddr_dqs2 ddr_dqm3 ddr_dqs3 ddr_d29 ddr_d30 Reserved VSS

Ball Map Position

123

456

789

AM4372, AM4376, AM4377, AM4378, AM4379

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4.2 Pin Attributes

1. BALL NUMBER: Package ball numbers associated with each signals.

2. PIN NAME: The name of the package pin.

Note: The table does not take into account subsystem terminal multiplexing options.

3. SIGNAL NAME: The signal name for that pin in the mode being used.

4. MODE: Multiplexing mode number.

(a) Mode 0 is the primary mode; this means that when mode 0 is set, the function mapped on the

terminal corresponds to the name of the terminal. There is always a function mapped on the

primary mode. Notice that primary mode is not necessarily the default mode.

Note: The default mode is the mode at the release of the reset; also see the RESET REL. MODE

column.

(b) Modes 1 to 7 are possible modes for alternate functions. On each terminal, some modes are

effectively used for alternate functions, while some modes are not used and do not correspond to a

functional configuration.

5. TYPE: Signal direction

– I = Input

– O = Output

– IO = Input and Output

– D = Open drain

– DS = Differential

– A = Analog

– PWR = Power

– GND = Ground

Note: In the safe_mode, the buffer is configured in high-impedance.

6. BALL RESET STATE: State of the terminal while the active low PWRONRSTn terminal is low.

– 0: The buffer drives VOL (pulldown or pullup resistor not activated)

0(PD): The buffer drives VOL with an active