74HC/HCT574 MS! OCTAL D-TYPE FLIP-FLOP; POSITIVE EDGE-TRIGGER; 3-STATE FEATURES TYPICAL @ 3-state non-inverting outputs for SYMBOL | PARAMETER CONDITIONS UNIT bus oriented applications He HCT e S-bit positive edge-triggered teu! propagation delay 4 6 ; register tPLH CP to O, Cy = 15 pF s Common 3-state output bh Vec=5V input fmax maximum clock frequency 123 | 76 MHz @ Independent register and 3-state buffer operation Cc, input capacitance 3.5 3.5 pF @ Output capability: bus driver ower dissipation Icc category: MSI Cpp peel nied per flip-flop notes 1 and 2 22 25 pF GENERAL DESCRIPTION GND = 0 V; Tampb = 25 C; ty = te = G ns The 74HC/HCTS74 are high-speed Notes Si-gate CMOS devices and are pin ; . ; ae . compatible with low power Schottky 1. Cpp is used to determine the dynamic power dissipation (Pp in pW): TTL (LSTTL). They are specified in Pp =Cpp x Vcc? x fi + (CL x VCC? x fo) where: compliance with JEDEC standard no. 7A. fj; = input frequency in MHz CL = output load capacitance in pF The 74HC/HCT574 are octal D-type fo = output frequency in MHz Vcc = supply voltage in V flip-flops featuring separate D-type inputs Z (C. x Voc? x fg) = sum of outputs for each fipflop and non inverting 3-state 2. For HC the condition is V| = GND to Vcc outputs for bus oriented applications. ition is V] = GND t ~15V A clock (CP) and an output enable (OE) For HCT the condition is V| oVcc~1. input are common to all flip-flops. PACKAGE OUTLINES The 8 flip-flops will store the state of their individual D-inputs that meet the SEE PACKAGE INFORMATION SECTION set-up and hold time requirements on the LOW-to-HIGH CP transition. PIN DESCRIPTION When OE is LOW, the contents of the 8 flip-flops are available at the outputs. PIN NO. SYMBOL NAME AND FUNCTION When OE is HIGH, the outputs go to the . . high impedance OFF-state. Operation of 1 OE 3-state output enable input (active LOW) the OE input does not affect the state of 2, 3, 4,5, : the flip-flops. 67.8.9 Do to D7 data inputs The 574 is functionally identical to 10 GND ground (0 V) the 564, but has non-inverting outputs. 11 cP clock input (LOW-to-HIGH, edge-triggered) The 574 is functionally identical to 19, 18, 17, 16 the 374, but has a different pinning. 1B 14, 13, 12. Qo to G7 3-state flip-flop outputs 20 Vec positive supply voltage best U 120] Yoo v Pol2 2} 20g agteia a Die 3-40, yb oo[a [17} 22 40, Q2-17 03 (5) [x6] O3 $s1D3 a3/'6 574 D (6 | mk s4 Dg Og b15 > [7] mk 7-1 Ds Qs -14 0g [eo] Ta] Og & Dg Ogp13 oe] 12] 97 a OE ad ono [io iii} ce y vassees 7299606 Zz 7293004 Fig. 1 Pin configuration. Fig. 2 Logic symbol. Fig. 3 IEC logic symbol. December 1990 699 74HC/HCT574 MS! 3-STATE OUTPUTS FFItO FFE 7203867 Fig. 4 Functional diagram. FUNCTION TABLE INPUTS OUTPUTS OPERATING MODES PIP ECOPs dE | cP | Dy, Qp to Q7 load and read L t | L L register L t h H H load register and H t l L Zz disable outputs H t h H Zz H = HIGH voltage level h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition L = LOW voltage fevel | = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition Z = high impedance OF F-state t = LOW-to-HIGH clock transition i) Dy 02 By Da \/ W V7 Da oa cr cP FF3 FFS D7 +Y yoo Q, Q4 Fig. 5 Logic diagram. \/ 6 7Z93868.2 700 March 1988 Octal D-type flip-flop; positive edge-trigger; 3-state 74HC/HCT574 MSI DC CHARACTERISTICS FOR 74HC For the DC characteristics see chapter HCMOS family characteristics, section Family specifications. Output capability: bus driver icc category: MS! AC CHARACTERISTICS FOR 74HC GND = 0 V; t, = tp = 6 ns; Cy = 50 pF Tamb (C) TEST CONDITIONS 74HC SYMBOL | PARAMETER UNIT | Voc | WAVEFORMS +25 40 to +85 | 4010 +125 Vv min. | typ. | max. | min. | max. | min. | max. . 47 (| 150 190 225 2.0 TPHL/ | Propagation delay 17 | 30 35 45 |ns |45 | Fig 6 PLH etn 14 | 26 33 38 6.0 . 44 | 140 175 210 2.0 teZH! oaume output enable time 16 | 28 35 42 ns 45 | Fig 7 P2u oMn 13. | 24 30 36 6.0 . . 39 | 125 155 190 2.0 tpHz/ State output disable time 14 | 95 31 38 ns 45 Fig. 7 PLZ 10.On Ww | 21 26 32 6.0 tru / 14 | 60 75 90 2.0 He output transition time 5 12 15 18 ns 4.5 Fig. 6 TLH 4 | 10 13 15 6.0 . go |14 100 120 2.0 clock pulse width : tw 16 {5 20 24 ns 4.5 Fig. 6 HIGH or LOW 14 14 17 20 60 set-up time 60 {6 75 30 2.0 t 12 |2 16 18 ns 45 | Fig.8 wu Dp to CP 10 |2 13 15 6.0 . 5 |0 5 5 2.0 th me 5 |o 5 5 ns 45 | Fig 8 nto 5 10 5 5 6.0 : 6.0 | 37 48 4.0 2.0 fax maximum clock pulse 30 | 112 24 20 MHz | 45 | Fig. 6 requency 35 | 133 28 24 6.0 March 1988 701 74HC/HCT574 MSI DC CHARACTERISTICS FOR 74HCT For the DC characteristics see chapter HCMOS family characteristics, section Family specifications. Output capability: bus driver Icc category: MSI Note to HCT types The value of additional quiescent supply current (Alcc) for a unit toad of 1 is given in the family specifications. To determine Sicc per input, multiply this vatue by the unit load coefficient shown in the table below. UNIT LOAD INPUT | COEFFICIENT Dn 0.5 DE 1.25 cP 15 AC CHARACTERISTICS FOR 74HCT GNO = 0 V; ty = ty = 6 ns; CL = 50 pF Tamb (C) TEST CONDITIONS J4HCT SYMBOL | PARAMETER UNIT | Vcc | WAVEFORMS +25 40 to +85 | 40to +125 Vv min, | typ. | max. | min. | max. | min. | max. tpH/ propagation delay . 1PLH CP to Op, 18 | 33 41 50 ns 4.5 Fig. 6 tpzH/ 3-state output enable time . tpzL OE to O, 19 | 33 41 50 ns 45 Fig. 7 tpy2/ 3-state output disable time . tpLz OE 10 Q, 16 | 28 35 42 ns 4.5 Fig. 7 rH! output transition time 5 12 15 18 ns 4.5 Fig. 6 clock pulse width tw HIGH or LOW 16 |7 20 24 ns 4.5 Fig. 6 set-up time . tsu Dp to CP 12 |3 16 18 ns 4.5 Fig. 8 hold time i th Dp to CP 5 -1 5 5 ns 45 Fig. 8 maximum clock pulse . fmax frequency 30 | 69 24 20 MHz | 4.5 Fig. 6 702 March 1988 Octal D-type flip-flop; positive edge-trigger; 3-state AC WAVEFORMS 74HC/HCT574 MSI CP INPUT Q,, OUTPUT 7201869 Fig. 6 Waveforms showing the clock input (CP) pulse width, the CP input to output (Q,,) propagation delays, the output transition times and the maximum clock pulse frequency. or INPUT OUTPUT LOW -to- OFF OFF -to- LOW OUTPUT HIGH - to - OFF OFF -t0-HIGH outputs ele output) __ lag outputs 7293039 anabied disabled enabled Fig. 7 Waveforms showing the 3-state enable and disable times. O, INPUT CP INPUT 7203870 Fig. 8 Waveforms showing the data set-up and hold times for Dy, input to CP input. Note to Fig. 8 The shaded areas indicate when the input is permitted to change for predictable output performance. Note to AC waveforms (1) HC: Viy = 50%; V) = GND to Vcc. HCT: Viy = 1.3V; V;_ = GND to 3V. January 1986 703