AT91M55800A-33AJ - Atmel Corporation

Features

•Utilizes the ARM7TDMI® ARM® Thumb® Processor Core

– High-performance 32-bit RISC Architecture

– High-density 16-bit Instruction Set

– Leader in MIPS/Watt

– EmbeddedICE™ (In-Circuit Emulation)

•8K Bytes Internal SRAM

•Fully-programmable External Bus Interface (EBI)

– Maximum External Address Space of 128M Bytes

– Eight Chip Selects

– Software Programmable 8/16-bit External Databus

•8-level Priority, Individually Maskable, Vectored Interrupt Controller

– Seven External Interrupts, Including a High-priority, Low-latency Interrupt Request

•Fifty-eight Programmable I/O Lines

•6-channel 16-bit Timer/Counter

– Six External Clock Inputs and Two Multi-purpose I/O Pins per Channel

•Three USARTs

•Master/Slave SPI Interface

– 8-bit to 16-bit Programmable Data Length

– Four External Slave Chip Selects

•Programmable Watchdog Timer

•8-channel 10-bit ADC

•2-channel 10-bit DAC

•Clock Generator with On-chip Main Oscillator and PLL for Multiplication

– 3 to 20 MHz Frequency Range Main Oscillator

•Real-time Clock with On-chip 32 kHz Oscillator

– Battery Backup Operation and External Alarm

•8-channel Peripheral Data Controller for USARTs and SPIs

•Advanced Power Management Controller (APMC)

– Normal, Wait, Slow, Standby and Power-down modes

•IEEE® 1149.1 JTAG Boundary-scan on all Digital Pins

•Fully Static Operation: 0 Hz to 33 MHz

•2.7V to 3.6V Core Operating Range

•2.7V to 5.5V I/O Operating Range

•2.7V to 3.6V Analog Operating Range

•1.8V to 3.6V Backup Battery Operating Range

•2.7V to 3.6V Oscillator and PLL Operating Range

•-40°C to +85°C Temperature Range

•Available in a 176-lead LQFP (Green) and a 176-ball BGAPackage (RoHS-compliant)

1. Description

The AT91M55800A is a member of the Atmel AT91 16/32-bit microcontroller family,

which is based on the ARM7TDMI processor core. This processor has a high-perfor-

mance 32-bit RISC architecture with a high-density 16-bit instruction set and very low

power consumption. In addition, a large number of internally banked registers result in

very fast exception handling, making the device ideal for real-time control

applications.

The fully programmable External Bus Interface provides a direct connection to off-chip

memory in as fast as one clock cycle for a read or write operation. An eight-level prior-

AT91 ARM

Thumb-based

Microcontrollers

AT91M55800A

Rev. 1745E–ATARM–18-Apr-06

1745E–ATARM–18-Apr-06

AT91M55800A

ity vectored interrupt controller in conjunction with the peripheral data controller significantly improve the real-time

performance of the device.

The device is manufactured using Atmel’s high-density CMOS technology. By combining the ARM7TDMI processor core

with an on-chip SRAM, a wide range of peripheral functions, analog interfaces and low-power oscillators on a monolithic

chip, the Atmel AT91M55800A is a powerful microcontroller that provides a highly-flexible and cost-effective solution to

many ultra low-power applications.

1745E–ATARM–18-Apr-06

AT91M55800A

2. Pin Configurations

Notes: 1. Analog pins

2. Battery backup pins

Table 2-1. Pin Configuration for 176-lead LQFP Package

Pin AT91M55800A Pin AT91M55800A Pin AT91M55800A Pin AT91M55800A

1 GND 45 GND 89 GND 133 GND

2 GND 46 GND 90 GND 134 GND

3 NCS0 47 D8 91 PA19/RXD1 135 NCS4

4 NCS1 48 D9 92 PA20/SCK2 136 NCS5

5 NCS2 49 D10 93 PA21/TXD2 137 NCS6

6 NCS3 50 D11 94 PA22/RXD2 138 NCS7

7 NLB/A0 51 D12 95 PA23/SPCK 139 PB0

8 A1 52 D13 96 PA24/MISO 140 PB1

9 A2 53 D14 97 PA25/MOSI 141 PB2

10 A3 54 D15 98 PA26/NPCS0/NSS 142 PB3/IRQ4

11 A4 55 PB19/TCLK0 99 PA27/NPCS1 143 PB4/IRQ5

12 A5 56 PB20/TIOA0 100 PA28/NPCS2 144 PB5

13 A6 57 PB21/TIOB0 101 PA29/NPCS3 145 PB6/AD0TRIG

14 A7 58 PB22/TCLK1 102 VDDIO 146 PB7/AD1TRIG

15 VDDIO 59 VDDIO 103 GND 147 VDDIO

16 GND 60 GND 104 VDDPLL 148 GND

17 A8 61 PB23/TIOA1 105 XIN 149 PB8

18 A9 62 PB24/TIOB1 106 XOUT 150 PB9

19 A10 63 PB25/TCLK2 107 GNDPLL 151 PB10

20 A11 64 PB26/TIOA2 108 PLLRC 152 PB11

21 A12 65 PB27/TIOB2 109 VDDBU(2) 153 PB12

22 A13 66 PA0/TCLK3 110 XIN32(2) 154 PB13

23 A14 67 PA1/TIOA3 111 XOUT32(2) 155 PB14

24 A15 68 PA2/TIOB3 112 NRSTBU(2) 156 PB15

25 A16 69 PA3/TCLK4 113 GNDBU(2) 157 PB16

26 A17 70 PA4/TIOA4 114 WAKEUP(2) 158 PB17

27 A18 71 PA5/TIOB4 115 SHDN(2) 159 NWDOVF

28 A19 72 PA6/TCLK5 116 GNDBU(2) 160 MCKO

29 VDDIO 73 VDDIO 117 VDDA(1) 161 VDDIO

30 GND 74 GND 118 AD0(1) 162 GND

31 A20 75 PA7/TIOA5 119 AD1(1) 163 PB18/BMS

32 A21 76 PA8/TIOB5 120 AD2(1) 164 JTAGSEL

33 A22 77 PA9/IRQ0 121 AD3(1) 165 TMS

34 A23 78 PA10/IRQ1 122 AD4(1) 166 TDI

35 D0 79 PA11/IRQ2 123 AD5(1) 167 TDO

36 D1 80 PA12/IRQ3 124 AD6(1) 168 TCK

37 D2 81 PA13/FIQ 125 AD7(1) 169 NTRST

38 D3 82 PA14/SCK0 126 ADVREF(1) 170 NRST

39 D4 83 PA15/TXD0 127 DAVREF(1) 171 NWAIT

40 D5 84 PA16/RXD0 128 DA0(1) 172 NOE/NRD

41 D6 85 PA17/SCK1 129 DA1(1) 173 NWE/NWR0

42 D7 86 PA18/TXD1/NTRI 130 GNDA(1) 174 NUB/NWR1

43 VDDCORE 87 VDDCORE 131 VDDCORE 175 VDDCORE

44 VDDIO 88 VDDIO 132 VDDIO 176 VDDIO

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AT91M55800A

Table 2-2. Pin Configuration for 176-ball BGA Package

Pin AT91M55800A Pin AT91M55800A Pin AT91M55800A Pin AT91M55800A

A1 NCS1 C1 A0/NLB E1 A4 G1 A12

A2 NWAIT C2 NCS0 E2 A3 G2 A9

A3 NRST C3 VDDIO E3 A5 G3 A8

A4 NTRST C4 VDDCORE E4 GND G4 GND

A5 PB18/BMS C5 TMS E5 – G5 –

A6 NWDOVF C6 VDDIO E6 – G6 –

A7 PB16 C7 MCK0 E7 – G7 –

A8 PB12 C8 PB13 E8 – G8 –

A9 PB10 C9 PB6/AD0TRIG E9 – G9 –

A10 PB9 C10 VDDIO E10 – G10 –

A11 PB8 C11 PB4/IRQ5 E11 – G11 –

A12 NCS7 C12 PB0 E12 AD6 G12 AD3

A13 NCS6 C13 VDDIO E13 AD5 G13 AD2

A14 GND C14 DA0 E14 NRSTBU G14 GND

A15 DAVREF C15 ADVREF E15 GNDBU G15 XIN32

B1 NCS2 D1 A2 F1 A10 H1 A15

B2 NUB/NWR1 D2 A1 F2 A7 H2 A14

B3 NWE/NWR0 D3 NCS3 F3 VDDIO H3 A13

B4 NOE/NRD D4 GND F4 A6 H4 A11

B5 TD0 D5 TCK F5 – H5 –

B6 TDI D6 JTAGSEL F6 – H6 –

B7 PB17 D7 GND F7 – H7 –

B8 PB11 D8 PB15 F8 – H8 –

B9 PB7/AD1TRIG D9 PB14 F9 – H9 –

B10 PB3/IRQ4 D10 PB5 F10 – H10 –

B11 PB2 D11 PB1 F11 – H11 –

B12 NCS5 D12 GND F12 GND H12 AD1

B13 NCS4 D13 VDDCORE F13 AD4 H13 AD0

B14 DA1 D14 AD7 F14 VDDBU H14 WAKEUP

B15 GNDA D15 VDDA F15 XOUT32 H15 GND

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AT91M55800A

J1 A17 L1 A20 N1 D4 R1 D10

J2 A18 L2 A23 N2 D6 R2 D11

J3 VDDIO L3 D0 N3 VDDIO R3 D12

J4 A16 L4 D1 N4 D14 R4 D13

J5 – L5 – N5 PB19/TCLK0 R5 PB20/TIOA0

J6 – L6 – N6 VDDIO R6 PB23/TIOA1

J7 – L7 – N7 PB25/TCLK2 R7 PB24/TIOB1

J8 – L8 – N8 PA1/TIOA3 R8 PA3/TCLK4

J9 – L9 – N9 VDDIO R9 PA4/TIOA4

J10 – L10 – N10 PA8/TIOB5 R10 PA5/TIOB4

J11 – L11 – N11 PA9/IRQ0 R11 PA6/TCLK5

J12 PA29/NPCS3 L12 PA25/MOSI N12 VDDCORE R12 PA12/IRQ3

J13 SHDN L13 PA22RXD2 N13 VDDIO R13 PA14/SCK0

J14 VDDPLL L14 PA26/NPCS0/NSS N14 PA19/RXD1 R14 PA15/TXD0

J15 PLLRC L15 XOUT N15 GND R15 PA16/RXD0

K1 A19 M1 D2 P1 D5

K2 A22 M2 D3 P2 D7

K3 A21 M3 VDDCORE P3 D8

K4 GND M4 GND P4 D9

K5 – M5 GND P5 D15

K6 – M6 PB21/TIOB0 P6 PB22/TCLK1

K7 – M7 GND P7 PB26/TIOA2

K8 – M8 PB27/TIOB2 P8 PA2/TIOB3

K9 – M9 PA0/TCLK3 P9 PA7/TIOA5

K10 – M10 GND P10 PA10/IRQ1

K11 – M11 PA23/SPCK P11 PA11/IRQ2

K12 PA28/NPCS2 M12 GND P12 PA13/FIQ

K13 VDDIO M13 PA21/TXD2 P13 PA17SCK1

K14 PA27/NPCS1 M14 PA24/MISO P14 PA18/TXD1/NTRI

K15 GNDPLL M15 XIN P15 PA20/SCK2

Table 2-2. Pin Configuration for 176-ball BGA Package (Continued)

Pin AT91M55800A Pin AT91M55800A Pin AT91M55800A Pin AT91M55800A

1745E–ATARM–18-Apr-06

AT91M55800A

Figure 2-1. 176-lead LQFP Pinout

Figure 2-2. 176-ball BGA Pinout

144

176

133

132 89

123456789101112

13 14 15

1745E–ATARM–18-Apr-06

AT91M55800A

3. Pin Description

Table 3-1. Pin Description

Module Name Function Type

Active

Level Comments

EBI

A0 - A23 Address bus Output –

D0 - D15 Data bus I/O –

NCS0 - NCS7 Chip select Output Low

NWR0 Lower byte 0 write signal Output Low Used in Byte-write option

NWR1 Lower byte 1 write signal Output Low Used in Byte-write option

NRD Read signal Output Low Used in Byte-write option

NWE Write enable Output Low Used in Byte-select option

NOE Output enable Output Low Used in Byte-select option

NUB Upper byte-select Output Low Used in Byte-select option

NLB Lower byte-select Output Low Used in Byte-select option

NWAIT Wait input Input Low

BMS Boot mode select Input – Sampled during reset

AIC IRQ0 - IRQ5 External interrupt request Input – PIO-controlled after reset

FIQ Fast external interrupt request Input – PIO-controlled after reset

Timer

TCLK0 - TCLK5 Timer external clock Input – PIO-controlled after reset

TIOA0 - TIOA5 Multipurpose timer I/O pin A I/O – PIO-controlled after reset

TIOB0 - TIOB5 Multipurpose timer I/O pin B I/O – PIO-controlled after reset

USART

SCK0 - SCK2 External serial clock I/O – PIO-controlled after reset

TXD0 - TXD2 Transmit data output Output – PIO-controlled after reset

RXD0 - RXD2 Receive data input Input – PIO-controlled after reset

SPI

SPCK SPI clock I/O – PIO-controlled after reset

MISO Master in slave out I/O – PIO-controlled after reset

MOSI Master out slave in I/O – PIO-controlled after reset

NSS Slave select Input Low PIO-controlled after reset

NPCS0 - NPCS3 Peripheral chip select Output Low PIO-controlled after reset

PIO PA0 - PA29 Parallel I/O port A I/O – Input after reset

PB0 - PB27 Parallel I/O port B I/O – Input after reset

WD NWDOVF Watchdog timer overflow Output Low Open drain

ADC

AD0-AD7 Analog input channels 0 - 7 Analog in –

AD0TRIG ADC0 external trigger Input – PIO-controlled after reset

AD1TRIG ADC1 external trigger Input – PIO-controlled after reset

ADVREF Analog reference Analog ref –

1745E–ATARM–18-Apr-06

AT91M55800A

DAC DA0 - DA1 Analog output channels 0 - 1 Analog out –

DAVREF Analog reference Analog ref –

Clock

XIN Main oscillator input Input –

XOUT Main oscillator output Output –

PLLRC RC filter for PLL Input –

XIN32 32 kHz oscillator input Input –

XOUT32 32 kHz oscillator output Output –

MCKO System clock Output –

APMC WAKEUP Wakeup request Input –

SHDN Shutdown request Output – Tri-state after backup reset

Reset

NRST Hardware reset input Input Low Schmidt trigger

NRSTBU Hardware reset input for battery

part Input Low Schmidt trigger

NTRI Tri-state mode select Input Low Sampled during reset

JTAG/ICE

JTAGSEL Selects between ICE and JTAG

mode Input –

TMS Test mode select Input – Schmidt trigger, internal pull-up

TDI Test data input Input – Schmidt trigger, internal pull-up

TDO Test data output Output –

TCK Test clock Input – Schmidt trigger, internal pull-up

NTRST Test reset input Input Low Schmidt trigger, internal pull-up

Power

VDDA Analog power Analog pwr –

GNDA Analog ground Analog gnd –

VDDBU Power backup Power –

GNDBU Ground backup Ground –

VDDCORE Digital core power Power –

VDDIO Digital I/O power Power –

VDDPLL Main oscillator and PLL power Power –

GND Digital ground Ground –

GNDPLL PLL ground Ground –

Table 3-1. Pin Description (Continued)

Module Name Function Type

Active

Level Comments

1745E–ATARM–18-Apr-06

AT91M55800A

4. Block Diagram

ARM7TDMI Core

Embedded

ICE

Reset

EBI: External

Bus Interface

Internal RAM

8K Bytes

ASB

Controller

AIC:

Advanced

Interrupt

Controller

AMBA Bridge

TC: Timer

Counter

Block 0

TC0

TC1

TC2

USART0

USART1 2 PDC

Channels

2 PDC

Channels

APB

ASB

NRST

D0 - D15

A1 - A23

A0/NLB

NRD/NOE

NWR0/NWE

NWR1/NUB

NCS0 - NCS7

PB19/TCLK0

PB22/TCLK1

PB25/TCLK2

PB20/TIOA0

PB21/TIOB0

PB23/TIOA1

PB24/TIOB1

PB26/TIOA2

PB27/TIOB2

PA10/IRQ1

PA11/IRQ2

PA12/IRQ3

PA13/FIQ

PA14/SCK0

PA15/TXD0

PA16/RXD0

PA17/SCK1

PA18/TXD1/NTRI

PA19/RXD1

PB11

PB12

PB13

PB14

PB15

PB16

TMS

TDO

TDI

TCK

NTRST

USART2 2 PDC

Channels

PA20/SCK2

PA21/TXD2

PA22/RXD2

SPI: Serial

Peripheral

Interface

TC: Timer

Counter

Block 1

TC3

TC4

TC5

PA0/TCLK3

PA3/TCLK4

PA6/TCLK5

PA1/TIOA3

PA2/TIOB3

PA4/TIOA4

PA5/TIOB4

PA7/TIOA5

PA8/TIOB5

PB10

PB4/IRQ5

PB5

PB1

PB2

PB8

PB9

PB3/IRQ4

PA9/IRQ0

PA24/MISO

PA25/MOSI

PA26/NPCS0/NSS

PA27/NPCS1

PA23/SPCK

PA28/NPCS2

PA29/NPCS3

PB18/BMS

EBI User

Interface

2 PDC

Channels

PB0

PB17

Clock

Generator

PLL

MCKO

PLLRC

XIN

XOUT

16 MHz

Chip ID

NWAIT

JTAGSEL

GNDBU

JTAGSEL

4-Channel

ADC0

AD0

AD1

AD2

AD3

4-Channel

ADC1

AD4

AD5

AD6

AD7

ADVREF

PB6/AD0TRIG

PB7/AD1TRIG

PIOB

Controller

PIOA Controller

WD: Watchdog Timer

NWDOVF

VDDIO, VDDCORE

GND

JTAG

WAKEUP

SHDN

DAC0

DAC1

DAVREF

DA0

DA1

VDDPLL

XOUT32

32.768 kHz

VDDBU

NRSTBU

RTC:

Real Time

Clock

APMC:

Advanced

Power

Management

Controller

GNDPLL

VDDA

GNDA

XIN32

Battery Backup

Analog

1745E–ATARM–18-Apr-06

AT91M55800A

5. Architectural Overview

The AT91M55800A microcontroller integrates an ARM7TDMI with its EmbeddedICE interface,

memories and peripherals. Its architecture consists of two main buses, the Advanced System

Bus (ASB) and the Advanced Peripheral Bus (APB). Designed for maximum performance and

controlled by the memory controller, the ASB interfaces the ARM7TDMI processor with the on-

chip 32-bit memories, the External Bus Interface (EBI) and the AMBA™ Bridge. The AMBA

Bridge drives the APB, which is designed for accesses to on-chip peripherals and optimized

for low power consumption.

The AT91M55800A microcontroller implements the ICE port of the ARM7TDMI processor on

dedicated pins, offering a complete, low cost and easy-to-use debug solution for target

debugging.

5.1 Memory

The AT91M55800A microcontroller embeds 8K bytes of internal SRAM. The internal memory

is directly connected to the 32-bit data bus and is single-cycle accessible.

The AT91M55800A microcontroller features an External Bus Interface (EBI), which enables

connection of external memories and application-specific peripherals. The EBI supports 8- or

16-bit devices and can use two 8-bit devices to emulate a single 16-bit device. The EBI imple-

ments the early read protocol, enabling faster memory accesses than standard memory

interfaces.

5.2 Peripherals

The AT91M55800A microcontroller integrates several peripherals, which are classified as sys-

tem or user peripherals. All on-chip peripherals are 32-bit accessible by the AMBA Bridge, and

can be programmed with a minimum number of instructions. The peripheral register set is

composed of control, mode, data, status and enable/disable/status registers.

An on-chip, 8-channel Peripheral Data Controller (PDC) transfers data between the on-chip

USARTs/SPI and the on and off-chip memories without processor intervention. One PDC

channel is connected to the receiving channel and one to the transmitting channel of each

USART and of the SPI.

Most importantly, the PDC removes the processor interrupt handling overhead and signifi-

cantly reduces the number of clock cycles required for a data transfer. It can transfer up to 64K

contiguous bytes. As a result, the performance of the microcontroller is increased and the

power consumption reduced.

5.2.1 System Peripherals

The External Bus Interface (EBI) controls the external memory and peripheral devices via an

8- or 16-bit data bus and is programmed through the APB. Each chip select line has its own

programming register.

The Advanced Power Management Controller (APMC) optimizes power consumption of the

product by controlling the clocking elements such as the oscillators and the PLL, system and

user peripheral clocks, and the power supplies.

The Advanced Interrupt Controller (AIC) controls the internal interrupt sources from the inter-

nal peripherals and the eight external interrupt lines (including the FIQ), to provide an interrupt

and/or fast interrupt request to the ARM7TDMI. It integrates an 8-level priority controller and,

using the Auto-vectoring feature, reduces the interrupt latency time.

1745E–ATARM–18-Apr-06

AT91M55800A

The Real-time Clock (RTC) peripheral is designed for very low power consumption, and com-

bines a complete time-of-day clock with alarm and a two-hundred year Gregorian calendar,

complemented by a programmable periodic interrupt.

The Parallel Input/Output Controllers (PIOA and PIOB) control the 58 I/O lines. They enable

the user to select specific pins for on-chip peripheral input/output functions, and general-pur-

pose input/output signal pins. The PIO controllers can be programmed to detect an interrupt

on a signal change from each line.

The Watchdog (WD) can be used to prevent system lock-up if the software becomes trapped

in a deadlock.

The Special Function (SF) module integrates the Chip ID and Reset Status registers.

5.2.2 User Peripherals

Three USARTs, independently configurable, enable communication at a high baud rate in syn-

chronous or asynchronous mode. The format includes start, stop and parity bits and up to 8

data bits. Each USART also features a Timeout and a Time Guard Register, facilitating the

use of the two dedicated Peripheral Data Controller (PDC) channels.

The six 16-bit Timer/Counters (TC) are highly programmable and support capture or waveform

modes. Each TC channel can be programmed to measure or generate different kinds of

waves, and can detect and control two input/output signals. Each TC also has three external

clock signals.

The SPI provides communication with external devices in master or slave mode. It has four

external chip selects which can be connected to up to 15 devices. The data length is program-

mable, from 8- to 16-bits.

The two identical 4-channel 10-bit analog-to-digital converters (ADC) are based on a Succes-

sive Approximation Register (SAR) approach.

1745E–ATARM–18-Apr-06

AT91M55800A

6. Associated Documentation

Table 6-1. Associated Documentation

Product Information Document Title

Literature

Number

AT91M55800A

Internal architecture of processor

ARM/Thumb instruction sets

Embedded in-circuit-emulator

ARM7TDMI (Thumb) Datasheet 0673

External memory interface mapping

Peripheral operations

Peripheral user interfaces

Ordering information

Packaging information

Soldering profile

Errata

AT91M55800A Datasheet (This document) 1745

DC Characteristics

Power consumption

Thermal and reliability coniderations

AC characteristics

AT91M55800A Electrical Characteristics 1727

Product overview

Ordering information

Packaging information

Soldering profile

AT91M55800A Summary Datasheet 1745S

1745E–ATARM–18-Apr-06

AT91M55800A

7. Product Overview

7.1 Power Supplies

The AT91M55800A has 5 kinds of power supply pins:

• VDDCORE pins, which power the chip core

• VDDIO pins, which power the I/O Lines

• VDDPLL pins, which power the oscillator and PLL cells

• VDDA pins, which power the analog peripherals ADC and DAC

• VDDBU pins, which power the RTC, the 32768 Hz oscillator and the Shut-down Logic of

the APMC

VDDIO and VDDCORE are separated to permit the I/O lines to be powered with 5V, thus

resulting in full TTL compliance.

The following ground pins are provided:

• GND for both VDDCORE and VDDIO

• GNDPLL for VDDPLL

•GNDA for VDDA

• GNDBU for VDDBU

All of these ground pins must be connected to the same voltage (generally the board electric

ground) with wires as short as possible. GNDPLL, GNDA and GNDBU are provided sepa-

rately in order to allow the user to add a decoupling capacitor directly between the power and

ground pads. In the same way, the PLL filter resistor and capacitors must be connected to the

device and to GNDBU with wires as short as possible. Also, the main oscillator crystal and the

32768 Hz crystal external load capacitances must be connected respectively to GNDPLL and

to GNDBU with wires as short as possible.

The main constraints applying to the different voltages of the device are:

• VDDBU must be lower than or equal to VDDCORE

• VDDA must be higher than or equal to VDDCORE

• VDDCORE must be lower than or equal to VDDIO

The nominal power combinations supported by the AT91M55800A are described in the follow-

ing table:

7.2 Input/Output Considerations

After the reset, the peripheral I/Os are initialized as inputs to provide the user with maximum

flexibility. It is recommended that in any application phase, the inputs to the AT91M55800A

microcontroller be held at valid logic levels to minimize the power consumption.

Table 7-1. Nominal Power Combinations

VDDIO VDDCORE VDDA VDDPLL VDDBU

Maximum Operating

Frequency

3V 3V 3V 3V 3V 33 MHz

3.3V 3.3V 3.3V 3.3V 3.3V 33 MHz

5V 3.3V 3.3V 3.3V 3.3V 33 MHz

1745E–ATARM–18-Apr-06

AT91M55800A

7.3 Master Clock

Master Clock is generated in one of the following ways, depending on programming in the

APMC registers:

• From the 32768 Hz low-power oscillator that clocks the RTC

• The on-chip main oscillator together with a PLL generate a software-programmable main

clock in the 500 Hz to 33 MHz range. The main oscillator can be bypassed to allow the user

to enter an external clock signal.

The Master Clock (MCK) is also provided as an output of the device on the pin MCKO, whose

state is controlled by the APMC module.

7.4 Reset

Reset restores the default states of the user interface registers (defined in the user interface of

each peripheral), and forces the ARM7TDMI to perform the next instruction fetch from address

zero. Aside from the program counter, the ARM7TDMI registers do not have defined reset

states.

7.4.1 NRST Pin

NRST is active low-level input. It is asserted asynchronously, but exit from reset is synchro-

nized internally to the MCK. At reset, the source of MCK is the Slow Clock (32768 Hz crystal),

and the signal presented on MCK must be active within the specification for a minimum of 10

clock cycles up to the rising edge of NRST, to ensure correct operation.

7.4.2 NTRST Pin

Test Access Port (TAP) reset functionality is provided through the NTRST signal.

The NTRST control pin initializes the selected TAP controller. The TAP controller involved in

this reset is determined according to the initial logical state applied on the JTAGSEL pin after

the last valid NRST.

In either Boundary Scan or ICE Mode a reset can be performed from the same or different cir-

cuitry, as shown in Figure 7-1 below. But in all cases, the NTRST like the NRST signal, must

be asserted after each power-up. (See the AT91M55800A electrical datasheet, Atmel lit°

1727, for the necessary minimum pulse assertion time.)

Figure 7-1. Separate or Common Reset Management

Notes: 1. NRST and NTRST handling in Debug Mode during development.

2. NRST and NTRST handling during production.

(1) (2)

Reset

Controller Reset

Controller

Reset

Controller

NTRST

NRST

NTRST

NRST

AT91M55800A AT91M55800A

1745E–ATARM–18-Apr-06

AT91M55800A

In order to benefit the most regarding the separation of NRST and NTRST during the Debug

phase of development, the user must independently manage both signals as shown in exam-

ple (1) of Figure 7-1 above. However, once Debug is completed, both signals are easily

managed together during production as shown in example (2) of Figure 7-1 above.

7.4.3 Watchdog Reset

The watchdog can be programmed to generate an internal reset. In this case, the reset has

the same effect as the NRST pin assertion, but the pins BMS and NTRI are not sampled. Boot

Mode and Tri-state Mode are not updated. If the NRST pin is asserted and the watchdog trig-

gers the internal reset, the NRST pin has priority.

7.5 Emulation Functions

7.5.1 Tri-state Mode

The AT91M55800A provides a Tri-state Mode, which is used for debug purposes. This

enables the connection of an emulator probe to an application board without having to desol-

der the device from the target board. In Tri-state Mode, all the output pin drivers of the

AT91M55800A microcontroller are disabled.

To enter Tri-state Mode, the pin NTRI must be held low during the last 10 clock cycles before

the rising edge of NRST. For normal operation the pin NTRI must be held high during reset, by

a resistor of up to 400K Ohm.

NTRI is multiplexed with I/O line PA18 and USART 1 serial data transmit line TXD1.

Standard RS232 drivers generally contain internal 400K Ohm pull-up resistors. If TXD1 is con-

nected to a device not including this pull-up, the user must make sure that a high level is tied

on NTRI while NRST is asserted.

7.5.2 JTAG/ICE Debug Mode

ARM Standard Embedded In-Circuit Emulation is supported via the JTAG/ICE port. It is con-

nected to a host computer via an external ICE Interface. The JTAG/ICE debug mode is

enabled when JTAGSEL is low.

In ICE Debug Mode the ARM Core responds with a non-JTAG chip ID which identifies the core

to the ICE system. This is not JTAG compliant.

7.5.3 IEEE 1149.1 JTAG Boundary-scan

JTAG Boundary-scan is enabled when JTAGSEL is high. The functions SAMPLE, EXTEST

and BYPASS are implemented. There is no JTAG chip ID. The Special Function module pro-

vides a chip ID which is independent of JTAG.

It is not possible to switch directly between JTAG and ICE operations. A chip reset must be

performed (NRST and NTRST) after JTAGSEL is changed.

7.6 Memory Controller

The ARM7TDMI processor address space is 4G bytes. The memory controller decodes the

internal 32-bit address bus and defines three address spaces:

• Internal memories in the four lowest megabytes

• Middle space reserved for the external devices (memory or peripherals) controlled by the

EBI

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AT91M55800A

• Internal peripherals in the four highest megabytes

In any of these address spaces, the ARM7TDMI operates in Little-Endian mode only.

7.6.1 Internal Memories

The AT91M55800A microcontroller integrates an 8-Kbyte SRAM bank. This memory bank is

mapped at address 0x0 (after the remap command), allowing ARM7TDMI exception vectors

between 0x0 and 0x20 to be modified by the software. The rest of the bank can be used for

stack allocation (to speed up context saving and restoring), or as data and program storage for

critical algorithms. All internal memory is 32 bits wide and single-clock cycle accessible. Byte

(8-bit), half-word (16-bit) or word (32-bit) accesses are supported and are executed within one

cycle. Fetching Thumb or ARM instructions is supported and internal memory can store twice

as many Thumb instructions as ARM ones.

7.6.2 Boot Mode Select

The ARM reset vector is at address 0x0. After the NRST line is released, the ARM7TDMI exe-

cutes the instruction stored at this address. This means that this address must be mapped in

nonvolatile memory after the reset.

The input level on the BMS pin during the last 10 clock cycles before the rising edge of the

NRST selects the type of boot memory (see Table 7-2).

The pin BMS is multiplexed with the I/O line PB18 that can be programmed after reset like any

standard PIO line.

7.6.3 Remap Command

The ARM vectors (Reset, Abort, Data Abort, Prefetch Abort, Undefined Instruction, Interrupt,

Fast Interrupt) are mapped from address 0x0 to address 0x20. In order to allow these vectors

to be redefined dynamically by the software, the AT91M55800A microcontroller uses a remap

command that enables switching between the boot memory and the internal RAM bank

addresses. The remap command is accessible through the EBI User Interface, by writing one

in RCB of EBI_RCR (Remap Control Register). Performing a remap command is mandatory if

access to the other external devices (connected to chip selects 1 to 7) is required. The remap

operation can only be changed back by an internal reset or an NRST assertion.

7.6.4 Abort Control

The abort signal providing a Data Abort or a Prefetch Abort exception to the ARM7TDMI is

asserted when accessing an undefined address in the EBI address space.

No abort is generated when reading the internal memory or by accessing the internal peripher-

als, whether the address is defined or not.

Table 7-2. Boot Mode Select

BMS Boot Mode

1 External 8-bit memory on NCS0

0 External 16-bit memory on NCS0

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AT91M55800A

7.7 External Bus Interface

The External Bus Interface handles the accesses between addresses 0x0040 0000 and

0xFFC0 0000. It generates the signals that control access to the external devices, and can

configure up to eight 16-Mbyte banks. In all cases it supports byte, half-word and word aligned

accesses.

For each of these banks, the user can program:

• Number of wait states

• Number of data float times (wait time after the access is finished to prevent any bus

contention in case the device is too long in releasing the bus)

• Data bus width (8-bit or 16-bit)

• With a 16-bit wide data bus, the user can program the EBI to control one 16-bit device

(Byte Access Select Mode) or two 8-bit devices in parallel that emulate a 16-bit memory

(Byte-write Access mode).

The External Bus Interface features also the Early Read Protocol, configurable for all the

devices, that significantly reduces access time requirements on an external device.

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AT91M55800A

8. Peripherals

The AT91M55800A peripherals are connected to the 32-bit wide Advanced Peripheral Bus.

Peripheral registers are only word accessible – byte and half-word accesses are not sup-

ported. If a byte or a half-word access is attempted, the memory controller automatically

masks the lowest address bits and generates a word access.

Each peripheral has a 16-Kbyte address space allocated (the AIC only has a 4-Kbyte address

space).

8.1 Peripheral Registers

The following registers are common to all peripherals:

• Control Register – Write-only register that triggers a command when a one is written to the

corresponding position at the appropriate address. Writing a zero has no effect.

• Mode Register – read/write register that defines the configuration of the peripheral. Usually

has a value of 0x0 after a reset.

• Data Register – read and/or write register that enables the exchange of data between the

processor and the peripheral.

• Status Register – Read-only register that returns the status of the peripheral.

• Enable/Disable/Status Registers – shadow command registers. Writing a one in the Enable

Writing a bit to zero has no effect. This register access method maximizes the efficiency of

bit manipulation, and enables modification of a register with a single non-interruptible

instruction, replacing the costly read-modify-write operation.

Unused bits in the peripheral registers are shown as “–” and must be written at 0 for upward

compatibility. These bits read 0.

8.2 Peripheral Interrupt Control

The Interrupt Control of each peripheral is controlled from the status register using the inter-

rupt mask. The status register bits are ANDed to their corresponding interrupt mask bits and

the result is then ORed to generate the Interrupt Source signal to the Advanced Interrupt

Controller.

The interrupt mask is read in the Interrupt Mask Register and is modified with the Interrupt

Enable Register and the Interrupt Disable Register. The enable/disable/status (or mask)

makes it possible to enable or disable peripheral interrupt sources with a non-interruptible sin-

gle instruction. This eliminates the need for interrupt masking at the AIC or Core level in real-

time and multi-tasking systems.

8.3 Peripheral Data Controller

An on-chip, 8-channel Peripheral Data Controller (PDC) transfers data between the on-chip

USARTs/SPI and the on and off-chip memories without processor intervention. One PDC

channel is connected to the receiving channel and one to the transmitting channel of each

USART and SPI.

The user interface of a PDC channel is integrated in the memory space of each peripheral. It

contains a 32-bit address pointer register and a 16-bit count register. When the programmed

data is transferred, an end of transfer interrupt is generated by the corresponding peripheral.

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AT91M55800A

Most importantly, the PDC removes the processor interrupt handling overhead and signifi-

cantly reduces the number of clock cycles required for a data transfer. It can transfer up to 64K

contiguous bytes. As a result, the performance of the microcontroller is increased and the

power consumption reduced.

8.4 System Peripherals

8.4.1 APMC: Advanced Power Management Controller

The AT91M55800A Advanced Power Management Controller allows optimization of power

consumption. The APMC enables/disables the clock inputs of most of the peripherals and the

ARM Core. Moreover, the main oscillator, the PLL and the analog peripherals can be put in

standby mode allowing minimum power consumption to be obtained. The APMC provides the

following operating modes:

• Normal: clock generator provides clock to the entire chip except the RTC.

• Wait mode: ARM Core clock deactivated

• Slow Clock mode: clock generator deactivated, master clock 32 kHz

• Standby mode: RTC active, all other clocks disabled

• Power down: RTC active, supply on the rest of the circuit deactivated

8.4.2 RTC: Real-time Clock

The AT91M55800A features a Real-time Clock (RTC) peripheral that is designed for very low

power consumption. It combines a complete time-of-day clock with alarm and a two-hundred

year Gregorian calendar, complemented by a programmable periodic interrupt.

The time and calendar values are coded in Binary-Coded Decimal (BCD) format. The time for-

mat can be 24-hour mode or 12-hour mode with an AM/PM indicator.

Updating time and calendar fields and configuring the alarm fields is performed by a parallel

capture on the 32-bit data bus. An entry control is performed to avoid loading registers with

incompatible BCD format data or with an incompatible date according to the current month/

year/century.

8.4.3 AIC: Advanced Interrupt Controller

The AIC has an 8-level priority, individually maskable, vectored interrupt controller, and drives

the NIRQ and NFIQ pins of the ARM7TDMI from:

• The external fast interrupt line (FIQ)

• The six external interrupt request lines (IRQ0 - IRQ5)

• The interrupt signals from the on-chip peripherals.

The AIC is largely programmable offering maximum flexibility, and its vectoring features

reduce the real-time overhead in handling interrupts.

The AIC also features a spurious vector, which reduces Spurious Interrupt handling to a mini-

mum, and a protect mode that facilitates the debug capabilities.

8.4.4 PIO: Parallel I/O Controller

The AT91M55800A has 58 programmable I/O lines. 13 pins are dedicated as general-purpose

I/O pins. The other I/O lines are multiplexed with an external signal of a peripheral to optimize

the use of available package pins. The PIO lines are controlled by two separate and identical

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AT91M55800A

PIO Controllers called PIOA and PIOB. The PIO controller enables the generation of an inter-

rupt on input change and insertion of a simple input glitch filter on any of the PIO pins.

8.4.5 WD: Watchdog

The Watchdog is built around a 16-bit counter, and is used to prevent system lock-up if the

software becomes trapped in a deadlock. It can generate an internal reset or interrupt, or

assert an active level on the dedicated pin NWDOVF. All programming registers are pass-

word-protected to prevent unintentional programming.

8.4.6 SF: Special Function

The AT91M55800A provides registers which implement the following special functions.

• Chip identification

• RESET status

8.5 User Peripherals

8.5.1 USART: Universal Synchronous/

Asynchronous Receiver Transmitter

The AT91M55800A provides three identical, full-duplex, universal synchronous/asynchronous

receiver/transmitters.

Each USART has its own baud rate generator, and two dedicated Peripheral Data Controller

channels. The data format includes a start bit, up to 8 data bits, an optional programmable par-

ity bit and up to 2 stop bits.

The USART also features a Receiver Timeout register, facilitating variable-length frame sup-

port when it is working with the PDC, and a Time-guard register, used when interfacing with

slow remote equipment.

8.5.2 TC: Timer Counter

The AT91M55800A features two Timer Counter blocks that include three identical 16-bit timer

counter channels. Each channel can be independently programmed to perform a wide range

of functions including frequency measurement, event counting, interval measurement, pulse

generation, delay timing and pulse-width modulation.

The Timer Counters can be used in Capture or Waveform mode, and all three counter chan-

nels can be started simultaneously and chained together.

8.5.3 SPI: Serial Peripheral Interface

The SPI provides communication with external devices in master or slave mode. It has four

external chip selects that can be connected to up to 15 devices. The data length is program-

mable, from 8- to 16-bit.

8.5.4 ADC: Analog-to-digital Converter

The two identical 4-channel 10-bit analog-to-digital converters (ADC) are based on a Succes-

sive Approximation Register (SAR) approach.

Each ADC has 4 analog input pins, AD0 to AD3 and AD4 to AD7, digital trigger input pins

AD0TRIG and AD1TRIG, and provides an interrupt signal to the AIC. Both ADCs share the

analog power supply pins VDDA and GNDA, and the input reference voltage pin ADVREF.

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AT91M55800A

Each channel can be enabled or disabled independently, and has its own data register. The

ADC can be configured to automatically enter Sleep mode after a conversion sequence, and

can be triggered by the software, the Timer Counter, or an external signal.

8.5.5 DAC: Digital-to-analog Converter

Each DAC has an analog output pin, DA0 and DA1, and provides an interrupt signal to the AIC

DA0IRQ and DA1IRQ. Both DACs share the analog power supply pins VDDA and GNDA, and

the input reference DAVREF.

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AT91M55800A

9. Memory Map

Figure 9-1. AT91M55800A Memory Map Before and after Remap Command

Address Function Size Abort Control

0xFFFFFFFF

0xFFC00000

0xFFBFFFFF

0x00400000

0x003FFFFF

0x00300000

0x002FFFFF

0x00200000

0x001FFFFF

0x00100000

0x000FFFFF

0x00000000

On-chip

Peripherals

External

Devices

(up to 8)

Reserved

On-chip

Device

Reserved

On-chip

Device

On-chip RAM

4M Bytes

Up to 8 Devices

Programmable Page Size

1, 4, 16, 64M Bytes

1M Byte

Yes

1M Byte No

Address Function Size Abort Control

0xFFFFFFFF

0xFFC00000

0xFFBFFFFF

0x00400000

0x003FFFFF

0x00300000

0x002FFFFF

0x00200000

0x001FFFFF

0x00100000

0x000FFFFF

0x00000000

On-chip

Peripherals

Reserved

On-chip RAM

Reserved

On-chip

Device

Reserved

On-chip

Device

External

Devices Selected

by NCS0

4M Bytes

1M Byte

Before Remap After Remap

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AT91M55800A

10. Peripheral Memory Map

Figure 1. AT91M55800A Peripheral Memory Map

Address Peripheral Peripheral Name Size

0xFFFFFFFF

0xFFFFF000

0xFFFFBFFF

0xFFFF8000

0xFFFF7FFF

0xFFFF4000

0xFFFF3FFF

0xFFFF0000

0xFFFD7FFF

0xFFFD4000

0xFFFC7FFF

0xFFFC4000

0xFFFCBFFF

0xFFFC8000

AIC

APMC

PIO B

TC 3,4,5

USART1

USART2

EBI

Advanced Interrupt Controller

WatchdogTimer

Advanced Power

Management Controller

Parallel I/O Controller B

Parallel I/O Controller A

Timer Counter Channels 3,4,5

Universal Synchronous/

Asynchronous

Receiver/Transmitter 1

Universal Synchronous/

Asynchronous

Receiver/Transmitter 2

Reserved

Special Function

External Bus Interface

4K Bytes

16K Bytes

Reserved

PIO A

Reserved

0xFFFD3FFF

0xFFFD0000

TC 0,1,2 Timer Counter Channels 0,1,2 16K Bytes

0xFFFC3FFF

0xFFFC0000

USART0 Universal Synchronous/

Asynchronous

Receiver/Transmitter 0

16K Bytes

0xFFFBBFFF

0xFFFB8000

0xFFFBFFFF

0xFFFBC000

RTC

SPI

Real-time Clock

Serial Peripheral Interface

16K Bytes

0xFFFB7FFF

0xFFFB4000

ADC1 Analog-to-digital Converter 1 16K Bytes

0xFFFAFFFF

0xFFFAC000

0xFFFB3FFF

0xFFFB0000

DAC1

ADC0

Digital-to-analog Converter 1

Analog-to-digital Converter 0

16K Bytes

0xFFFABFFF

0xFFFA8000

DAC0 Digital-to-analog Converter 0 16K Bytes

0xFFF03FFF

0xFFF00000

0xFFE03FFF

0xFFE00000

0xFFFEFFFF

0xFFFEC000

Reserved

0xFFC00000

16K Bytes

Reserved

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AT91M55800A

11. EBI: External Bus Interface

The EBI generates the signals that control the access to the external memory or peripheral

devices. The EBI is fully-programmable and can address up to 128M bytes. It has eight chip

selects and a 24-bit address bus.

The 16-bit data bus can be configured to interface with 8- or 16-bit external devices. Separate

read and write control signals allow for direct memory and peripheral interfacing.

The EBI supports different access protocols allowing single-clock cycle memory accesses.

The main features are:

• External memory mapping

• 8 active-low chip select lines

• 8- or 16-bit data bus

• Byte-write or byte-select lines

• Remap of boot memory

• Two different read protocols

• Programmable wait state generation

• External wait request

• Programmable data float time

The EBI User Interface is described on page 48.

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AT91M55800A

11.1 External Memory Mapping

The memory map associates the internal 32-bit address space with the external 24-bit

address bus.

The memory map is defined by programming the base address and page size of the external

memories (see EBI User Interface registers EBI_CSR0 to EBI_CSR7). Note that A0 - A23 is

only significant for 8-bit memory; A1 - A23 is used for 16-bit memory.

If the physical memory device is smaller than the programmed page size, it wraps around and

appears to be repeated within the page. The EBI correctly handles any valid access to the

memory device within the page. (See Figure 11-1.)

In the event of an access request to an address outside any programmed page, an Abort sig-

nal is generated. Two types of Abort are possible: instruction prefetch abort and data abort.

The corresponding exception vector addresses are respectively 0x0000 000C and 0x0000

0010. It is up to the system programmer to program the error handling routine to use in case of

an Abort (see the ARM7TDMI datasheet for further information).

Figure 11-1. External Memory Smaller than Page Size

1-Mbyte Device

Memory

Map

Low

Low Base

Base + 1M Byte

Base + 2M Byte

Base + 3M Byte

Base + 4M Byte

Repeat 1

Repeat 2

Repeat 3

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AT91M55800A

11.2 EBI Pin Description

The following table shows how certain EBI signals are multiplexed:

Name Description Type

A0 - A23 Address bus (output) Output

D0 - D15 Data bus (input/output) I/O

NCS0 - NCS7 Active low chip selects (output) Output

NRD Read Enable (output) Output

NWR0 - NWR1 Lower and upper write enable (output) Output

NOE Output enable (output) Output

NWE Write enable (output) Output

NUB, NLB Upper and lower byte-select (output) Output

NWAIT Wait request (input) Input

Multiplexed Signals Functions

A0 NLB 8- or 16-bit data bus

NRD NOE Byte-write or byte-select access

NWR0 NWE Byte-write or byte-select access

NWR1 NUB Byte-write or byte-select access

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AT91M55800A

11.3 Data Bus Width

A data bus width of 8 or 16 bits can be selected for each chip select. This option is controlled

by the DBW field in the EBI_CSR (Chip-select Register) for the corresponding chip select.

Figure 11-2 shows how to connect a 512K x 8-bit memory on NCS2.

Figure 11-2. Memory Connection for an 8-bit Data Bus

Figure 11-3 shows how to connect a 512K x 16-bit memory on NCS2.

Figure 11-3. Memory Connection for a 16-bit Data Bus

11.4 Byte-write or Byte-select Access

Each chip select with a 16-bit data bus can operate with one of two different types of write

access:

• Byte-write Access supports two Byte-write and a single read signal.

• Byte-select Access selects upper and/or lower byte with two byte-select lines, and separate

read and write signals.

This option is controlled by the BAT field in the EBI_CSR (Chip-select Register) for the corre-

sponding chip select.

Byte-write Access is used to connect 2 x 8-bit devices as a 16-bit memory page.

• The signal A0/NLB is not used.

• The signal NWR1/NUB is used as NWR1 and enables upper byte writes.

• The signal NWR0/NWE is used as NWR0 and enables lower byte writes.

• The signal NRD/NOE is used as NRD and enables half-word and byte reads.

Figure 11-4 shows how to connect two 512K x 8-bit devices in parallel on NCS2.

EBI

D0 - D7

D8 - D15

A1 - A18

NWR0

NRD

NCS2

D0 - D7

A1 - A18

Write Enable

Output Enable

Memory Enable

NWR1

EBI

D0 - D7

D8 - D15

A1 - A19

NLB

NWE

NOE

NCS2

D0 - D7

D8 - D15

A0 - A18

Low Byte Enable

Write Enable

Output Enable

Memory Enable

NUB High Byte Enable

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AT91M55800A

Figure 11-4. Memory Connection for 2 x 8-bit Data Busses

Byte-select Access is used to connect 16-bit devices in a memory page.

• The signal A0/NLB is used as NLB and enables the lower byte for both read and write

operations.

• The signal NWR1/NUB is used as NUB and enables the upper byte for both read and write

operations.

• The signal NWR0/NWE is used as NWE and enables writing for byte or half word.

• The signal NRD/NOE is used as NOE and enables reading for byte or half word.

Figure 11-5 shows how to connect a 16-bit device with byte and half-word access (e.g. 16-bit

SRAM) on NCS2.

Figure 11-5. Connection for a 16-bit Data Bus with Byte and Half-word Access

EBI

D0 - D7

D8 - D15

A1 - A19

NWR0

NRD

NCS2

D0 - D7

A0 - A18

Write Enable

Read Enable

Memory Enable

NWR1

D8 - D15

A0 - A18

Write Enable

Read Enable

Memory Enable

EBI

D0 - D7

D8 - D15

A1 - A19

NLB

NWE

NOE

NCS2

D0 - D7

D8 - D15

A0 - A18

Low Byte Enable

Write Enable

Output Enable

Memory Enable

NUB High Byte Enable

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AT91M55800A

Figure 11-6 shows how to connect a 16-bit device without byte access (e.g. Flash) on NCS2.

Figure 11-6. Connection for a 16-bit Data Bus Without Byte-write Capability.

11.5 Boot on NCS0

Depending on the device and the BMS pin level during the reset, the user can select either an

8-bit or 16-bit external memory device connected on NCS0 as the Boot Memory. In this case,

EBI_CSR0 (Chip-select Register 0) is reset at the following configuration for chip select 0:

• 8 wait states (WSE = 1, NWS = 7)

• 8-bit or 16-bit data bus width, depending on BMS

Byte access type and number of data float time are respectively set to Byte-write Access and

0. With a nonvolatile memory interface, any value can be programmed for these parameters.

Before the remap command, the user can modify the chip select 0 configuration, programming

the EBI_CSR0 with exact boot memory characteristics. The base address becomes effective

after the remap command, but the new number of wait states can be changed immediately.

This is useful if a boot sequence needs to be faster.

EBI

D0 - D7

D8 - D15

A1 - A19

NLB

NWE

NOE

NCS2

D0 - D7

D8 - D15

A0 - A18

Write Enable

Output Enable

Memory Enable

NUB

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AT91M55800A

11.6 Read Protocols

The EBI provides two alternative protocols for external memory read access: standard and

early read. The difference between the two protocols lies in the timing of the NRD (read cycle)

waveform.

The protocol is selected by the DRP field in EBI_MCR (Memory Control Register) and is valid

for all memory devices. Standard read protocol is the default protocol after reset.

Note: In the following waveforms and descriptions, NRD represents NRD and NOE since the two sig-

nals have the same waveform. Likewise, NWE represents NWE, NWR0 and NWR1 unless

NWR0 and NWR1 are otherwise represented. ADDR represents A0 - A23 and/or A1 - A23.

11.6.1 Standard Read Protocol

Standard read protocol implements a read cycle in which NRD and NWE are similar. Both are

active during the second half of the clock cycle. The first half of the clock cycle allows time to

ensure completion of the previous access as well as the output of address and NCS before the

read cycle begins.

During a standard read protocol, external memory access, NCS is set low and ADDR is valid

at the beginning of the access while NRD goes low only in the second half of the master clock

cycle to avoid bus conflict (see Figure 11-7). NWE is the same in both protocols. NWE always

goes low in the second half of the master clock cycle (see Figure 11-8).

Figure 11-7. Standard Read Protocol

11.6.2 Early Read Protocol

Early read protocol provides more time for a read access from the memory by asserting NRD

at the beginning of the clock cycle. In the case of successive read cycles in the same memory,

NRD remains active continuously. Since a read cycle normally limits the speed of operation of

the external memory system, early read protocol can allow a faster clock frequency to be

used. However, an extra wait state is required in some cases to avoid contentions on the

external bus.

ADDR

NCS

NWE

MCK

NRD

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AT91M55800A

Figure 11-8. Early Read Protocol

11.6.3 Early Read Wait State

In early read protocol, an early read wait state is automatically inserted when an external write

cycle is followed by a read cycle to allow time for the write cycle to end before the subsequent

read cycle begins (see Figure 11-9). This wait state is generated in addition to any other pro-

grammed wait states (i.e. data float wait).

No wait state is added when a read cycle is followed by a write cycle, between consecutive

accesses of the same type or between external and internal memory accesses.

Early read wait states affect the external bus only. They do not affect internal bus timing.

Figure 11-9. Early Read Wait State

ADDR

NCS

NWE

MCK

NRD

ADDR

NCS

NWE

MCK

Write Cycle Early Read Wait Read Cycle

NRD

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AT91M55800A

11.7 Write Data Hold Time

During write cycles in both protocols, output data becomes valid after the falling edge of the

NWE signal and remains valid after the rising edge of NWE, as illustrated in the figure below.

The external NWE waveform (on the NWE pin) is used to control the output data timing to

guarantee this operation.

It is therefore necessary to avoid excessive loading of the NWE pins, which could delay the

write signal too long and cause a contention with a subsequent read cycle in standard

protocol.

Figure 11-10. Data Hold Time

In early read protocol the data can remain valid longer than in standard read protocol due to

the additional wait cycle which follows a write access.

ADDR

NWE

Data output

MCK

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AT91M55800A

11.8 Wait States

The EBI can automatically insert wait states. The different types of wait states are listed below:

• Standard wait states

• Data float wait states

• External wait states

• Chip select change wait states

• Early read wait states (as described in Read Protocols)

11.8.1 Standard Wait States

Each chip select can be programmed to insert one or more wait states during an access on

the corresponding device. This is done by setting the WSE field in the corresponding

EBI_CSR. The number of cycles to insert is programmed in the NWS field in the same

Below is the correspondence between the number of standard wait states programmed and

the number of cycles during which the NWE pulse is held low:

0 wait states 1/2 cycle

1 wait state 1 cycle

For each additional wait state programmed, an additional cycle is added.

Figure 11-11. One Wait State Access

Notes: 1. Early Read Protocol

2. Standard Read Protocol

11.8.2 Data Float Wait State

Some memory devices are slow to release the external bus. For such devices it is necessary

to add wait states (data float waits) after a read access before starting a write access or a read

access to a different external memory.

The Data Float Output Time (tDF) for each external memory device is programmed in the TDF

field of the EBI_CSR register for the corresponding chip select. The value (0 - 7 clock cycles)

ADDR

NCS

NWE

MCK

1 Wait State Access

NRD (1) (2)

1745E–ATARM–18-Apr-06

AT91M55800A

indicates the number of data float waits to be inserted and represents the time allowed for the

data output to go high impedance after the memory is disabled.

Data float wait states do not delay internal memory accesses. Hence, a single access to an

external memory with long tDF will not slow down the execution of a program from internal

memory.

The EBI keeps track of the programmed external data float time during internal accesses, to

ensure that the external memory system is not accessed while it is still busy.

Internal memory accesses and consecutive accesses to the same external memory do not

have added Data Float wait states.

Figure 11-12. Data Float Output Time

Notes: 1. Early Read Protocol

2. Standard Read Protocol

11.8.3 External Wait

The NWAIT input can be used to add wait states at any time. NWAIT is active low and is

detected on the rising edge of the clock.

If NWAIT is low at the rising edge of the clock, the EBI adds a wait state and changes neither

the output signals nor its internal counters and state. When NWAIT is de-asserted, the EBI fin-

ishes the access sequence.

The NWAIT signal must meet setup and hold requirements on the rising edge of the clock.

ADDR

NRD

D0-D15

MCK

(1) (2)

NCS

1745E–ATARM–18-Apr-06

AT91M55800A

Figure 11-13. External Wait

Notes: 1. Early Read Protocol

2. Standard Read Protocol

11.8.4 Chip Select Change Wait States

A chip select wait state is automatically inserted when consecutive accesses are made to two

different external memories (if no wait states have already been inserted). If any wait states

have already been inserted, (e.g., data float wait) then none are added.

Figure 11-14. Chip Select Wait

Notes: 1. Early Read Protocol

2. Standard Read Protocol

ADDR

NCS

NWE

MCK

NRD (1) (2)

NWAIT

NCS1

NCS2

MCK

Mem 1 Chip Select Wait Mem 2

NRD

NWE

(1) (2)

1745E–ATARM–18-Apr-06

AT91M55800A

11.9 Memory Access Waveforms

Figure 11-15 through Figure 11-18 show examples of the two alternative protocols for external

memory read access.

Figure 11-15. Standard Read Protocol with no tDF

Read Mem 1 Write Mem 1 Read Mem 1 Read Mem 2 Write Mem 2 Read Mem 2

Chip Select

Change Wait

A0 - A23

NRD

NWE

NCS1

NCS2

D0 - D15 (Mem 1)

D0 - D15 (Mem 2)

D0 - D15 (AT91)

MCK

tWHDX tWHDX

1745E–ATARM–18-Apr-06

AT91M55800A

Figure 11-16. Early Read Protocol with no tDF

Read

Mem 1

Write

Mem 1

A0 - A23

NRD

NWE

NCS1

NCS2

D0 - D15 (Mem 1)

D0 - D15 (Mem 2)

D0 - D15 (AT91)

MCK

Early Read

Wait Cycle

Read

Mem 1

Read

Mem 2

Write

Mem 2

Early Read

Wait Cycle

Read

Mem 2

Chip Select

Change Wait

Long tWHDX Long tWHDX

1745E–ATARM–18-Apr-06

AT91M55800A

Figure 11-17. Standard Read Protocol with tDF

Read Mem 1

Write

Mem 1

A0 - A23

NRD

NWE

NCS1

NCS2

D0 - D15 (Mem 1)

D0 - D15 (Mem 2)

D0 - D15 (AT91)

MCK

Data

Float Wait

Read Mem 1

Data

Float Wait

Read

Mem 2 Read Mem 2

Data

Float Wait

Write

Mem 2

Write

Mem 2

Write

Mem 2

tWHDX

tDF tDF

tDF

1745E–ATARM–18-Apr-06

AT91M55800A

Figure 11-18. Early Read Protocol with tDF

Read Mem 1

Write

Mem 1

A0 - A23

NRD

NWE

NCS1

NCS2

D0 - D15 (Mem 1)

D0 - D15 (Mem 2)

D0 - D15 (AT91)

MCK

Data

Float Wait

Early

Read Wait Read Mem 1

Data

Float Wait

Read

Mem 2 Read Mem 2

Data

Float Wait

Write

Mem 2

Write

Mem 2

Write

Mem 2

WHDX

1745E–ATARM–18-Apr-06

AT91M55800A

Figure 11-19 through Figure 11-25 show the timing cycles and wait states for read and write

access to the various AT91M55800A external memory devices. The configurations described

are as follows:

Table 11-1. Memory Access Waveforms

Figure Number Number of Wait States Bus Width Size of Data Transfer

11-19 0 16 Word

11-20 1 16 Word

11-21 1 16 Half-word

11-22 0 8 Word

11-23 1 8 Half-word

11-24 1 8 Byte

11-25 0 16 Byte

1745E–ATARM–18-Apr-06

AT91M55800A

Figure 11-19. 0 Wait States, 16-bit Bus Width, Word Transfer

ADDR ADDR+1

B2B1 B

4 B3

B4 B3 B2 B1

MCK

A1 - A23

NCS

NRD

D0 - D15

Internal Bus X X B2 B1

READ ACCESS

NRD

B2 B1B4 B3 D0 - D15

WRITE ACCESS

NWE

B2 B1 B4 B3 D0 - D15

NLB

NUB

· Standard Protocol

· Early Protocol

· Byte Write/

Byte Select Option

1745E–ATARM–18-Apr-06

AT91M55800A

Figure 11-20. 1 Wait State, 16-bit Bus Width, Word Transfer

ADDR ADDR+1

B2B1

B4 B3

X X B2 B1B4 B3 B2 B1

1 Wait State 1 Wait State

MCK

A1 - A23

NCS

NRD

D0 - D15

Internal Bus

WRITE ACCESS

READ ACCESS

NRD

D0 - D15

· Standard Protocol

· Early Protocol

B4B3

NWE

D0 - D15 B2B1B4B3

NLB

NUB

B2 B1

· Byte Write/

Byte Select Option

1745E–ATARM–18-Apr-06

AT91M55800A

Figure 11-21. 1 Wait State, 16-bit Bus Width, Half-word Transfer

B2 B1

1 Wait State

MCK

A1 - A23

NCS

NRD

D0 - D15

Internal Bus X X B2 B1

READ ACCESS

· Standard Protocol

NLB

NUB

· Early Protocol

B2 B1

NRD

D0 - D15

WRITE ACCESS

NWE

B2 B1

D0 - D15

· Byte Write/

Byte Select Option

1745E–ATARM–18-Apr-06

AT91M55800A

Figure 11-22. 0 Wait States, 8-bit Bus Width, Word Transfer

ADDR ADDR+1

X B1

X B3 B2 B1

MCK

A0 - A23

NCS

NRD

D0 - D15

Internal Bus

ADDR+2 ADDR+3

X X B2 B1

X B2

X X X B1

X B3X B4

B4 B3 B2 B1

READ ACCESS

· Standard Protocol

· Early Protocol

NRD

X B1

D0 - D15 X B2 X B3X B4

WRITE ACCESS

NWR0

NWR1

X B1

D0 - D15 X B2 X B3X B4

1745E–ATARM–18-Apr-06

AT91M55800A

Figure 11-23. 1 Wait State, 8-bit Bus Width, Half-word Transfer

ADDR

X B1

1 Wait State

MCK

A0 - A23

NCS

NRD

D0 - D15

Internal Bus

ADDR+1

1 Wait State

X X B2 B1

X B2

X X X B1

READ ACCESS

· Standard Protocol

· Early Protocol

NRD

X B1

D0 - D15 X B2

WRITE ACCESS

NWR0

X B1

D0 - D15 X B2

NWR1

1745E–ATARM–18-Apr-06

AT91M55800A

Figure 11-24. 1 Wait State, 8-bit Bus Width, Byte Transfer

XB1

1 Wait State

MCK

A0 - A23

NCS

NRD

D0-D15

Internal Bus X X X B1

READ ACCESS

· Standard Protocol

· Early Protocol

D0 - D15 X B1

WRITE ACCESS

NWR0

D0-D15 X B1

NRD

NWR1

1745E–ATARM–18-Apr-06

AT91M55800A

Figure 11-25. 0 Wait States, 16-bit Bus Width, Byte Transfer

MCK

A1-A23

NCS

NWR1

D0-D15 X B

ADDR X X X 0 ADDR X X X 0

ADDR X X X 0 ADDR X X X 1

Internal Address

Internal Bus X X X B

X X B

NLB

NUB

READ ACCESS

· Standard Protocol

NRD

· Early Protocol

NRD

D0-D15 XB

WRITE ACCESS

NWR0

D0-D15 B

Byte Write Option

Byte Select Option

NWE

1745E–ATARM–18-Apr-06

AT91M55800A

11.10 EBI User Interface

The EBI is programmed using the registers listed in the table below. The Remap Control Reg-

ister (EBI_RCR) controls exit from Boot Mode (see Section 11.5 ”Boot on NCS0” on page 29)

The Memory Control Register (EBI_MCR) is used to program the number of active chip

selects and data read protocol. Eight Chip-select Registers (EBI_CSR0 to EBI_CSR7) are

used to program the parameters for the individual external memories. Each EBI_CSR must be

programmed with a different base address, even for unused chip selects.

Base Address: 0xFFE00000 (Code Label EBI_BASE)

Notes: 1. 8-bit boot (if BMS is detected high)

2. 16-bit boot (if BMS is detected low)

Table 11-2. EBI Memory Map

Offset Register Name Access Reset State

0x00 Chip-select Register 0 EBI_CSR0 Read/Write 0x0000203E(1)

0x0000203D(2)

0x04 Chip-select Register 1 EBI_CSR1 Read/Write 0x10000000

0x08 Chip-select Register 2 EBI_CSR2 Read/Write 0x20000000

0x0C Chip-select Register 3 EBI_CSR3 Read/Write 0x30000000

0x10 Chip-select Register 4 EBI_CSR4 Read/Write 0x40000000

0x14 Chip-select Register 5 EBI_CSR5 Read/Write 0x50000000

0x18 Chip-select Register 6 EBI_CSR6 Read/Write 0x60000000

0x1C Chip-select Register 7 EBI_CSR7 Read/Write 0x70000000

0x20 Remap Control Register EBI_RCR Write-only –

0x24 Memory Control Register EBI_MCR Read/Write 0

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AT91M55800A

11.10.1 EBI Chip Select Register

Access Type: Read/Write

Reset Value: See Table 11-2

Absolute Address: 0xFFE00000 - 0xFFE0001C

• DBW: Data Bus Width

• NWS: Number of Wait States

This field is valid only if WSE is set.

• WSE: Wait State Enable (Code Label EBI_WSE)

0 = Wait state generation is disabled. No wait states are inserted.

1 = Wait state generation is enabled.

31 30 29 28 27 26 25 24

23 22 21 20 19 18 17 16

BA ––––

15 14 13 12 11 10 9 8

––CSENBAT TDF PAGES

76543210

PAGES – WSE NWS DBW

DBW Data Bus Width

Code Label

EBI_DBW

0 0 Reserved –

0 1 16-bit data bus width EBI_DBW_16

1 0 8-bit data bus width EBI_DBW_8

1 1 Reserved –

NWS Number of Standard Wait States

Code Label

EBI_NWS

0 0 0 1 EBI_NWS_1

0 0 1 2 EBI_NWS_2

0 1 0 3 EBI_NWS_3

0 1 1 4 EBI_NWS_4

1 0 0 5 EBI_NWS_5

1 0 1 6 EBI_NWS_6

1 1 0 7 EBI_NWS_7

1 1 1 8 EBI_NWS_8

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AT91M55800A

• PAGES: Page Size

• TDF: Data Float Output Time

• BAT: Byte Access Type

• CSEN: Chip Select Enable (Code Label EBI_CSEN)

0 = Chip select is disabled.

1 = Chip select is enabled.

• BA: Base Address (Code Label EBI_BA)

These bits contain the highest bits of the base address. If the page size is larger than 1M byte, the unused bits of the base

address are ignored by the EBI decoder.

PAGES Page Size Active Bits in Base Address

Code Label

EBI_PAGES

0 0 1M Byte 12 Bits (31-20) EBI_PAGES_1M

0 1 4M Bytes 10 Bits (31-22) EBI_PAGES_4M

1 0 16M Bytes 8 Bits (31-24) EBI_PAGES_16M

1 1 64M Bytes 6 Bits (31-26) EBI_PAGES_64M

TDF Number of Cycles Added after the Transfer

Code Label

EBI_TDF

0 0 0 0 EBI_TDF_0

0 0 1 1 EBI_TDF_1

0 1 0 2 EBI_TDF_2

0 1 1 3 EBI_TDF_3

1 0 0 4 EBI_TDF_4

1 0 1 5 EBI_TDF_5

1 1 0 6 EBI_TDF_6

1 1 1 7 EBI_TDF_7

BAT Selected BAT

Code Label

EBI_BAT

0 Byte-write access type EBI_BAT_BYTE_WRITE

1 Byte-select access type EBI_BAT_BYTE_SELECT

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AT91M55800A

11.10.2 EBI Remap Control Register

Access Type: Write-only

Absolute Address: 0xFFE00020

Offset: 0x20

• RCB: Remap Command Bit (Code Label EBI_RCB)

0 = No effect.

1 = Cancels the remapping (performed at reset) of the page zero memory devices.

11.10.3 EBI Memory Control Register

Access Type: Read/Write

Reset Value: 0

Absolute Address: 0xFFE00024

Offset: 0x24

• DRP: Data Read Protocol

31 30 29 28 27 26 25 24

––––––––

23 22 21 20 19 18 17 16

––––––––

15 14 13 12 11 10 9 8

––––––––

76543210

–––––––RCB

31 30 29 28 27 26 25 24

––––––––

23 22 21 20 19 18 17 16

––––––––

15 14 13 12 11 10 9 8

––––––––

76543210

–––DRP––––

DRP Selected DRP

Code Label

EBI_DRP

0 Standard read protocol for all external memory devices enabled EBI_DRP_STANDARD

1 Early read protocol for all external memory devices enabled EBI_DRP_EARLY

1745E–ATARM–18-Apr-06

AT91M55800A

12. APMC: Advanced Power Management Controller

The AT91M55800A features an Advanced Power Management Controller, which optimizes

both the power consumption of the device and the complete system. The APMC controls the

clocking elements such as the oscillators and the PLL, the core and the peripheral clocks, and

has the capability to control the system power supply.

Main Power is used throughout this document to identify the voltages powering the

AT91M55800A and other components of the system, with the exception of the Battery Backup

voltage, which is applied to the VDDBU. Main Power supplies VDDIO, VDDCORE and, if

required, the analog voltage VDDA. A battery or battery capacitor generally supplies the Bat-

tery Backup Power.

The APMC consists of the following elements:

• The RTC Oscillator, which provides the Slow Clock at 32768 Hz.

• The Main Oscillator, which provides a clock that depends on the frequency of the crystal

connected to the XIN and XOUT pins.

• The Phase Lock Loop.

• The ARM Core Clock Controller, which allows entry to the Idle Mode.

• The Peripheral Clock Controller, which conserves the power consumption of unused

peripherals.

• The Master Clock Output Controller.

• The Shut-down Logic, which controls the Main Power.

Figure 12-1. APMC Module

Note: The RTC peripheral is described in a separate section.

Advanced Peripheral Bus

IRQ

Control

PLL TimerOSC Timer

PLL Main OSC

Device

Clock

Control

RTC (1)

RTC

OSC

Reset Control

Shut-down

Logic

APMC

VDDIO/VDDCORE

VDDBU

WAKEUP

NRSTBU

XIN32

XOUT32

XIN

XOUT

SHDN

APMCIRQ

Arm Clock

Peripheral Clocks

ARM Interrupt (IRQ and FIQ)

Alarm

SLCKIRQ

Slow Clock_SLCK

1745E–ATARM–18-Apr-06

AT91M55800A

12.1 Operating Modes

Five operating modes are supported by the APMC and offer different power consumption lev-

els and event response latency times.

•Normal Mode:

The Main Power supply is switched on; the ARM Core Clock is enabled and the peripheral

clocks are enabled according to the application requirements.

• Idle Mode:

The Main Power is switched on; the ARM Core Clock is disabled and waiting for the next

interrupt (or a main reset); the peripheral clocks are enabled according to the application

requirements and the PDC transfers are still possible.

• Slow Clock Mode:

Similar to Normal Mode, but the Main Oscillator and the PLL are switched off to save

power; the device core and peripheral run in Slow Clock Mode; Note that Slow Clock

Mode is the mode selected after the reset.

• Standby Mode:

A combination of the Slow Clock Mode and the Idle Mode, which enables the processor to

respond quickly to a wake-up event by keeping very low power consumption.

• Power-down Mode:

The Main Power supply is turned off at the external power source until a programmable

edge on the wake-up signal or a programmable RTC Alarm occurs.

1745E–ATARM–18-Apr-06

AT91M55800A

Figure 12-2. APMC Block Diagram

ARM7TDMI

Clock

NIRQ

NFIQ

IDLE MODE

APMC_SCDR

APMC_SCSR

MCK (Master Clock)

Prescaler

Peripheral Clocks

Clear

Set

XIN

XOUT

MCKO

MCKODS

PRES

APMC_PCER

APMC_PCDR

APMC_PCSR

MOSCBYP

MUL

MOSCEN CSS

PLL

Main

Oscillator

Reset

Control

RTC

Oscillator

RTC (1)

Backup Reset

Slow Clock

RTC Alarm

Shut-down

Alarm

Backup

Reset

Wake-up

Acknowledge

Alarm Shut-down

Alarm

Output

Controller

SHDN

WKACKS SHDALS

WKEDG

WAKEUP

Edge Detector

WKACKC

ALWKEN

ALSHEN

SHDALC

NRSTBU

XIN32

XOUT32

Battery Power

VDDBU

Main Power

VDDIO

VDDCORE

Note: 1. The RTC is described in another chapter

1745E–ATARM–18-Apr-06

AT91M55800A

12.2 Slow Clock Generator

The AT91M55800A has a very low power 32 kHz oscillator powered by the backup battery

voltage supplied on the VDDBU pins. The XIN32 and XOUT32 pins must be connected to a

32768 Hz crystal. The oscillator has been especially designed to connect to a 6 pF typical load

capacitance crystal and does not require any external capacitor, as it integrates the XIN32 and

XOUT32 capacitors to ground. For a higher typical load capacitance, two external capaci-

tances must be wired as shown in Figure 12-3:

Figure 12-3. Higher Typical Load Capacitance

12.2.1 Backup Reset Controller

The backup reset controller initializes the logic supplied by the backup battery power. A simple

RC circuit connected to the NRSTBU pin provides a power-on reset signal to the RTC and the

shutdown logic. When the reset signal increases and as the startup time of the 32 kHz oscilla-

tor is around 300 ms, the AT91M55800A maintains the internal backup reset signal for 32768

oscillator clock cycles in order to guarantee the backup power supplied logic does not operate

before the oscillator output is stabilized.

Alternatively, a reset supervisor can be connected to the NRSTBU pin in place of the RC.

12.2.2 Slow Clock

The Slow Clock is the only clock considered permanent in an AT91M55800A-based system

and is essential in the operations of the APMC (Advanced Power Management Controller). In

any use-case, a 32768 Hz crystal must be connected to the XIN32 and XOUT32 pins in order

to ensure that the Slow Clock is present.

XIN32 XOUT32 GNDPLL

CL2

CL1

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AT91M55800A

12.3 Clock Generator

The clock generator consists of the main oscillator, the PLL and the clock selection logic with

its prescaler. It aims at selecting the Master Clock, called MCK throughout this datasheet. The

clock generator also contains the circuitry needed to drive the MCKO pin with the master clock

signal.

12.3.1 Main Oscillator

The Main Oscillator is designed for a 3 to 20 MHz fundamental crystal. The typical crystal con-

nection is illustrated in Figure 12-4. The 1 kΩ resistor is only required for crystals with

frequencies lower than 8 MHz. The oscillator contains 25 pF capacitances on each XIN and

XOUT pin. Consequently, CL1 and CL2 can be removed when a crystal with a load capaci-

tance of 12.5 pF is used.

Figure 12-4. Typical Crystal Connection of Main Oscillator

The Main Oscillator can be bypassed if the MOSCBYP bit in the Clock Generator Mode Regis-

ter (APMC_CGMR) is set to 1. In this case, any frequency (up to the maximum specified in the

electrical characteristics datasheet) can be input on the XIN pin. If the PLL is used, a minimum

input frequency is required.

To minimize the power required to start up the system, the Main Oscillator is disabled after the

reset. The software can deactivate the Main Oscillator to reduce the power consumption by

clearing the MOSCEN bit in APMC_CGMR. The MOSCS (Main Oscillator Status) bit in

APMC_SR is automatically cleared, indicating that the Main Oscillator is off.

Writing the MOSCEN bit in APMC_CGMR reactivates the Main Oscillator and loads the value

written in the OSCOUNT field in APMC_CGMR in the oscillator counter. Then, the oscillator

counter decrements every 8 clock cycles and when it reaches 0, the MOSCS bit is set and can

provide an interrupt.

12.3.2 Phase Lock Loop

The Main Oscillator output signal feeds the phase lock loop, which aims at multiplying the fre-

quency of its input signal by a number up to 64. This number is programmed in the MUL field

of APMC_CGMR and the multiplication ratio is the programmed value plus one (MUL+1). If a

null value is programmed into MUL, the PLL is automatically disabled to save power.

The PLL is disabled at reset to minimize the power consumption.

A start-up sequence must be executed to enable the PLL if it is disabled. This sequence is

started by writing a new MUL value in APMC_CGMR. This automatically clears the LOCK bit

XIN XOUT GNDPLL

CL2

CL1

1KΩ

1745E–ATARM–18-Apr-06

AT91M55800A

in APMC_SR and loads the PLL counter with the value programmed in the PLLCOUNT field.

Then, the PLL counter decrements at each Slow Clock cycle.

Note: Programming one in PLLCOUNT is the minimum allowed and guarantees at least 2 Slow Clock

cycles before the lock bit is set. Programming n in PLLCOUNT guarantees (n+1) the delay of

Slow Clock cycles. When the PLL Counter reaches 0, the LOCK bit in APMC_SR is set and can

cause an interrupt. Programming MUL or PLLCOUNT before the LOCK bit is set may lead to

unpredictable behavior.

If the PLL multiplication is changed while the PLL is already active, the LOCK bit in APMC_SR

is automatically cleared and the same sequence is restarted. The PLL is automatically

bypassed while the frequency is changing (while LOCK is 0). If the Main Oscillator is reacti-

vated at the same time the PLL is enabled, the LOCK bit is set only when both the Main

Oscillator and the PLL are stabilized.

12.3.3 PLL Filter

The Phase Lock Loop has a dedicated PLLRC pin which must connect with an appropriate

second order filter made up of one resistor and two capacitors. If the integrated PLL is not

used, it can remain disabled. The PLLRC pin must be grounded if the resistor and the capaci-

tors need to be saved. The following figure shows a typical filter connection.

Figure 12-5. Typical Filter Connection

In order to obtain optimal results with a 16 MHz input frequency and a 32 MHz output fre-

quency, the typical component values for the PLL filter are:

R = 287Ω - C1 = 680 nF - C2 = 68 nF

The lock time with these values is about 3.5 µs in this example.

12.3.4 Master Clock Selection

The MCK (Master Clock) can be selected through the CSS field in APMC_CGMR between the

Slow Clock, the output of the Main Oscillator or the output of the PLL.

The following CSS field definitions are forbidden and the write operations are not taken into

account by the APMC:

• deselect the Slow Clock if the Main Oscillator is disabled or its output is not stabilized

• disable the PLL without having first selected the Slow Clock or the Main Oscillator clock

• select the PLL clock and, in the same register, write disable the PLL

• select either the Main Oscillator or the PLL clocks and, in the same register, write disable

the Main Oscillator

• disable the Main Oscillator without having first selected the Slow Clock

This clock switch is performed in some Slow Clocks and PLLs or Main Oscillator clock cycles

as described in the state machine diagram below:

GNDPLL

PLLRC

1745E–ATARM–18-Apr-06

AT91M55800A

Figure 12-6. Clock Switch

12.3.5 Slow Clock Interrupt

The APMC also features the Slow Clock interrupt, allowing the user to detect when the Master

Clock is actually switched to the Slow Clock. Switching from the Slow Clock to a higher fre-

quency is generally performed safely, as the processor is running slower than the target

frequency. However, switching from a high frequency to the Slow Clock requires the high fre-

quency to be valid during the switch time. The Slow Clock interrupt permits the user to know

exactly when the switch has been achieved, thus, when the Main Oscillator or the PLL can be

disabled.

12.3.6 Prescaler

The prescaler is the last stage to provide the master clock. It permits the selected clock to be

divided by a power of 2 between 1 and 64. The default value is 1 after the reset. The prescaler

allows the microcontroller operating frequency to reach down to 512 Hz.

Precautions must be taken when defining a master clock lower than the Slow Clock, as some

peripherals (RTC and APMC) can still operate at Slow Clock frequency. In this case, access to

the peripheral registers that are updated at 32 kHz cannot be ensured.

12.3.7 Master Clock Output

The Master Clock can be output to the MCKO pad. The MCKO pad can be tri-stated to mini-

mize power consumption by setting the bit MCKODS (Master Clock Output Disable) in

APMC_CGMR (default is MCKO enabled).

Slow Clock Mode

PLL Clock Mode

Oscillator Clock Mode

5 SLCK Cycles

4 SLCK Cycles

3 PLL Clock Cycles 5 SLCK Cycles

3 SLCK Cycles

3 Oscillator Clock Cycles

5 SLCK Cycles

3 PLL Clock Cycles

4 SLCK Cycles

3 Oscillator Clock Cycles

7 SLCK Cycles

3 PLL Clock Cycles

1745E–ATARM–18-Apr-06

AT91M55800A

12.4 System Clock

The AT91M55800A has only one system clock: the ARM Core clock. It can be enabled and

disabled by writing to the System Clock Enable (APMC_SCER) and System Clock Disable

Registers (APMC_SCDR). The status of the ARM Core clock (at least for debug purposes)

can be read in the System Clock Status Register (APMC_SCSR).

The ARM Core clock is enabled after a reset and is automatically re-enabled by any enabled

interrupt.

When the ARM Core clock is disabled, the current instruction is finished before the clock is

stopped.

Note: Stopping the ARM Core does not prevent PDC transfers.

12.5 Peripheral Clocks

Each peripheral clock integrated in the AT91M55800A can be individually enabled and dis-

abled by writing to the Peripheral Clock Enable (APMC_PCER) and Peripheral Clock Disable

(APMC_PCDR) Registers. The status of the peripheral clocks can be read in the Peripheral

Clock Status Register (APMC_PCSR).

When a peripheral clock is disabled, the clock is immediately stopped. When the clock is re-

enabled, the peripheral resumes action where it left off.

In order to stop a peripheral, it is recommended that the system software waits until the periph-

eral has executed its last programmed operation before disabling the clock. This is to avoid

data corruption or erroneous behavior of the system.

The peripheral clocks are automatically disabled after a reset.

The bits that control the peripheral clocks are the same as those that control the Interrupt

Sources in the AIC.

12.6 Shut-down and Wake-up

The APMC (Advanced Power Management Controller) integrates shut-down and wake-up

logic to control an external main power supply. This logic is supplied by the Battery Backup

Power. This feature makes the Power-down mode possible.

If the SHDN pin is connected to the shut-down pin of the main power supply, the Shut-down

command (SHDALC) in APMC_PCR disables the main power. The shut-down input of the

converter is generally pulled up or down by a resistor, depending on its active level.

There are 3 ways to exit Power-down mode and restart the main power:

• An alarm programmed in the RTC occurs and the bit ALWKEN in APMC_PMR is set.

• An edge defined by the field WKEDG in APMC_PMR occurs on the pin WAKEUP.

• The user opens the Shut-down line with an external jumper or push-button.

Figure 12-7 shows a typical application using the Shut-down and Wake-up features.

1745E–ATARM–18-Apr-06

AT91M55800A

Figure 12-7. Shut-down and Wake-up Features

To accommodate the different types of main power supply available, and different signals that

can command the shut-down of this device, tri-state, level 0 and level 1 are user-definable for

the Shut-down pin. The Wake-up pin can be configured as detected on the positive or nega-

tive edge, and at high or low level. They are selected by the SHDALS and WKACKS fields in

APMC_PMR.

12.7 Alarm

If the Shut-down feature is not used, the pin SHDN can be used as an Alarm Output Signal

from the RTC Alarm. The Alarm State corresponds to Shut-down, and the Acknowledge or

Non-Alarm State corresponds to Wake-up.

The alarm control logic is the same as that for Shut-down. The SHDALC command in

APMC_PCR (defined by the field SHDALS in APMC_PMR) and the WKACKS command in

APMC_PCR (defined by the field WKACKS field in APMC_PMR) control the SHDN pin.

The alarm can be positioned by an RTC Alarm and be acknowledged by a programmable

edge on the WAKEUP pin. The Backup Reset initializes the logic in Non-Alarm State.

DC/DC ConverterPower

Supply

VDDIO

VDDCORE

GND

VDDBU

NRSTBU

GNDBU

SHDN

WAKE-UP

AT91M55800

SHD

Shut-down

Jumper

Disable

Main Start Up

Battery

Backup -

Resistor

required by

some DC/DC

Converters

1745E–ATARM–18-Apr-06

AT91M55800A

12.8 First Start-up Sequence

At initial startup, or after VDDBU has been disconnected, the battery-supplied logic must be

initialized.

The Battery Backup Reset sets the following default state:

• Shut-down Logic

Initialized in the Wake-up state (or Non Alarm)

• The Power Mode Register

Shut-down defines SHDN as level 0 (SHDALS = 1)

Wake-up defines SHDN as tri-state (WKACKS = 0)

• The Real-time Clock Configuration and Data Registers

A simple RC network can be used as a power-on reset for the battery supply.

The pin SHDN is tri-stated by default. An external resistor must hold the main power supply

shut-down pin in the inactive state. The shut-down logic can be programmed with the correct

active level of the power supply shut-down input during the first start-up sequence.

The first time the system is powered up, the SHDN pin is tri-stated because different power

supplies use different logic levels for their shut-down input signals. To minimize backup bat-

tery power consumption, there is no internal pull-up or pull-down on this signal.

If the power supply needs a logic level on its shut-down input in order to start the main power

supply then an external “Force Start Up” jumper is required to provide this level.

The jumper provides the necessary level on the SHDN to maintain the power supply when the

AT91 boots, and it can be removed until the next loss of battery power.

1745E–ATARM–18-Apr-06

AT91M55800A

12.9 APMC User Interface

Base Address:0xFFFF4000 (Code Label APMC_BASE)

Table 12-1. APMC Memory Map

Offset Register Name Access Main Reset Backup Reset

0x00 System Clock Enable Register APMC_SCER W – –

0x04 System Clock Disable Register APMC_SCDR W – –

0x08 System Clock Status Register APMC_SCSR R 0x1 –

0x0C Reserved – – – –

0x10 Peripheral Clock Enable Register APMC_PCER W – –

0x14 Peripheral Clock Disable Register APMC_PCDR W –

0x18 Peripheral Clock Status Register APMC_PCSR R 0 –

0x1C Reserved – W –

0x20 Clock Generator Mode Register APMC_CGMR R/W 0 –

0x24 Reserved – – – –

0x28 Power Control Register APMC_PCR W –

0x2C Power Mode Register APMC_PMR R/W 0x1

0x30 Status Register APMC_SR R – –

0x34 Interrupt Enable Register APMC_IER W – –

0x38 Interrupt Disable Register APMC_IDR W – –

0x3C Interrupt Mask Register APMC_IMR R 0 –

1745E–ATARM–18-Apr-06

AT91M55800A

12.9.1 APMC System Clock Enable Register

Access Type: Write-only

Offset: 0x00

• CPU: System Clock Enable Bit

0 = No effect.

1 = Enables the System Clock.

12.9.2 APMC System Clock Disable Register

Access Type: Write-only

Offset: 0x04

• CPU: System Clock Disable Bit

0 = No effect.

1 = Disables the System Clock.

31 30 29 28 27 26 25 24

––––––––

23 22 21 20 19 18 17 16

––––––––

15 14 13 12 11 10 9 8

––––––––

76543210

–––––––

CPU

31 30 29 28 27 26 25 24

––––––––

23 22 21 20 19 18 17 16

––––––––

15 14 13 12 11 10 9 8

––––––––

76543210

–––––––

CPU

1745E–ATARM–18-Apr-06

AT91M55800A

12.9.3 APMC System Clock Status Register

Access Type: Read-only

Reset Value: 0x1

Offset: 0x08

• CPU: System Clock Status Bit

0 = System Clock is disabled.

1 = System Clock is enabled.

12.9.4 APMC Peripheral Clock Enable Register

Access Type: Write-only

Offset: 0x10

• Peripheral Clock Enable (per peripheral)

0 = No effect.

1 = Enables the peripheral clock.

31 30 29 28 27 26 25 24

––––––––

23 22 21 20 19 18 17 16

––––––––

15 14 13 12 11 10 9 8

––––––––

76543210

–––––––

CPU

31 30 29 28 27 26 25 24

––––––––

23 22 21 20 19 18 17 16

–––––

DAC1 DAC0 ADC1

15 14 13 12 11 10 9 8

ADC0 PIOB PIOA –TC5 TC4 TC3 TC2

76543210

TC1 TC0 SPI US2 US1 US0 ––

1745E–ATARM–18-Apr-06

AT91M55800A

12.9.5 APMC Peripheral Clock Disable Register

Access Type: Write-only

Offset: 0x14

• Peripheral Clock Disable (per peripheral)

0 = No effect.

1 = Disables the peripheral clock.

12.9.6 APMC Peripheral Clock Status Register

Access Type: Read-only

Reset Value: 0x0

Offset: 0x18

• Peripheral Clock Status (per peripheral)

0 = The peripheral clock is disabled.

1 = The peripheral clock is enabled.

31 30 29 28 27 26 25 24

––––––––

23 22 21 20 19 18 17 16

–––––

DAC1 DAC0 ADC1

15 14 13 12 11 10 9 8

ADC0 PIOB PIOA –TC5 TC4 TC3 TC2

76543210

TC1 TC0 SPI US2 US1 US0 ––

31 30 29 28 27 26 25 24

––––––––

23 22 21 20 19 18 17 16

–––––

DAC1 DAC0 ADC1

15 14 13 12 11 10 9 8

ADC0 PIOB PIOA –TC5 TC4 TC3 TC2

76543210

TC1 TC0 SPI US2 US1 US0 ––

1745E–ATARM–18-Apr-06

AT91M55800A

12.9.7 APMC Clock Generator Mode Register

Access Type: Read/Write

Reset Value: 0x0

Offset: 0x20

• MOSCBYP: Main Oscillator Bypass (Code Label APMC_MOSC_BYP)

0 = Crystal must be connected between XIN and XOUT.

1 = External clock must be provided on XIN.

• MOSCEN: Main Oscillator Enable (Code Label APMC_MOSC_EN)

0 = Main Oscillator is disabled.

1 = Main Oscillator is enabled.

Note: When operating in Bypass Mode, the Main Oscillator must be disabled. MOSCEN and MOSCBYP bits must never be set

together.

• MCKODS: Master Clock Output Disable (Code Label APMC_MCKO_DIS)

0 = The MCKO pin is driven with the Master Clock (MCK).

1 = The MCKO pin is tri-stated.

• PRES: Prescaler Selection

• MUL: Phase Lock Loop Factor

0 = The PLL is deactivated, reducing power consumption to a minimum.

1 - 63 = The PLL output is at a higher frequency (MUL+1) than the input if the bit lock is set in APMC_SR.

31 30 29 28 27 26 25 24

–– PLLCOUNT

23 22 21 20 19 18 17 16

OSCOUNT

15 14 13 12 11 10 9 8

CSS MUL

76543210

–PRES –MCKODS MOSCEN MOSCBYP

PRES Prescaler Selected Code Label

0 0 0 None. Prescaler Output is the selected clock. APMC_PRES_NONE

0 0 1 Selected clock is divided by 2 APMC_PRES_DIV2

0 1 0 Selected clock is divided by 4 APMC_PRES_DIV4

0 1 1 Selected clock is divided by 8 APMC_PRES_DIV8

1 0 0 Selected clock is divided by 16 APMC_PRES_DIV16

1 0 1 Selected clock is divided by 32 APMC_PRES_DIV32

1 1 0 Selected clock is divided by 64 APMC_PRES_DIV64

111Reserved –

1745E–ATARM–18-Apr-06

AT91M55800A

• CSS: Clock Source Selection

• OSCOUNT: Main Oscillator Counter

Specifies the number of 32,768 Hz divided by 8 clock cycles for the main oscillator start-up timer to count before the main

oscillator is stabilized, after the oscillator is enabled. The main oscillator counter is a down-counter which is preloaded with

the OSCOUNT value when the MOSCEN bit in the Clock Generator Mode register (CGMR) is set, but only if the

OSCOUNT value is different from 0x0.

• PLLCOUNT: PLL Lock Counter

Specifies the number of 32,768 Hz clock cycles for the PLL lock timer to count before the PLL is locked, after the PLL is

started. The PLL counter is a down-counter which is preloaded with the PLLCOUNT value when the MUL field in the Clock

Generator Mode register (CGMR) is modified, but only if the MUL value is different from 0 (PLL disabled) and also the

PLLCOUNT value itself different from 0x0. PLLCOUNT must be loaded with a minimum value of 2 in order to guarantee a

time of at least one slow clock period.

CSS Clock Source Selection Code Label

0 0 Low-frequency clock provided by the RTC APMC_CSS_LF

0 1 Main oscillator Output or external clock APMC_CSS_MOSC

1 0 Phase Lock Loop Output APMC_CSS_PLL

1 1 Reserved –

1745E–ATARM–18-Apr-06

AT91M55800A

12.9.8 APMC Power Control Register

Access Type: Write-only

Offset: 0x28

• SHDALC: Shut-down or Alarm Command (Code Label APMC_SHDALC)

0 = No effect.

1 = Configures the SHDN pin as defined by the field SHDALS in APMC_PMR.

• WKACKC: Wake-up or Alarm Acknowledge Command (Code Label APMC_WKACKC)

0 = No effect.

1 = Configures the SHDN pin as defined by the field WKACKS in APMC_PMR.

Note: If both the SHDALC and WKACKS bits are set, the WKACKS command has priority.

31 30 29 28 27 26 25 24

––––––––

23 22 21 20 19 18 17 16

––––––––

15 14 13 12 11 10 9 8

––––––––

76543210

––––––

WKACKC SHDALC

1745E–ATARM–18-Apr-06

AT91M55800A

12.9.9 APMC Power Mode Register

Access Type: Read/Write

Backup Reset Value:0x1

Offset: 0x2C

• SHDALS: Shut-down or Alarm Output Selection

This field defines the state of the SHDAL pin when shut-down or alarm is requested.

• WKACKS: Wake-up or Alarm Acknowledge Output Selection

This field defines the state of the WKACKS pin when wake-up or alarm acknowledge is requested.

• ALWKEN: Alarm Wake-up Enable (Code Label APMC_WKEN)

0 = The alarm from the RTC has no wake-up effect.

1 = The alarm from the RTC commands a wake-up.

• ALSHEN: Alarm Shut-down Enable (Code Label APMC_ALSHEN)

0 = The alarm from the RTC has no shut-down effect.

1 = If ALWKEN is 0, the alarm from the RTC commands a shut-down.

31 30 29 28 27 26 25 24

––––––––

23 22 21 20 19 18 17 16

––––––––

15 14 13 12 11 10 9 8

––––––––

76543210

WKEDG ALSHEN ALWKEN WKACKS SHDALS

SHDALS Shut-down or Alarm Output Selected Code Label

0 0 Tri-stated APMC_SHDALS_OUT_TRIS

0 1 Level 0 APMC_SHDALS_OUT_LEVEL0

1 0 Level 1 APMC_SHDALS_OUT_LEVEL1

11Reserved –

WKACKS

Wake-up or Alarm Acknowledge Output

Selected Code Label

0 0 Tri-stated APMC_WKACKS_OUT_TRIS

0 1 Level 0 APMC_WKACKS_OUT_LEVEL_0

1 0 Level 1 APMC_WKACKS_OUT_LEVEL_1

1 1 Reserved –

1745E–ATARM–18-Apr-06

AT91M55800A

• WKEDG: Wake-up Input Edge Selection

This field defines the edge to detect on the Wake-up pin (WAKEUP) to provoke a wake-up.

WKEDG Wake-up Input Edge Selection Code Label

0 0 None. No edge is detected on wake-up. APMC_WKEDG_NONE

0 1 Positive edge APMC_WKEDG_POS_EDG

1 0 Negative edge APMC_WKEDG_NEG_EDG

1 1 Both edges APMC_WKEDG_BOTH_EDG

1745E–ATARM–18-Apr-06

AT91M55800A

12.9.10 APMC Status Register

Access Type: Read-only

Offset: 0x30

• MOSCS: Main Oscillator Status (Code Label APMC_MOSCS)

0 = Main Oscillator output signal is not stabilized or the Main Oscillator is disabled.

1 = The Main Oscillator is enabled and its output is stabilized. Actually, this bit indicates that the Main Oscillator counter

reached 0.

• LOCK: PLL Lock Status (Code Label APMC_PLL_LOCK)

0 = PLL output signal or main oscillator output signal is not stabilized, or the main oscillator is disabled.

1 = Main Oscillator is enabled and its output is stabilized and the PLL output signal is stabilized. Actually, this bit is set

when the PLL Lock Counter reaches 0.

12.9.11 APMC Interrupt Enable Register

Access Type: Write-only

Offset: 0x34

• MOSCS: Main Oscillator Interrupt Enable (Code Label APMC_MOSCS)

0 = No effect.

1 = Enables the Main Oscillator Stabilized Interrupt.

• LOCK: PLL Lock Interrupt Enable (Code Label APMC_PLL_LOCK)

0 = No effect.

1 = Enables the PLL Lock Interrupt.

31 30 29 28 27 26 25 24

––––––––

23 22 21 20 19 18 17 16

––––––––

15 14 13 12 11 10 9 8

––––––––

76543210

––––––

LOCK MOSCS

31 30 29 28 27 26 25 24

––––––––

23 22 21 20 19 18 17 16

––––––––

15 14 13 12 11 10 9 8

––––––––

76543210

––––––

LOCK MOSCS

1745E–ATARM–18-Apr-06

AT91M55800A

12.9.12 APMC Interrupt Disable Register

Access Type: Write-only

Offset: 0x38

• MOSCS: Main Oscillator Interrupt Disable (Code Label APMC_MOSCS)

0 = No effect.

1 = Disables the Main Oscillator Stabilized Interrupt.

• LOCK: PLL Lock Interrupt Disable (Code Label APMC_PLL_LOCK)

0 = No effect.

1 = Disables the PLL Lock Interrupt.

12.9.13 APMC Interrupt Mask Register

Access Type: Read-only

Reset Value: 0x0

Offset: 0x3C

• MOSCS: Main Oscillator Interrupt Mask (Code Label APMC_MOSCS)

0 = The Main Oscillator Interrupt is disabled.

1 = The Main Oscillator Interrupt is enabled.

• LOCK: PLL Lock Interrupt Mask (Code Label APMC_PLL_LOCK)

0 = The PLL Lock Interrupt is disabled.

1 = The PLL Lock Interrupt is enabled.

31 30 29 28 27 26 25 24

––––––––

23 22 21 20 19 18 17 16

––––––––

15 14 13 12 11 10 9 8

––––––––

76543210

––––––

LOCK MOSCS

31 30 29 28 27 26 25 24

––––––––

23 22 21 20 19 18 17 16

––––––––

15 14 13 12 11 10 9 8

––––––––

76543210

––––––

LOCK MOSCS

1745E–ATARM–18-Apr-06

AT91M55800A

13. RTC: Real-time Clock