91912HKPC 20080324-S00002 No. A2123-1/7
http://onsemi.com
Semiconductor Components Industries, LLC, 2013
July, 2013
LC79430KNE
Overview
The LC79430KNE is a large-scale dot matrix LCD common driver LSI. The LC79430KNE contains an 80-bit
bidirectional shift register and is equipped with a 4-level LCD driver. The input/output pins for cascade connection can
be used to further increase the IC’s number of bits. The LC79430KNE can be used in conjunction with segment driver
LC79401KNE (QIP100E) to drive a wide-screen LCD panel.
Features
• On-chip LC D drive circuit (80 bi t s)
• Display duty selection ranging from 1/64 to 1/256
• On-chip input/output pins support a further increases in bit number
• Supports externally supplied bias voltage
• On-chip 80 -b i t bidirect i o nal shi ft regi ster (supports 40-bi t × 2 di vision)
• Supports single mode (80-bit sh ift register) and dual mode (40- bit × 2 shift register) applications
(1) O1 → O80
(2) O80 → O1
(3) O1 → O40 and O41 → O80
(4) O80 → O41 and O40 → O1
All four of the shift direction selection listed above all supported
• Operating power supply voltag e /operating temperature include
VDD (Logic section) : 2.7 to 5.5V/-20 to +85°C
VDD-VEE (LCD section) : 12 to 32V/-20 to +85°C
• CMOS process
• 100-pin flat plastic package (QIP100E)
Ordering number : ENA2123
CMOS LSI
Dot-Matrix LCD Drivers
Single mode
Dual mode
LC79430KNE
No. A2123-2/7
Specifications
Absolute Maximum Ratings at Ta = 25±2°C, VSS = 0V
Parameter Symbol Conditions Ratings unit
Maximum supply voltage (Logic) VDD max -0.3 to +7.0 V
Maximum supply voltage (LCD) VDD-VEE max *1 0 to 35 V
Maximum input voltage VI max -0.3 to VDD+0.3 V
Storage temperature Tstg -40 to +125 °C
Note *1 The following relations between elemen ts should be maintained: VDD≥V1>V2>V5>VEE, VDD-V2≤7V,
V5-VEE≤7V
Allowable Operating Ranges at Ta = -20 to +85°C, VSS = 0V
Parameter Symbol Conditions min typ max unit
Supply voltage (Logic) VDD 2.7 5.5 V
Supply voltage (LCD) VDD-VEE *2, 3 12 32 V
Input high level voltage VIH DIO1, DIO80, CP, M, DMIN, MODE,
RS/LS, DISPOFF 0.8VDD V
Input low level voltage VIL DIO1, DIO80, CP, M, DMIN, MODE,
RS/LS, DISPOFF 0.2VDD V
CP Shift clock fCP CP 1 MHz
CP pulse width tWC CP 63 ns
Setup time tSETUP DIO1 → CP, DIO80 → CP,
DMIN → CP
100 ns
Hold time tHOLD DIO1 → CP, DIO80 → CP,
DMIN → CP
100 ns
CP rise time tR CP 50 ns
CP fall time tF CP 50 ns
Note *2 The following relations between elemen ts should be maintained: VDD≥V1>V2>V5>VEE, VDD-V2≤7V,
V5-VEE≤7V
*3 When the power supply is turned on, power to the LCD driver is turned on after or simu ltaneously with the
turning on of the logic section’s power supply. When the power supply is turned off, th e logic power supply is
turned off after or at the same time the LCD driver power supply is turned off.
Electrical Characteristics at Ta = 25±2°C, VDD = 2.7 to 5.5V
Parameter Symbol Conditions min typ max unit
Input high level current IIH V
IN=VDD, VDD=5.5V, DIO1, DIO80,
CP, M, DMIN, MODE, RS/LS, DISPOFF 1μA
Input low level current IIL V
IN=VSS, VDD=5.5V, DIO1, DIO80,
CP, M, DMIN, MODE, RS/LS, DISPOFF -1 μA
Output high level voltage
VOH I
OH=-0.4mA, DIO1, DIO80 VDD-0.4 V
Output low level voltage VOL I
OL=0.4mA, DIO1, DIO80 0.4 V
RON(1) VDD-VEE=30V, ⎜VDE-VO⎜=0.5V
VDD=4.5V, O1 to O80 *4 1.0 kΩ
Driver on resistance
RON(2) VDD-VEE=20V, ⎜VDE-VO⎜=0.5V
VDD=4.5V, O1 to O80 *4 1.0 kΩ
Consumable current drain (1) ISS V
DD-VEE=30V, CP=14kHz
no-load, VDD=5.5V ; VSS 100 μA
Consumable current drain (2) IEE V
DD-VEE=30V, CP=14kHz
no-load, VDD=5.5V ; VEE 100 μA
Input capacitance CI f=1MHz ; CP 8 pF
Note *4 VDE = V1 or V2 or V5 or VEE, V1 = VDD, V2 = 16/17 (VDD-VEE), V5 = 1/17 (VDD-VEE)
Switching Characteristics at Ta = 25±2°C, VSS = 0V, VDD = 2.7 to 5.5V
Parameter Symbol Conditions min typ max unit
tPLH CL=15pF ; CP → DIO1, CP → DIO80 250 ns Output delay time
tPHL CL=15pF ; CP → DIO1, CP → DIO80 250 ns
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
LC79430KNE
No. A2123-3/7
Package Dimensions
unit:mm (typ)
3151A
Pin Assignment
Top view
SANYO : QIP100E(14X20)
20.0
23.2
14.0
17.2
0.15
0.8
(2.7)
3.0max
0.1
0.3
0.65
(0.58)
130
80 51
31
50
100
81
LC79430KNE
O50
O49
O48
O47
O46
O45
O44
O43
O42
O41
O40
O39
O38
O37
O36
O35
O34
O33
O32
O31
O1
O2
O3
O4
O5
O6
O7
O8
O9
O10
O11
O12
O13
O14
O15
O16
O17
O18
O19
O20
O21
O22
O23
O24
O25
O26
O27
O28
O29
O30
1 2 3 45 6 7 8 9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
49
47
48
46
45
44
42
43
41
40
39
37
38
36
35
34
32
33
31
50
O80
O79
O78
O77
O76
O75
O74
O73
O72
O71
O70
O69
O68
O67
O66
O65
O64
O61
O60
O59
O58
O57
O56
O55
O54
O53
O52
O51
O62
O63
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
82
84
83
85
86
87
89
88
90
91
92
94
93
95
96
97
99
98
100
81
NC
DIO80
NC
VEE
V5
V2
V1
NC
DISPOFF
VDD
RS/LS
VSS
NC
M
MODE
CP
DMIN
DIO1
NC
NC
LC79430KNE
No. A2123-4/7
Equivalent Circuit Block Diagram
4 Level LCD Drive Circuit
(80 bits)
Level Shifter (80bits)
Bidirectional
Shift Register
(80 bits)
I/O I/O
O1 O2 O3 O79 O80
VDD
VSS
V1
V2
V5
VEE
M
DISPOFF
DIO1
CP
DIO80
RS/LS
MODE
DMIN
LC79430KNE
No. A2123-5/7
Pin Function
Pin No Symbol I/O Function
90 VDD
92 VSS
84 VEE
Supply VDD-VSS : Logic power supply
VDD-VEE : LCD drive circuit power supply
87 V1
86 V2
85 V5
Supply
LCD drive level power supply
V1, VEE : Selected level
V2, V5 : Unselected level
96 CP I Bidirectional shift register shift clock (falling edge trigger)
98
82
91
95
97
DIO1
DIO80
RS/LS
MODE
DMIN
I/O
I/O
I
I
I
MODE RS/LS Data Transfer Direction DIO1 DIO80 DMIN
L (Shift right) O1 → O80 IN OUT *
L
(Single) H (Shift left) O80 → O1 OUT IN *
O1 → O40
L (Shift right)
O41 → O80
IN OUT IN
O80 → O41
H
(Dual)
H (Shift left)
O40 → O1
OUT IN IN
* Don’t care (May be set to either “H” or “L”)
94 M I LCD drive output alternation signal
89 DISPOFF I O1 to O80 output controlling input pins.
1
80
O1
O80
O
LCD drive outputs
The output levels are determined by the combination of the output the data,
The M signal, and the DISPOFF pin as shown in the table.
M Data
DISPOFF Output
L L H V2
L H H VEE
H L H V5
H H H V1
* * L V1
* Don’t care (May be set to either “H” or “L”)
81
83
88
93
99
100
NC - Must be left open.
LC79430KNE
No. A2123-6/7
Application Example (LC79401KNE/LC79430KNE)
R/L
Seg318
Seg319
Seg320
Seg1
DIO1 DIO80
VDD
VSS
VEE
Seg2
Seg3
Com240
Com239
Com238
Com3
LCD PANEL
240×320
1/240 duty
Power supply circuit
Case of 1/n bias
Com2
Com1
LC79430KNE
#1
M
RS/LS
CP
MODE
DMIN
V1
V2
V5
DISPOFF
DI1 to DI4
O1 to O80
O1 to O80 O1 to O80
O1 to O80O1 to O80
LC79401KNE
#4
LC79401KNE
#2
LC79401KNE
#1
M
LOAD
CP
V1
V3
V4
VEE
VSS
VDD
CDI
VEE
VSS
VDD
CDI
VEE
VSS
VDD
CDI CDOCDOCDO
R/L
DISPOFF
DI1 to DI4
M
LOAD
CP
V1
V3
V4
Controller
FLM
M
LOAD
GND
VDD
VEE
R
R
CP
DI1 to DI4
DISPOFF
DISPOFF
DIO1 DIO80
VDD
VSS
VEE
LC79430KNE
#3
M
RS/LS
CP
MODE
DMIN
V1
V2
V5
DISPOFF
R/L
DISPOFF
DI1 to DI4
M
LOAD
CP
V1
V3
V4
+
-
+
-
R
(n-4)R
R
V1
V2
V3
V4
V5
+
-
+
-
LC79430KNE
No. A2123-7/7
Switching Characteristics Diagram
PS
tWC
CP
DIO1
(DIO80)
(DMIN)
DIO80
(DIO1)
tR tF
tSETUP
tHOLD
tPLH, tPHL
0.2VDD
0.8VDD
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