User's Guide SLVU962 - November 2013 TPS54388EVM User's Guide The TPS54388-Q1 DC-DC converter is designed to provide up to a 3-A output from an input voltage source of 2.95 V to 6 V. Table 1 lists the ratings for the input-voltage and output-current range of the evaluation module (EVM). This evaluation module is designed to demonstrate the small printed-circuitboard (PCB) areas that can be achieved when designing with the TPS54388-Q1 regulator. The switching frequency is externally set at a nominal 2000 kHz. The high-side and low-side MOSFETs are incorporated inside the TPS54388-Q1 device to achieve high efficiencies and to maintain a low junction temperature at high output currents. The compensation components are external to the integrated circuit (IC) and have been selected to optimize the transient performance of the device. An external divider allows for an adjustable output voltage. Additionally, the TPS54388-Q1 device provides adjustable slow-start and undervoltage lockout inputs. The absolute-maximum input voltage is 7 V for the TPS54388EVM. Table 1. Input Voltage and Output Current Summary EVM Input Voltage Range Output current Range TPS54388EVM VIN = 3 V to 6 V 0 A to 3 A 1 2 3 4 Contents Performance-Specification Summary .................................................................................... 2 Test Setup and Results .................................................................................................... 3 Board Layout ................................................................................................................ 8 Schematic and Bill of Materials .......................................................................................... 11 1 TPS54388EVM Efficiency.................................................................................................. 2 TPS54388EVM Load Regulation ......................................................................................... 4 3 TPS54388EVM Line Regulation .......................................................................................... 5 4 TPS54388EVM Load Transient ........................................................................................... 5 5 TPS54388EVM Loop-Response Measurement ......................................................................... 6 6 TPS54388EVM Output Ripple ............................................................................................ TPS54388EVM Startup Relative to VIN .................................................................................. TPS54388EVM Startup Relative to Enable.............................................................................. TPS54388EVM Top-Side Layout ......................................................................................... TPS54388EVM Bottom-Side Layout ..................................................................................... TPS54388EVM Top-Side Assembly ...................................................................................... TPS54388EVM Bottom-Side Assembly ................................................................................ TPS54388EVM Schematic ............................................................................................... 6 List of Figures 7 8 9 10 11 12 13 4 7 7 8 9 9 10 11 List of Tables 1 Input Voltage and Output Current Summary ............................................................................ 1 2 TPS54388EVM Performance-Specification Summary ................................................................. 2 3 Common Output-Voltage Options ........................................................................................ 2 4 EVM Connectors and Test Points ........................................................................................ 3 5 TPS54388EVM Bill of Materials ......................................................................................... 12 SLVU962 - November 2013 Submit Documentation Feedback TPS54388EVM User's Guide Copyright (c) 2013, Texas Instruments Incorporated 1 Performance-Specification Summary 1 www.ti.com Performance-Specification Summary Table 2 lists a summary of the TPS54388EVM performance specifications. Specifications are given for an input voltage of VIN = 5 V and an output voltage of 1.2 V, unless otherwise specified. The ambient temperature is 25C for all measurements, unless otherwise noted. Table 2. TPS54388EVM Performance-Specification Summary SPECIFICATION TEST CONDITION VIN operating voltage range MIN TYP MAX 3 5 6 V VIN start voltage 2.84 V VIN stop voltage 2.68 V 1.2 V Output voltage set point Output current range VIN = 3 V to 6 V Line regulation IO = 1 A, VIN = 3 V to 6 V Load regulation VIN = 3.3 V, IO = 0 A to 3 A IO = 0.75 A to 2.25 A Load transient response IO = 2.25 A to 0.75 A 0 3 A 0.1% 0.15% Voltage change -30 Recovery time 70 s Voltage change 30 mV Recovery time 80 s mV kHz Loop bandwidth VIN = 5 V, IO = 2.25 A 88 Phase margin VIN = 5 V, IO = 2.25 A 42 Output ripple voltage IO = 3 A 10 mVpp Output rise time Operating frequency Maximum efficiency 1.1 UNIT VIN = 3.3V, IO = 1.6A 4 ms 2000 kHz 86% Modifications This EVM is designed to provide access to the features of the TPS54388-Q1 device. Some modifications can be made to the module. 1.1.1 Output Voltage Set-Point The voltage dividers R5 and R7 set the output voltage. To change the output voltage of the EVM, changeing the value of resistor R5 is necessary. Changing the value of R5 changes the output voltage above 0.8 V. The value of R5 for a specific output voltage is calculated using Equation 1. V - VREF R5 = 80.6 kW OUT VREF (1) Table 3 lists the R5 values for some common output voltages. Note that VIN must be in a range so that the minimum on-time is greater than 75 ns, and the maximum duty cycle is less than 92%. The values given in Table 3 are standard values and are not the exact value calculated using Equation 1. Table 3. Common Output-Voltage Options Output Voltage (V) 2 R5 Value (k) 1 20 1.2 40.2 1.5 71.5 1.8 100 2.5 174 3.3 249 TPS54388EVM User's Guide SLVU962 - November 2013 Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated Test Setup and Results www.ti.com 1.1.2 Slow-Start Time The slow-start time is adjusted by changing the value of C15. Equation 2 calculates the required value of C15 for a desired slow-start time. C15 (nF ) = TSS (ms ) ISS (A) VREF (V) where * ISS = 2 A (2) C15 is set to 0.01 F on the EVM for a default slow-start time of 4 ms. 1.1.3 Adjustable Undervoltage Lockout The undervoltage lockout (UVLO) is adjusted externally using R3 and R4. The EVM is set for a start voltage of 2.84 V and a stop voltage of 2.68 V using R3 = 25.5 k and R2 = 20 k. Use Equation 3 and Equation 4 along with notes included in the TPS54388-Q1 data sheet (SLVSAF1) to calculate required resistor values for different start and stop voltages. 0.944 VSTART - VSTOP R3 = 1.7110-6 (3) 1.18 R3 R4 = VSTOP - 1.18 + R3 3.5 10-6 (4) 2 Test Setup and Results This section describes how to properly connect, set up, and use the TPS54388EVM evaluation module. Test results typical of this evaluation module are also included. This section covers efficiency, output voltage regulation, load transients, loop response, output ripple, and startup. 2.1 Input and Output Connections The TPS54388EVM is provided with input and output connectors and test points as shown in Table 4. A power supply capable supplying 3 A must be connected to J1 through a pair of 20-AWG wires. The load must be connected to J2 through a pair of 20-AWG wires. The maximum load-current capability must be at least 3 A to use the full capability of this EVM. Wire lengths must be minimized to reduce losses in the wires. Test-point TP1 provides a place to monitor the VIN input voltages with TP2 providing a convenient ground reference. TP3 monitors the output voltage with TP4 as the ground reference. Table 4. EVM Connectors and Test Points Reference Designator Function J1 VIN (see Table 1 for VIN range) J2 VOUT, 1.2 V at 2 A maximum JP1 2-pin header for enable. Connect EN to ground to disable, open to enable TP1 VIN test point at VIN connector TP2 GND test point at VIN TP3 VOUT test point at VOUT connector TP4 GND test point at VOUT TP5 Test point between voltage divider network and output. Used for loop response measurements TP6 COMP test point SLVU962 - November 2013 Submit Documentation Feedback TPS54388EVM User's Guide Copyright (c) 2013, Texas Instruments Incorporated 3 Test Setup and Results 2.2 www.ti.com Efficiency Figure 1 shows the efficiency for the TPS54388EVM at two different input voltages and at an ambient temperature of 25C. 100 90 80 Efficiency - % 70 60 50 40 30 20 Vin = 3.3 V Vin = 5 V 10 0 0.0 0.5 1.0 1.5 2.0 2.5 Output Current - A 3.0 C001 Figure 1. TPS54388EVM Efficiency 2.3 Output-Voltage Load Regulation Figure 2 shows the load regulation for the TPS54388EVM at two different input voltages. Output Voltage Deviation - % 0.05 0.00 0.05 0.10 0.15 0.20 Vin = 3.3 V Vin = 5 V 0.25 0.0 0.5 1.0 1.5 Output Current - A 2.0 C003 Figure 2. TPS54388EVM Load Regulation 4 TPS54388EVM User's Guide SLVU962 - November 2013 Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated Test Setup and Results www.ti.com 2.4 Output-Voltage Line Regulation Figure 3 shows the line regulation for the TPS54388EVM at room temperature and ILOAD = 1.5 A. Output Voltage Deviation - % 0.06 0.04 0.02 0.00 0.02 0.04 0.06 0.08 0.10 3.00 3.50 4.00 4.50 5.00 5.50 Input Voltage - V 6.00 C002 Figure 3. TPS54388EVM Line Regulation 2.5 Load Transients Figure 4 shows the TPS54388EVM response to a load step. The current step is from 25% to 75% of maximum rated load at 5 V input. Figure 4. TPS54388EVM Load Transient SLVU962 - November 2013 Submit Documentation Feedback TPS54388EVM User's Guide Copyright (c) 2013, Texas Instruments Incorporated 5 Test Setup and Results 2.6 www.ti.com Loop Response Figure 5 shows the TPS54388EVM loop-response characteristics. Gain and phase plots are shown for a VIN voltage of 5 V and a load current of 2.25 A. Figure 5. TPS54388EVM Loop-Response Measurement 2.7 Output-Voltage Ripple Figure 6 shows the TPS54388EVM output-voltage ripple. The output current is the rated full-load current of 3 A and VIN = 5 V. The ripple voltage is measured directly across the output capacitors. Figure 6. TPS54388EVM Output Ripple 6 TPS54388EVM User's Guide SLVU962 - November 2013 Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated Test Setup and Results www.ti.com 2.8 Power Up Figure 7 and Figure 8 show the start-up waveforms for the TPS54388EVM. In Figure 8, the output voltage ramps up as soon as the input voltage reaches the UVLO threshold as set by the R3 and R4 resistor divider network. In Figure 9, the input voltage is applied initially and the output is inhibited by using a jumper at JP1 to tie EN to GND. When the jumper is removed, EN is released. When the EN voltage reaches the enable-threshold voltage, the start-up sequence begins, and the output voltage ramps up to the externally set value of 1.2 V. The input voltage for these plots is 5 V and the load is 1 . Figure 7. TPS54388EVM Startup Relative to VIN Figure 8. TPS54388EVM Startup Relative to Enable SLVU962 - November 2013 Submit Documentation Feedback TPS54388EVM User's Guide Copyright (c) 2013, Texas Instruments Incorporated 7 Board Layout 3 www.ti.com Board Layout This section provides a description of TPS54388EVM board layout and layer illustrations. 3.1 Layout Figure 9, Figure 10, Figure 11, and Figure 12 show the board layout of the TPS54388EVM. The top-side layer of the EVM contains the main traces for VIN, VOUT, and VPH. Also on the top-side layer are connections for the remaining pins of the TPS54388-Q1 device and a large area filled with ground. The bottom-side layer contains some components and another large area filled with ground. The top-side ground areas are connected to the bottom ground plane with multiple vias placed around the board including four vias directly under the TPS54388-Q1 device to provide a thermal path from the top-side ground area to the bottom-side ground plane. The input decoupling capacitors (C2, C3, C4, and C5) and bootstrap capacitor (C11) are all located as close to the IC as possible. In addition, the voltage set-point resistor divider components are also located close to the IC on the bottom of the board. For the TPS54388-Q1 device, an additional input bulkcapacitor can be required depending on the EVM connection to the input supply. Figure 9. TPS54388EVM Top-Side Layout 8 TPS54388EVM User's Guide SLVU962 - November 2013 Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated Board Layout www.ti.com Figure 10. TPS54388EVM Bottom-Side Layout Figure 11. TPS54388EVM Top-Side Assembly SLVU962 - November 2013 Submit Documentation Feedback TPS54388EVM User's Guide Copyright (c) 2013, Texas Instruments Incorporated 9 Board Layout www.ti.com Figure 12. TPS54388EVM Bottom-Side Assembly 10 TPS54388EVM User's Guide SLVU962 - November 2013 Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated Schematic and Bill of Materials www.ti.com 4 Schematic and Bill of Materials 4.1 Schematic Figure 13 is the schematic of the TPS54388EVM. Figure 13. TPS54388EVM Schematic SLVU962 - November 2013 Submit Documentation Feedback TPS54388EVM User's Guide Copyright (c) 2013, Texas Instruments Incorporated 11 Schematic and Bill of Materials 4.2 www.ti.com Bill of Materials Table 5 lists the bill of materials for the TPS54388EVM. Table 5. TPS54388EVM Bill of Materials Count 12 RefDes Value Description Size Part Number MFR 1 C1 2.2 nF Capacitor, Ceramic, 16 V, X7R, 10% 603 GRM188R71C222KA01D-ND Murata 0 C2 Open Capacitor, Ceramic Multi sizes Engineering Only Standard 2 C3, C4 10 F Capacitor, Ceramic, 10 V, X5R, 20% 1206 C3216X5R1A106M160AB TDK 2 C5, C11 0.1 F Capacitor, Ceramic, 25 V, X5R, 10% 603 C1608X5R1H104K080AA TDK 5 C6, C7, C8, C9, C10 22 F Capacitor, Ceramic, 10 V, X5R, 20% 1210 C3225X5R1A226M230AA TDK 0 C12 47 pF Capacitor, Ceramic, 50 V, C0G, 5% 603 C1608C0G1H470J080AA TDK 1 C13 10 pF Capacitor, Ceramic, 50 V, C0G 603 C1608C0G1H100D080AA TDK 1 C14 1800 pF Capacitor, Ceramic, 50 V, X7R, 10% 603 GRM188R71H182KA01D Murata 1 C15 0.01 F Capacitor, Ceramic, 16 V, X7R, 15% 603 GRM188R71C103KA01D Murata 2 J1, J2 ED555/2DS Terminal Block, 2-pin, 6-A, 3,5 mm 0.27 x 0.25 inch ED555/2DS OST 1 JP1 PEC02SAAN Header, Male 2-pin, 100-mil spacing 0.100 inch x 2 PEC36SAAN Sullins 1 L1 0.75 H Inductor, SMT, 10 A, 7.5 m 0.255 x 0.270 inch FDV0630-R75M TOKO 1 R1 4.7 Resistor, Chip, 1/16 W, 1% 603 CRCW06034R70FNEA Vishay 1 R2 51.1 Resistor, Chip, 1/16 W, 1% 603 3-1879335-7 TE 1 R3 25.5k Resistor, Chip, 1/16 W, 1% 603 9-1879337-8 TE 1 R4 20.0k Resistor, Chip, 1/16 W, 1% 603 8-1879337-8 TE 1 R5 40.2k Resistor, Chip, 1/16 W, 1% 603 1-1879338-8 TE 1 R6 100k Resistor, Chip, 1/16 W, 1% 603 5-1879338-6 TE 1 R7 80.6k Resistor, Chip, 1/16 W, 1% 603 4-1879338-7 TE 1 R8 18.0k Resistor, Chip, 1/16 W, 1% 603 8-1879337-4 TE 1 R9 82k Resistor, Chip, 1/16 W, 1% 603 1623002-2 TE 4 TP1, TP2, TP5, TP6 5000 Test Point, Red, Thru Hole Color Keyed 0.100 x 0.100 inch 5000 Keystone 2 TP3, TP4 5001 Test Point, Black, Thru Hole Color Keyed 0.100 x 0.100 inch 5001 Keystone 1 -- -- Shunt, 100-mil, Black 0.1 929950-00 3M 1 U1 TPS54388-Q1 IC, DC-DC Converter, 2.95 V to 6 V, 3 A QFN-16 TPS54388QRTERQ1 TI 1 -- -- PCB, 2 inch x 1.5 inch x 0.062 inch -- HVL041-003 Any TPS54388EVM User's Guide SLVU962 - November 2013 Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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