DS055 (v2.1 April 3, 2007 www.xilinx.com 1
Product Specification 1-800-255-7778
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Features
6 ns pin-to-pin logic delays
System frequency up to 208 MHz
288 macrocells with 6,400 usable gates
Available in small footprint packages
- 144-pin TQFP (117 user I/O pins)
- 208-pin PQFP (168 user I/O pins)
- 256-pin BGA (192 user I/O pins)
- 256-pin FBGA (192 user I/O pins)
- 280-pin CSP (192 user I/O pins)
- Pb-free available for all packages
Optimized for high-performance 3.3V systems
- Low power operation
- 5V tolerant I/O pins accept 5V, 3.3V, and 2.5V
signals
- 3.3V or 2.5V output capability
- Advanced 0.35 micron feature size CMOS
Fast FLASH™ technology
Advanced system features
- In-system programmable
- Superior pin-locking and routability with
Fast CONNECT™ II switch matrix
- Extra wide 54-input Function Blocks
- Up to 90 product-terms per macrocell with
individual product-term allocation
- Local clock inversion with three global and one
product-term clocks
- Individual output enable per output pin with local
inversion
- Input hysteresis on all user and boundary-scan pin
inputs
- Bus-hold circuitry on all user pin inputs
- Full IEEE Standard 1149.1 boundary-scan (JTAG)
Fast concurrent programming
Slew rate control on individual outputs
Enhanced data security features
Excellent quality and reliability
- Endurance exceeding 10,000 program/erase
cycles
- 20 year data retention
- ESD protection exceeding 2,000V
Pin-compatible with 5V-core XC95288 device in the
208-pin HQFP package
WARNING: Programming temperature range of
TA = 0° C to +70° C
Description
The XC95288XL is a 3.3V CPLD targeted for high-perfor-
mance, low-voltage applications in leading-edge communi-
cations and computing systems. It is comprised of 16
54V18 Function Blocks, providing 6,400 usable gates with
propagation delays of 6 ns. See Figure 2 for architecture
overview.
Power Estimation
Power dissipation in CPLDs can vary substantially depend-
ing on the system frequency, design application and output
loading. To help reduce power dissipation, each macrocell
in a XC9500XL device may be configured for low-power
mode (from the default high-performance mode). In addi-
tion, unused product-terms and macrocells are automati-
cally deactivated by the software to further conserve power.
For a general estimate of ICC, the following equation may be
used:
ICC(mA) = MCHS(0.175*PTHS + 0.345) + MCLP(0.052*PTLP
+ 0.272) + 0.04 * MCTOG(MCHS +MCLP)* f
where:
MCHS = # macrocells in high-speed configuration
PTHS = average number of high-speed product terms
per macrocell
MCLP = # macrocells in low power configuration
PTLP = average number of low power product terms per
macrocell
f = maximum clock frequency
MCTOG = average % of flip-flops toggling per clock
(~12%)
This calculation was derived from laboratory measurements
of an XC9500XL part filled with 16-bit counters and allowing
a single output (the LSB) to be enabled. The actual ICC
value varies with the design application and should be veri-
fied during normal system operation. Figure 1 shows the
above estimation in a graphical form. For a more detailed
discussion of power consumption in this device, see Xilinx
0
XC95288XL High Performance
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XC95288XL High Performance CPLD
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application note XAPP114, “Understanding XC9500XL
CPLD Power.”
Figure 1: Typical ICC vs. Frequency for XC95288XL
Clock Frequency (MHz)
Typical ICC (mA)
100 200 250
DS055_01_121501
200
250
300
350
400
450
500
550
50
50 150
150
100
0
94 MHz
HighP
e
rformanc
e
208 MHz
LowPo
wer
XC95288XL High Performance CPLD
DS055 (v2.1 April 3, 2007 www.xilinx.com 3
Product Specification 1-800-255-7778
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Figure 2: XC95288XL Architecture
Function Block outputs (indicated by the bold line) drive the I/O Blocks directly.
In-System Programming Controller
JTAG
Controller
I/O
Blocks
Function
Block 1
Macrocells
1 to 18
Macrocells
1 to 18
JTAG Port
3
54
I/O/GTS
I/O/GSR
I/O/GCK
I/O
I/O
I/O
I/O
4
1
I/O
I/O
I/O
I/O
3
DS055_02_101300
1
Function
Block 2
54
18
18
Function
Block 3
Macrocells
1 to 18
Macrocells
1 to 18
54
Function
Block 16
54
18
18
Function
Block 4
Macrocells
1 to 18
54
18
Fast CONNECT II Switch Matrix
XC95288XL High Performance CPLD
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1-800-255-7778 Product Specification
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Absolute Maximum Ratings(2)
Recommended Operation Conditions
Quality and Reliability Characteristics
DC Characteristic Over Recommended Operating Conditions
Symbol Description Value Units
VCC Supply voltage relative to GND –0.5 to 4.0 V
VIN Input voltage relative to GND(1) 0.5 to 5.5 V
VTS Voltage applied to 3-state output(1) 0.5 to 5.5 V
TSTG Storage temperature (ambient)(3) –65 to +150 oC
TJJunction temperature +150 oC
Notes:
1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the
device pins may undershoot to –2.0V or overshoot to +7.0V, provided this over- or undershoot lasts less than 10 ns and with the
forcing current being limited to 200 mA. External I/O voltage may not exceed VCCINT by 4.0V.
2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
3. For soldering guidelines and thermal considerations, see the Device Packaging information on the Xilinx website. For Pb-free
packages, see XAPP427.
Symbol Parameter Min Max Units
VCCINT Supply voltage for internal logic
and input buffers
Commercial TA = 0oC to 70oC3.0 3.6 V
Industrial TA = –40oC to +85oC3.0 3.6 V
VCCIO Supply voltage for output drivers for 3.3V operation 3.0 3.6 V
Supply voltage for output drivers for 2.5V operation 2.3 2.7 V
VIL Low-level input voltage 0 0.80 V
VIH High-level input voltage 2.0 5.5 V
VOOutput voltage 0 VCCIO V
Symbol Parameter Min Max Units
TDR Data Retention 20 - Years
NPE Program/Erase Cycles (Endurance) 10,000 - Cycles
VESD Electrostatic Discharge (ESD) 2,000 - Volts
Symbol Parameter Test Conditions Min Max Units
VOH Output high voltage for 3.3V outputs IOH = –4.0 mA 2.4 - V
Output high voltage for 2.5V outputs IOH = –500 μA90% V
CCIO -V
VOL Output low voltage for 3.3V outputs IOL = 8.0 mA - 0.4 V
Output low voltage for 2.5V outputs IOL = 500 μA-0.4V
IIL Input leakage current VCC = Max; VIN = GND or VCC 10μA
IIH I/O high-Z leakage current VCC = Max; VIN = GND or VCC 10μA
IIH I/O high-Z leakage current VCC = Max; VCCIO = Max;
VIN = GND or 3.6V
10μA
VCC Min < VIN < 5.5V - ±50 μA
CIN I/O capacitance VIN = GND; f = 1.0 MHz - 10 pF
ICC Operating supply current
(low power mode, active)
VIN = GND, No load; f = 1.0 MHz 85 (Typical) mA
XC95288XL High Performance CPLD
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Product Specification 1-800-255-7778
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AC Characteristics
Symbol Parameter
XC95288XL-6 XC95288XL-7 XC95288XL-10
UnitsMin Max Min Max Min Max
TPD I/O to output valid - 6.0 - 7.5 - 10.0 ns
TSU I/O setup time before GCK 4.0 - 4.8 - 6.5 - ns
THI/O hold time after GCK 0 - 0 - 0 - ns
TCO GCK to output valid - 3.8 - 4.5 - 5.8 ns
fSYSTEM Multiple FB internal operating frequency - 208.3 - 125.0 - 100.0 MHz
TPSU I/O setup time before p-term clock input 1.0 - 1.6 - 2.1 - ns
TPH I/O hold time after p-term clock input 2.6 - 3.2 - 4.4 - ns
TPCO P-term clock output valid - 6.8 - 7.7 - 10.2 ns
TOE GTS to output valid - 4.5 - 5.0 - 7.0 ns
TOD GTS to output disable - 4.5 - 5.0 - 7.0 ns
TPOE Product term OE to output enabled - 8.4 - 9.5 - 11.0 ns
TPOD Product term OE to output disabled - 8.4 - 9.5 - 11.0 ns
TAO GSR to output valid - 10.8 - 12.0 - 14.5 ns
TPAO P-term S/R to output valid - 11.8 - 12.6 - 15.3 ns
TWLH GCK pulse width (High or Low) 2.4 - 4.0 - 4.5 - ns
TAPRPW Asynchronous preset/reset pulse width
(High or Low)
6.0 - 6.5 - 7.0 - ns
TPLH P-term clock pulse width (High or Low) 6.0 - 6.5 - 7.0 - ns
Figure 3: AC Load Circuit
Device Output
Output Type V
TEST
3.3V
2.5V
V
TEST
R
1
320 Ω
250 Ω
R
1
R
2
C
L
R
2
360 Ω
660 Ω
C
L
35 pF
35 pF
DS058_03_081500
V
CCIO
3.3V
2.5V
XC95288XL High Performance CPLD
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1-800-255-7778 Product Specification
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Internal Timing Parameters
Symbol Parameter
XC95288XL-6 XC95288XL-7 XC95288XL-10
UnitsMin Max Min Max Min Max
Buffer Delays
TIN Input buffer delay - 2.2 - 2.3 - 3.5 ns
TGCK GCK buffer delay - 1.2 - 1.5 - 1.8 ns
TGSR GSR buffer delay - 2.2 - 3.1 - 4.5 ns
TGTS GTS buffer delay - 4.5 - 5.0 - 7.0 ns
TOUT Output buffer delay - 2.4 - 2.5 - 3.0 ns
TEN Output buffer enable/disable
delay
-0-0-0ns
Product Term Control Delays
TPTCK Product term clock delay - 2.0 - 2.4 - 2.7 ns
TPTSR Product term set/reset delay - 1.0 - 1.4 - 1.8 ns
TPTTS Product term 3-state delay - 6.2 - 7.2 - 7.5 ns
Internal Register and Combinatorial Delays
TPDI Combinatorial logic propagation delay - 0.4 - 1.3 - 1.7 ns
TSUI Register setup time 2.0 - 2.6 - 3.0 - ns
THI Register hold time 1.6 - 2.2 - 3.5 - ns
TECSU Register clock enable setup time 2.0 - 2.6 - 3.0 - ns
TECHO Register clock enable hold time 1.6 - 2.2 - 3.5 - ns
TCOI Register clock to output valid time - 0.2 - 0.5 - 1.0 ns
TAOI Register async. S/R to output delay - 6.2 - 6.4 - 7.0 ns
TRAI Register async. S/R recover before clock 6.0 7.5 10.0 ns
TLOGI Internal logic delay - 1.0 - 1.4 - 1.8 ns
TLOGILP Internal low power logic delay - 5.5 - 6.4 - 7.3 ns
Feedback Delays
TFFast CONNECT II feedback delay - 1.6 - 3.5 - 4.2 ns
Time Adders
TPTA Incremental product term allocator delay
(first incremental delay)
-0.8-0.8-1.0ns
TPTA2 Incremental product term allocator delay
(subsequent incremental delay)
-0.3-0.3-0.4ns
TSLEW Slew-rate limited delay - 3.5 - 4.0 - 4.5 ns
XC95288XL High Performance CPLD
DS055 (v2.1 April 3, 2007 www.xilinx.com 7
Product Specification 1-800-255-7778
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XC95288XL I/O Pins (2)
Func-
tion
Block
Macro
cell TQ144 PQ208 BG256 FG256 CS280
BScan
Order
Func-
tion
Block
Macro
cell TQ144 PQ208 BG256 FG256 CS280
BScan
Order
11 ––––8613 1 –––753
1 2 28 L1 H1 K2 858 3 2 28 38 P1 L2 N2 750
1 3 29L2H5K3855 3 3 39R1L5P1747
14 ––––8523 4 –––744
1 5 20 30 L3 J1 K4 849 3 5 40 P3 M1 P2 741
1 6 21 31 L4 J5 L1 846 3 6 41 R2 L4 P3 738
17 ––––8433 7 –––735
1 8 22 32 M1 J2 L2 840 3 8 43 P4 N1 P4 732
1 9 M2 J3 L3 837 3 9 R3 L3 R1 729
11023 33M3K1L4834 3 1030
(1) 44(1) T2(1) M2(1) R3(1) 726
1 11 M4 J4 M1 831 3 11 U1 M4 R2 723
1 12 24 34 N1 K2 M2 828 3 12 31 45 T3 P1 R4 720
113 ––––825313––717
11425 35N2K5M3822 3 1432
(1) 46(1) U2(1) M3(1) T1(1) 714
115 26 36N3L1M4819 3 15 3347V1N2T2711
116 ––––816316–––708
1 17 27 37 N4 K3 N1 813 3 17 48 T4 N4 T3 705
118 ––––810318–––702
21 ––––8074 1 ––699
2 2 9 15G2D1G3804 4 2 2
(1) 3(1) C2(1) D3(1) C2(1) 696
2 3 10 16 G1 G4 G2 801 4 3 4 D2 D2 B1 693
24 ––––7984 4 ––690
2 5 11 17 H4 E1 G1 795 4 5 3(1) 5(1) D3(1) E3(1) C1(1) 687
2 6 12 18 H3 G3 G4 792 4 6 4 6 E4 C2 D4 684
27 ––––7894 7 ––681
2 8 13 19 H2 G2 H1 786 4 8 5(1) 7(1) C1(1) D4(1) D3(1) 678
2 9 H1 F5 H3 783 4 9 D1 B1 D2 675
2 10 14 20 J4 F1 H2 780 4 10 8 E3 E4 D1 672
2 11 J3 G5 H4777 4 11 E2 C1 E3669
21215 21J2H2J1774 4 126
(1) 9(1) E1(1) E5(1) E2(1) 666
213 ––––771413–––663
2 14 16 22 J1 H4 J2 768 4 14 7 10 F3 E2 E4 660
2 15 17 23 K2 G1 J3 765 4 15 12 F2 F2 F3 657
216 ––––762416–––654
2 17 19 25 K1 H3 J4 759 4 17 14 G3 E6 F4 651
218 ––––756418–––648
Notes:
1. Global control pin.
2. The pin-outs are the same for Pb-free versions of packages.
XC95288XL High Performance CPLD
8www.xilinx.com DS055 (v2.1 April 3, 2007
1-800-255-7778 Product Specification
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51 ––––6457 1 ––537
5 2 34 49 U3 R1 U1 642 7 2 62 W6 R3 W5 534
5 3 50 V2 N3 V1 639 7 3 45 63 Y6 M6 U6 531
54 ––––6367 4 ––528
5 5 35 51 V3 P2 U2 633 7 5 46 64 V7 T3 V6 525
5 6 54Y2P4V3630 7 6 66U8T4W6522
57 ––––6277 7 ––519
5838
(1) 55(1) W4(1) P5(1) W2(1) 624 7 8 67 W7 P7 U7 516
5 9 V4 T2 W3 621 7 9 Y7 T5 V7 513
5 10 39 56 U5 N5 T4 618 7 10 69 V8 N7 W7 510
5 11 Y3 R4 U4 615 7 11 W8 R7 T7 507
5 12 40 57 Y4M5V4612 7 12 4870 Y8M7W8504
513 ––––609713–––501
5 14 41 58 V5 R5 W4 606 7 14 71 U9 T6 U8 498
5 15 43 60 V6 R6 V5 603 7 15 49 72 V9 N8 V8 495
516 ––––600716–––492
5 17 44 61 U7 N6 T5 597 7 17 73 W9 T7 T8 489
518 ––––594718–––486
61 ––––5918 1 -–––483
6 2 135 197 D7 A5 D7 588 8 2 130 186 A9 E11 B10 480
6 3 136 198 C6 D6 A6 585 8 3 131 187 B9 A8 C10 477
64 ––––5828 4 ––474
6 5 137 199 B5 B5 B6 579 8 5 132 188 C9 C8 D10 471
6 6 138 200 A4 C6 C6 576 8 6 189 D9 B8 A9 468
67 ––––5738 7 ––465
6 8 139 201 C5 A4 D6 570 8 8 133 191 A8 D8 B9 462
6 9 B4 E7 A5 567 8 9 B8 A7 C9 459
6 10 140 202 A3 A3 C5 564 8 10 134 192 C8 E9 D9 456
6 11 D5 C5 B5 561 8 11 D8 B7 A8 453
6 12 203 C4 A2 D5 558 8 12 193 A7 D7 B8 450
613 ––––555813–––447
6 14 142 205 B2 B4 B4 552 8 14 194 B7 A6 C8 444
6 15 143(1) 206(1) A2(1) C4(1) C4(1) 549 8 15 195 B6 B6 B7 441
616 ––––546816–––438
6 17 208 C3 B3 A3 543 8 17 196 A5 E8 C7 435
618 ––––540818–––432
Notes:
1. Global control pin.
2. The pin-outs are the same for Pb-free versions of packages.
XC95288XL I/O Pins (Continued)(2)
Func-
tion
Block
Macro
cell TQ144 PQ208 BG256 FG256 CS280
BScan
Order
Func-
tion
Block
Macro
cell TQ144 PQ208 BG256 FG256 CS280
BScan
Order
XC95288XL High Performance CPLD
DS055 (v2.1 April 3, 2007 www.xilinx.com 9
Product Specification 1-800-255-7778
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91 ––––429111 –––321
9 2 50 74 Y11 R8 U9 426 11 2 87 Y15 P10 W13 318
9 3 51 75 W11 P8 T9 423 11 3 60 88 V14 T12 V13 315
94 ––––420114 –––312
9 5 52 76 V11 T8 W10 417 11 5 61 89 W15 N10 U13 309
9 6 53 77 U11 M8 V10 414 11 6 90 Y16 T13 T13 306
9 7 411 11 7 303
9 8 54 78 Y12 T9 U10 408 11 8 91 U14 M11 W14 300
9 9 W12 P9 W11 405 11 9 Y17 N11 T14 297
9 10 80 V12 R9 V11 402 11 10 64 95 V16 T14 W15 294
9 11 56 82 U12 M9 U11 399 11 11 66 97 Y18 R12 V15 291
9 12 57 83 Y13 T10 T11 396 11 12 68 99 V17 T15 W16 288
9 13 393 11 13 285
9 14 58 84 W13 M10 W12 390 11 14 69 100 Y19 R14 U16 282
9 15 85 V13 R10 V12 387 11 15 101 V18 N13 W17 279
9 16 384 11 16 276
9 17 59 86 W14 T11 T12 381 11 17 70 102 W19 R13 W18 273
9 18 378 11 18 270
10 1 375 12 1 267
10 2 117 170 A14 B11 C14 372 12 2 110 158 B18 B13 B19 264
10 3 118 171 C13 D11 B14 369 12 3 111 159 C17 B14 B18 261
10 4 366 12 4 258
10 5 119 173 B13 A11 A14 363 12 5 112 160 D16 C13 B17 255
10 6 120 174 A13 D10 C13 360 12 6 161 A18 A15 A18 252
10 7 357 12 7 249
10 8 121 175 D12 B10 B13 354 12 8 113 162 A17 C12 A17 246
10 9 C12 E12 A13 351 12 9 C16 B12 D16 243
10 10 124 178 A12 F12 A12 348 12 10 115 164 A16 D13 C16 240
10 11 125 179 B11 B9 C12 345 12 11 165 C15 A14 B16 237
10 12 126 180 C11 C9 B12 342 12 12 116 166 D14 E13 A16 234
10 13 339 12 13 231
10 14 128 182 B10 A9 B11 336 12 14 167 B15 A13 C15 228
10 15 183 C10 D9 C11 333 12 15 168 A15 C11 B15 225
10 16 330 12 16 222
10 17 129 185 D10 E10 A10 327 12 17 169 C14 A12 D15 219
10 18 324 12 18 216
Notes:
1. Global control pin.
2. The pin-outs are the same for Pb-free versions of packages.
XC95288XL I/O Pins (Continued)(2)
Func-
tion
Block
Macro
cell TQ144 PQ208 BG256 FG256 CS280
BScan
Order
Func-
tion
Block
Macro
cell TQ144 PQ208 BG256 FG256 CS280
BScan
Order
XC95288XL High Performance CPLD
10 www.xilinx.com DS055 (v2.1 April 3, 2007
1-800-255-7778 Product Specification
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13 1 213 15 1 105
13 2 71 103 Y20 P13 V17 210 15 2 79 117 P19 M12 P16 102
13 3 106 V19 P15 U18 207 15 3 80 118 P20 M16 P19 99
13 4 204 15 4 96
13 5 107 U19 N14 V19 201 15 5 119 N17 K14 N17 93
13 6 109 T17 R16 U19 198 15 6 120 N18 L16 N18 90
13 7 195 15 7 87
13 8 74 110 V20 N15 T16 192 15 8 81 121 N19 K13 N19 84
13 9 U20 M15 T17 189 15 9 N20 K15 N16 81
13 10 111 T18 M13 T18 186 15 10 82 122 M17 L12 M19 78
13 11 75 112 T19 P16 T19 183 15 11 83 123 M18 K16 M17 75
13 12 113 R18 N16 R18 180 15 12 85 125 M20 J14 M16 72
13 13 177 15 13 69
13 14 76 114 P17 M14 R16 174 15 14 86 126 L19 J15 L19 66
13 15 77 115 R20 L15 R19 171 15 15 87 127 L18 J13 L18 63
13 16 168 15 16 60
13 17 78 116 P18 L13 P17 165 15 17 88 128 L20 J16 L17 57
13 18 162 15 18 54
14 1 159 16 1 51
14 2 144 G19 F15 G19 156 16 2 91 131 K19 K12 L16 48
14 3 100 145 F19 E15 G16 153 16 3 92 133 K18 J12 K18 45
14 4 150 16 4 42
14 5 101 146 E20 F13 F19 147 16 5 93 134 K17 H15 K17 39
14 6 102 147 G17 D16 F18 144 16 6 94 135 J20 H14 K16 36
14 7 141 16 7 33
14 8 103 148 F18 F14 F17 138 16 8 95 136 J19 G16 J19 30
14 9 E19 C16 F16 135 16 9 J18 H13 J18 27
14 10 104 149 D20 E14 E19 132 16 10 96 137 J17 G15 J17 24
14 11 105 150 E18 D15 E17 129 16 11 97 138 H20 H16 J16 21
14 12 151 D19 G12 E18 126 16 12 98 139 H19 F16 H19 18
14 13 123 16 13 15
14 14 106 152 C20 C15 E16 120 16 14 140 H18 H12 H18 12
14 15 107 154 D18 D14 D18 117 16 15 142 H17 E16 H17 9
14 16 114 16 16 6
14 17 155 C18 B16 D17 111 16 17 143 G20 G14 H16 3
14 18 108 16 18 0
Notes:
1. Global control pin.
2. The pin-outs are the same for Pb-free versions of packages.
XC95288XL I/O Pins (Continued)(2)
Func-
tion
Block
Macro
cell TQ144 PQ208 BG256 FG256 CS280
BScan
Order
Func-
tion
Block
Macro
cell TQ144 PQ208 BG256 FG256 CS280
BScan
Order
XC95288XL High Performance CPLD
DS055 (v2.1 April 3, 2007 www.xilinx.com 11
Product Specification 1-800-255-7778
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XC95288XL Global, JTAG and Power Pins(1)
Pin Type TQ144 PQ208 BG256 FG256 CS280
I/O/GCK1 30 44 T2 M2 R3
I/O/GCK2 32 46 U2 M3 T1
I/O/GCK3 38 55 W4 P5 W2
I/O/GTS1 5 7 C1 D4 D3
I/O/GTS2 6 9 E1 E5 E2
I/O/GTS3 2 3 C2 D3 C2
I/O/GTS4 3 5 D3 E3 C1
I/O/GSR 143 206 A2 C4 C4
TCK 67 98 U16 P12 T15
TDI 63 94 W16 R11 U14
TDO 122 176 B12 A10 D13
TMS 65 96 W17 N12 U15
VCCINT 3.3V 8, 42, 84, 141 11, 59, 124, 153,
204
F1, P2, W5, Y9,
V10, U13, W18,
T20, M19, F20, E17,
B17, B14, A10, C7,
B3, G4
F4, F7, G6, H6, J6,
K6, L7, F8, L8, F9,
L9, F10, L10, G11,
H11, J11, K11
E1, F2, N3, U5, W9,
V9, U12, V16, R17,
M18, G18, D19,
C18, A15, A11, D8,
A4
VCCIO 2.5V/3.3 V 1, 37, 55, 73, 109,
127
1, 26, 53, 65, 79,
92, 105, 132, 157,
172, 181, 184
D4, D6, D11, D15,
D17, F4, F17, K4,
L17, R4, R17, U4,
U6, U10, U15, U17
F3, K4, D5, F6, L6,
P6, C7, N9, C10,
F11, L11, P11, D12,
G13, L14
C3, F1, K1, N4, V2
T6, T10, V14, V18,
P18, K19, G17,
C19, D14, D12, D11,
A7
GND 18, 29, 36, 47, 62,
72, 89, 90, 99,
108, 114, 123,
144
2, 13, 24, 27, 42,
52, 68, 81, 93,
104,1 08, 129,
130, 141, 156,
163, 177, 190,
207
B1, K3, T1, Y5,
W10, Y10, Y14,
V15, U18, R19, K20,
G18, B16, D13, A11,
A6, J9, J10, J11,
J12, K9, K10, K11,
K12, L9, L10, L11,
L12, M9, M10, M11,
M12
A1, A16, C14, T1,
B2, B15, R2, C3,
P3, G7, H7, J7, K7,
G8, H8, J8, K8, G9,
H9, J9, K9, G10,
H10, J10, K10, P14,
R15, T16
E5, F5, G5, H5, J5,
K5, L5, M5, N5, R5,
R6, R7, R8, R9 R10,
R11, R12, R13, R14,
R15, P15, N15,
M15, L15, K15, J15,
H15, G15, F15, E15,
E14, E13, E12, E11,
E10, E9, E8, E7, E6,
P5
No Connects A1, A19, A20, B19,
B20, C19, W1, W2,
W3, W20, Y1
- A1, B2, W1, U3,
W19, U17, A19,
C17, A2, B3
Notes:
1. The pin-outs are the same for Pb-free versions of packages.