June 2004 Connectivity Solutions
Data M anua
l
SCPS082
IMPORTANT NOTICE
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Products Applications
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Copyright 2004, Texas Instruments Incorporated
iii
Contents
Section Title Page
1 Introduction 1−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 Controller Functional Description 1−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1.1 PCI6621 Controller 1−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1.2 PCI6421 Controller 1−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1.3 PCI6611 Controller 1−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1.4 PCI6411 Controller 1−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1.5 Multifunctional Terminals 1−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1.6 PCI Bus Power Management 1−3. . . . . . . . . . . . . . . . . . . . . . . . .
1.1.7 Power Switch Interface 1−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Features 1−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Related Documents 1−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 Trademarks 1−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 Terms and Definitions 1−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.6 Ordering Information 1−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Terminal Descriptions 2−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 Detailed Terminal Descriptions 2−13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Feature/Protocol Descriptions 3−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Power Supply Sequencing 3−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 I/O Characteristics 3−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 Clamping Voltages 3−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4 Peripheral Component Interconnect (PCI) Interface 3−2. . . . . . . . . . . . . .
3.4.1 Device Resets 3−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.2 Serial EEPROM I2C Bus 3−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.3 Functions 0 and 1 (CardBus) Subsystem Identification 3−3. . .
3.4.4 Function 3 (Flash Media) Subsystem Identification 3−4. . . . . .
3.4.5 Function 4 SD Host Subsystem Identification 3−4. . . . . . . . . . .
3.4.6 Function 5 Smart Card Subsystem Identification 3−4. . . . . . . .
3.5 PC Card Applications 3−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.1 PC Card Insertion/Removal and Recognition 3−4. . . . . . . . . . .
3.5.2 Low Voltage CardBus Card Detection 3−5. . . . . . . . . . . . . . . . .
3.5.3 UltraMedia Card Detection 3−5. . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.4 Flash Media Card Detection 3−6. . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.5 Power Switch Interface 3−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.6 Internal Ring Oscillator 3−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.7 Integrated Pullup Resistors for PC Card Interface 3−7. . . . . . .
3.5.8 SPKROUT and CAUDPWM Usage 3−7. . . . . . . . . . . . . . . . . . .
3.5.9 LED Socket Activity Indicators 3−8. . . . . . . . . . . . . . . . . . . . . . . .
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3.5.10 CardBus Socket Registers 3−8. . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.11 48-MHz Clock Requirements 3−9. . . . . . . . . . . . . . . . . . . . . . . . .
3.6 Serial EEPROM Interface 3−9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.1 Serial-Bus Interface Implementation 3−9. . . . . . . . . . . . . . . . . . .
3.6.2 Accessing Serial-Bus Devices Through Software 3−9. . . . . . .
3.6.3 Serial-Bus Interface Protocol 3−10. . . . . . . . . . . . . . . . . . . . . . . . .
3.6.4 Serial-Bus EEPROM Application 3−12. . . . . . . . . . . . . . . . . . . . . .
3.7 Programmable Interrupt Subsystem 3−15. . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.1 PC Card Functional and Card Status Change Interrupts 3−15.
3.7.2 Interrupt Masks and Flags 3−17. . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.3 Using Parallel IRQ Interrupts 3−17. . . . . . . . . . . . . . . . . . . . . . . . .
3.7.4 Using Parallel PCI Interrupts 3−18. . . . . . . . . . . . . . . . . . . . . . . . .
3.7.5 Using Serialized IRQSER Interrupts 3−18. . . . . . . . . . . . . . . . . . .
3.7.6 SMI Support in the PCI6x21/PCI6x11 Controller 3−18. . . . . . . .
3.8 Power Management Overview 3−19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.1 Integrated Low-Dropout Voltage Regulator (LDO-VR) 3−20. . . .
3.8.2 CardBus (Functions 0 and 1) Clock Run Protocol 3−20. . . . . . .
3.8.3 CardBus PC Card Power Management 3−21. . . . . . . . . . . . . . . .
3.8.4 16-Bit PC Card Power Management 3−21. . . . . . . . . . . . . . . . . . .
3.8.5 Suspend Mode 3−21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.6 Requirements for Suspend Mode 3−22. . . . . . . . . . . . . . . . . . . . .
3.8.7 Ring Indicate 3−22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.8 PCI Power Management 3−23. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.8.1 CardBus Power Management
(Functions 0 and 1) 3−23. . . . . . . . . . . . . . . . . . . . . .
3.8.8.2 Flash Media (Function 3)
Power Management 3−24. . . . . . . . . . . . . . . . . . . . . .
3.8.8.3 SD Host (Function 4)
Power Management 3−24. . . . . . . . . . . . . . . . . . . . . .
3.8.8.4 Smart Card (Function 5)
Power Management 3−24. . . . . . . . . . . . . . . . . . . . . .
3.8.9 CardBus Bridge Power Management 3−25. . . . . . . . . . . . . . . . . .
3.8.10 ACPI Support 3−25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.11 Master List of PME Context Bits and Global Reset-Only
Bits 3−26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 PC Card Controller Programming Model 4−1. . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 PCI Configuration Register Map (Functions 0 and 1) 4−1. . . . . . . . . . . . .
4.2 Vendor ID Register 4−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3 Device ID Register Functions 0 and 1 4−3. . . . . . . . . . . . . . . . . . . . . . . . . .
4.4 Command Register 4−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5 Status Register 4−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6 Revision ID Register 4−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7 Class Code Register 4−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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4.8 Cache Line Size Register 4−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.9 Latency Timer Register 4−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.10 Header Type Register 4−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.11 BIST Register 4−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.12 CardBus Socket Registers/ExCA Base Address Register 4−8. . . . . . . . .
4.13 Capability Pointer Register 4−8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.14 Secondary Status Register 4−9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.15 PCI Bus Number Register 4−10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.16 CardBus Bus Number Register 4−10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.17 Subordinate Bus Number Register 4−10. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.18 CardBus Latency Timer Register 4−11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.19 CardBus Memory Base Registers 0, 1 4−11. . . . . . . . . . . . . . . . . . . . . . . . . .
4.20 CardBus Memory Limit Registers 0, 1 4−12. . . . . . . . . . . . . . . . . . . . . . . . . .
4.21 CardBus I/O Base Registers 0, 1 4−12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.22 CardBus I/O Limit Registers 0, 1 4−13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.23 Interrupt Line Register 4−13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.24 Interrupt Pin Register 4−14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.25 Bridge Control Register 4−15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.26 Subsystem Vendor ID Register 4−16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.27 Subsystem ID Register 4−16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.28 PC Card 16-Bit I/F Legacy-Mode Base-Address Register 4−17. . . . . . . . .
4.29 System Control Register 4−18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.30 MC_CD Debounce Register 4−20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.31 General Control Register 4−21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.32 General-Purpose Event Status Register 4−22. . . . . . . . . . . . . . . . . . . . . . . .
4.33 General-Purpose Event Enable Register 4−23. . . . . . . . . . . . . . . . . . . . . . .
4.34 General-Purpose Input Register 4−23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.35 General-Purpose Output Register 4−24. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.36 Multifunction Routing Status Register 4−25. . . . . . . . . . . . . . . . . . . . . . . . . .
4.37 Retry Status Register 4−26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.38 Card Control Register 4−27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.39 Device Control Register 4−28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.40 Diagnostic Register 4−29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.41 Capability ID Register 4−30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.42 Next Item Pointer Register 4−30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.43 Power Management Capabilities Register 4−31. . . . . . . . . . . . . . . . . . . . . .
4.44 Power Management Control/Status Register 4−32. . . . . . . . . . . . . . . . . . . .
4.45 Power Management Control/Status Bridge Support Extensions
Register 4−33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.46 Power-Management Data Register 4−33. . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.47 Serial Bus Data Register 4−34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.48 Serial Bus Index Register 4−34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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4.49 Serial Bus Slave Address Register 4−35. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.50 Serial Bus Control/Status Register 4−36. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 ExCA Compatibility Registers (Functions 0 and 1) 5−1. . . . . . . . . . . . . . . . . .
5.1 ExCA Identification and Revision Register 5−5. . . . . . . . . . . . . . . . . . . . . .
5.2 ExCA Interface Status Register 5−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3 ExCA Power Control Register 5−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4 ExCA Interrupt and General Control Register 5−8. . . . . . . . . . . . . . . . . . .
5.5 ExCA Card Status-Change Register 5−9. . . . . . . . . . . . . . . . . . . . . . . . . . .
5.6 ExCA Card Status-Change Interrupt Configuration Register 5−10. . . . . . .
5.7 ExCA Address Window Enable Register 5−11. . . . . . . . . . . . . . . . . . . . . . . .
5.8 ExCA I/O Window Control Register 5−12. . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.9 ExCA I/O Windows 0 and 1 Start-Address Low-Byte Registers 5−13. . . .
5.10 ExCA I/O Windows 0 and 1 Start-Address High-Byte Registers 5−13. . . .
5.11 ExCA I/O Windows 0 and 1 End-Address Low-Byte Registers 5−14. . . . .
5.12 ExCA I/O Windows 0 and 1 End-Address High-Byte Registers 5−14. . . .
5.13 ExCA Memory Windows 0−4 Start-Address Low-Byte Registers 5−15. . .
5.14 ExCA Memory Windows 0−4 Start-Address High-Byte Registers 5−16. . .
5.15 ExCA Memory Windows 0−4 End-Address Low-Byte Registers 5−17. . . .
5.16 ExCA Memory Windows 0−4 End-Address High-Byte Registers 5−18. . .
5.17 ExCA Memory Windows 0−4 Offset-Address Low-Byte Registers 5−19. .
5.18 ExCA Memory Windows 0−4 Offset-Address High-Byte Registers 5−20.
5.19 ExCA Card Detect and General Control Register 5−21. . . . . . . . . . . . . . . .
5.20 ExCA Global Control Register 5−22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.21 ExCA I/O Windows 0 and 1 Offset-Address Low-Byte Registers 5−23. . .
5.22 ExCA I/O Windows 0 and 1 Offset-Address High-Byte Registers 5−23. . .
5.23 ExCA Memory Windows 0−4 Page Registers 5−24. . . . . . . . . . . . . . . . . . .
6 CardBus Socket Registers (Functions 0 and 1) 6−1. . . . . . . . . . . . . . . . . . . . . .
6.1 Socket Event Register 6−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2 Socket Mask Register 6−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3 Socket Present State Register 6−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4 Socket Force Event Register 6−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.5 Socket Control Register 6−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.6 Socket Power Management Register 6−8. . . . . . . . . . . . . . . . . . . . . . . . . . .
7 Flash Media Controller Programming Model 7−1. . . . . . . . . . . . . . . . . . . . . . . .
7.1 Vendor ID Register 7−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2 Device ID Register 7−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3 Command Register 7−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.4 Status Register 7−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.5 Class Code and Revision ID Register 7−5. . . . . . . . . . . . . . . . . . . . . . . . . .
7.6 Latency Timer and Class Cache Line Size Register 7−5. . . . . . . . . . . . . .
7.7 Header Type and BIST Register 7−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.8 Flash Media Base Address Register 7−6. . . . . . . . . . . . . . . . . . . . . . . . . . .
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7.9 Subsystem Vendor Identification Register 7−7. . . . . . . . . . . . . . . . . . . . . . .
7.10 Subsystem Identification Register 7−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.11 Capabilities Pointer Register 7−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.12 Interrupt Line Register 7−8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.13 Interrupt Pin Register 7−8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.14 Minimum Grant Register 7−9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.15 Maximum Latency Register 7−9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.16 Capability ID and Next Item Pointer Registers 7−10. . . . . . . . . . . . . . . . . . .
7.17 Power Management Capabilities Register 7−11. . . . . . . . . . . . . . . . . . . . . .
7.18 Power Management Control and Status Register 7−12. . . . . . . . . . . . . . . .
7.19 Power Management Bridge Support Extension Register 7−12. . . . . . . . . .
7.20 Power Management Data Register 7−13. . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.21 General Control Register 7−13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.22 Subsystem Access Register 7−14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.23 Diagnostic Register 7−15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8 SD Host Controller Programming Model 8−1. . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.1 Vendor ID Register 8−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.2 Device ID Register 8−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.3 Command Register 8−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.4 Status Register 8−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.5 Class Code and Revision ID Register 8−5. . . . . . . . . . . . . . . . . . . . . . . . . .
8.6 Latency Timer and Class Cache Line Size Register 8−6. . . . . . . . . . . . . .
8.7 Header Type and BIST Register 8−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.8 SD Host Base Address Register 8−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.9 Subsystem Vendor Identification Register 8−7. . . . . . . . . . . . . . . . . . . . . . .
8.10 Subsystem Identification Register 8−8. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.11 Capabilities Pointer Register 8−8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.12 Interrupt Line Register 8−8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.13 Interrupt Pin Register 8−9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.14 Minimum Grant Register 8−9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.15 Maximum Latency Register 8−10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.16 Slot Information Register 8−10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.17 Capability ID and Next Item Pointer Registers 8−11. . . . . . . . . . . . . . . . . . .
8.18 Power Management Capabilities Register 8−12. . . . . . . . . . . . . . . . . . . . . .
8.19 Power Management Control and Status Register 8−13. . . . . . . . . . . . . . . .
8.20 Power Management Bridge Support Extension Register 8−13. . . . . . . . . .
8.21 Power Management Data Register 8−14. . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.22 General Control Register 8−14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.23 Subsystem Access Register 8−15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.24 Diagnostic Register 8−15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.25 Slot 0 3.3-V Maximum Current Register 8−16. . . . . . . . . . . . . . . . . . . . . . . .
8.26 Slot 1 3.3-V Maximum Current Register 8−16. . . . . . . . . . . . . . . . . . . . . . . .
viii
Section Title Page
8.27 Slot 2 3.3-V Maximum Current Register 8−16. . . . . . . . . . . . . . . . . . . . . . . .
8.28 Slot 3 3.3-V Maximum Current Register 8−17. . . . . . . . . . . . . . . . . . . . . . . .
8.29 Slot 4 3.3-V Maximum Current Register 8−17. . . . . . . . . . . . . . . . . . . . . . . .
8.30 Slot 5 3.3-V Maximum Current Register 8−17. . . . . . . . . . . . . . . . . . . . . . . .
9 Smart Card Controller Programming Model 9−1. . . . . . . . . . . . . . . . . . . . . . . . .
9.1 Vendor ID Register 9−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.2 Device ID Register 9−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.3 Command Register 9−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.4 Status Register 9−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.5 Class Code and Revision ID Register 9−5. . . . . . . . . . . . . . . . . . . . . . . . . .
9.6 Latency Timer and Class Cache Line Size Register 9−5. . . . . . . . . . . . . .
9.7 Header Type and BIST Register 9−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.8 Smart Card Base Address Register 0 9−6. . . . . . . . . . . . . . . . . . . . . . . . . .
9.9 Smart Card Base Address Register 1−4 9−7. . . . . . . . . . . . . . . . . . . . . . . .
9.10 Subsystem Vendor Identification Register 9−7. . . . . . . . . . . . . . . . . . . . . . .
9.11 Subsystem Identification Register 9−8. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.12 Capabilities Pointer Register 9−8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.13 Interrupt Line Register 9−8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.14 Interrupt Pin Register 9−9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.15 Minimum Grant Register 9−9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.16 Maximum Latency Register 9−10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.17 Capability ID and Next Item Pointer Registers 9−10. . . . . . . . . . . . . . . . . . .
9.18 Power Management Capabilities Register 9−11. . . . . . . . . . . . . . . . . . . . . .
9.19 Power Management Control and Status Register 9−12. . . . . . . . . . . . . . . .
9.20 Power Management Bridge Support Extension Register 9−12. . . . . . . . . .
9.21 Power Management Data Register 9−13. . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.22 General Control Register 9−13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.23 Subsystem ID Alias Register 9−14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.24 Class Code Alias Register 9−14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.25 Smart Card Configuration 1 Register 9−15. . . . . . . . . . . . . . . . . . . . . . . . . . .
9.26 Smart Card Configuration 2 Register 9−17. . . . . . . . . . . . . . . . . . . . . . . . . . .
10 Electrical Characteristics 10−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.1 Absolute Maximum Ratings Over Operating Temperature Ranges 10−1.
10.2 Recommended Operating Conditions 10−1. . . . . . . . . . . . . . . . . . . . . . . . . .
10.3 Electrical Characteristics Over Recommended Operating
Conditions 10−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.4 Electrical Characteristics Over Recommended Ranges of Operating
Conditions 10−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.4.1 Device 10−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.4.2 Driver 10−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.4.3 Receiver 10−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.5 PCI Clock/Reset Timing Requirements Over Recommended Ranges
of Supply Voltage and Operating Free-Air Temperature 10−4. . . . . . . . . . .
ix
Section Title Page
10.6 Switching Characteristics for PHY Port Interface 10−5. . . . . . . . . . . . . . . . .
10.7 Operating, Timing, and Switching Characteristics of XI 10−5. . . . . . . . . . .
10.8 PCI Timing Requirements Over Recommended Ranges of
Supply Voltage and Operating Free-Air Temperature 10−5. . . . . . . . . . . . .
11 Mechanical Information 11−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
x
List of Illustrations
Figure Title Page
2−1 PCI6621 GHK/ZHK-Package Terminal Diagram 2−1. . . . . . . . . . . . . . . . . . . . .
2−2 PCI6421 GHK/ZHK-Package Terminal Diagram 2−2. . . . . . . . . . . . . . . . . . . . .
2−3 PCI6611 GHK/ZHK-Package Terminal Diagram 2−3. . . . . . . . . . . . . . . . . . . . .
2−4 PCI6411 GHK/ZHK-Package Terminal Diagram 2−4. . . . . . . . . . . . . . . . . . . . .
3−1 PCI6x21/PCI6x11 System Block Diagram 3−1. . . . . . . . . . . . . . . . . . . . . . . . . .
3−2 3-State Bidirectional Buffer 3−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−3 Serial ROM Application 3−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−4 SPKROUT Connection to Speaker Driver 3−8. . . . . . . . . . . . . . . . . . . . . . . . . .
3−5 Two Sample LED Circuits 3−8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−6 Serial-Bus Start/Stop Conditions and Bit Transfers 3−10. . . . . . . . . . . . . . . . . .
3−7 Serial-Bus Protocol Acknowledge 3−10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−8 Serial-Bus Protocol—Byte Write 3−11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−9 Serial-Bus Protocol—Byte Read 3−11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−10 EEPROM Interface Doubleword Data Collection 3−12. . . . . . . . . . . . . . . . . . . .
3−11 IRQ Implementation 3−18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−12 System Diagram Implementing CardBus Device Class Power
Management 3−20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−13 Signal Diagram of Suspend Function 3−22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−14 RI_OUT Functional Diagram 3−23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−15 Block Diagram of a Status/Enable Cell 3−25. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−1 ExCA Register Access Through I/O 5−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−2 ExCA Register Access Through Memory 5−2. . . . . . . . . . . . . . . . . . . . . . . . . . .
6−1 Accessing CardBus Socket Registers Through PCI Memory 6−1. . . . . . . . . .
10−1 Test Load Diagram 10−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
xi
List of Tables
Table Title Page
1−1 Terms and Definitions 1−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−1 Signal Names by GHK Terminal Number 2−5. . . . . . . . . . . . . . . . . . . . . . . . . . .
2−2 CardBus PC Card Signal Names Sorted Alphabetically 2−9. . . . . . . . . . . . . .
2−3 16-Bit PC Card Signal Names Sorted Alphabetically 2−11. . . . . . . . . . . . . . . . .
2−4 Power Supply Terminals 2−14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−5 PC Card Power Switch Terminals 2−15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−6 PCI System Terminals 2−15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−7 PCI Address and Data Terminals 2−16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−8 PCI Interface Control Terminals 2−17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−9 Multifunction and Miscellaneous Terminals 2−18. . . . . . . . . . . . . . . . . . . . . . . . .
2−10 16-Bit PC Card Address and Data Terminals 2−19. . . . . . . . . . . . . . . . . . . . . . .
2−11 16-Bit PC Card Interface Control Terminals 2−20. . . . . . . . . . . . . . . . . . . . . . . . .
2−12 CardBus PC Card Interface System Terminals 2−22. . . . . . . . . . . . . . . . . . . . . .
2−13 CardBus PC Card Address and Data Terminals 2−23. . . . . . . . . . . . . . . . . . . . .
2−14 CardBus PC Card Interface Control Terminals 2−24. . . . . . . . . . . . . . . . . . . . . .
2−15 Reserved Terminals 2−26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−16 SD/MMC Terminals 2−26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−17 Memory Stick/PRO Terminals 2−26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−18 Smart Media/XD Terminals 2−27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−19 Smart Card Terminals 2−28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−1 PC Card—Card Detect and Voltage Sense Connections 3−5. . . . . . . . . . . . .
3−2 TPS2228 Control Logic—xVPP/VCORE 3−6. . . . . . . . . . . . . . . . . . . . . . . . . . .
3−3 TPS2228 Control Logic—xVCC 3−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−4 TPS2226 Control Logic—xVPP 3−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−5 TPS2226 Control Logic—xVCC 3−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−6 CardBus Socket Registers 3−9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−7 PCI6x21/PCI6x11 Registers Used to Program Serial-Bus Devices 3−10. . . . .
3−8 EEPROM Loading Map 3−13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−9 Interrupt Mask and Flag Registers 3−16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−10 PC Card Interrupt Events and Description 3−16. . . . . . . . . . . . . . . . . . . . . . . . . .
3−11 Interrupt Pin Register Cross Reference 3−18. . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−12 SMI Control 3−19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−13 Requirements for Internal/External 1.5-V Core Power Supply 3−20. . . . . . . . .
3−14 Power-Management Registers 3−24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−15 Function 3 Power-Management Registers 3−24. . . . . . . . . . . . . . . . . . . . . . . . . .
3−16 Function 4 Power-Management Registers 3−24. . . . . . . . . . . . . . . . . . . . . . . . . .
3−17 Function 5 Power-Management Registers 3−25. . . . . . . . . . . . . . . . . . . . . . . . . .
xii
Table Title Page
4−1 Bit Field Access Tag Descriptions 4−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−2 Functions 0 and 1 PCI Configuration Register Map 4−1. . . . . . . . . . . . . . . . . .
4−3 Command Register Description 4−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−4 Status Register Description 4−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−5 Secondary Status Register Description 4−9. . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−6 Interrupt Pin Register Cross Reference 4−15. . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−7 Bridge Control Register Description 4−15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−8 System Control Register Description 4−18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−9 General Control Register Description 4−21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−10 General-Purpose Event Status Register Description 4−22. . . . . . . . . . . . . . . . .
4−11 General-Purpose Event Enable Register Description 4−23. . . . . . . . . . . . . . . .
4−12 General-Purpose Input Register Description 4−23. . . . . . . . . . . . . . . . . . . . . . . .
4−13 General-Purpose Output Register Description 4−24. . . . . . . . . . . . . . . . . . . . . .
4−14 Multifunction Routing Status Register Description 4−25. . . . . . . . . . . . . . . . . . .
4−15 Retry Status Register Description 4−26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−16 Card Control Register Description 4−27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−17 Device Control Register Description 4−28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−18 Diagnostic Register Description 4−29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−19 Power Management Capabilities Register Description 4−31. . . . . . . . . . . . . . .
4−20 Power Management Control/Status Register Description 4−32. . . . . . . . . . . . .
4−21 Power Management Control/Status Bridge Support Extensions Register
Description 4−33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−22 Serial Bus Data Register Description 4−34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−23 Serial Bus Index Register Description 4−34. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−24 Serial Bus Slave Address Register Description 4−35. . . . . . . . . . . . . . . . . . . . .
4−25 Serial Bus Control/Status Register Description 4−36. . . . . . . . . . . . . . . . . . . . . .
5−1 ExCA Registers and Offsets 5−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−2 ExCA Identification and Revision Register Description 5−5. . . . . . . . . . . . . . .
5−3 ExCA Interface Status Register Description 5−6. . . . . . . . . . . . . . . . . . . . . . . .
5−4 ExCA Power Control Register Description—82365SL Support 5−7. . . . . . . .
5−5 ExCA Power Control Register Description—82365SL-DF Support 5−7. . . . .
5−6 ExCA Interrupt and General Control Register Description 5−8. . . . . . . . . . . .
5−7 ExCA Card Status-Change Register Description 5−9. . . . . . . . . . . . . . . . . . . .
5−8 ExCA Card Status-Change Interrupt Configuration Register
Description 5−10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−9 ExCA Address Window Enable Register Description 5−11. . . . . . . . . . . . . . . .
5−10 ExCA I/O Window Control Register Description 5−12. . . . . . . . . . . . . . . . . . . . .
5−11 ExCA Memory Windows 0−4 Start-Address High-Byte Registers
Description 5−16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−12 ExCA Memory Windows 0−4 End-Address High-Byte Registers
Description 5−18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−13 ExCA Memory Windows 0−4 Offset-Address High-Byte Registers
Description 5−20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−14 ExCA Card Detect and General Control Register Description 5−21. . . . . . . . .
xiii
Table Title Page
5−15 ExCA Global Control Register Description 5−22. . . . . . . . . . . . . . . . . . . . . . . . .
6−1 CardBus Socket Registers 6−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−2 Socket Event Register Description 6−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−3 Socket Mask Register Description 6−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−4 Socket Present State Register Description 6−4. . . . . . . . . . . . . . . . . . . . . . . . .
6−5 Socket Force Event Register Description 6−6. . . . . . . . . . . . . . . . . . . . . . . . . .
6−6 Socket Control Register Description 6−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−7 Socket Power Management Register Description 6−8. . . . . . . . . . . . . . . . . . .
7−1 Function 3 Configuration Register Map 7−1. . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−2 Command Register Description 7−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−3 Status Register Description 7−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−4 Class Code and Revision ID Register Description 7−5. . . . . . . . . . . . . . . . . . .
7−5 Latency Timer and Class Cache Line Size Register Description 7−5. . . . . . .
7−6 Header Type and BIST Register Description 7−6. . . . . . . . . . . . . . . . . . . . . . . .
7−7 Flash Media Base Address Register Description 7−6. . . . . . . . . . . . . . . . . . . .
7−8 PCI Interrupt Pin Register 7−8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−9 Minimum Grant Register Description 7−9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−10 Maximum Latency Register Description 7−9. . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−11 Capability ID and Next Item Pointer Registers Description 7−10. . . . . . . . . . . .
7−12 Power Management Capabilities Register Description 7−11. . . . . . . . . . . . . . .
7−13 Power Management Control and Status Register Description 7−12. . . . . . . . .
7−14 General Control Register 7−13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−15 Subsystem Access Register Description 7−14. . . . . . . . . . . . . . . . . . . . . . . . . . .
7−16 Diagnostic Register Description 7−15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8−1 Function 4 Configuration Register Map 8−1. . . . . . . . . . . . . . . . . . . . . . . . . . . .
8−2 Command Register Description 8−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8−3 Status Register Description 8−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8−4 Class Code and Revision ID Register Description 8−5. . . . . . . . . . . . . . . . . . .
8−5 Latency Timer and Class Cache Line Size Register Description 8−6. . . . . . .
8−6 Header Type and BIST Register Description 8−6. . . . . . . . . . . . . . . . . . . . . . . .
8−7 SD host Base Address Register Description 8−7. . . . . . . . . . . . . . . . . . . . . . . .
8−8 PCI Interrupt Pin Register 8−9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8−9 Minimum Grant Register Description 8−9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8−10 Maximum Latency Register Description 8−10. . . . . . . . . . . . . . . . . . . . . . . . . . . .
8−11 Maximum Latency Register Description 8−10. . . . . . . . . . . . . . . . . . . . . . . . . . . .
8−12 Capability ID and Next Item Pointer Registers Description 8−11. . . . . . . . . . . .
8−13 Power Management Capabilities Register Description 8−12. . . . . . . . . . . . . . .
8−14 Power Management Control and Status Register Description 8−13. . . . . . . . .
8−15 General Control Register 8−14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8−16 Subsystem Access Register Description 8−15. . . . . . . . . . . . . . . . . . . . . . . . . . .
8−17 Diagnostic Register Description 8−15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9−1 Function 5 Configuration Register Map 9−1. . . . . . . . . . . . . . . . . . . . . . . . . . . .
9−2 Command Register Description 9−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
xiv
Table Title Page
9−3 Status Register Description 9−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9−4 Class Code and Revision ID Register Description 9−5. . . . . . . . . . . . . . . . . . .
9−5 Latency Timer and Class Cache Line Size Register Description 9−5. . . . . . .
9−6 Header Type and BIST Register Description 9−6. . . . . . . . . . . . . . . . . . . . . . . .
9−7 PCI Interrupt Pin Register 9−9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9−8 Minimum Grant Register Description 9−9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9−9 Maximum Latency Register Description 9−10. . . . . . . . . . . . . . . . . . . . . . . . . . . .
9−10 Capability ID and Next Item Pointer Registers Description 9−10. . . . . . . . . . . .
9−11 Power Management Capabilities Register Description 9−11. . . . . . . . . . . . . . .
9−12 Power Management Control and Status Register Description 9−12. . . . . . . . .
9−13 General Control Register 9−13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9−14 Subsystem ID Alias Register Description 9−14. . . . . . . . . . . . . . . . . . . . . . . . . . .
9−15 Smart Card Configuration 1 Register Description 9−16. . . . . . . . . . . . . . . . . . . .
9−16 Smart Card Configuration 2 Register Description 9−17. . . . . . . . . . . . . . . . . . . .
1−1
1 Introduction
The Texas Instruments PCI6621 controller is an integrated dual-socket UltraMedia PC Card controller, Smart Card
controller, and flash media controller. This high-performance integrated solution provides the latest in PC Card, Smart
Card, Secure Digital (SD), MultiMediaCard (MMC), Memory Stick/PRO, SmartMedia, and XD technology.
The Texas Instruments PCI6421 controller is an integrated dual-socket UltraMedia PC Card controller, and flash
media controller. This high-performance integrated solution provides the latest in PC Card, SD, MMC, Memory
Stick/PRO, SmartMedia, and XD technology.
The Texas Instruments PCI6611 controller is an integrated single-socket UltraMedia PC Card controller, Smart Card
controller, and flash media controller. This high-performance integrated solution provides the latest in PC Card, Smart
Card, SD, MMC, Memory Stick/PRO, SmartMedia, and XD technology.
The Texas Instruments PCI6411 controller is an integrated single-socket UltraMedia PC Card controller and flash
media controller. This high-performance integrated solution provides the latest in PC Card, SD, MMC, Memory
Stick/PRO, SmartMedia, and XD technology.
For the remainder of this document, the PCI6x21 controller refers to the PCI6621 and PCI6421 controllers, and the
PCI6x11 controller refers to the PCI6611 and PCI6411 controllers.
1.1 Controller Functional Description
1.1.1 PCI6621 Controller
The PCI6621 controller is a five-function PCI controller compliant with PCI Local Bus Specification, Revision 2.3.
Functions 0 and 1 provide the independent PC Card socket controllers compliant with the PC Card Standard (Release
8.1). The PCI6621 controller provides features that make it the best choice for bridging between the PCI bus and PC
Cards, and supports any combination of Smart Card, Flash Media, 16-bit, CardBus, and USB custom card interface
PC Cards in the two sockets, powered at 5 V or 3.3 V, as required.
All card signals are internally buffered to allow hot insertion and removal without external buffering. The PCI6621
controller is register compatible with the Intel 82365SL-DF ExCA controller. The PCI6621 internal data path logic
allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance. Independent
buffering and a pipeline architecture provide an unsurpassed performance level with sustained bursting. The
PCI6621 controller can be programmed to accept posted writes to improve bus utilization.
Function 3 of the PCI6621 controller is a PCI-based Flash Media controller that supports Memory Stick, Memory
Stick-Pro, SmartMedia, XD, SD, and MMC cards. This function controls communication with these Flash Media cards
through a passive PC Card adapter or through a dedicated Flash Media socket. In addition, this function includes D MA
capabilities for improved Flash Media performance.
Function 4 o f the PCI6621 controller is a PCI-based SD host controller that supports MMC, SD, and SDIO cards. This
function controls communication with these Flash Media cards through a passive PC Card adapter or through a
dedicated Flash Media socket. In addition, this function is compliant with the SD Host Controller Standard
Specification and includes both DMA capabilities and support for SD suspend/resume.
Function 5 of the PCI6621 controller is a PCI-based Smart Card controller used for communication with Smart Cards
inserted in P C Card adapters. Utilizing Smart Card technology from Gemplus, this function provides compatibility with
many different types of Smart Cards.
1.1.2 PCI6421 Controller
The PCI6421 controller is a four-function PCI controller compliant with PCI Local Bus Specification, Revision 2.3.
1−2
Functions 0 a n d 1 provide the independent PC Card socket controllers compliant with the PC Card Standard (Release
8.1). The PCI6421 controller provides features that make it the best choice for bridging between the PCI bus and PC
Cards, and supports any combination of Smart Card, Flash Media, 16-bit, CardBus, and USB custom card interface
PC Cards in the two sockets, powered at 5 V or 3.3 V, as required.
All card signals are internally buffered to allow hot insertion and removal without external buffering. The PCI6421
controller is register compatible with the Intel 82365SL-DF ExCA controller. The PCI6421 internal data path logic
allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance. Independent
buffering and a pipeline architecture provide an unsurpassed performance level with sustained bursting. The
PCI6421 controller can be programmed to accept posted writes to improve bus utilization.
Function 3 of the PCI6421 controller is a PCI-based Flash Media controller that supports Memory Stick, Memory
Stick-Pro, SmartMedia, XD, SD, and MMC cards. This function controls communication with these Flash Media cards
through a passive PC Card adapter or through a dedicated Flash Media socket. In addition, this function includes D MA
capabilities for improved Flash Media performance.
Function 4 o f the PCI6421 controller is a PCI-based SD host controller that supports MMC, SD, and SDIO cards. This
function controls communication with these Flash Media cards through a passive PC Card adapter or through a
dedicated Flash Media socket. In addition, this function is compliant with the SD Host Controller Standard
Specification and includes both DMA capabilities and support for SD suspend/resume.
1.1.3 PCI6611 Controller
The PCI6611 controller is a four-function PCI controller compliant with PCI Local Bus Specification, Revision 2.3.
Function 0 provides an independent PC Card socket controller compliant with the PC Card Standard (Release 8.1).
The PCI6611 controller provides features that make it the best choice for bridging between the PCI bus and PC Cards,
and supports Smart Card, Flash Media, 16-bit, CardBus or USB custom card interface PC Cards, powered at 5 V
or 3.3 V, as required.
All card signals are internally buffered to allow hot insertion and removal without external buffering. The PCI6611
controller is register compatible with the Intel 82365SL-DF ExCA controller. The PCI6611 internal data path logic
allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance. Independent
buffering and a pipeline architecture provide an unsurpassed performance level with sustained bursting. The
PCI6611 controller can be programmed to accept posted writes to improve bus utilization.
Function 3 of the PCI6611 controller is a PCI-based Flash Media controller that supports Memory Stick, Memory
Stick-Pro, SmartMedia, XD, SD, and MMC cards. This function controls communication with these Flash Media cards
through a passive PC Card adapter or through a dedicated Flash Media socket. In addition, this function includes D MA
capabilities for improved Flash Media performance.
Function 4 o f the PCI6611 controller is a PCI-based SD host controller that supports MMC, SD, and SDIO cards. This
function controls communication with these Flash Media cards through a passive PC Card adapter or through a
dedicated Flash Media socket. In addition, this function is compliant with the SD Host Controller Standard
Specification and includes both DMA capabilities and support for SD suspend/resume.
Function 5 o f the PCI6611 controller is a PCI-based Smart Card controller used for communication with Smart Cards
inserted in P C Card adapters. Utilizing Smart Card technology from Gemplus, this function provides compatibility with
many different types of Smart Cards.
1.1.4 PCI6411 Controller
The PCI6411 controller is a three-function PCI controller compliant with PCI Local Bus Specification, Revision 2.3.
Function 0 provides an independent PC Card socket controller compliant with the PC Card Standard (Release 8.1).
The PCI6411 controller provides features that make it the best choice for bridging between the PCI bus and PC Cards,
and supports Smart Card, Flash Media, 16-bit, CardBus or USB custom card interface PC Cards, powered at 5 V
or 3.3 V, as required.
1−3
All card signals are internally buffered to allow hot insertion and removal without external buffering. The PCI6411
controller is register compatible with the Intel 82365SL-DF ExCA controller. The PCI6411 internal data path logic
allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance. Independent
buffering and a pipeline architecture provide an unsurpassed performance level with sustained bursting. The
PCI6411 controller can be programmed to accept posted writes to improve bus utilization.
Function 3 of the PCI6411 controller is a PCI-based Flash Media controller that supports Memory Stick, Memory
Stick-Pro, SmartMedia, XD, SD, and MMC cards. This function controls communication with these Flash Media cards
through a passive PC Card adapter or through a dedicated Flash Media socket. In addition, this function includes D MA
capabilities for improved Flash Media performance.
Function 4 o f the PCI6411 controller is a PCI-based SD host controller that supports MMC, SD, and SDIO cards. This
function controls communication with these Flash Media cards through a passive PC Card adapter or through a
dedicated Flash Media socket. In addition, this function is compliant with the SD Host Controller Standard
Specification and includes both DMA capabilities and support for SD suspend/resume.
1.1.5 Multifunctional Terminals
Various implementation-specific functions and general-purpose inputs and outputs are provided through eight
multifunction terminals. These terminals present a system with options in PC/PCI DMA, PCI LOCK , serial and parallel
interrupts, PC Card activity indicator LEDs, flash media LEDs, and other platform-specific signals. PCI complaint
general-purpose events may be programmed and controlled through the multifunction terminals, and an
ACPI-compliant programming interface is included for the general-purpose inputs and outputs.
1.1.6 PCI Bus Power Management
The PCI6x21/PCI6x11 controller is compliant with the latest PCI Bus Power Management Specification, and provides
several low-power modes, which enable the host power system to further reduce power consumption.
1.1.7 Power Switch Interface
The PCI6x21/PCI6x11 controller also has a three-pin serial interface compatible with the Texas Instruments TPS2228
(default), TPS2226, TPS2224, and TPS2223A power switches. All three power switches provide power to the
CardBus socket(s) on the PCI6x21/PCI6x11 controller. The power to each dedicated socket is controlled through
separate power control pins. Each of these power control pins can be connected to an external 3.3-V power switch.
1.2 Features
The PCI6x21/PCI6x11 controller supports the following features:
•PC Card Standard 8.1 compliant
•PCI Bus Power Management Interface Specification 1.1 compliant
•Advanced Configuration and Power Interface (ACPI) Specification 2.0 compliant
•PCI Local Bus Specification Revision 2.3 compliant
•PC 98/99 and PC2001 compliant
•Windows Logo Program 2.0 compliant
•PCI Bus Interface Specification for PCI-to-CardBus Bridges
•1.5-V core logic and 3.3-V I/O cells with internal voltage regulator to generate 1.5-V core VCC
•Universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling environments
•Supports PC Card or CardBus with hot insertion and removal
•Supports 132-MBps burst transfers to maximize data throughput on both the PCI bus and the CardBus
1−4
•Supports serialized IRQ with PCI interrupts
•Programmable multifunction terminals
•Many interrupt modes supported
•Serial ROM interface for loading subsystem ID and subsystem vendor ID
•ExCA-compatible registers are mapped in memory or I/O space
•Intel 82365SL-DF register compatible
•Supports ring indicate, SUSPEND, and PCI CLKRUN protocols and PCI bus Lock (LOCK)
•Provides VGA/palette memory and I/O, and subtractive decoding options, LED activity terminals
•Compliant with Intel Mobile Power Guideline 2000
•Power-down features to conserve energy in battery-powered applications include: automatic device power
down during suspend
•PCI power-management D0, D1, D2, and D3 power states
•Advanced submicron, low-power CMOS technology
1.3 Related Documents
•Advanced Configuration and Power Interface (ACPI) Specification (Revision 2.0)
•PC Card Standard (Release 8.1)
•PCI Bus Power Management Interface Specification (Revision 1.1)
•Serial Bus Protocol 2 (SBP-2)
•Serialized IRQ Support for PCI Systems
•PCI Mobile Design Guide
•PCI Bus Power Management Interface Specification for PCI to CardBus Bridges
•PCI14xx Implementation Guide for D3 Wake-Up
•PCI to PCMCIA CardBus Bridge Register Description
•Texas Instruments TPS2224 and TPS2226 product data sheet, SLVS317
•Texas Instruments TPS2223A product data sheet, SLVS428
•Texas Instruments TPS2228 product data sheet, SLVS419
•PCI Local Bus Specification (Revision 2.3)
•PCMCIA Proposal (262)
•The Multimedia Card System Specification, Version 3.31
•SD Memory Card Specifications, SD Group, March 2000
•Memory Stick Format Specification, Version 2.0 (Memory Stick-Pro)
•ISO Standards for Identification Cards ISO/IEC 7816
•SD Host Controller Standard Specification, rev. 1.0
•Memory Stick Format Specification, Sony Confidential, ver. 2.0
•SmartMedia Standard 2000, May 19, 2000
1−5
1.4 Trademarks
Intel is a trademark of Intel Corporation.
TI and MicroStar BGA are trademarks of Texas Instruments.
i.LINK is a trademark of Sony Corporation of America.
Memory Stick is a trademark of Sony Kabushiki Kaisha TA Sony Corporation, Japan.
Other trademarks are the property of their respective owners.
1.5 Terms and Definitions
Terms and definitions used in this document are given in Table 1−1.
Table 1−1. Terms and Definitions
TERM DEFINITIONS
AT AT (advanced technology, as in PC AT) attachment interface
ATA driver An existing host software component that loads when any flash media adapter and card is inserted into a PC Card
socket. This driver is logically attached to a predefined CIS provided by the PCI6x21/PCI6x11 controller when the
adapter and media are both inserted.
CIS Card information structure. Tuple list defined by the PC Card standard to communicate card information to the host
computer
CSR Control and status register
Flash Media SmartMedia, Memory Stick, MS/PRO, xD, MMC, or SD/MMC Flash operating in an ATA compatible mode
ISO/IEC 7816 The Smart Card standard
Memory StickA small-form-factor flash interface that is defined, promoted, and licensed by Sony
Memory Stick ProMemory Stick Version 2.0, same physical dimensions of MS with higher speed data exchange and higher data
capacity than conventional Memory Stick.
MMC MultiMediaCard. Specified by the MMC Association, and scope is encompassed by the SD Flash specification.
PCMCIA Personal Computer Memory Card International Association. Standards body that governs the PC Card standards
RSVD Reserved for future use
SD Flash Secure Digital Flash. Standard governed by the SD Association
Smart Card The name applied to ID cards containing integrated circuits, as defined by ISO/IEC 7816-1
SPI Serial peripheral interface, a general-purpose synchronous serial interface. For more information, see the
Multimedia Card System Specification, version 3.2.
SSFDC Solid State Floppy Disk Card. The SSFDC Forum specifies SmartMedia
TI Smart Card driver A qualified software component provided by Texas Instruments that loads when an UltraMedia-based Smart Card
adapter is inserted into a PC Card slot. This driver is logically attached to a CIS provided by the PCI6621 when the
adapter and media are both inserted.
UltraMediaDe facto industry standard promoted by Texas Instruments that integrates CardBus, Smart Card, Memory Stick,
MultiMediaCard/Secure Digital and SmartMedia functionality into one controller.
xD Extreme Digital, small form factor flash based on SmartMedia cards, developed by Fuji Film and Olympus Optical.
1.6 Ordering Information
ORDERING NUMBER NAME VOLTAGE PACKAGE
PCI6621 Dual Socket CardBus and UltraMedia Controller with
Dedicated Flash Media Socket 3.3-V, 5-V tolerant I/Os 288-ball PBGA
(GHK or ZHK)
PCI6421 Dual Socket CardBus and UltraMedia Controller with
Dedicated Flash Media Socket 3.3-V, 5-V tolerant I/Os 288-ball PBGA
(GHK or ZHK)
PCI6611 Single Socket CardBus and UltraMedia Controller with
Dedicated Flash Media Socket 3.3-V, 5-V tolerant I/Os 288-ball PBGA
(GHK or ZHK)
PCI6411 Single Socket CardBus and UltraMedia Controller with
Dedicated Flash Media Socket 3.3-V, 5-V tolerant I/Os 288-ball PBGA
(GHK or ZHK)
1−6
2−1
2 Terminal Descriptions
The PCI6x21/PCI6x11 controller is available in the 288-terminal MicroStar BGA package (GHK) or the 288-terminal
lead-free (Pb, atomic number 82) MicroStar BGA package (ZHK). Figure 2−1 is a pin diagram of the PCI6621
package. Figure 2−2 is a pin diagram of the PCI6421 package. Figure 2−3 is a pin diagram of the PCI6611 package.
Figure 2−4 is a pin diagram of the PCI6411 package.
W
P
D
A
R
T
U
V
M
N
K
L
H
J
F
G
E
B
C
19151051 14131211 169876432 17 18
A_CINT//
A_READY
(IREQ)
A_CAD25
//A_A1 VCCA
A_CAD21
//A_A5
A_CAD19
//A_A25
A_CC/BE2
//A_A12
A_CDEVSEL
//A_A21
A_CPAR
//A_A13
VCCA
A_CAD11
//A_OE
A_CAD8
//A_D15
A_RSVD
//A_D14
A_CAD3
//A_D5 A_CAD0
//A_D3
B_CAD30
//B_D9
B_CAD27
//B_D0
B_CSTSCHG
//B_BVD1
(STSCHG/RI)
A_CAUDIO
//A_BVD2
(SPKR)
A_CSERR
//A_WAIT A_CAD26
//A_A0
A_CC/BE3
//A_REG A_CAD22
//A_A4
A_CAD20
//A_A6
A_CAD17
//A_A24
A_CCLK
//A_A16 A_CBLOCK
//A_A19
A_CAD16
//A_A17
A_CAD12
//A_A11
A_CC/BE0
//A_CE1
A_CAD6
//A_D13
A_CAD4
//A_D12 A_CCD1
//A_CD1
B_CAD28
//B_D8
B_CCLKRUN
//B_WP
(IOIS16)
B_CSERR
//B_WAIT
B_CINT
//B_READY
(IREQ)
A_CCD2
//A_CD2
A_CCLKRUN
//A_WP
(IOIS16)
A_CSTSCHG
//A_BVD1
(STSCHG/RI)
A_CVS1
//A_VS1
A_CAD23
//A_A3
A_CRST
//A_RESET
A_CAD18
//A_A7
A_CTRDY
//A_A22
A_CPERR
//A_A14
A_CC/BE1
//A_A8
A_CAD13
//A_IORD
A_CAD9
//A_A10 A_CAD5
//A_D6 A_CAD2
//A_D11 B_RSVD
//B_D2
B_CCD2
//B_CD2
B_CAUDIO
//B_BVD2
(SPKR)
B_CVS1
//B_VS1
B_CAD24
//B_A2
A_CAD30
//A_D9
A_CAD29
//A_D1
A_CAD28
//A_D8 B_CAD25
//B_A1
B_CC/BE3
//B_REG
VCCB
B_USB_EN
A_CAD31
//A_D10
A_CAD27
//A_D0
A_CAD24
//A_A2 A_CVS2
//A_VS2
A_CFRAME
//A_A23
A_CGNT
//A_WE
A_RSVD
//A_A18
A_CAD10
//A_CE2
A_CAD7
//A_D7
B_CAD31
//B_D10 B_CAD29
//B_D1
B_CREQ
//B_INPACK B_CAD22
//B_A4
B_CRST
//B_RESET
MS_BS//
SD_CMD
//SM_WE
A_RSVD
//A_D2
A_CREQ
//A_INPACK
A_CIRDY
//A_A15
A_CAD14
//A_A9
A_CAD1
//A_D4
B_CAD26
//B_A0
B_CAD23
//B_A3
B_CAD20
//B_A6 B_CVS2
//B_VS2
B_CAD18
//B_A7
MS_DATA1
//SD_DAT1
//SM_D1
MS_CLK//
SD_CLK//
SM_EL_WP
VCC
VCC
A_CSTOP
//A_A20
A_CAD15
//A_IOWR
VCC
VCC
VCC
B_CAD21
//B_A5 B_CC/BE2
//B_A12 B_CFRAME
//B_A23
B_CIRDY
//B_A15
SD_CLK//
SM_RE//
SC_GPIO1
SD_CMD//
SM_ALE//
SC_GPIO2
SM_R/B
//
SC_RFU
GND GND
VCC
GND
VCC B_CTRDY
//B_A22
B_CAD19
//B_A25
B_CAD17
//B_A24
B_CCLK
//B_A16
B_CDEVSEL
//B_A21
B_CGNT
//B_WE
SD_DAT2
//SM_D6//
SC_GPIO4
SD_WP//
SM_CE
SC_RST
SM_ PHYS
_WP//
SC_FCB
VCC
GND
GND GND
GND
B_CPERR
//B_A14
B_CSTOP
//B_A20 B_CBLOCK
//B_A19
B_CPAR
//B_A13
VR_
PORT
SC_
VCC_
5V
SC_CLK
VR_
PORT
SCL
VCC
GND
GND GND VCC
B_CAD15
//B_IOWR
B_CAD14
//B_A9
B_RSVD
//B_A18
B_CC/BE1
//B_A8 B_CAD16
//B_A17 VCCB
VR_EN
CLK_48 SDA
CLOCK
MFUNC1
SPKROUT GND GND GND GND GND
B_CAD7
//B_D7
B_CAD10
//B_CE2
B_CAD13
//B_IORD B_CAD12
//B_A11 B_CAD11
//B_OE
DATA LATCH MFUNC0 MFUNC5
VCC GND
NC
AGND
VCC
TEST0
VCC
B_CAD4
//B_D12
B_CAD3
//B_D5 B_CC/BE0
//B_CE1
B_CAD9
//B_A10
B_CAD8
//B_D15
MFUNC2 MFUNC4MFUNC3
GRST
AD17
VCC
PAR
AD12
AD2
RSVD
SC_CD
B_CCD1
//B_CD1 B_CAD6
//B_D13
B_CAD5
//B_D6
B_RSVD
//B_D14
MFUNC6 SUSPEND PRST
AD30 AD26
C/BE1
RSVD
SC_OC
RSVD
B_CAD0
//B_D3
B_CAD2
//B_D11
B_CAD1
//B_D4
PCLK
GNT RI_OUT
//PME
AD21
C/BE2
DEVSEL
AD11
AD6
AD1
AVDD
AGND
SC_
PWR_
CTRL
PHY_
TEST_
MA
RSVD
REQ AD31
AD27
VSSPLL
RSVD RSVD
AD29
AD28
AD24
AD22
AD18
IRDY
PERR
AD14
VDPLL_
33
C/BE0
AD3
RSVD
VSSPLL
RSVD
AVDD
SC_
DATA
VDPLL_
15
VCCP
AD25
IDSEL
AD20
AD16 TRDY
SERR
AD13
AD10
AD8
AD4
RSVD RSVD RSVD
RSVD
RSVD AVDD RSVD
RSVD
C/BE3
AD23
AD19
FRAME
STOP
AD15
VCCP
AD9
AD7
AD5
AD0 RSVD RSVD
RSVD
RSVD
AGND
RSVD
MC_PWR
_CTRL_0
MS_SDIO
(DATA0)//
SD_DAT0//
SM_D0
SM_CLE//
SC_GPIO0
A_USB_EN
MC_PWR
_CTRL_1
MS_DATA2
//SD_DAT2
//SM_D2
SD_DAT0//
SM_D4//
SC_GPIO6
MS_DATA3
//SD_DAT3
//SM_D3
SD_DAT3
//SM_D7//
SC_GPIO3
SD_DAT1//
SM_D5//
SC_GPIO5
SD_CD
MS_CD SM_CD
Figure 2−1. PCI6621 GHK/ZHK-Package Terminal Diagram
2−2
B_CCLKRUN
//B_WP
(IOIS16)
W
P
D
A
R
T
U
V
M
N
K
L
H
J
F
G
E
B
C
19151051 14131211 169876432 17 18
A_CINT//
A_READY
(IREQ)
A_CAD25
//A_A1 VCCA
A_CAD21
//A_A5
A_CAD19
//A_A25
A_CC/BE2
//A_A12
A_CDEVSEL
//A_A21
A_CPAR
//A_A13
VCCA
A_CAD11
//A_OE
A_CAD8
//A_D15
A_RSVD
//A_D14
A_CAD3
//A_D5 A_CAD0
//A_D3
B_CAD30
//B_D9
B_CAD27
//B_D0
B_CSTSCHG
//B_BVD1
(STSCHG/RI)
A_CAUDIO
//A_BVD2
(SPKR)
A_CSERR
//A_WAIT A_CAD26
//A_A0
A_CC/BE3
//A_REG A_CAD22
//A_A4
A_CAD20
//A_A6
A_CAD17
//A_A24
A_CCLK
//A_A16 A_CBLOCK
//A_A19
A_CAD16
//A_A17
A_CAD12
//A_A11
A_CC/BE0
//A_CE1
A_CAD6
//A_D13
A_CAD4
//A_D12 A_CCD1
//A_CD1
B_CAD28
//B_D8
B_CSERR
//B_WAIT
B_CINT
//B_READY
(IREQ)
A_CCD2
//A_CD2
A_CCLKRUN
//A_WP
(IOIS16)
A_CSTSCHG
//A_BVD1
(STSCHG/RI)
A_CVS1
//A_VS1
A_CAD23
//A_A3
A_CRST
//A_RESET
A_CAD18
//A_A7
A_CTRDY
//A_A22
A_CPERR
//A_A14
A_CC/BE1
//A_A8
A_CAD13
//A_IORD
A_CAD9
//A_A10 A_CAD5
//A_D6 A_CAD2
//A_D11 B_RSVD
//B_D2
B_CCD2
//B_CD2
B_CAUDIO
//B_BVD2
(SPKR)
B_CVS1
//B_VS1
B_CAD24
//B_A2
A_CAD30
//A_D9
A_CAD29
//A_D1
A_CAD28
//A_D8 B_CAD25
//B_A1
B_CC/BE3
//B_REG
VCCB
B_USB_EN
A_CAD31
//A_D10
A_CAD27
//A_D0
A_CAD24
//A_A2 A_CVS2
//A_VS2
A_CFRAME
//A_A23
A_CGNT
//A_WE
A_RSVD
//A_A18
A_CAD10
//A_CE2
A_CAD7
//A_D7
B_CAD31
//B_D10 B_CAD29
//B_D1
B_CREQ
//B_INPACK B_CAD22
//B_A4
B_CRST
//B_RESET
MS_BS//
SD_CMD
//SM_WE
A_RSVD
//A_D2
A_CREQ
//A_INPACK
A_CIRDY
//A_A15
A_CAD14
//A_A9
A_CAD1
//A_D4
B_CAD26
//B_A0
B_CAD23
//B_A3
B_CAD20
//B_A6 B_CVS2
//B_VS2
B_CAD18
//B_A7
MS_DATA1
//SD_DAT1
//SM_D1
MS_CLK//
SD_CLK//
SM_EL_WP
VCC
VCC
A_CSTOP
//A_A20
A_CAD15
//A_IOWR
VCC
VCC
VCC
B_CAD21
//B_A5 B_CC/BE2
//B_A12 B_CFRAME
//B_A23
B_CIRDY
//B_A15
SD_CLK
//SM_RE
SD_CMD//
SM_ALE
SM_R/B
GND GND
VCC
GND
VCC B_CTRDY
//B_A22
B_CAD19
//B_A25
B_CAD17
//B_A24
B_CCLK
//B_A16
B_CDEVSEL
//B_A21
B_CGNT
//B_WE
SD_DAT2
//SM_D6
SD_WP//
SM_CE
RSVD
SM_PHYS
_WP
VCC
GND
GND GND
GND
B_CPERR
//B_A14
B_CSTOP
//B_A20 B_CBLOCK
//B_A19
B_CPAR
//B_A13
VR_
PORT
RSVD
RSVD
VR_
PORT
SCL
VCC
GND
GND GND VCC
B_CAD15
//B_IOWR
B_CAD14
//B_A9
B_RSVD
//B_A18
B_CC/BE1
//B_A8 B_CAD16
//B_A17 VCCB
VR_EN
CLK_48 SDA
CLOCK
MFUNC1
SPKROUT GND GND GND GND GND
B_CAD7
//B_D7
B_CAD10
//B_CE2
B_CAD13
//B_IORD B_CAD12
//B_A11 B_CAD11
//B_OE
DATA LATCH MFUNC0 MFUNC5
VCC GND
NC
AGND
VCC
TEST0
VCC
B_CAD4
//B_D12
B_CAD3
//B_D5 B_CC/BE0
//B_CE1
B_CAD9
//B_A10
B_CAD8
//B_D15
MFUNC2 MFUNC4MFUNC3
GRST
AD17
VCC
PAR
AD12
AD2
RSVD
RSVD
B_CCD1
//B_CD1 B_CAD6
//B_D13
B_CAD5
//B_D6
B_RSVD
//B_D14
MFUNC6 SUSPEND PRST
AD30 AD26
C/BE1
RSVD
RSVD
RSVD
B_CAD0
//B_D3
B_CAD2
//B_D11
B_CAD1
//B_D4
PCLK
GNT RI_OUT
//PME
AD21
C/BE2
DEVSEL
AD11
AD6
AD1
AVDD
AGND
RSVD
PHY_
TEST_
MA
RSVD
REQ AD31
AD27
VSSPLL
RSVD RSVD
AD29
AD28
AD24
AD22
AD18
IRDY
PERR
AD14
VDPLL
_33
C/BE0
AD3
RSVD
VSSPLL
RSVD
AVDD
RSVD
VDPLL
_15
VCCP
AD25
IDSEL
AD20
AD16 TRDY
SERR
AD13
AD10
AD8
AD4
RSVD RSVD RSVD
RSVD
RSVD AVDD RSVD
RSVD
C/BE3
AD23
AD19
FRAME
STOP
AD15
VCCP
AD9
AD7
AD5
AD0 RSVD RSVD
RSVD
RSVD
AGND
RSVD
MC_PWR
_CTRL_0
MS_SDIO
(DATA0)//
SD_DAT0//
SM_D0
SM_CLE
A_USB_EN
MC_PWR
_CTRL_1
MS_DATA2
//SD_DAT2
//SM_D2
SD_DAT0//
SM_D4
MS_DATA3//
SD_DAT3
//SM_D3
SD_DAT3
//SM_D7 SD_DAT1
//SM_D5
SD_CD
MS_CD SM_CD
Figure 2−2. PCI6421 GHK/ZHK-Package Terminal Diagram
2−3
W
P
D
A
R
T
U
V
M
N
K
L
H
J
F
G
E
B
C
19151051 14131211 169876432 17 18
A_CINT//
A_READY
(IREQ)
A_CAD25
//A_A1 VCCA
A_CAD21
//A_A5
A_CAD19
//A_A25
A_CC/BE2
//A_A12
A_CDEVSEL
//A_A21
A_CPAR
//A_A13
VCCA
A_CAD11
//A_OE
A_CAD8
//A_D15
A_RSVD
//A_D14
A_CAD3
//A_D5 A_CAD0
//A_D3
A_CAUDIO
//A_BVD2
(SPKR)
A_CSERR
//A_WAIT A_CAD26
//A_A0
A_CC/BE3
//A_REG A_CAD22
//A_A4
A_CAD20
//A_A6
A_CAD17
//A_A24
A_CCLK
//A_A16 A_CBLOCK
//A_A19
A_CAD16
//A_A17
A_CAD12
//A_A11
A_CC/BE0
//A_CE1
A_CAD6
//A_D13
A_CAD4
//A_D12 A_CCD1
//A_CD1
A_CCD2
//A_CD2
A_CCLKRUN
//A_WP
(IOIS16)
A_CSTSCHG
//A_BVD1
(STSCHG/RI)
A_CVS1
//A_VS1
A_CAD23
//A_A3
A_CRST
//A_RESET
A_CAD18
//A_A7
A_CTRDY
//A_A22
A_CPERR
//A_A14
A_CC/BE1
//A_A8
A_CAD13
//A_IORD
A_CAD9
//A_A10 A_CAD5
//A_D6 A_CAD2
//A_D11 RSVD
A_CAD30
//A_D9
A_CAD29
//A_D1
A_CAD28
//A_D8
B_USB_EN
A_CAD31
//A_D10
A_CAD27
//A_D0
A_CAD24
//A_A2 A_CVS2
//A_VS2
A_CFRAME
//A_A23
A_CGNT
//A_WE
A_RSVD
//A_A18
A_CAD10
//A_CE2
A_CAD7
//A_D7
MS_BS//
SD_CMD
//SM_WE
A_RSVD
//A_D2
A_CREQ
//A_INPACK
A_CIRDY
//A_A15
A_CAD14
//A_A9
A_CAD1
//A_D4
MS_DATA1
//SD_DAT1
//SM_D1
MS_CLK//
SD_CLK//
SM_EL_WP
VCC
VCC
A_CSTOP
//A_A20
A_CAD15
//A_IOWR
VCC
VCC
VCC
SD_CLK//
SM_RE//
SC_GPIO1
SD_CMD//
SM_ALE//
SC_GPIO2
SM_R/B
//SC_RFU
GND GND
VCC
GND
VCC
SD_DAT2
//SM_D6//
SC_GPIO4
SD_WP//
SM_CE
SC_RST
SM_
PHYS_WP
// SC_FCB
VCC
GND
GND GND
GND
VR_
PORT
SC_
VCC_
5V
SC_CLK
VR_
PORT
SCL
VCC
GND
GND GND VCC
VR_EN
CLK_48 SDA
CLOCK
MFUNC1
SPKROUT GND GND GND GND GND
DATA LATCH MFUNC0 MFUNC5
VCC GND
NC
AGND
VCC
TEST0
VCC
MFUNC2 MFUNC4MFUNC3
GRST
AD17
VCC
PAR
AD12
AD2
RSVD
SC_CD
MFUNC6 SUSPEND PRST
AD30 AD26
C/BE1
RSVD
SC_OC
RSVD
PCLK
GNT RI_OUT
//PME
AD21
C/BE2
DEVSEL
AD11
AD6
AD1
AVDD
AGND
SC_
PWR_
CTRL
PHY_
TEST_
MA
RSVD
REQ AD31
AD27
VSSPLL
RSVD RSVD
AD29
AD28
AD24
AD22
AD18
IRDY
PERR
AD14
VDPLL
_33
C/BE0
AD3
RSVD
VSSPLL
RSVD
AVDD
SC_
DATA
VDPLL
_15
VCCP
AD25
IDSEL
AD20
AD16 TRDY
SERR
AD13
AD10
AD8
AD4
RSVD RSVD RSVD
RSVD
RSVD AVDD RSVD
RSVD
C/BE3
AD23
AD19
FRAME
STOP
AD15
VCCP
AD9
AD7
AD5
AD0 RSVD RSVD
RSVD
RSVD
AGND
RSVD
MC_PWR
_CTRL_0
MS_SDIO
(DATA0)//
SD_DAT0//
SM_D0
SM_CLE //
SC_GPIO0
A_USB_EN
MC_PWR
_CTRL_1
MS_DATA2
//SD_DAT2
//SM_D2
SD_DAT0//
SM_D4//
SC_GPIO6
MS_DATA3//
SD_DAT3
//SM_D3
SD_DAT3
//SM_D7//
SC_GPIO3
SD_DAT1//
SM_D5//
SC_GPIO5
SD_CD
MS_CD SM_CD
RSVD RSVD RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD RSVD
RSVD RSVD
RSVD
RSVD
RSVD RSVD RSVD
RSVD RSVD RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD RSVD
RSVD
RSVDRSVD
RSVDRSVD
RSVD
Figure 2−3. PCI6611 GHK/ZHK-Package Terminal Diagram
2−4
W
P
D
A
R
T
U
V
M
N
K
L
H
J
F
G
E
B
C
19151051 14131211 169876432 17 18
A_CINT//
A_READY
(IREQ)
A_CAD25
//A_A1 VCCA
A_CAD21
//A_A5
A_CAD19
//A_A25
A_CC/BE2
//A_A12
A_CDEVSEL
//A_A21
A_CPAR
//A_A13
VCCA
A_CAD11
//A_OE
A_CAD8
//A_D15
A_RSVD
//A_D14
A_CAD3
//A_D5 A_CAD0
//A_D3
A_CAUDIO
//A_BVD2
(SPKR)
A_CSERR
//A_WAIT A_CAD26
//A_A0
A_CC/BE3
//A_REG A_CAD22
//A_A4
A_CAD20
//A_A6
A_CAD17
//A_A24
A_CCLK
//A_A16 A_CBLOCK
//A_A19
A_CAD16
//A_A17
A_CAD12
//A_A11
A_CC/BE0
//A_CE1
A_CAD6
//A_D13
A_CAD4
//A_D12 A_CCD1
//A_CD1
A_CCD2
//A_CD2
A_CCLKRUN
//A_WP
(IOIS16)
A_CSTSCHG
//A_BVD1
(STSCHG/RI)
A_CVS1
//A_VS1
A_CAD23
//A_A3
A_CRST
//A_RESET
A_CAD18
//A_A7
A_CTRDY
//A_A22
A_CPERR
//A_A14
A_CC/BE1
//A_A8
A_CAD13
//A_IORD
A_CAD9
//A_A10 A_CAD5
//A_D6 A_CAD2
//A_D11 RSVD
A_CAD30
//A_D9
A_CAD29
//A_D1
A_CAD28
//A_D8
B_USB_EN
A_CAD31
//A_D10
A_CAD27
//A_D0
A_CAD24
//A_A2 A_CVS2
//A_VS2
A_CFRAME
//A_A23
A_CGNT
//A_WE
A_RSVD
//A_A18
A_CAD10
//A_CE2
A_CAD7
//A_D7
MS_BS//
SD_CMD
//SM_WE
A_RSVD
//A_D2
A_CREQ
//A_INPACK
A_CIRDY
//A_A15
A_CAD14
//A_A9
A_CAD1
//A_D4
MS_DATA1
//SD_DAT1
//SM_D1
MS_CLK//
SD_CLK//
SM_EL_WP
VCC
VCC
A_CSTOP
//A_A20
A_CAD15
//A_IOWR
VCC
VCC
VCC
SD_CLK//
SM_RE
SD_CMD//
SM_ALE
SM_R/B
GND GND
VCC
GND
VCC
SD_DAT2
//SM_D6
SD_WP//
SM_CE
SM_PHYS
_WP
VCC
GND
GND GND
GND
VR_
PORT
VR_
PORT
SCL
VCC
GND
GND GND VCC
VR_EN
CLK_48 SDA
CLOCK
MFUNC1
SPKROUT GND GND GND GND GND
DATA LATCH MFUNC0 MFUNC5
VCC GND
NC
AGND
VCC
TEST0
VCC
MFUNC2 MFUNC4MFUNC3
GRST
AD17
VCC
PAR
AD12
AD2
RSVD
MFUNC6 SUSPEND PRST
AD30 AD26
C/BE1
RSVD
RSVD
PCLK
GNT RI_OUT
//PME
AD21
C/BE2
DEVSEL
AD11
AD6
AD1
AVDD
AGND
PHY_
TEST_
MA
RSVD
REQ AD31
AD27
VSSPLL
RSVD RSVD
AD29
AD28
AD24
AD22
AD18
IRDY
PERR
AD14
VDPLL_
33
C/BE0
AD3
RSVD
VSSPLL
RSVD
AVDD
VDPLL_
15
VCCP
AD25
IDSEL
AD20
AD16 TRDY
SERR
AD13
AD10
AD8
AD4
RSVD RSVD RSVD
RSVD
RSVD AVDD RSVD
RSVD
C/BE3
AD23
AD19
FRAME
STOP
AD15
VCCP
AD9
AD7
AD5
AD0 RSVD RSVD
RSVD
RSVD
AGND
RSVD
MC_PWR
_CTRL_0
MS_SDIO
(DATA0)//
SD_DAT0//
SM_D0
SM_CLE
A_USB_EN
MC_PWR
_CTRL_1
MS_DATA2
//SD_DAT2
//SM_D2
SD_DAT0
//SM_D4
MS_DATA3//
SD_DAT3
//SM_D3
SD_DAT3
//SM_D7
SD_DAT1
//SM_D5
SD_CD
MS_CD SM_CD
RSVD RSVD RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD RSVD
RSVD RSVD
RSVD
RSVD
RSVD RSVD RSVD
RSVD RSVD RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD RSVD
RSVD
RSVDRSVD
RSVDRSVD
RSVD
RSVD
RSVDRSVD RSVD RSVD
RSVD RSVD
Figure 2−4. PCI6411 GHK/ZHK-Package Terminal Diagram
Table 2−1 lists the terminal assignments arranged in terminal-number order, with corresponding signal names for
both CardBus and 16-bit PC Cards for the PCI6421 and PCI6621 GHK packages. Table 2−2 and Table 2−3 list the
terminal assignments arranged in alphanumerical order by signal name, with corresponding terminal numbers for the
GHK package; Table 2−2 is for CardBus signal names and Table 2−3 is for 16-bit PC Card signal names.
Terminal E5 on the GHK package is an identification ball used for device orientation.
2−5
Table 2−1. Signal Names by GHK Terminal Number
TERMINAL
NUMBER
SIGNAL NAME
TERMINAL
NUMBER
SIGNAL NAME
TERMINAL
NUMBER CardBus PC Card 16-Bit PC Card
TERMINAL
NUMBER CardBus PC Card 16-Bit PC Card
A02 A_CAUDIO A_BVD2(SPKR) C06 A_CAD22 A_A4
A03 A_CVS1 A_VS1 C07 A_CAD19 A_A25
A04 A_CAD25 A_A1 C08 A_CFRAME A_A23
A05 VCCA VCCA C09 A_CDEVSEL A_A21
A06 A_CRST A_RESET C10 A_RSVD A_A18
A07 A_CAD17 A_A24 C11 A_CAD13 A_IORD
A08 A_CTRDY A_A22 C12 A_CAD11 A_OE
A09 A_CSTOP A_A20 C13 A_CAD7 A_D7
A10 A_CAD16 A_A17 C14 A_CAD4 A_D12
A11 VCCA VCCA C15 A_CCD1 A_CD1
A12 A_CAD9 A_A10 C16 B_CAD27 B_D0
A13 A_CAD5 A_D6 C17 B_CAUDIO B_BVD2(SPKR)
A14 A_CAD2 A_D11 C18 B_CVS1 B_VS1
A15 B_RSVD B_D2 C19 B_CAD25 B_A1
A16 B_CAD30 B_D9 D01 A_CAD31 A_D10
A17 B_CAD28 B_D8 D02 A_RSVD A_D2
A18 B_CCLKRUN B_WP(IOIS16) D03 A_CAD29 A_D1
B01 A_CAD27 A_D0 D17 B_CAD26 B_A0
B02 A_CSTSCHG A_BVD1(STSCHG/RI) D18 B_CAD24 B_A2
B03 A_CSERR A_WAIT D19 VCCB VCCB
B04 A_CAD26 A_A0 E01 B_USB_EN B_USB_EN
B05 A_CAD23 A_A3 E02 A_USB_EN A_USB_EN
B06 A_CAD21 A_A5 E03 SD_CD SD_CD
B07 A_CAD18 A_A7 E05 A_CCD2 A_CD2
B08 A_CIRDY A_A15 E06 A_CAD24 A_A2
B09 A_CGNT A_WE E07 A_CREQ A_INPACK
B10 A_CC/BE1 A_A8 E08 A_CVS2 A_VS2
B11 A_CAD12 A_A11 E09 A_CCLK A_A16
B12 A_CAD10 A_CE2 E10 A_CBLOCK A_A19
B13 A_RSVD A_D14 E11 A_CAD15 A_IOWR
B14 A_CAD1 A_D4 E12 A_CAD8 A_D15
B15 B_CAD31 B_D10 E13 A_CAD3 A_D5
B16 B_CAD29 B_D1 E14 A_CAD0 A_D3
B17 B_CCD2 B_CD2 E17 B_CAD23 B_A3
B18 B_CSERR B_WAIT E18 B_CREQ B_INPACK
B19 B_CINT B_READY(IREQ) E19 B_CAD22 B_A4
C01 A_CAD30 A_D9 F01 MC_PWR_CTRL_0 MC_PWR_CTRL_0
C02 A_CAD28 A_D8 F02 MC_PWR_CTRL_1 MC_PWR_CTRL_1
C03 A_CCLKRUN A_WP(IOIS16) F03 MS_BS
//SD_CMD
//SM_WE
MS_BS
//SD_CMD
//SM_WE
C04 A_CINT A_READY(IREQ) F05 MC_CD MC_CD
C05 A_CC/BE3 A_REG F06 SM_CD SM_CD
2−6
Table 2−1. Signal Names by GHK Terminal Number (Continued)
TERMINAL
SIGNAL NAME
TERMINAL
SIGNAL NAME
TERMINAL
NUMBER CardBus PC Card 16-Bit PC Card
TERMINAL
NUMBER CardBus PC Card 16-Bit PC Card
F09 A_CC/BE2 A_A12 H09 VCC VCC
F10 A_CPERR A_A14 H10 VCC VCC
F12 A_CAD6 A_D13 H11 VCC VCC
F14 B_CSTSCHG B_BVD1(STSCHG/RI) H12 VCC VCC
F15 B_CC/BE3 B_REG H13 GND GND
F17 B_CRST B_RESET H14 B_CAD19 B_A25
F18 B_CAD20 B_A6 H15 B_CAD18 B_A7
F19 B_CVS2 B_VS2 H17 B_CTRDY B_A22
G01 MS_SDIO(DATA0)
//SD_DAT0
//SM_D0
MS_SDIO(DATA0)
//SD_DAT0
//SM_D0
H18 B_CCLK B_A16
G02 MS_DATA1
//SD_DAT1
//SM_D1
MS_DATA1
//SD_DAT1
//SM_D1
H19 B_CDEVSEL B_A21
G03 MS_DATA2
//SD_DAT2
//SM_D2
MS_DATA2
//SD_DAT2
//SM_D2
J01 SD_DAT2
//SM_D6
//SC_GPIO4
SD_DAT2
//SM_D6
//SC_GPIO4
G05 MS_CLK
//SD_CLK
//SM_EL_WP
MS_CLK
//SD_CLK
//SM_EL_WP
J02 SD_DAT3
//SM_D7
//SC_GPIO3
SD_DAT3
//SM_D7
//SC_GPIO3
G07 GND GND J03 SD_CMD
//SM_ALE
//SC_GPIO2
SD_CMD
//SM_ALE
//SC_GPIO2
G08 GND GND J05 SD_CLK
//SM_RE
//SC_GPIO1
SD_CLK
//SM_RE
//SC_GPIO1
G09 A_CAD20 A_A6 J06 SD_DAT1
//SM_D5
//SC_GPIO5
SD_DAT1
//SM_D5
//SC_GPIO5
G10 A_CPAR A_A13 J07 SM_CLE
//SC_GPIO0 SM_CLE
//SC_GPIO0
G11 A_CAD14 A_A9 J08 VCC VCC
G12 A_CC/BE0 A_CE1 J09 GND GND
G13 GND GND J10 GND GND
G15 B_CAD21 B_A5 J11 GND GND
G17 B_CAD17 B_A24 J12 VCC VCC
G18 B_CC/BE2 B_A12 J13 B_CIRDY B_A15
G19 B_CFRAME B_A23 J15 B_CGNT B_WE
H01 VR_PORT VR_PORT J17 B_CSTOP B_A20
H02 VR_EN VR_EN J18 B_CPERR B_A14
H03 SD_DAT0
//SM_D4
//SC_GPIO6
SD_DAT0
//SM_D4
//SC_GPIO6
J19 B_CBLOCK B_A19
H05 MS_DATA3
//SD_DAT3
//SM_D3
MS_DATA3
//SD_DAT3
//SM_D3
K01 SM_R/B
//SC_RFU SM_R/B
//SC_RFU
H07 SD_WP
//SM_CE SD_WP
//SM_CE K02 SM_PHYS_WP
//SC_FCB SM_PHYS_WP
//SC_FCB
H08 VCC VCC K03 SC_RST SC_RST
2−7
Table 2−1. Signal Names by GHK Terminal Number (Continued)
TERMINAL
SIGNAL NAME
TERMINAL
SIGNAL NAME
TERMINAL
NUMBER CardBus PC Card 16-Bit PC Card
TERMINAL
NUMBER CardBus PC Card 16-Bit PC Card
K05 SC_CLK SC_CLK M18 B_CC/BE0 B_CE1
K07 SC_VCC_5V SC_VCC_5V M19 VR_PORT VR_PORT
K08 VCC VCC N01 DATA DATA
K09 GND GND N02 LATCH LATCH
K10 GND GND N03 MFUNC0 MFUNC0
K11 GND GND N05 MFUNC5 MFUNC5
K12 VCC VCC N07 VCC VCC
K13 B_CPAR B_A13 N08 DEVSEL DEVSEL
K14 B_CC/BE1 B_A8 N09 AD12 AD12
K15 B_RSVD B_A18 N10 AD8 AD8
K17 B_CAD16 B_A17 N11 AD1 AD1
K18 B_CAD14 B_A9 N12 AGND AGND
K19 VCCB VCCB N13 B_CCD1 B_CD1
L01 SC_DATA SC_DATA N15 B_CAD4 B_D12
L02 SC_CD SC_CD N17 B_RSVD B_D14
L03 SC_OC SC_OC N18 B_CAD5 B_D6
L05 SC_PWR_CTRL SC_PWR_CTRL N19 B_CAD6 B_D13
L06 CLOCK CLOCK P01 MFUNC2 MFUNC2
L07 SPKROUT SPKROUT P02 MFUNC3 MFUNC3
L08 GND GND P03 MFUNC4 MFUNC4
L09 GND GND P05 PCLK PCLK
L10 GND GND P06 AD20 AD20
L11 GND GND P09 PAR PAR
L12 GND GND P12 TEST0 TEST0
L13 B_CAD15 B_IOWR P14 VSSPLL VSSPLL
L15 B_CAD13 B_IORD P15 RSVD RSVD
L17 B_CAD12 B_A11 P17 B_CAD1 B_D4
L18 B_CAD11 B_OE P18 B_CAD2 B_D11
L19 B_CAD10 B_CE2 P19 B_CAD0 B_D3
M01 CLK_48 CLK_48 R01 MFUNC6 MFUNC6
M02 SDA SDA R02 SUSPEND SUSPEND
M03 SCL SCL R03 PRST PRST
M05 MFUNC1 MFUNC1 R06 AD21 AD21
M07 VCC VCC R07 AD16 AD16
M08 GND GND R08 TRDY TRDY
M09 VCC VCC R09 AD13 AD13
M10 VCC VCC R10 AD9 AD9
M11 RSVD RSVD R11 AD5 AD5
M12 VCC VCC R12 RSVD RSVD
M13 B_CAD3 B_D5 R13 AVDD AVDD
M14 B_CAD8 B_D15 R14 AVDD AVDD
M15 B_CAD7 B_D7 R17 PHY_TEST_MA PHY_TEST_MA
M17 B_CAD9 B_A10 R18 RSVD RSVD
2−8
Table 2−1. Signal Names by GHK Terminal Number (Continued)
TERMINAL
SIGNAL NAME
TERMINAL
SIGNAL NAME
TERMINAL
NUMBER CardBus PC Card 16-Bit PC Card
TERMINAL
NUMBER CardBus PC Card 16-Bit PC Card
R19 RSVD RSVD V06 AD18 AD18
T01 GRST GRST V07 FRAME FRAME
T02 GNT GNT V08 PERR PERR
T03 RI_OUT/PME RI_OUT/PME V09 AD15 AD15
T17 VSSPLL VSSPLL V10 AD11 AD11
T18 VDPLL_15 VDPLL_15 V11 AD7 AD7
T19 RSVD RSVD V12 AD3 AD3
U01 REQ REQ V13 RSVD RSVD
U02 AD31 AD31 V14 RSVD RSVD
U03 AD28 AD28 V15 RSVD RSVD
U04 AD25 AD25 V16 RSVD RSVD
U05 AD22 AD22 V17 AVDD AVDD
U06 AD17 AD17 V18 RSVD RSVD
U07 IRDY IRDY V19 VDPLL_33 VDPLL_33
U08 SERR SERR W02 AD27 AD27
U09 AD14 AD14 W03 VCCP VCCP
U10 AD10 AD10 W04 C/BE3 C/BE3
U11 AD6 AD6 W05 IDSEL IDSEL
U12 AD2 AD2 W06 AD19 AD19
U13 RSVD RSVD W07 C/BE2 C/BE2
U14 AGND AGND W08 STOP STOP
U15 RSVD RSVD W09 C/BE1 C/BE1
U16 AGND AGND W10 VCCP VCCP
U17 RSVD RSVD W11 C/BE0 C/BE0
U18 RSVD RSVD W12 AD4 AD4
U19 RSVD RSVD W13 AD0 AD0
V01 AD30 AD30 W14 RSVD RSVD
V02 AD29 AD29 W15 RSVD RSVD
V03 AD26 AD26 W16 RSVD RSVD
V04 AD24 AD24 W17 NC NC
V05 AD23 AD23 W18 RSVD RSVD
2−9
Table 2−2. CardBus PC Card Signal Names Sorted Alphabetically
SIGNAL NAME TERMINAL
NUMBER SIGNAL NAME TERMINAL
NUMBER SIGNAL NAME TERMINAL
NUMBER SIGNAL NAME TERMINAL
NUMBER
AD0 W13 A_CAD5 A13 A_CPERR F10 B_CAD30 A16
AD1 N11 A_CAD6 F12 A_CREQ E07 B_CAD31 B15
AD2 U12 A_CAD7 C13 A_CRST A06 B_CAUDIO C17
AD3 V12 A_CAD8 E12 A_CSERR B03 B_CBLOCK J19
AD4 W12 A_CAD9 A12 A_CSTOP A09 B_CC/BE0 M18
AD5 R11 A_CAD10 B12 A_CSTSCHG B02 B_CC/BE1 K14
AD6 U11 A_CAD11 C12 A_CTRDY A08 B_CC/BE2 G18
AD7 V11 A_CAD12 B11 A_CVS1 A03 B_CC/BE3 F15
AD8 N10 A_CAD13 C11 A_CVS2 E08 B_CCD1 N13
AD9 R10 A_CAD14 G11 A_RSVD B13 B_CCD2 B17
AD10 U10 A_CAD15 E11 A_RSVD C10 B_CCLK H18
AD11 V10 A_CAD16 A10 A_RSVD D02 B_CCLKRUN A18
AD12 N09 A_CAD17 A07 A_USB_EN E02 B_CDEVSEL H19
AD13 R09 A_CAD18 B07 B_CAD0 P19 B_CFRAME G19
AD14 U09 A_CAD19 C07 B_CAD1 P17 B_CGNT J15
AD15 V09 A_CAD20 G09 B_CAD2 P18 B_CINT B19
AD16 R07 A_CAD21 B06 B_CAD3 M13 B_CIRDY J13
AD17 U06 A_CAD22 C06 B_CAD4 N15 B_CPAR K13
AD18 V06 A_CAD23 B05 B_CAD5 N18 B_CPERR J18
AD19 W06 A_CAD24 E06 B_CAD6 N19 B_CREQ E18
AD20 P06 A_CAD25 A04 B_CAD7 M15 B_CRST F17
AD21 R06 A_CAD26 B04 B_CAD8 M14 B_CSERR B18
AD22 U05 A_CAD27 B01 B_CAD9 M17 B_CSTOP J17
AD23 V05 A_CAD28 C02 B_CAD10 L19 B_CSTSCHG F14
AD24 V04 A_CAD29 D03 B_CAD11 L18 B_CTRDY H17
AD25 U04 A_CAD30 C01 B_CAD12 L17 B_CVS1 C18
AD26 V03 A_CAD31 D01 B_CAD13 L15 B_CVS2 F19
AD27 W02 A_CAUDIO A02 B_CAD14 K18 B_RSVD A15
AD28 U03 A_CBLOCK E10 B_CAD15 L13 B_RSVD K15
AD29 V02 A_CC/BE0 G12 B_CAD16 K17 B_RSVD N17
AD30 V01 A_CC/BE1 B10 B_CAD17 G17 B_USB_EN E01
AD31 U02 A_CC/BE2 F09 B_CAD18 H15 C/BE0 W11
AGND N12 A_CC/BE3 C05 B_CAD19 H14 C/BE1 W09
AGND U14 A_CCD1 C15 B_CAD20 F18 C/BE2 W07
AGND U16 A_CCD2 E05 B_CAD21 G15 C/BE3 W04
AVDD R13 A_CCLK E09 B_CAD22 E19 CLK_48 M01
AVDD R14 A_CCLKRUN C03 B_CAD23 E17 CLOCK L06
AVDD V17 A_CDEVSEL C09 B_CAD24 D18 DATA N01
A_CAD0 E14 A_CFRAME C08 B_CAD25 C19 DEVSEL N08
A_CAD1 B14 A_CGNT B09 B_CAD26 D17 FRAME V07
A_CAD2 A14 A_CINT C04 B_CAD27 C16 GND G07
A_CAD3 E13 A_CIRDY B08 B_CAD28 A17 GND G08
A_CAD4 C14 A_CPAR G10 B_CAD29 B16 GND G13
2−10
Table 2−2. CardBus PC Card Signal Names Sorted Alphabetically (Continued)
SIGNAL NAME TERMINAL
NUMBER SIGNAL NAME TERMINAL
NUMBER SIGNAL NAME TERMINAL
NUMBER SIGNAL NAME TERMINAL
NUMBER
GND H13 PCLK P05 SC_GPIO5 J06 SM_PHYS_WP K02
GND J09 PERR V08 SC_GPIO6 H03 SM_R/B K01
GND J10 PHY_TEST_MA R17 SC_OC L03 SM_RE J05
GND J11 PRST R03 SC_PWR_CTRL L05 SM_WE F03
GND K09 REQ U01 SC_RFU K01 SPKROUT L07
GND K10 RI_OUT/PME T03 SC_RST K03 STOP W08
GND K11 RSVD M11 SC_VCC_5V K07 SUSPEND R02
GND L08 RSVD P15 SDA M02 TEST0 P12
GND L09 RSVD R12 SD_CD E03 TRDY R08
GND L10 RSVD R18 SD_CLK G05 VCC H08
GND L11 RSVD R19 SD_CLK J05 VCC H09
GND L12 RSVD T19 SD_CMD F03 VCC H10
GND M08 RSVD U13 SD_CMD J03 VCC H11
GNT T02 RSVD U15 SD_DAT0 G01 VCC H12
GRST T01 RSVD U17 SD_DAT0 H03 VCC J08
IDSEL W05 RSVD U18 SD_DAT1 G02 VCC J12
IRDY U07 RSVD U19 SD_DAT1 J06 VCC K08
LATCH N02 RSVD V13 SD_DAT2 G03 VCC K12
MC_PWR_CTRL_0 F01 RSVD V14 SD_DAT2 J01 VCC M07
MC_PWR_CTRL_1 F02 RSVD V15 SD_DAT3 H05 VCC M09
MFUNC0 N03 RSVD V16 SD_DAT3 J02 VCC M10
MFUNC1 M05 RSVD V18 SD_WP H07 VCC M12
MFUNC2 P01 RSVD W14 SERR U08 VCC N07
MFUNC3 P02 RSVD W15 SM_ALE J03 VCCA A05
MFUNC4 P03 RSVD W16 SM_CD F06 VCCA A11
MFUNC6 R01 RSVD W18 SM_CE H07 VCCB D19
MFUNC5 N05 SCA M03 SM_CLE J07 VCCB K19
MS_BS F03 SC_CD L02 SM_D0 G01 VCCP W03
MS_CD F05 SC_CLK K05 SM_D1 G02 VCCP W10
MS_CLK G05 SC_DATA L01 SM_D2 G03 VDPLL_15 T18
MS_DATA1 G02 SC_FCB K02 SM_D3 H05 VDPLL_33 V19
MS_DATA2 G03 SC_GPIO0 J07 SM_D4 H03 VR_EN H02
MS_DATA3 H05 SC_GPIO1 J05 SM_D5 J06 VR_PORT H01
MS_SDIO(DATA0) G01 SC_GPIO2 J03 SM_D6 J01 VR_PORT M19
NC W17 SC_GPIO3 J02 SM_D7 J02 VSSPLL P14
PAR P09 SC_GPIO4 J01 SM_EL_WP G05 VSSPLL T17
2−11
Table 2−3. 16-Bit PC Card Signal Names Sorted Alphabetically
SIGNAL
NAME TERMINAL
NUMBER SIGNAL NAME TERMINAL
NUMBER SIGNAL NAME TERMINAL
NUMBER SIGNAL NAME TERMINAL
NUMBER
AD0 W13 A_A5 B06 A_INPACK E07 B_CE1 M18
AD1 N11 A_A6 G09 A_IORD C11 B_CE2 L19
AD2 U12 A_A7 B07 A_IOWR E11 B_D0 C16
AD3 V12 A_A8 B10 A_OE C12 B_D1 B16
AD4 W12 A_A9 G11 A_READY(IREQ) C04 B_D2 A15
AD5 R11 A_A10 A12 A_REG C05 B_D3 P19
AD6 U11 A_A11 B11 A_RESET A06 B_D4 P17
AD7 V11 A_A12 F09 A_USB_EN E02 B_D5 M13
AD8 N10 A_A13 G10 A_VS1 A03 B_D6 N18
AD9 R10 A_A14 F10 A_VS2 E08 B_D7 M15
AD10 U10 A_A15 B08 A_WAIT B03 B_D8 A17
AD11 V10 A_A16 E09 A_WE B09 B_D9 A16
AD12 N09 A_A17 A10 A_WP(IOIS16) C03 B_D10 B15
AD13 R09 A_A18 C10 B_A0 D17 B_D11 P18
AD14 U09 A_A19 E10 B_A1 C19 B_D12 N15
AD15 V09 A_A20 A09 B_A2 D18 B_D13 N19
AD16 R07 A_A21 C09 B_A3 E17 B_D14 N17
AD17 U06 A_A22 A08 B_A4 E19 B_D15 M14
AD18 V06 A_A23 C08 B_A5 G15 B_INPACK E18
AD19 W06 A_A24 A07 B_A6 F18 B_IORD L15
AD20 P06 A_A25 C07 B_A7 H15 B_IOWR L13
AD21 R06 A_BVD1(STSCHG/RI) B02 B_A8 K14 B_OE L18
AD22 U05 A_BVD2(SPKR) A02 B_A9 K18 B_READY(IREQ) B19
AD23 V05 A_CD1 C15 B_A10 M17 B_REG F15
AD24 V04 A_CD2 E05 B_A11 L17 B_RESET F17
AD25 U04 A_CE1 G12 B_A12 G18 B_USB_EN E01
AD26 V03 A_CE2 B12 B_A13 K13 B_VS1 C18
AD27 W02 A_D0 B01 B_A14 J18 B_VS2 F19
AD28 U03 A_D1 D03 B_A15 J13 B_WAIT B18
AD29 V02 A_D2 D02 B_A16 H18 B_WE J15
AD30 V01 A_D3 E14 B_A17 K17 B_WP(IOIS16) A18
AD31 U02 A_D4 B14 B_A18 K15 C/BE0 W11
AGND N12 A_D5 E13 B_A19 J19 C/BE1 W09
AGND U14 A_D6 A13 B_A20 J17 C/BE2 W07
AGND U16 A_D7 C13 B_A21 H19 C/BE3 W04
AVDD R13 A_D8 C02 B_A22 H17 CLK_48 M01
AVDD R14 A_D9 C01 B_A23 G19 CLOCK L06
AVDD V17 A_D10 D01 B_A24 G17 DATA N01
A_A0 B04 A_D11 A14 B_A25 H14 DEVSEL N08
A_A1 A04 A_D12 C14 B_BVD1(STSCHG/RI) F14 FRAME V07
A_A2 E06 A_D13 F12 B_BVD2(SPKR) C17 GND G07
A_A3 B05 A_D14 B13 B_CD1 N13 GND G08
A_A4 C06 A_D15 E12 B_CD2 B17 GND G13
2−12
Table 2−3. 16-Bit PC Card Signal Names Sorted Alphabetically (Continued)
SIGNAL NAME TERMINAL
NUMBER SIGNAL NAME TERMINAL
NUMBER SIGNAL NAME TERMINAL
NUMBER SIGNAL NAME TERMINAL
NUMBER
GND H13 PCLK P05 SC_GPIO5 J06 SM_PHYS_WP K02
GND J09 PERR V08 SC_GPIO6 H03 SM_R/B K01
GND J10 PHY_TEST_MA R17 SC_OC L03 SM_RE J05
GND J11 PRST R03 SC_PWR_CTRL L05 SM_WE F03
GND K09 REQ U01 SC_RFU K01 SPKROUT L07
GND K10 RI_OUT/PME T03 SC_RST K03 STOP W08
GND K11 RSVD M11 SC_VCC_5V K07 SUSPEND R02
GND L08 RSVD P15 SDA M02 TEST0 P12
GND L09 RSVD R12 SD_CD E03 TRDY R08
GND L10 RSVD R18 SD_CLK G05 VCC H08
GND L11 RSVD R19 SD_CLK J05 VCC H09
GND L12 RSVD T19 SD_CMD F03 VCC H10
GND M08 RSVD U13 SD_CMD J03 VCC H11
GNT T02 RSVD U15 SD_DAT0 G01 VCC H12
GRST T01 RSVD U17 SD_DAT0 H03 VCC J08
IDSEL W05 RSVD U18 SD_DAT1 G02 VCC J12
IRDY U07 RSVD U19 SD_DAT1 J06 VCC K08
LATCH N02 RSVD V13 SD_DAT2 G03 VCC K12
MC_PWR_CTRL_0 F01 RSVD V14 SD_DAT2 J01 VCC M07
MC_PWR_CTRL_1 F02 RSVD V15 SD_DAT3 H05 VCC M09
MFUNC0 N03 RSVD V16 SD_DAT3 J02 VCC M10
MFUNC1 M05 RSVD V18 SD_WP H07 VCC M12
MFUNC2 P01 RSVD W14 SERR U08 VCC N07
MFUNC3 P02 RSVD W15 SM_ALE J03 VCCA A05
MFUNC4 P03 RSVD W16 SM_CD F06 VCCA A11
MFUNC6 R01 RSVD W18 SM_CE H07 VCCB D19
MFUNC5 N05 SCA M03 SM_CLE J07 VCCB K19
MS_BS F03 SC_CD L02 SM_D0 G01 VCCP W03
MS_CD F05 SC_CLK K05 SM_D1 G02 VCCP W10
MS_CLK G05 SC_DATA L01 SM_D2 G03 VDPLL_15 T18
MS_DATA1 G02 SC_FCB K02 SM_D3 H05 VDPLL_33 V19
MS_DATA2 G03 SC_GPIO0 J07 SM_D4 H03 VR_EN H02
MS_DATA3 H05 SC_GPIO1 J05 SM_D5 J06 VR_PORT H01
MS_SDIO(DATA0) G01 SC_GPIO2 J03 SM_D6 J01 VR_PORT M19
NC W17 SC_GPIO3 J02 SM_D7 J02 VSSPLL P14
PAR P09 SC_GPIO4 J01 SM_EL_WP G05 VSSPLL T17
2−13
2.1 Detailed Terminal Descriptions
Please see Table 2−4 through Table 2−19 for more detailed terminal descriptions. The following list defines the
column headings and the abbreviations used in the detailed terminal description tables.
•I/O Type:
− I = Digital input
− O = Digital output
− I/O = Digital input/output
− AI = Analog input
− PWR = Power
− GND = Ground
•Input/Output Description:
− AF = Analog feedthrough
− TTLI1 = 5-V tolerant TTL input buffer
− TTLI2 = 5-V tolerant TTL input buffer with hysteresis
− TTLO1 = 5-V tolerant low-noise 4-mA TTL output buffer
− PCII1 = 5-V tolerant PCI input buffer
− PCII2 = 5-V tolerant PCI input buffer
− PCII3 = 5-V tolerant PCI input buffer
− PCII4 = 5-V tolerant PCI input buffer
− PCII5 = 5-V tolerant PCI input buffer
− PCIO2 = 5-V tolerant PCI output buffer
− PCIO4 = 5-V tolerant PCI output buffer
− PCIO5 = 5-V tolerant PCI output buffer
− LVCI1 = LVCMOS input buffer
− LVCO1 = Low-noise 4-mA LVCMOS open drain output buffer
− LVCO2 = Low-noise 4-mA LVCMOS open drain output buffer
− LVCO3 = Low-noise 8-mA LVCMOS open drain output buffer
•PU/PD signifies whether the terminal has an internal pullup or pulldown resistor. These pullups are disabled
and enabled by design when appropriate to preserve power.
− PD1 = 20-µA failsafe pulldown
− PD2 = 100-µA failsafe pulldown
− PU1 = 200-µA pullup
− PU2 = 100-µA pullup
− PU3 = 100-µA pullup
− PU4 = 100-µA pullup
− SW = Switchable 50-µA pullup/200-µA pulldown implemented depending on situation
•Power Rail signifies which rail the terminal is clamped to for protection.
•External Components signifies any external components needed for normal operation.
•Pin Strapping (If Unused) signifies how the terminal must be implemented if its function is not needed.
The terminals are grouped in tables by functionality, such as PCI system function, power-supply function, etc. The
terminal numbers are also listed for convenient reference.
2−14
Table 2−4. Power Supply Terminals
Output description, internal pullup/pulldown resistors, and the power rail designation are not applicable for the power
supply terminals.
TERMINAL
DESCRIPTION
I/O
INPUT
EXTERNAL
PIN STRAPPING
NAME NUMBER DESCRIPTION
I/O
TYPE INPUT
EXTERNAL
COMPONENTS
PIN STRAPPING
(IF UNUSED)
AGND N12, U14,
U16 Analog circuit ground terminals GND NA
AVDD R13, R14,
V17
Analog circuit power terminals. A parallel combination of high
frequency decoupling capacitors near each terminal is suggested,
such as 0.1 µF and 0.001 µF. Lower frequency 10-µF filtering
capacitors are also recommended. These supply terminals are
separated from VDPLL_33 internal to the controller to provide
noise isolation. They must be tied to a low-impedance point on the
circuit board.
GND
0.1-µF, 0.001-µF,
and 10-µF
capacitors tied to
AGND
NA
GND
G07, G08,
G13, H13,
J09, J10,
J11, K09,
K10, K11,
L08, L09,
L10, L11,
L12, M08
Digital ground terminal GND NA
VCC
H08, H09,
H10, H11,
H12, J08,
J12, K08,
K12, M07,
M09, M10,
M12, N07
Power supply terminal for I/O and internal voltage regulator PWR NA
VCCA A05, A11 Clamp voltage for PC Card A interface. Matches card A signaling
environment, 5 V or 3.3 V PWR Float
VCCB D19, K19 Clamp voltage for PC Card B interface. Matches card B signaling
environment, 5 V or 3.3 V PWR Float
VCCP W03, W10 Clamp voltage for PCI and miscellaneous I/O, 5 V or 3.3 V PWR NA
VDPLL_15 T18
1.5-V PLL circuit power terminal. An external capacitor (0.1 µF
recommended) must be placed between terminals T18 and T17
(VSSPLL) when the internal voltage regulator is enabled
(VR_EN = 0 V). When the internal voltage regulator is disabled,
1.5-V must be supplied to this terminal and a parallel combination
of high frequency decoupling capacitors near the terminal is
suggested, such as 0.1 µF and 0.001 µF. Lower frequency 10-µF
filtering capacitors are also recommended.
0.1-µF, 0.001-µF,
and 10-µF
capacitors tied to
VSPLL
NA
VDPLL_33 V19
3.3-V PLL circuit power terminal. A parallel combination of high
frequency decoupling capacitors near the terminal is suggested,
such as 0.1 µF and 0.001 µF. Lower frequency 10-µF filtering
capacitors are also recommended. This supply terminal is
separated from AVDD internal to the controller to provide noise
isolation. It must be tied to a low-impedance point on the circuit
board. When the internal voltage regulator is disabled
(VR_EN = 3.3 V), no voltage is required to be supplied to this
terminal.
PWR
0.1-µF, 0.001-µF,
and 10-µF
capacitors tied to
VSPLL
NA
VR_EN H02 Internal voltage regulator enable. Active low FT FT Pulled directly to
GND NA
VR_PORT H01, M19 1.5-V output from the internal voltage regulator PWR 0.1-µF capacitor
tied to GND NA
VSSPLL P14, T17 PLL circuit ground terminal. This terminal must be tied to the
low-impedance circuit board ground plane. GND NA
2−15
Table 2−5. PC Card Power Switch Terminals
Internal pullup/pulldown resistors, power rail designation, and pin strapping are not applicable for the power switch
terminals.
TERMINAL
DESCRIPTION
I/O
INPUT
OUTPUT
EXTERNAL
NAME NO. DESCRIPTION
I/O
TYPE INPUT OUTPUT
EXTERNAL
COMPONENTS
CLOCK L06 Power switch clock. Information on the DATA line is sampled at the rising edge of
CLOCK. CLOCK defaults to an input, but can be changed to an output by using bit 27
(P2CCLK) in the system control register (offset 80h, see Section 4.29). I/O TTLI1 TTLO1 PCMCIA power
switch
DATA N01 Power switch data. DATA is used to communicate socket power control information
serially to the power switch. O LVCO1 PCMCIA power
switch
LATCH N02 Power switch latch. LATCH is asserted by the controller to indicate to the power
switch that the data on the DATA line is valid. O LVCO1 PCMCIA power
switch
Table 2−6. PCI System Terminals
Internal pullup/pulldown resistors and pin strapping are not applicable for the PCI terminals.
TERMINAL
DESCRIPTION
I/O
INPUT
POWER
EXTERNAL
NAME NO. DESCRIPTION
I/O
TYPE INPUT
POWER
RAIL
EXTERNAL
COMPONENTS
GRST T01
Global reset. When the global reset is asserted, the GRST signal causes the
controller to place all output buffers in a high-impedance state and reset all internal
registers. When GRST is asserted, the controller is completely in its default state. For
systems that require wake-up from D3, GRST is normally asserted only during initial
boot. PRST must be asserted following initial boot so that PME context is retained
when transitioning from D3 to D0. For systems that do not require wake-up from D3,
GRST must be tied to PRST. When the SUSPEND mode is enabled, the controller is
protected from the GRST, and the internal registers are preserved. All outputs are
placed in a high-impedance state, but the contents of the registers are preserved.
I LVCI2 Power-on reset or
tied to PRST
PCLK P05 PCI bus clock. PCLK provides timing for all transactions on the PCI bus. All PCI
signals are sampled at the rising edge of PCLK. I PCII3 VCCP
PRST R03
PCI bus reset. When the PCI bus reset is asserted, PRST causes the controller to
place all output buffers in a high-impedance state and reset some internal registers.
When PRST is asserted, the controller is completely nonfunctional. After PRST is
deasserted, the controller is in a default state.
When SUSPEND and PRST are asserted, the controller is protected from PRST
clearing the internal registers. All outputs are placed in a high-impedance state, but
the contents of the registers are preserved.
I PCII3 VCCP
2−16
Table 2−7. PCI Address and Data Terminals
Internal pullup/pulldown resistors and pin strapping are not applicable for the PCI address and data terminals.
TERMINAL
DESCRIPTION
I/O
INPUT
OUTPUT
POWER
NAME NO. DESCRIPTION
I/O
TYPE INPUT OUTPUT
POWER
RAIL
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
U02
V01
V02
U03
W02
V03
U04
V04
V05
U05
R06
P06
W06
V06
U06
R07
V09
U09
R09
N09
V10
U10
R10
N10
V11
U11
R11
W12
V12
U12
N11
W13
PCI address/data bus. These signals make up the multiplexed PCI address and data bus on the
primary interface. During the address phase of a primary-bus PCI cycle, AD31−AD0 contain a
32-bit address or other destination information. During the data phase, AD31−AD0 contain data. I/O PCII3 PCIO3 VCCP
C/BE3
C/BE2
C/BE1
C/BE0
W04
W07
W09
W11
PCI-bus commands and byte enables. These signals are multiplexed on the same PCI
terminals. During the address phase of a primary-bus PCI cycle, C/BE3−C/BE0 define the bus
command. During the data phase, this 4-bit bus is used as byte enables. The byte enables
determine which byte paths of the full 32-bit data bus carry meaningful data. C/BE0 applies to
byte 0 (AD7−AD0), C/BE1 applies to byte 1 (AD15−AD8), C/BE2 applies to byte 2
(AD23−AD16), and C/BE3 applies to byte 3 (AD31−AD24).
I/O PCII3 PCIO3 VCCP
PAR P09
PCI-bus parity. In all PCI-bus read and write cycles, the controller calculates even parity across
the AD31−AD0 and C/BE3−C/BE0 buses. As an initiator during PCI cycles, the controller
outputs this parity indicator with a one-PCLK delay. As a target during PCI cycles, the controller
compares its calculated parity to the parity indicator of the initiator. A compare error results in
the assertion of a parity error (PERR).
I/O PCII3 PCIO3 VCCP
2−17
Table 2−8. PCI Interface Control Terminals
Internal pullup/pulldown resistors and pin strapping are not applicable for the PCI interface control terminals.
TERMINAL
DESCRIPTION
I/O
INPUT
OUTPUT
POWER
EXTERNAL
NAME NO. DESCRIPTION
I/O
TYPE INPUT OUTPUT
POWER
RAIL
EXTERNAL
COMPONENTS
DEVSEL N08
PCI device select. The controller asserts DEVSEL to claim a PCI cycle
as the target device. As a PCI initiator on the bus, the controller monitors
DEVSEL until a target responds. If no target responds before timeout
occurs, then the controller terminates the cycle with an initiator abort.
I/O PCII3 PCIO3 VCCP Pullup resistor per
PCI specification
FRAME V07
PCI cycle frame. FRAME is driven by the initiator of a bus cycle. FRAME
is asserted to indicate that a bus transaction is beginning, and data
transfers continue while this signal is asserted. When FRAME is
deasserted, the PCI bus transaction is in the final data phase.
I/O PCII3 PCIO3 VCCP Pullup resistor per
PCI specification
GNT T02
PCI bus grant. GNT is driven by the PCI bus arbiter to grant the
controller access to the PCI bus after the current data transaction has
completed. GNT may or may not follow a PCI bus request, depending on
the PCI bus parking algorithm.
I PCII3 VCCP
IDSEL W05 Initialization device select. IDSEL selects the controller during
configuration space accesses. IDSEL can be connected to one of the
upper 24 PCI address lines on the PCI bus. I PCII3 VCCP
IRDY U07
PCI initiator ready. IRDY indicates the ability of the PCI bus initiator to
complete the current data phase of the transaction. A data phase is
completed on a rising edge of PCLK where both IRDY and TRDY are
asserted. Until IRDY and TRDY are both sampled asserted, wait states
are inserted.
I/O PCII3 PCIO3 VCCP Pullup resistor per
PCI specification
PERR V08 PCI parity error indicator. PERR is driven by a PCI controller to indicate
that calculated parity does not match PAR when PERR is enabled
through bit 6 of the command register (PCI offset 04h, see Section 4.4). I/O PCII3 PCIO3 VCCP Pullup resistor per
PCI specification
REQ U01 PCI bus request. REQ is asserted by the controller to request access to
the PCI bus as an initiator. O PCIO3 VCCP
SERR U08
PCI system error. SERR is an output that is pulsed from the controller
when enabled through bit 8 of the command register (PCI offset 04h,
see Section 4.4) indicating a system error has occurred. The controller
need not be the target of the PCI cycle to assert this signal. When SERR
is enabled in the command register, this signal also pulses, indicating
that an address parity error has occurred on a CardBus interface.
O PCIO3 VCCP Pullup resistor per
PCI specification
STOP W08
PCI cycle stop signal. STOP is driven by a PCI target to request the
initiator to stop the current PCI bus transaction. STOP is used for target
disconnects and is commonly asserted by target devices that do not
support burst data transfers.
I/O PCII3 PCIO3 VCCP Pullup resistor per
PCI specification
TRDY R08
PCI target ready. TRDY indicates the ability of the primary bus target to
complete the current data phase of the transaction. A data phase is
completed on a rising edge of PCLK when both IRDY and TRDY are
asserted. Until both IRDY and TRDY are asserted, wait states are
inserted.
I/O PCII3 PCIO3 VCCP Pullup resistor per
PCI specification
2−18
Table 2−9. Multifunction and Miscellaneous Terminals
The power rail designation is not applicable for the multifunction and miscellaneous terminals.
TERMINAL
DESCRIPTION
I/O
INPUT
OUTPUT
PU/
EXTERNAL
PIN STRAPPING
NAME NO. DESCRIPTION
I/O
TYPE INPUT OUTPUT
PU/
PD
EXTERNAL
COMPONENTS
PIN STRAPPING
(IF UNUSED)
A_USB_EN
B_USB_EN E02
E01
USB enable. These output terminals control an
external CBT switch for each socket when an USB
card is inserted into the socket. O LVCO1 CBT switch Float
CLK_48 M01 A 48-MHz clock must be connected to this terminal. I LVCI1 48 MHz clock
source
MFUNC0 N03 I/O PCII3 PCIO3 10-kΩ to 47-kΩ
pullup resistor
MFUNC1 M05 I/O PCII3 PCIO3 10-kΩ to 47-kΩ
pullup resistor
MFUNC2 P01
Multifunction terminals 0−6. See Section 4.36,
I/O PCII3 PCIO3 10-kΩ to 47-kΩ
pullup resistor
MFUNC3 P02 Multifunction terminals 0−6. See Section 4.36,
Multifunction Routing Status Register, for
configuration details.
I/O PCII3 PCIO3 10-kΩ to 47-kΩ
pullup resistor
MFUNC4 P03
configuration details.
I/O PCII3 PCIO3 10-kΩ to 47-kΩ
pullup resistor
MFUNC5 N05 I/O PCII3 PCIO3 10-kΩ to 47-kΩ
pullup resistor
MFUNC6 R01 I/O PCII3 PCIO3 10-kΩ to 47-kΩ
pullup resistor
NC W17 Reserved. This terminal has no connection
anywhere within the package. Float
PHY_TEST_
MA R17 PHY test pin. Not for customer use. It must be pulled
high with a 4.7-kΩ resistor. I LVCI1 PD1 NA
RI_OUT/
PME T03 Ring indicate out and power management event
output. This terminal provides an output for
ring-indicate or PME signals. O LVCO2 Pullup resistor per
PCI specification NA
RSVD T19 Reserved. This terminal has no connection
anywhere within the package. — Float
SCL M03
Serial clock. At PRST, the SCL signal is sampled to
determine if a two-wire serial ROM is present. If the
serial ROM is detected, then this terminal provides
the serial clock signaling and is implemented as
open-drain. For normal operation (a ROM is
implemented in the design), this terminal must be
pulled high to the ROM VDD with a 2.7-kΩ resistor.
Otherwise, it must be pulled low to ground with a
220-Ω resistor.
I/O TTLI1 TTLO1
Pullup resistor per
I2C specification
(value depends on
EEPROM,
typically 2.7 kΩ)
Tie to GND if not
using EEPROM
SDA M02
Serial data. This terminal is implemented as
open-drain, and for normal operation (a ROM is
implemented in the design), this terminal must be
pulled high to the ROM VDD with a 2.7-kΩ resistor.
Otherwise, it must be pulled low to ground with a
220-Ω resistor.
I/O TTLI1 TTLO1
Pullup resistor per
I2C specification
(value depends on
EEPROM,
typically 2.7 kΩ)
Tie to GND if not
using EEPROM
SPKROUT L07
Speaker output. SPKROUT is the output to the host
system that can carry SPKR or CAUDIO through the
controller from the PC Card interface. SPKROUT is
driven as the exclusive-OR combination of card
SPKR//CAUDIO inputs.
O TTLO1 10-kΩ to 47-kΩ
pulldown resistor 10-kΩ to 47-kΩ
pulldown resistor
SUSPEND R02
Suspend. SUSPEND protects the internal registers
from clearing when the GRST or PRST signal is
asserted. See Section 3.8.5, Suspend Mode, for
details.
I PCII6 10-kΩ to 47-kΩ
pullup resistor 10-kΩ to 47-kΩ
pullup resistor
TEST0 P12 Terminal TEST0 is used for factory test of the
controller and must be connected to ground for
normal operation. I/O LVCI1 PD1 Tie to GND
2−19
Table 2−10. 16-Bit PC Card Address and Data Terminals
External components are not applicable for the 16-bit PC Card address and data terminals. If any 16-bit PC Card
address and data terminal is unused, then the terminal may be left floating.
SOCKET A TERMINAL SOCKET B TERMINAL†
DESCRIPTION
I/O
POWER
NAME NO. NAME NO. DESCRIPTION
I/O
TYPE
POWER
RAIL
A_A25
A_A24
A_A23
A_A22
A_A21
A_A20
A_A19
A_A18
A_A17
A_A16
A_A15
A_A14
A_A13
A_A12
A_A11
A_A10
A_A9
A_A8
A_A7
A_A6
A_A5
A_A4
A_A3
A_A2
A_A1
A_A0
C07
A07
C08
A08
C09
A09
E10
C10
A10
E09
B08
F10
G10
F09
B11
A12
G11
B10
B07
G09
B06
C06
B05
E06
A04
B04
B_A25
B_A24
B_A23
B_A22
B_A21
B_A20
B_A19
B_A18
B_A17
B_A16
B_A15
B_A14
B_A13
B_A12
B_A11
B_A10
B_A9
B_A8
B_A7
B_A6
B_A5
B_A4
B_A3
B_A2
B_A1
B_A0
H14
G17
G19
H17
H19
J17
J19
K15
K17
H18
J13
J18
K13
G18
L17
M17
K18
K14
H15
F18
G15
E19
E17
D18
C19
D17
PC Card address. 16-bit PC Card address lines. A25 is the most significant
bit. OVCCA/
VCCB
A_D15
A_D14
A_D13
A_D12
A_D11
A_D10
A_D9
A_D8
A_D7
A_D6
A_D5
A_D4
A_D3
A_D2
A_D1
A_D0
E12
B13
F12
C14
A14
D01
C01
C02
C13
A13
E13
B14
E14
D02
D03
B01
B_D15
B_D14
B_D13
B_D12
B_D11
B_D10
B_D9
B_D8
B_D7
B_D6
B_D5
B_D4
B_D3
B_D2
B_D1
B_D0
M14
N17
N19
N15
P18
B15
A16
A17
M15
N18
M13
P17
P19
A15
B16
C16
PC Card data. 16-bit PC Card data lines. D15 is the most significant bit. I/O VCCA/
VCCB
†These terminals are reserved for the PCI6611 and PCI6411 controllers.
2−20
Table 2−11. 16-Bit PC Card Interface Control Terminals
External components are not applicable for the 16-bit PC Card interface control terminals. If any 16-bit PC Card
interface control terminal is unused, then the terminal may be left floating.
SKT A TERMINAL SKT B TERMINAL†
DESCRIPTION
I/O
POWER
NAME NO. NAME NO. DESCRIPTION
I/O
TYPE
POWER
RAIL
A_BVD1
(STSCHG/RI) B02 B_BVD1
(STSCHG/RI) F14
Battery voltage detect 1. BVD1 is generated by 16-bit memory PC Cards that
include batteries. BVD1 is used with BVD2 as an indication of the condition of the
batteries on a memory PC Card. Both BVD1 and BVD2 are high when the battery
is good. When BVD2 is low and BVD1 is high, the battery is weak and must be
replaced. When BVD1 is low, the battery is no longer serviceable and the data in
the memory PC Card is lost. See Section 5.6, ExCA Card Status-Change Interrupt
Configuration Register, for enable bits. See Section 5.5, ExCA Card
Status-Change Register, and Section 5.2, ExCA Interface Status Register, for the
status bits for this signal.
Status change. STSCHG alerts the system to a change in the READY, write
protect, or battery voltage dead condition of a 16-bit I/O PC Card.
Ring indicate. RI is used by 16-bit modem cards to indicate a ring detection.
IVCCA/
VCCB
A_BVD2
(SPKR)A02 B_BVD2
(SPKR)C17
Battery voltage detect 2. BVD2 is generated by 16-bit memory PC Cards that
include batteries. BVD2 is used with BVD1 as an indication of the condition of the
batteries on a memory PC Card. Both BVD1 and BVD2 are high when the battery
is good. When BVD2 is low and BVD1 is high, the battery is weak and must be
replaced. When BVD1 is low, the battery is no longer serviceable and the data in
the memory PC Card is lost. See Section 5.6, ExCA Card Status-Change Interrupt
Configuration Register, for enable bits. See Section 5.5, ExCA Card
Status-Change Register, and Section 5.2, ExCA Interface Status Register, for the
status bits for this signal.
Speaker. SPKR is an optional binary audio signal available only when the card and
socket have been configured for the 16-bit I/O interface. The audio signals from
cards A and B are combined by the controller and are output on SPKROUT.
DMA request. BVD2 can be used as the DMA request signal during DMA
operations to a 16-bit PC Card that supports DMA. The PC Card asserts BVD2 to
indicate a request for a DMA operation.
IVCCA/
VCCB
A_CD1
A_CD2 C15
E05 B_CD1
B_CD2 N13
B17
Card detect 1 and card detect 2. CD1 and CD2 are internally connected to ground
on the PC Card. When a PC Card is inserted into a socket, CD1 and CD2 are
pulled low. For signal status, see Section 5.2, ExCA Interface Status Register.I
A_CE1
A_CE2 G12
B12 B_CE1
B_CE2 M18
L19
Card enable 1 and card enable 2. CE1 and CE2 enable even- and odd-numbered
address bytes. CE1 enables even-numbered address bytes, and CE2 enables
odd-numbered address bytes. OVCCA/
VCCB
A_INPACK E07 B_INPACK E18
Input acknowledge. INPACK is asserted by the PC Card when it can respond to an
I/O read cycle at the current address.
DMA request. INPACK can be used as the DMA request signal during DMA
operations from a 16-bit PC Card that supports DMA. If it is used as a strobe, then
the PC Card asserts this signal to indicate a request for a DMA operation.
IVCCA/
VCCB
A_IORD C11 B_IORD L15
I/O read. IORD is asserted by the controller to enable 16-bit I/O PC Card data
output during host I/O read cycles.
DMA write. IORD is used as the DMA write strobe during DMA operations from a
16-bit PC Card that supports DMA. The controller asserts IORD during DMA
transfers from the PC Card to host memory.
OVCCA/
VCCB
A_IOWR E11 B_IOWR L13
I/O write. IOWR is driven low by the controller to strobe write data into 16-bit I/O
PC Cards during host I/O write cycles.
DMA read. IOWR is used as the DMA write strobe during DMA operations from a
16-bit PC Card that supports DMA. The controller asserts IOWR during transfers
from host memory to the PC Card.
OVCCA/
VCCB
†These terminals are reserved for the PCI6611 and PCI6411 controllers.
2−21
Table 2−11. 16-Bit PC Card Interface Control Terminals (Continued)
SKT A TERMINAL SKT B TERMINAL†
DESCRIPTION
I/O
POWER
NAME NO. NAME NO. DESCRIPTION
I/O
TYPE
POWER
RAIL
A_OE C12 B_OE L18
Output enable. OE is driven low by the controller to enable 16-bit memory PC Card
data output during host memory read cycles.
DMA terminal count. OE is used as terminal count (TC) during DMA operations to a
16-bit PC Card that supports DMA. The controller asserts OE to indicate TC for a DMA
write operation.
OVCCA/
VCCB
A_READY
(IREQ)C04 B_READY
(IREQ)B19
Ready. The ready function is provided when the 16-bit PC Card and the host socket are
configured for the memory-only interface. READY is driven low by 16-bit memory PC
Cards to indicate that the memory card circuits are busy processing a previous write
command. READY is driven high when the 16-bit memory PC Card is ready to accept a
new data transfer command.
Interrupt request. IREQ is asserted by a 16-bit I/O PC Card to indicate to the host that a
controller on the 16-bit I/O PC Card requires service by the host software. IREQ is high
(deasserted) when no interrupt is requested.
IVCCA/
VCCB
A_REG C05 B_REG F15
Attribute memory select. REG remains high for all common memory accesses. When
REG is asserted, access is limited to attribute memory (OE or WE active) and to the I/O
space (IORD or IOWR active). Attribute memory is a separately accessed section of
card memory and is generally used to record card capacity and other configuration and
attribute information.
DMA acknowledge. REG is used as a DMA acknowledge (DACK) during DMA
operations to a 16-bit PC Card that supports DMA. The controller asserts REG to
indicate a DMA operation. REG is used in conjunction with the DMA read (IOWR) or
DMA write (IORD) strobes to transfer data.
OVCCA/
VCCB
A_RESET A06 B_RESET F17 PC Card reset. RESET forces a hard reset to a 16-bit PC Card. OVCCA/
VCCB
A_VS1
A_VS2 A03
E08 B_VS1
B_VS2 C18
F19 Voltage sense 1 and voltage sense 2. VS1 and VS2, when used in conjunction with
each other, determine the operating voltage of the PC Card. I/O VCCA/
VCCB
A_WAIT B03 B_WAIT B18 Bus cycle wait. WAIT is driven by a 16-bit PC Card to extend the completion of the
memory or I/O cycle in progress. IVCCA/
VCCB
A_WE B09 B_WE J15
Write enable. WE is used to strobe memory write data into 16-bit memory PC Cards.
WE is also used for memory PC Cards that employ programmable memory
technologies.
DMA terminal count. WE is used as a TC during DMA operations to a 16-bit PC Card
that supports DMA. The controller asserts WE to indicate the TC for a DMA read
operation.
OVCCA/
VCCB
A_WP
(IOIS16)C03 B_WP
(IOIS16)A18
Write protect. WP applies to 16-bit memory PC Cards. WP reflects the status of the
write-protect switch on 16-bit memory PC Cards. For 16-bit I/O cards, WP is used for
the 16-bit port (IOIS16) function.
I/O is 16 bits. IOIS16 applies to 16-bit I/O PC Cards. IOIS16 is asserted by the 16-bit
PC Card when the address on the bus corresponds to an address to which the 16-bit
PC Card responds, and the I/O port that is addressed is capable of 16-bit accesses.
DMA request. WP can be used as the DMA request signal during DMA operations to a
16-bit PC Card that supports DMA. If used, then the PC Card asserts WP to indicate a
request for a DMA operation.
IVCCA/
VCCB
†These terminals are reserved for the PCI6611 and PCI6411 controllers.
2−22
Table 2−12. CardBus PC Card Interface System Terminals
A 33-Ω to 47-Ω series damping resistor (per PC Card specification) is the only external component needed for
terminals B08 (A_CCLK) and H17 (B_CCLK). If any CardBus PC Card interface system terminal is unused, then the
terminal may be left floating.
SKT A TERMINAL SKT B TERMINAL†
DESCRIPTION
I/O
INPUT
OUTPUT
PU/
POWER
NAME NO. NAME NO. DESCRIPTION
I/O
TYPE INPUT OUTPUT
PU/
PD
POWER
RAIL
A_CCLK E09 B_CCLK H18
CardBus clock. CCLK provides synchronous timing
for all transactions on the CardBus interface. All
signals except CRST, CCLKRUN, CINT, CSTSCHG,
CAUDIO, CCD2, CCD1, CVS2, and CVS1 are
sampled on the rising edge of CCLK, and all timing
parameters are defined with the rising edge of this
signal. CCLK operates at the PCI bus clock
frequency, but it can be stopped in the low state or
slowed down for power savings.
O PCIO3 VCCA/
VCCB
A_CCLKRUN C03 B_CCLKRUN A18
CardBus clock run. CCLKRUN is used by a CardBus
PC Card to request an increase in the CCLK
frequency, and by the controller to indicate that the
CCLK frequency is going to be decreased.
I/O PCII4 PCIO4 PU3 VCCA/
VCCB
A_CRST A06 B_CRST F17
CardBus reset. CRST brings CardBus PC
Card-specific registers, sequencers, and signals to a
known state. When CRST is asserted, all CardBus
PC Card signals are placed in a high-impedance
state, and the controller drives these signals to a valid
logic level. Assertion can be asynchronous to CCLK,
but deassertion must be synchronous to CCLK.
O PCII4 PCIO4 PU3 VCCA/
VCCB
†These terminals are reserved for the PCI6611 and PCI6411 controllers.
2−23
Table 2−13. CardBus PC Card Address and Data Terminals
External components are not applicable for the 16-bit PC Card address and data terminals. If any CardBus PC Card
address and data terminal is unused, then the terminal may be left floating.
SKT A TERMINAL SKT B TERMINAL†
DESCRIPTION
I/O
INPUT
OUTPUT
POWER
NAME NO. NAME NO. DESCRIPTION
I/O
TYPE INPUT OUTPUT
POWER
RAIL
A_CAD31
A_CAD30
A_CAD29
A_CAD28
A_CAD27
A_CAD26
A_CAD25
A_CAD24
A_CAD23
A_CAD22
A_CAD21
A_CAD20
A_CAD19
A_CAD18
A_CAD17
A_CAD16
A_CAD15
A_CAD14
A_CAD13
A_CAD12
A_CAD11
A_CAD10
A_CAD9
A_CAD8
A_CAD7
A_CAD6
A_CAD5
A_CAD4
A_CAD3
A_CAD2
A_CAD1
A_CAD0
D01
C01
D03
C02
B01
B04
A04
E06
B05
C06
B06
G09
C07
B07
A07
A10
E11
G11
C11
B11
C12
B12
A12
E12
C13
F12
A13
C14
E13
A14
B14
E14
B_CAD31
B_CAD30
B_CAD29
B_CAD28
B_CAD27
B_CAD26
B_CAD25
B_CAD24
B_CAD23
B_CAD22
B_CAD21
B_CAD20
B_CAD19
B_CAD18
B_CAD17
B_CAD16
B_CAD15
B_CAD14
B_CAD13
B_CAD12
B_CAD11
B_CAD10
B_CAD9
B_CAD8
B_CAD7
B_CAD6
B_CAD5
B_CAD4
B_CAD3
B_CAD2
B_CAD1
B_CAD0
B15
A16
B16
A17
C16
D17
C19
D18
E17
E19
G15
F18
H14
H15
G17
K17
L13
K18
L15
L17
L18
L19
M17
M14
M15
N19
N18
N15
M13
P18
P17
P19
CardBus address and data. These signals make up the multiplexed
CardBus address and data bus on the CardBus interface. During
the address phase of a CardBus cycle, CAD31−CAD0 contain a
32-bit address. During the data phase of a CardBus cycle,
CAD31−CAD0 contain data. CAD31 is the most significant bit.
I/O PCII7 PCIO7 VCCA/
VCCB
A_CC/BE3
A_CC/BE2
A_CC/BE1
A_CC/BE0
C05
F09
B10
G12
B_CC/BE3
B_CC/BE2
B_CC/BE1
B_CC/BE0
F15
G18
K14
M18
CardBus bus commands and byte enables. CC/BE3−CC/BE0 are
multiplexed on the same CardBus terminals. During the address
phase of a CardBus cycle, CC/BE3−CC/BE0 define the bus
command. During the data phase, this 4-bit bus is used as byte
enables. The byte enables determine which byte paths of the full
32-bit data bus carry meaningful data. CC/BE0 applies to byte 0
(CAD7−CAD0), CC/BE1 applies to byte 1 (CAD15−CAD8),
CC/BE2 applies to byte 2 (CAD23−CAD16), and CC/BE3 applies to
byte 3 (CAD31−CAD24).
I/O PCII7 PCIO7 VCCA/
VCCB
A_CPAR G10 B_CPAR K13
CardBus parity. In all CardBus read and write cycles, the controller
calculates even parity across the CAD and CC/BE buses. As an
initiator during CardBus cycles, the controller outputs CPAR with a
one-CCLK delay. As a target during CardBus cycles, the controller
compares its calculated parity to the parity indicator of the initiator;
a compare error results in a parity error assertion.
I/O PCII7 PCIO7 VCCA/
VCCB
†These terminals are reserved for the PCI6611 and PCI6411 controllers.
2−24
Table 2−14. CardBus PC Card Interface Control Terminals
If any CardBus PC Card interface control terminal is unused, then the terminal may be left floating.
SKT A TERMINAL SKT B TERMINAL†
DESCRIPTION
I/O
INPUT
OUTPUT
PU/
POWER
NAME NO. NAME NO. DESCRIPTION
I/O
TYPE INPUT OUTPUT
PU/
PD
POWER
RAIL
A_CAUDIO A02 B_CAUDIO C17
CardBus audio. CAUDIO is a digital input signal from
a PC Card to the system speaker. The controller
supports the binary audio mode and outputs a binary
signal from the card to SPKROUT.
I PCII4 PCIO4 PU3 VCCA/
VCCB
A_CBLOCK E10 B_CBLOCK J19 CardBus lock. CBLOCK is used to gain exclusive
access to a target. I/O PCII4 PCIO4 PU3 VCCA/
VCCB
A_CCD1
C15
B_CCD1
N13
CardBus detect 1 and CardBus detect 2. CCD1 and
CCD2 are used in conjunction with CVS1 and CVS2
I
TTLI2
PU4
A_CCD1
A_CCD2
C15
E05
B_CCD1
B_CCD2
N13
B17
CCD2 are used in conjunction with CVS1 and CVS2
to identify card insertion and interrogate cards to
determine the operating voltage and card type.
I TTLI2 PU4
A_CDEVSEL C09 B_CDEVSEL H19
CardBus device select. The controller asserts
CDEVSEL to claim a CardBus cycle as the target
device. As a CardBus initiator on the bus, the
controller monitors CDEVSEL until a target responds.
If no target responds before timeout occurs, then the
controller terminates the cycle with an initiator abort.
I/O PCII4 PCIO4 PU3 VCCA/
VCCB
A_CFRAME C08 B_CFRAME G19
CardBus cycle frame. CFRAME is driven by the
initiator of a CardBus bus cycle. CFRAME is asserted
to indicate that a bus transaction is beginning, and
data transfers continue while this signal is asserted.
When CFRAME is deasserted, the CardBus bus
transaction is in the final data phase.
I/O PCII7 PCIO7 VCCA/
VCCB
A_CGNT B09 B_CGNT J15
CardBus bus grant. CGNT is driven by the controller
to grant a CardBus PC Card access to the CardBus
bus after the current data transaction has been
completed.
O PCII7 PCIO7 VCCA/
VCCB
A_CINT C04 B_CINT B19 CardBus interrupt. CINT is asserted low by a CardBus
PC Card to request interrupt servicing from the host. I PCII4 PCIO4 PU3 VCCA/
VCCB
A_CIRDY B08 B_CIRDY J13
CardBus initiator ready. CIRDY indicates the ability of
the CardBus initiator to complete the current data
phase of the transaction. A data phase is completed
on a rising edge of CCLK when both CIRDY and
CTRDY are asserted. Until CIRDY and CTRDY are
both sampled asserted, wait states are inserted.
I/O PCII4 PCIO4 PU3 VCCA/
VCCB
A_CPERR F10 B_CPERR J18
CardBus parity error. CPERR reports parity errors
during CardBus transactions, except during special
cycles. It is driven low by a target two clocks following
the data cycle during which a parity error is detected.
I/O PCII4 PCIO4 PU3 VCCA/
VCCB
A_CREQ E07 B_CREQ E18 CardBus request. CREQ indicates to the arbiter that
the CardBus PC Card desires use of the CardBus bus
as an initiator. I PCII4 PCIO4 PU3 VCCA/
VCCB
A_CSERR B03 B_CSERR B18
CardBus system error. CSERR reports address parity
errors and other system errors that could lead to
catastrophic results. CSERR is driven by the card
synchronous to CCLK, but deasserted by a weak
pullup; deassertion may take several CCLK periods.
The controller can report CSERR to the system by
assertion of SERR on the PCI interface.
I PCII4 PCIO4 PU3 VCCA/
VCCB
†These terminals are reserved for the PCI6611 and PCI6411 controllers.
2−25
Table 2−14. CardBus PC Card Interface Control Terminals (Continued)
SKT A TERMINAL SKT B TERMINAL†
DESCRIPTION
I/O
INPUT
OUTPUT
PU/
POWER
NAME NO. NAME NO. DESCRIPTION
I/O
TYPE INPUT OUTPUT
PU/
PD
POWER
RAIL
A_CSTOP A09 B_CSTOP J17
CardBus stop. CSTOP is driven by a CardBus target
to request the initiator to stop the current CardBus
transaction. CSTOP is used for target disconnects,
and is commonly asserted by target devices that do
not support burst data transfers.
I/O PCII4 PCIO4 PU3 VCCA/
VCCB
A_CSTSCHG B02 B_CSTSCHG F14 CardBus status change. CSTSCHG alerts the system
to a change in the card status, and is used as a
wake-up mechanism. I PCII6 SW1 VCCA/
VCCB
A_CTRDY A08 B_CTRDY H17
CardBus target ready. CTRDY indicates the ability of
the CardBus target to complete the current data
phase of the transaction. A data phase is completed
on a rising edge of CCLK, when both CIRDY and
CTRDY are asserted; until this time, wait states are
inserted.
I/O PCII1 PCIO1 PU5 VCCA/
VCCB
A_CVS1
A_CVS2 A03
E08 B_CVS1
B_CVS2 C18
F19
CardBus voltage sense 1 and CardBus voltage sense
2. CVS1 and CVS2 are used in conjunction with
CCD1 and CCD2 to identify card insertion and
interrogate cards to determine the operating voltage
and card type.
I/O TTLI2 TTLO1 PU4 VCCA/
VCCB
†These terminals are reserved for the PCI6611 and PCI6411 controllers.
2−26
Table 2−15. Reserved Terminals
TERMINAL
DESCRIPTION
PIN STRAPPING
NAME NO. DESCRIPTION PIN STRAPPING
RSVD R19, U15, U17,
U18, V15, V18,
W15, W18 Reserved Float
RSVD P15, R12, R18,
U13, V13, V14,
V16, W14, W16 Reserved Tie to GND
RSVD M11 Reserved Pullup to VCC through 1-kΩ resistor
RSVD U19 Reserved Pull directly to VCC
Table 2−16. SD/MMC Terminals
If any SD/MMC terminal is unused, then the terminal may be left floating.
TERMINAL
DESCRIPTION
I/O
INPUT
OUTPUT
PU/
POWER
EXTERNAL
NAME NO. DESCRIPTION
I/O
TYPE INPUT OUTPUT
PU/
PD
POWER
RAIL
EXTERNAL
COMPONENTS
MC_PWR_CTRL_0
MC_PWR_CTRL_1
F01
F02 Media card power control for flash media sockets. O LVCO1 Power switch or
FET to turn power
on to FM socket
SD_CD E03 SD/MMC card detect. This input is asserted when
SD/MMC cards are inserted. I LVCI1 PU2 VCC
SD_CLK J05, G05 SD flash clock. This output provides the SD/MMC
clock, which operates at 16 MHz. I/O TTLO2 SW2 VCC
SD_CMD J03, F03 SD flash command. This signal provides the SD
command per the SD Memory Card Specifications.I/O TTLI2 TTLO2 SW2 VCC
SD_DAT3
SD_DAT2
SD_DAT1
SD_DAT0
J02, H05
J01, G03
J06, G02
H03, G01
SD flash data [3:0]. These signals provide the SD
data path per the SD Memory Card Specifications.I/O TTLI2 TTLO2 SW2 VCC
SD_WP H07 SD write protect data. This signal indicates that the
media inserted in the socket is write protected. I TTLI2 SW2 VCC
Table 2−17. Memory Stick/PRO Terminals
If any Memory Stick/PRO terminal is unused, then the terminal may be left floating.
TERMINAL
DESCRIPTION
I/O
INPUT
OUTPUT
PU/
POWER
EXTERNAL
NAME NO. DESCRIPTION
I/O
TYPE INPUT OUTPUT
PU/
PD
POWER
RAIL
EXTERNAL
COMPONENTS
MC_PWR_CTRL_0
MC_PWR_CTRL_1
F01
F02 Media card power control for flash media sockets. O LVCO1 Power switch or
FET to turn power
on to FM socket
MS_BS F03 Memory Stick bus state. This signal provides Memory
Stick bus state information. I/O TTLO2 SW2 VCC
MS_CD F05 Media Card detect. This input is asserted when a
Memory Stick or Memory Stick Pro media is inserted. I LVCI1 PU2 VCC
MS_CLK G05 Memory Stick clock. This output provides the MS clock,
which operates at 16 MHz. I/O TTLO2 SW2 VCC
MS_DATA3
MS_DATA2
MS_DATA1
H05
G03
G02
Memory Stick data [3:1]. These signals provide the
Memory Stick data path. I/O TTLI2 TTLO2 SW2 VCC
MS_SDIO (DATA0) G01 Memory Stick serial data I/O. This signal provides
Memory Stick data input/output. Memory Stick data 0. I/O TTLI2 TTLO2 SW2 VCC
2−27
Table 2−18. Smart Media/XD Terminals
If any Smart Media/XD terminal is unused, then the terminal may be left floating.
TERMINAL
DESCRIPTION
I/O
INPUT
OUTPUT
PU/
POWER
EXTERNAL
NAME NO. DESCRIPTION
I/O
TYPE INPUT OUTPUT
PU/
PD
POWER
RAIL
EXTERNAL
PARTS
MC_PWR_CTRL_0
MC_PWR_CTRL_1
F01
F02 Media card power control for flash media sockets. O LVCO1 Power switch or
FET to turn power
on to FM socket
SM_ALE J03
SmartMedia address latch enable. This signal
functions as specified in the SmartMedia
specification, and is used to latch addresses
passed over SM_D7−SM_D0.
O TTLO2 SW2 VCC
SM_CD F06 SmartMedia card detect. This input is asserted
when SmartMedia cards are inserted. I LVCI1 PU2 VCC
SM_CE H07
SmartMedia card enable. This signal functions as
specified in the SmartMedia specification, and is
used to enable the media for a pending
transaction.
O TTLO2 SW2 VCC
SM_CLE J07
SmartMedia command latch enable. This signal
functions as specified in the SmartMedia
specification, and is used to latch commands
passed over SM_D7−SM_D0.
O TTLO2 SW2 VCC
SM_D7
SM_D6
SM_D5
SM_D4
SM_D3
SM_D2
SM_D1
SM_D0
J02
J01
J06
H03
H05
G03
G02
G01
SmartMedia data terminals. These signals pass
data to and from the SmartMedia, and functions
as specified in the SmartMedia specifications. I/O TTLI2 TTLO2 SW2 VCC
SM_EL_WP G05 SmartMedia electrical write protect. O TTLO2 SW2 VCC
SM_PHYS_WP K02 SmartMedia physical write protect. This input
comes from the write protect tab of the
SmartMedia card. I PCII5 PCIO5 SW3
SM_RE J05 SmartMedia read enable. This signal functions as
specified in the SmartMedia specification, and is
used to latch a read transfer from the card. O TTLO2 SW2 VCC
SM_R/B K01 SmartMedia read/busy. This signal functions as
specified in the SmartMedia specification, and is
used to pace data transfers to the card. I PCII5 PCIO5 SW3 VCC
SM_WE F03 SmartMedia write enable. This signal functions as
specified in the SmartMedia specification, and is
used to latch a write transfer to the card. O TTLO2 SW2 VCC
2−28
Table 2−19. Smart Card Terminals †
If any Smart Card terminal is unused, then the terminal may be left floating, except for SC_VCC_5V which must be
connected to 5 V.
TERMINAL
DESCRIPTION
I/O
INPUT
OUTPUT
PU/
POWER
EXTERNAL
NAME NO. DESCRIPTION
I/O
TYPE INPUT OUTPUT
PU/
PD
POWER
RAIL
EXTERNAL
PARTS
SC_CD L02 Smart Card card detect. This input is asserted when Smart
Cards are inserted. I TTLI2 SW2 VCC
SC_CLK K05 Smart Card clock. The controller drives a 3-MHz clock to the
Smart Card interface when enabled. O PCIO8
22 kΩ resistor to
GND
68 pF capacitor
to GND
SC_DATA L01 Smart Card data input/output I/O PCII5 PCIO5 SW3
SC_OC L03 Smart Card overcurrent. This input comes from the Smart
Card power switch. I LVCI1 PU2 5 V
SC_PWR_CTRL L05 Smart Card power control for the Smart Card socket. O LVCO1
Power switch or
FET to turn on
power to FM
socket
SC_FCB K02 Smart Card function code. The controller does not support
synchronous Smart Cards as specified in ISO/IEC 7816-10,
and this terminal is in a high-impedance state. I PCII5 PCIO5 SW3
SC_GPIO6
SC_GPIO5
SC_GPIO4
SC_GPIO3
SC_GPIO2
SC_GPIO1
SC_GPIO0
H03
J06
J01
J02
J03
J05
J07
Smart Card general-purpose I/O terminals. These signals
can be controlled by firmware and are used as control
signals for an external Smart Card interface chip or level
shifter.
I/O TTLI2 TTLO2 SW2 5 V
SC_RFU K01 Smart Card reserved. This terminal is in a high-impedance
state. I PCII5 PCIO5 SW3 5 V
SC_RST K03 Smart Card This signal starts and stops the Smart Card
reset sequence. The controller asserts this reset when
requested by the host. O PCIO6
SC_VCC_5V K07 Smart Card power terminal PWR 1 kΩ resistor to
5 V
†These terminals are reserved for the PCI6421 and PCI6411 controllers.
3−1
3 Feature/Protocol Descriptions
The following sections give an overview of the PCI6x21/PCI6x11 controller. Figure 3−1 shows the connections to the
PCI6x21/PCI6x11 controller. The PCI interface includes all address/data and control signals for PCI protocol. The
interrupt interface includes terminals for parallel PCI, parallel ISA, and serialized PCI and ISA signaling.
PCI Bus
PCI6x21/
PCI6x11
EEPROM
Power Switch
SD/MMC
PC
Card/
UltraMedia
Card
Power
Switch
PC
Card/
UltraMedia
Card
Power Switch
SD/MMC
MS/MSPRO
SM/xD
Figure 3−1. PCI6x21/PCI6x11 System Block Diagram
3.1 Power Supply Sequencing
The PCI6x21/PCI6x11 controller contains 3.3-V I/O buffers with 5-V tolerance requiring a core power supply and
clamp voltages. The core power supply is always 1.5 V. The clamp voltages can be either 3.3 V or 5 V, depending
on the interface. The following power-up and power-down sequences are recommended.
The power-up sequence is:
1. Power core 1.5 V.
2. Apply the I/O voltage.
3. Apply the analog voltage.
4. Apply the clamp voltage.
The power-down sequence is:
1. Remove the clamp voltage.
2. Remove the analog voltage.
3. Remove the I/O voltage.
4. Remove power from the core.
NOTE: If the voltage regulator is enabled, then steps 2, 3, and 4 of the power-up sequence
and steps 1, 2, and 3 of the power-down sequence all occur simultaneously.
3−2
3.2 I/O Characteristics
The PCI6x21/PCI6x11 controller meets the ac specifications of the PC Card Standard (release 8.1) and the PCI Local
Bus Specification. Figure 3−2 shows a 3-state bidirectional buffer. Section 10.2, Recommended Operating
Conditions, provides the electrical characteristics of the inputs and outputs.
Tied for Open Drain OE
Pad
VCCP
Figure 3−2. 3-State Bidirectional Buffer
3.3 Clamping Voltages
The clamping voltages are set to match whatever external environment the PCI6x21/PCI6x11 controller is interfaced
with: 3.3 V or 5 V. The I/O sites can be pulled through a clamping diode to a voltage rail that protects the core from
external signals. The core power supply is 1.5 V and is independent of the clamping voltages. For example, PCI
signaling can be either 3.3 V or 5 V, and the PCI6x21/PCI6x11 controller must reliably accommodate both voltage
levels. This is accomplished by using a 3.3-V I/O buffer that is 5-V tolerant, with the applicable clamping voltage
applied. If a system designer desires a 5-V PCI bus, then VCCP can be connected to a 5-V power supply.
3.4 Peripheral Component Interconnect (PCI) Interface
The PCI6x21/PCI6x11 controller is fully compliant with the PCI Local Bus Specification. The PCI6x21/PCI6x11
controller provides all required signals for PCI master or slave operation, and may operate in either a 5-V or 3.3-V
signaling environment by connecting the VCCP terminals to the desired voltage level. In addition to the mandatory
PCI signals, the PCI6x21/PCI6x11 controller provides the optional interrupt signals INTA, INTB, INTC, and INTD.
3.4.1 Device Resets
During the power-up sequence, GRST and PRST must be asserted. GRST can only be deasserted 100 µs after PCLK
is stable, and 2 ms after VCC is stable. PRST can be deasserted at the same time as GRST or any time thereafter.
3.4.2 Serial EEPROM I2C Bus
The PCI6x21/PCI6x11 controller offers many choices for modes of operation, and these choices are selected by
programming several configuration registers. For system board applications, these registers are normally
programmed through the BIOS routine. For add-in card and docking-station/port-replicator applications, the
PCI6x21/PCI6x11 controller provides a two-wire inter-integrated circuit (IIC or I2C) serial bus for use with an external
serial EEPROM.
The PCI6x21/PCI6x11 controller is always the bus master, and the EEPROM is always the slave. Either device can
drive the bus low, but neither device drives the bus high. The high level is achieved through the use of pullup resistors
on the SCL and SDA signal lines. The PCI6x21/PCI6x11 controller is always the source of the clock signal, SCL.
System designers who wish to load register values with a serial EEPROM must use pullup resistors on the SCL and
SDA terminals. If the PCI6x21/PCI6x11 controller detects a logic-high level on the SCL terminal at the end of GRST,
then it initiates incremental reads from the external EEPROM. Any size serial EEPROM up to the I2C limit of 16 Kbits
can be used, but only the first 96 bytes (from offset 00h to o f fset 5Fh) are required to configure the PCI6x21/PCI6x11
controller. Figure 3−3 shows a serial EEPROM application.
In addition to loading configuration data from an EEPROM, the PCI6x21/PCI6x11 I2C bus can be used to read and
write from other I2C serial devices. A system designer can control the I2C bus, using the PCI6x21/PCI6x11 controller
3−3
as bus master, by reading and writing PCI configuration registers. Setting bit 3 (SBDETECT) in the serial bus
control/status register (PCI offset B3h, see Section 4.50) causes the PCI6x21/PCI6x11 controller to route the SDA
and SCL signals to the SDA and SCL terminals, respectively. The read/write data, slave address, and byte addresses
are manipulated by accessing the serial bus data, serial bus index, and serial bus slave address registers (PCI offsets
B0h, B1h, and B2h; see Sections 4.47, 4.48, and 4.49, respectively).
EEPROM interface status information is communicated through the serial bus control and status register (PCI offset
B3h, see Section 4.50). Bit 3 (SBDETECT) in this register indicates whether or not the PCI6x21/PCI6x11 serial ROM
circuitry detects the pullup resistor on SCL. Any undefined condition, such as a missing acknowledge, results in bit
0 (ROM_ERR) being set. Bit 4 (ROMBUSY) is set while the subsystem ID register is loading (serial ROM interface
is busy).
The subsystem vendor ID for functions 2 and 3 is also loaded through EEPROM. The EEPROM load data goes to
all four functions from the serial EEPROM loader.
SCL
SDA
VCC
A0
A1
A2
SCL
SDA
PCI6x21/PCI6x11
Serial
ROM
Figure 3−3. Serial ROM Application
3.4.3 Functions 0 and 1 (CardBus) Subsystem Identification
The subsystem vendor ID register (PCI offset 40h, see Section 4.26) and subsystem ID register (PCI offset 42h, see
Section 4.27) make up a doubleword of PCI configuration space for functions 0 and 1. This doubleword register is
used for system and option card (mobile dock) identification purposes and is required by some operating systems.
Implementation of this unique identifier register is a PC 99/PC 2001 requirement.
The PCI6x21/PCI6x11 controller offers two mechanisms to load a read-only value into the subsystem registers. The
first mechanism relies upon the system BIOS providing the subsystem ID value. The default access mode to the
subsystem registers is read-only, but can be made read/write by clearing bit 5 (SUBSYSR W) in the system control
register (PCI offset 80h, see Section 4.29). Once this bit is cleared, the BIOS can write a subsystem identification
value into the registers at PCI offset 40h. The BIOS must set the SUBSYSRW bit such that the subsystem vendor
ID register and subsystem ID register are limited to read-only access. This approach saves the added cost of
implementing the serial electrically erasable programmable ROM (EEPROM).
In some conditions, such as in a docking environment, the subsystem vendor ID register and subsystem ID register
must be loaded with a unique identifier via a serial EEPROM. The PCI6x21/PCI6x11 controller loads the data from
the serial EEPROM after a reset of the primary bus. Note that the SUSPEND input gates the PCI reset from the entire
PCI6x21/PCI6x11 core, including the serial-bus state machine (see Section 3.8.5, Suspend Mode, for details on
using SUSPEND).
The PCI6x21/PCI6x11 controller provides a two-line serial-bus host controller that can interface to a serial EEPROM.
See Section 3.6, Serial EEPROM Interface, for details on the two-wire serial-bus controller and applications.
3−4
3.4.4 Function 3 (Flash Media) Subsystem Identification
The subsystem identification register is used for system and option card identification purposes. This register can
be initialized from the serial EEPROM or programmed via the subsystem access register at offset 50h in the PCI
configuration space (see Section 7.22, Subsystem Access Register). See Table 7−15 for a complete description of
the register contents.
The contents of the subsystem access register are aliased to the subsystem vendor ID and subsystem ID registers
at Function 3 PCI offsets 2Ch and 2Eh, respectively. See Table 7−15 for a complete description of the register
contents.
3.4.5 Function 4 SD Host Subsystem Identification
The subsystem identification register is used for system and option card identification purposes. This register can
be initialized from the serial EEPROM or programmed via the subsystem access register at offset 8Ch in the PCI
configuration space (see Section 8.23, Subsystem Access Register). See Table 8−16 for a complete description of
the register contents.
The contents of the subsystem access register are aliased to the subsystem vendor ID and subsystem ID registers
at Function 4 PCI offsets 2Ch and 2Eh, respectively. See Table 8−16 for a complete description of the register
contents.
3.4.6 Function 5 Smart Card Subsystem Identification
The subsystem identification register is used for system and option card identification purposes. This register can
be initialized from the serial EEPROM or programmed via the subsystem access register at offset 50h in the PCI
configuration space (see Section 9.23, Subsystem ID Alias Register). See Table 9−14 for a complete description of
the register contents.
The contents of the subsystem access register are aliased to the subsystem vendor ID and subsystem ID registers
at Function 5 PCI offsets 2Ch and 2Eh, respectively. See Table 9−14 for a complete description of the register
contents.
3.5 PC Card Applications
The PCI6x21/PCI6x11 controller supports all the PC Card features and applications as described below.
•Card insertion/removal and recognition per the PC Card Standard (release 8.1)
•Speaker and audio applications
•LED socket activity indicators
•PC Card controller programming model
•CardBus socket registers
3.5.1 PC Card Insertion/Removal and Recognition
The PC Card Standard (release 8.1) addresses the card-detection and recognition process through an interrogation
procedure that the socket must initiate on card insertion into a cold, nonpowered socket. Through this interrogation,
card voltage requirements and interface (16-bit versus CardBus) are determined.
The scheme uses the card-detect and voltage-sense signals. The configuration of these four terminals identifies the
card type and voltage requirements of the PC Card interface.
3−5
3.5.2 Low Voltage CardBus Card Detection
The card detection logic of the PCI6x21/PCI6x11 controller includes the detection of Cardbus cards with VCC = 3.3 V
and V PP = 1.8 V. The reporting of the 1.8-V CardBus card (VCC = 3.3 V, VPP = 1.8 V) is reported through the socket
present state register as follows based on bit 10 (12V_SW_SEL) in the general control register (PCI offset 86h, see
Section 4.31):
•If the 12V_SW_SEL bit is 0 (TPS2228 is used), then the 1.8-V CardBus card causes the 3VCARD bit in the
socket present state register to be set.
•If the 12V_SW_SEL bit is 1 (TPS2226 is used), then the 1.8-V CardBus card causes the XVCARD bit in
the socket present state register to be set.
3.5.3 UltraMedia Card Detection
The PCI6x21/PCI6x11 controller is capable of detecting all the UltraMedia devices defined by the PCMCIA Proposal
0262 – MultiMedia Cards, Secure Digital, Memory Stick devices, and Smart Card devices. The detection of these
devices is made possible through circuitry included in the PCI6x21/PCI6x11 controller and the adapters used to
interface these devices with the PC Card/CardBus sockets. No additional hardware requirements are placed on the
system designer in order to support these devices.
The PC Card Standard addresses the card detection and recognition process through an interrogation procedure that
the socket must initiate upon card insertion into a cold, unpowered socket. Through this interrogation, card voltage
requirements and interface type (16-bit vs. CardBus) are determined. The scheme uses the CD1, CD2, VS1, and VS2
signals (CCD1, CCD2, CVS1, CVS2 for CardBus). A PC Card designer connects these four terminals in a certain
configuration to indicate the type of card and its supply voltage requirements. The encoding scheme for this, defined
in the PC Card Standard, is shown in Table 3−1.
Table 3−1. PC Card—Card Detect and Voltage Sense Connections
CD2//CCD2 CD1//CCD1 VS2//CVS2 VS1//CVS1 Key Interface VCC VPP/VCORE
Ground Ground Open Open 5 V 16-bit PC Card 5 V Per CIS (VPP)
Ground Ground Open Ground 5 V 16-bit PC Card 5 V and 3.3 V Per CIS (VPP)
Ground Ground Ground Ground 5 V 16-bit PC Card 5 V, 3.3 V, and
X.X V Per CIS (VPP)
Ground Ground Open Ground LV 16-bit PC Card 3.3 V Per CIS (VPP)
Ground Connect to
CVS1 Open Connect to
CCD1 LV CardBus PC Card 3.3 V Per CIS (VPP)
Ground Ground Ground Ground LV 16-bit PC Card 3.3 V and X.X V Per CIS (VPP)
Connect to
CVS2 Ground Connect to
CCD2 Ground LV CardBus PC Card 3.3 V and X.X V Per CIS (VPP)
Connect to
CVS1 Ground Ground Connect to
CCD2 LV CardBus PC Card 3.3 V, X.X V,
and Y.Y V Per CIS (VPP)
Ground Ground Ground Open LV 16-bit PC Card X.X V Per CIS (VPP)
Connect to
CVS2 Ground Connect to
CCD2 Open LV CardBus PC Card 3.3 V 1.8 V (VCORE)
Ground Connect to
CVS2 Connect to
CCD1 Open LV CardBus PC Card X.X V and Y.Y V Per CIS (VPP)
Connect to
CVS1 Ground Open Connect to
CCD2 LV CardBus PC Card Y.Y V Per CIS (VPP)
Ground Connect to
CVS1 Ground Connect to
CCD1 LV UltraMedia Per query terminals
Ground Connect to
CVS2 Connect to
CCD1 Ground Reserved Reserved
3−6
3.5.4 Flash Media Card Detection
The PCI6x21/PCI6x11 controller detects an MMC/SD card insertion through the MC_CD_0 terminal. When this
terminal is 0, an MMC/SD card is inserted in the socket. The PCI6x21/PCI6x11 controller debounces the MC_CD_0
signal such that instability of the signal does not cause false card insertions. The debounce time is approximately 50
ms. The MC_CD_0 signal is not debounced on card removals. The filtered MC_CD_0 signal is used in the MMC/SD
card detection and power control logic.
The MMC/SD card detection and power control logic contains three main states:
•Socket empty, power off
•Card inserted, power off
•Card inserted, power on
The PCI6x21/PCI6x11 controller detects a Memory Stick card insertion through the MC_CD_1 terminal. When this
terminal is 0, a Memory Stick card is inserted in the socket. The PCI6x21/PCI6x11 controller debounces the
MC_CD_1 signal such that instability of the signal does not cause false card insertions. The debounce time is
approximately 50 ms. The MC_CD_1 signal is not debounced on card removals. The filtered MC_CD_1 signal is used
in the Memory Stick card detection and power control logic.
The Memory Stick card detection and power control logic contains three main states:
•Socket empty, power off
•Card inserted, power off
•Card inserted, power on
3.5.5 Power Switch Interface
The power switch interface of the PCI6x21/PCI6x11 controller is a 3-pin serial interface. This 3-pin interface is
implemented such that the PCI6x21/PCI6x11 controller can connect to both the TPS2226 and TPS2228 power
switches. Bit 10 (12V_SW_SEL) in the general control register (PCI offset 86h, see Section 4.31) selects the power
switch that is implemented. The PCI6x21/PCI6x11 controller defaults to use the control logic for the TPS2228 power
switch. See Table 3−2 and Table 3−5 below for the power switch control logic.
Table 3−2. TPS2228 Control Logic—xVPP/VCORE
AVPP/VCORE CONTROL SIGNALS OUTPUT
V_AVPP/VCORE
BVPP/VCORE CONTROL SIGNALS OUTPUT
V_BVPP/VCORE
D8(SHDN) D0 D1 D9
OUTPUT
V_AVPP/VCORE D8(SHDN) D4 D5 D10
OUTPUT
V_BVPP/VCORE
1 0 0 X 0 V 1 0 0 X 0 V
1 0 1 0 3.3 V 1 0 1 0 3.3 V
1 0 1 1 5 V 1 0 1 1 5 V
1 1 0 X Hi-Z 1 1 0 X Hi-Z
1 1 1 0 Hi-Z 1 1 1 0 Hi-Z
1 1 1 1 1.8 V 1 1 1 1 1.8 V
0 X X X Hi-Z 0 X X X Hi-Z
Table 3−3. TPS2228 Control Logic—xVCC
AVCC CONTROL SIGNALS OUTPUT
V_AVCC
BVCC CONTROL SIGNALS OUTPUT
V_BVCC
D8(SHDN) D3 D2
OUTPUT
V_AVCC D8(SHDN) D6 D7
OUTPUT
V_BVCC
1 0 0 0 V 1 0 0 0 V
1 0 1 3.3 V 1 0 1 3.3 V
1 1 0 5 V 1 1 0 5 V
1 1 1 0 V 1 1 1 0 V
0 X X Hi-Z 0 X X Hi-Z
3−7
Table 3−4. TPS2226 Control Logic—xVPP
AVPP CONTROL SIGNALS OUTPUT
V_AVPP
BVPP CONTROL SIGNALS OUTPUT
V_BVPP
D8(SHDN) D0 D1 D9
OUTPUT
V_AVPP D8(SHDN) D4 D5 D10
OUTPUT
V_BVPP
1 0 0 X 0 V 1 0 0 X 0 V
1 0 1 0 3.3 V 1 0 1 0 3.3 V
1 0 1 1 5 V 1 0 1 1 5 V
1 1 0 X 12 V 1 1 0 X 12 V
1 1 1 X Hi-Z 1 1 1 X Hi-Z
0 X X X Hi-Z 0 X X X Hi-Z
Table 3−5. TPS2226 Control Logic—xVCC
AVCC CONTROL SIGNALS OUTPUT
V_AVCC
BVCC CONTROL SIGNALS OUTPUT
V_BVCC
D8(SHDN) D3 D2
OUTPUT
V_AVCC D8(SHDN) D6 D7
OUTPUT
V_BVCC
1 0 0 0 V 1 0 0 0 V
1 0 1 3.3 V 1 0 1 3.3 V
1 1 0 5 V 1 1 0 5 V
1 1 1 0 V 1 1 1 0 V
0 X X Hi-Z 0 X X Hi-Z
3.5.6 Internal Ring Oscillator
The internal ring oscillator provides an internal clock source for the PCI6x21/PCI6x11 controller so that neither the
PCI clock nor an external clock is required in order for the PCI6x21/PCI6x11 controller to power down a socket or
interrogate a PC Card. This internal oscillator, operating nominally at 16 kHz, is always enabled.
3.5.7 Integrated Pullup Resistors for PC Card Interface
The PC Card Standard requires pullup resistors on various terminals to support both CardBus and 16-bit PC Card
configurations. The PCI6x21/PCI6x11 controller has integrated all of these pullup resistors and requires no additional
external components. The I/O buffer on the BVD1(STSCHG)/CSTSCHG terminal has the capability to switch to an
internal pullup resistor when a 16-bit PC Card is inserted, or switch to an internal pulldown resistor when a CardBus
card is inserted. This prevents inadvertent CSTSCHG events. The pullup resistor requirements for the various
UltraMedia interfaces are either included in the UltraMedia cards (or the UltraMedia adapter) or are part of the existing
PCMCIA architecture. The PCI6x21/PCI6x11 controller does not require any additional components for UltraMedia
support.
3.5.8 SPKROUT and CAUDPWM Usage
The SPKROUT terminal carries the digital audio signal from the PC Card to the system. When a 16-bit PC Card is
configured for I/O mode, the BVD2 terminal becomes the SPKR input terminal from the card. This terminal, in
CardBus applications, is referred to as CAUDIO. SPKR passes a TTL-level binary audio signal to the
PCI6x21/PCI6x11 controller. The CardBus CAUDIO signal also can pass a single-amplitude binary waveform as well
as a PWM signal. The binary audio signal from each PC Card sockets is enabled by bit 1 (SPKROUTEN) of the card
control register (PCI offset 91h, see Section 4.38).
Older controllers support CAUDIO in binary or PWM mode, but use the same output terminal (SPKROUT). Some
audio chips may not support both modes on one terminal and may have a separate terminal for binary and PWM.
The PCI6x21/PCI6x11 implementation includes a signal for PWM, CAUDPWM, which can be routed to an MFUNC
terminal. Bit 2 (AUD2MUX), located in the card control register, is programmed to route a CardBus CAUDIO PWM
terminal to CAUDPWM. See Section 4.36, Multifunction Routing Register, for details on configuring the MFUNC
terminals.
Figure 3−4 illustrates the SPKROUT connection.
3−8
Speaker
Subsystem
BINARY_SPKR
System
Core Logic
PCI6x21/
PCI6x11 CAUDPWM
SPKROUT
PWM_SPKR
Figure 3−4. SPKROUT Connection to Speaker Driver
3.5.9 LED Socket Activity Indicators
The socket activity LEDs are provided to indicate when a PC Card is being accessed. The LEDA1 and LEDA2 signals
can be routed to the multifunction terminals. When configured for LED outputs, these terminals output an active high
signal to indicate socket activity. LEDA1 indicates socket A (card A) activity, and LEDA2 indicates socket B (card B)
activity. The LED_SKT output indicates socket activity to either socket A or socket B. See Section 4.36, Multifunction
Routing Status Register, for details on configuring the multifunction terminals.
The active-high LED signal is driven for 64 ms. When the LED is not being driven high, it is driven to a low state. Either
of the two circuits shown in Figure 3−5 can be implemented to provide LED signaling, and the board designer must
implement the circuit that best fits the application.
The LED activity signals are valid when a card is inserted, powered, and not in reset. For PC Card-16, the LED activity
signals are pulsed when READY(IREQ) is low. For CardBus cards, the LED activity signals are pulsed if CFRAME,
IRDY, or CREQ are active.
PCI6x21/
PCI6x11
Current Limiting
R ≈ 150 Ω
Socket A
LED
MFUNCx Current Limiting
R ≈ 150 Ω
Socket B
LED
MFUNCy
Figure 3−5. Two Sample LED Circuits
As indicated, the LED signals are driven for a period of 64 ms by a counter circuit. To avoid the possibility of the LEDs
appearing to be stuck when the PCI clock is stopped, the LED signaling is cut off when the SUSPEND signal is
asserted, when the PCI clock is to be stopped during the clock run protocol, or when in the D2 or D1 power state.
If any additional socket activity occurs during this counter cycle, then the counter is reset and the LED signal remains
driven. If socket activity is frequent (at least once every 64 ms), then the LED signals remain driven.
3.5.10 CardBus Socket Registers
The PCI6x21/PCI6x11 controller contains all registers for compatibility with the PCI Local Bus Specification and the
PC Card Standard. These registers, which exist as the CardBus socket registers, are listed in Table 3−6.
3−9
Table 3−6. CardBus Socket Registers
REGISTER NAME OFFSET
Socket event 00h
Socket mask 04h
Socket present state 08h
Socket force event 0Ch
Socket control 10h
Reserved 14h−1Ch
Socket power management 20h
3.5.11 48-MHz Clock Requirements
The PCI6x21/PCI6x11 controller is designed to use an external 48-MHz clock connected to the CLK_48 terminal to
provide the reference for an internal oscillator circuit. This oscillator in turn drives a PLL circuit that generates the
various clocks required for the flash media function (Function 3) of the PCI6x21/PCI6x11 controller.
The 48-MHz clock must maintain a frequency of 48 MHz ± 0.8% over normal operating conditions. This clock must
maintain a duty cycle of 40% − 60%. The PCI6x21/PCI6x11 controller requires that the 48-MHz clock be running and
stable (a minimum of 10 clock pulses) before a GRST deassertion.
The following are typical specifications for crystals used with the PCI6x21/PCI6x11 controller in order to achieve the
required frequency accuracy and stability.
•Crystal mode of operation: Fundamental
•Frequency tolerance @ 25°C: Total frequency variation for the complete circuit is ±100 ppm. A crystal with
±30 ppm frequency tolerance is recommended for adequate margin.
•Frequency stability (over temperature and age): A crystal with ±30 ppm frequency stability is recommended
for adequate margin.
NOTE: The total frequency variation must be kept below ±100 ppm from nominal with some
allowance for error introduced by board and device variations. Trade-offs between frequency
tolerance and stability may be made as long as the total frequency variation is less than
±100 ppm. For example, the frequency tolerance of the crystal may be specified at 50 ppm and
the temperature tolerance may be specified at 30 ppm to give a total of 80 ppm possible
variation due to the crystal alone. Crystal aging also contributes to the frequency variation.
3.6 Serial EEPROM Interface
The PCI6x21/PCI6x11 controller has a dedicated serial bus interface that can be used with an EEPROM to load
certain registers in the PCI6x21/PCI6x11 controller. The EEPROM is detected by a pullup resistor on the SCL
terminal. See Table 3−8 for the EEPROM loading map.
3.6.1 Serial-Bus Interface Implementation
The PCI6x21/PCI6x11 controller drives SCL at nearly 100 kHz during data transfers, which is the maximum specified
frequency for standard mode I2C. The serial EEPROM must be located at address A0h.
Some serial device applications may include PC Card power switches, card ejectors, or other devices that may
enhance the user’s PC Card experience. The serial EEPROM device and PC Card power switches are discussed
in the sections that follow.
3.6.2 Accessing Serial-Bus Devices Through Software
The PCI6x21/PCI6x11 controller provides a programming mechanism to control serial bus devices through software.
The programming is accomplished through a doubleword of PCI configuration space at offset B0h. Table 3−7 lists
the registers used to program a serial-bus device through software.
3−10
Table 3−7. PCI6x21/PCI6x11 Registers Used to Program Serial-Bus Devices
PCI OFFSET REGISTER NAME DESCRIPTION
B0h Serial-bus data Contains the data byte to send on write commands or the received data byte on read commands.
B1h Serial-bus index The content of this register is sent as the word address on byte writes or reads. This register is not used
in the quick command protocol.
B2h Serial-bus slave
address Write transactions to this register initiate a serial-bus transaction. The slave device address and the
R/W command selector are programmed through this register.
B3h Serial-bus control
and status Read data valid, general busy, and general error status are communicated through this register. In
addition, the protocol-select bit is programmed through this register.
3.6.3 Serial-Bus Interface Protocol
The SCL and SDA signals are bidirectional, open-drain signals and require pullup resistors as shown in Figure 3−3.
The PCI6x21/PCI6x11 controller, which supports up to 100-Kb/s data-transfer rate, is compatible with standard mode
I2C using 7-bit addressing.
All data transfers are initiated by the serial bus master. The beginning of a data transfer is indicated by a start
condition, which is signaled when the SDA line transitions to the low state while SCL is in the high state, as shown
in Figure 3−6. The end of a requested data transfer is indicated by a stop condition, which is signaled by a low-to-high
transition of SDA while SCL is in the high state, as shown in Figure 3−6. Data on SDA must remain stable during the
high state of the SCL signal, as changes on the SDA signal during the high state of SCL are interpreted as control
signals, that is, a start or a stop condition.
SDA
SCL
Start
Condition Stop
Condition Change of
Data Allowed
Data Line Stable,
Data Valid
Figure 3−6. Serial-Bus Start/Stop Conditions and Bit Transfers
Data is transferred serially in 8-bit bytes. The number of bytes that may be transmitted during a data transfer is
unlimited; however, each byte must be completed with an acknowledge bit. An acknowledge (ACK) is indicated by
the receiver pulling the SDA signal low, so that it remains low during the high state of the SCL signal. Figure 3−7
illustrates the acknowledge protocol.
SCL From
Master 123 789
SDA Output
By Transmitter
SDA Output
By Receiver
Figure 3−7. Serial-Bus Protocol Acknowledge
3−11
The PCI6x21/PCI6x11 controller is a serial bus master; all other devices connected to the serial bus external to the
PCI6x21/PCI6x11 controller are slave devices. As the bus master, the PCI6x21/PCI6x11 controller drives the SCL
clock at nearly 100 kHz during bus cycles and places SCL in a high-impedance state (zero frequency) during idle
states.
Typically, the PCI6x21/PCI6x11 controller masters byte reads and byte writes under software control. Doubleword
reads are performed by the serial EEPROM initialization circuitry upon a PCI reset and may not be generated under
software control. See Section 3.6.4, Serial-Bus EEPROM Application, for details on how the PCI6x21/PCI6x11
controller automatically loads the subsystem identification and other register defaults through a serial-bus EEPROM.
Figure 3−8 illustrates a byte write. The PCI6x21/PCI6x11 controller issues a start condition and sends the 7-bit slave
device address and the command bit zero. A 0 in the R/W command bit indicates that the data transfer is a write. The
slave device acknowledges if it recognizes the address. If no acknowledgment is received by the PCI6x21/PCI6x11
controller, then an appropriate status bit is set in the serial-bus control/status register (PCI offset B3h, see
Section 4.50). The word address byte is then sent by the PCI6x21/PCI6x11 controller, and another slave
acknowledgment is expected. Then the PCI6x21/PCI6x11 controller delivers the data byte MSB first and expects a
final acknowledgment before issuing the stop condition.
Sb6 b4b5 b3 b2 b1 b0 0 b7 b6 b5 b4 b3 b2 b1 b0AA
Slave Address W ord Address
R/W
S/P = Start/Stop ConditionA = Slave Acknowledgement
b7 b6 b4b5 b3 b2 b1 b0 A P
Data Byte
Figure 3−8. Serial-Bus Protocol—Byte Write
Figure 3−9 illustrates a byte read. The read protocol is very similar to the write protocol, except the R/W command
bit must be set to 1 to indicate a read-data transfer. In addition, the PCI6x21/PCI6x11 master must acknowledge
reception of the read bytes from the slave transmitter. The slave transmitter drives the SDA signal during read data
transfers. The SCL signal remains driven by the PCI6x21/PCI6x11 master.
Sb6 b4b5 b3 b2 b1 b0 0 b7 b6 b5 b4 b3 b2 b1 b0AA
Slave Address Word Address
R/W
Sb6 b4b5 b3 b2 b1 b0 1 A
Slave Address
S/P = Start/Stop ConditionM = Master Acknowledgement
b7 b6 b4b5 b3 b2 b1 b0 M P
Data Byte
Start Restart R/W
A = Slave Acknowledgement
Stop
Figure 3−9. Serial-Bus Protocol—Byte Read
Figure 3−10 illustrates EEPROM interface doubleword data collection protocol.
3−12
S1 10 0 0 0 0 0 b7 b6 b5 b4 b3 b2 b1 b0AA
Slave Address Word Address
R/W
Data Byte 2 Data Byte 1 Data Byte 0 M PMM
M = Master Acknowledgement S/P = Start/Stop ConditionA = Slave Acknowledgement
Data Byte 3 M
S1 10 00001A
Restart R/W
Slave Address
Start
Figure 3−10. EEPROM Interface Doubleword Data Collection
3.6.4 Serial-Bus EEPROM Application
When the PCI bus is reset and the serial-bus interface is detected, the PCI6x21/PCI6x11 controller attempts to read
the subsystem identification and other register defaults from a serial EEPROM.
This format must be followed for the PCI6x21/PCI6x11 controller to load initializations from a serial EEPROM. All bit
fields must be considered when programming the EEPROM.
The serial EEPROM is addressed at slave address 1010 000b by the PCI6x21/PCI6x11 controller. All hardware
address bits for the EEPROM must be tied to the appropriate level to achieve this address. The serial EEPROM chip
in the sample application (Figure 3−10) assumes the 1010b high-address nibble. The lower three address bits are
terminal inputs to the chip, and the sample application shows these terminal inputs tied to GND.
3−13
Table 3−8. EEPROM Loading Map
SERIAL ROM
OFFSET BYTE DESCRIPTION
00h CardBus function indicator (00h)
01h Number of bytes (20h)
PCI 04h, command register, function 0, bits 8, 6−5, 2−0
02h [7]
Command
register, bit 8
[6]
Command
register, bit 6
[5]
Command
register, bit 5
[4:3]
RSVD [2]
Command
register, bit 2
[1]
Command
register, bit 1
[0]
Command
register, bit 0
PCI 04h, command register, function 1, bits 8, 6−5, 2−0
03h [7]
Command
register, bit 8
[6]
Command
register, bit 6
[5]
Command
register, bit 5
[4:3]
RSVD [2]
Command
register, bit 2
[1]
Command
register, bit 1
[0]
Command
register, bit 0
04h PCI 40h, subsystem vendor ID, byte 0
05h PCI 41h, subsystem vendor ID, byte 1
06h PCI 42h, subsystem ID, byte 0
07h PCI 43h, subsystem ID, byte 1
08h PCI 44h, PC Card 16-bit I/F legacy mode base address register, byte 0, bits 7−1
09h PCI 45h, PC Card 16-bit I/F legacy mode base address register, byte 1
0Ah PCI 46h, PC Card 16-bit I/F legacy mode base address register, byte 2
0Bh PCI 47h, PC Card 16-bit I/F legacy mode base address register, byte 3
0Ch PCI 80h, system control, function 0, byte 0, bits 6−0
0Dh PCI 80h, system control, function 1, byte 0, bit 2
0Eh PCI 81h, system control, byte 1, bits 7,6
0Fh Reserved nonloadable (PCI 82h, system control, byte 2)
10h PCI 83h, system control, byte 3, bits 7−2, 0
11h PCI 8Ch, MFUNC routing, byte 0
12h PCI 8Dh, MFUNC routing, byte 1
13h PCI 8Eh, MFUNC routing, byte 2
14h PCI 8Fh, MFUNC routing, byte 3
15h PCI 90h, retry status, bits 7, 6
16h PCI 91h, card control, bit 7
17h PCI 92h, device control, bits 6, 5, 3−0 (bit 0 must be programmed to 0)
18h PCI 93h, diagnostic, bits 4−0
19h PCI A2h, power-management capabilities, function 0, bit 15 (bit 7 of EEPROM offset 16h corresponds to bit 15)
1Ah PCI A2h, power-management capabilities, function 1, bit 15 (bit 7 of EEPROM offset 16h corresponds to bit 15)
1Bh CB Socket + 0Ch, function 0 socket force event, bit 27 (bit 3 of EEPROM offset 17h corresponds to bit 27)
1Ch CB Socket + 0Ch, function 1 socket force event, bit 27 (bit 3 of EEPROM offset 18h corresponds to bit 27)
1Dh ExCA 00h, ExCA identification and revision, bits 7−0
1Eh PCI 86h, general control, byte 0, bits 7−0
1Fh PCI 87h, general control, byte 1, bits 7, 6 (can only be set to 1 if bits 1:0 = 01), 4−0
20h PCI 89h, GPE enable, bits 7, 6, 4−0
21h PCI 8Bh, general-purpose output, bits 4−0
22h−3Ah Reserved
3−14
Table 3−8. EEPROM Loading Map (Continued)
SERIAL ROM
OFFSET BYTE DESCRIPTION
3Bh Flash media core function indicator (03h)
3Ch Number of bytes (05h)
3Dh PCI 2Ch, subsystem vendor ID, byte 0
3Eh PCI 2Dh, subsystem vendor ID, byte 1
3Fh PCI 2Eh, subsystem ID, byte 0
40h PCI 2Fh, subsystem ID, byte 1
41h PCI 4Ch, general control, bits 6−4, 2−0
42h SD host controller function indicator (03h)
43h Number of bytes (0Bh)
44h PCI 2Ch, subsystem vendor ID, byte 0
45h PCI 2Dh, subsystem vendor ID, byte 1
46h PCI 2Eh, subsystem ID, byte 0
47h PCI 2Fh, subsystem ID, byte 1
48h PCI 88h, general control bits 6−4, 0
49h PCI 94h, slot 0 3.3 V maximum current
4Ah PCI 98h, slot 1 3.3 V maximum current
4Bh PCI 9Ch, slot 2 3.3 V maximum current
4Ch Reserved (PCI A0h, slot 3 3.3 V maximum current)
4Dh Reserved (PCI A4h, slot 4 3.3 V maximum current)
4Eh Reserved (PCI A8h, slot 5 3.3 V maximum current)
4Fh PCI Smart Card function indicator (05h)
50h Number of bytes (0Eh)
51h PCI 09h, class code, byte 0
52h PCI 0Ah, class code, byte 1
53h PCI 0Bh, class code, byte 2
54h PCI 2Ch, subsystem vendor ID, byte 0
55h PCI 2Dh, subsystem vendor ID, byte 1
56h PCI 2Eh, subsystem ID, byte 0
57h PCI 2Fh, subsystem ID, byte 1
58h PCI 4Ch, general control bits 6−4
59h PCI 58h, Smart Card configuration 1, byte 0, bits 6−4, 2−0
5Ah PCI 59h, Smart Card configuration 1, byte 1, bits 6−4, 2−0
5Bh PCI 5Ah, Smart Card configuration 1, byte 2, bits 6−4, 2−0
5Ch PCI 5Bh, Smart Card configuration 1, byte 3, bits 7−4, 2−0
5Dh PCI 5Ch, Smart Card configuration 2, byte 0
5Eh PCI 5Dh, Smart Card configuration 2, byte 1
5Fh End-of-list indicator (80h)
3−15
3.7 Programmable Interrupt Subsystem
Interrupts provide a way for I/O devices to let the microprocessor know that they require servicing. The dynamic
nature of PC Cards and the abundance of PC Card I/O applications require substantial interrupt support from the
PCI6x21/PCI6x11 controller. The PCI6x21/PCI6x11 controller provides several interrupt signaling schemes to
accommodate the needs of a variety of platforms. The different mechanisms for dealing with interrupts in this
controller are based on various specifications and industry standards. The ExCA register set provides interrupt
control for some 16-bit PC Card functions, and the CardBus socket register set provides interrupt control for the
CardBus PC Card functions. The PCI6x21/PCI6x11 controller is, therefore, backward compatible with existing
interrupt control register definitions, and new registers have been defined where required.
The PCI6x21/PCI6x11 controller detects PC Card interrupts and events at the PC Card interface and notifies the host
controller using one of several interrupt signaling protocols. To simplify the discussion of interrupts in the
PCI6x21/PCI6x11 controller, PC Card interrupts are classified either as card status change (CSC) or as functional
interrupts.
The method by which any type of PCI6x21/PCI6x11 interrupt is communicated to the host interrupt controller varies
from system to system. The PCI6x21/PCI6x11 controller offers system designers the choice of using parallel PCI
interrupt signaling, parallel ISA-type IRQ interrupt signaling, or the IRQSER serialized ISA and/or PCI interrupt
protocol. It is possible to use the parallel PCI interrupts in combination with either parallel IRQs or serialized IRQs,
as detailed in the sections that follow. All interrupt signaling is provided through the seven multifunction terminals,
MFUNC0−MFUNC6.
3.7.1 PC Card Functional and Card Status Change Interrupts
PC Card functional interrupts are defined as requests from a PC Card application for interrupt service and are
indicated by asserting specially-defined signals on the PC Card interface. Functional interrupts are generated by
16-bit I/O PC Cards and by CardBus PC Cards.
Card status change (CSC)-type interrupts are defined as events at the PC Card interface that are detected by the
PCI6x21/PCI6x11 controller and may warrant notification of host card and socket services software for service. CSC
events include both card insertion and removal from PC Card sockets, as well as transitions of certain PC Card
signals.
Table 3−9 summarizes the sources of PC Card interrupts and the type of card associated with them. CSC and
functional interrupt sources are dependent on the type of card inserted in the PC Card socket. The four types of cards
that can be inserted into any PC Card socket are:
•16-bit memory card
•16-bit I/O card
•CardBus cards
•UltraMedia card
3−16
Table 3−9. Interrupt Mask and Flag Registers
CARD TYPE EVENT MASK FLAG
16-bit memory
Battery conditions (BVD1, BVD2) ExCA offset 05h/45h/805h bits 1 and 0 ExCA offset 04h/44h/804h bits 1 and 0
16-bit memory Wait states (READY) ExCA offset 05h/45h/805h bit 2 ExCA offset 04h/44h/804h bit 2
16-bit I/O Change in card status (STSCHG)ExCA offset 05h/45h/805h bit 0 ExCA offset 04h/44h/804h bit 0
16-bit I/O/
UltraMedia Interrupt request (IREQ)Always enabled PCI configuration offset 91h bit 0
All 16-bit PC
Cards/
Smart Card
adapters/
UltraMedia/
Flash Media
Power cycle complete ExCA offset 05h/45h/805h bit 3 ExCA offset 04h/44h/804h bit 3
Change in card status (CSTSCHG) Socket mask bit 0 Socket event bit 0
CardBus
Interrupt request (CINT)Always enabled PCI configuration offset 91h bit 0
CardBus
Power cycle complete Socket mask bit 3 Socket event bit 3
Card insertion or removal Socket mask bits 2 and 1 Socket event bits 2 and 1
Functional interrupt events are valid only for 16-bit I/O and CardBus cards; that is, the functional interrupts are not
valid for 16-bit memory cards. Furthermore, card insertion and removal-type CSC interrupts are independent of the
card type.
Table 3−10. PC Card Interrupt Events and Description
CARD TYPE EVENT TYPE SIGNAL DESCRIPTION
Battery conditions
CSC
BVD1(STSCHG)//CSTSCHG A transition on BVD1 indicates a change in the
PC Card battery conditions.
16-bit
memory
Battery conditions
(BVD1, BVD2) CSC BVD2(SPKR)//CAUDIO A transition on BVD2 indicates a change in the
PC Card battery conditions.
memory
Wait states
(READY) CSC READY(IREQ)//CINT A transition on READY indicates a change in the
ability of the memory PC Card to accept or provide
data.
16-bit I/O Change in card
status (STSCHG)CSC BVD1(STSCHG)//CSTSCHG The assertion of STSCHG indicates a status change
on the PC Card.
16-bit I/O/
UltraMedia Interrupt request
(IREQ)Functional READY(IREQ)//CINT The assertion of IREQ indicates an interrupt request
from the PC Card.
CardBus
Change in card
status (CSTSCHG) CSC BVD1(STSCHG)//CSTSCHG The assertion of CSTSCHG indicates a status
change on the PC Card.
CardBus Interrupt request
(CINT)Functional READY(IREQ)//CINT The assertion of CINT indicates an interrupt request
from the PC Card.
All PC Cards
/
Smart Card
adapters/
Card insertion
or removal CSC CD1//CCD1,
CD2//CCD2
A transition on either CD1//CCD1 or CD2//CCD2
indicates an insertion or removal of a 16-bit or
CardBus PC Card.
adapters/
UltraMedia/
Flash Media Power cycle
complete CSC N/A An interrupt is generated when a PC Card power-up
cycle has completed.
The naming convention for PC Card signals describes the function for 16-bit memory, I/O cards, and CardBus. For
example, READY(IREQ)//CINT includes READY for 16-bit memory cards, IREQ for 16-bit I/O cards, and CINT for
CardBus cards. The 16-bit memory card signal name is first, with the I/O card signal name second, enclosed in
parentheses. The CardBus signal name follows after a double slash (//).
The 1997 PC Card Standard describes the power-up sequence that must be followed by the PCI6x21/PCI6x11
controller when an insertion event occurs and the host requests that the socket VCC and VPP be powered. Upon
completion of this power-up sequence, the PCI6x21/PCI6x11 interrupt scheme can be used to notify the host system
(see Table 3−10), denoted by the power cycle complete event. This interrupt source is considered a
3−17
PCI6x21/PCI6x11 internal event, because it depends on the completion of applying power to the socket rather than
on a signal change at the PC Card interface.
3.7.2 Interrupt Masks and Flags
Host software may individually mask (or disable) most of the potential interrupt sources listed in Table 3−10 by setting
the appropriate bits in the PCI6x21/PCI6x11 controller. By individually masking the interrupt sources listed, software
can control those events that cause a PCI6x21/PCI6x11 interrupt. Host software has some control over the system
interrupt the PCI6x21/PCI6x11 controller asserts by programming the appropriate routing registers. The
PCI6x21/PCI6x11 controller allows host software to route PC Card CSC and PC Card functional interrupts to separate
system interrupts. Interrupt routing somewhat specific to the interrupt signaling method used is discussed in more
detail in the following sections.
When an interrupt is signaled by the PCI6x21/PCI6x11 controller, the interrupt service routine must determine which
of the events listed in Table 3−9 caused the interrupt. Internal registers in the PCI6x21/PCI6x11 controller provide
flags that report the source of an interrupt. By reading these status bits, the interrupt service routine can determine
the action to be taken.
Table 3−9 details the registers and bits associated with masking and reporting potential interrupts. All interrupts can
be masked except the functional PC Card interrupts, and an interrupt status flag is available for all types of interrupts.
Notice that there is not a mask bit to stop the PCI6x21/PCI6x11 controller from passing PC Card functional interrupts
through to the appropriate interrupt scheme. These interrupts are not valid until the card is properly powered, and
there must never be a card interrupt that does not require service after proper initialization.
Table 3−9 lists the various methods of clearing the interrupt flag bits. The flag bits in the ExCA registers (16-bit PC
Card-related interrupt flags) can be cleared using two different methods. One method is an explicit write of 1 to the
flag bit to clear and the other is by reading the flag bit register. The selection of flag bit clearing methods is made by
bit 2 (IFCMODE) in the ExCA global control register (ExCA of fset 1Eh/5Eh/81Eh, see Section 5.20), and defaults to
the flag-cleared-on-read method.
The CardBus-related interrupt flags can be cleared by an explicit write of 1 to the interrupt flag in the socket event
register (see Section 6.1). Although some of the functionality is shared between the CardBus registers and the ExCA
registers, software must not program the chip through both register sets when a CardBus card is functioning.
3.7.3 Using Parallel IRQ Interrupts
The seven multifunction terminals, MFUNC6−MFUNC0, implemented in the PCI6x21/PCI6x11 controller can be
routed to obtain a subset of the ISA IRQs. The IRQ choices provide ultimate flexibility in PC Card host interruptions.
To use the parallel ISA-type IRQ interrupt signaling, software must program the device control register (PCI offset
92h, see Section 4.39), to select the parallel IRQ signaling scheme. See Section 4.36, Multifunction Routing Status
Register, for details on configuring the multifunction terminals.
A system using parallel IRQs requires (at a minimum) one PCI terminal, INTA, to signal CSC events. This requirement
is dictated by certain card and socket-services software. The INTA requirement calls for routing the MFUNC0 terminal
for INTA signaling. The INTR TIE bit is used, in this case, to route socket interrupt events to INTA. This leaves (at a
maximum) six different IRQs to support legacy 16-bit PC Card functions.
As an example, suppose the six IRQs used by legacy PC Card applications are IRQ3, IRQ4, IRQ5, IRQ9, IRQ10,
and IRQ15. The multifunction routing status register must be programmed to a value of 0A9F 5432h. This value
routes the MFUNC0 terminal to INTA signaling and routes the remaining terminals as illustrated in Figure 3−11. Not
shown is that INTA must also be routed to the programmable interrupt controller (PIC), or to some circuitry that
provides parallel PCI interrupts to the host.
3−18
PCI6x21/PCI6x11 PIC
MFUNC1
MFUNC2
MFUNC3
MFUNC4
MFUNC5
MFUNC6
IRQ3
IRQ4
IRQ5
IRQ15
IRQ9
IRQ10
Figure 3−11. IRQ Implementation
Power-on software is responsible for programming the multifunction routing status register to reflect the IRQ
configuration of a system implementing the PCI6x21/PCI6x11 controller. The multifunction routing status register is
a global register that is shared between the four PCI6x21/PCI6x11 functions. See Section 4.36, Multifunction Routing
Status Register, for details on configuring the multifunction terminals.
The parallel ISA-type IRQ signaling from the MFUNC6−MFUNC0 terminals is compatible with the input signal
requirements of the 8259 PIC. The parallel IRQ option is provided for system designs that require legacy ISA IRQs.
Design constraints may demand more MFUNC6−MFUNC0 IRQ terminals than the PCI6x21/PCI6x11 controller
makes available.
3.7.4 Using Parallel PCI Interrupts
Parallel PCI interrupts are available when exclusively in parallel PCI interrupt/parallel ISA IRQ signaling mode, and
when only IRQs are serialized with the IRQSER protocol. The INTA, INTB, INTC, and INTD can be routed to MFUNC
terminals (MFUNC0, MFUNC1, MFUNC2, and MFUNC4). If bit 29 (INTR TIE) is set in the system control register (PCI
offset 80h, see Section 4.29), then INTA and INTB are tied internally. When the TIEALL bit is set, all four functions
return a value of 01h on reads from the interrupt pin register for both parallel and serial PCI interrupts.
The INTRTIE and TIEALL bits affect the read-only value provided through accesses to the interrupt pin register (PCI
offset 3Dh, see Section 4.24). Table 3−11 summarizes the interrupt signaling modes.
Table 3−11. Interrupt Pin Register Cross Reference
INTRTIE
Bit TIEALL
Bit
INTPIN
Function 0
(CardBus)
INTPIN
Function 1
(CardBus)
INTPIN
Function 3
(Flash Media)
INTPIN
Function 4
(SD Host)
INTPIN
Function 5
(Smart Card)
0 0 0x01 (INTA)0x02 (INTB)Determined by bits 6−5
(INT_SEL field) in flash
Determined by bits 6−5
(INT_SEL field) in SD host
Determined by bits 6−5
(INT_SEL field) in Smart
1 0 0x01 (INTA)0x01 (INTA)
(INT_SEL field) in flash
media general control
register (see Section 7.21)
(INT_SEL field) in SD host
general control register
(see Section 8.22)
(INT_SEL field) in Smart
Card general control
register (see Section 9.22)
X 1 0x01 (INTA)0x01 (INTA)0x01 (INTA)0x01 (INTA)0x01 (INTA)
3.7.5 Using Serialized IRQSER Interrupts
The serialized interrupt protocol implemented in the PCI6x21/PCI6x11 controller uses a single terminal to
communicate all interrupt status information to the host controller. The protocol defines a serial packet consisting of
a start cycle, multiple interrupt indication cycles, and a stop cycle. All data in the packet is synchronous with the PCI
clock. The packet data describes 16 parallel ISA IRQ signals and the optional 4 PCI interrupts INTA, INTB, INTC, and
INTD. For details on the IRQSER protocol, refer to the document Serialized IRQ Support for PCI Systems.
3.7.6 SMI Support in the PCI6x21/PCI6x11 Controller
The PCI6x21/PCI6x11 controller provides a mechanism for interrupting the system when power changes have been
made to the PC Card socket interfaces. The interrupt mechanism is designed to fit into a system maintenance
interrupt (SMI) scheme. SMI interrupts are generated by the PCI6x21/PCI6x11 controller, when enabled, after a write
cycle to either the socket control register (CB offset 10h, see Section 6.5) of the CardBus register set, or the ExCA
power control register (ExCA offset 02h/42h/802h, see Section 5.3) causes a power cycle change sequence to be
sent on the power switch interface.
3−19
The SMI control is programmed through three bits in the system control register (PCI offset 80h, see Section 4.29).
These bits are SMIROUTE (bit 26), SMISTATUS (bit 25), and SMIENB (bit 24). Table 3−12 describes the SMI control
bits function.
Table 3−12. SMI Control
BIT NAME FUNCTION
SMIROUTE This shared bit controls whether the SMI interrupts are sent as a CSC interrupt or as IRQ2.
SMISTAT This socket-dependent bit is set when an SMI interrupt is pending. This status flag is cleared by writing back a 1.
SMIENB When set, SMI interrupt generation is enabled. This bit is shared by functions 0 and 1.
If CSC SMI interrupts are selected, then the SMI interrupt is sent as the CSC on a per-socket basis. The CSC interrupt
can be either level or edge mode, depending upon the CSCMODE bit in the ExCA global control register (ExCA offset
1Eh/5Eh/81Eh, see Section 5.20).
If IRQ2 is selected by SMIROUTE, then the IRQSER signaling protocol supports SMI signaling in the IRQ2 IRQ/Data
slot. In a parallel ISA IRQ system, the support for an active low IRQ2 is provided only if IRQ2 is routed to either
MFUNC3 or MFUNC6 through the multifunction routing status register (PCI offset 8Ch, see Section 4.36).
3.8 Power Management Overview
In addition to the low-power CMOS technology process used for the PCI6x21/PCI6x11 controller, various features
are designed into the controller to allow implementation of popular power-saving techniques. These features and
techniques are as follows:
•Clock run protocol
•Cardbus PC Card power management
•16-bit PC Card power management
•Suspend mode
•Ring indicate
•PCI power management
•Cardbus bridge power management
•ACPI support
3−20
PCI Bus
PCI6x21/
PCI6x11
EEPROM
Power Switch
SD/MMC
PC
Card/
UltraMedia
Card
Power
Switch
PC
Card/
UltraMedia
Card
Power Switch
SD/MMC
MS/MSPRO
SM/xD
†The system connection to GRST is implementation-specific. GRST must be asserted on initial power up of the PCI6x21/PCI6x11 controller. PRST
must be asserted for subsequent warm resets.
Figure 3−12. System Diagram Implementing CardBus Device Class Power Management
3.8.1 Integrated Low-Dropout Voltage Regulator (LDO-VR)
The PCI6x21/PCI6x11 controller requires 1.5-V core voltage. The core power can be supplied by the
PCI6x21/PCI6x11 controller itself using the internal LDO-VR. The core power can alternatively be supplied by an
external power supply through the VR_PORT terminal. Table 3−13 lists the requirements for both the internal core
power supply and the external core power supply.
Table 3−13. Requirements for Internal/External 1.5-V Core Power Supply
SUPPLY VCC VR_EN VR_PORT NOTE
Internal 3.3 V GND 1.5-V output Internal 1.5-V LDO-VR is enabled. A 1.0-µF bypass capacitor is required on the VR_PORT
terminal for decoupling. This output is not for external use.
External 3.3 V VCC 1.5-V input Internal 1.5-V LDO-VR is disabled. An external 1.5-V power supply, of minimum 50-mA
capacity, is required. A 0.1-µF bypass capacitor on the VR_PORT terminal is required.
3.8.2 CardBus (Functions 0 and 1) Clock Run Protocol
The PCI CLKRUN feature is the primary method of power management on the PCI interface of the PCI6x21/PCI6x11
controller. CLKRUN signaling is provided through the MFUNC6 terminal. Since some chip sets do not implement
CLKRUN, this is not always available to the system designer, and alternate power-saving features are provided. For
details on the CLKRUN protocol see the PCI Mobile Design Guide.
The PCI6x21/PCI6x11 controller does not permit the central resource to stop the PCI clock under any of the following
conditions:
•Bit 1 (KEEPCLK) in the system control register (PCI offset 80h, see Section 4.29) is set.
•The 16-bit PC Card resource manager is busy.
•The PCI6x21/PCI6x11 CardBus master state machine is busy. A cycle may be in progress on CardBus.
3−21
•The PCI6x21/PCI6x11 master is busy. There may be posted data from CardBus to PCI in the
PCI6x21/PCI6x11 controller.
•Interrupts are pending.
•The CardBus CCLK for the socket has not been stopped by the PCI6x21/PCI6x11 CCLKRUN manager.
•PC Card interrogation is in progress.
The PCI6x21/PCI6x11 controller restarts the PCI clock using the CLKRUN protocol under any of the following
conditions:
•A 16-bit PC Card IREQ or a CardBus CINT has been asserted by either card.
•A CardBus CBWAKE (CSTSCHG) or 16-bit PC Card STSCHG/RI event occurs in the socket.
•A CardBus attempts to start the CCLK using CCLKRUN.
•A CardBus card arbitrates for the CardBus bus using CREQ.
•Bit 1 (KEEPCLK) in the system control register (PCI offset 80h, see Section 4.29) is set.
•Data is in any of the FIFOs (receive or transmit).
•The master state machine is busy.
•There are pending interrupts.
3.8.3 CardBus PC Card Power Management
The PCI6x21/PCI6x11 controller implements its own card power-management engine that can turn off the CCLK to
a socket when there is no activity to the CardBus PC Card. The PCI clock-run protocol is followed on the CardBus
CCLKRUN interface to control this clock management.
3.8.4 16-Bit PC Card Power Management
The COE bit (bit 7) of the ExCA power control register (ExCA offset 02h/42h/802h, see Section 5.3) and PWRDWN
bit (bit 0) of the ExCA global control register (ExCA offset 1Eh/5Eh/81Eh, see Section 5.20) are provided for 16-bit
PC Card power management. The COE bit places the card interface in a high-impedance state to save power. The
power savings when using this feature are minimal. The COE bit resets the PC Card when used, and the PWRDWN
bit does not. Furthermore, the PWRDWN bit is an automatic COE, that is, the PWRDWN performs the COE function
when there is no card activity.
NOTE: The 16-bit PC Card must implement the proper pullup resistors for the COE and
PWRDWN modes.
3.8.5 Suspend Mode
The SUSPEND signal, provided for backward compatibility, gates the PRST (PCI reset) signal and the GRST (global
reset) signal from the PCI6x21/PCI6x11 controller. Besides gating PRST and GRST, SUSPEND also gates PCLK
inside the PCI6x21/PCI6x11 controller in order to minimize power consumption.
It should also be noted that asynchronous signals, such as card status change interrupts and RI_OUT, can be passed
to the host system without a PCI clock. However, if card status change interrupts are routed over the serial interrupt
stream, then the PCI clock must be restarted in order to pass the interrupt, because neither the internal oscillator nor
an external clock is routed to the serial-interrupt state machine. Figure 3−13 is a signal diagram of the suspend
function.
3−22
RESET
GNT
SUSPEND
PCLK
RESETIN
SUSPENDIN
PCLKIN
External Terminals
Internal Signals
Figure 3−13. Signal Diagram of Suspend Function
3.8.6 Requirements for Suspend Mode
The suspend mode prevents the clearing of all register contents on the assertion of reset (PRST or GRST) which
would require the reconfiguration of the PCI6x21/PCI6x11 controller by software. Asserting the SUSPEND signal
places the PCI outputs of the controller in a high-impedance state and gates the PCLK signal internally to the
controller unless a PCI transaction is currently in process (GNT is asserted). It is important that the PCI bus not be
parked on the PCI6x21/PCI6x11 controller when SUSPEND is asserted because the outputs are in a high-impedance
state.
The GPIOs, MFUNC signals, and RI_OUT signal are all active during SUSPEND, unless they are disabled in the
appropriate PCI6x21/PCI6x11 registers.
3.8.7 Ring Indicate
The RI_OUT output is an important feature in power management, allowing a system to go into a suspended mode
and wake-up on modem rings and other card events. TI-designed flexibility permits this signal to fit wide platform
requirements. RI_OUT on the PCI6x21/PCI6x11 controller can be asserted under any of the following conditions:
•A 16-bit PC Card modem in a powered socket asserts RI to indicate to the system the presence of an
incoming call.
•A powered down CardBus card asserts CSTSCHG (CBWAKE) requesting system and interface wake-up.
•A powered CardBus card asserts CSTSCHG from the insertion/removal of cards or change in battery
voltage levels.
Figure 3−14 shows various enable bits for the PCI6x21/PCI6x11 RI_OUT function; however, it does not show the
masking of CSC events. See Table 3−9 for a detailed description of CSC interrupt masks and flags.
3−23
Card
I/F
PC Card
Socket A CSC
CSTSMASK RIENB
RI_OUT
RI_OUT Function
RINGEN
CDRESUME
CSC
RI
PC Card
Socket B
Figure 3−14. RI_OUT Functional Diagram
RI from the 16-bit PC Card interface is masked by bit 7 (RINGEN) in the ExCA interrupt and general control register
(ExCA o ffset 03h/43h/803h, see Section 5.4). This is programmed on a per-socket basis and is only applicable when
a 16-bit card is powered in the socket.
The CBWAKE signaling to RI_OUT is enabled through the same mask as the CSC event for CSTSCHG. The mask
bit (bit 0, CSTSMASK) is programmed through the socket mask register (CB offset 04h, see Section 6.2) in the
CardBus socket registers.
RI_OUT can be routed through any of three different pins, RI_OUT/PME, MFUNC2, or MFUNC4. The RI_OUT
function is enabled by setting bit 7 (RIENB) in the card control register (PCI offset 91h, see Section 4.38). The PME
function is enabled by setting bit 8 (PME_ENABLE) in the power-management control/status register (PCI of fset A4h,
see Section 4.44). When bit 0 (RIMUX) in the system control register (PCI offset 80h, see Section 4.29) is set to 0,
both the RI_OUT function and the PME function are routed to the RI_OUT /PME terminal. If both functions are enabled
and RIMUX is set to 0, then the RI_OUT/PME terminal becomes RI_OUT only and PME assertions are never seen.
Therefore, in a system using both the RI_OUT function and the PME function, RIMUX must be set to 1 and RI_OUT
must be routed to either MFUNC2 or MFUNC4.
3.8.8 PCI Power Management
3.8.8.1 CardBus Power Management (Functions 0 and 1)
The PCI Bus Power Management Interface Specification for PCI to CardBus Bridges establishes the infrastructure
required to let the operating system control the power of PCI functions. This is done by defining a standard PCI
interface and operations to manage the power of PCI functions on the bus. The PCI bus and the PCI functions can
be assigned one of seven power-management states, resulting in varying levels of power savings.
The seven power-management states of PCI functions are:
•D0-uninitialized − Before controller configuration, controller not fully functional
•D0-active − Fully functional state
•D1 − Low-power state
•D2 − Low-power state
•D3hot − Low-power state. Transition state before D3cold
•D3cold − PME signal-generation capable. Main power is removed and VAUX is available.
•D3off − No power and completely nonfunctional
NOTE 1: In the D0-uninitialized state, the PCI6x21/PCI6x11 controller does not generate PME and/or interrupts. When bits 0 (IO_EN) and 1
(MEM_EN) of the command register (PCI of fset 04h, see Section 4.4) are both set, the PCI6x21/PCI6x11 controller switches the state
to D0-active. Transition from D3cold to the D0-uninitialized state happens at the deassertion of PRST. The assertion of GRST forces
the controller to the D0-uninitialized state immediately.
NOTE 2: The PWR_STATE bits (bits 1−0) of the power-management control/status register (PCI offset A4h, see Section 4.44) only code for four
power states, D0, D1, D2, and D3hot. The differences between the three D3 states is invisible to the software because the controller
is not accessible in the D3cold or D3off state.
3−24
Similarly, bus power states of the PCI bus are B0−B3. The bus power states B0−B3 are derived from the device power
state of the originating bridge device.
For the operating system (OS) to manage the controller power states on the PCI bus, the PCI function must support
four power-management operations. These operations are:
•Capabilities reporting
•Power status reporting
•Setting the power state
•System wake-up
The OS identifies the capabilities of the PCI function by traversing the new capabilities list. The presence of
capabilities i n addition to the standard PCI capabilities is indicated by a 1 in bit 4 (CAPLIST) of the status register (PCI
offset 06h, see Section 4.5).
The capabilities pointer provides access to the first item in the linked list of capabilities. For the PCI6x21/PCI6x11
controller, a CardBus bridge with PCI configuration space header type 2, the capabilities pointer is mapped to an of fset
of 14h. The first byte of each capability register block is required to be a unique ID of that capability. PCI power
management has been assigned an ID of 01h. The next byte is a pointer to the next pointer item in the list of
capabilities. If there are no more items in the list, then the next item pointer must be set to 0. The registers following
the next item pointer are specific to the capability of the function. The PCI power-management capability implements
the register block outlined in Table 3−14.
Table 3−14. Power-Management Registers
REGISTER NAME OFFSET
Power-management capabilities Next item pointer Capability ID A0h
Data Power-management control/status register bridge support extensions Power-management control/status (CSR) A4h
The power-management capabilities register (PCI offset A2h, see Section 4.43) provides information on the
capabilities of the function related to power management. The power-management control/status register (PCI of fset
A4h, see Section 4.44) enables control of power-management states and enables/monitors power-management
events. The data register is an optional register that can provide dynamic data.
For more information on PCI power management, see the PCI Bus Power Management Interface Specification for
PCI to CardBus Bridges.
3.8.8.2 Flash Media (Function 3) Power Management
The PCI Bus Power Management Interface Specification is applicable for the flash media dedicated sockets. This
function supports the D0 and D3 power states.
Table 3−15. Function 3 Power-Management Registers
REGISTER NAME OFFSET
Power-management capabilities Next item pointer Capability ID 44h
Data Power-management control/status register bridge support extensions Power-management control/status (CSR) 48h
3.8.8.3 SD Host (Function 4) Power Management
The PCI Bus Power Management Interface Specification is applicable for the SD host dedicated sockets. This
function supports the D0 and D3 power states.
Table 3−16. Function 4 Power-Management Registers
REGISTER NAME OFFSET
Power-management capabilities Next item pointer Capability ID 80h
Data Power-management control/status register bridge support extensions Power-management control/status (CSR) 84h
3.8.8.4 Smart Card (Function 5) Power Management
The PCI Bus Power Management Interface Specification is applicable for the Smart Card dedicated sockets. This
function supports the D0 and D3 power states.
3−25
Table 3−17. Function 5 Power-Management Registers
REGISTER NAME OFFSET
Power-management capabilities Next item pointer Capability ID 44h
Data Power-management control/status register bridge support extensions Power-management control/status (CSR) 48h
3.8.9 CardBus Bridge Power Management
The PCI Bus Power Management Interface Specification for PCI to CardBus Bridges was approved by PCMCIA in
December of 1997. This specification follows the device and bus state definitions provided in the PCI Bus Power
Management Interface Specification published by the PCI Special Interest Group (SIG). The main issue addressed
in the PCI Bus Power Management Interface Specification for PCI to CardBus Bridges i s wake-up from D3hot or D3cold
without losing wake-up context (also called PME context).
The specific issues addressed by the PCI Bus Power Management Interface Specification for PCI to CardBus Bridges
for D3 wake-up are as follows:
•Preservation of device context. The specification states that a reset must occur during the transition from
D3 to D0. Some method to preserve wake-up context must be implemented so that the reset does not clear
the PME context registers.
•Power source in D3cold if wake-up support is required from this state.
The Texas Instruments PCI6x21/PCI6x11 controller addresses these D3 wake-up issues in the following manner:
•Two resets are provided to handle preservation of PME context bits:
− Global reset (GRST) is used only on the initial boot up of the system after power up. It places the
PCI6x21/PCI6x11 controller in its default state and requires BIOS to configure the controller before
becoming fully functional.
− PCI reset (PRST) has dual functionality based on whether PME is enabled or not. If PME is enabled,
then PM E context is preserved. If PME is not enabled, then PRST acts the same as a normal PCI reset.
Please see the master list of PME context bits in Section 3.8.11.
•Power source in D3cold if wake-up support is required from this state. Since VCC is removed in D3cold, an
auxiliary power source must be supplied to the PCI6x21/PCI6x11 VCC terminals. Consult the PCI14xx
Implementation Guide for D3 Wake-Up or the PCI Power Management Interface Specification for PCI to
CardBus Bridges for further information.
3.8.10 ACPI Support
The Advanced Configuration and Power Interface (ACPI) Specification provides a mechanism that allows unique
pieces of hardware to be described to the ACPI driver. The PCI6x21/PCI6x11 controller offers a generic interface that
is compliant with ACPI design rules.
Two doublewords of general-purpose ACPI programming bits reside in PCI6x21/PCI6x11 PCI configuration space
at offset 88h. The programming model is broken into status and control functions. In compliance with ACPI, the top
level event status and enable bits reside in the general-purpose event status register (PCI offset 88h, see
Section 4.32) and general-purpose event enable register (PCI of fset 89h, see Section 4.33). The status and enable
bits are implemented as defined by ACPI and illustrated in Figure 3−15.
Event Output
Event Input
Enable Bit
Status Bit
Figure 3−15. Block Diagram of a Status/Enable Cell
The status and enable bits generate an event that allows the ACPI driver to call a control method associated with the
pending status bit. The control method can then control the hardware by manipulating the hardware control bits or
3−26
by investigating child status bits and calling their respective control methods. A hierarchical implementation would
be somewhat limiting, however, as upstream devices would have to remain in some level of power state to report
events.
For more information of ACPI, see the Advanced Configuration and Power Interface (ACPI) Specification.
3.8.11 Master List of PME Context Bits and Global Reset-Only Bits
PME context bit means that the bit is cleared only by the assertion of GRST when the PME enable bit, bit 8 of the
power management control/status register (PCI of fset A4h, see Section 4.44) is set. If PME is not enabled, then these
bits are cleared when either PRST or GRST is asserted.
The PME context bits (functions 0 and 1) are:
•Bridge control register (PCI offset 3Eh, see Section 4.25): bit 6
•System control register (PCI offset 80h, see Section 4.29): bits 10−8
•Power management control/status register (PCI offset A4h, see Section 4.44): bit 15
•ExCA power control register (ExCA 802h/842h, see Section 5.3): bits 7, 5 (82365SL mode only), 4, 3, 1,
0
•ExCA interrupt and general control (ExCA 803h/843h, see Section 5.4): bits 6, 5
•ExCA card status-change register (ExCA 804h/844h, see Section 5.5): bits 3−0
•ExCA card status-change interrupt configuration register (ExCA 805h/845h, see Section 5.6): bits 3−0
•ExCA card detect and general control register (ExCA 816h/856h, see Section 5.19): bits 7, 6
•Socket event register (CardBus offset 00h, see Section 6.1): bits 3−0
•Socket mask register (CardBus offset 04h, see Section 6.2): bits 3−0
•Socket present state register (CardBus offset 08h, see Section 6.3): bits 13−7, 5−1
•Socket control register (CardBus offset 10h, see Section 6.5): bits 6−4, 2−0
Global reset-only bits, as the name implies, are cleared only by GRST. These bits are never cleared by PRST,
regardless of the setting of the PME enable bit. The GRST signal is gated only by the SUSPEND signal. This means
that assertion of SUSPEND blocks the GRST signal internally, thus preserving all register contents. Figure 3−12 is
a diagram showing the application of GRST and PRST.
The global reset-only bits (functions 0 and 1) are:
•Status register (PCI offset 06h, see Section 4.5): bits 15−11, 8
•Secondary status register (PCI offset 16h, see Section 4.14): bits 15−11, 8
•Subsystem vendor ID register (PCI offset 40h, see Section 4.26): bits 15–0
•Subsystem ID register (PCI offset 42h, see Section 4.27): bits 15–0
•PC Card 16-bit I/F legacy-mode base-address register (PCI offset 44h, see Section 4.28): bits 31−0
•System control register (PCI offset 80h, see Section 4.29): bits 31−24, 22−13, 11, 6−0
•MC_CD debounce register (PCI offset 84h, see Section 4.30): bits 7−0
•General control register (PCI offset 86h, see Section 4.31): bits 13−10, 7, 5−3, 1, 0
•General-purpose event status register (PCI offset 88h, see Section 4.32): bits 7, 6, 4−0
•General-purpose event enable register (PCI offset 89h, see Section 4.33): bits 7, 6, 4−0
•General-purpose output register (PCI offset 8Bh, see Section 4.35): bits 4−0
•Multifunction routing register (PCI offset 8Ch, see Section 4.36): bits 31−0
•Retry status register (PCI offset 90h, see Section 4.37): bits 7−5, 3, 1
•Card control register (PCI offset 91h, see Section 4.38): bits 7, 2−0
•Device control register (PCI offset 92h, see Section 4.39): bits 7−5, 3−0
•Diagnostic register (PCI offset 93h, see Section 4.40): bits 7−0
•Power management capabilities register (PCI offset A2h, see Section 4.43): bit 15
•Power management CSR register (PCI offset A4h, see Section 4.44): bits 15, 8
•Serial bus data register (PCI offset B0h, see Section 4.47): bits 7−0
•Serial bus index register (PCI offset B1h, see Section 4.48): bits 7−0
•Serial bus slave address register (PCI offset B2h, see Section 4.49): bits 7−0
3−27
•Serial bus control/status register (PCI offset B3h, see Section 4.50): bits 7, 3−0
•ExCA identification and revision register (ExCA 800h/840h, see Section 5.1): bits 7−0
•ExCA global control register (ExCA 81Eh/85Eh, see Section 5.20): bits 2−0
•CardBus socket power management register (CardBus 20h, see Section 6.6): bits 25, 24
The global reset-only (function 3) register bits:
•Subsystem vendor ID register (PCI offset 2Ch, see Section 7.9): bits 15–0
•Subsystem ID register (PCI offset 2Eh, see Section 7.10): bits 15–0
•Power management control and status register (PCI offset 48h, see Section 7.18): bits 15, 8, 1, 0
•General control register (PCI offset 4Ch, see Section 7.21): bits 6−4, 2–0
•Diagnostic register (PCI offset 54h, see Section 7.23): bits 31–0
The global reset-only (function 4) register bits:
•Subsystem vendor ID register (PCI offset 2Ch, see Section 8.9): bits 15–0
•Subsystem ID register (PCI offset 2Eh, see Section 8.10): bits 15–0
•Power management control and status register (PCI offset 84h, see Section 8.19): bits 15, 8, 1, 0
•General control register (PCI offset 88h, see Section 8.22): bits 6−4, 0
•Diagnostic register (PCI offset 90h, see Section 8.24): bits 31–0
The global reset-only (function 5) register bits:
•Subsystem vendor ID register (PCI offset 2Ch, see Section 9.10): bits 15–0
•Subsystem ID register (PCI offset 2Eh, see Section 9.11): bits 15–0
•Power management control and status register (PCI offset 48h, see Section 9.19): bits 15, 8, 1, 0
•General control register (PCI offset 4Ch, see Section 9.22): bits 6−4, 0
3−28
4−1
4 PC Card Controller Programming Model
This chapter describes the PCI6x21/PCI6x11 PCI configuration registers that make up the 256-byte PCI configuration
header for each PCI6x21/PCI6x11 function. There are some bits which affect both CardBus functions, but which, in
order to work properly, must be accessed only through function 0. These are called global bits. Registers containing
one or more global bits are denoted by § in Table 4−2.
Any bit followed by a † is not cleared by the assertion of PRST (see CardBus Bridge Power Management,
Section 3.8.9, for more details) if PME is enabled (PCI offset A4h, bit 8). In this case, these bits are cleared only by
GRST. If PME is not enabled, then these bits are cleared by GRST or PRST. These bits are sometimes referred to
as PME context bits and are implemented to allow PME context to be preserved during the transition from D3hot or
D3cold to D0.
If a bit is followed by a ‡, then this bit is cleared only by GRST in all cases (not conditional on PME being enabled).
These bits are intended to maintain device context such as interrupt routing and MFUNC programming during warm
resets.
A bit description table, typically included when the register contains bits of more than one type or purpose, indicates
bit field names, a detailed field description, and field access tags which appear in the type column. Table 4−1
describes the field access tags.
Table 4−1. Bit Field Access Tag Descriptions
ACCESS TAG NAME MEANING
R Read Field can be read by software.
W Write Field can be written by software to any value.
S Set Field can be set by a write of 1. Writes of 0 have no effect.
C Clear Field can be cleared by a write of 1. Writes of 0 have no effect.
U Update Field can be autonomously updated by the PCI6x21/PCI6x11 controller.
4.1 PCI Configuration Register Map (Functions 0 and 1)
The PCI6x21/PCI6x11 is a multifunction PCI device, and the PC Card controller is integrated as PCI functions 0 and
1. The configuration header, compliant with the PCI Local Bus Specification as a CardBus bridge header, is
PC99/PC2001 compliant as well. Table 4−2 illustrates the PCI configuration register map, which includes both the
predefined portion of the configuration space and the user-definable registers.
Table 4−2. Functions 0 and 1 PCI Configuration Register Map
REGISTER NAME OFFSET
Device ID Vendor ID 00h
Status ‡ Command 04h
Class code Revision ID 08h
BIST Header type Latency timer Cache line size 0Ch
CardBus socket registers/ExCA base address register 10h
Secondary status ‡ Reserved Capability pointer 14h
CardBus latency timer Subordinate bus number CardBus bus number PCI bus number 18h
CardBus memory base register 0 1Ch
CardBus memory limit register 0 20h
CardBus memory base register 1 24h
CardBus memory limit register 1 28h
‡One or more bits in this register are cleared only by the assertion of GRST.
4−2
Table 4−2. Functions 0 and 1 PCI Configuration Register Map (Continued)
REGISTER NAME OFFSET
CardBus I/O base register 0 2Ch
CardBus I/O limit register 0 30h
CardBus I/O base register 1 34h
CardBus I/O limit register 1 38h
Bridge control † Interrupt pin Interrupt line 3Ch
Subsystem ID ‡ Subsystem vendor ID ‡ 40h
PC Card 16-bit I/F legacy-mode base-address ‡ 44h
Reserved 48h−7Ch
System control †‡§ 80h
General control ‡§ Reserved MC_CD debounce ‡ 84h
General-purpose output ‡ General-purpose input General-purpose event
enable ‡ General-purpose event
status ‡ 88h
Multifunction routing status ‡ 8Ch
Diagnostic ठDevice control ठCard control ठRetry status ठ90h
Reserved 94h−9Ch
Power management capabilities ‡ Next item pointer Capability ID A0h
Power management data
(Reserved)
Power management
control/status bridge support
extensions Power management control/status †‡ A4h
Reserved A8h−ACh
Serial bus control/status ‡ Serial bus slave address ‡ Serial bus index ‡ Serial bus data ‡ B0h
Reserved B4h−FCh
†One or more bits in this register are PME context bits and can be cleared only by the assertion of GRST when PME is enabled. If PME is not
enabled, then this bit is cleared by the assertion of PRST or GRST.
‡One or more bits in this register are cleared only by the assertion of GRST.
§One or more bits in this register are global in nature and must be accessed only through function 0.
4.2 Vendor ID Register
The vendor ID register contains a value allocated by the PCI SIG that identifies the manufacturer of the PCI device.
The vendor ID assigned to Texas Instruments is 104Ch.
Bit 15 14 13 12 11 109876543210
Name Vendor ID
Type RRRRRRRRRRRRRRRR
Default 0001000001001100
Register: Vendor ID
Offset: 00h (Functions 0, 1)
Type: Read-only
Default: 104Ch
4−3
4.3 Device ID Register Functions 0 and 1
This read-only register contains the device ID assigned by TI to the PCI6x21/PCI6x11 CardBus controller functions
(PCI functions 0 and 1).
Bit 15 14 13 12 11 109876543210
Name Device ID
Type RRRRRRRRRRRRRRRR
Default 1000000000110001
Register: Device ID
Offset: 02h (Functions 0 and 1)
Type: Read-only
Default: 8031h
4−4
4.4 Command Register
The PCI command register provides control over the PCI6x21/PCI6x11 interface to the PCI bus. All bit functions
adhere to the definitions in the PCI Local Bus Specification (see Table 4−3). None of the bit functions in this register
are shared among the PCI6x21/PCI6x11 PCI functions. Three command registers exist in the PCI6x21/PCI6x11
controller, one for each function. Software manipulates the PCI6x21/PCI6x11 functions as separate entities when
enabling functionality through the command register. The SERR_EN and PERR_EN enable bits in this register are
internally wired OR between the three functions, and these control bits appear to software to be separate for each
function.
Bit 15 14 13 12 11 109876543210
Name Command
Type RRRRRRW RRW RRW RW R R RW RW RW
Default 0000000000000000
Register: Command
Offset: 04h
Type: Read-only, Read/Write
Default: 0000h
Table 4−3. Command Register Description
BIT SIGNAL TYPE FUNCTION
15−11 RSVD R Reserved. Bits 15−11 return 0s when read.
10 INT_DISABLE RW INTx disable. When set to 1, this bit disables the function from asserting interrupts on the INTx signals.
0 = INTx assertion is enabled (default)
1 = INTx assertion is disabled
9 FBB_EN R Fast back-to-back enable. The PCI6x21/PCI6x11 controller does not generate fast back-to-back
transactions; therefore, this bit is read-only. This bit returns a 0 when read.
8 SERR_EN RW
System error (SERR) enable. This bit controls the enable for the SERR driver on the PCI interface. SERR
can be asserted after detecting an address parity error on the PCI bus. Both this bit and bit 6 must be set
for the PCI6x21/PCI6x11 controller to report address parity errors.
0 = Disables the SERR output driver (default)
1 = Enables the SERR output driver
7 RSVD R Reserved. Bit 7 returns 0 when read.
6 PERR_EN RW
Parity error response enable. This bit controls the PCI6x21/PCI6x11 response to parity errors through the
PERR signal. Data parity errors are indicated by asserting PERR, while address parity errors are indicated
by asserting SERR.
0 = PCI6x21/PCI6x11 controller ignores detected parity errors (default).
1 = PCI6x21/PCI6x11 controller responds to detected parity errors.
5 VGA_EN RW VGA palette snoop. When set to 1, palette snooping is enabled (i.e., the PCI6x21/PCI6x11 controller does
not respond to palette register writes and snoops the data). When the bit is 0, the PCI6x21/PCI6x11
controller treats all palette accesses like all other accesses.
4 MWI_EN R
Memory write-and-invalidate enable. This bit controls whether a PCI initiator device can generate memory
write-and-invalidate commands. The PCI6x21/PCI6x11 controller does not support memory
write-and-invalidate commands, it uses memory write commands instead; therefore, this bit is hardwired
to 0. This bit returns 0 when read. Writes to this bit have no effect.
3 SPECIAL R Special cycles. This bit controls whether or not a PCI device ignores PCI special cycles. The
PCI6x21/PCI6x11 controller does not respond to special cycle operations; therefore, this bit is hardwired
to 0. This bit returns 0 when read. Writes to this bit have no effect.
2 MAST_EN RW
Bus master control. This bit controls whether or not the PCI6x21/PCI6x11 controller can act as a PCI bus
initiator (master). The PCI6x21/PCI6x11 controller can take control of the PCI bus only when this bit is set.
0 = Disables the PCI6x21/PCI6x11 ability to generate PCI bus accesses (default)
1 = Enables the PCI6x21/PCI6x11 ability to generate PCI bus accesses
4−5
Table 4−3. Command Register Description (continued)
BIT SIGNAL TYPE FUNCTION
1 MEM_EN RW
Memory space enable. This bit controls whether or not the PCI6x21/PCI6x11 controller can claim cycles
in PCI memory space.
0 = Disables the PCI6x21/PCI6x11 response to memory space accesses (default)
1 = Enables the PCI6x21/PCI6x11 response to memory space accesses
0 IO_EN RW
I/O space control. This bit controls whether or not the PCI6x21/PCI6x11 controller can claim cycles in PCI
I/O space.
0 = Disables the PCI6x21/PCI6x11 controller from responding to I/O space accesses (default)
1 = Enables the PCI6x21/PCI6x11 controller to respond to I/O space accesses
4.5 Status Register
The status register provides device information to the host system. Bits in this register can be read normally. A bit
in the status register is reset when a 1 is written to that bit location; a 0 written to a bit location has no effect. All bit
functions adhere to the definitions in the PCI Bus Specification, as seen in the bit descriptions. PCI bus status is shown
through each function. See Table 4−4 for a complete description of the register contents.
Bit 15 14 13 12 11 109876543210
Name Status
Type RW RW RW RW RW R R RW RRRRRURRR
Default 0000001000010000
Register: Status
Offset: 06h (Functions 0, 1)
Type: Read-only, Read/Write
Default: 0210h
Table 4−4. Status Register Description
BIT SIGNAL TYPE FUNCTION
15 ‡ PAR_ERR RW Detected parity error. This bit is set when a parity error is detected, either an address or data parity error.
Write a 1 to clear this bit.
14 ‡ SYS_ERR RW Signaled system error. This bit is set when SERR is enabled and the PCI6x21/PCI6x11 controller signaled
a system error to the host. Write a 1 to clear this bit.
13 ‡ MABORT RW Received master abort. This bit is set when a cycle initiated by the PCI6x21/PCI6x11 controller on the PCI
bus has been terminated by a master abort. Write a 1 to clear this bit.
12 ‡ TABT_REC RW Received target abort. This bit is set when a cycle initiated by the PCI6x21/PCI6x11 controller on the PCI
bus was terminated by a target abort. Write a 1 to clear this bit.
11 ‡ TABT_SIG RW Signaled target abort. This bit is set by the PCI6x21/PCI6x11 controller when it terminates a transaction on
the PCI bus with a target abort. Write a 1 to clear this bit.
10−9 PCI_SPEED R DEVSEL timing. These bits encode the timing of DEVSEL and are hardwired to 01b indicating that the
PCI6x21/PCI6x11 controller asserts this signal at a medium speed on nonconfiguration cycle accesses.
8 ‡ DATAPAR RW
Data parity error detected. Write a 1 to clear this bit.
0 = The conditions for setting this bit have not been met.
1 = A data parity error occurred and the following conditions were met:
a. PERR was asserted by any PCI device including the PCI6x21/PCI6x11 controller.
b. The PCI6x21/PCI6x11 controller was the bus master during the data parity error.
c. The parity error response bit is set in the command register.
7 FBB_CAP R Fast back-to-back capable. The PCI6x21/PCI6x11 controller cannot accept fast back-to-back transactions;
thus, this bit is hardwired to 0.
6 UDF R UDF supported. The PCI6x21/PCI6x11 controller does not support user-definable features; therefore, this
bit is hardwired to 0.
5 66MHZ R 66-MHz capable. The PCI6x21/PCI6x11 controller operates at a maximum PCLK frequency of 33 MHz;
therefore, this bit is hardwired to 0.
‡One or more bits in this register are cleared only by the assertion of GRST.
4−6
Table 4−4. Status Register Description (continued)
BIT SIGNAL TYPE FUNCTION
4 CAPLIST R Capabilities list. This bit returns 1 when read. This bit indicates that capabilities in addition to standard PCI
capabilities are implemented. The linked list of PCI power-management capabilities is implemented in this
function.
3 INT_STATUS RU Interrupt status. This bit reflects the interrupt status of the function. Only when bit 10 (INT_DISABLE) in the
command register (PCI offset 04h, see Section 4.4) is a 0 and this bit is a 1, is the function’s INTx signal
asserted. Setting the INT_DISABLE bit to a 1 has no effect on the state of this bit.
2−0 RSVD R Reserved. These bits return 0s when read.
4.6 Revision ID Register
The revision ID register indicates the silicon revision of the PCI6x21/PCI6x11 controller.
Bit 7 6 5 4 3 2 1 0
Name Revision ID
Type R R R R R R R R
Default 0 0 0 0 0 0 0 0
Register: Revision ID
Offset: 08h (functions 0, 1)
Type: Read-only
Default: 00h
4.7 Class Code Register
The class code register recognizes PCI6x21/PCI6x11 functions 0 and 1 as a bridge device (06h) and a CardBus
bridge device (07h), with a 00h programming interface.
Bit 23 22 21 20 19 18 17 16 15 14 13 12 11 109876543210
Name PCI class code
Base class Subclass Programming interface
Type RRRRRRRRRRRRRRRRRRRRRRRR
Default 000001100000011100000000
Register: PCI class code
Offset: 09h (functions 0, 1)
Type: Read-only
Default: 06 0700h
4.8 Cache Line Size Register
The cache line size register is programmed by host software to indicate the system cache line size.
Bit 7 6 5 4 3 2 1 0
Name Cache line size
Type RW RW RW RW RW RW RW RW
Default 0 0 0 0 0 0 0 0
Register: Cache line size
Offset: 0Ch (Functions 0, 1)
Type: Read/Write
Default: 00h
4−7
4.9 Latency Timer Register
The latency timer register specifies the latency timer for the PCI6x21/PCI6x11 controller , in units of PCI clock cycles.
When the PCI6x21/PCI6x11 controller is a PCI bus initiator and asserts FRAME, the latency timer begins counting
from zero. If the latency timer expires before the PCI6x21/PCI6x11 transaction has terminated, then the
PCI6x21/PCI6x11 controller terminates the transaction when its GNT is deasserted.
Bit 7 6 5 4 3 2 1 0
Name Latency timer
Type RW RW RW RW RW RW RW RW
Default 0 0 0 0 0 0 0 0
Register: Latency timer
Offset: 0Dh
Type: Read/Write
Default: 00h
4.10 Header Type Register
The header type register returns 82h when read, indicating that the PCI6x21/PCI6x11 functions 0 and 1 configuration
spaces adhere to the CardBus bridge PCI header. The CardBus bridge PCI header ranges from PCI registers
00h−7Fh, and 80h−FFh is user-definable extension registers.
Bit 7 6 5 4 3 2 1 0
Name Header type
Type R R R R R R R R
Default 1 0 0 0 0 0 1 0
Register: Header type
Offset: 0Eh (Functions 0, 1)
Type: Read-only
Default: 82h
4.11 BIST Register
Because the PCI6x21/PCI6x11 controller does not support a built-in self-test (BIST), this register returns the value
of 00h when read.
Bit 7 6 5 4 3 2 1 0
Name BIST
Type R R R R R R R R
Default 0 0 0 0 0 0 0 0
Register: BIST
Offset: 0Fh (Functions 0, 1)
Type: Read-only
Default: 00h
4−8
4.12 CardBus Socket Registers/ExCA Base Address Register
This register is programmed with a base address referencing the CardBus socket registers and the memory-mapped
ExCA register set. Bits 31−12 are read/write, and allow the base address to be located anywhere in the 32-bit PCI
memory address space on a 4-Kbyte boundary. Bits 11−0 are read-only, returning 0s when read. When software
writes all 1s to this register, the value read back is FFFF F000h, indicating that at least 4K bytes of memory address
space are required. The CardBus registers start at offset 000h, and the memory-mapped ExCA registers begin at
offset 800h. This register is not shared by functions 0 and 1, so the system maps each socket control register
separately.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CardBus socket registers/ExCA base address
Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Default 0000000000000000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CardBus socket registers/ExCA base address
Type RW RW RW RW RRRRRRRRRRRR
Default 0000000000000000
Register: CardBus socket registers/ExCA base address
Offset: 10h
Type: Read-only, Read/Write
Default: 0000 0000h
4.13 Capability Pointer Register
The capability pointer register provides a pointer into the PCI configuration header where the PCI power management
register block resides. PCI header doublewords at A0h and A4h provide the power management (PM) registers. Each
socket has its own capability pointer register. This register is read-only and returns A0h when read.
Bit 7 6 5 4 3 2 1 0
Name Capability pointer
Type RRRRRRRR
Default 1 0 1 0 0 0 0 0
Register: Capability pointer
Offset: 14h
Type: Read-only
Default: A0h
4−9
4.14 Secondary Status Register
The secondary status register is compatible with the PCI-PCI bridge secondary status register. It indicates
CardBus-related device information to the host system. This register is very similar to the PCI status register (PCI
offset 06h, see Section 4.5), and status bits are cleared by a writing a 1. This register is not shared by the two socket
functions, but is accessed on a per-socket basis. See Table 4−5 for a complete description of the register contents.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Secondary status
Type RC RC RC RC RC R R RC R R R R R R R R
Default 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
Register: Secondary status
Offset: 16h
Type: Read-only, Read/Clear
Default: 0200h
Table 4−5. Secondary Status Register Description
BIT SIGNAL TYPE FUNCTION
15 ‡ CBPARITY RC Detected parity error. This bit is set when a CardBus parity error is detected, either an address or data
parity error. Write a 1 to clear this bit.
14 ‡ CBSERR RC Signaled system error. This bit is set when CSERR is signaled by a CardBus card. The PCI6x21/PCI6x11
controller does not assert the CSERR signal. Write a 1 to clear this bit.
13 ‡ CBMABORT RC Received master abort. This bit is set when a cycle initiated by the PCI6x21/PCI6x11 controller on the
CardBus bus is terminated by a master abort. Write a 1 to clear this bit.
12 ‡ REC_CBTA RC Received target abort. This bit is set when a cycle initiated by the PCI6x21/PCI6x11 controller on the
CardBus bus is terminated by a target abort. Write a 1 to clear this bit.
11 ‡ SIG_CBTA RC Signaled target abort. This bit is set by the PCI6x21/PCI6x11 controller when it terminates a transaction
on the CardBus bus with a target abort. Write a 1 to clear this bit.
10−9 CB_SPEED R CDEVSEL timing. These bits encode the timing of CDEVSEL and are hardwired to 01b indicating that the
PCI6x21/PCI6x11 controller asserts this signal at a medium speed.
8 ‡ CB_DPAR RC
CardBus data parity error detected. Write a 1 to clear this bit.
0 = The conditions for setting this bit have not been met.
1 = A data parity error occurred and the following conditions were met:
a. CPERR was asserted on the CardBus interface.
b. The PCI6x21/PCI6x11 controller was the bus master during the data parity error.
c. The parity error response enable bit (bit 0) is set in the bridge control register (PCI offset 3Eh,
see Section 4.25).
7 CBFBB_CAP R Fast back-to-back capable. The PCI6x21/PCI6x11 controller cannot accept fast back-to-back
transactions; therefore, this bit is hardwired to 0.
6 CB_UDF R User-definable feature support. The PCI6x21/PCI6x11 controller does not support user-definable
features; therefore, this bit is hardwired to 0.
5 CB66MHZ R 66-MHz capable. The PCI6x21/PCI6x11 CardBus interface operates at a maximum CCLK frequency of
33 MHz; therefore, this bit is hardwired to 0.
4−0 RSVD R These bits return 0s when read.
‡One or more bits in this register are cleared only by the assertion of GRST.
4−10
4.15 PCI Bus Number Register
The PCI bus number register is programmed by the host system to indicate the bus number of the PCI bus to which
the PCI6x21/PCI6x11 controller is connected. The PCI6x21/PCI6x11 controller uses this register in conjunction with
the CardBus bus number and subordinate bus number registers to determine when to forward PCI configuration
cycles to its secondary buses.
Bit 7 6 5 4 3 2 1 0
Name PCI bus number
Type RW RW RW RW RW RW RW RW
Default 0 0 0 0 0 0 0 0
Register: PCI bus number
Offset: 18h (Functions 0, 1)
Type: Read/Write
Default: 00h
4.16 CardBus Bus Number Register
The CardBus bus number register is programmed by the host system to indicate the bus number of the CardBus bus
to which the PCI6x21/PCI6x11 controller is connected. The PCI6x21/PCI6x11 controller uses this register in
conjunction with the PCI bus number and subordinate bus number registers to determine when to forward PCI
configuration cycles to its secondary buses. This register is separate for each PCI6x21/PCI6x11 controller function.
Bit 7 6 5 4 3 2 1 0
Name CardBus bus number
Type RW RW RW RW RW RW RW RW
Default 0 0 0 0 0 0 0 0
Register: CardBus bus number
Offset: 19h
Type: Read/Write
Default: 00h
4.17 Subordinate Bus Number Register
The subordinate bus number register is programmed by the host system to indicate the highest numbered bus below
the CardBus bus. The PCI6x21/PCI6x11 controller uses this register in conjunction with the PCI bus number and
CardBus bus number registers to determine when to forward PCI configuration cycles to its secondary buses. This
register is separate for each CardBus controller function.
Bit 7 6 5 4 3 2 1 0
Name Subordinate bus number
Type RW RW RW RW RW RW RW RW
Default 0 0 0 0 0 0 0 0
Register: Subordinate bus number
Offset: 1Ah
Type: Read/Write
Default: 00h
4−11
4.18 CardBus Latency Timer Register
The CardBus latency timer register is programmed by the host system to specify the latency timer for the
PCI6x21/PCI6x11 CardBus interface, in units of CCLK cycles. When the PCI6x21/PCI6x11 controller is a CardBus
initiator and asserts CFRAME, the CardBus latency timer begins counting. If the latency timer expires before the
PCI6x21/PCI6x11 transaction has terminated, then the PCI6x21/PCI6x11 controller terminates the transaction at the
end of the next data phase. A recommended minimum value for this register of 20h allows most transactions to be
completed.
Bit 7 6 5 4 3 2 1 0
Name CardBus latency timer
Type RW RW RW RW RW RW RW RW
Default 0 0 0 0 0 0 0 0
Register: CardBus latency timer
Offset: 1Bh (Functions 0, 1)
Type: Read/Write
Default: 00h
4.19 CardBus Memory Base Registers 0, 1
These registers indicate the lower address of a PCI memory address range. They are used by the PCI6x21/PCI6x11
controller to determine when to forward a memory transaction to the CardBus bus, and likewise, when to forward a
CardBus cycle to PCI. Bits 31−12 of these registers are read/write and allow the memory base to be located anywhere
in the 32-bit PCI memory space on 4-Kbyte boundaries. Bits 11−0 are read-only and always return 0s. Writes to these
bits have no effect. Bits 8 and 9 of the bridge control register (PCI offset 3Eh, see Section 4.25) specify whether
memory windows 0 and 1 are prefetchable or nonprefetchable. The memory base register or the memory limit register
must be nonzero in order for the PCI6x21/PCI6x11 controller to claim any memory transactions through CardBus
memory windows (i.e., these windows by default are not enabled to pass the first 4 Kbytes of memory to CardBus).
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name Memory base registers 0, 1
Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Memory base registers 0, 1
Type RW RW RW RW R R R R R R R R R R R R
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Register: Memory base registers 0, 1
Offset: 1Ch, 24h
Type: Read-only, Read/Write
Default: 0000 0000h
4−12
4.20 CardBus Memory Limit Registers 0, 1
These registers indicate the upper address of a PCI memory address range. They are used by the PCI6x21/PCI6x11
controller to determine when to forward a memory transaction to the CardBus bus, and likewise, when to forward a
CardBus cycle to PCI. Bits 31−12 of these registers are read/write and allow the memory base to be located anywhere
in the 32-bit PCI memory space on 4-Kbyte boundaries. Bits 11−0 are read-only and always return 0s. Writes to these
bits have no effect. Bits 8 and 9 of the bridge control register (PCI offset 3Eh, see Section 4.25) specify whether
memory windows 0 and 1 are prefetchable or nonprefetchable. The memory base register or the memory limit register
must be nonzero in order for the PCI6x21/PCI6x11 controller to claim any memory transactions through CardBus
memory windows (i.e., these windows by default are not enabled to pass the first 4 Kbytes of memory to CardBus).
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name Memory limit registers 0, 1
Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Default 0000000000000000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Memory limit registers 0, 1
Type RW RW RW RW RRRRRRRRRRRR
Default 0000000000000000
Register: Memory limit registers 0, 1
Offset: 20h, 28h
Type: Read-only, Read/Write
Default: 0000 0000h
4.21 CardBus I/O Base Registers 0, 1
These registers indicate the lower address of a PCI I/O address range. They are used by the PCI6x21/PCI6x11
controller to determine when to forward an I/O transaction to the CardBus bus, and likewise, when to forward a
CardBus cycle to the PCI bus. The lower 16 bits of this register locate the bottom of the I/O window within a 64-Kbyte
page. The upper 16 bits (31−16) are all 0s, which locates this 64-Kbyte page in the first page of the 32-bit PCI I/O
address space. Bits 31−2 are read/write and always return 0s forcing I/O windows to be aligned on a natural
doubleword boundary in the first 64-Kbyte page of PCI I/O address space. Bits 1−0 are read-only, returning 00 or 0 1
when read, depending on the value of bit 11 (IO_BASE_SEL) in the general control register (PCI offset 86h, see
Section 4.31). These I/O windows are enabled when either the I/O base register or the I/O limit register is nonzero.
The I/O windows by default are not enabled to pass the first doubleword of I/O to CardBus.
Either the I/O base register or the I/O limit register must be nonzero to enable any I/O transactions.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name I/O base registers 0, 1
Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Default 0000000000000000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name I/O base registers 0, 1
Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW R R
Default 000000000000000X
Register: I/O base registers 0, 1
Offset: 2Ch, 34h
Type: Read-only, Read/Write
Default: 0000 000Xh
4−13
4.22 CardBus I/O Limit Registers 0, 1
These registers indicate the upper address of a PCI I/O address range. They are used by the PCI6x21/PCI6x11
controller to determine when to forward an I/O transaction to the CardBus bus, and likewise, when to forward a
CardBus cycle to PCI. The lower 16 bits of this register locate the top of the I/O window within a 64-Kbyte page, and
the upper 16 bits are a page register which locates this 64-Kbyte page in 32-bit PCI I/O address space. Bits 15−2
are read/write and allow the I/O limit address to be located anywhere in the 64-Kbyte page (indicated by bits 31−16
of the appropriate I/O base register) on doubleword boundaries.
Bits 31−16 are read-only and always return 0s when read. The page is set in the I/O base register. Bits 15−2 are
read/write and bits 1−0 are read-only, returning 00 or 01 when read, depending on the value of bit 12 (IO_LIMIT_SEL)
in the general control register (PCI offset 86h, see Section 4.31). Writes to read-only bits have no effect.
These I/O windows are enabled when either the I/O base register or the I/O limit register is nonzero. By default, the
I/O windows are not enabled to pass the first doubleword of I/O to CardBus.
Either the I/O base register or the I/O limit register must be nonzero to enable any I/O transactions.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name I/O limit registers 0, 1
Type RRRRRRRRRRRRRRRR
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name I/O limit registers 0, 1
Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW R R
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X
Register: I/O limit registers 0, 1
Offset: 30h, 38h
Type: Read-only, Read/Write
Default: 0000 000Xh
4.23 Interrupt Line Register
The interrupt line register is a read/write register used by the host software. As part of the interrupt routing procedure,
the host software writes this register with the value of the system IRQ assigned to the function.
Bit 7 6 5 4 3 2 1 0
Name Interrupt line
Type RW RW RW RW RW RW RW RW
Default 1 1 1 1 1 1 1 1
Register: Interrupt line
Offset: 3Ch
Type: Read/Write
Default: FFh
4−14
4.24 Interrupt Pin Register
The value read from this register is function dependent. The default value for function 0 is 01h (INTA), and the default
value for function 1 is 02h (INTB), the default value for function 2 is 03h (INTC), and the default value for function 3
is 04h (INTD). The value also depends on the values of bits 28, the tie-all bit (TIEALL), and 29, the interrupt tie bit
(INTRTIE), in the system control register (PCI offset 80h, see Section 4.29). The INTRTIE bit is compatible with
previous TI CardBus controllers, and when set to 1, ties INTB to INTA internally. The TIEALL bit ties INTA, INTB, INTC,
and INTD together internally. The internal interrupt connections set by INTRTIE and TIEALL are communicated to
host software through this standard register interface. This read-only register is described for all PCI6x21/PCI6x11
functions in Table 4−6.
PCI function 0
Bit 7 6 5 4 3 2 1 0
Name Interrupt pin − PCI function 0
Type RRRRRRRR
Default 0 0 0 0 0 0 0 1
PCI function 1
Bit 7 6 5 4 3 2 1 0
Name Interrupt pin − PCI function 1
Type RRRRRRRR
Default 0 0 0 0 0 0 1 0
PCI function 3
Bit 7 6 5 4 3 2 1 0
Name Interrupt pin − PCI function 3
Type RRRRRRRR
Default 0 0 0 0 0 X X X
PCI function 4
Bit 7 6 5 4 3 2 1 0
Name Interrupt pin − PCI function 4
Type RRRRRRRR
Default 0 0 0 0 0 X X X
PCI function 5
Bit 7 6 5 4 3 2 1 0
Name Interrupt pin − PCI function 5
Type RRRRRRRR
Default 0 0 0 0 0 X X X
Register: Interrupt pin
Offset: 3Dh
Type: Read-only
Default: 01h (function 0), 02h (function 1), 04h (function 3), 04h (function 4), 04h (function 5)
4−15
Table 4−6. Interrupt Pin Register Cross Reference
INTRTIE BIT
(BIT 29,
OFFSET 80h)
TIEALL BIT
(BIT 28,
OFFSET 80h)
INTPIN
FUNCTION 0
(CARDBUS)
INTPIN
FUNCTION 1
(CARDBUS)
INTPIN
FUNCTION 3
(FLASH MEDIA)
INTPIN
Function 4
(SD Host)
INTPIN
Function 5
(Smart Card)
0 0 01h (INTA)02h (INTB)Determined by bits
6−5 (INT_SEL field) in
flash media general
Determined by bits
6−5 (INT_SEL field) in
SD host general
Determined by bits
6−5 (INT_SEL field) in
Smart Card general
1 0 01h (INTA)01h (INTA)
flash media general
control register (see
Section 7.21)
SD host general
control register (see
Section 8.22)
Smart Card general
control register (see
Section 9.22)
X 1 01h (INTA)01h (INTA)01h (INTA)0x01 (INTA)0x01 (INTA)
4.25 Bridge Control Register
The bridge control register provides control over various PCI6x21/PCI6x11 bridging functions. Some bits in this
register are global in nature and must be accessed only through function 0. See Table 4−7 for a complete description
of the register contents.
Bit 15 14 13 12 11 109876543210
Name Bridge control
Type RRRRRRW RW RW RW RW RW RRW RW RW RW
Default 0000001101000000
Register: Bridge control
Offset: 3Eh (Function 0, 1)
Type: Read-only, Read/Write
Default: 0340h
Table 4−7. Bridge Control Register Description
BIT SIGNAL TYPE FUNCTION
15−11 RSVD R These bits return 0s when read.
10 POSTEN RW
Write posting enable. Enables write posting to and from the CardBus sockets. W rite posting enables the
posting of write data on burst cycles. Operating with write posting disabled impairs performance on burst
cycles. Note that burst write data can be posted, but various write transactions may not. This bit is socket
dependent and is not shared between functions 0 and 1.
9 PREFETCH1 RW
Memory window 1 type. This bit specifies whether or not memory window 1 is prefetchable. This bit is
socket dependent. This bit is encoded as:
0 = Memory window 1 is nonprefetchable.
1 = Memory window 1 is prefetchable (default).
8 PREFETCH0 RW
Memory window 0 type. This bit specifies whether or not memory window 0 is prefetchable. This bit is
socket dependent. This bit is encoded as:
0 = Memory window 0 is nonprefetchable.
1 = Memory window 0 is prefetchable (default).
7 INTR RW
PCI interrupt − IREQ routing enable. This bit is used to select whether PC Card functional interrupts are
routed to PCI interrupts or to the IRQ specified in the ExCA registers.
0 = Functional interrupts are routed to PCI interrupts (default).
1 = Functional interrupts are routed by ExCA registers.
6 † CRST RW
CardBus reset. When this bit is set, the CRST signal is asserted on the CardBus interface. The CRST
signal can also be asserted by passing a PRST assertion to CardBus.
0 = CRST is deasserted.
1 = CRST is asserted (default).
This bit is not cleared by the assertion of PRST. It is only cleared by the assertion of GRST.
†One or more bits in this register are PME context bits and can be cleared only by the assertion of GRST when PME is enabled. If PME is not
enabled, then this bit is cleared by the assertion of PRST or GRST.
4−16
Table 4−7. Bridge Control Register Description (Continued)
BIT SIGNAL TYPE FUNCTION
5 MABTMODE RW
Master abort mode. This bit controls how the PCI6x21/PCI6x11 controller responds to a master abort when
the PCI6x21/PCI6x11 controller is an initiator on the CardBus interface. This bit is common between each
socket.
0 = Master aborts not reported (default).
1 = Signal target abort on PCI and signal SERR, if enabled.
4 RSVD R This bit returns 0 when read.
3 VGAEN RW VGA enable. This bit affects how the PCI6x21/PCI6x11 controller responds to VGA addresses. When this
bit is set, accesses to VGA addresses are forwarded.
2 ISAEN RW ISA mode enable. This bit affects how the PCI6x21/PCI6x11 controller passes I/O cycles within the
64-Kbyte ISA range. This bit is not common between sockets. When this bit is set, the PCI6x21/PCI6x11
controller does not forward the last 768 bytes of each 1K I/O range to CardBus.
1 CSERREN RW
CSERR enable. This bit controls the response of the PCI6x21/PCI6x11 controller to CSERR signals on
the CardBus bus. This bit is separate for each socket.
0 = CSERR is not forwarded to PCI SERR (default)
1 = CSERR is forwarded to PCI SERR.
0 CPERREN RW
CardBus parity error response enable. This bit controls the response of the PCI6x21/PCI6x11 to CardBus
parity errors. This bit is separate for each socket.
0 = CardBus parity errors are ignored (default).
1 = CardBus parity errors are reported using CPERR.
4.26 Subsystem Vendor ID Register
The subsystem vendor ID register, used for system and option card identification purposes, may be required for
certain operating systems. This register is read-only or read/write, depending on the setting of bit 5 (SUBSYSRW)
in the system control register (PCI of fset 80h, See Section 4.29). When bit 5 is 0, this register is read/write; when bit 5
is 1, this register is read-only. The default mode is read-only. All bits in this register are reset by GRST only.
Bit 15 14 13 12 11 109876543210
Name Subsystem vendor ID
Type RRRRRRRRRRRRRRRR
Default 0000000000000000
Register: Subsystem vendor ID
Offset: 40h (Functions 0, 1)
Type: Read-only, (Read/Write when bit 5 in the system control register is 0)
Default: 0000h
4.27 Subsystem ID Register
The subsystem ID register, used for system and option card identification purposes, may be required for certain
operating systems. This register is read-only or read/write, depending on the setting of bit 5 (SUBSYSRW) in the
system control register (PCI offset 80h, see Section 4.29). When bit 5 is 0, this register is read/write; when bit 5 is
1, this register is read-only. The default mode is read-only. All bits in this register are reset by GRST only.
If an EEPROM is present, then the subsystem ID and subsystem vendor ID is loaded from the EEPROM after a reset.
Bit 15 14 13 12 11 109876543210
Name Subsystem ID
Type RRRRRRRRRRRRRRRR
Default 0000000000000000
Register: Subsystem ID
Offset: 42h (Functions 0, 1)
Type: Read-only, (Read/Write when bit 5 in the system control register is 0)
Default: 0000h
4−17
4.28 PC Card 16-Bit I/F Legacy-Mode Base-Address Register
The PCI6x21/PCI6x11 controller supports the index/data scheme of accessing the ExCA registers, which is mapped
by this register. An address written to this register is the address for the index register and the address+1 is the data
address. Using this access method, applications requiring index/data ExCA access can be supported. The base
address can be mapped anywhere in 32-bit I/O space on a word boundary; hence, bit 0 is read-only, returning 1 when
read. As specified in the PCI to PCMCIA CardBus Bridge Register Description specification, this register is shared
by functions 0 and 1. See the ExCA register set description in Section 5 for register offsets. All bits in this register
are reset by GRST only.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name PC Card 16-bit I/F legacy-mode base-address
Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name PC Card 16-bit I/F legacy-mode base-address
Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW R
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Register: PC Card 16-bit I/F legacy-mode base-address
Offset: 44h (Functions 0, 1)
Type: Read-only, Read/Write
Default: 0000 0001h
4−18
4.29 System Control Register
System-level initializations are performed through programming this doubleword register. Some of the bits are global
in nature and must be accessed only through function 0. See Table 4−8 for a complete description of the register
contents.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name System control
Type RW RW RW RW RW RW RW RW RRW RW RW R R R R
Default 0000100001000000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name System control
Type RW RW RRRRRRRRW RW RW RW RRW RW
Default 1001000001100000
Register: System control
Offset: 80h (Functions 0, 1)
Type: Read-only, Read/Write
Default: 0840 9060h
Table 4−8. System Control Register Description
BIT SIGNAL TYPE FUNCTION
31−30 ‡§ SER_STEP RW
Serial input stepping. In serial PCI interrupt mode, these bits are used to configure the serial stream PCI
interrupt frames, and can be used to accomplish an even distribution of interrupts signaled on the four PCI
interrupt slots.
00 = INTA/INTB/INTC/INTD signal in INTA/INTB/INTC/INTD slots (default)
01 = INTA/INTB/INTC/INTD signal in INTB/INTC/INTD/INTA slots
10 = INTA/INTB/INTC/INTD signal in INTC/INTD/INTA/INTB slots
11 = INTA/INTB/INTC/INTD signal in INTD/INTA/INTB/INTC slots
29 ठINTRTIE RW This bit ties INTA to INTB internally (to INTA), and reports this through the interrupt pin register (PCI offset
3Dh, see Section 4.24). This bit has no effect on INTC or INTD.
28 ‡ TIEALL RW This bit ties INTA, INTB, INTC, and INTD internally (to INTA), and reports this through the interrupt pin
register (PCI offset 3Dh, see Section 4.24).
27 ‡ PSCCLK RW
P2C power switch clock. The PCI6x21/PCI6x11 CLOCK signal clocks the serial interface power switch
and the internal state machine. The default state for this bit is 0, requiring an external clock source provided
to the CLOCK terminal. Bit 27 can be set to 1, allowing the internal oscillator to provide the clock signal.
0 = CLOCK is provided externally, input to the PCI6x21/PCI6x11 controller.
1 = CLOCK is generated by the internal oscillator and driven by the PCI6x21/PCI6x11 controller.
(default)
26 ठSMIROUTE RW
SMI interrupt routing. This bit is shared between functions 0 and 1, and selects whether IRQ2 or CSC is
signaled when a write occurs to power a PC Card socket.
0 = PC Card power change interrupts are routed to IRQ2 (default).
1 = A CSC interrupt is generated on PC Card power changes.
25 ‡ SMISTATUS RW
SMI interrupt status. This socket-dependent bit is set when a write occurs to set the socket power, and
the SMIENB bit is set. Writing a 1 to this bit clears the status.
0 = SMI interrupt is signaled.
1 = SMI interrupt is not signaled.
24 ठSMIENB RW
SMI interrupt mode enable. When this bit is set, the SMI interrupt signaling generates an interrupt when
a write to the socket power control occurs. This bit is shared and defaults to 0 (disabled).
0 = SMI interrupt mode is disabled (default).
1 = SMI interrupt mode is enabled.
23 RSVD R Reserved
‡One or more bits in this register are cleared only by the assertion of GRST.
§These bits are global in nature and must be accessed only through function 0.
4−19
Table 4−8.System Control Register Description (continued)
BIT SIGNAL TYPE FUNCTION
22 ‡ CBRSVD RW
CardBus reserved terminals signaling. When this bit is set, the RSVD CardBus terminals are driven
low when a CardBus card has been inserted. When this bit is low, these signals are placed in a
high-impedance state.
0 = Place the CardBus RSVD terminals in a high-impedance state.
1 = Drive the CardBus RSVD terminals low (default).
21 ‡ VCCPROT RW VCC protection enable. This bit is socket dependent.
0 = VCC protection is enabled for 16-bit cards (default).
1 = VCC protection is disabled for 16-bit cards.
20−16 ‡ RSVD RW These bits are reserved. Do not change the value of these bits.
15 ठMRBURSTDN RW
Memory read burst enable downstream. When this bit is set, the PCI6x21/PCI6x11 controller allows
memory read transactions to burst downstream.
0 = MRBURSTDN downstream is disabled.
1 = MRBURSTDN downstream is enabled (default).
14 ठMRBURSTUP RW
Memory read burst enable upstream. When this bit is set, the PCI6x21/PCI6x11 controller allows
memory read transactions to burst upstream.
0 = MRBURSTUP upstream is disabled (default).
1 = MRBURSTUP upstream is enabled.
13 ‡ SOCACTIVE R
Socket activity status. When set, this bit indicates access has been performed to or from a PC Card.
Reading this bit causes it to be cleared. This bit is socket dependent.
0 = No socket activity (default)
1 = Socket activity
12 RSVD R Reserved. This bit returns 1 when read.
11 ‡ PWRSTREAM R
Power-stream-in-progress status bit. When set, this bit indicates that a power stream to the power
switch is i n progress and a powering change has been requested. When this bit is cleared, it indicates
that the power stream is complete.
0 = Power stream is complete, delay has expired (default).
1 = Power stream is in progress.
10 † DELAYUP R
Power-up delay-in-progress status bit. When set, this bit indicates that a power-up stream has been
sent to the power switch, and proper power may not yet be stable. This bit is cleared when the power-up
delay has expired.
0 = Power-up delay has expired (default).
1 = Power-up stream sent to switch. Power might not be stable.
9 † DELAYDOWN R
Power-down delay-in-progress status bit. When set, this bit indicates that a power-down stream has
been sent to the power switch, and proper power may not yet be stable. This bit is cleared when the
power-down delay has expired.
0 = Power-down delay has expired (default).
1 = Power-down stream sent to switch. Power might not be stable.
8 † INTERROGATE R
Interrogation in progress. When set, this bit indicates an interrogation is in progress, and clears when
the interrogation completes. This bit is socket-dependent.
0 = Interrogation not in progress (default)
1 = Interrogation in progress
7 RSVD R Reserved. This bit returns 0 when read.
6 ठPWRSAVINGS RW
Power savings mode enable. When this bit is set, the PCI6x21/PCI6x11 controller consumes less
power with no performance loss. This bit is shared between the two PCI6x21/PCI6x11 CardBus
functions.
0 = Power savings mode disabled
1 = Power savings mode enabled (default)
5 ठSUBSYSRW RW
Subsystem ID and subsystem vendor ID, ExCA ID and revision register read/write enable. This bit also
controls read/write for the function 3 subsystem ID register.
0 = Registers are read/write.
1 = Registers are read-only (default).
†One or more bits in this register are PME context bits and can be cleared only by the assertion of GRST when PME is enabled. If PME is not
enabled, then this bit is cleared by the assertion of PRST or GRST.
‡One or more bits in this register are cleared only by the assertion of GRST.
§These bits are global in nature and must be accessed only through function 0.
4−20
Table 4−8.System Control Register Description (continued)
BIT SIGNAL TYPE FUNCTION
4 ठCB_DPAR RW CardBus data parity SERR signaling enable.
0 = CardBus data parity not signaled on PCI SERR signal (default)
1 = CardBus data parity signaled on PCI SERR signal
3 ठRSVD R Reserved. This bit returns 0 when read.
2 ‡ EXCAPOWER R ExCA power control bit.
0 = Enables 3.3 V (default)
1 = Enables 5 V
1 ठKEEPCLK RW
Keep clock. When this bit is set, the PCI6x21/PCI6x11 controller follows the CLKRUN protocol to
maintain the system PCLK and the CCLK (CardBus clock). This bit is global to the PCI6x21/PCI6x11
functions.
0 = Allow system PCLK and CCLK clocks to stop (default)
1 = Never allow system PCLK or CCLK clock to stop
Note that the functionality of this bit has changed relative to that of the PCI12XX family of TI CardBus
controllers. In these CardBus controllers, setting this bit only maintains the PCI clock, not the CCLK.
In the PCI6x21/PCI6x11 controller, setting this bit maintains both the PCI clock and the CCLK.
0 ठRIMUX RW
PME/RI_OUT select bit. When this bit is 1, the PME signal is routed to the PME/RI_OUT terminal (R03).
When this bit is 0 and bit 7 (RIENB) of the card control register is 1, the RI_OUT signal is routed to the
PME/RI_OUT terminal. If this bit is 0 and bit 7 (RIENB) of the card control register is 0, then the output
is placed in a high-impedance state. This terminal is encoded as:
0 = RI_OUT signal is routed to the PME/RI_OUT terminal if bit 7 of the card control register is 1.
(default)
1 = PME signal is routed to the PME/RI_OUT terminal of the PCI6x21/PCI6x11 controller.
NOTE: If this bit (bit 0) is 0 and bit 7 of the card control register (PCI offset 91h, see Section 4.38) is
0, then the output on the PME/RI_OUT terminal is placed in a high-impedance state.
‡One or more bits in this register are cleared only by the assertion of GRST.
§These bits are global in nature and must be accessed only through function 0.
4.30 MC_CD Debounce Register
This register provides debounce time in units of 2 ms for the MC_CD signal on UltraMedia cards. This register defaults
to 19h, which gives a default debounce time of 50 ms. All bits in this register are reset by GRST only.
Bit 7 6 5 4 3 2 1 0
Name MC_CD debounce
Type RW RW RW RW RW RW RW RW
Default 0 0 0 1 1 0 0 1
Register: MC_CD debounce
Offset: 84h (Functions 0, 1)
Type: Read/Write
Default: 19h
4−21
4.31 General Control Register
The general control register provides top level PCI arbitration control. It also provides the ability to disable the 1394
OHCI function and provides control over miscellaneous new functionality. See Table 4−9 for a complete description
of the register contents.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name General control
Type R R RW RW RW RW R R R R RW RW RW RRW RW
Default 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
Register: General control
Offset: 86h
Type: Read/Write, Read-only
Default: 0080h
Table 4−9. General Control Register Description
BIT SIGNAL TYPE FUNCTION
15 ‡ FM_PWR_CTRL
_POL RW
Flash media power control pin polarity. This bit controls the polarity of the MC_PWR_CTRL_0 and
MC_PWR_CTRL_1 terminals.
0 = MC_PWR_CTRL_x terminals are active low (default)
1 = MC_PWR_CTRL_x terminals are active high
14 ‡ SC_IF_SEL RWU
Smart Card interface select. This bit controls the selection of the dedicated Smart Card interface
used by the controller.
0 = EMV interface selected (default)
1 = PCI7x10-style interface selected
Note: The PCI7x10-style interface is only allowed when bits 9−8 (FM_IF_SEL field) are 01. If bits
9−8 contain any other value, then this bit is 0. Care must be taken in the design to ensure that this
bit can be set to 1 at the same time that bits 9−8 are set to 01.
13 ‡ SIM_MODE RW When this bit is set, it reduces the query time for UltraMedia card types.
0 = Query time is unaffected (default)
1 = Query time is reduced for simulation purposes
12 ‡ IO_LIMIT_SEL RW
When this bit is set, bit 0 in the I/O limit registers (PCI offsets 30h and 38h) for both CardBus functions
is set.
0 = Bit 0 in the I/O limit registers is 0 (default)
1 = Bit 0 in the I/O limit registers is 1
11 ‡ IO_BASE_SEL RW
When this bit is set, bit 0 in the I/O base registers (PCI offsets 2Ch and 34h) for both CardBus functions
is set.
0 = Bit 0 in the I/O base registers is 0 (default)
1 = Bit 0 in the I/O base registers is 1
10 ‡ 12V_SW_SEL RW Power switch select. This bit selects which power switch is implemented in the system.
0 = A 1.8-V capable power switch (TPS2228) is used (default)
1 = A 12-V capable power switch (TPS2226) is used
9−8 ‡ FM_IF_SEL RW
Dedicated flash media interface selection. This field controls the mode of the dedicated flash media
interface.
00 = Flash media interface configured as SD/MMC socket + MS socket (default)
01 = Flash media interface configured as 2-in-1 (SD/MMC, MS) socket
10 = Flash media interface configured as 3-in-1 (SD/MMC, MS, SM/XD) socket
11 = Reserved
7 ‡ DISABLE_SC RW When this bit is set, the Smart Card function is completely nonaccessible and nonfunctional.
6 ‡ DISABLE_SD RW When this bit is set, the SD host controller function is completely nonaccessible and nonfunctional.
5 ‡ DISABLE_FM RW When this bit is set, the flash media function is completely nonaccessible and nonfunctional.
4 ‡ DISABLE_SKTB RW When this bit is set, CardBus socket B (function 1) is completely nonaccessible and nonfunctional.
3 ‡ DISABLE_OHCI RW When this bit is set, the OHCI 1394 controller function is completely nonaccessible and nonfunctional.
‡One or more bits in this register are cleared only by the assertion of GRST.
4−22
Table 4−9. General Control Register Description (Continued)
BIT SIGNAL TYPE FUNCTION
2 ‡ DED_SC_PWR_
CTRL RW
Dedicated Smart Card power control. This bit determines how power to the dedicated Smart Card
socket is controlled.
0 = Controlled through the SC_PWR_CTRL terminal (default)
1 = Controlled through the VPP voltage of socket B of the CardBus power switch (the design
must ensure that this mode can only be set when CardBus socket B is disabled).
1−0 ‡ ARB_CTRL RW
Controls top level PCI arbitration:
00 = 1394 OHCI priority 10 = Flash media/SD host priority
01 = CardBus priority 11 = Fair round robin
Note: When flash media/SD host priority is selected, there must be a two-level priority scheme with the
first level being a round robin between the flash media and SD host functions and the second level being
a round robin between the CardBus and 1394 functions.
‡One or more bits in this register are cleared only by the assertion of GRST.
4.32 General-Purpose Event Status Register
The general-purpose event status register contains status bits that are set when general events occur, and can be
programmed to generate general-purpose event signaling through GPE. See Table 4−10 for a complete description
of the register contents.
Bit 7 6 5 4 3 2 1 0
Name General-purpose event status
Type RCU RCU R RCU RCU RCU RCU RCU
Default 0 0 0 0 0 0 0 0
Register: General-purpose event status
Offset: 88h
Type: Read/Clear/Update, Read-only
Default: 00h
Table 4−10. General-Purpose Event Status Register Description
BIT SIGNAL TYPE FUNCTION
7 ‡ PWR_STS RCU Power change status. This bit is set when software changes the VCC or VPP power state of either socket.
6 ‡ VPP12_STS RCU 12-V V PP request status. This bit is set when software has changed the requested VPP level to or from 12 V
for either socket.
5 RSVD R Reserved. This bit returns 0 when read. A write has no effect.
4 ‡ GP4_STS RCU GPI4 status. This bit is set on a change in status of the MFUNC5 terminal input level if configured as a
general-purpose input, GPI4.
3 ‡ GP3_STS RCU GPI3 status. This bit is set on a change in status of the MFUNC4 terminal input level if configured as a
general-purpose input, GPI3.
2 ‡ GP2_STS RCU GPI2 status. This bit is set on a change in status of the MFUNC2 terminal input level if configured as a
general-purpose input, GPI2.
1 ‡ GP1_STS RCU GPI1 status. This bit is set on a change in status of the MFUNC1 terminal input level if configured as a
general-purpose input, GPI1.
0 ‡ GP0_STS RCU GPI0 status. This bit is set on a change in status of the MFUNC0 terminal input level if configured as a
general-purpose input, GPI0.
‡One or more bits in this register are cleared only by the assertion of GRST.
4−23
4.33 General-Purpose Event Enable Register
The general-purpose event enable register contains bits that are set to enable GPE signals. See Table 4−11 for a
complete description of the register contents.
Bit 7 6 5 4 3 2 1 0
Name General-purpose event enable
Type RW RW RRW RW RW RW RW
Default 0 0 0 0 0 0 0 0
Register: General-purpose event enable
Offset: 89h
Type: Read-only, Read/Write
Default: 00h
Table 4−11. General-Purpose Event Enable Register Description
BIT SIGNAL TYPE FUNCTION
7 ‡ PWR_EN RW Power change GPE enable. When this bit is set, GPE is signaled on PWR_STS events.
6 ‡ VPP12_EN RW 12-V VPP GPE enable. When this bit is set, GPE is signaled on VPP12_STS events.
5 RSVD R Reserved. This bit returns 0 when read. A write has no effect.
4 ‡ GP4_EN RW GPI4 GPE enable. When this bit is set, GPE is signaled on GP4_STS events.
3 ‡ GP3_EN RW GPI3 GPE enable. When this bit is set, GPE is signaled on GP3_STS events.
2 ‡ GP2_EN RW GPI2 GPE enable. When this bit is set, GPE is signaled on GP2_STS events.
1 ‡ GP1_EN RW GPI1 GPE enable. When this bit is set, GPE is signaled on GP1_STS events.
0 ‡ GP0_EN RW GPI0 GPE enable. When this bit is set, GPE is signaled on GP0_STS events.
‡One or more bits in this register are cleared only by the assertion of GRST.
4.34 General-Purpose Input Register
The general-purpose input register contains the logical value of the data input to the GPI terminals. See Table 4−12
for a complete description of the register contents.
Bit 7 6 5 4 3 2 1 0
Name General-purpose input
Type R R R RU RU RU RU RU
Default 0 0 0 X X X X X
Register: General-purpose input
Offset: 8Ah
Type: Read/Update, Read-only
Default: XXh
Table 4−12. General-Purpose Input Register Description
BIT SIGNAL TYPE FUNCTION
7−5 RSVD R Reserved. These bits return 0s when read. Writes have no effect.
4 GPI4_DATA RU GPI4 data input. This bit represents the logical value of the data input from GPI4.
3 GPI3_DATA RU GPI3 data input. This bit represents the logical value of the data input from GPI3.
2 GPI2_DATA RU GPI2 data input. This bit represents the logical value of the data input from GPI2.
1 GPI1_DATA RU GPI1 data input. This bit represents the logical value of the data input from GPI1.
0 GPI0_DATA RU GPI0 data input. This bit represents the logical value of the data input from GPI0.
4−24
4.35 General-Purpose Output Register
The general-purpose output register is used to drive the GPO4−GPO0 outputs. See Table 4−13 for a complete
description of the register contents.
Bit 7 6 5 4 3 2 1 0
Name General-purpose output
Type R R R RW RW RW RW RW
Default 0 0 0 0 0 0 0 0
Register: General-purpose output
Offset: 8Bh
Type: Read-only, Read/Write
Default: 00h
Table 4−13. General-Purpose Output Register Description
BIT SIGNAL TYPE FUNCTION
7−5 RSVD R Reserved. These bits return 0s when read. Writes have no effect.
4 ‡ GPO4_DATA RW This bit represents the logical value of the data driven to GPO4.
3 ‡ GPO3_DATA RW This bit represents the logical value of the data driven to GPO3.
2 ‡ GPO2_DATA RW This bit represents the logical value of the data driven to GPO2.
1 ‡ GPO1_DATA RW This bit represents the logical value of the data driven to GPO1.
0 ‡ GPO0_DATA RW This bit represents the logical value of the data driven to GPO0.
‡One or more bits in this register are cleared only by the assertion of GRST.
4−25
4.36 Multifunction Routing Status Register
The multifunction routing status register is used to configure the MFUNC6−MFUNC0 terminals. These terminals may
be configured for various functions. This register is intended to be programmed once at power-on initialization. The
default value for this register can also be loaded through a serial EEPROM. See Table 4−14 for a complete description
of the register contents.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name Multifunction routing status
Type RRW RW RW RRW RW RW RRW RW RW RRW RW RW
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Multifunction routing status
Type RRW RW RW RRW RW RW RRW RW RW RRW RW RW
Default 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
Register: Multifunction routing status
Offset: 8Ch
Type: Read/Write, Read-only
Default: 0000 1000h
Table 4−14. Multifunction Routing Status Register Description
BIT SIGNAL TYPE FUNCTION
31−28 ‡ RSVD R Bits 31−28 return 0s when read.
27−24 ‡ MFUNC6 RW
Multifunction terminal 6 configuration. These bits control the internal signal mapped to the MFUNC6 terminal
as follows:
0000 = RSVD 0100 = IRQ4 1000 = IRQ8 1100 = IRQ12
0001 = CLKRUN 0101 = IRQ5 1001 = IRQ9 1101 = IRQ13
0010 = IRQ2 0110 = IRQ6 1010 = IRQ10 1110 = IRQ14
0011 = IRQ3 0111 = IRQ7 1011 = IRQ11 1111 = IRQ15
23−20 ‡ MFUNC5 RW
Multifunction terminal 5 configuration. These bits control the internal signal mapped to the MFUNC5 terminal
as follows:
0000 = GPI4 0100 = SC_DBG_RX 1000 = CAUDPWM 1100 = LEDA1
0001 = GPO4 0101 = IRQ5 1001 = IRQ9 1101 = LED_SKT
0010 = PCGNT 0110 = RSVD 1010 = FM_LED 1110 = GPE
0011 = IRQ3 0111 = RSVD 1011 = OHCI_LED 1111 = IRQ15
19−16 ‡ MFUNC4 RW
Multifunction terminal 4 configuration. These bits control the internal signal mapped to the MFUNC4 terminal
as follows:
0000 = GPI3 0100 = IRQ4 1000 = CAUDPWM 1100 = RI_OUT
0001 = GPO3 0101 = SC_DBG_TX 1001 = IRQ9 1101 = LED_SKT
0010 = LOCK PCI 0110 = RSVD 1010 = INTD 1110 = GPE
0011 = IRQ3 0111 = RSVD 1011 = FM_LED 1111 = IRQ15
15−12 ‡ MFUNC3 RW
Multifunction terminal 3 configuration. These bits control the internal signal mapped to the MFUNC3 terminal
as follows:
0000 = RSVD 0100 = IRQ4 1000 = IRQ8 1100 = IRQ12
0001 = IRQSER 0101 = IRQ5 1001 = IRQ9 1101 = IRQ13
0010 = IRQ2 0110 = IRQ6 1010 = IRQ10 1110 = IRQ14
0011 = IRQ3 0111 = IRQ7 1011 = IRQ11 1111 = IRQ15
11−8 ‡ MFUNC2 RW
Multifunction terminal 2 configuration. These bits control the internal signal mapped to the MFUNC2 terminal
as follows:
0000 = GPI2 0100 = IRQ4 1000 = CAUDPWM 1100 = RI_OUT
0001 = GPO2 0101 = IRQ5 1001 = FM_LED 1101 = TEST_MUX
0010 = PCREQ 0110 = RSVD 1010 = IRQ10 1110 = GPE
0011 = IRQ3 0111 = RSVD 1011 = INTC 1111 = IRQ7
‡One or more bits in this register are cleared only by the assertion of GRST.
4−26
Table 4−14. Multifunction Routing Status Register Description (Continued)
BIT SIGNAL TYPE FUNCTION
7−4 ‡ MFUNC1 RW
Multifunction terminal 1 configuration. These bits control the internal signal mapped to the MFUNC1 terminal
as follows:
0000 = GPI1 0100 = OHCI_LED 1000 = CAUDPWM 1100 = LEDA1
0001 = GPO1 0101 = IRQ5 1001 = IRQ9 1101 = LEDA2
0010 = INTB 0110 = RSVD 1010 = IRQ10 1110 = GPE
0011 = IRQ3 0111 = RSVD 1011 = IRQ11 1111 = IRQ15
3−0 ‡ MFUNC0 RW
Multifunction terminal 0 configuration. These bits control the internal signal mapped to the MFUNC0 terminal
as follows:
0000 = GPI0 0100 = IRQ4 1000 = CAUDPWM 1100 = LEDA1
0001 = GPO0 0101 = IRQ5 1001 = IRQ9 1101 = LEDA2
0010 = INTA 0110 = RSVD 1010 = IRQ10 1110 = GPE
0011 = IRQ3 0111 = RSVD 1011 = IRQ11 1111 = IRQ15
‡One or more bits in this register are cleared only by the assertion of GRST.
4.37 Retry Status Register
The contents of the retry status register enable the retry time-out counters and display the retry expiration status. The
flags are set when the PCI6x21/PCI6x11 controller, as a master, receives a retry and does not retry the request within
215 clock cycles. The flags are cleared by writing a 1 to the bit. Access this register only through function 0. See
Table 4−15 for a complete description of the register contents.
Bit 7 6 5 4 3 2 1 0
Name Retry status
Type RW RW RC R RC R RC R
Default 1 1 0 0 0 0 0 0
Register: Retry status
Offset: 90h (Functions 0, 1)
Type: Read-only, Read/Write, Read/Clear
Default: C0h
Table 4−15. Retry Status Register Description
BIT SIGNAL TYPE FUNCTION
7 ‡ PCIRETRY RW PCI retry time-out counter enable. This bit is encoded as:
0 = PCI retry counter disabled
1 = PCI retry counter enabled (default)
6 ठCBRETRY RW CardBus retry time-out counter enable. This bit is encoded as:
0 = CardBus retry counter disabled
1 = CardBus retry counter enabled (default)
5 ‡ TEXP_CBB RC CardBus target B retry expired. Write a 1 to clear this bit.
0 = Inactive (default)
1 = Retry has expired.
4 RSVD R Reserved. This bit returns 0 when read.
3 ठTEXP_CBA RC CardBus target A retry expired. Write a 1 to clear this bit.
0 = Inactive (default)
1 = Retry has expired.
2 RSVD R Reserved. This bit returns 0 when read.
1 ‡ TEXP_PCI RC PCI target retry expired. Write a 1 to clear this bit.
0 = Inactive (default)
1 = Retry has expired.
0 RSVD R Reserved. This bit returns 0 when read.
‡One or more bits in this register are cleared only by the assertion of GRST.
§These bits are global in nature and must be accessed only through function 0.
4−27
4.38 Card Control Register
The card control register is provided for PCI1130 compatibility. RI_OUT is enabled through this register, and the
enable bit is shared between functions 0 and 1. See Table 4−16 for a complete description of the register contents.
The RI_OUT signal is enabled through this register, and the enable bit is shared between functions 0 and 1.
Bit 7 6 5 4 3 2 1 0
Name Card control
Type RW RW RW R R RW RW RW
Default 0 0 0 0 0 0 0 0
Register: Card control
Offset: 91h
Type: Read-only, Read/Write
Default: 00h
Table 4−16. Card Control Register Description
BIT SIGNAL TYPE FUNCTION
7 ठRIENB RW Ring indicate enable. When this bit is 1, the RI_OUT output is enabled. This bit defaults to 0.
6−3 RSVD RW These bits are reserved. Do not change the value of these bits.
2 ‡ AUD2MUX RW
CardBus audio-to-MFUNC. When this bit is set, the CAUDIO CardBus signal must be routed through an
MFUNC terminal. If this bit is set for both functions, then function 0 is routed.
0 = CAUDIO set to CAUDPWM on MFUNC terminal (default)
1 = CAUDIO is not routed.
1 ‡ SPKROUTEN RW
When bit 1 is set, the SPKR terminal from the PC Card is enabled and is routed to tthe SPKROUT terminal.
The SPKR signal from socket 0 is XORed with the SPKR signal from socket 1 and sent to SPKROUT. The
SPKROUT terminal drives data only when the SPKROUTEN bit of either function is set. This bit is encoded
as:0 = SPKR to SPKROUT not enabled (default)
1 = SPKR to SPKROUT enabled
0 ‡ IFG RW
Interrupt flag. This bit is the interrupt flag for 16-bit I/O PC Cards and for CardBus cards. This bit is set when
a functional interrupt is signaled from a PC Card interface, and is socket dependent (i.e., not global). Write
back a 1 to clear this bit.
0 = No PC Card functional interrupt detected (default)
1 = PC Card functional interrupt detected
‡One or more bits in this register are cleared only by the assertion of GRST.
§This bit is global in nature and must be accessed only through function 0.
4−28
4.39 Device Control Register
The device control register is provided for PCI1130 compatibility. It contains bits that are shared between functions
0 and 1. The interrupt mode select is programmed through this register. The socket-capable force bits are also
programmed through this register. See Table 4−17 for a complete description of the register contents.
Bit 7 6 5 4 3 2 1 0
Name Device control
Type RW RW RW RRW RW RW RW
Default 0 1 1 0 0 1 1 0
Register: Device control
Offset: 92h (Functions 0, 1)
Type: Read-only, Read/Write
Default: 66h
Table 4−17. Device Control Register Description
BIT SIGNAL TYPE FUNCTION
7 ‡ SKTPWR_LOCK RW
Socket power lock bit. When this bit is set to 1, software cannot power down the PC Card socket while
in D3. It may be necessary to lock socket power in order to support wake on LAN or RING if the
operating system is programmed to power down a socket when the CardBus controller is placed in the
D3 state.
6 ठ3VCAPABLE RW 3-V socket capable force bit.
0 = Not 3-V capable
1 = 3-V capable (default)
5 ‡ IO16R2 RW Diagnostic bit. This bit defaults to 1.
4 RSVD R Reserved. This bit returns 0 when read. A write has no effect.
3 ठTEST RW TI test bit. Write only 0 to this bit.
2−1 ‡§ INTMODE RW
Interrupt mode. These bits select the interrupt signaling mode. The interrupt mode bits are encoded:
00 = Parallel PCI interrupts only
01 = Reserved
10 = IRQ serialized interrupts and parallel PCI interrupts INTA, INTB, INTC, and INTD
11 = IRQ and PCI serialized interrupts (default)
0 ठRSVD RW Reserved. Bit 0 is reserved for test purposes. Only a 0 must be written to this bit.
‡One or more bits in this register are cleared only by the assertion of GRST.
§These bits are global in nature and must be accessed only through function 0.
4−29
4.40 Diagnostic Register
The diagnostic register is provided for internal TI test purposes. It is a read/write register, but only 0s must be written
to it. See Table 4−18 for a complete description of the register contents.
Bit 7 6 5 4 3 2 1 0
Name Diagnostic
Type RW RRW RW RW RW RW RW
Default 0 1 1 0 0 0 0 0
Register: Diagnostic
Offset: 93h (functions 0, 1)
Type: Read/Write
Default: 60h
Table 4−18. Diagnostic Register Description
BIT SIGNAL TYPE FUNCTION
7 ठTRUE_VAL RW This bit defaults to 0. This bit is encoded as:
0 = Reads true values in PCI vendor ID and PCI device ID registers (default)
1 = Returns all 1s to reads from the PCI vendor ID and PCI device ID registers
6 ‡ RSVD R Reserved. This bit is read-only and returns 1 when read.
5 ‡ CSC RW
CSC interrupt routing control
0 = CSC interrupts routed to PCI if ExCA 803 bit 4 = 1
1 = CSC interrupts routed to PCI if ExCA 805 bits 7−4 = 0000b (default).
In this case, the setting of ExCA 803 bit 4 is a don’t care.
4 ठDIAG4 RW Diagnostic RETRY_DIS. Delayed transaction disable.
3 ठDIAG3 RW Diagnostic RETRY_EXT. Extends the latency from 16 to 64.
2 ठDIAG2 RW Diagnostic DISCARD_TIM_SEL_CB. Set = 210, reset = 215.
1 ठDIAG1 RW Diagnostic DISCARD_TIM_SEL_PCI. Set = 210, reset = 215.
0 ‡ RSVD RW These bits are reserved. Do not change the value of these bits.
‡One or more bits in this register are cleared only by the assertion of GRST.
§This bit is global and is accessed only through function 0.
4−30
4.41 Capability ID Register
The capability ID register identifies the linked list item as the register for PCI power management. The register returns
01h when read, which is the unique ID assigned by the PCI SIG for the PCI location of the capabilities pointer and
the value.
Bit 7 6 5 4 3 2 1 0
Name Capability ID
Type RRRRRRRR
Default 0 0 0 0 0 0 0 1
Register: Capability ID
Offset: A0h
Type: Read-only
Default: 01h
4.42 Next Item Pointer Register
The contents of this register indicate the next item in the linked list of the PCI power management capabilities.
Because the PCI6x21/PCI6x11 functions only include one capabilities item, this register returns 0s when read.
Bit 7 6 5 4 3 2 1 0
Name Next item pointer
Type RRRRRRRR
Default 0 0 0 0 0 0 0 0
Register: Next item pointer
Offset: A1h
Type: Read-only
Default: 00h
4−31
4.43 Power Management Capabilities Register
The power management capabilities register contains information on the capabilities of the PC Card function related
to power management. Both PCI6x21/PCI6x11 CardBus bridge functions support D0, D1, D2, and D3 power states.
Default register value is FE12h for operation in accordance with PCI Bus Power Management Interface Specification
revision 1.1. See Table 4−19 for a complete description of the register contents.
Bit 15 14 13 12 11 109876543210
Name Power management capabilities
Type RW RRRRRRRRRRRRRRR
Default 1111111000010010
Register: Power management capabilities
Offset: A2h (Functions 0, 1)
Type: Read-only, Read/Write
Default: FE12h
Table 4−19. Power Management Capabilities Register Description
BIT SIGNAL TYPE FUNCTION
This 5-bit field indicates the power states from which the PCI6x21/PCI6x11 controller functions can assert
PME. A 0 for any bit indicates that the function cannot assert the PME signal while in that power state.
These 5 bits return 11111b when read. Each of these bits is described below:
15 ‡
PME support
RW Bit 15 − defaults to a 1 indicating the PME signal can be asserted from the D3cold state. This bit is read/write
because wake-up support from D3cold is contingent on the system providing an auxiliary power source
to the VCC terminals. If the system designer chooses not to provide an auxiliary power source to the VCC
terminals for D3cold wake-up support, then BIOS must write a 0 to this bit.
14−11 R Bit 14 − contains the value 1 to indicate that the PME signal can be asserted from the D3hot state.
Bit 13 − contains the value 1 to indicate that the PME signal can be asserted from the D2 state.
Bit 12 − contains the value 1 to indicate that the PME signal can be asserted from the D1 state.
Bit 11 − contains the value 1 to indicate that the PME signal can be asserted from the D0 state.
10 D2_Support R This bit returns a 1 when read, indicating that the function supports the D2 device power state.
9 D1_Support R This bit returns a 1 when read, indicating that the function supports the D1 device power state.
8−6 RSVD R Reserved. These bits return 000b when read.
5 DSI R Device-specific initialization. This bit returns 0 when read.
4 AUX_PWR R
Auxiliary power source. This bit is meaningful only if bit 15 (D3cold supporting PME) is set. When this bit
is set, it indicates that support for PME in D3cold requires auxiliary power supplied by the system by way
of a proprietary delivery vehicle.
A 0 (zero) in this bit field indicates that the function supplies its own auxiliary power source.
If the function does not support PME while in the D3cold state (bit 15=0), then this field must always return
0.
3 PMECLK R When this bit is 1, it indicates that the function relies on the presence of the PCI clock for PME operation.
When this bit is 0, it indicates that no PCI clock is required for the function to generate PME.
Functions that do not support PME generation in any state must return 0 for this field.
2−0 Version R These 3 bits return 010b when read, indicating that there are 4 bytes of general-purpose power
management (PM) registers as described in draft revision 1.1 of the PCI Bus Power Management Interface
Specification.
‡One or more bits in this register are cleared only by the assertion of GRST.
4−32
4.44 Power Management Control/Status Register
The power management control/status register determines and changes the current power state of the
PCI6x21/PCI6x11 CardBus function. The contents of this register are not affected by the internally generated reset
caused by the transition from the D3hot to D0 state. See Table 4−20 for a complete description of the register contents.
All PCI registers, ExCA registers, and CardBus registers are reset as a result of a D3hot-to-D0 state transition, with
the exception of the PME context bits (if PME is enabled) and the GRST only bits.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Power management control/status
Type RWC R R R R R R RW RRRRRRRW RW
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Register: Power management control/status
Offset: A4h (Functions 0, 1)
Type: Read-only, Read/Write, Read/Write/Clear
Default: 0000h
Table 4−20. Power Management Control/Status Register Description
BIT SIGNAL TYPE FUNCTION
15 † PMESTAT RC PME status. This bit is set when the CardBus function would normally assert the PME signal, independent
of the state of the PME_EN bit. This bit is cleared by a writeback of 1, and this also clears the PME signal
if PME was asserted by this function. Writing a 0 to this bit has no effect.
14−13 DATASCALE R This 2-bit field returns 0s when read. The CardBus function does not return any dynamic data.
12−9 DATASEL R Data select. This 4-bit field returns 0s when read. The CardBus function does not return any dynamic data.
8 ‡ PME_ENABLE RW This bit enables the function to assert PME. If this bit is cleared, then assertion of PME is disabled. This
bit is not cleared by the assertion of PRST. It is only cleared by the assertion of GRST.
7−2 RSVD R Reserved. These bits return 0s when read.
1−0 PWRSTATE RW
Power state. This 2-bit field is used both to determine the current power state of a function and to set the
function into a new power state. This field is encoded as:
00 = D0
01 = D1
10 = D2
11 = D3hot
†One or more bits in this register are PME context bits and can be cleared only by the assertion of GRST when PME is enabled. If PME is not
enabled, then this bit is cleared by the assertion of PRST or GRST.
‡One or more bits in this register are cleared only by the assertion of GRST.
4−33
4.45 Power Management Control/Status Bridge Support Extensions Register
This register supports PCI bridge-specific functionality. It is required for all PCI-to-PCI bridges. See Table 4−21 for
a complete description of the register contents.
Bit 7 6 5 4 3 2 1 0
Name Power management control/status bridge support extensions
Type R R R R R R R R
Default 1 1 0 0 0 0 0 0
Register: Power management control/status bridge support extensions
Offset: A6h (Functions 0, 1)
Type: Read-only
Default: C0h
Table 4−21. Power Management Control/Status Bridge Support Extensions Register Description
BIT SIGNAL TYPE FUNCTION
7 BPCC_EN R
Bus power/clock control enable. This bit returns 1 when read. This bit is encoded as:
0 = Bus power/clock control is disabled.
1 = Bus power/clock control is enabled (default).
A 0 indicates that the bus power/clock control policies defined in the PCI Bus Power Management Interface
Specification are disabled. When the bus power/clock control enable mechanism is disabled, the power
state field (bits 1−0) of the power management control/status register (PCI offset A4h, see Section 4.44)
cannot b e used by the system software to control the power or the clock of the secondary bus. A 1 indicates
that the bus power/clock control mechanism is enabled.
6 B2_B3 R
B2/B3 support for D3hot. The state of this bit determines the action that is to occur as a direct result of
programming the function to D3hot. This bit is only meaningful if bit 7 (BPCC_EN) is a 1. This bit is encoded
as:0 = When the bridge is programmed to D3hot, its secondary bus has its power removed (B3).
1 = When the bridge function is programmed to D3hot, its secondary bus PCI clock is stopped (B2)
(default).
5−0 RSVD R Reserved. These bits return 0s when read.
4.46 Power-Management Data Register
The power-management data register returns 0s when read, because the CardBus functions do not report dynamic
data.
Bit 7 6 5 4 3 2 1 0
Name Power-management data
Type R R R R R R R R
Default 0 0 0 0 0 0 0 0
Register: Power-management data
Offset: A7h (functions 0, 1)
Type: Read-only
Default: 00h
4−34
4.47 Serial Bus Data Register
The serial bus data register is for programmable serial bus byte reads and writes. This register represents the data
when generating cycles on the serial bus interface. To write a byte, this register must be programmed with the data,
the serial bus index register must be programmed with the byte address, the serial bus slave address must be
programmed with the 7-bit slave address, and the read/write indicator bit must be reset.
On byte reads, the byte address is programmed into the serial bus index register, the serial bus slave address register
must be programmed with both the 7-bit slave address and the read/write indicator bit, and bit 5 (REQBUSY) in the
serial bus control and status register (see Section 4.50) must be polled until clear. Then the contents of this register
are valid read data from the serial bus interface. See Table 4−22 for a complete description of the register contents.
Bit 7 6 5 4 3 2 1 0
Name Serial bus data
Type RW RW RW RW RW RW RW RW
Default 0 0 0 0 0 0 0 0
Register: Serial bus data
Offset: B0h (function 0)
Type: Read/Write
Default: 00h
Table 4−22. Serial Bus Data Register Description
BIT SIGNAL TYPE FUNCTION
7−0 ‡ SBDATA RW Serial bus data. This bit field represents the data byte in a read or write transaction on the serial interface.
On reads, the REQBUSY bit must be polled to verify that the contents of this register are valid.
‡One or more bits in this register are cleared only by the assertion of GRST.
4.48 Serial Bus Index Register
The serial bus index register is for programmable serial bus byte reads and writes. This register represents the byte
address when generating cycles on the serial bus interface. To write a byte, the serial bus data register must be
programmed with the data, this register must be programmed with the byte address, and the serial bus slave address
must be programmed with both the 7-bit slave address and the read/write indicator.
On byte reads, the word address is programmed into this register, the serial bus slave address must be programmed
with both the 7-bit slave address and the read/write indicator bit, and bit 5 (REQBUSY) in the serial bus control and
status register (see Section 4.50) must be polled until clear. Then the contents of the serial bus data register are valid
read data from the serial bus interface. See Table 4−23 for a complete description of the register contents.
Bit 7 6 5 4 3 2 1 0
Name Serial bus index
Type RW RW RW RW RW RW RW RW
Default 0 0 0 0 0 0 0 0
Register: Serial bus index
Offset: B1h (function 0)
Type: Read/Write
Default: 00h
Table 4−23. Serial Bus Index Register Description
BIT SIGNAL TYPE FUNCTION
7−0 ‡ SBINDEX RW Serial bu s index. This bit field represents the byte address in a read or write transaction on the serial interface.
‡One or more bits in this register are cleared only by the assertion of GRST.
4−35
4.49 Serial Bus Slave Address Register
The serial bus slave address register is for programmable serial bus byte read and write transactions. To write a byte,
the serial bus data register must be programmed with the data, the serial bus index register must be programmed
with the byte address, and this register must be programmed with both the 7-bit slave address and the read/write
indicator bit.
On byte reads, the byte address is programmed into the serial bus index register, this register must be programmed
with both the 7-bit slave address and the read/write indicator bit, and bit 5 (REQBUSY) in the serial bus control and
status register (see Section 4.50) must be polled until clear. Then the contents of the serial bus data register are valid
read data from the serial bus interface. See Table 4−24 for a complete description of the register contents.
Bit 7 6 5 4 3 2 1 0
Name Serial bus slave address
Type RW RW RW RW RW RW RW RW
Default 0 0 0 0 0 0 0 0
Register: Serial bus slave address
Offset: B2h (function 0)
Type: Read/Write
Default: 00h
Table 4−24. Serial Bus Slave Address Register Description
BIT SIGNAL TYPE FUNCTION
7−1 ‡ SLAVADDR RW Serial bus slave address. This bit field represents the slave address of a read or write transaction on the
serial interface.
0 ‡ RWCMD RW
Read/write command. Bit 0 indicates the read/write command bit presented to the serial bus on byte read
and write accesses.
0 = A byte write access is requested to the serial bus interface.
1 = A byte read access is requested to the serial bus interface.
‡One or more bits in this register are cleared only by the assertion of GRST.
4−36
4.50 Serial Bus Control/Status Register
The serial bus control and status register communicates serial bus status information and selects the quick command
protocol. Bit 5 (REQBUSY) in this register must be polled during serial bus byte reads to indicate when data is valid
in the serial bus data register. See Table 4−25 for a complete description of the register contents.
Bit 7 6 5 4 3 2 1 0
Name Serial bus control/status
Type RW R R R RW RW RC RC
Default 0 0 0 0 0 0 0 0
Register: Serial bus control/status
Offset: B3h (function 0)
Type: Read-only, Read/Write, Read/Clear
Default: 00h
Table 4−25. Serial Bus Control/Status Register Description
BIT SIGNAL TYPE FUNCTION
7 ‡ PROT_SEL RW Protocol select. When bit 7 is set, the send-byte protocol is used on write requests and the receive-byte
protocol is used on read commands. The word address byte in the serial bus index register (see
Section 4.48) is not output by the PCI6x21/PCI6x11 controller when bit 7 is set.
6 RSVD R Reserved. Bit 6 returns 0 when read.
5 REQBUSY R
Requested serial bus access busy. Bit 5 indicates that a requested serial bus access (byte read or write)
is in progress. A request is made, and bit 5 is set, by writing to the serial bus slave address register (see
Section 4.49). Bit 5 must be polled on reads from the serial interface. After the byte read access has been
completed, this bit is cleared and the read data is valid in the serial bus data register.
4 ROMBUSY R
Serial EEPROM busy status. Bit 4 indicates the status of the PCI6x21/PCI6x11 serial EEPROM circuitry.
Bit 4 is set during the loading of the subsystem ID and other default values from the serial bus EEPROM.
0 = Serial EEPROM circuitry is not busy
1 = Serial EEPROM circuitry is busy
3 ‡ SBDETECT RW
Serial bus detect. When the serial bus interface is detected through a pullup resistor on the SCL terminal
after reset, this bit is set to 1.
0 = Serial bus interface not detected
1 = Serial bus interface detected
2 ‡ SBTEST RW Serial bus test. When bit 2 is set, the serial bus clock frequency is increased for test purposes.
0 = Serial bus clock at normal operating frequency, 100 kHz (default)
1 = Serial bus clock frequency increased for test purposes
1 ‡ REQ_ERR RC
Requested serial bus access error. Bit 1 indicates when a data error occurs on the serial interface during
a requested cycle and may be set due to a missing acknowledge. Bit 1 is cleared by a writeback of 1.
0 = No error detected during user-requested byte read or write cycle
1 = Data error detected during user-requested byte read or write cycle
0 ‡ ROM_ERR RC
EEPROM data error status. Bit 0 indicates when a data error occurs on the serial interface during the
auto-load from the serial bus EEPROM and may be set due to a missing acknowledge. Bit 0 is also set on
invalid EEPROM data formats. See Section 3.6.4, Serial Bus EEPROM Application, for details on
EEPROM data format. Bit 0 is cleared by a writeback of 1.
0 = No error detected during autoload from serial bus EEPROM
1 = Data error detected during autoload from serial bus EEPROM
‡One or more bits in this register are cleared only by the assertion of GRST.
5−1
5 ExCA Compatibility Registers (Functions 0 and 1)
The ExCA (exchangeable card architecture) registers implemented in the PCI6x21/PCI6x11 controller are
register-compatible with the Intel 82365SL-DF PCMCIA controller. ExCA registers are identified by an offset value,
which is compatible with the legacy I/O index/data scheme used on the Intel 82365 ISA controller. The ExCA
registers are a c c essed through this scheme by writing the register offset value into the index register (I/O base), and
reading or writing the data register (I/O base + 1). The I/O base address used in the index/data scheme is programmed
in the PC Card 16-bit I/F legacy mode base address register, which is shared by both card sockets. The offsets from
this base address run contiguously from 00h to 3Fh for socket A, and from 40h to 7Fh for socket B. See Figure 5−1
for an ExCA I/O mapping illustration. Table 5−1 identifies each ExCA register and its respective ExCA offset.
The PCI6x21/PCI6x11 controller also provides a memory-mapped alias of the ExCA registers by directly mapping
them into PCI memory space. They are located through the CardBus socket registers/ExCA registers base address
register (PCI register 10h) at memory offset 800h. Each socket has a separate base address programmable by
function. See Figure 5−2 for an ExCA memory mapping illustration. Note that memory of fsets are 800h−844h for both
functions 0 and 1. This illustration also identifies the CardBus socket register mapping, which is mapped into the same
4K window at memory offset 0h.
The interrupt registers in the ExCA register set, as defined by the 82365SL specification, control such card functions
as reset, type, interrupt routing, and interrupt enables. Special attention must be paid to the interrupt routing registers
and the host interrupt signaling method selected for the PCI6x21/PCI6x11 controller to ensure that all possible
PCI6x21/PCI6x11 interrupts can potentially be routed to the programmable interrupt controller. The ExCA registers
that are critical to the interrupt signaling are at memory address ExCA offsets 803h and 805h.
Access to I/O mapped 16-bit PC Cards is available to the host system via two ExCA I/O windows. These are regions
of host I/O address space into which the card I/O space is mapped. These windows are defined by start, end, and
offset addresses programmed in the ExCA registers described in this chapter. I/O windows have byte granularity.
Access to memory-mapped 16-bit PC Cards is available to the host system via five ExCA memory windows. These
are regions of host memory space into which the card memory space is mapped. These windows are defined by start,
end, and offset addresses programmed in the ExCA registers described in this chapter. Memory windows have
4-Kbyte granularity.
A bit location followed by a ‡ means that this bit is not cleared by the assertion of PRST. This bit is only cleared by
the assertion of GRST. This is necessary to retain device context during the transition from D3 to D0.
5−2
16-Bit Legacy-Mode Base Address
PCI6x21/PCI6x11 Configuration Registers
10hCardBus Socket/ExCA Base Address
Note: The 16-bit legacy-mode base address
register is shared by function 0 and 1 as
indicated by the shading.
44h
Index
Data
Host I/O Space
PC Card A
ExCA
Registers
PC Card B
ExCA
Registers
00h
Offset
3Fh
40h
7Fh
Offset of desired register is placed in the index register and the
data from that location is returned in the data register.
Offset
Figure 5−1. ExCA Register Access Through I/O
16-Bit Legacy-Mode Base Address
CardBus Socket/ExCA Base Address 10h
44h
CardBus
Socket A
Registers
ExCA
Registers
Card A
20h
800h
844h
Host
Memory Space
CardBus
Socket B
Registers
ExCA
Registers
Card B
20h
800h
844h
Host
Memory Space
Note: The CardBus socket/ExCA base
address mode register is separate for
functions 0 and 1.
address register’s base address.
Offsets are from the CardBus socket/ExCA base
00h
00h
PCI6x21/PCI6x11 Configuration Registers Offset
Offset
Offset
Figure 5−2. ExCA Register Access Through Memory
5−3
Table 5−1. ExCA Registers and Offsets
EXCA REGISTER NAME PCI MEMORY ADDRESS
OFFSET (HEX) EXCA OFFSET
(CARD A) EXCA OFFSET
(CARD B)
Identification and revision ‡ 800 00 40
Interface status 801 01 41
Power control † 802† 02 42
Interrupt and general control † 803† 03 43
Card status change † 804† 04 44
Card status change interrupt configuration † 805† 05 45
Address window enable 806 06 46
I / O window control 807 07 47
I / O window 0 start-address low-byte 808 08 48
I / O window 0 start-address high-byte 809 09 49
I / O window 0 end-address low-byte 80A 0A 4A
I / O window 0 end-address high-byte 80B 0B 4B
I / O window 1 start-address low-byte 80C 0C 4C
I / O window 1 start-address high-byte 80D 0D 4D
I / O window 1 end-address low-byte 80E 0E 4E
I / O window 1 end-address high-byte 80F 0F 4F
Memory window 0 start-address low-byte 810 10 50
Memory window 0 start-address high-byte 811 11 51
Memory window 0 end-address low-byte 812 12 52
Memory window 0 end-address high-byte 813 13 53
Memory window 0 offset-address low-byte 814 14 54
Memory window 0 offset-address high-byte 815 15 55
Card detect and general control † 816 16 56
Reserved 817 17 57
Memory window 1 start-address low-byte 818 18 58
Memory window 1 start-address high-byte 819 19 59
Memory window 1 end-address low-byte 81A 1A 5A
Memory window 1 end-address high-byte 81B 1B 5B
Memory window 1 offset-address low-byte 81C 1C 5C
Memory window 1 offset-address high-byte 81D 1D 5D
Global control ‡ 81E 1E 5E
Reserved 81F 1F 5F
Memory window 2 start-address low-byte 820 20 60
Memory window 2 start-address high-byte 821 21 61
Memory window 2 end-address low-byte 822 22 62
Memory window 2 end-address high-byte 823 23 63
Memory window 2 offset-address low-byte 824 24 64
Memory window 2 offset-address high-byte 825 25 65
†One or more bits in this register are cleared only by the assertion of GRST when PME is enabled. If PME is not enabled, then this bit is cleared
by the assertion of PRST or GRST.
‡One or more bits in this register are cleared only by the assertion of GRST.
5−4
Table 5−1. ExCA Registers and Offsets (continued)
EXCA REGISTER NAME PCI MEMORY ADDRESS
OFFSET (HEX) EXCA OFFSET
(CARD A) EXCA OFFSET
(CARD B)
Reserved 826 26 66
Reserved 827 27 67
Memory window 3 start-address low-byte 828 28 68
Memory window 3 start-address high-byte 829 29 69
Memory window 3 end-address low-byte 82A 2A 6A
Memory window 3 end-address high-byte 82B 2B 6B
Memory window 3 offset-address low-byte 82C 2C 6C
Memory window 3 offset-address high-byte 82D 2D 6D
Reserved 82E 2E 6E
Reserved 82F 2F 6F
Memory window 4 start-address low-byte 830 30 70
Memory window 4 start-address high-byte 831 31 71
Memory window 4 end-address low-byte 832 32 72
Memory window 4 end-address high-byte 833 33 73
Memory window 4 offset-address low-byte 834 34 74
Memory window 4 offset-address high-byte 835 35 75
I/O window 0 offset-address low-byte 836 36 76
I/O window 0 offset-address high-byte 837 37 77
I/O window 1 offset-address low-byte 838 38 78
I/O window 1 offset-address high-byte 839 39 79
Reserved 83A 3A 7A
Reserved 83B 3B 7B
Reserved 83C 3C 7C
Reserved 83D 3D 7D
Reserved 83E 3E 7E
Reserved 83F 3F 7F
Memory window page register 0 840 − −
Memory window page register 1 841 − −
Memory window page register 2 842 − −
Memory window page register 3 843 − −
Memory window page register 4 844 − −
5−5
5.1 ExCA Identification and Revision Register
This register provides host software with information on 16-bit PC Card support and 82365SL-DF compatibility. See
Table 5−2 for a complete description of the register contents.
NOTE: If bit 5 (SUBSYRW) in the system control register is 1, then this register is read-only.
Bit 7 6 5 4 3 2 1 0
Name ExCA identification and revision
Type R R RW RW RW RW RW RW
Default 1 0 0 0 0 1 0 0
Register: ExCA identification and revision
Offset: CardBus Socket Address + 800h: Card A ExCA Offset 00h
Card B ExCA Offset 40h
Type: Read/Write, Read-only
Default: 84h
Table 5−2. ExCA Identification and Revision Register Description
BIT SIGNAL TYPE FUNCTION
7−6 ‡ IFTYPE R Interface type. These bits, which are hardwired as 10b, identify the 16-bit PC Card support provided by the
PCI6x21/PCI6x11 controller. The PCI6x21/PCI6x11 controller supports both I/O and memory 16-bit PC
Cards.
5−4 ‡ RSVD RW These bits can be used for 82365SL emulation.
3−0 ‡ 365REV RW 82365SL-DF revision. This field stores the Intel 82365SL-DF revision supported by the PCI6x21/PCI6x11
controller. Host software can read this field to determine compatibility to the 82365SL-DF register set. This
field defaults to 0100b upon reset. W riting 0010b to this field places the controller in the 82356SL mode.
‡One or more bits in this register are cleared only by the assertion of GRST.
5−6
5.2 ExCA Interface Status Register
This register provides information on current status of the PC Card interface. An X in the default bit values indicates
that the value of the bit after reset depends on the state of the PC Card interface. See Table 5−3 for a complete
description of the register contents.
Bit 7 6 5 4 3 2 1 0
Name ExCA interface status
Type RRRRRRRR
Default 0 0 X X X X X X
Register: ExCA interface status
Offset: CardBus Socket Address + 801h: Card A ExCA Offset 01h
Card B ExCA Offset 41h
Type: Read-only
Default: 00XX XXXXb
Table 5−3. ExCA Interface Status Register Description
BIT SIGNAL TYPE FUNCTION
7 RSVD R This bit returns 0 when read. A write has no effect.
6 CARDPWR R
CARDPWR. Card power. This bit indicates the current power status of the PC Card socket. This bit reflects
how the ExCA power control register has been programmed. The bit is encoded as:
0 = VCC and VPP to the socket are turned off (default).
1 = VCC and VPP to the socket are turned on.
5 READY R This bit indicates the current status of the READY signal at the PC Card interface.
0 = PC Card is not ready for a data transfer.
1 = PC Card is ready for a data transfer.
4 CARDWP R
Card write protect. This bit indicates the current status of the WP signal at the PC Card interface. This signal
reports to the PCI6x21/PCI6x11 controller whether or not the memory card is write protected. Further, write
protection for an entire PCI6x21/PCI6x11 16-bit memory window is available by setting the appropriate bit
in the ExCA memory window offset-address high-byte register.
0 = WP signal is 0. PC Card is R/W.
1 = WP signal is 1. PC Card is read-only.
3 CDETECT2 R
Card detect 2. This bit indicates the status of the CD2 signal at the PC Card interface. Software can use
this and CDETECT1 to determine if a PC Card is fully seated in the socket.
0 = CD2 signal is 1. No PC Card inserted.
1 = CD2 signal is 0. PC Card at least partially inserted.
2 CDETECT1 R
Card detect 1. This bit indicates the status of the CD1 signal at the PC Card interface. Software can use
this and CDETECT2 to determine if a PC Card is fully seated in the socket.
0 = CD1 signal is 1. No PC Card inserted.
1 = CD1 signal is 0. PC Card at least partially inserted.
1−0 BVDSTAT R
Battery voltage detect. When a 16-bit memory card is inserted, the field indicates the status of the battery
voltage detect signals (BVD1, BVD2) at the PC Card interface, where bit 0 reflects the BVD1 status, and
bit 1 reflects BVD2.
00 = Battery is dead.
01 = Battery is dead.
10 = Battery is low; warning.
11 = Battery is good.
When a 16-bit I/O card is inserted, this field indicates the status of the SPKR (bit 1) signal and the STSCHG
(bit 0) a t the PC Card interface. In this case, the two bits in this field directly reflect the current state of these
card outputs.
5−7
5.3 ExCA Power Control Register
This register provides PC Card power control. Bit 7 of this register enables the 16-bit outputs on the socket interface,
and can be used for power management in 16-bit PC Card applications. See Table 5−5 for a complete description
of the register contents.
Bit 7 6 5 4 3 2 1 0
Name ExCA power control
Type RW R R RW RW RRW RW
Default 0 0 0 0 0 0 0 0
Register: ExCA power control
Offset: CardBus Socket Address + 802h: Card A ExCA Offset 02h
Card B ExCA Offset 42h
Type: Read-only, Read/Write
Default: 00h
Table 5−4. ExCA Power Control Register Description—82365SL Support
BIT SIGNAL TYPE FUNCTION
7 COE RW
Card output enable. Bit 7 controls the state of all of the 16-bit outputs on the PCI6x21/PCI6x11 controller.
This bit is encoded as:
0 = 16-bit PC Card outputs disabled (default)
1 = 16-bit PC Card outputs enabled
6 RSVD R Reserved. Bit 6 returns 0 when read.
5 † AUTOPWRSWEN RW Auto power switch enable.
0 = Automatic socket power switching based on card detects is disabled.
1 = Automatic socket power switching based on card detects is enabled.
4 CAPWREN RW
PC Card power enable.
0 = VCC = No connection
1 = VCC is enabled and controlled by bit 2 (EXCAPOWER) of the system control register
(PCI offset 80h, see Section 4.29).
3−2 RSVD R Reserved. Bits 3 and 2 return 0s when read.
1−0 EXCAVPP RW
PC Card VPP power control. Bits 1 and 0 are used to request changes to card VPP. The PCI6x21/PCI6x11
controller ignores this field unless VCC to the socket is enabled. This field is encoded as:
00 = No connection (default) 10 = 12 V
01 = VCC 11 = Reserved
†One or more bits in this register are cleared only by the assertion of GRST when PME is enabled. If PME is not enabled, then this bit is cleared
by the assertion of PRST or GRST.
Table 5−5. ExCA Power Control Register Description—82365SL-DF Support
BIT SIGNAL TYPE FUNCTION
7 † COE RW
Card output enable. This bit controls the state of all of the 16-bit outputs on the PCI6x21/PCI6x11 controller.
This bit is encoded as:
0 = 16-bit PC Card outputs are disabled (default).
1 = 16-bit PC Card outputs are enabled.
6−5 RSVD R Reserved. These bits return 0s when read. Writes have no effect.
4−3 † EXCAVCC RW VCC. These bits are used to request changes to card VCC. This field is encoded as:
00 = 0 V (default) 10 = 5 V
01 = 0 V reserved 11 = 3.3 V
2 RSVD R This bit returns 0 when read. A write has no effect.
1−0 † EXCAVPP RW
VPP. These bits are used to request changes to card VPP. The PCI6x21/PCI6x11 controller ignores this
field unless VCC to the socket is enabled (i.e., 5 Vdc or 3.3 Vdc). This field is encoded as:
00 = 0 V (default) 10 = 12 V
01 = VCC 11 = 0 V reserved
†This bit is cleared only by the assertion of GRST when PME is enabled. If PME is not enabled, then this bit is cleared by the assertion of PRST
or GRST.
5−8
5.4 ExCA Interrupt and General Control Register
This register controls interrupt routing for I/O interrupts as well as other critical 16-bit PC Card functions. See
Table 5−6 for a complete description of the register contents.
Bit 7 6 5 4 3 2 1 0
Name ExCA interrupt and general control
Type RW RW RW RW RW RW RW RW
Default 0 0 0 0 0 0 0 0
Register: ExCA interrupt and general control
Offset: CardBus Socket Address + 803h: Card A ExCA Offset 03h
Card B ExCA Offset 43h
Type: Read/Write
Default: 00h
Table 5−6. ExCA Interrupt and General Control Register Description
BIT SIGNAL TYPE FUNCTION
7 RINGEN RW
Card ring indicate enable. Enables the ring indicate function of the BVD1/RI terminals. This bit is encoded
as:0 = Ring indicate disabled (default)
1 = Ring indicate enabled
6 † RESET RW
Card reset. This bit controls the 16-bit PC Card RESET signal, and allows host software to force a card
reset. This bit affects 16-bit cards only. This bit is encoded as:
0 = RESET signal asserted (default)
1 = RESET signal deasserted.
5 † CARDTYPE RW Card type. This bit indicates the PC Card type. This bit is encoded as:
0 = Memory PC Card is installed (default)
1 = I/O PC Card is installed
4 CSCROUTE RW
PCI interrupt − CSC routing enable bit. This bit has meaning only if the CSC interrupt routing control bit
(PCI offset 93h, bit 5) is 0. In this case, when this bit is set (high), the card status change interrupts are
routed t o PCI interrupts. When low, the card status change interrupts are routed using bits 7−4 in the ExCA
card status-change interrupt configuration register (ExCA offset 805h, see Section 5.6). This bit is encoded
as:0 = CSC interrupts routed by ExCA registers (default)
1 = CSC interrupts routed to PCI interrupts
If the CSC interrupt routing control bit (bit 5) of the diagnostic register (PCI offset 93h, see Section 4.40)
is set to 1, this bit has no meaning, which is the default case.
3−0 INTSELECT RW
Card interrupt select for I/O PC Card functional interrupts. These bits select the interrupt routing for I/O
PC Card functional interrupts. This field is encoded as:
0000 = N o IRQ selected (default). CSC interrupts are routed to PCI Interrupts. This bit setting is ORed
with bit 4 (CSCROUTE) for backward compatibility.
0001 = IRQ1 enabled
0010 = SMI enabled
0011 = IRQ3 enabled
0100 = IRQ4 enabled
0101 = IRQ5 enabled
0110 = IRQ6 enabled
0111 = IRQ7 enabled
1000 = IRQ8 enabled
1001 = IRQ9 enabled
1010 = IRQ10 enabled
1011 = IRQ11 enabled
1100 = IRQ12 enabled
1101 = IRQ13 enabled
1110 = IRQ14 enabled
1111 = IRQ15 enabled
†This bit is cleared only by the assertion of GRST when PME is enabled. If PME is not enabled, then this bit is cleared by the assertion of PRST
or GRST.
5−9
5.5 ExCA Card Status-Change Register
The ExCA card status-change register controls interrupt routing for I/O interrupts as well as other critical 16-bit PC
Card functions. The register enables these interrupt sources to generate an interrupt to the host. When the interrupt
source is disabled, the corresponding bit in this register always reads 0. When an interrupt source is enabled, the
corresponding bit in this register is set to indicate that the interrupt source is active. After generating the interrupt to
the host, the interrupt service routine must read this register to determine the source of the interrupt. The interrupt
service routine is responsible for resetting the bits in this register as well. Resetting a bit is accomplished by one of
two methods: a read of this register or an explicit writeback of 1 to the status bit. The choice of these two methods
is based on bit 2 (interrupt flag clear mode select) in the ExCA global control register (CB offset 81Eh, see
Section 5.20). See Table 5−7 for a complete description of the register contents.
Bit 7 6 5 4 3 2 1 0
Name ExCA card status-change
Type R R R R R R R R
Default 0 0 0 0 0 0 0 0
Register: ExCA card status-change
Type: Read-only
Offset: CardBus socket address + 804h; Card A ExCA offset 04h
Card B ExCA offset 44h
Default: 00h
Table 5−7. ExCA Card Status-Change Register Description
BIT SIGNAL TYPE FUNCTION
7−4 RSVD R Reserved. Bits 7−4 return 0s when read.
3 † CDCHANGE R
Card detect change. Bit 3 indicates whether a change on CD1 or CD2 occurred at the PC Card
interface. This bit is encoded as:
0 = No change detected on either CD1 or CD2
1 = Change detected on either CD1 or CD2
2 † READYCHANGE R
Ready change. When a 16-bit memory is installed in the socket, bit 2 includes whether the source of
a PCI6x21/PCI6x11 interrupt was due to a change on READY at the PC Card interface, indicating that
the PC Card is now ready to accept new data. This bit is encoded as:
0 = No low-to-high transition detected on READY (default)
1 = Detected low-to-high transition on READY
When a 16-bit I/O card is installed, bit 2 is always 0.
1 † BATWARN R
Battery warning change. When a 16-bit memory card is installed in the socket, bit 1 indicates whether
the source of a PCI6x21/PCI6x11 interrupt was due to a battery-low warning condition. This bit is
encoded as:
0 = No battery warning condition (default)
1 = Detected battery warning condition
When a 16-bit I/O card is installed, bit 1 is always 0.
0 † BATDEAD R
Battery dead or status change. When a 16-bit memory card is installed in the socket, bit 0 indicates
whether the source of a PCI6x21/PCI6x11 interrupt was due to a battery dead condition. This bit is
encoded as:
0 = STSCHG deasserted (default)
1 = STSCHG asserted
Ring indicate. When the PCI6x21/PCI6x11 is configured for ring indicate operation, bit 0 indicates the
status of RI.
†These are PME context bits and can be cleared only by the assertion of GRST when PME is enabled. If PME is not enabled, then these bits are
cleared by the assertion of PRST or GRST.
5−10
5.6 ExCA Card Status-Change Interrupt Configuration Register
This register controls interrupt routing for CSC interrupts, as well as masks/unmasks CSC interrupt sources. See
Table 5−8 for a complete description of the register contents.
Bit 7 6 5 4 3 2 1 0
Name ExCA card status-change interrupt configuration
Type RW RW RW RW RW RW RW RW
Default 0 0 0 0 0 0 0 0
Register: ExCA card status-change interrupt configuration
Offset: CardBus Socket Address + 805h: Card A ExCA Offset 05h
Card B ExCA Offset 45h
Type: Read/Write
Default: 00h
Table 5−8. ExCA Card Status-Change Interrupt Configuration Register Description
BIT SIGNAL TYPE FUNCTION
7−4 CSCSELECT RW
Interrupt select for card status change. These bits select the interrupt routing for card status-change
interrupts. This field is encoded as:
0000 = CSC interrupts routed to PCI interrupts if bit 5 of the diagnostic register (PCI offset 93h) is set
to 1b. In this case bit 4 of ExCA 803 is a don’t care. This is the default setting.
0000 = N o I S A i n t errupt routing if bit 5 of the diagnostic register (PCI of fset 93h) is set to 0b. In this case,
CSC interrupts are routed to PCI interrupts by setting bit 4 of ExCA 803h to 1b.
0001 = IRQ1 enabled
0010 = SMI enabled
0011 = IRQ3 enabled
0100 = IRQ4 enabled
0101 = IRQ5 enabled
0110 = IRQ6 enabled
0111 = IRQ7 enabled
1000 = IRQ8 enabled
1001 = IRQ9 enabled
1010 = IRQ10 enabled
1011 = IRQ11 enabled
1100 = IRQ12 enabled
1101 = IRQ13 enabled
1110 = IRQ14 enabled
1111 = IRQ15 enabled
3† CDEN RW Card detect enable. Enables interrupts on CD1 or CD2 changes. This bit is encoded as:
0 = Disables interrupts on CD1 or CD2 line changes (default)
1 = Enables interrupts on CD1 or CD2 line changes
2† READYEN RW
Ready enable. This bit enables/disables a low-to-high transition on the PC Card READY signal to generate
a host interrupt. This interrupt source is considered a card status change. This bit is encoded as:
0 = Disables host interrupt generation (default)
1 = Enables host interrupt generation
1† BATWARNEN RW
Battery warning enable. This bit enables/disables a battery warning condition to generate a CSC interrupt.
This bit is encoded as:
0 = Disables host interrupt generation (default)
1 = Enables host interrupt generation
0† BATDEADEN RW
Battery dead enable. This bit enables/disables a battery dead condition on a memory PC Card or assertion
of the STSCHG I/O PC Card signal to generate a CSC interrupt.
0 = Disables host interrupt generation (default)
1 = Enables host interrupt generation
†This bit is cleared only by the assertion of GRST when PME is enabled. If PME is not enabled, then this bit is cleared by the assertion of PRST
or GRST.
5−11
5.7 ExCA Address Window Enable Register
The ExCA address window enable register enables/disables the memory and I/O windows to the 16-bit PC Card. By
default, all windows to the card are disabled. The PCI6x21/PCI6x11 controller does not acknowledge PCI memory
or I/O cycles to the card if the corresponding enable bit in this register is 0, regardless of the programming of the
memory or I/O window start/end/offset address registers. See Table 5−9 for a complete description of the register
contents.
Bit 7 6 5 4 3 2 1 0
Name ExCA address window enable
Type RW RW RRW RW RW RW RW
Default 0 0 0 0 0 0 0 0
Register: ExCA address window enable
Type: Read-only, Read/Write
Offset: CardBus socket address + 806h; Card A ExCA offset 06h
Card B ExCA offset 46h
Default: 00h
Table 5−9. ExCA Address Window Enable Register Description
BIT SIGNAL TYPE FUNCTION
7 IOWIN1EN RW I/O window 1 enable. Bit 7 enables/disables I/O window 1 for the PC Card. This bit is encoded as:
0 = I/O window 1 disabled (default)
1 = I/O window 1 enabled
6 IOWIN0EN RW I/O window 0 enable. Bit 6 enables/disables I/O window 0 for the PC Card. This bit is encoded as:
0 = I/O window 0 disabled (default)
1 = I/O window 0 enabled
5 RSVD R Reserved. Bit 5 returns 0 when read.
4 MEMWIN4EN RW
Memory window 4 enable. Bit 4 enables/disables memory window 4 for the PC Card. This bit is
encoded as:
0 = Memory window 4 disabled (default)
1 = Memory window 4 enabled
3 MEMWIN3EN RW
Memory window 3 enable. Bit 3 enables/disables memory window 3 for the PC Card. This bit is
encoded as:
0 = Memory window 3 disabled (default)
1 = Memory window 3 enabled
2 MEMWIN2EN RW
Memory window 2 enable. Bit 2 enables/disables memory window 2 for the PC Card. This bit is
encoded as:
0 = Memory window 2 disabled (default)
1 = Memory window 2 enabled
1 MEMWIN1EN RW
Memory window 1 enable. Bit 1 enables/disables memory window 1 for the PC Card. This bit is
encoded as:
0 = Memory window 1 disabled (default)
1 = Memory window 1 enabled
0 MEMWIN0EN RW
Memory window 0 enable. Bit 0 enables/disables memory window 0 for the PC Card. This bit is
encoded as:
0 = Memory window 0 disabled (default)
1 = Memory window 0 enabled
5−12
5.8 ExCA I/O Window Control Register
The ExCA I/O window control register contains parameters related to I/O window sizing and cycle timing. See
Table 5−10 for a complete description of the register contents.
Bit 7 6 5 4 3 2 1 0
Name ExCA I/O window control
Type RW RW RW RW RW RW RW RW
Default 0 0 0 0 0 0 0 0
Register: ExCA I/O window control
Type: Read/Write
Offset: CardBus socket address + 807h: Card A ExCA offset 07h
Card B ExCA offset 47h
Default: 00h
Table 5−10. ExCA I/O Window Control Register Description
BIT SIGNAL TYPE FUNCTION
7 WAITSTATE1 RW
I/O window 1 wait state. Bit 7 controls the I/O window 1 wait state for 16-bit I/O accesses. Bit 7 has no effect
on 8-bit accesses. This wait-state timing emulates the ISA wait state used by the Intel 82365SL-DF. This
bit is encoded as:
0 = 16-bit cycles have standard length (default).
1 = 16-bit cycles are extended by one equivalent ISA wait state.
6 ZEROWS1 RW
I/O window 1 zero wait state. Bit 6 controls the I/O window 1 wait state for 8-bit I/O accesses. Bit 6 has
no effect on 16-bit accesses. This wait-state timing emulates the ISA wait state used by the Intel
82365SL-DF. This bit is encoded as:
0 = 8-bit cycles have standard length (default).
1 = 8-bit cycles are reduced to equivalent of three ISA cycles.
5 IOSIS16W1 RW
I/O window 1 IOIS16 source. Bit 5 controls the I/O window 1 automatic data-sizing feature that uses IOIS16
from the PC Card to determine the data width of the I/O data transfer. This bit is encoded as:
0 = Window data width determined by DATASIZE1, bit 4 (default).
1 = Window data width determined by IOIS16.
4 DATASIZE1 RW
I/O window 1 data size. Bit 4 controls the I/O window 1 data size. Bit 4 is ignored if bit 5 (IOSIS16W1) is
set. This bit is encoded as:
0 = Window data width is 8 bits (default).
1 = Window data width is 16 bits.
3 WAITSTATE0 RW
I/O window 0 wait state. Bit 3 controls the I/O window 0 wait state for 16-bit I/O accesses. Bit 3 has no effect
on 8-bit accesses. This wait-state timing emulates the ISA wait state used by the Intel 82365SL-DF. This
bit is encoded as:
0 = 16-bit cycles have standard length (default).
1 = 16-bit cycles are extended by one equivalent ISA wait state.
2 ZEROWS0 RW
I/O window 0 zero wait state. Bit 2 controls the I/O window 0 wait state for 8-bit I/O accesses. Bit 2 has
no effect on 16-bit accesses. This wait-state timing emulates the ISA wait state used by the Intel
82365SL-DF. This bit is encoded as:
0 = 8-bit cycles have standard length (default).
1 = 8-bit cycles are reduced to equivalent of three ISA cycles.
1 IOSIS16W0 RW
I/O window 0 IOIS16 source. Bit 1 controls the I/O window 0 automatic data sizing feature that uses IOIS16
from the PC Card to determine the data width of the I/O data transfer. This bit is encoded as:
0 = Window data width is determined by DATASIZE0, bit 0 (default).
1 = Window data width is determined by IOIS16.
0 DATASIZE0 RW
I/O window 0 data size. Bit 0 controls the I/O window 0 data size. Bit 0 is ignored if bit 1 (IOSIS16W0) is
set. This bit is encoded as:
0 = Window data width is 8 bits (default).
1 = Window data width is 16 bits.
5−13
5.9 ExCA I/O Windows 0 and 1 Start-Address Low-Byte Registers
These registers contain the low byte of the 16-bit I/O window start address for I/O windows 0 and 1. The 8 bits of these
registers correspond to the lower 8 bits of the start address.
Bit 7 6 5 4 3 2 1 0
Name ExCA I/O windows 0 and 1 start-address low-byte
Type RW RW RW RW RW RW RW RW
Default 0 0 0 0 0 0 0 0
Register: ExCA I/O window 0 start-address low-byte
Offset: CardBus Socket Address + 808h: Card A ExCA Offset 08h
Card B ExCA Offset 48h
Register: ExCA I/O window 1 start-address low-byte
Offset: CardBus Socket Address + 80Ch: Card A ExCA Of fset 0Ch
Card B ExCA Offset 4Ch
Type: Read/Write
Default: 00h
5.10 ExCA I/O Windows 0 and 1 Start-Address High-Byte Registers
These registers contain the high byte of the 16-bit I/O window start address for I/O windows 0 and 1. The 8 bits of
these registers correspond to the upper 8 bits of the start address.
Bit 7 6 5 4 3 2 1 0
Name ExCA I/O windows 0 and 1 start-address high-byte
Type RW RW RW RW RW RW RW RW
Default 0 0 0 0 0 0 0 0
Register: ExCA I/O window 0 start-address high-byte
Offset: CardBus Socket Address + 809h: Card A ExCA Offset 09h
Card B ExCA Offset 49h
Register: ExCA I/O window 1 start-address high-byte
Offset: CardBus Socket Address + 80Dh: Card A ExCA Of fset 0Dh
Card B ExCA Offset 4Dh
Type: Read/Write
Default: 00h
5−14
5.11 ExCA I/O Windows 0 and 1 End-Address Low-Byte Registers
These registers contain the low byte of the 16-bit I/O window end address for I/O windows 0 and 1. The 8 bits of these
registers correspond to the lower 8 bits of the start address.
Bit 7 6 5 4 3 2 1 0
Name ExCA I/O windows 0 and 1 end-address low-byte
Type RW RW RW RW RW RW RW RW
Default 0 0 0 0 0 0 0 0
Register: ExCA I/O window 0 end-address low-byte
Offset: CardBus Socket Address + 80Ah: Card A ExCA Offset 0Ah
Card B ExCA Offset 4Ah
Register: ExCA I/O window 1 end-address low-byte
Offset: CardBus Socket Address + 80Eh: Card A ExCA Offset 0Eh
Card B ExCA Offset 4Eh
Type: Read/Write
Default: 00h
5.12 ExCA I/O Windows 0 and 1 End-Address High-Byte Registers
These registers contain the high byte of the 16-bit I/O window end address for I/O windows 0 and 1. The 8 bits of these
registers correspond to the upper 8 bits of the end address.
Bit 7 6 5 4 3 2 1 0
Name ExCA I/O windows 0 and 1 end-address high-byte
Type RW RW RW RW RW RW RW RW
Default 0 0 0 0 0 0 0 0
Register: ExCA I/O window 0 end-address high-byte
Offset: CardBus Socket Address + 80Bh: Card A ExCA Offset 0Bh
Card B ExCA Offset 4Bh
Register: ExCA I/O window 1 end-address high-byte
Offset: CardBus Socket Address + 80Fh: Card A ExCA Offset 0Fh
Card B ExCA Offset 4Fh
Type: Read/Write
Default: 00h
5−15
5.13 ExCA Memory Windows 0−4 Start-Address Low-Byte Registers
These registers contain the low byte of the 16-bit memory window start address for memory windows 0, 1, 2, 3, and 4.
The 8 bits of these registers correspond to bits A19−A12 of the start address.
Bit 7 6 5 4 3 2 1 0
Name ExCA memory windows 0−4 start-address low-byte
Type RW RW RW RW RW RW RW RW
Default 0 0 0 0 0 0 0 0
Register: ExCA memory window 0 start-address low-byte
Offset: CardBus Socket Address + 810h: Card A ExCA Offset 10h
Card B ExCA Offset 50h
Register: ExCA memory window 1 start-address low-byte
Offset: CardBus Socket Address + 818h: Card A ExCA Offset 18h
Card B ExCA Offset 58h
Register: ExCA memory window 2 start-address low-byte
Offset: CardBus Socket Address + 820h: Card A ExCA Offset 20h
Card B ExCA Offset 60h
Register: ExCA memory window 3 start-address low-byte
Offset: CardBus Socket Address + 828h: Card A ExCA Offset 28h
Card B ExCA Offset 68h
Register: ExCA memory window 4 start-address low-byte
Offset: CardBus Socket Address + 830h: Card A ExCA Offset 30h
Card B ExCA Offset 70h
Type: Read/Write
Default: 00h
5−16
5.14 ExCA Memory Windows 0−4 Start-Address High-Byte Registers
These registers contain the high nibble of the 16-bit memory window start address for memory windows 0, 1, 2, 3,
and 4. The lower 4 bits of these registers correspond to bits A23−A20 of the start address. In addition, the memory
window data width and wait states are set in this register. See Table 5−11 for a complete description of the register
contents.
Bit 7 6 5 4 3 2 1 0
Name ExCA memory windows 0−4 start-address high-byte
Type RW RW RW RW RW RW RW RW
Default 0 0 0 0 0 0 0 0
Register: ExCA memory window 0 start-address high-byte
Offset: CardBus Socket Address + 811h: Card A ExCA Offset 11h
Card B ExCA Offset 51h
Register: ExCA memory window 1 start-address high-byte
Offset: CardBus Socket Address + 819h: Card A ExCA Offset 19h
Card B ExCA Offset 59h
Register: ExCA memory window 2 start-address high-byte
Offset: CardBus Socket Address + 821h: Card A ExCA Offset 21h
Card B ExCA Offset 61h
Register: ExCA memory window 3 start-address high-byte
Offset: CardBus Socket Address + 829h: Card A ExCA Offset 29h
Card B ExCA Offset 69h
Register: ExCA memory window 4 start-address high-byte
Offset: CardBus Socket Address + 831h: Card A ExCA Offset 31h
Card B ExCA Offset 71h
Type: Read/Write
Default: 00h
Table 5−11. ExCA Memory Windows 0−4 Start-Address High-Byte Registers Description
BIT SIGNAL TYPE FUNCTION
7 DATASIZE RW This bit controls the memory window data width. This bit is encoded as:
0 = Window data width is 8 bits (default)
1 = Window data width is 16 bits
6 ZEROWAIT RW
Zero wait-state. This bit controls the memory window wait state for 8- and 16-bit accesses. This wait-state
timing emulates the ISA wait state used by the 82365SL-DF. This bit is encoded as:
0 = 8- and 16-bit cycles have standard length (default).
1 = 8-bit cycles reduced to equivalent of three ISA cycles
16-bit cycles reduced to the equivalent of two ISA cycles
5−4 SCRATCH RW Scratch pad bits. These bits have no effect on memory window operation.
3−0 STAHN RW Start address high-nibble. These bits represent the upper address bits A23−A20 of the memory window
start address.
5−17
5.15 ExCA Memory Windows 0−4 End-Address Low-Byte Registers
These registers contain the low byte of the 16-bit memory window end address for memory windows 0, 1, 2, 3 , a n d 4.
The 8 bits of these registers correspond to bits A19−A12 of the end address.
Bit 7 6 5 4 3 2 1 0
Name ExCA memory windows 0−4 end-address low-byte
Type RW RW RW RW RW RW RW RW
Default 0 0 0 0 0 0 0 0
Register: ExCA memory window 0 end-address low-byte
Offset: CardBus Socket Address + 812h: Card A ExCA Offset 12h
Card B ExCA Offset 52h
Register: ExCA memory window 1 end-address low-byte
Offset: CardBus Socket Address + 81Ah: Card A ExCA Offset 1Ah
Card B ExCA Offset 5Ah
Register: ExCA memory window 2 end-address low-byte
Offset: CardBus Socket Address + 822h: Card A ExCA Offset 22h
Card B ExCA Offset 62h
Register: ExCA memory window 3 end-address low-byte
Offset: CardBus Socket Address + 82Ah: Card A ExCA Offset 2Ah
Card B ExCA Offset 6Ah
Register: ExCA memory window 4 end-address low-byte
Offset: CardBus Socket Address + 832h: Card A ExCA Offset 32h
Card B ExCA Offset 72h
Type: Read/Write
Default: 00h
5−18
5.16 ExCA Memory Windows 0−4 End-Address High-Byte Registers
These registers contain the high nibble of the 16-bit memory window end address for memory windows 0, 1, 2, 3,
and 4. The lower 4 bits of these registers correspond to bits A23−A20 of the end address. In addition, the memory
window wait states are set in this register. See Table 5−12 for a complete description of the register contents.
Bit 7 6 5 4 3 2 1 0
Name ExCA memory windows 0−4 end-address high-byte
Type RW RW R R RW RW RW RW
Default 0 0 0 0 0 0 0 0
Register: ExCA memory window 0 end-address high-byte
Offset: CardBus Socket Address + 813h: Card A ExCA Offset 13h
Card B ExCA Offset 53h
Register: ExCA memory window 1 end-address high-byte
Offset: CardBus Socket Address + 81Bh: Card A ExCA Offset 1Bh
Card B ExCA Offset 5Bh
Register: ExCA memory window 2 end-address high-byte
Offset: CardBus Socket Address + 823h: Card A ExCA Offset 23h
Card B ExCA Offset 63h
Register: ExCA memory window 3 end-address high-byte
Offset: CardBus Socket Address + 82Bh: Card A ExCA Offset 2Bh
Card B ExCA Offset 6Bh
Register: ExCA Memory window 4 end-address high-byte
Offset: CardBus Socket Address + 833h: Card A ExCA Offset 33h
Card B ExCA Offset 73h
Type: Read/Write, Read-only
Default: 00h
Table 5−12. ExCA Memory Windows 0−4 End-Address High-Byte Registers Description
BIT SIGNAL TYPE FUNCTION
7−6 MEMWS RW Wait state. These bits specify the number of equivalent ISA wait states to be added to 16-bit memory
accesses. The number of wait states added is equal to the binary value of these 2 bits.
5−4 RSVD R Reserved. These bits return 0s when read. Writes have no effect.
3−0 ENDHN RW End-address high nibble. These bits represent the upper address bits A23−A20 of the memory window end
address.
5−19
5.17 ExCA Memory Windows 0−4 Offset-Address Low-Byte Registers
These registers contain the low byte of the 16-bit memory window offset address for memory windows 0, 1, 2, 3,
and 4. The 8 bits of these registers correspond to bits A19−A12 of the offset address.
Bit 7 6 5 4 3 2 1 0
Name ExCA memory windows 0−4 offset-address low-byte
Type RW RW RW RW RW RW RW RW
Default 0 0 0 0 0 0 0 0
Register: ExCA memory window 0 offset-address low-byte
Offset: CardBus Socket Address + 814h: Card A ExCA Offset 14h
Card B ExCA Offset 54h
Register: ExCA memory window 1 offset-address low-byte
Offset: CardBus Socket Address + 81Ch: Card A ExCA Of fset 1Ch
Card B ExCA Offset 5Ch
Register: ExCA memory window 2 offset-address low-byte
Offset: CardBus Socket Address + 824h: Card A ExCA Offset 24h
Card B ExCA Offset 64h
Register: ExCA memory window 3 offset-address low-byte
Offset: CardBus Socket Address + 82Ch: Card A ExCA Of fset 2Ch
Card B ExCA Offset 6Ch
Register: ExCA memory window 4 offset-address low-byte
Offset: CardBus Socket Address + 834h: Card A ExCA Offset 34h
Card B ExCA Offset 74h
Type: Read/Write
Default: 00h
5−20
5.18 ExCA Memory Windows 0−4 Offset-Address High-Byte Registers
These registers contain the high 6 bits of the 16-bit memory window offset address for memory windows 0, 1, 2, 3,
and 4. The lower 6 bits of these registers correspond to bits A25−A20 of the offset address. In addition, the write
protection and common/attribute memory configurations are set in this register. See Table 5−13 for a complete
description of the register contents.
Bit 7 6 5 4 3 2 1 0
Name ExCA memory window 0−4 offset-address high-byte
Type RW RW RW RW RW RW RW RW
Default 0 0 0 0 0 0 0 0
Register: ExCA memory window 0 offset-address high-byte
Offset: CardBus Socket Address + 815h: Card A ExCA Offset 15h
Card B ExCA Offset 55h
Register: ExCA memory window 1 offset-address high-byte
Offset: CardBus Socket Address + 81Dh: Card A ExCA Of fset 1Dh
Card B ExCA Offset 5Dh
Register: ExCA memory window 2 offset-address high-byte
Offset: CardBus Socket Address + 825h: Card A ExCA Offset 25h
Card B ExCA Offset 65h
Register: ExCA memory window 3 offset-address high-byte
Offset: CardBus Socket Address + 82Dh: Card A ExCA Of fset 2Dh
Card B ExCA Offset 6Dh
Register: ExCA memory window 4 offset-address high-byte
Offset: CardBus Socket Address + 835h: Card A ExCA Offset 35h
Card B ExCA Offset 75h
Type: Read/Write
Default: 00h
Table 5−13. ExCA Memory Windows 0−4 Offset-Address High-Byte Registers Description
BIT SIGNAL TYPE FUNCTION
7 WINWP RW
Write protect. This bit specifies whether write operations to this memory window are enabled.
This bit is encoded as:
0 = Write operations are allowed (default).
1 = Write operations are not allowed.
6 REG RW
This bit specifies whether this memory window is mapped to card attribute or common memory.
This bit is encoded as:
0 = Memory window is mapped to common memory (default).
1 = Memory window is mapped to attribute memory.
5−0 OFFHB RW Offset-address high byte. These bits represent the upper address bits A25−A20 of the memory window offset
address.
5−21
5.19 ExCA Card Detect and General Control Register
This register controls how the ExCA registers for the socket respond to card removal. It also reports the status of the
VS1 and VS2 signals at the PC Card interface. Table 5−14 describes each bit in the ExCA card detect and general
control register.
Bit 7 6 5 4 3 2 1 0
Name ExCA card detect and general control
Type R R W RW R R RW R
Default X X 0 0 0 0 0 0
Register: ExCA card detect and general control
Offset: CardBus Socket Address + 816h: Card A ExCA Offset 16h
Card B ExCA Offset 56h
Type: Read-only, Write-only, Read/Write
Default: XX00 0000b
Table 5−14. ExCA Card Detect and General Control Register Description
BIT SIGNAL TYPE FUNCTION
7 † VS2STAT R
VS2. This bit reports the current state of the VS2 signal at the PC Card interface, and, therefore, does not
have a default value.
0 = VS2 is low.
1 = VS2 is high.
6 † VS1STAT R
VS1. This bit reports the current state of the VS1 signal at the PC Card interface, and, therefore, does not
have a default value.
0 = VS1 is low.
1 = VS1 is high.
5 SWCSC W
Software card detect interrupt. If card detect enable, bit 3 in the ExCA card status change interrupt
configuration register (ExCA offset 805h, see Section 5.6) is set, then writing a 1 to this bit causes a
card-detect card-status-change interrupt for the associated card socket.
If the card-detect enable bit is cleared to 0 in the ExCA card status-change interrupt configuration register
(ExCA offset 805h, see Section 5.6), then writing a 1 to the software card-detect interrupt bit has no effect.
This bit is write-only.
A read operation of this bit always returns 0. Writing a 1 to this bit also clears it. If bit 2 of the ExCA global
control register (ExCA offset 81Eh, see Section 5.20) is set and a 1 is written to clear bit 3 of the ExCA
card status change interrupt register, then this bit also is cleared.
4 CDRESUME RW
Card detect resume enable. If this bit is set to 1 and a card detect change has been detected on the CD1
and CD2 inputs, then the RI_OUT output goes from high to low. The RI_OUT remains low until the card
status change bit in the ExCA card status-change register (ExCA of fset 804h, see Section 5.5) is cleared.
If this bit is a 0, then the card detect resume functionality is disabled.
0 = Card detect resume disabled (default)
1 = Card detect resume enabled
3−2 RSVD R These bits return 0s when read. Writes have no effect.
1 REGCONFIG RW
Register configuration upon card removal. This bit controls how the ExCA registers for the socket react
to a card removal event. This bit is encoded as:
0 = No change to ExCA registers upon card removal (default)
1 = Reset ExCA registers upon card removal
0 RSVD R This bit returns 0 when read. A write has no effect.
†One or more bits in this register are cleared only by the assertion of GRST when PME is enabled. If PME is not enabled, then this bit is cleared
by the assertion of PRST or GRST.
5−22
5.20 ExCA Global Control Register
This register controls both PC Card sockets, and is not duplicated for each socket. The host interrupt mode bits in
this register are retained for 82365SL-DF compatibility. See Table 5−15 for a complete description of the register
contents.
Bit 7 6 5 4 3 2 1 0
Name ExCA global control
Type R R R RW RW RW RW RW
Default 0 0 0 0 0 0 0 0
Register: ExCA global control
Offset: CardBus Socket Address + 81Eh: Card A ExCA Offset 1Eh
Card B ExCA Offset 5Eh
Type: Read-only, Read/Write
Default: 00h
Table 5−15. ExCA Global Control Register Description
BIT SIGNAL TYPE FUNCTION
7−5 RSVD R These bits return 0s when read. Writes have no effect.
4 INTMODEB RW
Level/edge interrupt mode select, card B. This bit selects the signaling mode for the PCI6x21/PCI6x11 host
interrupt for card B interrupts. This bit is encoded as:
0 = Host interrupt is edge mode (default).
1 = Host interrupt is level mode.
3 INTMODEA RW
Level/edge interrupt mode select, card A. This bit selects the signaling mode for the PCI6x21/PCI6x11 host
interrupt for card A interrupts. This bit is encoded as:
0 = Host interrupt is edge-mode (default).
1 = Host interrupt is level-mode.
2 ‡ IFCMODE RW
Interrupt flag clear mode select. This bit selects the interrupt flag clear mechanism for the flags in the ExCA
card status change register. This bit is encoded as:
0 = Interrupt flags cleared by read of CSC register (default)
1 = Interrupt flags cleared by explicit writeback of 1
1 ‡ CSCMODE RW
Card status change level/edge mode select. This bit selects the signaling mode for the
PCI6x21/PCI6x11 host interrupt for card status changes. This bit is encoded as:
0 = Host interrupt is edge-mode (default).
1 = Host interrupt is level-mode.
0 ‡ PWRDWN RW
Power-down mode select. When this bit is set to 1, the PCI6x21/PCI6x11 controller is in power-down
mode. In power-down mode the PCI6x21/PCI6x11 card outputs are placed in a high-impedance state until
an active cycle is executed on the card interface. Following an active cycle the outputs are again placed
in a high-impedance state. The PCI6x21/PCI6x11 controller still receives functional interrupts and/or card
status change interrupts; however, an actual card access is required to wake up the interface. This bit is
encoded as:
0 = Power-down mode disabled (default)
1 = Power-down mode enabled
‡One or more bits in this register are cleared only by the assertion of GRST.
5−23
5.21 ExCA I/O Windows 0 and 1 Offset-Address Low-Byte Registers
These registers contain the low byte of the 16-bit I/O window offset address for I/O windows 0 and 1. The 8 bits of
these registers correspond to the lower 8 bits of the offset address, and bit 0 is always 0.
Bit 7 6 5 4 3 2 1 0
Name ExCA I/O windows 0 and 1 offset-address low-byte
Type RW RW RW RW RW RW RW R
Default 0 0 0 0 0 0 0 0
Register: ExCA I/O window 0 offset-address low-byte
Offset: CardBus Socket Address + 836h: Card A ExCA Offset 36h
Card B ExCA Offset 76h
Register: ExCA I/O window 1 offset-address low-byte
Offset: CardBus Socket Address + 838h: Card A ExCA Offset 38h
Card B ExCA Offset 78h
Type: Read/Write, Read-only
Default: 00h
5.22 ExCA I/O Windows 0 and 1 Offset-Address High-Byte Registers
These registers contain the high byte of the 16-bit I/O window offset address for I/O windows 0 and 1. The 8 bits of
these registers correspond to the upper 8 bits of the offset address.
Bit 7 6 5 4 3 2 1 0
Name ExCA I/O windows 0 and 1 offset-address high-byte
Type RW RW RW RW RW RW RW RW
Default 0 0 0 0 0 0 0 0
Register: ExCA I/O window 0 offset-address high-byte
Offset: CardBus Socket Address + 837h: Card A ExCA Offset 37h
Card B ExCA Offset 77h
Register: ExCA I/O window 1 offset-address high-byte
Offset: CardBus Socket Address + 839h: Card A ExCA Offset 39h
Card B ExCA Offset 79h
Type: Read/Write
Default: 00h
5−24
5.23 ExCA Memory Windows 0−4 Page Registers
The upper 8 bits of a 4-byte PCI memory address are compared to the contents of this register when decoding
addresses for 16-bit memory windows. Each window has its own page register, all of which default to 00h. By
programming this register to a nonzero value, host software can locate 16-bit memory windows in any one of 256
16-Mbyte regions in the 4-gigabyte PCI address space. These registers are only accessible when the ExCA registers
are memory-mapped, that is, these registers may not be accessed using the index/data I/O scheme.
Bit 7 6 5 4 3 2 1 0
Name ExCA memory windows 0−4 page
Type RW RW RW RW RW RW RW R
Default 0 0 0 0 0 0 0 0
Register: ExCA memory windows 0−4 page
Offset: CardBus Socket Address + 840h, 841h, 842h, 843h, 844h
Type: Read/Write
Default: 00h
6−1
6 CardBus Socket Registers (Functions 0 and 1)
The 1997 PC Card Standard requires a CardBus socket controller to provide five 32-bit registers that report and
control socket-specific functions. The PCI6x21/PCI6x11 controller provides the C ard Bu s s ock et /E xC A ba se ad dre ss
register (PCI offset 10h, see Section 4.12) to locate these CardBus socket registers in PCI memory address space.
Each function has a separate base address register for accessing the CardBus socket registers (see Figure 6−1).
Table 6−1 gives the location of the socket registers in relation to the CardBus socket/ExCA base address.
In addition to the five required registers, the PCI6x21/PCI6x11 controller implements a register at offset 20h that
provides power management control for the socket.
16-Bit Legacy-Mode Base Address
CardBus Socket/ExCA Base Address 10h
44h
CardBus
Socket A
Registers
ExCA
Registers
Card A
20h
800h
844h
Host
Memory Space
CardBus
Socket B
Registers
ExCA
Registers
Card B
20h
800h
844h
Host
Memory Space
Note: The CardBus socket/ExCA base
address mode register is separate for
functions 0 and 1.
address register’s base address.
Offsets are from the CardBus socket/ExCA base
00h
00h
PCI6x21/PCI6x11 Configuration Registers Offset
Offset
Offset
Figure 6−1. Accessing CardBus Socket Registers Through PCI Memory
Table 6−1. CardBus Socket Registers
REGISTER NAME OFFSET
Socket event † 00h
Socket mask † 04h
Socket present state † 08h
Socket force event 0Ch
Socket control † 10h
Reserved 14h−1Ch
Socket power management ‡ 20h
†One or more bits in the register are PME context bits and can be cleared only by the assertion of GRST when PME is enabled. If PME is not
enabled, then these bits are cleared by the assertion of PRST or GRST.
‡One or more bits in this register are cleared only by the assertion of GRST.
6−2
6.1 Socket Event Register
This register indicates a change in socket status has occurred. These bits do not indicate what the change is, only
that one has occurred. Software must read the socket present state register for current status. Each bit in this register
can be cleared by writing a 1 to that bit. The bits in this register can be set to a 1 by software through writing a 1 to
the corresponding bit in the socket force event register . All bits in this register are cleared by PCI reset. They can be
immediately set again, if, when coming out of PC Card reset, the bridge finds the status unchanged (i.e., CSTSCHG
reasserted or card detect is still true). Software needs to clear this register before enabling interrupts. If it is not cleared
and interrupts are enabled, then an unmasked interrupt is generated based on any bit that is set. See Table 6−2 for
a complete description of the register contents.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name Socket event
Type RRRRRRRRRRRRRRRR
Default 0000000000000000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Socket event
Type RRRRRRRRRRRRRWC RWC RWC RWC
Default 0000000000000000
Register: Socket event
Offset: CardBus Socket Address + 00h
Type: Read-only, Read/Write to Clear
Default: 0000 0000h
Table 6−2. Socket Event Register Description
BIT SIGNAL TYPE FUNCTION
31−4 RSVD R These bits return 0s when read.
3†PWREVENT RWC Power cycle. This bit is set when the PCI6x21/PCI6x11 controller detects that the PWRCYCLE bit in the
socket present state register (offset 08h, see Section 6.3) has changed. This bit is cleared by writing a 1.
2†CD2EVENT RWC CCD2. This bit is set when the PCI6x21/PCI6x1 1 controller detects that the CDETECT2 field in the socket
present state register (offset 08h, see Section 6.3) has changed. This bit is cleared by writing a 1.
1†CD1EVENT RWC CCD1. This bit is set when the PCI6x21/PCI6x1 1 controller detects that the CDETECT1 field in the socket
present state register (offset 08h, see Section 6.3) has changed. This bit is cleared by writing a 1.
0†CSTSEVENT RWC
CSTSCHG. This bit is set when the CARDSTS field in the socket present state register (offset 08h, see
Section 6.3) has changed state. For CardBus cards, this bit is set on the rising edge of the CSTSCHG
signal. For 16-bit PC Cards, this bit is set on both transitions of the CSTSCHG signal. This bit is reset by
writing a 1.
†This bit is cleared only by the assertion of GRST when PME is enabled. If PME is not enabled, then this bit is cleared by the assertion of PRST
or GRST.
6−3
6.2 Socket Mask Register
This register allows software to control the CardBus card events which generate a status change interrupt. The state
of these mask bits does not prevent the corresponding bits from reacting in the socket event register (offset 00h, see
Section 6.1). See Table 6−3 for a complete description of the register contents.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name Socket mask
Type RRRRRRRRRRRRRRRR
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Socket mask
Type RRRRRRRRRRRRRW RW RW RW
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Register: Socket mask
Offset: CardBus Socket Address + 04h
Type: Read-only, Read/Write
Default: 0000 0000h
Table 6−3. Socket Mask Register Description
BIT SIGNAL TYPE FUNCTION
31−4 RSVD R These bits return 0s when read.
3†PWRMASK RW
Power cycle. This bit masks the PWRCYCLE bit in the socket present state register (offset 08h, see
Section 6.3) from causing a status change interrupt.
0 = PWRCYCLE event does not cause a CSC interrupt (default).
1 = PWRCYCLE event causes a CSC interrupt.
2−1†CDMASK RW
Card detect mask. These bits mask the CDETECT1 and CDETECT2 bits in the socket present state
register (offset 08h, see Section 6.3) from causing a CSC interrupt.
00 = Insertion/removal does not cause a CSC interrupt (default).
01 = Reserved (undefined)
10 = Reserved (undefined)
11 = Insertion/removal causes a CSC interrupt.
0†CSTSMASK RW
CSTSCHG mask. This bit masks the CARDSTS field in the socket present state register (offset 08h, see
Section 6.3) from causing a CSC interrupt.
0 = CARDSTS event does not cause a CSC interrupt (default).
1 = CARDSTS event causes a CSC interrupt.
†This bit is cleared only by the assertion of GRST when PME is enabled. If PME is not enabled, then this bit is cleared by the assertion of PRST
or GRST.
6−4
6.3 Socket Present State Register
This register reports information about the socket interface. Writes to the socket force event register (of fset 0Ch, see
Section 6.4), as well as general socket interface status, are reflected here. Information about PC Card VCC support
and card type is only updated at each insertion. Also note that the PCI6x21/PCI6x11 controller uses the CCD1 and
CCD2 signals during card identification, and changes on these signals during this operation are not reflected in this
register.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name Socket present state
Type RRRRRRRRRRRRRRRR
Default 0011000000000000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Socket present state
Type RRRRRRRRRRRRRRRR
Default 0 0 0 0 0 0 0 0 0 X 0 0 0 X X X
Register: Socket present state
Offset: CardBus Socket Address + 08h
Type: Read-only
Default: 3000 00XXh
Table 6−4. Socket Present State Register Description
BIT SIGNAL TYPE FUNCTION
31 YVSOCKET R YV socket. This bit indicates whether or not the socket can supply VCC = Y.Y V to PC Cards. The
PCI6x21/PCI6x11 controller does not support Y.Y-V VCC; therefore, this bit is always reset unless
overridden by the socket force event register (offset 0Ch, see Section 6.4). This bit defaults to 0.
30 XVSOCKET R XV socket. This bit indicates whether or not the socket can supply VCC = X.X V to PC Cards. The
PCI6x21/PCI6x11 controller does not support X.X-V VCC; therefore, this bit is always reset unless
overridden by the socket force event register (offset 0Ch, see Section 6.4). This bit defaults to 0.
29 3VSOCKET R 3-V socket. This bit indicates whether or not the socket can supply VCC = 3.3 Vdc to PC Cards. The
PCI6x21/PCI6x11 controller does support 3.3-V V CC; therefore, this bit is always set unless overridden
by the socket force event register (offset 0Ch, see Section 6.4).
28 5VSOCKET R 5-V socket. This bit indicates whether or not the socket can supply VCC = 5 Vdc to PC Cards. The
PCI6x21/PCI6x11 controller does support 5-V VCC; therefore, this bit is always set unless overridden
by bit 6 of the device control register (PCI offset 92h, see Section 4.39).
27−14 RSVD R These bits return 0s when read.
13 † YVCARD R YV card. This bit indicates whether or not the PC Card inserted in the socket supports VCC = Y.Y Vdc.
This bit can be set by writing a 1 to the corresponding bit in the socket force event register (offset 0Ch,
see Section 6.4).
12 † XVCARD R XV card. This bit indicates whether or not the PC Card inserted in the socket supports VCC = X.X Vdc.
This bit can be set by writing a 1 to the corresponding bit in the socket force event register (of fset 0Ch,
see Section 6.4).
11 † 3VCARD R 3-V card. This bit indicates whether or not the PC Card inserted in the socket supports VCC = 3.3 Vdc.
This bit can be set by writing a 1 to the corresponding bit in the socket force event register (of fset 0Ch,
see Section 6.4).
10 † 5VCARD R 5-V card. This bit indicates whether or not the PC Card inserted in the socket supports VCC = 5 Vdc.
This bit can be set by writing a 1 to the corresponding bit in the socket force event register (of fset 0Ch,
see Section 6.4).
†One or more bits in the register are PME context bits and can be cleared only by the assertion of GRST when PME is enabled. If PME is not
enabled, then these bits are cleared by the assertion of PRST or GRST.
6−5
Table 6−4. Socket Present State Register Description (Continued)
BIT SIGNAL TYPE FUNCTION
9 † BADVCCREQ R
Bad VCC request. This bit indicates that the host software has requested that the socket be powered at
an invalid voltage.
0 = Normal operation (default)
1 = Invalid VCC request by host software
8 † DATALOST R
Data lost. This bit indicates that a PC Card removal event may have caused lost data because the cycle
did not terminate properly or because write data still resides in the PCI6x21/PCI6x11 controller.
0 = Normal operation (default)
1 = Potential data loss due to card removal
7 † NOTACARD R
Not a card. This bit indicates that an unrecognizable PC Card has been inserted in the socket. This bit is
not updated until a valid PC Card is inserted into the socket.
0 = Normal operation (default)
1 = Unrecognizable PC Card detected
6 IREQCINT R
READY(IREQ)//CINT. This bit indicates the current status of the READY(IREQ)//CINT signal at the PC
Card interface.
0 = READY(IREQ)//CINT is low.
1 = READY(IREQ)//CINT is high.
5 † CBCARD R CardBus card detected. This bit indicates that a CardBus PC Card is inserted in the socket. This bit is not
updated until another card interrogation sequence occurs (card insertion).
4 † 16BITCARD R 16-bit card detected. This bit indicates that a 16-bit PC Card is inserted in the socket. This bit is not
updated until another card interrogation sequence occurs (card insertion).
3 † PWRCYCLE R Power cycle. This bit indicates the status of each card powering request. This bit is encoded as:
0 = Socket is powered down (default).
1 = Socket is powered up.
2 † CDETECT2 R
CCD2. This bit reflects the current status of the CCD2 signal at the PC Card interface. Changes to this
signal during card interrogation are not reflected here.
0 = CCD2 is low (PC Card may be present)
1 = CCD2 is high (PC Card not present)
1 † CDETECT1 R
CCD1. This bit reflects the current status of the CCD1 signal at the PC Card interface. Changes to this
signal during card interrogation are not reflected here.
0 = CCD1 is low (PC Card may be present).
1 = CCD1 is high (PC Card not present).
0 CARDSTS R CSTSCHG. This bit reflects the current status of the CSTSCHG signal at the PC Card interface.
0 = CSTSCHG is low.
1 = CSTSCHG is high.
†One or more bits in the register are PME context bits and can be cleared only by the assertion of GRST when PME is enabled. If PME is not
enabled, then these bits are cleared by the assertion of PRST or GRST.
6.4 Socket Force Event Register
This register is used to force changes to the socket event register (of fset 00h, see Section 6.1) and the socket present
state register (offset 08h, see Section 6.3). The CVSTEST bit (bit 14) in this register must be written when forcing
changes that require card interrogation. See Table 6−5 for a complete description of the register contents.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name Socket force event
Type RRRRRRRRRRRRRRRR
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Socket force event
Type R W W W W W W W W R W W W W W W
Default XXXXXXXXXXXXXXXX
Register: Socket force event
Offset: CardBus Socket Address + 0Ch
Type: Read-only, Write-only
Default: 0000 XXXXh
6−6
Table 6−5. Socket Force Event Register Description
BIT SIGNAL TYPE FUNCTION
31−15 RSVD R Reserved. These bits return 0s when read.
14 CVSTEST W Card VS test. When this bit is set, the PCI6x21/PCI6x11 controller reinterrogates the PC Card, updates
the socket present state register (offset 08h, see Section 6.3), and re-enables the socket power control.
13 FYVCARD W Force YV card. W rites to this bit cause the YVCARD bit in the socket present state register (of fset 08h,
see Section 6.3) to be written. When set, this bit disables the socket power control.
12 FXVCARD W Force XV card. W rites to this bit cause the XVCARD bit in the socket present state register (of fset 08h,
see Section 6.3) to be written. When set, this bit disables the socket power control.
11 F3VCARD W Force 3-V card. W rites to this bit cause the 3VCARD bit in the socket present state register (offset 08h,
see Section 6.3) to be written. When set, this bit disables the socket power control.
10 F5VCARD W Force 5-V card. W rites to this bit cause the 5VCARD bit in the socket present state register (of fset 08h,
see Section 6.3) to be written. When set, this bit disables the socket power control.
9 FBADVCCREQ W Force BadVccReq. Changes to the BADVCCREQ bit in the socket present state register (offset 08h,
see Section 6.3) can be made by writing this bit.
8 FDATALOST W Force data lost. Writes to this bit cause the DATALOST bit in the socket present state register (offset
08h, see Section 6.3) to be written.
7 FNOTACARD W Force not a card. Writes to this bit cause the NOTACARD bit in the socket present state register (offset
08h, see Section 6.3) to be written.
6 RSVD R This bit returns 0 when read.
5 FCBCARD W Force CardBus card. W rites to this bit cause the CBCARD bit in the socket present state register (of fset
08h, see Section 6.3) to be written.
4 F16BITCARD W Force 16-bit card. Writes to this bit cause the 16BITCARD bit in the socket present state register (of fset
08h, see Section 6.3) to be written.
3 FPWRCYCLE W Force power cycle. W rites to this bit cause the PWREVENT bit in the socket event register (of fset 00h,
see Section 6.1) to be written, and the PWRCYCLE bit in the socket present state register (of fset 08h,
see Section 6.3) is unaffected.
2 FCDETECT2 W Force CCD2. Writes to this bit cause the CD2EVENT bit in the socket event register (offset 00h, see
Section 6.1) to be written, and the CDETECT2 bit in the socket present state register (of fset 08h, see
Section 6.3) is unaf fected.
1 FCDETECT1 W Force CCD1. Writes to this bit cause the CD1EVENT bit in the socket event register (offset 00h, see
Section 6.1) to be written, and the CDETECT1 bit in the socket present state register (of fset 08h, see
Section 6.3) is unaf fected.
0 FCARDSTS W Force CSTSCHG. W rites to this bit cause the CSTSEVENT bit in the socket event register (offset 00h,
see Section 6.1) to be written. The CARDSTS bit in the socket present state register (offset 08h, see
Section 6.3) is unaf fected.
6−7
6.5 Socket Control Register
This register provides control of the voltages applied to the socket VPP and VCC. The PCI6x21/PCI6x11 controller
ensures that the socket is powered up only at acceptable voltages when a CardBus card is inserted. See Table 6−6
for a complete description of the register contents.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name Socket control
Type RRRRRRRRRRRRRRRR
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Socket control
Type RRRRRRRW RRW RW RW RW RRW RW RW
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Register: Socket control
Offset: CardBus Socket Address + 10h
Type: Read-only, Read/Write
Default: 0000 0000h
Table 6−6. Socket Control Register Description
BIT SIGNAL TYPE FUNCTION
31−11 RSVD R These bits return 0s when read.
10 RSVD R This bit returns 1 when read.
9−8 RSVD R These bits return 0s when read.
7 STOPCLK RW
This bit controls how the CardBus clock run state machine decides when to stop the CardBus clock
to the CardBus card:
0 = The CardBus CLKRUN protocol can only attempt to stop/slow the CaredBus clock if the
sockethas been idle for 8 clocks and the PCI CLKRUN protocol is preparing to stop/slow the
PCI bus clock.
1 = The CardBus CLKRUN protocol can only attempt to stop/slow the CaredBus clock if the
socket has been idle for 8 clocks, regardless of the state of the PCI CLKRUN signal.
6−4 † VCCCTRL RW
VCC control. These bits are used to request card VCC changes.
000 = Request power off (default) 100 = Request VCC = X.X V
001 = Reserved 101 = Request VCC = Y.Y V
010 = Request VCC = 5 V 110 = Reserved
011 = Request VCC = 3.3 V 111 = Reserved
3 RSVD R This bit returns 0 when read.
2−0 † VPPCTRL RW
VPP control. These bits are used to request card VPP changes.
000 = Request power off (default) 100 = Request VPP = X.X V
001 = Request VPP = 12 V 101 = Request VPP = Y.Y V
010 = Request VPP = 5 V 110 = Reserved
011 = Request VPP = 3.3 V 111 = Reserved
†One or more bits in the register are PME context bits and can be cleared only by the assertion of GRST when PME is enabled. If PME is not
enabled, then this bit is cleared by the assertion of PRST or GRST.
6−8
6.6 Socket Power Management Register
This register provides power management control over the socket through a mechanism for slowing or stopping the
clock on the card interface when the card is idle. See Table 6−7 for a complete description of the register contents.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name Socket power management
Type RRRRRRRRRRRRRRRRW
Default 0000000000000000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Socket power management
Type RRRRRRRRRRRRRRRRW
Default 0000000000000000
Register: Socket power management
Offset: CardBus Socket Address + 20h
Type: Read-only, Read/Write
Default: 0000 0000h
Table 6−7. Socket Power Management Register Description
BIT SIGNAL TYPE FUNCTION
31−26 RSVD R Reserved. These bits return 0s when read.
25 ‡ SKTACCES R
Socket access status. This bit provides information on whether a socket access has occurred. This bit is
cleared by a read access.
0 = No PC Card access has occurred (default).
1 = PC Card has been accessed.
24 ‡ SKTMODE R Socket mode status. This bit provides clock mode information.
0 = Normal clock operation
1 = Clock frequency has changed.
23−17 RSVD R These bits return 0s when read.
16 CLKCTRLEN RW CardBus clock control enable. This bit, when set, enables clock control according to bit 0 (CLKCTRL).
0 = Clock control disabled (default)
1 = Clock control enabled
15−1 RSVD R These bits return 0s when read.
0 CLKCTRL RW
CardBus clock control. This bit determines whether the CardBus CLKRUN protocol attempts to stop or
slow the CardBus clock during idle states. The CLKCTRLEN bit enables this bit.
0 = Allows the CardBus CLKRUN protocol to attempt to stop the CardBus clock (default)
1 = Allows the CardBus CLKRUN protocol to attempt to slow the CardBus clock by a factor of 16
‡One or more bits in this register are cleared only by the assertion of GRST.
7−1
7 Flash Media Controller Programming Model
This section describes the internal PCI configuration registers used to program the PCI6x21/PCI6x11 flash media
controller interface. All registers are detailed in the same format: a brief description for each register is followed by
the register offset and a bit table describing the reset state for each register.
A bit description table, typically included when the register contains bits of more than one type or purpose, indicates
bit field names, a detailed field description, and field access tags which appear in the type column. Table 4−1
describes the field access tags.
The PCI6x21/PCI6x11 controller is a multifunction PCI device. The flash media controller core is integrated as PCI
function 3. The function 3 configuration header is compliant with the PCI Local Bus Specification as a standard
header. Table 7−1 illustrates the configuration header that includes both the predefined portion of the configuration
space and the user-definable registers.
Table 7−1. Function 3 Configuration Register Map
REGISTER NAME OFFSET
Device ID Vendor ID 00h
Status Command 04h
Class code Revision ID 08h
BIST Header type Latency timer Cache line size 0Ch
Flash media base address 10h
Reserved 14h−28h
Subsystem ID ‡ Subsystem vendor ID ‡ 2Ch
Reserved 30h
Reserved PCI power
management
capabilities pointer
34h
Reserved 38h
Maximum latency Minimum grant Interrupt pin Interrupt line 3Ch
Reserved 40h
Power management capabilities Next item pointer Capability ID 44h
PM data
(Reserved) PMCSR_BSE Power management control and status ‡ 48h
Reserved General control ‡ 4Ch
Subsystem access 50h
Diagnostic ‡ 54h
Reserved 58h−FCh
‡One or more bits in this register are cleared only by the assertion of GRST.
7−2
7.1 Vendor ID Register
The vendor ID register contains a value allocated by the PCI SIG and identifies the manufacturer of the PCI device.
The vendor ID assigned to Texas Instruments is 104Ch.
Bit 15 14 13 12 11 109876543210
Name Vendor ID
Type RRRRRRRRRRRRRRRR
Default 0001000001001100
Register: Vendor ID
Offset: 00h
Type: Read-only
Default: 104Ch
7.2 Device ID Register
The device ID register contains a value assigned to the flash media controller by Texas Instruments. The device
identification for the flash media controller is 8033h.
Bit 15 14 13 12 11 109876543210
Name Device ID
Type RRRRRRRRRRRRRRRR
Default 1000000000110011
Register: Device ID
Offset: 02h
Type: Read-only
Default: 8033h
7−3
7.3 Command Register
The command register provides control over the PCI6x21/PCI6x11 interface to the PCI bus. All bit functions adhere
to the definitions in the PCI Local Bus Specification, as seen in the following bit descriptions. See Table 7−2 for a
complete description of the register contents.
Bit 15 14 13 12 11 109876543210
Name Command
Type RRRRRRW RRW RRW RRW RRW RW R
Default 0000000000000000
Register: Command
Offset: 04h
Type: Read/Write, Read-only
Default: 0000h
Table 7−2. Command Register Description
BIT FIELD NAME TYPE DESCRIPTION
15−11 RSVD R Reserved. Bits 15−11 return 0s when read.
10 INT_DISABLE RW INTx disable. When set to 1, this bit disables the function from asserting interrupts on the INTx signals.
0 = INTx assertion is enabled (default)
1 = INTx assertion is disabled
9 FBB_ENB R Fast back-to-back enable. The flash media interface does not generate fast back-to-back transactions;
therefore, bit 9 returns 0 when read.
8 SERR_ENB RW SERR enable. When bit 8 is set to 1, the flash media interface SERR driver is enabled. SERR can be
asserted after detecting an address parity error on the PCI bus.
7 STEP_ENB R Address/data stepping control. The flash media interface does not support address/data stepping;
therefore, bit 7 is hardwired to 0.
6 PERR_ENB RW Parity error enable. When bit 6 is set to 1, the flash media interface is enabled to drive PERR response
to parity errors through the PERR signal.
5 VGA_ENB R VGA palette snoop enable. The flash media interface does not feature VGA palette snooping;
therefore, bit 5 returns 0 when read.
4 MWI_ENB RW Memory write and invalidate enable. The flash media controller does not generate memory write
invalidate transactions; therefore, bit 4 returns 0 when read.
3 SPECIAL R Special cycle enable. The flash media interface does not respond to special cycle transactions;
therefore, bit 3 returns 0 when read.
2 MASTER_ENB RW Bus master enable. When bit 2 is set to 1, the flash media interface is enabled to initiate cycles on the
PCI bus.
1 MEMORY_ENB RW Memory response enable. Setting bit 1 to 1 enables the flash media interface to respond to memory
cycles on the PCI bus.
0 IO_ENB R I/O space enable. The flash media interface does not implement any I/O-mapped functionality;
therefore, bit 0 returns 0 when read.
7−4
7.4 Status Register
The status register provides device information to the host system. All bit functions adhere to the definitions in the
PCI Local Bus Specification, as seen in the following bit descriptions. Bits in this register may be read normally. A
bit in the status register is reset when a 1 is written to that bit location; a 0 written to a bit location has no effect. See
Table 7−3 for a complete description of the register contents.
Bit 15 14 13 12 11 109876543210
Name Status
Type RCU RCU RCU RCU RCU R R RCU R R R R RU R R R
Default 0000001000010000
Register: Status
Offset: 06h
Type: Read/Clear/Update, Read-only
Default: 0210h
Table 7−3. Status Register Description
BIT FIELD NAME TYPE DESCRIPTION
15 PAR_ERR RCU Detected parity error. Bit 15 is set to 1 when either an address parity or data parity error is detected.
14 SYS_ERR RCU Signaled system error. Bit 14 is set to 1 when SERR is enabled and the flash media controller has
signaled a system error to the host.
13 MABORT RCU Received master abort. Bit 13 is set to 1 when a cycle initiated by the flash media controller on the PCI
bus has been terminated by a master abort.
12 TABORT_REC RCU Received target abort. Bit 12 is set to 1 when a cycle initiated by the flash media controller on the PCI
bus was terminated by a target abort.
11 TABORT_SIG RCU Signaled target abort. Bit 11 is set to 1 by the flash media controller when it terminates a transaction
on the PCI bus with a target abort.
10−9 PCI_SPEED R DEVSEL timing. Bits 10 and 9 encode the timing of DEVSEL and are hardwired to 01b, indicating that
the flash media controller asserts this signal at a medium speed on nonconfiguration cycle accesses.
8 DATAPAR RCU Data parity error detected. Bit 8 is set to 1 when the following conditions have been met:
a. PERR was asserted by any PCI device including the flash media controller.
b. The flash media controller was the bus master during the data parity error.
c. Bit 6 (PERR_EN) in the command register at offset 04h in the PCI configuration space
(see Section 7.3) is set to 1.
7 FBB_CAP R Fast back-to-back capable. The flash media controller cannot accept fast back-to-back transactions;
therefore, bit 7 is hardwired to 0.
6 UDF R User-definable features (UDF) supported. The flash media controller does not support the UDF;
therefore, bit 6 is hardwired to 0.
5 66MHZ R 66-MHz capable. The flash media controller operates at a maximum PCLK frequency of 33 MHz;
therefore, bit 5 is hardwired to 0.
4 CAPLIST R Capabilities list. Bit 4 returns 1 when read, indicating that the flash media controller supports additional
PCI capabilities.
3 INT_STATUS RU Interrupt status. This bit reflects the interrupt status of the function. Only when bit 10 (INT_DISABLE)
in the command register (see Section 7.3) is a 0 and this bit is 1, is the function’s INTx signal asserted.
Setting the INT_DISABLE bit to 1 has no effect on the state of this bit. This bit is set only when a valid
interrupt condition exists. This bit is not set when an interrupt condition exists and signaling of that event
is not enabled.
2−0 RSVD R Reserved. Bits 3−0 return 0s when read.
7−5
7.5 Class Code and Revision ID Register
The class code and revision ID register categorizes the base class, subclass, and programming interface of the
function. The base class is 01h, identifying the controller as a mass storage controller. The subclass is 80h, identifying
the function as other mass storage controller, and the programming interface is 00h. Furthermore, the TI chip revision
is indicated in the least significant byte (00h). See Table 7−4 for a complete description of the register contents.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name Class code and revision ID
Type RRRRRRRRRRRRRRRR
Default 0000000110000000
Bit 15 14 13 12 11 109876543210
Name Class code and revision ID
Type RRRRRRRRRRRRRRRR
Default 0000000000000000
Register: Class code and revision ID
Offset: 08h
Type: Read-only
Default: 0180 0000h
Table 7−4. Class Code and Revision ID Register Description
BIT FIELD NAME TYPE DESCRIPTION
31−24 BASECLASS R Base class. This field returns 01h when read, which classifies the function as a mass storage controller.
23−16 SUBCLASS R Subclass. This field returns 80h when read, which specifically classifies the function as other mass
storage controller.
15−8 PGMIF R Programming interface. This field returns 00h when read.
7−0 CHIPREV R Silicon revision. This field returns 00h when read, which indicates the silicon revision of the flash media
controller.
7.6 Latency Timer and Class Cache Line Size Register
The latency timer and class cache line size register is programmed by host BIOS to indicate system cache line size
and the latency timer associated with the flash media controller. See Table 7−5 for a complete description of the
register contents.
Bit 15 14 13 12 11 109876543210
Name Latency timer and class cache line size
Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Default 0000000000000000
Register: Latency timer and class cache line size
Offset: 0Ch
Type: Read/Write
Default: 0000h
Table 7−5. Latency Timer and Class Cache Line Size Register Description
BIT FIELD NAME TYPE DESCRIPTION
15−8 LATENCY_TIMER RW PCI latency timer. The value in this register specifies the latency timer for the flash media controller,
in units of PCI clock cycles. When the flash media controller is a PCI bus initiator and asserts FRAME,
the latency timer begins counting from zero. If the latency timer expires before the flash media
transaction has terminated, then the flash media controller terminates the transaction when its GNT
is deasserted.
7−0 CACHELINE_SZ RW Cache line size. This value is used by the flash media controller during memory write and invalidate,
memory-read line, and memory-read multiple transactions.
7−6
7.7 Header Type and BIST Register
The header type and built-in self-test (BIST) register indicates the flash media controller PCI header type and no
built-in self-test. See Table 7−6 for a complete description of the register contents.
Bit 15 14 13 12 11 109876543210
Name Header type and BIST
Type RRRRRRRRRRRRRRRR
Default 0000000010000000
Register: Header type and BIST
Offset: 0Eh
Type: Read-only
Default: 0010h
Table 7−6. Header Type and BIST Register Description
BIT FIELD NAME TYPE DESCRIPTION
15−8 BIST R Built-in self-test. The flash media controller does not include a BIST; therefore, this field returns 00h
when read.
7−0 HEADER_TYPE R PCI header type. The flash media controller includes the standard PCI header. Bit 7 indicates if the flash
media is a multifunction device.
7.8 Flash Media Base Address Register
The flash media base address register specifies the base address of the memory-mapped interface registers. Since
the implementation of the flash media controller core in the PCI6x21/PCI6x11 controller contains 2 sockets, the size
of the base address register is 8192 bytes. See Table 7−7 for a complete description of the register contents.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name Flash media base address
Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Default 0000000000000000
Bit 15 14 13 12 11 109876543210
Name Flash media base address
Type RW RW RW RW RW RRRRRRRRRRR
Default 0000000000000000
Register: Flash media base address
Offset: 10h
Type: Read/Write, Read-only
Default: 0000 0000h
Table 7−7. Flash Media Base Address Register Description
BIT FIELD NAME TYPE DESCRIPTION
31−12 BAR RW Base address. This field specifies the upper bits of the 32-bit starting base address.
11−4 RSVD R Reserved. Bits 11−4 return 0s when read to indicate that the size of the base address is 8192 bytes.
3 PREFETCHABLE R Prefetchable. Since this base address is not prefetchable, bit 3 returns 0 when read.
2−1 RSVD R Reserved. Bits 2−1 return 0s when read.
0 MEM_INDICATOR R Memory space indicator. Bit 0 is hardwired to 0 to indicate that the base address maps into memory
space.
7−7
7.9 Subsystem Vendor Identification Register
The subsystem identification register, used for system and option card identification purposes, may be required for
certain operating systems. This read-only register is initialized through the EEPROM and can be written through the
subsystem access register at PCI offset 50h (see Section 7.22). All bits in this register are reset by GRST only.
Bit 15 14 13 12 11 109876543210
Name Subsystem vendor identification
Type RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU
Default 0000000000000000
Register: Subsystem vendor identification
Offset: 2Ch
Type: Read/Update
Default: 0000h
7.10 Subsystem Identification Register
The subsystem identification register, used for system and option card identification purposes, may be required for
certain operating systems. This read-only register is initialized through the EEPROM and can be written through the
subsystem access register at PCI offset 50h (see Section 7.22). All bits in this register are reset by GRST only.
Bit 15 14 13 12 11 109876543210
Name Subsystem identification
Type RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU
Default 0000000000000000
Register: Subsystem identification
Offset: 2Eh
Type: Read/Update
Default: 0000h
7.11 Capabilities Pointer Register
The power management capabilities pointer register provides a pointer into the PCI configuration header where the
power-management register block resides. Since the PCI power management registers begin at 44h, this read-only
register is hardwired to 44h.
Bit 7 6 5 4 3 2 1 0
Name Capabilities pointer
Type R R R R R R R R
Default 0 1 0 0 0 1 0 0
Register: Capabilities pointer
Offset: 34h
Type: Read-only
Default: 44h
7−8
7.12 Interrupt Line Register
The interrupt line register is programmed by the system and indicates to the software which interrupt line the flash
media interface has assigned to it. The default value of this register is FFh, indicating that an interrupt line has not
yet been assigned to the function.
Bit 7 6 5 4 3 2 1 0
Name Interrupt line
Type RW RW RW RW RW RW RW RW
Default 11111111
Register: Interrupt line
Offset: 3Ch
Type: Read/Write
Default: FFh
7.13 Interrupt Pin Register
This register decodes the interrupt select inputs and returns the proper interrupt value based on Table 7−8, indicating
that the flash media interface uses an interrupt. If one of the USE_INTx terminals is asserted, the interrupt select bits
are ignored, and this register returns the interrupt value for the highest priority USE_INTx terminal that is asserted.
If bit 28, the tie-all bit (TIEALL), in the system control register (PCI offset 80h, see Section 4.29) is set to 1, then the
PCI6x21/PCI6x11 controller asserts the USE_INTA input to the flash media controller core. If bit 28 (TIEALL) in the
system control register (PCI of fset 80h, see Section 4.29) is set to 0, then none of the USE_INTx inputs are asserted
and the interrupt for the flash media function is selected by the INT_SEL bits in the flash media general control register .
Bit 7 6 5 4 3 2 1 0
Name Interrupt pin
Type RRRRRRRR
Default 0 0 0 0 0 X X X
Register: Interrupt pin
Offset: 3Dh
Type: Read-only
Default: 0Xh
Table 7−8. PCI Interrupt Pin Register
INT_SEL BITS USE_INTA INTPIN
00 0 01h (INTA)
01 0 02h (INTB)
10 0 03h (INTC)
11 004h (INTD)
XX 1 01h (INTA)
7−9
7.14 Minimum Grant Register
The minimum grant register contains the minimum grant value for the flash media controller core.
Bit 76543210
Name Minimum grant
Type RU RU RU RU RU RU RU RU
Default 00000111
Register: Minimum grant
Offset: 3Eh
Type: Read/Update
Default: 07h
Table 7−9. Minimum Grant Register Description
BIT FIELD NAME TYPE DESCRIPTION
7−0 MIN_GNT RU Minimum grant. The contents of this field may be used by host BIOS to assign a latency timer register value
to the flash media controller . The default for this register indicates that the flash media controller may need
to sustain burst transfers for nearly 64 µs and thus request a large value be programmed in bits 15−8 of
the PCI6x21/PCI6x11 latency timer and class cache line size register at offset 0Ch in the PCI configuration
space (see Section 7.6).
7.15 Maximum Latency Register
The maximum latency register contains the maximum latency value for the flash media controller core.
Bit 76543210
Name Maximum latency
Type RU RU RU RU RU RU RU RU
Default 00000100
Register: Maximum latency
Offset: 3Eh
Type: Read/Update
Default: 04h
Table 7−10. Maximum Latency Register Description
BIT FIELD NAME TYPE DESCRIPTION
7−0 MAX_LAT RU Maximum latency. The contents of this field may be used by host BIOS to assign an arbitration priority level
to the flash media controller . The default for this register indicates that the flash media controller may need
to access the PCI bus as often as every 0.25 µs; thus, an extremely high priority level is requested. The
contents of this field may also be loaded through the serial EEPROM.
7−10
7.16 Capability ID and Next Item Pointer Registers
The capability ID and next item pointer register identifies the linked-list capability item and provides a pointer to the
next capability item. See Table 7−11 for a complete description of the register contents.
Bit 15 14 13 12 11 109876543210
Name Capability ID and next item pointer
Type RRRRRRRRRRRRRRRR
Default 0000000000000001
Register: Capability ID and next item pointer
Offset: 44h
Type: Read-only
Default: 0001h
Table 7−11. Capability ID and Next Item Pointer Registers Description
BIT FIELD NAME TYPE DESCRIPTION
15−8 NEXT_ITEM R Next item pointer. The flash media controller supports only one additional capability, PCI power
management, that is communicated to the system through the extended capabilities list; therefore,
this field returns 00h when read.
7−0 CAPABILITY_ID R Capability identification. This field returns 01h when read, which is the unique ID assigned by the PCI
SIG for PCI power-management capability.
7−11
7.17 Power Management Capabilities Register
The power management capabilities register indicates the capabilities of the flash media controller related to PCI
power management. See Table 7−12 for a complete description of the register contents.
Bit 15 14 13 12 11 109876543210
Name Power management capabilities
Type RURRRRRRRRRRRRRRR
Default 0111111000000010
Register: Power management capabilities
Offset: 46h
Type: Read/Update, Read-only
Default: 7E02h
Table 7−12. Power Management Capabilities Register Description
BIT FIELD NAME TYPE DESCRIPTION
15 PME_D3COLD RU PME support from D3cold. This bit can be set to 1 or cleared to 0 via bit 4 (D3_COLD) in the general
control register at offset 4Ch in the PCI configuration space (see Section 7.21). When this bit is set to
1, it indicates that the controller is capable of generating a PME wake event from D3cold. This bit state
is dependent upon the PCI6x21/PCI6x11 VAUX implementation and may be configured by using bit 4
(D3_COLD) in the general control register (see Section 7.21).
14−11 PME_SUPPORT R PME support. This 4-bit field indicates the power states from which the flash media interface may
assert PME. This field returns a value of 11 11b by default, indicating that PME may be asserted from
the D3hot, D2, D1, and D0 power states.
10 D2_SUPPORT R D2 support. Bit 10 is hardwired to 1, indicating that the flash media controller supports the D2 power
state.
9 D1_SUPPORT R D1 support. Bit 9 is hardwired to 1, indicating that the flash media controller supports the D1 power
state.
8−6 AUX_CURRENT R Auxiliary current. This 3-bit field reports the 3.3-VAUX auxiliary current requirements. When bit 15
(PME_D3COLD) is cleared, this field returns 000b; otherwise, it returns 001b.
000b = Self-powered
001b = 55 mA (3.3-VAUX maximum current required)
5 DSI R Device-specific initialization. This bit returns 0 when read, indicating that the flash media controller
does not require special initialization beyond the standard PCI configuration header before a generic
class driver is able to use it.
4 RSVD R Reserved. Bit 4 returns 0 when read.
3 PME_CLK R PME clock. This bit returns 0 when read, indicating that the PCI clock is not required for the flash media
controller to generate PME.
2−0 PM_VERSION R Power-management version. This field returns 010b when read, indicating that the flash media
controller is compatible with the registers described in the PCI Bus Power Management Interface
Specification (Revision 1.1).
7−12
7.18 Power Management Control and Status Register
The power management control and status register implements the control and status of the flash media controller.
This register is not af fected by the internally generated reset caused by the transition from the D3hot to D0 state. See
Table 7−13 for a complete description of the register contents.
Bit 15 14 13 12 11 109876543210
Name Power management control and status
Type RCU R R R R R R RW R R R R R R RW RW
Default 0000000000000000
Register: Power management control and status
Offset: 48h
Type: Read/Clear, Read/Write, Read-only
Default: 0000h
Table 7−13. Power Management Control and Status Register Description
BIT FIELD NAME TYPE DESCRIPTION
15 ‡ PME_STAT RCU PME status. This bit defaults to 0.
14−13 DATA_SCALE R This field returns 0s, because the data register is not implemented.
12−9 DATA_SELECT R This field returns 0s, because the data register is not implemented.
8 ‡ PME_EN RW PME enable. Enables PME signaling. assertion is disabled.
7−2 RSVD R Reserved. Bits 7−2 return 0s when read.
1−0 ‡ PWR_STATE RW Power state. This 2-bit field determines the current power state and sets the flash media controller to
a new power state. This field is encoded as follows:
00 = Current power state is D0.
01 = Current power state is D1.
10 = Current power state is D2.
11 = Current power state is D3hot.
‡One or more bits in this register are cleared only by the assertion of GRST.
7.19 Power Management Bridge Support Extension Register
The power management bridge support extension register provides extended power-management features not
applicable to the flash media controller; thus, it is read-only and returns 0 when read.
Bit 7 6 5 4 3 2 1 0
Name Power management bridge support extension
Type RRRRRRRR
Default 00000000
Register: Power management bridge support extension
Offset: 4Ah
Type: Read-only
Default: 00h
7−13
7.20 Power Management Data Register
The power management bridge support extension register provides extended power-management features not
applicable to the flash media controller; thus, it is read-only and returns 0 when read.
Bit 76543210
Name Power management data
Type RRRRRRRR
Default 00000000
Register: Power management data
Offset: 4Bh
Type: Read-only
Default: 00h
7.21 General Control Register
The general control register provides miscellaneous PCI-related configuration. See Table 7−14 for a complete
description of the register contents.
Bit 76543210
Name General control
Type R R R RW RW RW RW RW
Default 00000000
Register: General control
Offset: 4Ch
Type: Read/Write, Read-only
Default: 00h
Table 7−14. General Control Register
BIT FIELD NAME TYPE DESCRIPTION
7 RSVD R Reserved. Bit 7 returns 0 when read.
6−5 ‡ INT_SEL RW Interrupt select. These bits are program the INTPIN register and set which interrupt output is used.
This field is ignored if one of the USE_INTx terminals is asserted.
00 = INTA
01 = INTB
10 = INTC
11 = INTD
4 ‡ D3_COLD RW D3cold PME support. This bit sets and clears the D3cold PME support bit in the power management
capabilities register.
3 RSVD R Reserved. Bit 3 returns 0 when read.
2 ‡ SM_DIS RW SmartMedia disable. Setting this bit disables support for SmartMedia cards. The flash media
controller reports a SmardMedia card as an unsupported card if this bit is set. If this bit is set, then
all of the SM_SUPPORT bits in the socket enumeration register are 0.
1 ‡ MMC_SD_DIS RW MMC/SD disable. Setting this bit disables support for MMC/SD cards. The flash media controller
reports a MMC/SD card as an unsupported card if this bit is set. If this bit is set, then all of the
SD_SUPPORT bits in the socket enumeration register are 0.
0 ‡ MS_DIS RW Memory Stick disable. Setting this bit disables support for Memory Stick cards. The flash media
controller reports a Memory Stick card as an unsupported card if this bit is set. If this bit is set, then
all of the MS_SUPPORT bits in the socket enumeration register are 0.
‡One or more bits in this register are cleared only by the assertion of GRST.
7−14
7.22 Subsystem Access Register
The contents of the subsystem access register are aliased to the subsystem vendor ID and subsystem ID registers
at PCI offsets 2Ch and 2Eh, respectively. See Table 7−15 for a complete description of the register contents.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name Subsystem access
Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Default 0000000000000000
Bit 15 14 13 12 11 109876543210
Name Subsystem access
Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Default 0000000000000000
Register: Subsystem access
Offset: 50h
Type: Read/Write
Default: 0000 0000h
Table 7−15. Subsystem Access Register Description
BIT FIELD NAME TYPE DESCRIPTION
31−16 SubsystemID RW Subsystem device ID. The value written to this field is aliased to the subsystem ID register at
PCI offset 2Eh.
15−0 SubsystemVendorID RW Subsystem vendor ID. The value written to this field is aliased to the subsystem vendor ID
register at PCI offset 2Ch.
7−15
7.23 Diagnostic Register
This register programs the M and N inputs to the PLL and enables the diagnostic modes. The default values for M
and N in this register set the PLL output to be 80 MHz, which is divided to get the 40 MHz and 20 MHz needed by
the flash media cores. See Table 7−16 for a complete description of the register contents. All bits in this register are
reset by GRST only.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name Diagnostic
Type RRRRRRRRRRRRRRRR/W
Default 0000000000000000
Bit 15 14 13 12 11 109876543210
Name Diagnostic
Type R R R R R R R R/W R R R RW RW RW RW RW
Default 0000001100000101
Register: Diagnostic
Type: Read-only, Read/Write
Offset: 54h
Default: 0000 0305h
Table 7−16. Diagnostic Register Description
BIT SIGNAL TYPE FUNCTION
31−17 TBD_CTRL R PLL control bits. These bits are reserved for PLL control and test bits.
16 DIAGNOSTIC RW Diagnostic test bit. This test bit shortens the PLL clock CLK_VALID time and shortens the card detect
debounce times for simulation and TDL.
15−11 RSVD R Reserved. Bits 15−11 return 0s when read.
10−8 PLL_N RW PLL_N input. The default value of this field is 03h.
7−5 RSVD R Reserved. Bits 7−5 return 0s when read.
4−0 PLL_M RW PLL_M input. The default value of this field is 05h.
7−16
8−1
8 SD Host Controller Programming Model
This section describes the internal PCI configuration registers used to program the PCI6x21/PCI6x11 SD host
controller interface. All registers are detailed in the same format: a brief description for each register is followed by
the register offset and a bit table describing the reset state for each register.
A bit description table, typically included when the register contains bits of more than one type or purpose, indicates
bit field names, a detailed field description, and field access tags which appear in the type column. Table 4−1
describes the field access tags.
The PCI6x21/PCI6x11 controller is a multifunction PCI device. The SD host controller core is integrated as PCI
function 4. The function 4 configuration header is compliant with the PCI Local Bus Specification as a standard
header. Table 8−1 illustrates the configuration header that includes both the predefined portion of the configuration
space and the user-definable registers.
Table 8−1. Function 4 Configuration Register Map
REGISTER NAME OFFSET
Device ID Vendor ID 00h
Status Command 04h
Class code Revision ID 08h
BIST Header type Latency timer Cache line size 0Ch
Slot 0 base address 10h
Slot 1 base address 14h
Slot 2 base address 18h
Reserved 1Ch−28h
Subsystem ID ‡ Subsystem vendor ID ‡ 2Ch
Reserved 30h
Reserved PCI power
management
capabilities pointer 34h
Reserved 38h
Maximum latency Minimum grant Interrupt pin Interrupt line 3Ch
Reserved Slot information 40h
Reserved 44h−7Ch
Power management capabilities Next item pointer Capability ID 80h
PM data
(Reserved) PMCSR_BSE Power management control and status ‡ 84h
Reserved General control ‡ 88h
Subsystem alias 8Ch
Diagnostic ‡ 90h
Reserved Slot 0 3.3-V
maximum current 94h
Reserved Slot 1 3.3-V
maximum current 98h
Reserved Slot 2 3.3-V
maximum current 9Ch
Reserved A0h−FCh
‡One or more bits in this register are cleared only by the assertion of GRST.
8−2
8.1 Vendor ID Register
The vendor ID register contains a value allocated by the PCI SIG and identifies the manufacturer of the PCI device.
The vendor ID assigned to Texas Instruments is 104Ch.
Bit 15 14 13 12 11 109876543210
Name Vendor ID
Type RRRRRRRRRRRRRRRR
Default 0001000001001100
Register: Vendor ID
Offset: 00h
Type: Read-only
Default: 104Ch
8.2 Device ID Register
The device ID register contains a value assigned to the SD host controller by Texas Instruments. The device
identification for the SD host controller is 8034h.
Bit 15 14 13 12 11 109876543210
Name Device ID
Type RRRRRRRRRRRRRRRR
Default 1000000000110100
Register: Device ID
Offset: 02h
Type: Read-only
Default: 8034h
8−3
8.3 Command Register
The command register provides control over the SD host controller interface to the PCI bus. All bit functions adhere
to the definitions in the PCI Local Bus Specification, as seen in the following bit descriptions. See Table 8−2 for a
complete description of the register contents.
Bit 15 14 13 12 11 109876543210
Name Command
Type RRRRRRW RRW RRW RRW RRW RW R
Default 0000000000000000
Register: Command
Offset: 04h
Type: Read/Write, Read-only
Default: 0000h
Table 8−2. Command Register Description
BIT FIELD NAME TYPE DESCRIPTION
15−11 RSVD R Reserved. Bits 15−11 return 0s when read.
10 INT_DISABLE RW INTx disable. When set to 1, this bit disables the function from asserting interrupts on the INTx signals.
0 = INTx assertion is enabled (default)
1 = INTx assertion is disabled
9 FBB_ENB R Fast back-to-back enable. The SD host controller does not generate fast back-to-back transactions;
therefore, bit 9 returns 0 when read.
8 SERR_ENB RW SERR enable. When bit 8 is set to 1, the SD host controller SERR driver is enabled. SERR can be
asserted after detecting an address parity error on the PCI bus.
7 STEP_ENB R Address/data stepping control. The SD host controller does not support address/data stepping;
therefore, bit 7 is hardwired to 0.
6 PERR_ENB RW Parity error enable. When bit 6 is set to 1, the SD host controller is enabled to drive PERR response
to parity errors through the PERR signal.
5 VGA_ENB R VGA palette snoop enable. The SD host controller does not feature VGA palette snooping; therefore,
bit 5 returns 0 when read.
4 MWI_ENB RW Memory write and invalidate enable. The SD host controller does not generate memory write invalidate
transactions; therefore, bit 4 returns 0 when read.
3 SPECIAL R Special cycle enable. The SD host controller does not respond to special cycle transactions; therefore,
bit 3 returns 0 when read.
2 MASTER_ENB RW Bus master enable. When bit 2 is set to 1, the SD host controller is enabled to initiate cycles on the
PCI bus.
1 MEMORY_ENB RW Memory response enable. Setting bit 1 to 1 enables the SD host controller to respond to memory cycles
on the PCI bus.
0 IO_ENB R I/O space enable. The SD host controller does not implement any I/O-mapped functionality; therefore,
bit 0 returns 0 when read.
8−4
8.4 Status Register
The status register provides device information to the host system. All bit functions adhere to the definitions in the
PCI Local Bus Specification, as seen in the following bit descriptions. Bits in this register may be read normally. A
bit in the status register is reset when a 1 is written to that bit location; a 0 written to a bit location has no effect. See
Table 8−3 for a complete description of the register contents.
Bit 15 14 13 12 11 109876543210
Name Status
Type RCU RCU RCU RCU RCU R R RCU R R R R RU R R R
Default 0000001000010000
Register: Status
Offset: 06h
Type: Read/Clear/Update, Read-only
Default: 0210h
Table 8−3. Status Register Description
BIT FIELD NAME TYPE DESCRIPTION
15 PAR_ERR RCU Detected parity error. Bit 15 is set to 1 when either an address parity or data parity error is detected.
14 SYS_ERR RCU Signaled system error. Bit 14 is set to 1 when SERR is enabled and the SD host controller has signaled
a system error to the host.
13 MABORT RCU Received master abort. Bit 13 is set to 1 when a cycle initiated by the SD host controller on the PCI
bus has been terminated by a master abort.
12 TABORT_REC RCU Received target abort. Bit 12 is set to 1 when a cycle initiated by the SD host controller on the PCI bus
was terminated by a target abort.
11 TABORT_SIG RCU Signaled target abort. Bit 11 is set to 1 by the SD host controller when it terminates a transaction on
the PCI bus with a target abort.
10−9 PCI_SPEED R DEVSEL timing. Bits 10 and 9 encode the timing of DEVSEL and are hardwired to 01b, indicating that
the SD host controller asserts this signal at a medium speed on nonconfiguration cycle accesses.
8 DATAPAR RCU Data parity error detected. Bit 8 is set to 1 when the following conditions have been met:
a. PERR was asserted by any PCI device including the SD host controller.
b. The SD host controller was the bus master during the data parity error.
c. Bit 6 (PERR_EN) in the command register at offset 04h in the PCI configuration space
(see Section 8.3) is set to 1.
7 FBB_CAP R Fast back-to-back capable. The SD host controller cannot accept fast back-to-back transactions;
therefore, bit 7 is hardwired to 0.
6 UDF R User-definable features (UDF) supported. The SD host controller does not support the UDF; therefore,
bit 6 is hardwired to 0.
5 66MHZ R 66-MHz capable. The SD host controller operates at a maximum PCLK frequency of 33 MHz;
therefore, bit 5 is hardwired to 0.
4 CAPLIST R Capabilities list. Bit 4 returns 1 when read, indicating that the SD host controller supports additional
PCI capabilities.
3 INT_STATUS RU Interrupt status. This bit reflects the interrupt status of the function. Only when bit 10 (INT_DISABLE)
in the command register (see Section 8.3) is a 0 and this bit is 1, is the function’s INTx signal asserted.
Setting the INT_DISABLE bit to 1 has no effect on the state of this bit. This bit is set only when a valid
interrupt condition exists. This bit is not set when an interrupt condition exists and signaling of that event
is not enabled.
2−0 RSVD R Reserved. Bits 3−0 return 0s when read.
8−5
8.5 Class Code and Revision ID Register
The class code and revision ID register categorizes the base class, subclass, and programming interface of the
function. The base class is 08h, identifying the controller as a generic system peripheral. The subclass is 05h,
identifying the function as an SD host controller. The programming interface is 01h, indicating that the function is a
standard SD host with DMA capabilities. Furthermore, the TI chip revision is indicated in the least significant byte
(00h). See Table 8−4 for a complete description of the register contents.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name Class code and revision ID
Type RRRRRRRRRRRRRRRR
Default 0000100000000101
Bit 15 14 13 12 11 109876543210
Name Class code and revision ID
Type RRRRRRRRRRRRRRRR
Default 0 0 0 0 0 0 0 X X X X X X X X X
Register: Class code and revision ID
Offset: 08h
Type: Read-only
Default: 0805 0XXXh
Table 8−4. Class Code and Revision ID Register Description
BIT FIELD NAME TYPE DESCRIPTION
31−24 BASECLASS R Base class. This field returns 08h when read, which broadly classifies the function as a generic system
peripheral.
23−16 SUBCLASS R Subclass. This field returns 05h when read, which specifically classifies the function as an SD host
controller.
15−8 PGMIF R Programming interface. If bit 0 (DMA_EN) in the general control register is 0, then this field returns 00 h
when re a d t o i n d i c a t e t h a t t h e f u n c t i o n i s a standard SD host without DMA capabilities. If the DMA_EN
bit is 1, then this field returns 01h when read to indicate that the function is a standard SD host with
DMA capabilities.
7−0 CHIPREV R Silicon revision. This field returns the silicon revision of the SD host controller .
8−6
8.6 Latency Timer and Class Cache Line Size Register
The latency timer and class cache line size register is programmed by host BIOS to indicate system cache line size
and the latency timer associated with the SD host controller. See Table 8−5 for a complete description of the register
contents.
Bit 15 14 13 12 11 109876543210
Name Latency timer and class cache line size
Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Default 0000000000000000
Register: Latency timer and class cache line size
Offset: 0Ch
Type: Read/Write
Default: 0000h
Table 8−5. Latency Timer and Class Cache Line Size Register Description
BIT FIELD NAME TYPE DESCRIPTION
15−8 LATENCY_TIMER RW PCI latency timer . The value in this register specifies the latency timer for the SD host controller, in units
of PCI clock cycles. When the SD host controller is a PCI bus initiator and asserts FRAME, the latency
timer begins counting from zero. If the latency timer expires before the SD host transaction has
terminated, then the SD host controller terminates the transaction when its GNT is deasserted.
7−0 CACHELINE_SZ RW Cache line size. This value is used by the SD host controller during memory write and invalidate,
memory-read line, and memory-read multiple transactions.
8.7 Header Type and BIST Register
The header type and built-in self-test (BIST) register indicates the SD host controller PCI header type and no built-in
self-test. See Table 8−6 for a complete description of the register contents.
Bit 15 14 13 12 11 109876543210
Name Header type and BIST
Type RRRRRRRRRRRRRRRR
Default 00000000x0000000
Register: Header type and BIST
Offset: 0Eh
Type: Read-only
Default: 00x0h
Table 8−6. Header Type and BIST Register Description
BIT FIELD NAME TYPE DESCRIPTION
15−8 BIST R Built-in self-test. The SD host controller does not include a BIST; therefore, this field returns 00h when
read.
7−0 HEADER_TYPE R PCI header type. The SD host controller includes the standard PCI header. Bit 7 indicates if the SD host
is a multifunction device.
8−7
8.8 SD Host Base Address Register
The SD host base address register specifies the base address of the memory-mapped interface registers for each
standard SD host socket. The size of each base address register (BAR) is 256 bytes. The number of BARs is
dependent on the number of SD sockets in the implementation See Table 8−7 for a complete description of the
register contents.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name SD host base address
Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Default 0000000000000000
Bit 15 14 13 12 11 109876543210
Name SD host base address
Type RW RW RW RW RW RRRRRRRRRRR
Default 0000000000000000
Register: SD host base address
Offset: 10h
Type: Read/Write, Read-only
Default: 0000 0000h
Table 8−7. SD host Base Address Register Description
BIT FIELD NAME TYPE DESCRIPTION
31−8 BAR RW Base address. This field specifies the upper 24 bits of the 32-bit starting base address. The size of
the base address is 256 bytes.
7−4 RSVD R Reserved. Bits 7−4 return 0s when read.
3 PREFETCHABLE R Prefetchable indicator. This bit is hardwired to 0 to indicate that the memory space is not prefetchable.
2−1 TYPE R This field is hardwired to 00 to indicate that the base address is located in 32-bit address space.
0 MEM_INDICATOR R Memory space indicator. Bit 0 is hardwired to 0 to indicate that the base address maps into memory
space.
8.9 Subsystem Vendor Identification Register
The subsystem identification register, used for system and option card identification purposes, may be required for
certain operating systems. This read-only register is initialized through the EEPROM and can be written through the
subsystem access register at PCI offset 8Ch (see Section 8.23). All bits in this register are reset by GRST only.
Bit 15 14 13 12 11 109876543210
Name Subsystem vendor identification
Type RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU
Default 0000000000000000
Register: Subsystem vendor identification
Offset: 2Ch
Type: Read/Update
Default: 0000h
8−8
8.10 Subsystem Identification Register
The subsystem identification register, used for system and option card identification purposes, may be required for
certain operating systems. This read-only register is initialized through the EEPROM and can be written through the
subsystem access register at PCI offset 8Ch (see Section 8.23). All bits in this register are reset by GRST only.
Bit 15 14 13 12 11 109876543210
Name Subsystem identification
Type RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU
Default 0000000000000000
Register: Subsystem identification
Offset: 2Eh
Type: Read/Update
Default: 0000h
8.11 Capabilities Pointer Register
The power management capabilities pointer register provides a pointer into the PCI configuration header where the
power-management register block resides. Since the PCI power management registers begin at 80h, this read-only
register is hardwired to 80h.
Bit 7 6 5 4 3 2 1 0
Name Capabilities pointer
Type R R R R R R R R
Default 1 0 0 0 0 0 0 0
Register: Capabilities pointer
Offset: 34h
Type: Read-only
Default: 80h
8.12 Interrupt Line Register
The interrupt line register is programmed by the system and indicates to the software which interrupt line the SD host
controller has assigned to it. The default value of this register is FFh, indicating that an interrupt line has not yet been
assigned to the function.
Bit 7 6 5 4 3 2 1 0
Name Interrupt line
Type RW RW RW RW RW RW RW RW
Default 11111111
Register: Interrupt line
Offset: 3Ch
Type: Read/Write
Default: FFh
8−9
8.13 Interrupt Pin Register
This register decodes the interrupt select inputs and returns the proper interrupt value based on Table 8−8, indicating
that the SD host controller uses an interrupt. If one of the USE_INTx terminals is asserted, the interrupt select bits
are ignored, and this register returns the interrupt value for the highest priority USE_INTx terminal that is asserted.
If bit 28, the tie-all bit (TIEALL), in the system control register (PCI offset 80h, see Section 4.29) is set to 1, then the
PCI6x21/PCI6x11 controller asserts the USE_INTA input to the SD host controller core. If bit 28 (TIEALL) in the
system control register (PCI of fset 80h, see Section 4.29) is set to 0, then none of the USE_INTx inputs are asserted
and the interrupt for the SD host controller function is selected by the INT_SEL bits in the SD host general control
register.
Bit 7 6 5 4 3 2 1 0
Name Interrupt pin
Type R R R R R R R R
Default 0 0 0 0 0 X X X
Register: Interrupt pin
Offset: 3Dh
Type: Read-only
Default: 0Xh
Table 8−8. PCI Interrupt Pin Register
INT_SEL BITS USE_INTA INTPIN
00 0 01h (INTA)
01 0 02h (INTB)
10 0 03h (INTC)
11 004h (INTD)
XX 1 01h (INTA)
8.14 Minimum Grant Register
The minimum grant register contains the minimum grant value for the SD host controller core.
Bit 76543210
Name Minimum grant
Type RU RU RU RU RU RU RU RU
Default 00000111
Register: Minimum grant
Offset: 3Eh
Type: Read/Update
Default: 07h
Table 8−9. Minimum Grant Register Description
BIT FIELD NAME TYPE DESCRIPTION
7−0 MIN_GNT RU Minimum grant. The contents of this field may be used by host BIOS to assign a latency timer register value
to the SD host controller. The default for this register indicates that the SD host controller may need to
sustain burst transfers for nearly 64 µs and thus request a large value be programmed in bits 15−8 of the
PCI6x21/PCI6x11 latency timer and class cache line size register at offset 0Ch in the PCI configuration
space (see Section 8.6).
8−10
8.15 Maximum Latency Register
The maximum latency register contains the maximum latency value for the SD host controller core.
Bit 7 6 5 4 3 2 1 0
Name Maximum latency
Type RU RU RU RU RU RU RU RU
Default 00000100
Register: Maximum latency
Offset: 3Fh
Type: Read/Update
Default: 04h
Table 8−10. Maximum Latency Register Description
BIT FIELD NAME TYPE DESCRIPTION
7−0 MAX_LAT RU Maximum latency. The contents of this field may be used by host BIOS to assign an arbitration priority level
to the SD host controller. The default for this register indicates that the SD host controller may need to
access the PCI bus as often as every 0.25 µs; thus, an extremely high priority level is requested. The
contents of this field may also be loaded through the serial EEPROM.
8.16 Slot Information Register
This read-only register contains information on the number of SD sockets implemented and the base address
Registers used.
Bit 7 6 5 4 3 2 1 0
Name Slot information
Type RRRRRRRR
Default 0 X X X 0 0 0 0
Register: Maximum latency
Offset: 40h
Type: Read/Update
Default: X0h
Table 8−11. Maximum Latency Register Description
BIT FIELD NAME TYPE DESCRIPTION
7 RSVD R Reserved. This bit returns 0 when read.
6−4 NUMBER_SLOTS R Number of slots. This field indicates the number of SD sockets supported by the SD host controller.
Since the controller supports three SD sockets, this field returns 010 when read.
3 RSVD R Reserved. This bit returns 0 when read.
2−0 FIRST_BAR R First base address register number . This field is hardwired to 000b to indicate that the first BAR used
for the SD host standard registers is BAR0.
8−11
8.17 Capability ID and Next Item Pointer Registers
The capability ID and next item pointer register identifies the linked-list capability item and provides a pointer to the
next capability item. See Table 8−12 for a complete description of the register contents.
Bit 15 14 13 12 11 109876543210
Name Capability ID and next item pointer
Type RRRRRRRRRRRRRRRR
Default 0000000000000001
Register: Capability ID and next item pointer
Offset: 80h
Type: Read-only
Default: 0001h
Table 8−12. Capability ID and Next Item Pointer Registers Description
BIT FIELD NAME TYPE DESCRIPTION
15−8 NEXT_ITEM R Next item pointer. The SD host controller supports only one additional capability, PCI power
management, that is communicated to the system through the extended capabilities list; therefore,
this field returns 00h when read.
7−0 CAPABILITY_ID R Capability identification. This field returns 01h when read, which is the unique ID assigned by the PCI
SIG for PCI power-management capability.
8−12
8.18 Power Management Capabilities Register
The power management capabilities register indicates the capabilities of the SD host controller related to PCI power
management. See Table 8−13 for a complete description of the register contents.
Bit 15 14 13 12 11 109876543210
Name Power management capabilities
Type RURRRRRRRRRRRRRRR
Default 0111111000000010
Register: Power management capabilities
Offset: 82h
Type: Read/Update, Read-only
Default: 7E02h
Table 8−13. Power Management Capabilities Register Description
BIT FIELD NAME TYPE DESCRIPTION
15 PME_D3COLD RU PME support from D3cold. This bit can be set to 1 or cleared to 0 via bit 4 (D3_COLD) in the general
control register at of fset 88h in the PCI configuration space (see Section 8.22). When this bit is set to
1, it indicates that the SD host controller is capable of generating a PME wake event from D3cold. This
bit state is dependent upon the SD host controller VAUX implementation and may be configured by
using bit 4 (D3_COLD) in the general control register (see Section 8.22).
14−11 PME_SUPPORT R PME support. This 4-bit field indicates the power states from which the SD host controller may assert
PME. This field returns a value of 1111b by default, indicating that PME may be asserted from
the D3hot, D2, D1, and D0 power states.
10 D2_SUPPORT R D2 support. Bit 10 is hardwired to 1, indicating that the SD host controller supports the D2 power state.
9 D1_SUPPORT R D1 support. Bit 9 is hardwired to 1, indicating that the SD host controller supports the D1 power state.
8−6 AUX_CURRENT R 3.3-VAUX auxiliary current requirements. This requirement is design dependent.
5 DSI R Device-specific initialization. This bit returns 0 when read, indicating that the SD host controller does
not require special initialization beyond the standard PCI configuration header before a generic class
driver is able to use it.
4 RSVD R Reserved. Bit 4 returns 0 when read.
3 PME_CLK R PME clock. This bit returns 0 when read, indicating that the PCI clock is not required for the SD host
controller to generate PME.
2−0 PM_VERSION R Power-management version. This field returns 010b when read, indicating that the SD host controller
is compatible with the registers described in the PCI Bus Power Management Interface Specification
(Revision 1.1).
8−13
8.19 Power Management Control and Status Register
The power management control and status register implements the control and status of the SD host controller. This
register is not affected by the internally generated reset caused by the transition from the D3hot to D0 state. See
Table 8−14 for a complete description of the register contents.
Bit 15 14 13 12 11 109876543210
Name Power management control and status
Type RCU R R R R R R RW RRRRRRRW RW
Default 0000000000000000
Register: Power management control and status
Offset: 84h
Type: Read/Clear, Read/Write, Read-only
Default: 0000h
Table 8−14. Power Management Control and Status Register Description
BIT FIELD NAME TYPE DESCRIPTION
15 ‡ PME_STAT RCU PME status. This bit defaults to 0.
14−13 DATA_SCALE R Data scale. This field returns 0s when read, because the SD host controller does not use the data
register.
12−9 DATA_SELECT R Data select. This field returns 0s when read, because the SD host controller does not use the data
register.
8 ‡ PME_EN RW PME enable. Enables PME signaling.
7−2 RSVD R Reserved. Bits 7−2 return 0s when read.
1−0 ‡ PWR_STATE RW Power state. This 2-bit field determines the current power state and sets the SD host controller to a
new power state. This field is encoded as follows:
00 = Current power state is D0.
01 = Current power state is D1.
10 = Current power state is D2.
11 = Current power state is D3hot.
‡One or more bits in this register are cleared only by the assertion of GRST.
8.20 Power Management Bridge Support Extension Register
The power management bridge support extension register provides extended power-management features not
applicable to the SD host controller; thus, it is read-only and returns 00h when read.
Bit 76543210
Name Power management bridge support extension
Type RRRRRRRR
Default 00000000
Register: Power management bridge support extension
Offset: 86h
Type: Read-only
Default: 00h
8−14
8.21 Power Management Data Register
The power management bridge support extension register provides extended power-management features not
applicable to the SD host controller; thus, it is read-only and returns 0 when read.
Bit 7 6 5 4 3 2 1 0
Name Power management data
Type RRRRRRRR
Default 00000000
Register: Power management data
Offset: 87h
Type: Read-only
Default: 00h
8.22 General Control Register
The general control register provides miscellaneous PCI-related configuration. See Table 8−15 for a complete
description of the register contents.
Bit 7 6 5 4 3 2 1 0
Name General control
Type RRW RW RW RW RW RW RW
Default 00000000
Register: General control
Offset: 88h
Type: Read/Write, Read-only
Default: 00h
Table 8−15. General Control Register
BIT FIELD NAME TYPE DESCRIPTION
7 RSVD R Reserved. Bit 7 returns 0 when read.
6−5 ‡ INT_SEL RW Interrupt select. These bits are program the INTPIN register and set which interrupt output is used.
This field is ignored if one of the USE_INTx terminals is asserted.
00 = INTA
01 = INTB
10 = INTC
11 = INTD
4 ‡ D3_COLD RW D3cold PME support. This bit sets and clears the D3cold PME support bit in the power management
capabilities register.
3−1 RSVD R Reserved. Bits 3−1 return 0s when read.
0 ‡ DMA_EN RW DMA enable. This bit enables DMA functionality of the SD host controller core. When this bit is set,
the PGMIF field in the class code register returns 01h and the DMA_SUPPOR T bit in the capabilities
register of each SD host socket is set. When this bit is 0, the PGMIF field returns 00h and the
DMA_SUPPORT bit of each SD host socket is 0.
‡One or more bits in this register are cleared only by the assertion of GRST.
8−15
8.23 Subsystem Access Register
The contents of the subsystem access register are aliased to the subsystem vendor ID and subsystem ID registers
at PCI offsets 2Ch and 2Eh, respectively. See Table 8−16 for a complete description of the register contents.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name Subsystem access
Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Default 0000000000000000
Bit 15 14 13 12 11 109876543210
Name Subsystem access
Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Default 0000000000000000
Register: Subsystem access
Offset: 8Ch
Type: Read/Write
Default: 0000 0000h
Table 8−16. Subsystem Access Register Description
BIT FIELD NAME TYPE DESCRIPTION
31−16 SubsystemID RW Subsystem device ID. The value written to this field is aliased to the subsystem ID register at
PCI offset 2Eh.
15−0 SubsystemVendorID RW Subsystem vendor ID. The value written to this field is aliased to the subsystem vendor ID
register at PCI offset 2Ch.
8.24 Diagnostic Register
This register enables the diagnostic modes. See Table 8−17 for a complete description of the register contents. All
bits in this register are reset by GRST only.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name Diagnostic
Type RRRRRRRRRRRRRRRRW
Default 0000000000000000
Bit 15 14 13 12 11 109876543210
Name Diagnostic
Type RRRRRRRRRRRRRRRR
Default 0000000000000000
Register: Diagnostic
Type: Read-only, Read/Write
Offset: 90h
Default: 0000 0000h
Table 8−17. Diagnostic Register Description
BIT SIGNAL TYPE FUNCTION
31−17 RSVD R Reserved. Bits 31−17 return 0s when read.
16 DIAGNOSTIC RW Diagnostic test bit. This test bit shortens the card detect debounce times for simulation and TDL.
15−0 RSVD R Reserved. Bits 15−0 return 0s when read.
8−16
8.25 Slot 0 3.3-V Maximum Current Register
This register is a read/write register and the contents of this register are aliased to the 3_3_MAX_CURRENT field
in the slot 0 maximum current capabilities register at offset 48h in the SD host standard registers. This register is a
GRST only register.
Bit 7 6 5 4 3 2 1 0
Name Slot 0 3.3-V maximum current
Type RW RW RW RW RW RW RW RW
Default 00000000
Register: Slot 3.3-V maximum current
Type: Read/Write
Offset: 94h
Default: 0000h
8.26 Slot 1 3.3-V Maximum Current Register
This register is a read/write register and the contents of this register are aliased to the 3_3_MAX_CURRENT field
in the slot 1 maximum current capabilities register at offset 48h in the SD host standard registers. This register is a
GRST only register. If slot 1 is not implemented, this register is read-only and returns 0s when read.
Bit 7 6 5 4 3 2 1 0
Name Slot 1 3.3-V maximum current
Type RW RW RW RW RW RW RW RW
Default 00000000
Register: Slot 1 3.3-V maximum current
Type: Read/Write
Offset: 98h
Default: 0000h
8.27 Slot 2 3.3-V Maximum Current Register
This register is a read/write register and the contents of this register are aliased to the 3_3_MAX_CURRENT field
in the slot 2 maximum current capabilities register at offset 48h in the SD host standard registers. This register is a
GRST only register. If slot 2 is not implemented, this register is read-only and returns 0s when read.
Bit 7 6 5 4 3 2 1 0
Name Slot 2 3.3-V maximum current
Type RW RW RW RW RW RW RW RW
Default 00000000
Register: Slot 2 3.3-V maximum current
Type: Read/Write
Offset: 9Ch
Default: 0000h
8−17
8.28 Slot 3 3.3-V Maximum Current Register
This register is a read/write register and the contents of this register are aliased to the 3_3_MAX_CURRENT field
in the slot 3 maximum current capabilities register at offset 48h in the SD host standard registers. This register is a
GRST only register. If slot 3 is not implemented, this register is read-only and returns 0s when read.
Bit 7 6 5 4 3 2 1 0
Name Slot 3 3.3-V maximum current
Type RW RW RW RW RW RW RW RW
Default 00000000
Register: Slot 3 3.3-V maximum current
Type: Read/Write
Offset: A0h
Default: 0000h
8.29 Slot 4 3.3-V Maximum Current Register
This register is a read/write register and the contents of this register are aliased to the 3_3_MAX_CURRENT field
in the slot 4 maximum current capabilities register at offset 48h in the SD host standard registers. This register is a
GRST only register. If slot 4 is not implemented, this register is read-only and returns 0s when read.
Bit 7 6 5 4 3 2 1 0
Name Slot 4 3.3-V maximum current
Type RW RW RW RW RW RW RW RW
Default 00000000
Register: Slot 4 3.3-V maximum current
Type: Read/Write
Offset: A4h
Default: 0000h
8.30 Slot 5 3.3-V Maximum Current Register
This register is a read/write register and the contents of this register are aliased to the 3_3_MAX_CURRENT field
in the slot 5 maximum current capabilities register at offset 48h in the SD host standard registers. This register is a
GRST only register. If slot 5 is not implemented, this register is read-only and returns 0s when read.
Bit 7 6 5 4 3 2 1 0
Name Slot 5 3.3-V maximum current
Type RW RW RW RW RW RW RW RW
Default 00000000
Register: Slot 5 3.3-V maximum current
Type: Read/Write
Offset: A8h
Default: 0000h
8−18
9−1
9 Smart Card Controller Programming Model
This section describes the internal PCI configuration registers used to program the PCI6x21/PCI6x11 Smart Card
controller interface. All registers are detailed in the same format: a brief description for each register is followed by
the register offset and a bit table describing the reset state for each register.
A bit description table, typically included when the register contains bits of more than one type or purpose, indicates
bit field names, a detailed field description, and field access tags which appear in the type column. Table 4−1
describes the field access tags.
The PCI6x21/PCI6x11 controller is a multifunction PCI device. The Smart Card controller core is integrated as PCI
function 5. The function 5 configuration header is compliant with the PCI Local Bus Specification as a standard
header. Table 9−1 illustrates the configuration header that includes both the predefined portion of the configuration
space and the user-definable registers.
Table 9−1. Function 5 Configuration Register Map
REGISTER NAME OFFSET
Device ID Vendor ID 00h
Status Command 04h
Class code Revision ID 08h
BIST Header type Latency timer Cache line size 0Ch
SC global control base address 10h
SC socket 0 base address 14h
SC socket 1 base address 18h
Reserved 1Ch−28h
Subsystem ID ‡ Subsystem vendor ID ‡ 2Ch
Reserved 30h
Reserved PCI power
management
capabilities pointer
34h
Reserved 38h
Maximum latency Minimum grant Interrupt pin Interrupt line 3Ch
Reserved 40h
Power management capabilities Next item pointer Capability ID 44h
PM data
(Reserved) PMCSR_BSE Power management control and status ‡ 48h
Reserved General control ‡ 4Ch
Subsystem alias 50h
Class code alias 54h
Smart Card configuration 1 58h
Smart Card configuration 2 5Ch
Reserved 60h−FCh
‡One or more bits in this register are cleared only by the assertion of GRST.
9−2
9.1 Vendor ID Register
The vendor ID register contains a value allocated by the PCI SIG and identifies the manufacturer of the PCI device.
The vendor ID assigned to Texas Instruments is 104Ch.
Bit 15 14 13 12 11 109876543210
Name Vendor ID
Type RRRRRRRRRRRRRRRR
Default 0001000001001100
Register: Vendor ID
Offset: 00h
Type: Read-only
Default: 104Ch
9.2 Device ID Register
The device ID register contains a value assigned to the Smart Card controller by Texas Instruments. The device
identification for the Smart Card controller is 8035h.
Bit 15 14 13 12 11 109876543210
Name Device ID
Type RRRRRRRRRRRRRRRR
Default 1000000000110101
Register: Device ID
Offset: 02h
Type: Read-only
Default: 8035h
9−3
9.3 Command Register
The command register provides control over the Smart Card controller interface to the PCI bus. All bit functions
adhere to the definitions in the PCI Local Bus Specification, as seen in the following bit descriptions. The SERR_EN
and PERR_EN enable bits in this register are internally wired-OR between other functions, and these control bits
appear separately according to their software function. See Table 9−2 for a complete description of the register
contents.
Bit 15 14 13 12 11 109876543210
Name Command
Type RRRRRRW RRW RRW R R R R RW R
Default 0000000000000000
Register: Command
Offset: 04h
Type: Read/Write, Read-only
Default: 0000h
Table 9−2. Command Register Description
BIT FIELD NAME TYPE DESCRIPTION
15−11 RSVD R Reserved. Bits 15−11 return 0s when read.
10 INT_DIS RW INTx disable. When set to 1, this bit disables the function from asserting interrupts on the INTx signals.
0 = INTx assertion is enabled (default)
1 = INTx assertion is disabled
9 FBB_EN R Fast back-to-back enable. The Smart Card interface does not generate fast back-to-back transactions;
therefore, bit 9 returns 0 when read.
8 SER_EN RW System error (SERR) enable. Bit 8 controls the enable for the SERR driver on the PCI interface. SERR
can be asserted after detecting an address parity error on the PCI bus. Both bits 8 and 6 (PERR_EN)
must be set for this function to report address parity errors.
0 = Disable SERR output driver (default)
1 = Enable SERR output driver
7 RSVD R Reserved. Bit 7 returns 0 when read.
6 PERR_EN RW Parity error response enable. Bit 6 controls this function response to parity errors through PERR. Data
parity errors are indicated by asserting PERR, whereas address parity errors are indicated by
asserting SERR.
0 = This function ignores detected parity error (default)
1 = This function responds to detected parity errors
5 VGA_EN R VGA palette snoop enable. The Smart Card interface does not feature VGA palette snooping;
therefore, bit 5 returns 0 when read.
4 MWI_EN R Memory write and invalidate enable. The Smart Card controller does not generate memory write
invalidate transactions; therefore, bit 4 returns 0 when read.
3 SPECIAL R Special cycle enable. The Smart Card interface does not respond to special cycle transactions;
therefore, bit 3 returns 0 when read.
2 MAST_EN R Bus master enable. This function is target only.
1 MEM_EN RW Memory space enable. This bit controls memory access.
0 = Disables this function from responding to memory space accesses (default)
1 = Enables this function to respond to memory space accesses
0 IO_EN R I/O space enable. The Smart Card interface does not implement any I/O-mapped functionality;
therefore, bit 0 returns 0 when read.
9−4
9.4 Status Register
The status register provides device information to the host system. All bit functions adhere to the definitions in the
PCI Local Bus Specification, as seen in the following bit descriptions. Bits in this register may be read normally. A
bit in the status register is reset when a 1 is written to that bit location; a 0 written to a bit location has no effect. See
Table 9−3 for a complete description of the register contents.
Bit 15 14 13 12 11 109876543210
Name Status
Type RCU RCU R R RCU R R R R R R R RU R R R
Default 0000001000010000
Register: Status
Offset: 06h
Type: Read/Clear/Update, Read-only
Default: 0210h
Table 9−3. Status Register Description
BIT FIELD NAME TYPE DESCRIPTION
15 PAR_ERR RCU Detected parity error. Bit 15 is set to 1 when either an address parity or data parity error is detected.
14 SYS_ERR RCU Signaled system error. Bit 14 is set to 1 when SERR is enabled and the Smart Card controller has
signaled a system error to the host.
13 MABORT R This function does not support bus mastering. This bit is hardwired to 0.
12 TABT_REC R This function does not support bus mastering and never receives a target abort. This bit is hardwired
to 0.
11 TABT_SIG RCU Signaled target abort. Bit 11 is set to 1 by the Smart Card controller when it terminates a transaction
on the PCI bus with a target abort.
10−9 PCI_SPEED R DEVSEL timing. Bits 10 and 9 encode the timing of DEVSEL and are hardwired to 01b, indicating that
the Smart Card controller asserts this signal at a medium speed on nonconfiguration cycle accesses.
8 DATAPAR R This function does not support bus mastering. This bit is hardwired to 0.
7 FBB_CAP R Fast back-to-back capable. The Smart Card controller cannot accept fast back-to-back transactions;
therefore, bit 7 is hardwired to 0.
6 RSVD R Reserved. Bit 6 returns 0 when read.
5 66MHZ R 66-MHz capable. The Smart Card controller operates at a maximum PCLK frequency of 33 MHz;
therefore, bit 5 is hardwired to 0.
4 CAPLIST R Capabilities list. Bit 4 returns 1 when read, indicating that the Smart Card controller supports additional
PCI capabilities. The linked list of PCI power-management capabilities is implemented in this function.
3 INT_STAT RU Interrupt status. This bit reflects the interrupt status of the function. Only when bit 10 (INT_DISABLE)
in the command register (see Section 7.3) is a 0 and this bit is 1, is the function’s INTx signal asserted.
Setting the INT_DISABLE bit to 1 has no effect on the state of this bit. This bit is set only when a valid
interrupt condition exists. This bit is not set when an interrupt condition exists and signaling of that event
is not enabled.
2−0 RSVD R Reserved. Bits 3−0 return 0s when read.
9−5
9.5 Class Code and Revision ID Register
The class code and revision ID register categorizes the base class, subclass, and programming interface of the
function. The base class is 07h, identifying the controller as a communication device. The subclass is 80h, identifying
the function as other mass storage controller, and the programming interface is 00h. Furthermore, the TI chip revision
is indicated in the least significant byte (00h). See Table 9−4 for a complete description of the register contents.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name Class code and revision ID
Type RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU
Default 0000011110000000
Bit 15 14 13 12 11 109876543210
Name Class code and revision ID
Type RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU
Default 0000000000000000
Register: Class code and revision ID
Offset: 08h
Type: Read-only
Default: 0780 0000h
Table 9−4. Class Code and Revision ID Register Description
BIT FIELD NAME TYPE DESCRIPTION
31−24 BASECLASS R Base class. This field returns 07h when read, which classifies the function as a communication device.
23−16 SUBCLASS R Subclass. This field returns 80h when read, which specifically classifies the function as other mass
storage controller.
15−8 PGMIF R Programming interface. This field returns 00h when read.
7−0 CHIPREV R Silicon revision. This field returns 00h when read, which indicates the silicon revision of the Smart Card
controller.
9.6 Latency Timer and Class Cache Line Size Register
The latency timer and class cache line size register is programmed by host BIOS to indicate system cache line size
and the latency timer associated with the Smart Card controller. See Table 9−5 for a complete description of the
register contents.
Bit 15 14 13 12 11 109876543210
Name Latency timer and class cache line size
Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Default 0000000000000000
Register: Latency timer and class cache line size
Offset: 0Ch
Type: Read/Write
Default: 0000h
Table 9−5. Latency Timer and Class Cache Line Size Register Description
BIT FIELD NAME TYPE DESCRIPTION
15−8 LATENCY_TIMER RW PCI latency timer. The value in this register specifies the latency timer for the Smart Card controller,
in units of PCI clock cycles. When the Smart Card controller is a PCI bus initiator and asserts FRAME,
the latency timer begins counting from zero. If the latency timer expires before the Smart Card
transaction has terminated, then the Smart Card controller terminates the transaction when its GNT
is deasserted.
7−0 CACHELINE_SZ RW Cache line size. This value is used by the Smart Card controller during memory write and invalidate,
memory-read line, and memory-read multiple transactions.
9−6
9.7 Header Type and BIST Register
The header type and built-in self-test (BIST) register indicates the Smart Card controller PCI header type and no
built-in self-test. See Table 9−6 for a complete description of the register contents.
Bit 15 14 13 12 11 109876543210
Name Header type and BIST
Type RRRRRRRRRRRRRRRR
Default 00000000x0000000
Register: Header type and BIST
Offset: 0Eh
Type: Read-only
Default: 00x0h
Table 9−6. Header Type and BIST Register Description
BIT FIELD NAME TYPE DESCRIPTION
15−8 BIST R Built-in self-test. The Smart Card controller does not include a BIST; therefore, this field returns 00h
when read.
7−0 HEADER_TYPE R PCI header type. The Smart Card controller includes the standard PCI header . Bit 7 indicates if the Smart
Card is a multifunction device.
9.8 Smart Card Base Address Register 0
This register is used by this function to determine where to forward a memory transaction to the Smart Card global
control register set. Bits 31−12 of this register are read/write and allow the base address to be located anywhere in
the 32-bit PCI memory space on 4-Kbyte boundary. The window size is always 4K bytes. Bits 11−0 are read-only and
always return 0s. Write transactions to these bits have no effect. Bit 3 (0b) specifies that this window is
nonprefetchable. Bits 2−1 (00b) specify that this memory window can allocate anywhere in the 32-bit address space.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name Smart Card base address register 0
Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Default 0000000000000000
Bit 15 14 13 12 11 109876543210
Name Smart Card base address register 0
Type RW RW RW RW R R R R R R R R R R R R
Default 0000000000000000
Register: Smart Card base address register 0
Offset: 10h
Type: Read/Write, Read-only
Default: 0000 0000h
9−7
9.9 Smart Card Base Address Register 1−4
Each socket has its own base address register. For example, a device supports three Smart Card sockets uses three
base address registers, BA1 (socket 0), BA2 (socket 1) and BA3 (socket 2).
These registers are used by this function to determine where to forward a memory transaction to the Smart Card
Control and Communication Register sets. Bits 31−12 of this register are read/write and allow the base address to
be located anywhere in the 32-bit PCI memory space on 4-Kbyte boundaries and the window size is always 4K bytes.
Bits 11−4 are read-only and always return 0s. Write transactions to these bits have n o ef fect. Bit 3 (0b) specifies that
these windows are nonprefetchable. Bits 2−1 (00b) specify that this memory window can allocate anywhere in the
32-bit address space.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name Smart Card base address register 1−4
Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Default 0000000000000000
Bit 15 14 13 12 11 109876543210
Name Smart Card base address register 1−4
Type RW RW RW RW RRRRRRRRRRRR
Default 0000000000000000
Register: Smart Card base address register 1−4
Offset: 14h, 18h, 1Ch, and 20h
Type: Read/Write, Read-only
Default: 0000 0000h
9.10 Subsystem Vendor Identification Register
This register is read-update and can be modified through the subsystem vendor ID alias register. Default value is
104Ch. This default value complies with the WLP (Windows Logo Program) requirements without BIOS or EEPROM
configuration. All bits in this register are reset by GRST only.
Bit 15 14 13 12 11 109876543210
Name Subsystem vendor identification
Type RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU
Default 0001000001001100
Register: Subsystem vendor identification
Offset: 2Ch
Type: Read/Update
Default: 104Ch
9−8
9.11 Subsystem Identification Register
This register is read-update and can be modified through the subsystem ID alias register. This register has no effect
to the functionality. Default value is 8035h. This default value complies with the WLP (Windows Logo Program)
requirements without BIOS or EEPROM configuration. All bits in this register are reset by GRST only.
Bit 15 14 13 12 11 109876543210
Name Subsystem identification
Type RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU
Default 1000000000110101
Register: Subsystem identification
Offset: 2Eh
Type: Read/Update
Default: 8035h
9.12 Capabilities Pointer Register
The power management capabilities pointer register provides a pointer into the PCI configuration header where the
power-management register block resides. Since the PCI power management registers begin at 44h, this read-only
register is hardwired to 44h.
Bit 7 6 5 4 3 2 1 0
Name Capabilities pointer
Type R R R R R R R R
Default 0 1 0 0 0 1 0 0
Register: Capabilities pointer
Offset: 34h
Type: Read-only
Default: 44h
9.13 Interrupt Line Register
The interrupt line register is programmed by the system and indicates to the software which interrupt line the Smart
Card interface has assigned to it. The default value of this register is FFh, indicating that an interrupt line has not yet
been assigned to the function.
Bit 7 6 5 4 3 2 1 0
Name Interrupt line
Type RW RW RW RW RW RW RW RW
Default 11111111
Register: Interrupt line
Offset: 3Ch
Type: Read/Write
Default: FFh
9−9
9.14 Interrupt Pin Register
This register decodes the interrupt select inputs and returns the proper interrupt value based on Table 9−7, indicating
that the Smart Card interface uses an interrupt. If one of the USE_INTx terminals is asserted, the interrupt select bits
are ignored, and this register returns the interrupt value for the highest priority USE_INTx terminal that is asserted.
If bit 28, the tie-all bit (TIEALL), in the system control register (PCI offset 80h, see Section 4.29) is set to 1, then the
PCI6x21/PCI6x11 controller asserts the USE_INTA input to the Smart Card controller core. If bit 28 (TIEALL) in the
system control register (PCI of fset 80h, see Section 4.29) is set to 0, then none of the USE_INTx inputs are asserted
and the interrupt for the Smart Card function is selected by the INT_SEL bits in the Smart Card general control register .
Bit 7 6 5 4 3 2 1 0
Name Interrupt pin
Type R R R R R R R R
Default 0 0 0 0 0 X X X
Register: Interrupt pin
Offset: 3Dh
Type: Read-only
Default: 0Xh
Table 9−7. PCI Interrupt Pin Register
INT_SEL BITS USE_INTA INTPIN
00 0 01h (INTA)
01 0 02h (INTB)
10 0 03h (INTC)
11 004h (INTD)
XX 1 01h (INTA)
9.15 Minimum Grant Register
The minimum grant register contains the minimum grant value for the Smart Card controller core.
Bit 76543210
Name Minimum grant
Type RU RU RU RU RU RU RU RU
Default 00000111
Register: Minimum grant
Offset: 3Eh
Type: Read/Update
Default: 07h
Table 9−8. Minimum Grant Register Description
BIT FIELD NAME TYPE DESCRIPTION
7−0 MIN_GNT RU Minimum grant. The contents of this field may be used by host BIOS to assign a latency timer register value
to the Smart Card controller . The default for this register indicates that the Smart Card controller may need
to sustain burst transfers for nearly 64 µs and thus request a large value be programmed in bits 15−8 of
the PCI6x21/PCI6x11 latency timer and class cache line size register at offset 0Ch in the PCI configuration
space (see Section 9.6).
9−10
9.16 Maximum Latency Register
The maximum latency register contains the maximum latency value for the Smart Card controller core.
Bit 7 6 5 4 3 2 1 0
Name Maximum latency
Type RU RU RU RU RU RU RU RU
Default 00000100
Register: Maximum latency
Offset: 3Eh
Type: Read/Update
Default: 04h
Table 9−9. Maximum Latency Register Description
BIT FIELD NAME TYPE DESCRIPTION
7−0 MAX_LAT RU Maximum latency. The contents of this field may be used by host BIOS to assign an arbitration priority level
to the Smart Card controller . The default for this register indicates that the Smart Card controller may need
to access the PCI bus as often as every 0.25 µs; thus, an extremely high priority level is requested. The
contents of this field may also be loaded through the serial EEPROM.
9.17 Capability ID and Next Item Pointer Registers
The capability ID and next item pointer register identifies the linked-list capability item and provides a pointer to the
next capability item. See Table 9−10 for a complete description of the register contents.
Bit 15 14 13 12 11 109876543210
Name Capability ID and next item pointer
Type RRRRRRRRRRRRRRRR
Default 0000000000000001
Register: Capability ID and next item pointer
Offset: 44h
Type: Read-only
Default: 0001h
Table 9−10. Capability ID and Next Item Pointer Registers Description
BIT FIELD NAME TYPE DESCRIPTION
15−8 NEXT_ITEM R Next item pointer. The Smart Card controller supports only one additional capability, PCI power
management, that is communicated to the system through the extended capabilities list; therefore,
this field returns 00h when read.
7−0 CAPABILITY_ID R Capability identification. This field returns 01h when read, which is the unique ID assigned by the PCI
SIG for PCI power-management capability.
9−11
9.18 Power Management Capabilities Register
The power management capabilities register indicates the capabilities of the Smart Card controller related to PCI
power management. See Table 9−11 for a complete description of the register contents.
Bit 15 14 13 12 11 109876543210
Name Power management capabilities
Type RURRRRRRRRRRRRRRR
Default 0111111000000010
Register: Power management capabilities
Offset: 46h
Type: Read/Update, Read-only
Default: 7E02h
Table 9−11. Power Management Capabilities Register Description
BIT FIELD NAME TYPE DESCRIPTION
15 PME_D3COLD RU PME support from D3cold. This bit can be set to 1 or cleared to 0 via bit 4 (D3_COLD) in the general
control register at offset 4Ch in the PCI configuration space (see Section 9.22). When this bit is set to
1, it indicates that the controller is capable of generating a PME wake event from D3cold. This bit state
is dependent upon the PCI6x21/PCI6x11 VAUX implementation and may be configured by using bit 4
(D3_COLD) in the general control register (see Section 9.22).
14 PME_D3HOT R PME support. This 4-bit field indicates the power states from which the Smart Card interface ma
y
assert PME. This field returns a value of 11 11b by default, indicating that PME may be asserted from
13 PME_D2 R
PME support. This 4-bit field indicates the power states from which the Smart Card interface may
assert PME. This field returns a value of 11 11b by default, indicating that PME may be asserted from
the D3hot, D2, D1, and D0 power states.
12 PME_D1 R
the D3
hot
, D2, D1, and D0 power states.
11 PME_D0 R
10 D2_SUPPORT R D2 support. Bit 10 is hardwired to 1, indicating that the Smart Card controller supports the D2 power
state.
9 D1_SUPPORT R D1 support. Bit 9 is hardwired to 1, indicating that the Smart Card controller supports the D1 power
state.
8−6 AUX_CURRENT R Auxiliary current. This 3-bit field reports the 3.3-VAUX auxiliary current requirements. When bit 15
(PME_D3COLD) is cleared, this field returns 000b; otherwise, it returns 001b.
000b = Self-powered
001b = 55 mA (3.3-VAUX maximum current required)
5 DSI R Device-specific initialization. This function requires device-specific initialization.
4 RSVD R Reserved. Bit 4 returns 0 when read.
3 PME_CLK R PME clock. This bit returns 0 when read, indicating that the PCI clock is not required for the Smart Card
controller to generate PME.
2−0 PM_VERSION R Power-management version. This field returns 010b when read, indicating that the Smart Card
controller is compatible with the registers described in the PCI Bus Power Management Interface
Specification (Revision 1.1).
9−12
9.19 Power Management Control and Status Register
The power management control and status register implements the control and status of the Smart Card controller.
This register is not af fected by the internally generated reset caused by the transition from the D3hot to D0 state. See
Table 9−12 for a complete description of the register contents.
Bit 15 14 13 12 11 109876543210
Name Power management control and status
Type RCU R R R R R R RW R R R R R R RW RW
Default 0000000000000000
Register: Power management control and status
Offset: 48h
Type: Read/Clear/Update, Read/Write, Read-only
Default: 0000h
Table 9−12. Power Management Control and Status Register Description
BIT FIELD NAME TYPE DESCRIPTION
15 ‡ PME_STAT RCU PME status. This bit is set when the function would normally assert the PME signal independent of the
state of PME_EN bit. Writing a 1 to this bit clears it and causes the function to stop asserting a PME
(if enabled). Writing a 0 has no effect. This bit is initialized by GRST only when the PME_D3cold bit
is 1.
14−9 RSVD R Reserved. Bits 14−9 return 0s when read.
8 ‡ PME_EN RW PME enable. This bit is initialized by GRST only when PME_D3cold bit is 1.
7−2 RSVD R Reserved. Bits 7−2 return 0s when read.
1−0 ‡ DSTATE RW Device State: This bit field controls device power management state. Invalid state assignments are
ignored. (ex. Current state 10b → writing 01b. This is rejected and stays 10b. See the latest PCI Local
Bus Specification.) This bit field is initialized by GRST only when PME_D3cold bit is 1.
‡One or more bits in this register are cleared only by the assertion of GRST.
9.20 Power Management Bridge Support Extension Register
The power management bridge support extension register provides extended power-management features not
applicable to the Smart Card controller; thus, it is read-only and returns 0 when read.
Bit 7 6 5 4 3 2 1 0
Name Power management bridge support extension
Type RRRRRRRR
Default 00000000
Register: Power management bridge support extension
Offset: 4Ah
Type: Read-only
Default: 00h
9−13
9.21 Power Management Data Register
The power management bridge support extension register provides extended power-management features not
applicable to the Smart Card controller; thus, it is read-only and returns 0 when read.
Bit 76543210
Name Power management data
Type RRRRRRRR
Default 00000000
Register: Power management data
Offset: 4Bh
Type: Read-only
Default: 00h
9.22 General Control Register
This register controls this function. Information of this register can be read from the socket configuration register in
the Smart Card socket control register set. See Table 9−13 for a complete description of the register contents.
Bit 15 14 13 12 11 109876543210
Name General control
Type RRRRRRRRRRW RW RW RRRR
Default 0000000000000000
Register: General control
Offset: 4Ch
Type: Read/Write (EEPROM, GRST only)
Default: 0000h
Table 9−13. General Control Register
BIT FIELD NAME TYPE DESCRIPTION
15−7 RSVD R Reserved. Bits 15−7 return 0s when read.
6−5 ‡ INT_SEL RW Interrupt select. These bits are program the INTPIN register and set which interrupt output is used.
This field is ignored if one of the USE_INTx terminals is asserted.
00 = INTA (pin = 1)
01 = INTB (pin = 2)
10 = INTC (pin = 3)
11 = INTD (pin = 4)
4 ‡ D3_COLD RW Disable function. Setting this bit to 1 hides this function. PCI configuration register of this function
must be accessible at any time. Clock (PCI and 48 MHz) to the rest of the function blocks must be
gated to reduce power consumption.
3−0 RSVD R Reserved. Bits 3−0 return 0s when read.
‡One or more bits in this register are cleared only by the assertion of GRST.
9−14
9.23 Subsystem ID Alias Register
The contents of the subsystem access register are aliased to the subsystem vendor ID and subsystem ID registers
at PCI offsets 2Ch and 2Eh, respectively. See Table 9−14 for a complete description of the register contents.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name Subsystem ID alias
Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Default 1000000000110101
Bit 15 14 13 12 11 109876543210
Name Subsystem ID alias
Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Default 0001000001001100
Register: Subsystem ID alias
Offset: 50h
Type: Read/Write (EEPROM, GRST only)
Default: 8035 104Ch
Table 9−14. Subsystem ID Alias Register Description
BIT FIELD NAME TYPE DESCRIPTION
31−16 SubsystemID RW Subsystem device ID. The value written to this field is aliased to the subsystem ID register at
PCI offset 2Eh.
15−0 SubsystemVendorID RW Subsystem vendor ID. The value written to this field is aliased to the subsystem vendor ID
register at PCI offset 2Ch.
9.24 Class Code Alias Register
This register is alias of the class code. Not like original register, this register is read/write and loadable from EEPROM.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name Class code alias
Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Default 0000011110000000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Class code alias
Type RW RW RW RW RW RW RW RW RW RW RRRRRR
Default 0000000000000000
Register: Class code alias
Offset: 54h
Type: Read-only, Read/Write (EEPROM, GRST only)
Default: 0780 0000h
9−15
9.25 Smart Card Configuration 1 Register
BIOS or EEPROM configure system dependent Smart Card interface information through this register. Information
of this register can be read from the Smart Card configuration 1 alias register in the Smart Card global control register
set. The software utilizes this information and adjusts the software and firmware behavior if necessary.
Corresponding bits are tied to 0 if the socket is not implemented.
Class A and B support are depend on the system and integrated device. Supporting both classes requires method
(pins) to control 5.0 V and 3.0 V.
Default value and bit types are depending on the device. When this core is integrated into a device and does not have
all four sockets, removed sockets bits must be tied to 0 and changed to read-only bits.
See Table 9−15 for a complete description of the register contents. All bits in this register are reset by GRST only.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name Smart Card configuration 1
Type RW RW RW RW RRW RW RW RRW RW RW RRW RW RW
Default 0000001101110100
Bit 15 14 13 12 11 109876543210
Name Smart Card configuration 1
Type RRW RW RW RRRRRRW RW RW RRW RW RW
Default 0011001100000111
Register: Smart Card configuration 1
Offset: 58h
Type: Read/Write, Read-only (EEPROM, GRST only)
Default: 0374 3307h
9−16
Table 9−15. Smart Card Configuration 1 Register Description
BIT FIELD NAME TYPE DESCRIPTION
31−28 SCRTCH_PAD RW Scratch pad
27 CLASS_B_SKT3 R Socket 3 Class B Smart Card support. Since socket 3 is not implemented in the controller , this
bit is a read-only 0.
26 CLASS_B_SKT2 RW Socket 2 Class B Smart Card support. Since socket 2 is not implemented in the controller, this
bit is a read-only 0.
25 CLASS_B_SKT1 RW Socket 1 Class B Smart Card support. When this bit is set to 1, socket 1 supports Class B Smart
Cards.
24 CLASS_B_SKT0 RW Socket 0 Class B Smart Card support. When this bit is set to 1, socket 0 supports Class B Smart
Cards.
23 CLASS_A_SKT3 R Socket 3 Class A Smart Card support. Since socket 3 is not implemented in the controller , this
bit is a read-only 0.
22 CLASS_A_SKT2 RW Socket 2 Class A Smart Card support. Since socket 2 is not implemented in the controller, this
bit is a read-only 0.
21 CLASS_A_SKT1 RW Socket 1 Class A Smart Card support. When this bit is set to 1, socket 1 supports Class A Smart
Cards.
20 CLASS_A_SKT0 RW Socket 0 Class A Smart Card support. When this bit is set to 1, socket 0 supports Class A Smart
Cards.
19 EMVIF_EN_SKT3 R Socket 3 EMV interface enable. Since socket 3 is not implemented in the controller, this bit is
a read-only 0.
18 EMVIF_EN_SKT2 RW Socket 2 EMV interface enable. Since socket 2 is not implemented in the controller, this bit is
a read-only 0.
17 EMVIF_EN_SKT1 RW Socket 1 EMV interface enable. When this bit is set to 1, the internal EVM interface for socket
1 is enabled.
16 EMVIF_EN_SKT0 RW Socket 0 EMV interface enable. When this bit is set to 1, the internal EVM interface for socket
0 is enabled.
15 GPIO_EN_SKT3 R Socket 3 GPIO enable. Since socket 3 is not implemented in the controller, this bit is a read-only
0.
14 GPIO_EN_SKT2 RW Socket 2 GPIO enable. Since socket 2 is not implemented in the controller, this bit is a read-only
0.
13 GPIO_EN_SKT1 RW Socket 1 GPIO enable. When this bit is set to 1, the SC_GPIOs for socket 1 are enabled.
12 GPIO_EN_SKT0 RW Socket 0 GPIO enable. When this bit is set to 1, the SC_GPIOs for socket 0 are enabled.
11 PCMCIA_MODE_SKT3 R Socket 3 PCMCIA mode. Since socket 3 is not implemented in the controller, this bit is a
read-only 0.
10 PCMCIA_MODE_SKT2 R Socket 2 PCMCIA mode. Since socket 2 is not implemented in the controller, this bit is a
read-only 0.
9 PCMCIA_MODE_SKT1 R Socket 1 PCMCIA mode. Since socket 1 is implemented as a dedicated socket in the controller,
this bit returns 1 when read.
8 PCMCIA_MODE_SKT0 R Socket 0 PCMCIA mode. Since socket 0 is implemented as a dedicated socket in the controller,
this bit returns 1 when read.
7 PME_SUPPORT_SKT3 R Socket 3 PME support. Since socket 3 is not implemented in the controller, this bit is a read-only
0.
6 PME_SUPPORT_SKT2 RW Socket 2 PME support. Since socket 2 is not implemented in the controller, this bit is a read-only
0.
5 PME_SUPPORT_SKT1 RW Socket 1 PME support. When this bit is set to 1, socket 1 card insertions cause a PME event.
4 PME_SUPPORT_SKT0 RW Socket 0 PME support. When this bit is set to 1, socket 0 card insertions cause a PME event.
3 SKT3_EN R Socket 3 enable. Since socket 3 is not implemented in the controller, this bit is a read-only 0.
2 SKT2_EN RW Socket 2 enable. Since socket 2 is not implemented in the controller, this bit is a read-only 0.
1 SKT1_EN RW Socket 1 enable. When this bit is set to 1, socket 1 is enabled.
0 SKT0_EN RW Socket 0 enable. When this bit is set to 1, socket 0 is enabled.
9−17
9.26 Smart Card Configuration 2 Register
BIOS or EEPROM configure system dependent Smart Card interface information through this register. Information
of this register can be read from the Smart Card configuration 2 alias in the Smart Card global control register set.
The software utilizes this information and adjusts the software and firmware behavior, if necessary.
See Table 9−16 for a complete description of the register contents. All bits in this register are reset by GRST only.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name Smart Card configuration 2
Type RRRRRRRRRRRRRRRR
Default 0000000000000000
Bit 15 14 13 12 11 109876543210
Name Smart Card configuration 2
Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Default 0000000000000000
Register: Smart Card Configuration 2
Offset: 54h
Type: Read-only, Read/Write (EEPROM, GRST only)
Default: 0000 0000h
Table 9−16. Smart Card Configuration 2 Register Description
BIT SIGNAL TYPE FUNCTION
31−16 RSVD R Reserved. Bits 31−16 return 0s when read.
15−8 PWRUP_DELAY_
PCMCIA RPower up delay for the PCMCIA socket. This register indicates how long the external power switch
takes to apply stable power to the PCMCIA socket in ms. Software must wait before starting
operation after power up. This field has no effect for the hardware.
7−0 RSVD R Reserved. Bits 7−0 return 0s when read.
9−18
10−1
10 Electrical Characteristics
10.1 Absolute Maximum Ratings Over Operating Temperature Ranges†
Supply voltage range, VR_PORT −0.2 V to 2.2 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ANALOGVCC −0.3 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VCC −0.3 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PLLVCC −0.3 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VCCCB −0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VCCP −0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clamping voltage range, VCCP and VCCCB −0.5 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI: PCI, CardBus, PHY, miscellaneous −0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO: PCI, CardBus, PHY, miscellaneous −0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 2) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Human Body Model (HBM) ESD performance 1500 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature, TA0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Virtual junction temperature, TJ150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Applies for external input and bidirectional buffers. VI > VCC does not apply to fail-safe terminals. PCI terminals and miscellaneous
terminals are measured with respect to VCCP instead of VCC. PC Card terminals are measured with respect to CardBus VCC. The
limit specified applies for a dc condition.
2. Applies for external output and bidirectional buf fers. VO > VCC does not apply to fail-safe terminals. PCI terminals and miscellaneous
terminals are measured with respect to VCCP instead of VCC. PC Card terminals are measured with respect to CardBus VCC. The
limit specified applies for a dc condition.
10.2 Recommended Operating Conditions (see Note 3)
OPERATION MIN NOM MAX UNIT
VR_PORT (see Table 2−4 for description) 1.8 V 1.6 1.8 2 V
ANALOGVCC 3.3 V 3 3.3 3.6 V
VCC 3.3 V 3 3.3 3.6 V
PLLVCC 3.3 V 3 3.3 3.6 V
VCCP
PCI and miscellaneous I/O clamp voltage
3.3 V 3 3.3 3.6
V
VCCP PCI and miscellaneous I/O clamp voltage 5 V 4.75 5 5.25 V
VCCCB
PC Card I/O clamp voltage
3.3 V 3 3.3 3.6
V
VCCCB PC Card I/O clamp voltage 5 V 4.75 5 5.25 V
NOTE 3: Unused terminals (input or I/O) must be held high or low to prevent them from floating.
10−2
Recommended Operating Conditions (continued)
OPERATION MIN NOM MAX UNIT
PCI
3.3 V 0.5 VCCP VCCP
PCI 5 V 2 VCCP V
High-level input
3.3 V CardBus 0.475 VCC(A/B) VCC(A/B)
V
V
IH
†High-level input
voltage
PC Card 3.3 V 16-bit 2 VCC(A/B) V
VIH†
voltage
PC Card
5 V 16-bit 2.4 VCC(A/B) V
PC(0−2) 0.7 VCC VCC V
Miscellaneous‡2 VCC V
PCI
3.3 V 0 0.3 VCCP
PCI 5 V 0 0.8 V
3.3 V CardBus 0 0.325 VCC(A/B)
V
V
IL
†Low-level input voltage PC Card 3.3 V 16-bit 0 0.8 V
VIL†
Low-level input voltage
PC Card
5 V 16-bit 0 0.8 V
PC(0−2) 0 0.2 VCC V
Miscellaneous‡0 0.8 V
PCI 0 VCCP
V
I
Input voltage PC Card 0 VCCCB V
VI
Input voltage
Miscellaneous‡0 VCC
V
PCI 0 VCC
V
O
§Output voltage PC Card 0 VCC V
VO§
Output voltage
Miscellaneous‡0 VCC
V
tt
Input transition time
PCI and PC Card 1 4
ns
tt
Input transition time
(tr and tf)Miscellaneous‡0 6 ns
IOOutput current TPBIAS outputs −5.6 1.3 mA
VID
Differential input
Cable inputs during data reception 118 260
mV
VID
Differential input
voltage Cable inputs during arbitration 168 265 mV
VIC
Common-mode input
TPB cable inputs, source power node 0.4706 2.515
V
VIC
Common-mode input
voltage TPB cable inputs, nonsource power node 0.4706 2.015¶V
tPU Powerup reset time GRST input 2 ms
S100 operation ±1.08
Receive input jitter TPA, TPB cable inputs S200 operation ±0.5 ns
Receive input jitter
TPA, TPB cable inputs
S400 operation ±0.315
ns
Between TPA and TPB
S100 operation ±0.8
Receive input skew Between TPA and TPB
cable inputs
S200 operation ±0.55 ns
Receive input skew
cable inputs
S400 operation ±0.5
ns
TAOperating ambient temperature range 0 25 70 °C
TJ# Virtual junction temperature 0 25 115 °C
†Applies to external inputs and bidirectional buffers without hysteresis
‡Miscellaneous terminals are 1, 2, 12, 17, 111, 112, 125, 167, 181, and 187 for the PDV packaged device and B10, C09, D01, E03, F12, G03,
H02, L17, P17, and P18 for the GHK packaged device (CNA, SCL, SDA, SUSPEND, GRST, CDx, PHY_TEST_MA, and VSx terminals).
§Applies to external output buffers
¶For a node that does not source power, see Section 4.2.2.2 in IEEE Std 1394a−2000.
#These junction temperatures reflect simulation conditions. The customer is responsible for verifying junction temperature.
10−3
10.3 Electrical Characteristics Over Recommended Operating Conditions (unless
otherwise noted)
PARAMETER TERMINALS OPERATION TEST CONDITIONS MIN MAX UNIT
PCI
3.3 V IOH = −0.5 mA 0.9 VCC
V
PCI
5 V IOH = −2 mA 2.4 V
VOH
High-level output voltage
3.3 V CardBus IOH = −0.15 mA 0.9 VCC
VOH High-level output voltage PC Card 3.3 V 16-bit IOH = −0.15 mA 2.4
PC Card
5 V 16-bit IOH = −0.15 mA 2.8 V
Miscellaneous§
IOH = −4 mA
VCC−0.6
V
Miscellaneous
§
I
OH
= −4 mA V
CC
−0.
6
PCI
3.3 V IOL = 1.5 mA 0.1 VCC
PCI
5 V IOL = 6 mA 0.55
VOL
Low-level output voltage
3.3 V CardBus IOL = 0.7 mA 0.1 VCC
V
VOL
Low-level output voltage
PC Card 3.3 V 16-bit IOL = 0.7 mA 0.4 V
PC Card
5 V 16-bit IOL = 0.7 mA 0.55
Miscellaneous§IOL = 4 mA 0.5
IOZ 3-state output high-impedance Output terminals 3.6 V VO = VCC or GND ±20 µA
IOZL
High-impedance, low-level
Output terminals
3.6 V VI = VCC −1
A
IOZL
High-impedance, low-level
output current Output terminals 5.25 V VI = VCC −1 µA
IOZH
High-impedance, high-level
Output terminals
3.6 V VI = VCC†10
A
IOZH
High-impedance, high-level
output current Output terminals 5.25 V VI = VCC†25 µA
IIL
Low-level input current
Input terminals 3.6 V VI = GND ±20
A
IIL Low-level input current I/O terminals 3.6 V VI = GND ±20 µA
PCI 3.6 V VI = VCC‡±20
Others 3.6 V VI = VCC‡±20
IIH
High-level input current
Input terminals
3.6 V VI = VCC‡10
µA
I
IH
High-level input current
Input terminals 5.25 V VI = VCC‡20 µ
A
I/O terminals
3.6 V VI = VCC‡10
I/O terminals 5.25 V VI = VCC‡25
†For PCI and miscellaneous terminals, VI = VCCP. For PC Card terminals, VI = VCC(A/B).
‡For I/O terminals, input leakage (IIL and IIH) includes IOZ leakage of the disabled output.
§Miscellaneous terminals are 1, 2, 12, 17, 111, 112, 125, 167, 181, and 187 for the PDV packaged device and B10, C09, D01, E03, F12, G03,
H02, L17, P17, and P18 for the GHK packaged device (CNA, SCL, SDA, SUSPEND, GRST, CDx, PHY_TEST_MA, and VSx terminals).
10.4 Electrical Characteristics Over Recommended Ranges of Operating Conditions
(unless otherwise noted)
10.4.1 Device
PARAMETER TEST CONDITION MIN MAX UNIT
VTH Power status threshold, CPS input†400-kΩ resistor†4.7 7.5 V
VOTPBIAS output voltage At rated IO current 1.665 2.015 V
IIInput current (PC0−PC2 inputs) VCC = 3.6 V 5µA
†Measured at cable power side of resistor.
10−4
10.4.2 Driver
PARAMETER TEST CONDITION MIN MAX UNIT
VOD Differential output voltage 56 Ω, See Figure 10−1 172 265 mV
IDIFF Driver difference current, TPA+, TPA−, TPB+, TPB− Drivers enabled, speed signaling off −1.05†1.05†mA
ISP200 Common-mode speed signaling current, TPB+, TPB− S200 speed signaling enabled −4.84‡−2.53‡mA
ISP400 Common-mode speed signaling current, TPB+, TPB− S400 speed signaling enabled −12.4‡−8.10‡mA
VOFF Off state differential voltage Drivers disabled, See Figure 10−1 20 mV
†Limits defined as algebraic sum of TPA+ and TPA− driver currents. Limits also apply to TPB+ and TPB− algebraic sum of driver currents.
‡Limits defined as absolute limit of each of TPB+ and TPB− driver currents.
TPAx+
TPBx+
TPAx−
TPBx−
56 Ω
Figure 10−1. Test Load Diagram
10.4.3 Receiver
PARAMETER TEST CONDITION MIN TYP MAX UNIT
ZID
Differential impedance
Drivers disabled
4 7 kΩ
ZID Differential impedance Drivers disabled 4 pF
ZIC
Common-mode impedance
Drivers disabled
20 kΩ
ZIC Common-mode impedance Drivers disabled 24 pF
VTH−R Receiver input threshold voltage Drivers disabled −30 30 mV
VTH−CB Cable bias detect threshold, TPBx cable inputs Drivers disabled 0.6 1.0 V
VTH+Positive arbitration comparator threshold voltage Drivers disabled 89 168 mV
VTH−Negative arbitration comparator threshold voltage Drivers disabled −168 −89 mV
VTH−SP200 Speed signal threshold TPBIAS−TPA common mode
voltage, drivers disabled
49 131 mV
VTH−SP400 Speed signal threshold
TPBIAS−TPA common mode
voltage, drivers disabled 314 396 mV
10.5 PCI Clock/Reset Timing Requirements Over Recommended Ranges of Supply
Voltage and Operating Free-Air Temperature
PARAMETER ALTERNATE
SYMBOL TEST CONDITIONS MIN MAX UNIT
tcCycle time, PCLK tcyc 30 ns
tw(H) Pulse duration (width), PCLK high thigh 11 ns
tw(L) Pulse duration (width), PCLK low tlow 11 ns
tr, tfSlew rate, PCLK ∆v/∆t 1 4 V/ns
twPulse duration (width), GRST trst 1 ms
tsu Setup time, PCLK active at end of PRST trst-clk 100 ms
10−5
10.6 Switching Characteristics for PHY Port Interface
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Jitter, transmit Between TPA and TPB ±0.15 ns
Skew, transmit Between TPA and TPB ±0.10 ns
trTP differential rise time, transmit 10% to 90%, at 1394 connector 0.5 1.2 ns
tfTP differential fall time, transmit 90% to 10%, at 1394 connector 0.5 1.2 ns
10.7 Operating, Timing, and Switching Characteristics of XI
PARAMETER MIN TYP MAX UNIT
VDD 3.0 3.3 3.6 V (PLLVCC)
VIH High-level input voltage 0.63VCC V
VIL Low-level input voltage 0.33VCC V
Input clock frequency 24.576 MHz
Input clock frequency tolerance <100 PPM
Input slew rate 0.2 4 V/ns
Input clock duty cycle 40% 60%
10.8 PCI Timing Requirements Over Recommended Ranges of Supply Voltage and
Operating Free-Air Temperature
This data manual uses the following conventions to describe time ( t ) intervals. The format is tA, where subscript A
indicates the type of dynamic parameter being represented. One of the following is used: tpd = propagation delay time,
td (ten, tdis) = delay time, tsu = setup time, and th = hold time.
PARAMETER ALTERNATE
SYMBOL TEST CONDITIONS MIN MAX UNIT
tpd
Propagation delay time, See Note 4
PCLK-to-shared signal
valid delay time tval
CL = 50 pF,
11
ns
tpd Propagation delay time, See Note 4 PCLK-to-shared signal
invalid delay time tinv
CL = 50 pF,
See Note 4 2ns
ten Enable time, high impedance-to-active delay time from PCLK ton 2 ns
tdis Disable time, active-to-high impedance delay time from PCLK toff 28 ns
tsu Setup time before PCLK valid tsu 7 ns
thHold time after PCLK high th0 ns
NOTE 4: PCI shared signals are AD31−AD0, C/BE3−C/BE0, FRAME, TRDY, IRDY, STOP, IDSEL, DEVSEL, and PAR.
10−6
11−1
11 Mechanical Information
The PCI6x21/PCI6x11 device is available in the 288-terminal MicroStar BGA package (GHK) or the 288-terminal
lead (Pb atomic number 82) free MicroStar BGA package (ZHK). The following figure shows the mechanical
dimensions for the GHK package. The GHK and ZHK packages are mechanically identical; therefore, only the GHK
mechanical drawing is shown.
GHK (S-PBGA-N288) PLASTIC BALL GRID ARRAY
0,08 0,12
1,40 MAX0,85
0,45
0,55
0,35
0,45
0,95
15,90 SQ
16,10
Seating Plane
7
J
B
A
1
D
C
E
G
F
H
24
36
5
T
K
M
L
P
N
R
W
U
V
128 91011 15
14
13 1617
14,40 TYP
1819
4145273-4/E 08/02
A1 Corner
0,80
0,80
Bottom View
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. MicroStar BGA configuration.
MicroStar BGA is a trademark of Texas Instruments.
11−2
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PCI6421, Status: ACTIVE
Integrated dual-socket UltraMedia PC Card controller, and flash media
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28 Jun 2004 Download
PCI6421
Supply Voltage
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3.3
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PC Card Standard 8.1 compliant
PCI Bus Power Management Interface Specification 1.1 compliant
Advanced Configuration and Power Interface (ACPI) Specification 2.0 compliant
PCI Local Bus Specification Revision 2.3 compliant
PC 98/99 and PC 2001 compliant
Windows Logo Program 2.0 compliant
PCI Bus Interface Specification for PCI-to-CardBus Bridges
1.5-V core logic and 3.3-V I/O cells with internal voltage regulator to generate 1.5-V core VCC
Universal PC I interfaces compatible with 3.3-V and 5-V PC I signaling environments
Supports PC C ard or C ardBus with hot insertion and removal
Supports 132-MBps burst transfers to maximize data throughput on both the PC I bus and the
C ardBus
Supports serialized IRQ with PC I interrupts
Programmable multifunction terminals
Many interrupt modes supported
Serial ROM interface for loading subsystem ID and subsystem vendor ID
ExC A-compatible registers are mapped in memory or I/O space
Intel 82365SL-DF register compatible
Supports ring indicate, SUSPEND\, and PC I C LKRUN\ protocols and PC I bus Lock (LOC K)\
Provides VGA/palette memory and I/O, and subtractive decoding options, LED activity terminals
C ompliant with Intel Mobile Power Guideline 2000
Power-down features to conserve energy in battery-powered applications include: automatic
device power down during suspend
PC I power-management D0, D1, D2, and D3 power states
Advanced submicron, low-power C MOS technology
Intel is a trademark of Intel Corporation.
TI and MicroStar BGA are trademarks of Texas Instruments.
i.LINK is a trademark of Sony Corporation of America.
Memory Stick is a trademark of Sony Kabushiki Kaisha TA Sony Corporation, Japan.
Other trademarks are the property of their respective owners.
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The Texas Instruments PC I6621 controller is an integrated dual-socket UltraMedia PC C ard controller,
Smart C ard controller, and flash media controller. This high-performance integrated solution provides the
latest in PC C ard, Smart C ard, Secure Digital (SD), MultiMediaC ard (MMC ), Memory Stick/PRO,
SmartMedia, and XD technology.
The Texas Instruments PC I6421 controller is an integrated dual-socket UltraMedia PC C ard controller,
and flash media controller. This high-performance integrated solution provides the latest in PC C ard, SD,
MMC , Memory Stick/PRO, SmartMedia, and XD technology.
The Texas Instruments PC I6611 controller is an integrated single-socket UltraMedia PC C ard controller,
Smart C ard controller, and flash media controller. This high-performance integrated solution provides the
latest in PC C ard, Smart C ard, SD, MMC , Memory Stick/PRO, SmartMedia, and XD technology.
The Texas Instruments PC I6411 controller is an integrated single-socket UltraMedia PC C ard controller
and flash media controller. This high-performance integrated solution provides the latest in PC C ard, SD,
MMC , Memory Stick/PRO, SmartMedia, and XD technology.
For the remainder of this document, the PC I6x21 controller refers to the PC I6621 and PC I6421
controllers, and the PC I6x11 controller refers to the PC I6611 and PC I6411 controllers.
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