MMBT3904LT1-D - ON Semiconductor - Datasheet.Directory

General Purpose Transistor

NPN Silicon

MAXIMUM RATINGS

Rating Symbol Value Unit

Collector–Emitter Voltage VCEO 40 Vdc

Collector–Base Voltage VCBO 60 Vdc

Emitter–Base V oltage VEBO 6.0 Vdc

Collector Current — Continuous IC200 mAdc

THERMAL CHARACTERISTICS

Characteristic Symbol Max Unit

Total Device Dissipation FR–5 Board(1)

TA = 25°C

Derate above 25°C

PD225

1.8

mW/°C

Thermal Resistance Junction to Ambient RJA 556 °C/W

Total Device Dissipation

Alumina Substrate,(2) TA = 25°C

Derate above 25°C

PD300

2.4

mW/°C

Thermal Resistance Junction to Ambient RJA 417 °C/W

Junction and Storage Temperature TJ, Tstg –55 to +150 °C

DEVICE MARKING

MMBT3904LT1 = 1AM

ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)

Characteristic Symbol Min Max Unit

OFF CHARACTERISTICS

Collector–Emitter Breakdown Voltage (3)

(IC = 1.0 mAdc, IB = 0) V(BR)CEO 40 — Vdc

Collector–Base Breakdown Voltage

(IC = 10 Adc, IE = 0) V(BR)CBO 60 — Vdc

Emitter–Base Breakdown Voltage

(IE = 10 Adc, IC = 0) V(BR)EBO 6.0 — Vdc

Base Cutoff Current

(VCE = 30 Vdc, VEB = 3.0 Vdc) IBL — 50 nAdc

Collector Cutoff Current

(VCE = 30 Vdc, VEB = 3.0 Vdc) ICEX — 50 nAdc

1. FR–5 = 1.0  0.75  0.062 in.

2. Alumina = 0.4  0.3  0.024 in. 99.5% alumina.

3. Pulse Test: Pulse Width  300 s, Duty Cycle  2.0%.

Preferred devices are ON Semiconductor recommended choices for future use and best overall value.

ON Semiconductor

 Semiconductor Components Industries, LLC, 2001

November, 2001 – Rev. 3 1Publication Order Number:

MMBT3904LT1/D

MMBT3904LT1

ON Semiconductor Preferred Device

CASE 318–08, STYLE 6

SOT–23 (TO–236)

COLLECTOR

BASE

EMITTER

MMBT3904LT1

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ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) (Continued)

Characteristic Symbol Min Max Unit

ON CHARACTERISTICS(3)

DC Current Gain (1)

(IC = 0.1 mAdc, VCE = 1.0 Vdc)

(IC = 1.0 mAdc, VCE = 1.0 Vdc)

(IC = 10 mAdc, VCE = 1.0 Vdc)

(IC = 50 mAdc, VCE = 1.0 Vdc)

(IC = 100 mAdc, VCE = 1.0 Vdc)

HFE 40

100

—

300

—

Collector–Emitter Saturation Voltage (3)

(IC = 10 mAdc, IB = 1.0 mAdc)

(IC = 50 mAdc, IB = 5.0 mAdc)

VCE(sat) —

—0.2

0.3

Vdc

Base–Emitter Saturation Voltage (3)

(IC = 10 mAdc, IB = 1.0 mAdc)

(IC = 50 mAdc, IB = 5.0 mAdc)

VBE(sat) 0.65

—0.85

0.95

Vdc

SMALL–SIGNAL CHARACTERISTICS

Current–Gain — Bandwidth Product

(IC = 10 mAdc, VCE = 20 Vdc, f = 100 MHz) fT300 — MHz

Output Capacitance

(VCB = 5.0 Vdc, IE = 0, f = 1.0 MHz) Cobo — 4.0 pF

Input Capacitance

(VEB = 0.5 Vdc, IC = 0, f = 1.0 MHz) Cibo — 8.0 pF

Input Impedance

(VCE = 10 Vdc, IC = 1.0 mAdc, f = 1.0 kHz) hie 1.0 10 k ohms

Voltage Feedback Ratio

(VCE = 10 Vdc, IC = 1.0 mAdc, f = 1.0 kHz) hre 0.5 8.0 X 10–4

Small–Signal Current Gain

(VCE = 10 Vdc, IC = 1.0 mAdc, f = 1.0 kHz) hfe 100 400 —

Output Admittance

(VCE = 10 Vdc, IC = 1.0 mAdc, f = 1.0 kHz) hoe 1.0 40 mhos

Noise Figure

(VCE = 5.0 Vdc, IC = 100 Adc, RS = 1.0 k ohms, f = 1.0 kHz) NF — 5.0 dB

SWITCHING CHARACTERISTICS

Delay Time (VCC = 3.0 Vdc, VBE = –0.5 Vdc, td— 35

Rise Time

(VCC

Vdc

VBE

Vdc

IC = 10 mAdc, IB1 = 1.0 mAdc) tr— 35 ns

Storage Time (VCC = 3.0 Vdc, ts— 200

Fall Time

(VCC

Vdc

IC = 10 mAdc, IB1 = IB2 = 1.0 mAdc) tf— 50 ns

3. Pulse Test: Pulse Width  300 s, Duty Cycle  2.0%.

MMBT3904LT1

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Figure 1. Delay and Rise Time

Equivalent Test Circuit Figure 2. Storage and Fall Time

Equivalent Test Circuit

+3 V

275

10 k

1N916 CS < 4 pF*

+3 V

275

10 k

CS < 4 pF*

< 1 ns

-0.5 V

+10.9 V

300 ns

DUTY CYCLE = 2%

< 1 ns

-9.1 V′

+10.9 V

DUTY CYCLE = 2%

10 < t1 < 500 s

* Total shunt capacitance of test jig and connectors

TYPICAL TRANSIENT CHARACTERISTICS

Figure 3. Capacitance

REVERSE BIAS VOLTAGE (VOLTS)

2.0

3.0

5.0

7.0

1.0

0.1

Figure 4. Charge Data

IC, COLLECTOR CURRENT (mA)

5000

1.0

VCC = 40 V

IC/IB = 10

Q, CHARGE (pC)

3000

2000

1000

500

300

200

700

100

2.0 3.0 5.0 7.0 10 20 30 50 70 100 200

CAPACITANCE (pF)

1.0 2.0 3.0 5.0 7.0 10 20 30 40

0.2 0.3 0.5 0.7

Cibo

Cobo

TJ = 25°C

TJ = 125°C

MMBT3904LT1

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Figure 5. Turn–On Time

IC, COLLECTOR CURRENT (mA)

100

200

300

500

Figure 6. Rise Time

IC, COLLECTOR CURRENT (mA)

TIME (ns)

1.0 2.0 3.0 10 20 70

5100

t , RISE TIME (ns)

Figure 7. Storage Time

IC, COLLECTOR CURRENT (mA)

Figure 8. Fall Time

IC, COLLECTOR CURRENT (mA)

5.0 7.0 30 50 200

100

200

300

500

1.0 2.0 3.0 10 20 70

5100

5.0 7.0 30 50 200

100

200

300

500

1.0 2.0 3.0 10 20 70

5100

5.0 7.0 30 50 200

100

200

300

500

1.0 2.0 3.0 10 20 70

5100

5.0 7.0 30 50 200

t , FALL TIME (ns)

t , STORAGE TIME (ns)

′

VCC = 40 V

IC/IB = 10

VCC = 40 V

IB1 = IB2

IC/IB = 20

IC/IB = 10

tr @ VCC = 3.0 V

td @ VOB = 0 V

40 V

15 V

2.0 V

IC/IB = 10

IC/IB = 20

IC/IB = 10

IC/IB = 20

t′s = ts - 1/8 tf

IB1 = IB2

TYPICAL AUDIO SMALL–SIGNAL CHARACTERISTICS

NOISE FIGURE VARIATIONS

(VCE = 5.0 Vdc, TA = 25°C, Bandwidth = 1.0 Hz)

Figure 9.

f, FREQUENCY (kHz)

0.1

Figure 10.

RS, SOURCE RESISTANCE (k OHMS)

NF, NOISE FIGURE (dB)

1.0 2.0 4.0 10 20 40

0.2 0.4

0100

0.1 1.0 2.0 4.0 10 20 40

0.2 0.4 100

NF, NOISE FIGURE (dB)

f = 1.0 kHz IC = 1.0 mA

IC = 0.5 mA

IC = 50 A

IC = 100 A

SOURCE RESISTANCE = 200 

IC = 1.0 mA

SOURCE RESISTANCE = 200 

IC = 0.5 mA

SOURCE RESISTANCE = 500 

IC = 100 A

SOURCE RESISTANCE = 1.0 k

IC = 50 A

MMBT3904LT1

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h PARAMETERS

(VCE = 10 Vdc, f = 1.0 kHz, TA = 25°C)

Figure 11. Current Gain

IC, COLLECTOR CURRENT (mA)

100

200

300

Figure 12. Output Admittance

IC, COLLECTOR CURRENT (mA)

h , CURRENT GAIN

h , OUTPUT ADMITTANCE ( mhos)

Figure 13. Input Impedance

IC, COLLECTOR CURRENT (mA)

Figure 14. Voltage Feedback Ratio

IC, COLLECTOR CURRENT (mA)

100

2.0

3.0

5.0

7.0

1.0

0.1 0.2 1.0 2.0 5.0

0.5 10

0.3 0.5 3.0

0.7

2.0

5.0

1.0

0.2

0.5

h , VOLTAGE FEEDBACK RATIO (X 10 )

h , INPUT IMPEDANCE (k OHMS)

0.1 0.2 1.0 2.0 5.0 10

0.3 0.5 3.0

0.1 0.2 1.0 2.0 5.0 10

0.3 0.5 3.0

0.1 0.2 1.0 2.0 5.0 10

0.3 0.5 3.0



-4

TYPICAL STATIC CHARACTERISTICS

Figure 15. DC Current Gain

IC, COLLECTOR CURRENT (mA)

0.3

0.5

0.7

1.0

2.0

0.2

0.1

h , DC CURRENT GAIN (NORMALIZED)

0.5 2.0 3.0 10 50 70

0.2 0.3

0.1 100

1.00.7 200

30205.0 7.0

VCE = 1.0 V

TJ = +125°C

+25°C

-55°C

MMBT3904LT1

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Figure 16. Collector Saturation Region

IB, BASE CURRENT (mA)

0.4

0.6

0.8

1.0

0.2

0.1

V , COLLECTOR EMITTER VOLTAGE (VOLTS)

0.5 2.0 3.0 100.2 0.3

01.00.7 5.0 7.0

IC = 1.0 mA

TJ = 25°C

0.070.050.030.020.01

10 mA 30 mA 100 mA

Figure 17. “ON” Voltages

IC, COLLECTOR CURRENT (mA)

0.4

0.6

0.8

1.0

1.2

0.2

Figure 18. Temperature Coefficients

IC, COLLECTOR CURRENT (mA)

V, VOLTAGE (VOLTS)

1.0 2.0 5.0 10 20 50

0100

-0.5

0.5

1.0

0 60 80 120 140 160 180

20 40 100

COEFFICIENT (mV/ C)

200

-1.0

-1.5

-2.0

200

TJ = 25°C

VBE(sat) @ IC/IB =10

VCE(sat) @ IC/IB =10

VBE @ VCE =1.0 V

+25°C TO +125°C

-55°C TO +25°C

+25°C TO +125°C

-55°C TO +25°C

VC FOR VCE(sat)

VB FOR VBE(sat)

MMBT3904LT1

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The values for the equation are found in the maximum

ratings table on the data sheet. Substituting these values

into the equation for an ambient temperature TA of 25°C,

one can calculate the power dissipation of the device which

in this case is 225 milliwatts.

INFORMATION FOR USING THE SOT–23 SURFACE MOUNT PACKAGE

MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS

Surface mount board layout is a critical portion of the

total design. The footprint for the semiconductor packages

must be the correct size to insure proper solder connection

interface between the board and the package. With the

correct pad geometry, the packages will self align when

subjected to a solder reflow process.

SOT–23

inches

0.037

0.95

0.037

0.95

0.079

2.0

0.035

0.9

0.031

0.8

SOT–23 POWER DISSIPATION

PD = TJ(max) – TA

RθJA

PD = 150°C – 25°C

556°C/W = 225 milliwatts

The power dissipation of the SOT–23 is a function of the

pad size. This can vary from the minimum pad size for

soldering to a pad size given for maximum power dissipa-

tion. Power dissipation for a surface mount device is deter-

mined b y T J(max), the maximum rated junction temperature

of the die, RθJA, the thermal resistance from the device

junction to ambient, and the operating temperature, TA.

Using the values provided on the data sheet for the SOT–23

package, PD can be calculated as follows:

The 556°C/W for the SOT–23 package assumes the use

of the recommended footprint on a glass epoxy printed

circuit board to achieve a power dissipation of 225 milli-

watts. There are other alternatives to achieving higher

power dissipation from the SOT–23 package. Another

alternative would be to use a ceramic substrate or an

aluminum core board such as Thermal Clad. Using a

board material such as Thermal Clad, an aluminum core

board, the power dissipation can be doubled using the same

footprint.

SOLDERING PRECAUTIONS

The melting temperature of solder is higher than the

rated temperature of the device. When the entire device is

heated to a high temperature, failure to complete soldering

within a short time could result in device failure. There-

fore, the following items should always be observed in

order to minimize the thermal stress to which the devices

are subjected.

•Always preheat the device.

•The delta temperature between the preheat and

soldering should be 100°C or less.*

•When preheating and soldering, the temperature of the

leads and the case must not exceed the maximum

temperature ratings as shown on the data sheet. When

using infrared heating with the reflow soldering

method, the difference shall be a maximum of 10°C.

•The soldering temperature and time shall not exceed

260°C for more than 10 seconds.

•When shifting from preheating to soldering, the

maximum temperature gradient shall be 5°C or less.

•After soldering has been completed, the device should

be allowed to cool naturally for at least three minutes.

Gradual cooling should be used as the use of forced

cooling will increase the temperature gradient and

result in latent failure due to mechanical stress.

•Mechanical stress or shock should not be applied

during cooling.

* Soldering a device without preheating can cause exces-

sive thermal shock and stress which can result in damage

to the device.

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PACKAGE DIMENSIONS

CASE 318–08

ISSUE AF

SOT–23 (TO–236)

DIM

MIN MAX MIN MAX

MILLIMETERS

0.1102 0.1197 2.80 3.04

INCHES

B0.0472 0.0551 1.20 1.40

C0.0350 0.0440 0.89 1.11

D0.0150 0.0200 0.37 0.50

G0.0701 0.0807 1.78 2.04

H0.0005 0.0040 0.013 0.100

J0.0034 0.0070 0.085 0.177

K0.0140 0.0285 0.35 0.69

L0.0350 0.0401 0.89 1.02

S0.0830 0.1039 2.10 2.64

V0.0177 0.0236 0.45 0.60

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. MAXIMUM LEAD THICKNESS INCLUDES LEAD

FINISH THICKNESS. MINIMUM LEAD THICKNESS

IS THE MINIMUM THICKNESS OF BASE

MATERIAL.

STYLE 6:

PIN 1. BASE

2. EMITTER

3. COLLECTOR

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