DALLAS SEMICONDUCTOR CORP OFE D B 2.34130 OO0e4kb i i ~ T-46-35 iS Dallas Semiconductor Electronic Key DS1204U FEATURES . PIN CONNECTIONS * Cannot be deciphered by reverse engineering Partitloned memory thwarts pirating User insertable packaging allows per- sonal possession Exclusive blank keys on request Appropriate identification can be made with a 64 bit reprogrammable memory Unreadable 64 bit security match code virtually prevents deciphering by exhaus- tlve search with over 1012 possibilities 128 bits of secure read/write memory | creates additional barriers against hackers by permitting data changes as often as needed * Rapid erasure of identification security match code, and secure read/write mem- ory can occur if tampering is detected PIN NAMES : Pint Vcc +5VOLTS e User insertable - s Pin2RST RESET Over 10 years of data retention with no Pin 3 DQ DATA INPUTIOUTPUT limitations or restrictions on write cycle Pind CLK CLOCK Low power CMOS circuitry Pin5 GND GROUND 4 million bits/second data rate rm Durable and rugged Applications Include software authoriza- tlon, gray market software protection, proprietary data, financial transactions, secure personnel areas, and system ac- cess control DESCRIPTION The DS1204U Electronic Key is a miniature security system which stores 64 bits of user de- finable identification code and a 64 bit security match code which protects 128 bits of read/ write nonvolatile memory. The 64-bit identification code and the security match code are pro- grammed into the key via a special program mode operation. After programming, the key follows a special procedure with a serial format to retrieve or update data. 431DALLAS SEMICONDUCTOR CORP OFE D B aciyi30 OOOe4b? 3 i T-46-35 Interface cost to a microprocessor is minimized by on-chip circuitry which permits data transfer with only three signals: CLOCK, RESET, and DATA INPUT/OUTPUT. Low pin count and a guided entry for a mating receptacle overcomes mechanical problems normally encountered with conventional integrated circuit packaging, making the device transportable and user insertable. OPERATIONNORMAL MODE The Electronic Key has two modes of operation: the normal mode and the program mode. The block diagram (Figure 1) illustrates the main elements of the key when used in the nor- mal mode. To initiate data transfer with the key, RST is taken high and 24 bits are loaded into the command register on each low to high transition of the CLK input. The command register must match the exact bit pattern which defines normai operation for read or write or communi- cations is ignored. If the command register is loaded properly, communications are allowed to continue. The next 64 cycles to the key are read. Data is clocked out of the key on the high to low transition of the clock from the identification memory. Next, 64 write cycles must be written to the compare register. These 64 bits must match the exact pattern stored in the security match memory. If a match is not found, access to additional information is denied. instead, random data is output for the next 128 cycles when reading data. If write cycles are being executed, the write cycles are ignored. If a match is found, access is permitted to a 128-bit read/write nonvolatile memory. Figure 2 is a summary of normal mode operation and Figure 3 is a flow chart of the normal mode sequence. BLOCK DIAGRAM NORMAL MODE Figure 1 bIQ < 64 Bit Identification Control CLK Logic - A. __ - 64 Bit RST Security Match Nast Compare Register 428 Bit as Secure Memory Command Reglster JAN a - v Random Data 432 pailwait DALLAS SEMICONDUCTOR CORP OFE D B eui4i30 O0024b8 i T~46~35 SEQUENCE NORMAL MODE Figure 2 Protocol. Identification Security Match Command Word 64 Read Cycles i 64 Write Cycles Match Secure Memory >| 128 Reads or Writes FLOW CHART NORMAL MODE Figure 3 , >( RESET High ) NO Match for Read or Write | Read 64 Bits | Identification Write 64 Bits Security Match Output Garbled Data Read or Write Se N 128 Bits Based cure N.V. RAM on Protocol Output in High Z 433DALLAS SEMICONDUCTOR CORP QE D B o2.14130 Oo02449 24 T-46-35 PROGRAM MODE The block diagram of Figure 4 illustrates the main elements of the key when used in the program mode. To initiate the program mode, RST is driven high and 24 bits are loaded into the command register on each low to high transition of the CLK input. The command register must match the exact pattern which defines program operation. If an exact match is not found, the remainder of the program cycle is ignored. If the command register is properly loaded, then the next 128 bits which follow are written to the identification memory and the security match memory. Figure 5 is a summary of program mode operation and Figure 6 is a flow chart of program mode operation. , BLOCK DIAGRAM PROGRAM MODE Figure 4 op/IQ < Control 64 Bit K - Identification Logic CLK a a 4 -_- ee ren 64 Bil security Match i Command Register SEQUENCE PROGRAM MODE Figure 5 Protocol Identification Security Match Command Word 64 Write Cycles 64 Write CyclesDALLAS SEMICONDUCTOR CORP OSE D B e..4u130 OOO0e2470 3 i T-46~35 FLOW CHART PROGRAM MODE Figure 6 RESET High Write Command Protocol Match Program Mode Write 64 Bits identification Write 64 Bits Security Match RESET Low Output in High Z COMMAND WORD Each data transfer for the normal and program mode begins with a three byte command word as shown in Figure 7. As defined, the first byte of the command word specifies whether the 128 bit nonvolatile memory will be written into or read. If any one of the bits of the first byte of the command word fails to meet the exact pattern of read or write, the data transfer will be aborted. The 8 bit pattern for read is 01100010. The pattern for write is 10011101. The first two bits of the second byte of the command word specify whether the data transfer to follow is a pro- gram or normal cycle. The bit pattern for program is 0 in bit 0 and 1 in bit 1. The program mode can be selected only when the first byte of the command word specifies a write. If the program mode is specified and the first byte of the command word does not specify a write, data transfer will be aborted. The bit pattern which selects the normal mode of operation is 1 in bit 0 and 0 in bit 1. The other two possible combinations for the first two bits of byte 2 will cause data transfer to abort. The remaining 6 bits of byte 2 and the first 7 bits of byte 3 form unique patterns which allow multiple keys to reside on a common bus. As such, each respective code pattern must be written exactly for a given device or data transfer will abort. Dallas Semiconductor has 5 pat- terns available as standard products per the chart in Figure 7. Each pattern cerresponds toa specific part number. Under special contract with Dallas Semiconductor the user may specify any bit pattern other than that specified by Dallas Semiconductor as unavailable. The bit pattern as defined by the user must be written exactly or data transfer will abort. The last bit of byte 3 of the command word must be written to logic 1 or data transfer will abort. NOTE: Contact Dallas Semiconductor Sales Office for special command word code assignment which makes possible an exclusive blank key. 435 ahwe oe DALLAS SEMICONDUCTOR CoRP O9E D ff 2624130 Oooayr1 5 i T-46-35 COMMAND WORD Figure 7 Oo A ewi wl* wl R R wi wht Byte X X 4 P P Mm Byte2 23 1 X X X X Byte3 DS1204U-1 0 0 0 P P Byte 2 1 0 0 ) 0 Byte 3 DS1204U-2 0 0 0 P P Byte 2 1 0 0 0 0 Byte 3 DS1204U-3 0 0 1 P P Byte 2 1 0 0 0 0 Byte 3 DS1204U-4 0 0 1 Pp P Byte 2 1 0 0 0 0 Byte-3 DS1204U-5 4) 1 0 P P Byte 2 1 0 0 0 0 Byte 3 436 wailDALLAS SEMICONDUCTOR CORP OFE D B ec.yi30 O00e47?2 7 i T-46-35 RESET AND CLOCK CONTROL ___ _ All data transfers are initiated by driving the RST input high. The RST input serves three func- tions. First, it turns on control logic which allows access to the command register for the command sequence. Second, the RST signal provides a power source for the cycle to follow. To meet this requirement, a drive source for RST of 2mA @ 3.0 volts is required. However, if the Voc pin is connected to a 5 volt source within nominal limits, then RST is not used as a source of power and input levels revert to normal VjH and ViL inputs with a drive current re- quirement of 500 uA. Third, the RST signal provides a method of terminating data transfer. A clock cycle is a sequence of a falling edge followed by a rising edge. For data inputs, the data must be valid during the rising edge of a clock cycle. Command bits and data bits are in- put on the rising edge of the clock _and data bits are output on the falling edge of the clock. All data transfer terminates if the RST pin is low and the DQ pin goes to a high impedance state. When data transfer to the key is terminated and using RST, the transition of RESET must occur while the clock is at high level to avoid disturbing the last bit of data. Data transfer Is illustrated in Figure 8 for normal mode and Figure 9 for program mode. KEY CONNECTIONS The key is designed to be plugged into a standard 5 pin 0.1 inch center SIP receptacle. A. guide is provided to prevent the key from being plugged in backwards and aid in alignment of the receptacle. For portable applications, contact to the key pins can be determined to in- sure connection integrity before data transfer begins. CLK, RST, and DATA INPUT/OUTPUT all have internal 20K Ohm pull down resistors to ground which can be sensed by a reading device. 437 watwad DALLAS SEMICONDUCTOR CORP QFE D B e.1.4130 Goge473 4 i T-46-35 DATA TRANSFER NORMAL MODE Figure 8 | | | | | | | | | | J | | | | LJ | [| | L; CLOCK . - >) Js} XL CC (4 U - | . Soon | aeSET 1 )) 23 7 : -)) ) CC CC (<4 we rm RW b ) 1 | DO pes | ao a63 pao { pai2ze | pata? $ 1 _ 2 \ commano /- READ _/\ WRITE I READ/WRITE WORD 64 BITS 64 BITS 428 BITS DATA TRANSFER PROGRAM MODE Figure 9 af LLY UU ULL 2 - 3. t CC RESET te % v2 ~< rw] rw | 1! | ao | at | y) | ae2 | aes | ao | at | | 62 | Qs3 _ CC Vs {( \ commano / \._ wate. writ 2 WORD 64 BITS 64 BITSDALLAS SEMICONDUCTOR CORP OTE D B 2ciui30 oo0e474 O i T-46-35 ABSOLUTE MAXIMUM RATINGS VOLTAGE ON ANY PIN RELATIVE TO GROUND -1.0Vto +7V OPERATING TEMPERATURE 7" 0C to 70C STORAGE TEMPERATURE -40Cto +70C This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implled. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. RECOMMENDED D.C. OPERATING CONDITIONS (0C to 70C) PARAMETER SYMBOL MIN TYP MAX UNITS | NOTES Logic 1 VIH 2.0 . Vv 1,8,10 Logic 0 VIL -0.3 +0.8 Vv 1 RESET Logic 1 VIHE 3.0 V 1,9,11 Supply Vcc 4.5 5.0 5.5 Vv 1 D.C. ELECTRICAL CHARACTERISTICS (0C to 70C, Voc = SV + 10%) PARAMETER SYMBOL MIN TYP. MAX UNITS NOTES Input Leakage NIL +500 LA 4 Output Leakage ILO +500 uA Output Current @ 2.4V} loH -1 mA Output Current @ 0.4V lot +2 mA RST Input Resistance | Zpst 10 40 Ka D/Q Input Resistance ZDQ 10 40 KQ CLK Input Resistance | ZcLk 10 40 KO RST Current @3.0V IRST 2 mA 6,9,13 Active Current Ioc1 6 mA 6 Standby Current Icc2 2.5 mA 6 439yatemeretes DALLAS SEMICONDUCTOR CORP ose p Bf 2614130 cooau7s 2 T-46-35 CAPACITANCE (ta = 25C) PARAMETER SYMBOL MAX UNITS NOTES Input Capacitance CIN 5 pF Output Capacitance CouUT 7 pF A.C. ELECTRICAL CHARACTERISTICS (0C to 70C, Voc = SV + 10%) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Data To CLK Setup toc 35 ns 2,7 CLK to Data Hold tCDH 40 ns 2,7 CLK to Data Delay tCDD 100 ns 2,3,5,7 CLK Low Time tCL 125 ns 2,7 CLK High Time tCH 125 ns 2,7 CLK Frequency fCLK D.C. 4.0 MHZ 2,7 CLK Rise & Fall tp, te 500 ns 2,7 RST To CLK Set Up tcc 1 us 2,7 CLK To RST Hold tCCH 40 ns 2,7 RST Inactive Time tCWH 125 ns 2,7,14 RST To I/O High Z tcpz 50 ns 2,7 TIMING DIAGRAM WRITE DATA towH ve tt tcc CLOCK DATA INPUT/OUTPUT 440 wadDALLAS SEMICONDUCTOR CORP OSE D B 2.14130 gooa47b y i T=46~35 TIMING DIAGRAM READ DATA ON OAR WD = 10. 11. 12. 13. 14. . All voltages are referenced to GND. . Measured at VjH = 2.0 or Vi_ =.8V and 10 ns maximum rise and fall time. . Measured at VoH =2.4 volts and Vo =0.4 volts. . For CLK, D/Q, and RST de * towH F tk ate Load capacitance = 50 pF. . Measured with outputs open. . Measured at Vj} of RST 23.0Vwhen RST supplies power. . Logic 1 maximum is Vcc + 0.3 volts if the Voc pin supplies power and RST +0.3 volts if cE the RST pin supplies power. . Applies to RST when Vcc < 3.0 V. Input levels apply to CLK, DQ, and RST while Vcc is within nominal limits. When Vcc is not connected to the key, then RST input reverts to Vj HE. RST Logic 1_ maximum is Voc +0.3 volts if the Vcc pin supplies power and 5.5 volts maximum if RST supplies power. Each DS1204U is marked with a 4-digit code AABB. AA designates the year of manufac- ture. BB designates the week of manufacture. The expected tprp is defined as starting at the date of manufacture. Average A.C. RST current can be determined using the following formula: IroraL = 2 + ILoap p.c. + (4 X 10-9) (CL + 140) f Itotat and ILoap are in mA; Cis in pF; f is in MHZ. Applying the above formula, a load capacitance of 50 pF running at a frequency of 4.0 MHZ gives an ItoTa,_ of 5 MA. When RST is supplying power tCWH must be increased to 100 ms. 441 wastDALLAS SEMICONDUCTOR CORP OFE D ff 2614130 Oooay77 4 &f T-46-35 Electronic Key DS1204U XY + K INCHE 4 DIM. s MIN. MAX. A 610 630 B .740 .760 C 310 .330 D 100 110 E 515 525 F 100 110 G .100 .110 H 110 130 CV TT a ae J .030 .050 Poly ty yp typ 055 tty ot ow ola tly K 045 boob om ow ty L 045 055 Z z N M 100 110 i A >| : \- --, t Lt | cama <223 M is === Fe. j ft--sit Ge Mt 1 i L F L I | | [fs Lod $u ashDALLAS SEMICONDUCTOR CoRP O9E D ff 2414130 ono24za a i T-46-35 Key/Tag Holder DS9090 DIM. INCHES . MIN. MAX. A 670 | .690 B 790 | .810 Cc 370 390. D 290 | .310 E 410 | .430 F 070 090, = 443 wad