ID8259A - Intel - Datasheet.Directory

December 1988 Order Number: 231468-003

8259A

PROGRAMMABLE INTERRUPT CONTROLLER

(8259A/8259A-2)

Y8086, 8088 Compatible

YMCS-80, MCS-85 Compatible

YEight-Level Priority Controller

YExpandable to 64 Levels

YProgrammable Interrupt Modes

YIndividual Request Mask Capability

YSingle a5V Supply (No Clocks)

YAvailable in 28-Pin DIP and 28-Lead

PLCC Package

(See Packaging Spec., Order Ý231369)

YAvailable in EXPRESS

Ð Standard Temperature Range

Ð Extended Temperature Range

The Intel 8259A Programmable Interrupt Controller handles up to eight vectored priority interrupts for the CPU.

It is cascadable for up to 64 vectored priority interrupts without additional circuitry. It is packaged in a 28-pin

DIP, uses NMOS technology and requires a single a5V supply. Circuitry is static, requiring no clock input.

The 8259A is designed to minimize the software and real time overhead in handling multi-level priority inter-

rupts. It has several modes, permitting optimization for a variety of system requirements.

The 8259A is fully upward compatible with the Intel 8259. Software originally written for the 8259 will operate

the 8259A in all 8259 equivalent modes (MCS-80/85, Non-Buffered, Edge Triggered).

231468–1

Figure 1. Block Diagram

DIP

231468–2

PLCC

231468–31

Figure 2. Pin

Configurations

8259A

Table 1. Pin Description

Symbol Pin No. Type Name and Function

VCC 28 I SUPPLY: a5V Supply.

GND 14 I GROUND

CS 1ICHIP SELECT: A low on this pin enables RD and WR communication

between the CPU and the 8259A. INTA functions are independent of

CS.

WR 2IWRITE: A low on this pin when CS is low enables the 8259A to accept

command words from the CPU.

RD 3IREAD: A low on this pin when CS is low enables the 8259A to release

status onto the data bus for the CPU.

D7–D04–11 I/O BIDIRECTIONAL DATA BUS: Control, status and interrupt-vector

information is transferred via this bus.

CAS0–CAS212, 13, 15 I/O CASCADE LINES: The CAS lines form a private 8259A bus to control

a multiple 8259A structure. These pins are outputs for a master 8259A

and inputs for a slave 8259A.

SP/EN 16 I/O SLAVE PROGRAM/ENABLE BUFFER: This is a dual function pin.

When in the Buffered Mode it can be used as an output to control

buffer transceivers (EN). When not in the buffered mode it is used as

an input to designate a master (SP e1) or slave (SP e0).

INT 17 O INTERRUPT: This pin goes high whenever a valid interrupt request is

asserted. It is used to interrupt the CPU, thus it is connected to the

CPU’s interrupt pin.

IR0–IR718–25 I INTERRUPT REQUESTS: Asynchronous inputs. An interrupt request

is executed by raising an IR input (low to high), and holding it high until

it is acknowledged (Edge Triggered Mode), or just by a high level on an

IR input (Level Triggered Mode).

INTA 26 I INTERRUPT ACKNOWLEDGE: This pin is used to enable 8259A

interrupt-vector data onto the data bus by a sequence of interrupt

acknowledge pulses issued by the CPU.

A027 I AO ADDRESS LINE: This pin acts in conjunction with the CS,WR, and

RD pins. It is used by the 8259A to decipher various Command Words

the CPU writes and status the CPU wishes to read. It is typically

connected to the CPU A0 address line (A1 for 8086, 8088).

8259A

FUNCTIONAL DESCRIPTION

Interrupts in Microcomputer Systems

Microcomputer system design requires that I.O de-

vices such as keyboards, displays, sensors and oth-

er components receive servicing in a an efficient

manner so that large amounts of the total system

tasks can be assumed by the microcomputer with

little or no effect on throughput.

The most common method of servicing such devic-

es is the

Polled

approach. This is where the proces-

sor must test each device in sequence and in effect

‘‘ask’’ each one if it needs servicing. It is easy to see

that a large portion of the main program is looping

through this continuous polling cycle and that such a

method would have a serious detrimental effect on

system throughput, thus limiting the tasks that could

be assumed by the microcomputer and reducing the

cost effectiveness of using such devices.

A more desirable method would be one that would

allow the microprocessor to be executing its main

program and only stop to service peripheral devices

when it is told to do so by the device itself. In effect,

the method would provide an external asynchronous

input that would inform the processor that it should

complete whatever instruction that is currently being

executed and fetch a new routine that will service

the requesting device. Once this servicing is com-

plete, however, the processor would resume exactly

where it left off.

This method is called

Interrupt

. It is easy to see that

system throughput would drastically increase, and

thus more tasks could be assumed by the micro-

computer to further enhance its cost effectiveness.

The Programmable Interrupt Controller (PIC) func-

tions as an overall manager in an Interrupt-Driven

system environment. It accepts requests from the

peripheral equipment, determines which of the in-

coming requests is of the highest importance (priori-

ty), ascertains whether the incoming request has a

higher priority value than the level currently being

serviced, and issues an interrupt to the CPU based

on this determination.

Each peripheral device or structure usually has a

special program or ‘‘routine’’ that is associated with

its specific functional or operational requirements;

this is referred to as a ‘‘service routine’’. The PIC,

after issuing an Interrupt to the CPU, must somehow

input information into the CPU that can ‘‘point’’ the

Program Counter to the service routine associated

with the requesting device. This ‘‘pointer’’ is an ad-

dress in a vectoring table and will often be referred

to, in this document, as vectoring data.

231468–3

Figure 3a. Polled Method

231468–4

Figure 3b. Interrupt Method

8259A

The 8259A is a device specifically designed for use

in real time, interrupt driven microcomputer systems.

It manages eight levels or requests and has built-in

features for expandability to other 8259A’s (up to 64

levels). It is programmed by the system’s software

as an I/O peripheral. A selection of priority modes is

available to the programmer so that the manner in

which the requests are processed by the 8259A can

be configured to match his system requirements.

The priority modes can be changed or reconfigured

dynamically at any time during the main program.

This means that the complete interrupt structure can

be defined as required, based on the total system

environment.

INTERRUPT REQUEST REGISTER (IRR) AND

IN-SERVICE REGISTER (ISR)

The interrupts at the IR input lines are handled by

two registers in cascade, the Interrupt Request Reg-

ister (IRR) and the In-Service (ISR). The IRR is used

to store all the interrupt levels which are requesting

service; and the ISR is used to store all the interrupt

levels which are being serviced.

PRIORITY RESOLVER

This logic block determines the priorites of the bits

set in the IRR. The highest priority is selected and

strobed into the corresponding bit of the ISR during

INTA pulse.

INTERRUPT MASK REGISTER (IMR)

The IMR stores the bits which mask the interrupt

lines to be masked. The IMR operates on the IRR.

Masking of a higher priority input will not affect the

interrupt request lines of lower quality.

INT (INTERRUPT)

This output goes directly to the CPU interrupt input.

The VOH level on this line is designed to be fully

compatible with the 8080A, 8085A and 8086 input

levels.

INTA (INTERRUPT ACKNOWLEDGE)

INTA pulses will cause the 8259A to release vector-

ing information onto the data bus. The format of this

data depends on the system mode (mPM) of the

8259A.

DATA BUS BUFFER

This 3-state, bidirectional 8-bit buffer is used to inter-

face the 8259A to the system Data Bus. Control

words and status information are transferred

through the Data Bus Buffer.

READ/WRITE CONTROL LOGIC

The function of this block is to accept OUTput com-

mands from the CPU. It contains the Initialization

Command Word (ICW) registers and Operation

Command Word (OCW) registers which store the

various control formats for device operation. This

function block also allows the status of the 8259A to

be transferred onto the Data Bus.

CS (CHIP SELECT)

A LOW on this input enables the 8259A. No reading

or writing of the chip will occur unless the device is

selected.

WR (WRITE)

A LOW on this input enables the CPU to write con-

trol words (ICWs and OCWs) to the 8259A.

RD (READ)

A LOW on this input enables the 8259A to send the

status of the Interrupt Request Register (IRR), In

Service Register (ISR), the Interrupt Mask Register

(IMR), or the Interrupt level onto the Data Bus.

This input signal is used in conjunction with WR and

RD signals to write commands into the various com-

mand registers, as well as reading the various status

registers of the chip. This line can be tied directly to

one of the address lines.

8259A

231468–5

Figure 4a. 8259A Block Diagram

8259A

231468–6

Figure 4b. 8259A Block Diagram

8259A

THE CASCADE BUFFER/COMPARATOR

This function block stores and compares the IDs of

all 8259A’s used in the system. The associated

three I/O pins (CAS0-2) are outputs when the 8259A

is used as a master and are inputs when the 8259A

is used as a slave. As a master, the 8259A sends

the ID of the interrupting slave device onto the

CAS0– 2 lines. The slave thus selected will send its

preprogrammed subroutine address onto the Data

Bus during the next one or two consecutive INTA

pulses. (See section ‘‘Cascading the 8259A’’.)

INTERRUPT SEQUENCE

The powerful features of the 8259A in a microcom-

puter system are its programmability and the inter-

rupt routine addressing capability. The latter allows

direct or indirect jumping to the specific interrupt rou-

tine requested without any polling of the interrupting

devices. The normal sequence of events during an

interrupt depends on the type of CPU being used.

The events occur as follows in an MCS-80/85 sys-

tem:

1. One or more of the INTERRUPT REQUEST lines

(IR7– 0) are raised high, setting the correspond-

ing IRR bit(s).

2. The 8259A evaluates these requests, and sends

an INT to the CPU, if appropriate.

3. The CPU acknowledges the INT and responds

with an INTA pulse.

4. Upon receiving an INTA from the CPU group, the

highest priority ISR bit is set, and the correspond-

ing IRR bit is reset. The 8259A will also release a

CALL instruction code (11001101) onto the 8-bit

Data Bus through its D7– 0 pins.

5. This CALL instruction will initiate two more INTA

pulses to be sent to the 8259A from the CPU

group.

6. These two INTA pulses allow the 8259A to re-

lease its preprogrammed subroutine address

onto the Data Bus. The lower 8-bit address is re-

leased at the first INTA pulse and the higher 8-bit

address is released at the second INTA pulse.

7. This completes the 3-byte CALL instruction re-

leased by the 8259A. In the AEOI mode the ISR

bit is reset at the end of the third INTA pulse.

Otherwise, the ISR bit remains set until an appro-

priate EOI command is issued at the end of the

interrupt sequence.

The events occuring in an 8086 system are the

same until step 4.

4. Upon receiving an INTA from the CPU group, the

highest priority ISR bit is set and the correspond-

ing IRR bit is reset. The 8259A does not drive the

Data Bus during this cycle.

5. The 8086 will initiate a second INTA pulse. Dur-

ing this pulse, the 8259A releases an 8-bit pointer

onto the Data Bus where it is read by the CPU.

6. This completes the interrupt cycle. In the AEOI

mode the ISR bit is reset at the end of the sec-

ond INTA pulse. Otherwise, the ISR bit remains

set until an appropriate EOI command is issued

at the end of the interrupt subroutine.

If no interrupt request is present at step 4 of either

sequence (i.e., the request was too short in duration)

the 8259A will issue an interrupt level 7. Both the

vectoring bytes and the CAS lines will look like an

interrupt level 7 was requested.

When the 8259A PIC receives an interrupt, INT be-

comes active and an interrupt acknowledge cycle is

started. If a higher priority interrupt occurs between

the two INTA pulses, the INT line goes inactive im-

mediately after the second INTA pulse. After an un-

specified amount of time the INT line is activated

again to signify the higher priority interrupt waiting

for service. This inactive time is not specified and

can vary between parts. The designer should be

aware of this consideration when designing a sys-

tem which uses the 8259A. It is recommended that

proper asynchronous design techniques be fol-

lowed.

8259A

231468–7

Figure 4c. 8259A Block Diagram

231468–8

Figure 5. 8259A Interface to

Standard System Bus

INTERRUPT SEQUENCE OUTPUTS

MCS-80, MCS-85

This sequence is timed by three INTA pulses. During

the first INTA pulse the CALL opcode is enabled

onto the data bus.

Content of First Interrupt Vector Byte

D7 D6 D5 D4 D3 D2 D1 D0

CALL CODE 1 1 0 0 1 1 0 1

During the second INTA pulse the lower address of

the appropriate service routine is enabled onto the

data bus. When Interval e4 bits A5–A7are pro-

grammed, while A0–A4are automatically inserted by

the 8259A. When Interval e8 only A6and A7are

programmed, while A0–A5are automatically insert-

ed.

8259A

Content of Second Interrupt Vector Byte

IR Interval e4

D7 D6 D5 D4 D3 D2 D1 D0

7A7A6A511100

6A7A6A511000

5A7A6A510100

4A7A6A510000

3A7A6A501100

2A7A6A501000

1A7A6A500100

0A7A6A500000

IR Interval e8

D7 D6 D5 D4 D3 D2 D1 D0

7A7A6111000

6A7A6110000

5A7A6101000

4A7A6100000

3A7A6011000

2A7A6010000

1A7A6001000

0A7A6000000

During the third INTA pulse the higher address of the

appropriate service routine, which was programmed

as byte 2 of the initialization sequence (A8–A15), is

enabled onto the bus.

Content of Third Interrupt Vector Byte

D7 D6 D5 D4 D3 D2 D1 D0

A15 A14 A13 A12 A11 A10 A9 A8

8086, 8088

8086 mode is similar to MCS-80 mode except that

only two Interrupt Acknowledge cycles are issued by

the processor and no CALL opcode is sent to the

processor. The first interrupt acknowledge cycle is

similar to that of MCS-80, 85 systems in that the

8259A uses it to internally freeze the state of the

interrupts for priority resolution and as a master it

issues the interrupt code on the cascade lines at the

end of the INTA pulse. On this first cycle it does not

issue any data to the processor and leaves its data

bus buffers disabled. On the second interrupt ac-

knowledge cycle in 8086 mode the master (or slave

if so programmed) will send a byte of data to the

processor with the acknowledged interrupt code

composed as follows (note the state of the ADI

mode control is ignored and A5–A11 are unused in

8086 mode):

Content of Interrupt Vector Byte

for 8086 System Mode

D7 D6 D5 D4 D3 D2 D1 D0

IR7 T7 T6 T5 T4 T3 1 1 1

IR6 T7 T6 T5 T4 T3 1 1 0

IR5 T7 T6 T5 T4 T3 1 0 1

IR4 T7 T6 T5 T4 T3 1 0 0

IR3 T7 T6 T5 T4 T3 0 1 1

IR2 T7 T6 T5 T4 T3 0 1 0

IR1 T7 T6 T5 T4 T3 0 0 1

IR0 T7 T6 T5 T4 T3 0 0 0

PROGRAMMING THE 8259A

The 8259A accepts two types of command words

generated by the CPU:

Initialization Command Words (ICWs):

Before

normal operation can begin, each 8259A in the

system must be brought to a starting pointÐby a

sequence of 2 to 4 bytes timed by WR pulses.

Operation Command Words (OCWs):

These are

the command words which command the 8259A

to operate in various interrupt modes. These

modes are:

a. Fully nested mode

b. Rotating priority mode

c. Special mask mode

d. Polled mode

The OCWs can be written into the 8259A anytime

after initialization.

INITIALIZATION COMMAND WORDS

(ICWS)

General

Whenever a command is issued with A0 e0 and D4

e1, this is interpreted as Initialization Command

Word 1 (ICW1). ICW1 starts the intiitalization se-

quence during which the following automatically oc-

cur.

a. The edge sense circuit is reset, which means that

following initialization, an interrupt request (IR) in-

put must make a low-to-high transistion to gener-

ate an interrupt.

8259A

b. The Interrupt Mask Register is cleared.

c. IR7 input is assigned priority 7.

d. The slave mode address is set to 7.

e. Special Mask Mode is cleared and Status Read is

set to IRR.

f. If IC4 e0, then all functions selected in ICW4

are set to zero. (Non-Buffered mode*, no Auto-

EOI, MCS-80, 85 system).

*NOTE:

Master/Slave in ICW4 is only used in the buffered

mode.

Initialization Command Words 1 and 2

(ICW1, ICW2)

A5–A15:

Page starting address of service routines

In an MCS 80/85 system, the 8 request levels will

generate CALLs to 8 locations equally spaced in

memory. These can be programmed to be spaced at

intervals of 4 or 8 memory locations, thus the 8 rou-

tines will occupy a page of 32 or 64 bytes, respec-

tively.

The address format is 2 bytes long (A0–A15). When

the routine interval is 4, A0–A4are automatically in-

serted by the 8259A, while A5–A15 are programmed

externally. When the routine interval is 8, A0–A5are

automatically inserted by the 8259A, while A6–A15

are programmed externally.

The 8-byte interval will maintain compatibility with

current software, while the 4-byte interval is best for

a compact jump table.

In an 8086 system A15–A11 are inserted in the five

most significant bits of the vectoring byte and the

8259A sets the three least significant bits according

to the interrupt level. A10–A5are ignored and ADI

(Address interval) has no effect.

LTIM: If LTIM e1, then the 8259A will operate in

the level interrupt mode. Edge detect logic

on the interrupt inputs will be disabled.

ADI: CALL address interval. ADI e1 then inter-

val e4; ADI e0 then interval e8.

SNGL: Single. Means that this is the only 8259A in

the system. If SNGL e1 no ICW3 will be

issued.

IC4: If this bit is setÐICW4 has to be read. If

ICW4 is not needed, set IC4 e0.

Initialization Command Word 3 (ICW3)

This word is read only when there is more than one

8259A in the system and cascading is used, in which

case SNGL e0. It will load the 8-bit slave register.

The functions of this register are:

a. In the master mode (either when SP e1, or in

buffered mode when M/S e1 in ICW4) a ‘‘1’’ is

set for each slave in the system. The master then

will release byte 1 of the call sequence (for MCS-

80/85 system) and will enable the corresponding

slave to release bytes 2 and 3 (for 8086 only byte

2) through the cascade lines.

b. In the slave mode (either when SP e0, or if BUF

e1 and M/S e0 in ICW4) bits 2–0 identify the

slave. The slave compares its cascade input with

these bits and, if they are equal, bytes 2 and 3 of

the call sequence (or just byte 2 for 8086) are

released by it on the Data Bus.

231468–9

Figure 6. Initialization Sequence

8259A

Initialization Command Word 4 (ICW4)

SFNM: If SFNM e1 the special fully nested mode

is programmed.

BUF: If BUF e1 the buffered mode is pro-

grammed. In buffered mode SP/EN be-

comes an enable output and the master/

slave determination is by M/S.

M/S: If buffered mode is selected: M/S e1

means the 8259A is programmed to be a

master, M/S e0 means the 8259A is pro-

grammed to be a slave. If BUF e0, M/S

has no function.

AEOI: If AEOI e1 the automatic end of interrupt

mode is programmed.

mPM: Microprocessor mode: mPM e0 sets the

8259A for MCS-80, 85 system operation,

mPM e1 sets the 8259A for 8086 system

operation.

231468–10

231468–11

Figure 7. Initialization Command Word Format

8259A

231468–12

231468–13

231468–14

NOTE:

Slave ID is equal to the corresponding master IR input.

Figure 7. Initialization Command Word Format (Continued)

8259A

OPERATION COMMAND WORDS

(OCWS)

After the Initialization Command Words (ICWs) are

programmed into the 8259A, the chip is ready to ac-

cept interrupt requests at its input lines. However,

during the 8259A operation, a selection of algo-

rithms can command the 8259A to operate in vari-

ous modes through the Operation Command Words

(OCWs).

Operation Control Words (OCWs)

OCW1

A0 D7 D6 D5 D4 D3 D2 D1 D0

1 M7 M6 M5 M4M3M2M1 M0

OCW2

0 R SL EOI 0 0 L2 L1 L0

OCW3

0 0 ESMM SMM 0 1 P RR RIS

231468–15

231468–16

Figure 8. Operation Command Word Format

8259A

Operation Control Word 1 (OCW1)

OCW1 sets and clears the mask bits in the interrupt

Mask Register (IMR). M7–M0represent the eight

mask bits. M e1 indicates the channel is masked

(inhibited), M e0 indicates the channel is enabled.

Operation Control Word 2 (OCW2)

R, SL, EOIÐThese three bits control the Rotate and

End of Interrupt modes and combinations of the two.

A chart of these combinations can be found on the

Operation Command Word Format.

L2,L

ÐThese bits determine the interrupt level

acted upon when the SL bit is active.

231468–17

Figure 8. Operation Command Word Format (Continued)

8259A

Operation Control Word 3 (OCW3)

ESMMÐEnable Special Mask Mode. When this bit

is set to 1 it enables the SMM bit to set or reset the

Special Mask Mode. When ESMM e0 the SMM bit

becomes a ‘‘don’t care’’.

SMMÐSpecial Mask Mode. If ESMM e1 and SMM

e1 the 8259A will enter Special Mask Mode. If

ESMM e1 and SMM e0 the 8259A will revert to

normal mask mode. When ESMM e0, SMM has no

effect.

Fully Nested Mode

This mode is entered after initialization unless anoth-

er mode is programmed. The interrupt requests are

ordered in priority from 0 through 7 (0 highest).

When an interrupt is acknowledged the highest pri-

ority request is determined and its vector placed on

the bus. Additionally, a bit of the Interrupt Service

microprocessor issues an End of Interrupt (EOI)

command immediately before returning from the

service routine, or if AEOI (Automatic End of Inter-

rupt) bit is set, until the trailing edge of the last INTA.

While the IS bit is set, all further interrupts of the

same or lower priority are inhibited, while higher lev-

els will generate an interrupt (which will be acknowl-

edged only if the microprocessor internal Interupt

enable flip-flop has been re-enabled through soft-

ware).

After the initialization sequence, IR0 has the highest

prioirity and IR7 the lowest. Priorities can be

changed, as will be explained, in the rotating priority

mode.

End of Interrupt (EOI)

The In Service (IS) bit can be reset either automati-

cally following the trailing edge of the last in se-

quence INTA pulse (when AEOI bit in ICW1 is set) or

by a command word that must be issued to the

8259A before returning from a service routine (EOI

command). An EOI command must be issued twice

if in the Cascade mode, once for the master and

once for the corresponding slave.

There are two forms of EOI command: Specific and

Non-Specific. When the 8259A is operated in modes

which perserve the fully nested structure, it can de-

termine which IS bit to reset on EOI. When a Non-

Specific EOI command is issued the 8259A will auto-

matically reset the highest IS bit of those that are

set, since in the fully nested mode the highest IS

level was necessarily the last level acknowledged

and serviced. A non-specific EOI can be issued with

OCW2 (EOI e1, SL e0, R e0).

When a mode is used which may disturb the fully

nested structure, the 8259A may no longer be able

to determine the last level acknowledged. In this

case a Specific End of Interrupt must be issued

which includes as part of the command the IS level

to be reset. A specific EOI can be issued with OCW2

(EOI e1, SL e1, R e0, and L0–L2 is the binary

level of the IS bit to be reset).

It should be noted that an IS bit that is masked by an

IMR bit will not be cleared by a non-specific EOI if

the 8259A is in the Special Mask Mode.

Automatic End of Interrupt (AEOI)

Mode

If AEOI e1 in ICW4, then the 8259A will operate in

AEOI mode continuously until reprogrammed by

ICW4. in this mode the 8259A will automatically per-

form a non-specific EOI operation at the trailing

edge of the last interrupt acknowledge pulse (third

pulse in MCS-80/85, second in 8086). Note that

from a system standpoint, this mode should be used

only when a nested multilevel interrupt structure is

not required within a single 8259A.

The AEOI mode can only be used in a master 8259A

and not a slave. 8259As with a copyright date of

1985 or later will operate in the AEOI mode as a

master or a slave.

Automatic Rotation

(Equal Priority Devices)

In some applications there are a number of interrupt-

ing devices of equal priority. In this mode a device,

after being serviced, receives the lowest priority, so

a device requesting an interrupt will have to wait, in

the worst case until each of 7 other devices are

serviced at most

once

. For example, if the priority

and ‘‘in service’’ status is:

Before Rotate (IR4 the highest prioirity requiring

service)

‘‘IS’’ Status 231468–18

Priority Status 231468–19

8259A

After Rotate (IR4 was serviced, all other priorities

rotated correspondingly)

‘‘IS’’ Status 231468–20

Priority Status 231468–21

There are two ways to accomplish Automatic Rota-

tion using OCW2, the Rotation on Non-Specific EOI

Command (R e1, SL e0, EOI e1) and the Ro-

tate in Automatic EOI Mode which is set by (R e1,

SL e0, EOI e0) and cleared by (R e0, SL e0,

EOI e0).

Specific Rotation

(Specific Priority)

The programmer can change priorities by program-

ming the bottom priority and thus fixing all other pri-

orities; i.e., if IR5 is programmed as the bottom prior-

ity device, then IR6 will have the highest one.

The Set Priority command is issued in OCW2 where:

Re1, SL e1, L0– L2 is the binary priority level

code of the bottom priority device.

Observe that in this mode internal status is updated

by software control during OCW2. However, it is in-

dependent of the End of Interrupt (EOI) command

(also executed by OCW2). Priority changes can be

executed during an EOI command by using the Ro-

tate on Specific EOI command in OCW2 (R e1, SL

e1, EOI e1 and LO –L2 eIR level to receive

bottom priority).

Interrupt Masks

Each Interrupt Request input can bem masked indi-

vidually by the Interrupt Mask Register (IMR) pro-

grammed through OCW1. Each bit in the IMR masks

one interrupt channel if it is set (1). Bit 0 masks IR0,

Bit 1 masks IR1 and so forth. Masking an IR channel

does not affect the other channels operation.

Special Mask Mode

Some applications may require an interrupt service

routine to dynamically alter the system priority struc-

ture during its execution under software control. For

example, the routine may wish to inhibit lower priori-

ty requests for a portion of its execution but enable

some of them for another portion.

The difficulty here is that if an Interrupt Request is

acknowledged and an End of Interrupt command did

not reset its IS bit (i.e., while executing a service

routine), the 8259A would have inhibited all lower

priority requests with no easy way for the routine to

enable them.

That is where the Special Mask Mode comes in. In

the special Mask Mode, when a mask bit is set in

OCW1, it inhibits further interrupts at that level

and

enables

interrupts from

all other

levels (lower as well

as higher) that are not masked.

Thus, any interrupts may be selectively enabled by

loading the mask register.

The special Mask Mode is set by OWC3 where:

SSMM e1, SMM e1, and cleared where SSMM e

1, SMM e0.

Poll Command

In Poll mode the INT output functions as it normally

does. The microprocessor should ignore this output.

This can be accomplished either by not connecting

the INT output or by masking interrupts within the

microprocessor, thereby disabling its interrupt input.

Service to devices is achieved by software using a

Poll command.

The Poll command is issued by setting P e‘1’’ in

OCW3. The 8259A treats the next RD pulse to the

8259A (i.e., RD e0, CS e0) as an interrupt ac-

knowledge, sets the appropriate IS bit if there is a

request, and reads the priority level. Interrupt is fro-

zen from WR to RD.

The word enabled onto the data bus during RD is:

D7 D6 D5 D4 D3 D2 D1 D0

IÐÐÐÐW2W1W0

W0– W2: Binary code of the highest priority level

requesting service.

I: Equal to ‘‘1’’ if there is an interrupt.

This mode is useful if there is a routine command

common to several levels so that the INTA se-

quence is not needed (saves ROM space). Another

application is to use the poll mode to expand the

number of priority levels to more than 64.

Reading the 8259A Status

The input status of several internal registers can be

read to update the user information on the system.

8259A

NOTES: 231468–22

1. Master clear active only during ICW1.

2. FREEZE is active during INTA and poll sequences only.

3. Truth Table for a D-Latch.

C D Q Operation

1 Di Di Follow

0 X Qn-1 Hold

Figure 9. Priority CellÐSimplified Logic Diagram

The following registers can be read via OCW3 (IRR

and ISR or OCW1 [IMR]).

Interrupt Request Register (IRR):

8-bit register which

contains the levels requesting an interrupt to be ac-

knowledged. The highest request level is reset from

the IRR when an interrupt is acknowledged. (Not af-

fected by IMR.)

In-Service Register (ISR):

8-bit register which con-

tains the priority levels that are being serviced. The

ISR is updated when an End of Interrupt Command

is issued.

Interrupt Mask Register:

8-bit register which con-

tains the interrupt request lines which are masked.

The IRR can be read when, prior to the RD pulse, a

Read Register Command is issued with OCW3 (RR

e1, RIS e0.)

The ISR can be read, when, prior to the RD pulse, a

Read Register Command is issued with OCW3 (RR

e1, RIS e1).

There is no need to write an OCW3 before every

status read operation, as long as the status read

corresponds with the previous one; i.e., the 8259A

‘‘remembers’’ whether the IRR or ISR has been pre-

viously selected by the OCW3. This is not true when

poll is used.

After initialization the 8259A is set to IRR.

For reading the IMR, no OCW3 is needed. The out-

put data bus will contain the IMR whenever RD is

active and A0 e1 (OCW1).

Polling overrides status read when P e1, RR e1

in OCW3.

Edge and Level Triggered Modes

This mode is programmed using bit 3 in ICW1.

If LTIM e‘0’, an interrupt request will be recognized

by a low to high transition on an IR input. The IR

input can remain high without generating another in-

terrupt.

8259A

231468–23

Figure 10. IR Triggering Timing Requirements

If LTIM e‘1’, an interrupt request will be recognized

by a ‘high’ level on IR Input, and there is no need for

an edge detection. The interrupt request must be

removed before the EOI command is issued or the

CPU interrupts is enabled to prevent a second inter-

rupt from occurring.

The priority cell diagram shows a conceptual circuit

of the level sensitive and edge sensitive input circuit-

ry of the 8259A. Be sure to note that the request

latch is a transparent D type latch.

In both the edge and level triggered modes the IR

inputs must remain high until after the falling edge of

the first INTA. If the IR input goes low before this

time a DEFAULT IR7 will occur when the CPU ac-

knowledges the interrupt. This can be a useful safe-

guard for detecting interrupts caused by spurious

noise glitches on the IR inputs. To implement this

feature the IR7 routine is used for ‘‘clean up’’ simply

executing a return instruction, thus ignoring the inter-

rupt. If IR7 is needed for other purposes a default

IR7 can still be detected by reading the ISR. A nor-

mal IR7 interrupt will set the corresponding ISR bit, a

default IR7 won’t. If a default IR7 routine occurs dur-

ing a normal IR7 routine, however, the ISR will re-

main set. In this case it is necessary to keep track of

whether or not the IR7 routine was previously en-

tered. If another IR7 occurs it is a default.

The Special Fully Nest Mode

This mode will be used in the case of a big system

where cascading is used, and the priority has to be

conserved within each slave. In this case the fully

nested mode will be programmed to the master (us-

ing ICW4). This mode is similar to the normal nested

mode with the following exceptions:

a. When an interrupt request from a certain slave is

in service this slave is not locked out from the

master’s priority logic and further interrupt re-

quests from higher priority IR’s within the slave

will be recognized by the master and will initiate

interrupts to the processor. (In the normal nested

mode a slave is masked out when its request is in

service and no higher requests from the same

slave can be serviced.)

b. When exiting the Interrupt Service routine the

software has to check whether the interrupt serv-

iced was the only one from that slave. This is

done by sending a non-specific End of Interrupt

(EOI) command to the slave and then reading its

In-Service register and checking for zero. If it is

empty, a non-specific EOI can be sent to the

master too. If not, no EOI should be sent.

Buffered Mode

When the 8259A is used in a large system where

bus driving buffers are required on the data bus and

the cascading mode is used, there exists the prob-

lem of enabling buffers.

The buffered mode will structure the 8259A to send

an enable signal on SP/EN to enable the buffers. In

this mode, whenever the 8259A’s data bus outputs

are enabled, the SP/EN output becomes active.

This modification forces the use of software pro-

gramming to determine whether the 8259A is a mas-

ter or a slave. Bit 3 in ICW4 programs the buffered

mode, and bit 2 in ICW4 determines whether it is a

master or a slave.

8259A

CASCADE MODE

The 8259A can be easily interconnected in a system

of one master with up to eight slaves to handle up to

64 priority levels.

The master controls the slaves through the 3 line

cascade bus. The cascade bus acts like chip selects

to the slaves during the INTA sequence.

In a cascade configuration, the slave interrupt out-

puts are connected to the master interrupt request

inputs. When a slave request line is activated and

afterwards acknowledged, the master will enable the

corresponding slave to release the device routine

address during bytes 2 and 3 of INTA. (Byte 2 only

for 8086/8088).

The cascade bus lines are normally low and will con-

tain the slave address code from the trailing edge of

the first INTA pulse to the trailing edge of the third

pulse. Each 8259A in the system must follow a sep-

arate initialization sequence and can be pro-

grammed to work in a different mode. An EOI com-

mand must be issued twice: once for the master and

once for the corresponding slave. An address de-

coder is required to activate the Chip Select (CS)

input of each 8259A.

The cascade lines of the Master 8259A are activat-

ed only for slave inputs, non-slave inputs leave the

cascade line inactive (low).

231468–24

Figure 11. Cascading the 8259A

8259A

ABSOLUTE MAXIMUM RATINGS*

Ambient Temperature Under Bias ÀÀÀÀÀÀ0§Cto70

Storage Temperature ÀÀÀÀÀÀÀÀÀÀb65§Ctoa

150§C

Voltage on Any Pin

with Respect to GroundÀÀÀÀÀÀÀÀÀÀb0.5V to a7V

Power Dissipation ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1W

NOTICE: This is a production data sheet. The specifi-

cations are subject to change without notice.

WARNING: Stressing the device beyond the ‘‘Absolute

Maximum Ratings’’ may cause permanent damage.

These are stress ratings only. Operation beyond the

‘‘Operating Conditions’’ is not recommended and ex-

tended exposure beyond the ‘‘Operating Conditions’’

may affect device reliability.

D.C. CHARACTERISTICS TAe0§Cto70

C, VCC e5V g10%

Symbol Parameter Min Max Units Test Conditions

VIL Input Low Voltage b0.5 0.8 V

VIH Input High Voltage 2.0*VCC a0.5V V

VOL Output Low Voltage 0.45 V IOL e2.2 mA

VOH Output High Voltage 2.4 V IOH eb

400 mA

VOH(INT) Interrupt Output High 3.5 V IOH eb100 mA

Voltage 2.4 V IOH eb

400 mA

ILI Input Load Current b10 a10 mA0V

IN sVCC

ILOL Output Leakage Current b10 a10 mA 0.45V sVOUT sVCC

ICC VCC Supply Current 85 mA

ILIR IR Input Load Current b300 mAV

IN e0

10 mAV

IN eVCC

*NOTE:

For Extended Temperature EXPRESS VIH e2.3V.

CAPACITANCE TAe25§C; VCC eGND e0V

Symbol Parameter Min Typ Max Unit Test Conditions

CIN Input Capacitance 10 pF fc e1 MHz

CI/O I/O Capacitance 20 pF Unmeasured Pins Returned to VSS

8259A

A.C. CHARACTERISTICS TAe0§Cto70

C, VCC e5V g10%

TIMING REQUIREMENTS

Symbol Parameter 8259A 8259A-2 Units Test Conditions

Min Max Min Max

TAHRL AO/CS Setup to RD/INTA

00 ns

TRHAX AO/CS Hold after RD/INTA

00 ns

TRLRH RD Pulse Width 235 160 ns

TAHWL AO/CS Setup to WR

00 ns

TWHAX AO/CS Hold after WR

00 ns

TWLWH WR Pulse Width 290 190 ns

TDVWH Data Setup to WR

240 160 ns

TWHDX Data Hold after WR

00 ns

TJLJH Interrupt Request Width (Low) 100 100 ns See Note 1

TCVIAL Cascade Setup to Second or Third 55 40 ns

INTA

(Slave Only)

TRHRL End of RD to Next RD

End of INTA to Next INTA within 160 100 ns

an INTA Sequence Only

TWHWL End of WR to Next WR 190 100 ns

*TCHCL End of Command to Next Command 500 150 ns

(Not Same Command Type)

End of INTA Sequence to Next 500 300

INTA Sequence.

*Worst case timing for TCHCL in an actual microprocessor system is typically much greater than 500 ns (i.e. 8085A e

1.6 ms, 8085A-2 e1ms, 8086 e1ms, 8086-2 e625 ns)

NOTE:

This is the low time required to clear the input latch in the edge triggered mode.

TIMING RESPONSES

Symbol Parameter 8259A 8259A-2 Units Test Conditions

Min Max Min Max

TRLDV Data Valid from RD/INTA

200 120 ns C of Data Bus e

100 pF

TRHDZ Data Float after RD/INTA

10 100 10 85 ns C of Data Bus

TJHIH Interrupt Output Delay 350 300 ns Max Test C e100 pF

TIALCV Cascade Valid from First INTA

565 360 ns CINT e100 pF

Min Test C e15 pF

(Master Only)

TRLEL Enable Active from RD

or INTA

125 100 ns CCASCADE e100 pF

TRHEH Enable Inactive from RD

or INTA

150 150 ns

TAHDV Data Valid from Stable Address 200 200 ns

TCVDV Cascade Valid to Valid Data 300 200 ns

8259A

A.C. TESTING INPUT/OUTPUT WAVEFORM

231468–25

A.C. Testing: Inputs are driven at 2.4V for a logic ‘‘1’’ and 0.45V

for a logic ‘‘0’’. Timing measurements are made at 2.0V for a logic

‘‘1’’ and 0.8V for a logic ‘‘0’’.

A.C. TESTING LOAD CIRCUIT

231468–26

CLe100 pF

CLIncludes Jig Capacitance

WAVEFORMS

WRITE

231468–27

8259A

WAVEFORMS (Continued)

READ/INTA

231468–28

OTHER TIMING

231468–29

8259A

WAVEFORMS (Continued)

INTA SEQUENCE

231468–30

NOTES:

Interrupt output must remain HIGH at least until leading edge of first INTA.

1. Cycle 1 in 8086, 8088 systems, the Data Bus is not active.

Data Sheet Revision Review

The following changes have been made since revision 2 of the 8259A data sheet.

1. The first paragraph of the Poll Command section was rewritten to clarify the status of the INT pin.

2. A paragraph was added to the Interrupt Sequence section to indicate the status of the INT pin during

multiple interrupts.

3. A reference to PLCC packaging was added.

4. All references to the 8259A-8 have been deleted.

INTEL CORPORATION, 2200 Mission College Blvd., Santa Clara, CA 95052; Tel. (408) 765-8080

INTEL CORPORATION (U.K.) Ltd., Swindon, United Kingdom; Tel. (0793) 696 000

INTEL JAPAN k.k., Ibaraki-ken; Tel. 029747-8511

Printed in U.S.A./xxxx/1196/B10M/xx xx