1
FEATURES
>400.0 Mbps (200 MHz) switching rates
+340mV differential signaling
3.3 V powe r supply
TTL compatible outputs
Cold spare all pins
Nominal 100Integrated Termination Resistor
3.3ns maximum propagation delay
0.35ns maximum differential skew
Operational; total dose irradiation testing to MIL-STD-883
Method 1019
- Total-dose: 300 krad(Si) and 1Mrad(Si)
- Latchup immune (LET > 100 MeV-cm2/mg)
Packaging options:
- 16-lead flatpack (dual in-line)
Standard Microcircuit Drawing 5962-04201
- QML Q and V compliant part
Compatible with IEEE 1596.3SCI LVDS
Compatible with ANSI/TIA/EIA 644-1996 L VDS Standard
INTRODUCTION
The UT54LVDS032LVT with internal 100Integrated
Termination Resistor Quad Receiver is a quad CMOS
differential line receiver designed for applications requiring
ultra low power dissipation and high data rates. The device is
designed to support data rates in excess of 400.0 Mbps (200
MHz) utilizing Low Voltage Differential Signaling (LVDS)
technology.
The UT54LVDS032LVT accepts low voltage (340mV)
differential input signals and tr anslates them to 3V TTL output
levels. The receiver supports a three-state function that may be
used to multiplex outputs. The receiver also supports OPEN,
shorted and terminated (100 ) input fail-safe. Receiver output
will be HIGH for all fail-safe conditions.
All pins have Cold Spare buffers. These buffers will be high
impedance when VDD is tied to VSS.
An integrated termination resistor will reduce component count
and save board space.
+
R1
-
RIN1+
RIN1-
RIN2+
RIN2-
RIN3+
RIN3-
RIN4+
RIN4-
ROUT1
ROUT2
ROUT4
ROUT3
EN
EN
+
R2
-
+
R3
-
+
R4
-
Standard Products
UT54LVDS032LVT Low Voltage Quad Receiver with
Integrated Termination Resistor
Data Sheet
September, 2012
www.aeroflex.com/lvds
Figure 1. UT54LVDS032LV Quad Receiver Block Diagram
2
TRUTH TABLE
PIN DESCRIPTION
APPLICATIONS INFORMATION
The UT54LVDS032L VT receiver’s intended use is primarily in
an uncomplicated point-to-point configuration as is shown in
Figure 3. This configuration pro vides a clean signaling
environment for quick edge rates of the drivers. The receiver is
connected to the driver through a balanced media which may be
a standard twisted pair cable, a parallel pair cable, or simply
PCB traces. Typically, the characteristic impedance of the media
is in the range of 100. An int e grat ed termination resistor of
100is used to match the media. The termination resistor
converts the current sourced by the driver into voltages that are
detected by the receiver . Other co nfigurations are possible such
as a multi-receiver configuration, but the effects of a mid-stream
connector(s), cable stub(s), and other impedance discontinuities,
as well as ground shifting, noise margin limits, and total
termination loading must be taken into account.
The UT54LVDS032LVT differential line receiver is capable of
detecting signals as low as 100mV, over a + 1V common-mode
range centered around +1.2V. This is related to the driver offset
voltage which is typically +1.2V. The driven signal is centered
around this voltage and may shift +1V around this center point.
The +1V shifting may be the resul t of a ground potential
difference between the driver’s ground reference and the
receiver’s ground reference, the common-mode effects of
coupled noise or a combination of the two. Both receiver input
pins should honor their specified operating input voltage range
of 0V to +2.4V (measured from each pin to ground).
The integrated termination resistor is a nominal 100when VDD
is 3.0 to 3.6V. In cold spare mo de, the integ rated termination
resistor is 140
Enables Input Output
EN EN RIN+ - RIN- ROUT
L H X Z
All other combinations
of ENABLE inputs VID > 0.1V H
VID < -0.1V L
Full Fail-safe
OPEN/SHORT or
Terminated
H
Pin No. Name Description
2, 6, 10, 14 RIN+ Non-inverting receiver input pin
1, 7, 9, 15 RIN- Inverting receiver input pin
3, 5, 1 1, 13 ROUT Receiver output pin
4 EN Active high enable pin, OR-ed
with EN
12 EN Active low enable pin, OR-ed
with EN
16 VDD Power supply pin, +3.3 + 0.3V
8V
SS Ground pin
Figure 2. UT54LVDS032LVT Pinout
UT54LVDS032LV
Receiver
16
15
14
13
12
11
10
9
VDD
RIN4-
RIN4+
ROUT4
EN
ROUT3
RIN3+
RIN3-
1
RIN1-
2
RIN1+ 3
ROUT1
4
EN 5
ROUT2 6
RIN2+ 7
RIN2-
8
VSS
ENABLE
DATA
INPUT
1/4 UT54LVDS031LV
1/4 UT54LVDS032LV
+
-DATA
OUTPUT
Figure 3. Point-to-Point Application
RT 100
Receiver Fail-Safe
The UT54LVDS032LVT receiver is a high gain, high speed
device that amplifies a small differential signal (20mV) to
TTL logic levels. Due to the high gain and tight threshold of
the receiver, care should be taken to prevent noise from
appearing as a valid signal.
The receiver’s internal fail-safe circuitry is designed to
source/sink a small amount of current, providing fail-safe
protection (a stable known state of HIGH output voltage) for
floating, terminated or shorted receiver inputs.
1. Open Input Pins. The UT54L VDS032L VT is a quad
receiver device, and if an application requires only 1,
2 or 3 receivers, the unused channel(s) inputs should
be left OPEN. Do not tie unused receiver inputs to
ground or any other voltages. The input is biased by
internal high value pull up and pull down resistors to
set the output to a HIGH state. This internal circuitry
will guarantee a HIGH, stable output state for open
inputs.
2. Terminated Input. If the driver is disconnected
(cable unplugged), or if the driver is in a three-state
or power-of f condition, the receiver output will again
be in a HIGH state, even with the end of cable 100
integratedtermination resistor across the input pins.
The unplugged cable can become a floating antenn a
which can pick up noise. If the cable picks up more
than 10mV of differential noise, the receiver may see
the noise as a valid signal and switch. To insure that
any noise is seen as common-mode and not
differential, a balanced interconnect should be used .
Twisted pair cable offers better balance than flat
ribbon cable.
3. Shorted Inputs. If a fault condition occurs that shorts
the receiver inputs together, thus resulting in a 0V
differential input voltage, the receiver output remains
in a HIGH state. Shorted input fail-safe is not
supported across the common-mode range of th e
device (VSS to 2.4V). It is only supported with inputs
shorted and no external common -mode voltage
applied.
3
4
OPERATIONAL ENVIRONMENT
Notes:
1. Guarnteed but not tested.
ABSOLUTE MAXIMUM RATINGS1
(Referenced to VSS)
Notes:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device
at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability and performance.
2. Maximum junction temperatu re may be incr eased to +175C during burn-in and life test.
3. Test per MIL-STD-883, Method 1012.
RECOMMENDED OPERATING CONDITIONS
PARAMETER LIMIT UNITS
Total Ionizing Dose (TID) 1.0E6 rad(Si)
Single Event Latchup (SEL) >100 MeV-cm2/mg
Neutron Fluence11.0E13 n/cm2
SYMBOL PARAMETER LIMITS
VDD DC supply voltage -0.3 to 4.0V
VI/O Voltage on any pin during operation -0.3 to (VDD + 0.3V)
Voltage on any pin during cold spare -.3 to 4.0V
TSTG Storage temperature -65 to +150C
PDMaximum power dissipation 1.25 W
TJMaximum junction te mperature2+150C
JC Thermal resistance, junction-to-case310C/W
IIDC input current ±10mA
SYMBOL PARAMETER LIMITS
VDD Positive supply voltage 3.0 to 3.6V
TCCase temperature range -55 to +125C
VIN DC input voltage, receiver inputs
DC input voltage, log ic inp uts 2.4V
0 to VDD for EN, EN
5
DC ELECTRICAL CHARACTERISTICS *1
(VDD = 3.3V + 0.3V; -55C < TC < +125C); Unless otherwise noted, Tc is per the temperature range ordered
Notes:
* For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25oC per MIL-STD-883 Method 1019, Condition
A up to the maximum TID level procured.
1. Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to groun d.
2. Output short circuit current (IOS) is sp ecified as magnitude only, minus sign indicates direction only. Only one output should be shorted at a time, for a maximum
duration of one second .
3. Guaranteed by characterization.
4. Tested functionally.
SYMBOL PARAMETER CONDITION MIN MAX UNIT
VIH High-level input voltage (TTL) 2.0 V
VIL Low-level input voltage (TTL) 0.8 V
VOL Low-level output voltage IOL = 2mA, VDD = 3.0V 0.25 V
VOH High-level output voltage IOH = -0.4mA, VDD = 3.0V 2.7 V
IIN Logic input leakage current Enables = EN/EN = 3.6V,
VDD = 3.6 -10 +10 A
IIReceiver input Current VIN = 2.4V, VDD = 3.6V -15 +15 
ICS Cold Spare Leakage Current VIN=3.6V, VDD=VSS -20 +20 
VTH4Differential Input High Threshold VCM = +1.2V +100 mV
VTL4Differential Input Low Threshold VCM = +1.2V -100 mV
VCMR4Common Mode Voltage Range VID = 200mV peak to peak 0.1 2.3 V
IOZ Output Three-State Current Disabled, VOUT = 0 V or VDD -10 +10 
VCL Input clamp voltage ICL = +18mA -1.5 V
IOS2, 3 Output Short Circuit Current Enabled, VOUT = 0 V2-15 -130 mA
ICC Supply current, receivers enabled EN, EN = VDD or VSS
Inputs Open
15 mA
ICCZ Supply current, receivers disabled EN = VSS, EN = VDD
Inputs Open 4mA
RTERM Termination Resistor VDD = 3.0V to 3.6V 83 114
VDD = 0.0V 125 154
6
AC SWITCHING CHARACTERISTICS*1, 2, 3
(VDD = +3.3V + 0.3V, TC = -55 C to +125 C); Unless otherwise noted, Tc is per the temperature range ordered
Notes:
* For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25oC per MIL-STD-883 Method 1019, Condition
A up to the maximum TID level procured.
1. Channel-to-Channel Skew is defined as th e difference between the propagation delay of the channel and the other channels in the same chip with an event on the inputs.
2. Generator waveform for all tests un less otherwise specified: f = 1 MHz, Z0 = 50, tr and tf (0% - 100%) < 1ns for RIN and tr and tf < 1ns for EN or EN.
3. CL includes probe and jig capacitance.
4. Guaranteed by characterization.
5. Chip to Chip Skew is defined as the difference between the minimum and maximum specified differential propagation delays.
SYMBOL PARAMETER MIN MAX UNIT
tPHLD6Differential Propagation Delay High to Low
(figures 4 and 5) 1.8 3.3 ns
tPLHD6Differential Propagation Delay Low to High
(figures 4 and 5) 1.8 3.3 ns
tSKD Differential Skew (tPHLD - tPLHD) (figures 4 and 5) 0 0.35 ns
tSK1 Channel-to-Channel Skew1 (figures 4 and 5) 00.5ns
tSK2 Chip-to-Chip Skew5 (figures 4 and 5) 3.0 ns
tTLH Rise Time (figures 4 and 5) 1.2 ns
tTHL Fall Time (figures 4 and 5) 1.2 ns
tPHZ Disable Ti me High to Z (figures 6 and 7) 12 ns
tPLZ Disable Time Low to Z (figures 6 and 7) 12 ns
tPZH Enable Time Z to High (figures 6 and 7) 12 ns
tPZL Enable Time Z to Low (figures 6 and 7) 12 ns
7
R
RIN+ ROUT
Receiver Enabled
Generator
50
Figure 4. Receiver Propagation Delay and Transition Time Test Circuit or Equivalent Circuit
RIN-
50
40pF
50
VDD/2
RIN-
RIN+
ROUT
tPHLD
VOL
VOH
+1.1V
50%
+1.2V
tTHL
20%
80%
50%
20%
80%
tTLH
0V Differential
Figure 5. Receiver Propagation Delay and Transition Time Waveforms
tPLHD
VID = 200mV
+1.3V
8
Figure 6. Receiver Three-State Delay Test Circuit or Equivalent Circuit
RIN+
RIN-
EN VDD
100
100
40pf
EN when EN = VDD
EN when EN = VSS
Output when
VID = -100mV
Output when
VID = +100mV
tPHZ tPZH
0.5V 50%
VOH
VOZ
VOZ
0V
VDD
0V
VDD
1.5V
1.5V
1.5V
1.5V
0.5V
tPZL
tPLZ
Figure 7. Receiver Three-State Delay Waveform
50%
VOL
9
PACKAGING
Figure 8. 16-pin Ceramic Flatpack
10
ORDERING INFORMATION
UT54LVDS032LVT QUAD RECEIVER:
11
COLORADO
Toll Free: 800-645-8862
Fax: 719-594-8468
SE AND MID-ATLANTIC
Tel: 321-951-4164
Fax: 321-951-4254
INTERNATIONAL
Tel: 805-778-9229
Fax: 805-778-1980
WEST COAST
Tel: 949-362-2260
Fax: 949-362-2266
NORTHEAST
Tel: 603-888-3975
Fax: 603-888-4585
CENTRAL
Tel: 719-594-8017
Fax: 719-594-8468
www.aeroflex.com info-ams@aeroflex.com
Our passion for perform a nce is defined by three
attributes represented by the s e three icons:
solution-minde d, perform an c e-d riven and custom e r-focu sed
Aeroflex Colorado Springs (Aeroflex) reserves the right to
make changes to any products and services herein at any time
without notice. Consult Aeroflex or an authorized sales
representative to verify that the information in this data sheet
is current before using this product. Aeroflex does not assume
any responsibility or liability arising out of the application or
use of any product or service described herein, except as
expressly agreed to in writing by Aeroflex; nor does the
purchase, lease, or use of a product or service from Aeroflex
convey a license under any patent rights, copyrights,
trademark rights, or any other of the intellectual rights of
Aeroflex or of third parties.
UT54LVDS032LVT QU AD RECEIVER: SMD
5962 - ** *
Federal Stock Class Designator: No Options
Total Dose
(R) = 1E5 rad(Si)
(F) = 3E5 rad(Si)
(G) = 5E5 rad(Si)
(H) = 1E6 rad(Si)
Drawing Number: 04201
Device Type
01 = LVDS Receiver, 300k, 500k and 1M Rad(Si)
02 = LVDS Receiver, 100k Rad(Si)
Class Designator:
(Q) = QML Class Q
(V) = QML Class V
Case Outline:
(Y) = 16 lead Flatpack (dual-in-line)
Lead Finish:
(A) = Hot solder dipped
(C) = Gold
(X) = Factory Option (gold or solder)
**
04201
Notes:
1.Lead finish (A,C, or X) must be specifi ed.
2.If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold).
3.Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening.