LMK00308
March 14, 2012
3-GHz 8-Output Differential Clock Buffer/Level Translator
1.0 General Description
The LMK00308 is a 3-GHz, 8-output differential fanout buffer
intended for high-frequency, low-jitter clock/data distribution
and level translation. The input clock can be selected from
two universal inputs or one crystal input. The selected input
clock is distributed to two banks of 4 differential outputs and
one LVCMOS output. Both differential output banks can be
independently configured as LVPECL, LVDS, or HCSL
drivers, or disabled. The LVCMOS output has a synchronous
enable input for runt-pulse-free operation when enabled or
disabled. The LMK00308 operates from a 3.3 V core supply
and 3 independent 3.3 V/2.5 V output supplies..
The LMK00308 provides high performance, versatility, and
power efficiency, making it ideal for replacing fixed-output
buffer devices while increasing timing margin in the system.
2.0 Target Applications
■Clock Distribution and Level Translation for high-speed
ADCs, DACs, Serial Interfaces (Multi-Gigabit Ethernet,
XAUI, Fibre Channel, PCIe, SATA/SAS, SONET/SDH,
CPRI), and high-frequency backplanes
■Remote Radio Units (RRU) and Baseband Units (BBU)
■Switches and Routers
■Servers, Workstations, and Computing
3.0 Features
■3:1 Input Multiplexer
—Two universal inputs operate up to 3.1 GHz and accept
LVPECL, LVDS, CML, SSTL, HSTL, HCSL (AC-
coupled), or single-ended clocks
—One crystal input accepts a 10 to 40 MHz crystal or
single-ended clock
■Two Banks with 4 Differential Outputs each
—LVPECL, LVDS, HCSL, or Hi-Z (selectable per bank)
—LVPECL Additive Jitter with LMK03806 clock source
■20 fs RMS at 156.25 MHz (10 kHz – 1 MHz)
■51 fs RMS at 156.25 MHz (12 kHz – 20 MHz)
■High PSRR: -65 / -76 dBc (LVPECL/LVDS) at 156.25 MHz
■LVCMOS output with synchronous enable input
■Pin-controlled configuration
■VCC Core Supply: 3.3 V ± 5%
■3 Independent VCCO Output Supplies: 3.3 V/2.5 V ± 5%
■Industrial temperature range: -40°C to +85°C
■Package: 40-pin LLP (6.0 x 6.0 x 0.8 mm)
4.0 Functional Block Diagram
30177601
© 2012 Texas Instruments Incorporated 301776 SNAS576A www.ti.com
LMK00308 3-GHz 8-Output Differential Clock Buffer/Level Translator
5.0 Connection Diagram
40-Pin LLP Package
30177602
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LMK00308
6.0 Pin Descriptions
Pin # Pin Name(s) Type Description
DAP DAP GND Die Attach Pad. Connect to the PCB ground plane for heat dissipation.
1, 2 CLKoutA0, CLKoutA0* O Differential clock output A0. Output type set by CLKoutA_TYPE pins.
3, 6 VCCOA PWR
Power supply for Bank A Output buffers. VCCOA can operate from 3.3 V or
2.5 V. The VCCOA pins are internally tied together. Bypass with a 0.1 uF
low-ESR capacitor placed very close to each Vcco pin. (Note 1)
4, 5 CLKoutA1, CLKoutA1* O Differential clock output A1. Output type set by CLKoutA_TYPE pins.
7, 8 CLKoutA2, CLKoutA2* O Differential clock output A2. Output type set by CLKoutA_TYPE pins.
9, 10 CLKoutA3, CLKoutA3* O Differential clock output A3. Output type set by CLKoutA_TYPE pins.
11, 39 CLKoutA_TYPE0,
CLKoutA_TYPE1 I Bank A output buffer type selection pins (Note 2)
12, 35 Vcc PWR
Power supply for Core and Input buffer blocks. The Vcc supply operates
from 3.3 V. Bypass with a 0.1 uF low-ESR capacitor placed very close to
each Vcc pin.
13 OSCin I Input for crystal. Can also be driven by a XO, TCXO, or other external
single-ended clock.
14 OSCout O Output for crystal. Leave OSCout floating if OSCin is driven by a single-
ended clock.
15, 18 CLKin_SEL0, CLKin_SEL1 I Clock input selection pins (Note 2)
16, 17 CLKin0, CLKin0* I Universal clock input 0 (differential/single-ended)
19, 32 CLKoutB_TYPE0,
CLKoutB_TYPE1 I Bank B output buffer type selection pins (Note 2)
20, 31, 40 GND GND Ground
21, 22 CLKoutB3*, CLKoutB3 O Differential clock output B3. Output type set by CLKoutB_TYPE pins.
23, 24 CLKoutB2*, CLKoutB2 O Differential clock output B2. Output type set by CLKoutB_TYPE pins.
25, 28 VCCOB PWR
Power supply for Bank B Output buffers. VCCOB can operate from 3.3 V or
2.5 V. The VCCOB pins are internally tied together. Bypass with a 0.1 uF
low-ESR capacitor placed very close to each Vcco pin. (Note 1)
26, 27 CLKoutB1*, CLKoutB1 O Differential clock output B1. Output type set by CLKoutB_TYPE pins.
29, 30 CLKoutB0*, CLKoutB0 O Differential clock output B0. Output type set by CLKoutB_TYPE pins.
33, 34 CLKin1*, CLKin1 I Universal clock input 1 (differential/single-ended)
36 REFout O LVCMOS reference output. Enable output by pulling REFout_EN pin high.
37 VCCOC PWR
Power supply for REFout Output buffer. VCCOC can operate from 3.3 V or
2.5 V. Bypass with a 0.1 uF low-ESR capacitor placed very close to each
Vcco pin. (Note 1)
38 REFout_EN I REFout enable input. Enable signal is internally synchronized to selected
clock input. (Note 2)
Note 1: The output supply voltages/pins (VCCOA, VCCOB, and VCCOC) will be referred to generally as VCCO when no distinction is needed, or when the output supply
can be inferred by the output bank/type.
Note 2: CMOS control input with internal pull-down resistor.
Note 3: Any unused output pins should be left floating with minimum copper length (Note 5), or properly terminated if connected to a transmission line, or disabled/
Hi-Z if possible. See Section 7.3 Clock Outputs for output configuration or Section 14.3 Termination and Use of Clock Drivers output interface and termination
techniques.
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LMK00308
7.0 Functional Description
The LMK00308 is an 8-output differential clock fanout buffer
with low additive jitter that can operate up to 3.1 GHz. It fea-
tures a 3:1 input multiplexer with an optional crystal oscillator
input, two banks of 4 differential outputs with multi-mode
buffers (LVPECL, LVDS, HCSL, or Hi-Z), one LVCMOS out-
put, and 3 independent output buffer supplies. The input
selection and output buffer modes are controlled via pin strap-
ping. The device is offered in a 40-pin LLP package and
leverages much of the high-speed, low-noise circuit design
employed in the LMK04800 family of clock conditioners.
7.1 VCC and VCCO Power Supplies
The LMK00308 has a 3.3 V core power supply (VCC) and 3
independent 3.3 V/2.5 V output power supplies (VCCOA,
VCCOB, VCCOC). Output supply operation at 2.5 V enables low-
er power consumption and output-level compatibility with 2.5
V receiver devices. The output levels for LVPECL (VOH, VOL)
and LVCMOS (VOH) are referenced to the respective Vcco
supply, while the output levels for LVDS and HCSL are rela-
tively constant over the specified Vcco range. Refer to Sec-
tion 14.4 Power Supply and Thermal Considerations for
additional supply related considerations, such as power dis-
sipation, power supply bypassing, and power supply ripple
rejection (PSRR).
Note 4: Care should be taken to ensure the Vcco voltages do not exceed
the Vcc voltage to prevent turning-on the internal ESD protection circuitry.
7.2 Clock Inputs
The input clock can be selected from CLKin0/CLKin0*,
CLKin1/CLKin1*, or OSCin. Clock input selection is controlled
using the CLKin_SEL[1:0] inputs as shown in Table 1. Refer
to Section 14.1 Driving the Clock Inputs for clock input re-
quirements. When CLKin0 or CLKin1 is selected, the crystal
circuit is powered down. When OSCin is selected, the crystal
oscillator circuit will start-up and its clock will be distributed to
all outputs. Refer to Section 14.2 Crystal Interface for more
information. Alternatively, OSCin may be be driven by a sin-
gle-ended clock (up to 250 MHz) instead of a crystal.
TABLE 1. Input Selection
CLKin_SEL1 CLKin_SEL0 Selected Input
0 0 CLKin0, CLKin0*
0 1 CLKin1, CLKin1*
1 X OSCin
Table 2 shows the output logic state vs. input state when ei-
ther CLKin0/CLKin0* or CLKin1/CLKin1* is selected. When
OSCin is selected, the output state will be an inverted copy of
the OSCin input state.
TABLE 2. CLKin Input vs. Output States
State of
Selected CLKin
State of
Enabled Outputs
CLKinX and CLKinX*
inputs floating Logic low
CLKinX and CLKinX*
inputs shorted together Logic low
CLKin logic low Logic low
CLKin logic high Logic high
7.3 Clock Outputs
The differential output buffer type for Bank A and Bank B out-
puts can be separately configured using the CLKoutA_TYPE
[1:0] and CLKoutB_TYPE[1:0] inputs, respectively, as shown
in Table 3. For applications where all differential outputs are
not needed, any unused output pin should be left floating with
a minimum copper length (Note 5) to minimize capacitance
and potential coupling and reduce power consumption. If an
entire output bank will not be used, it is recommended to dis-
able/Hi-Z the bank to reduce power. Refer to Section 14.3
Termination and Use of Clock Drivers for more information on
output interface and termination techniques.
Note 5: For best soldering practices, the minimum trace length for any
unused output pin should extend to include the pin solder mask. This way
during reflow, the solder has the same copper area as connected pins. This
allows for good, uniform fillet solder joints helping to keep the IC level during
reflow.
TABLE 3. Differential Output Buffer Type Selection
CLKoutX_
TYPE1
CLKoutX_
TYPE0
CLKoutX Buffer Type
(Bank A or B)
0 0 LVPECL
0 1 LVDS
1 0 HCSL
1 1 Disabled (Hi-Z)
7.3.1 Reference Output
The reference output (REFout) provides a LVCMOS copy of
the selected input clock. The LVCMOS output high level is
referenced to the Vcco voltage. REFout can be enabled or
disabled using the enable input pin, REFout_EN, as shown in
Table 4.
TABLE 4. Reference Output Enable
REFout_EN REFout State
0 Disabled (Hi-Z)
1 Enabled
The REFout_EN input is internally synchronized with the se-
lected input clock by the SYNC block. This synchronizing
function prevents glitches and runt pulses from occurring on
the REFout clock when enabled or disabled. REFout will be
enabled within 3 cycles (tEN) of the input clock after
REFout_EN is toggled high. REFout will be disabled within 3
cycles (tDIS) of the input clock after REFout_EN is toggled low.
When REFout is disabled, the use of a resistive loading can
be used to set the output to a predetermined level. For ex-
ample, if REFout is configured with a 1 kΩ load to ground,
then the output will be pulled to low when disabled.
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LMK00308
8.0 Absolute Maximum Ratings (Note 6, Note 7)
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for
availability and specifications.
Parameter Symbol Ratings Units
Supply Voltages VCC, VCCO -0.3 to 3.6 V
Input Voltage VIN -0.3 to (VCC + 0.3) V
Storage Temperature Range TSTG -65 to +150 °C
Lead Temperature (solder 4 s) TL+260 °C
Junction Temperature TJ+150 °C
9.0 Recommended Operating Conditions
Parameter Symbol Min Typ Max Units
Ambient Temperature Range TA-40 25 85 °C
Junction Temperature TJ 125 °C
Core Supply Voltage Range VCC 3.15 3.3 3.45 V
Output Supply Voltage Range (Note 8,
Note 9)VCCO
3.3 – 5%
2.5 – 5%
3.3
2.5
3.3 + 5%
2.5 + 5% V
Note 6: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see Section 11.0 Electrical
Characteristics. The guaranteed specifications apply only to the test conditions listed.
Note 7: This device is a high-performance integrated circuit with an ESD rating up to 2 kV Human Body Model, up to 150 V Machine Model, and up to 750 V
Charged Device Model and is ESD sensitive. Handling and assembly of this device should only be done at ESD-free workstations.
Note 8: The output supply voltages/pins (VCCOA, VCCOB, and VCCOC) will be referred to generally as VCCO when no distinction is needed, or when the output supply
can be inferred by the output bank/type.
Note 9: Vcco should be less than or equal to Vcc (Vcco ≤ Vcc).
10.0 Package Thermal Resistance
Package θJA θJC (DAP)
40-Lead LLP (Note 10) 31.4 °C/W 7.2 °C/W
Note 10: Specification assumes 9 thermal vias connect the die attach pad (DAP) to the embedded copper plane on the 4-layer JEDEC board. These vias play a
key role in improving the thermal performance of the LLP. It is recommended that the maximum number of vias be used in the board layout.
11.0 Electrical Characteristics Unless otherwise specified: Vcc = 3.3 V ± 5%, Vcco = 3.3 V ± 5%, 2.5 V ±
5%, -40 °C ≤ TA ≤ 85 °C, CLKin driven differentially, input slew rate ≥ 3 V/ns. Typical values represent most likely parametric
norms at Vcc = 3.3 V, Vcco = 3.3 V, TA = 25 °C, and at the Recommended Operation Conditions at the time of product
characterization and are not guaranteed. (Note 8, Note 11)
Symbol Parameter Conditions Min Typ Max Units
Current Consumption
ICC_CORE
Core Supply Current, All Outputs
Disabled
CLKinX selected 8.5 10.5 mA
OSCin selected 10 13.5 mA
ICC_PECL
Additive Core Supply Current,
Per LVPECL Bank Enabled 20 26.5 mA
ICC_LVDS
Additive Core Supply Current,
Per LVDS Bank Enabled 25 30.5 mA
ICC_HCSL
Additive Core Supply Current,
Per HCSL Bank Enabled 31 38.5 mA
ICC_CMOS
Additive Core Supply Current,
LVCMOS Output Enabled 3.5 5.5 mA
ICCO_PECL
Additive Output Supply Current,
Per LVPECL Bank Enabled
Includes Output Bank Bias and Load
Currents, RT = 50 Ω to Vcco - 2V
on all outputs in bank
132 160 mA
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LMK00308
Symbol Parameter Conditions Min Typ Max Units
ICCO_LVDS
Additive Output Supply Current,
Per LVDS Bank Enabled 26 34.5 mA
ICCO_HCSL
Additive Output Supply Current,
Per HCSL Bank Enabled
Includes Output Bank Bias and Load
Currents, RT = 50 Ω
on all outputs in bank
68 84 mA
ICCO_CMOS
Additive Output Supply Current,
LVCMOS Output Enabled
200 MHz,
CL = 5 pF
Vcco =
3.3 V ± 5% 9 10 mA
Vcco =
2.5 V ± 5% 7 8 mA
Power Supply Ripple Rejection (PSRR)
PSRRPECL
Ripple-Induced
Phase Spur Level (Note 13)
Differential LVPECL Output
100 kHz, 100 mVpp
Ripple Injected on
Vcco, Vcco = 2.5 V
156.25 MHz -65
dBc
312.5 MHz -63
PSRRLVDS
Ripple-Induced
Phase Spur Level (Note 13)
Differential LVDS Output
156.25 MHz -76
dBc
312.5 MHz -74
PSRRHCSL
Ripple-Induced
Phase Spur Level (Note 13)
Differential HCSL Output
156.25 MHz -72
dBc
312.5 MHz -63
CMOS Control Inputs (CLKin_SELn, CLKoutX_TYPEn, REFout_EN)
VIH High-Level Input Voltage 1.6 Vcc V
VIL Low-Level Input Voltage GND 0.4 V
IIH High-Level Input Current VIH = Vcc, Internal pull-down resistor 50 µA
IIL Low-Level Input Current VIL = 0 V, Internal pull-down resistor -5 0.1 µA
Clock Inputs (CLKin0/CLKin0*, CLKin1/CLKin1*)
fCLKin
Input Frequency Range
(Note 20)
Functional up to 3.1 GHz
Output frequency range and timing specified
per output type (refer to LVPECL, LVDS,
HCSL, LVCMOS output specifications)
DC 3.1 GHz
VIHD Differential Input High Voltage
CLKin driven differentially
Vcc V
VILD Differential Input Low Voltage GND V
VID
Differential Input Voltage Swing
(Note 14)0.15 1.3 V
VCMD
Differential Input
Common Mode Voltage
VID = 150 mV 0.5 Vcc -
1.2
V
VID = 350 mV 0.5 Vcc -
1.1
VID = 800 mV 0.5 Vcc -
0.9
VIH
Single-Ended Input
High Voltage
CLKinX driven single-ended,
CLKinX* AC coupled to GND
VCM +
0.15 Vcc V
VIL
Single-Ended Input
Low Voltage GND VCM
-0.15 V
VCM
Single-Ended Input
Common Mode Voltage 0.5 Vcc -
1.2 V
ISOMUX
Mux Isolation,
CLKin0 to CLKin1
fOFFSET > 50 kHz,
PCLKinX = 0 dBm
fCLKin0 = 100 MHz -84
dBc
fCLKin0 = 200 MHz -82
fCLKin0 = 500 MHz -71
fCLKin0 = 1000 MHz -65
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LMK00308
Symbol Parameter Conditions Min Typ Max Units
Crystal Interface (OSCin, OSCout)
FCLK
External Clock
Frequency Range
(Note 20)
OSCin driven single-ended,
OSCout floating 250 MHz
FXTAL Crystal Frequency Range
Fundamental mode crystal
ESR ≤ 200 Ω (10 to 30 MHz)
ESR ≤ 125 Ω (30 to 40 MHz)
(Note 15)
10 40 MHz
CIN OSCin Input Capacitance 1 pF
LVPECL Outputs (CLKoutAn/CLKoutAn*, CLKoutBn/CLKoutBn*)
fCLKout_FS
Maximum Output Frequency
Full VOD Swing
(Note 20, Note 21)
VOD ≥ 600 mV,
RL = 100 Ω
differential
Vcco = 3.3 V ± 5%,
RT = 160 Ω to GND 1.0 1.2
GHz
Vcco = 2.5 V ± 5%,
RT = 91 Ω to GND 0.75 1.0
fCLKout_RS
Maximum Output Frequency
Reduced VOD Swing
(Note 20, Note 21)
VOD ≥ 400 mV,
RL = 100 Ω
differential
Vcco = 3.3 V ± 5%,
RT = 160 Ω to GND 1.5 3.1
GHz
Vcco = 2.5 V ± 5%,
RT = 91 Ω to GND 1.5 2.3
JitterADD
Additive RMS Jitter
Integration Bandwidth
1 MHz to 20 MHz
(Note 16)
Vcco = 3.3 V,
RT = 160 Ω to GND,
RL = 100 Ω
differential
CLKin: 100 MHz, Slew
rate ≥ 3 V/ns 59
fs
CLKin: 156.25 MHz,
Slew rate ≥ 2.7 V/ns 64
CLKin: 625 MHz, Slew
rate ≥ 3 V/ns 30
JitterADD
Additive RMS Jitter with
LVPECL clock source from
LMK03806
(Note 16, Note 17)
Vcco = 3.3 V,
RT = 160 Ω to GND,
RL = 100 Ω
differential
CLKin: 156.25 MHz,
JSOURCE = 190 fs RMS
(10 kHz to 1 MHz)
20
fs
CLKin: 156.25 MHz,
JSOURCE = 195 fs RMS
(12 kHz to 20 MHz)
51
Noise Floor Noise Floor
fOFFSET ≥ 10 MHz
Vcco = 3.3 V,
RT = 160 Ω to GND,
RL = 100 Ω
differential
CLKin: 100 MHz, Slew
rate ≥ 3 V/ns -162.5
dBc/Hz
CLKin: 156.25 MHz,
Slew rate ≥ 2.7 V/ns -158.1
CLKin: 625 MHz, Slew
rate ≥ 3 V/ns -154.4
DUTY Duty Cycle (Note 20) 50% input clock duty cycle 45 55 %
VOH Output High Voltage
TA = 25 °C, DC Measurement,
RT = 50 Ω to Vcco - 2 V
Vcco -
1.2
Vcco -
0.9
Vcco -
0.7 V
VOL Output Low Voltage Vcco -
2.0
Vcco -
1.75
Vcco -
1.5 V
VOD
Output Voltage Swing
(Note 14)600 830 1000 mV
tR
Output Rise Time
20% to 80% RT = 160 Ω to GND,
RL = 100 Ω differential
175 ps
tF
Output Fall Time
80% to 20% 175 ps
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LMK00308
Symbol Parameter Conditions Min Typ Max Units
LVDS Outputs (CLKoutAn/CLKoutAn*, CLKoutBn/CLKoutBn*)
fCLKout_FS
Maximum Output Frequency
Full VOD Swing
(Note 20, Note 21)
VOD ≥ 250 mV,
RL = 100 Ω differential 1.0 1.6 GHz
fCLKout_RS
Maximum Output Frequency
Reduced VOD Swing
(Note 20, Note 21)
VOD ≥ 200 mV,
RL = 100 Ω differential 1.5 2.1 GHz
JitterADD
Additive RMS Jitter
Integration Bandwidth
1 MHz to 20 MHz
(Note 16)
Vcco = 3.3 V,
RL = 100 Ω
differential
CLKin: 100 MHz, Slew
rate ≥ 3 V/ns 89
fs
CLKin: 156.25 MHz,
Slew rate ≥ 2.7 V/ns 77
CLKin: 625 MHz, Slew
rate ≥ 3 V/ns 37
Noise Floor Noise Floor
fOFFSET ≥ 10 MHz
Vcco = 3.3 V,
RL = 100 Ω
differential
CLKin: 100 MHz, Slew
rate ≥ 3 V/ns -159.5
dBc/Hz
CLKin: 156.25 MHz,
Slew rate ≥ 2.7 V/ns -157.0
CLKin: 625 MHz, Slew
rate ≥ 3 V/ns -152.7
DUTY Duty Cycle (Note 20) 50% input clock duty cycle 45 55 %
VOD
Output Voltage Swing
(Note 14)
TA = 25 °C,
DC Measurement,
RL = 100 Ω differential
250 400 450 mV
ΔVOD
Change in Magnitude of VOD for
Complementary Output States -50 50 mV
VOS Output Offset Voltage 1.125 1.25 1.375 V
ΔVOS
Change in Magnitude of VOS for
Complementary Output States -35 35 mV
ISA
ISB
Output Short Circuit Current
Single Ended
TA = 25 °C,
Single ended outputs shorted to GND -24 24 mA
ISAB
Output Short Circuit Current
Differential Complementary outputs tied together -12 12 mA
tR
Output Rise Time
20% to 80% RL = 100 Ω differential
175 ps
tF
Output Fall Time
80% to 20% 175 ps
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LMK00308
Symbol Parameter Conditions Min Typ Max Units
HCSL Outputs (CLKoutAn/CLKoutAn*, CLKoutBn/CLKoutBn*)
fCLKout
Output Frequency Range
(Note 20)RL = 50 Ω to GND, CL ≤ 5 pF DC 400 MHz
JitterADD
Additive RMS Jitter
Integration Bandwidth
1 MHz to 20 MHz
(Note 16)
Vcco = 3.3 V,
RT = 50 Ω to GND
CLKin: 100 MHz, Slew
rate ≥ 3 V/ns 77
fs
CLKin: 156.25 MHz,
Slew rate ≥ 2.7 V/ns 86
Noise Floor Noise Floor
fOFFSET ≥ 10 MHz
Vcco = 3.3 V,
RT = 50 Ω to GND
CLKin: 100 MHz, Slew
rate ≥ 3 V/ns -161.3
dBc/Hz
CLKin: 156.25 MHz,
Slew rate ≥ 2.7 V/ns -156.3
DUTY Duty Cycle (Note 20) 50% input clock duty cycle 45 55 %
VOH Output High Voltage TA = 25 °C, DC Measurement,
RT = 50 Ω to GND
520 810 920 mV
VOL Output Low Voltage -150 0.5 150 mV
VCROSS
Absolute Crossing Voltage
(Note 20, Note 22)RL = 50 Ω to GND,
CL ≤ 5 pF
160 350 460 mV
ΔVCROSS
Total Variation of VCROSS
(Note 20, Note 22) 140 mV
tR
Output Rise Time
20% to 80% (Note 22)250 MHz, RL = 50 Ω to GND,
CL ≤ 5 pF
300 ps
tF
Output Fall Time
80% to 20% (Note 22) 300 ps
LVCMOS Output (REFout)
fCLKout
Output Frequency Range
(Note 20)CL ≤ 5 pF DC 250 MHz
JitterADD
Additive RMS Jitter
Integration Bandwidth
1 MHz to 20 MHz
(Note 16)
Vcco = 3.3 V,
CL ≤ 5 pF
100 MHz, Input Slew
rate ≥ 3 V/ns 95 fs
Noise Floor Noise Floor
fOFFSET ≥ 10 MHz
Vcco = 3.3 V,
CL ≤ 5 pF
100 MHz, Input Slew
rate ≥ 3 V/ns -159.3 dBc/Hz
DUTY Duty Cycle (Note 20) 50% input clock duty cycle 45 55 %
VOH Output High Voltage 1 mA load
Vcco -
0.1 V
VOL Output Low Voltage 0.1 V
IOH Output High Current (Source)
Vo = Vcco / 2
Vcco = 3.3 V 28 mA
Vcco = 2.5 V 20
IOL Output Low Current (Sink) Vcco = 3.3 V 28 mA
Vcco = 2.5 V 20
tR
Output Rise Time
20% to 80% (Note 22)250 MHz, RL = 50 Ω to GND,
CL ≤ 5 pF
225 ps
tF
Output Fall Time
80% to 20% (Note 22) 225 ps
tEN Output Enable Time (Note 23)CL ≤ 5 pF 3 cycles
tDIS Output Disable Time (Note 23) 3 cycles
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LMK00308
Symbol Parameter Conditions Min Typ Max Units
Propagation Delay and Output Skew
tPD_PECL
Propagation Delay
CLKin-to-LVPECL
RT = 160 Ω to GND,
RL = 100 Ω differential 360 ps
tPD_LVDS
Propagation Delay
CLKin-to-LVDS RL = 100 Ω differential 400 ps
tPD_HCSL
Propagation Delay
CLKin-to-HCSL (Note 22)
RT = 50 Ω to GND,
CL ≤ 5 pF 590 ps
tPD_CMOS
Propagation Delay
CLKin-to-LVCMOS (Note 22)CL ≤ 5 pF Vcco = 3.3 V 1475 ps
Vcco = 2.5 V 1550
tSK(O)
Output Skew
LVPECL/LVDS/HCSL
(Note 20, Note 22, Note 24)
Skew specified between any two CLKouts
with the same buffer type. Load conditions
per output type are the same as propagation
delay specifications.
30 50 ps
tSK(PP)
Part-to-Part Output Skew
LVPECL/LVDS/HCSL
(Note 22, Note 24)
80 ps
Note 11: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 12: See Section 14.4 Power Supply and Thermal Considerations for more information on current consumption and power dissipation calculations.
Note 13: Power supply ripple rejection, or PSRR, is defined as the single-sideband phase spur level (in dBc) modulated onto the clock output when a single-tone
sinusoidal signal (ripple) is injected onto the Vcco supply. Assuming no amplitude modulation effects and small index modulation, the peak-to-peak deterministic
jitter (DJ) can be calculated using the measured single-sideband phase spur level (PSRR) as follows: DJ (ps pk-pk) = [ (2 * 10(PSRR / 20)) / (π * fCLK) ] * 1E12
Note 14: See Section 12.1 Differential Voltage Measurement Terminology for definition of VID and VOD voltages.
Note 15: The ESR requirements stated must be met to ensure that the oscillator circuitry has no startup issues. However, lower ESR values for the crystal may
be necessary to stay below the maximum power dissipation (drive level) specification of the crystal. Refer to Section 14.2 Crystal Interface for crystal drive level
considerations.
Note 16: For the 100 MHz and 156.25 MHz clock input conditions, Additive RMS Jitter (JADD) is calculated using Method #1: JADD = SQRT(JOUT2 - JSOURCE2),
where JOUT is the total RMS jitter measured at the output driver and JSOURCE is the RMS jitter of the clock source applied to CLKin. For the 625 MHz clock input
condition, Additive RMS Jitter is approximated using Method #2: JADD = SQRT(2*10dBc/10) / (2*π*fCLK), where dBc is the phase noise power of the Output Noise
Floor integrated from 1 to 20 MHz bandwidth. The phase noise power can be calculated as: dBc = Noise Floor + 10*log10(20 MHz - 1 MHz). The additive RMS
jitter was approximated for 625 MHz using Method #2 because the RMS jitter of the clock source was not sufficiently low enough to allow practical use of Method
#1. Refer to the “Noise Floor vs. CLKin Slew Rate” and “RMS Jitter vs. CLKin Slew Rate” plots in Section 13.0 Typical Performance Characteristics.
Note 17: 156.25 MHz LVPECL clock source from LMK03806 with 20 MHz crystal reference (crystal part number: ECS-200-20-30BU-DU). JSOURCE = 190 fs RMS
(10 kHz to 1 MHz) and 195 fs RMS (12 kHz to 20 MHz). Refer to the LMK03806 datasheet for more information.
Note 18: The noise floor of the output buffer is measured as the far-out phase noise of the buffer. Typically this offset is ≥ 10 MHz, but for lower frequencies this
measurement offset can be as low as 5 MHz due to measurement equipment limitations.
Note 19: Phase noise floor will degrade as the clock input slew rate is reduced. Compared to a single-ended clock, a differential clock input (LVPECL, LVDS)
will be less susceptible to degradation in noise floor at lower slew rates due to its common mode noise rejection. However, it is recommended to use the highest
possible input slew rate for differential clocks to achieve optimal noise floor performance at the device outputs.
Note 20: Specification is guaranteed by characterization and is not tested in production.
Note 21: See Section 13.0 Typical Performance Characteristics for output operation over frequency.
Note 22: AC timing parameters for HCSL or CMOS are dependent on output capacitive loading.
Note 23: Output Enable Time is the number of input clock cycles it takes for the output to be enabled after REFout_EN is pulled high. Similarly, Output Disable
Time is the number of input clock cycles it takes for the output to be disabled after REFout_EN is pulled low. The REFout_EN signal should have an edge transition
much faster than that of the input clock period for accurate measurement.
Note 24: Output skew is the propagation delay difference between any two outputs with identical output buffer type and equal loading while operating at the same
supply voltage and temperature conditions.
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LMK00308
12.0 Measurement Definitions
12.1 Differential Voltage Measurement Terminology
The differential voltage of a differential signal can be described by two different definitions causing confusion when reading
datasheets or communicating with other engineers. This section will address the measurement and description of a differential
signal so that the reader will be able to understand and discern between the two different definitions when used.
The first definition used to describe a differential signal is the absolute value of the voltage potential between the inverting and
non-inverting signal. The symbol for this first measurement is typically VID or VOD depending on if an input or output voltage is being
described.
The second definition used to describe a differential signal is to measure the potential of the non-inverting signal with respect to
the inverting signal. The symbol for this second measurement is VSS and is a calculated parameter. Nowhere in the IC does this
signal exist with respect to ground, it only exists in reference to its differential pair. VSS can be measured directly by oscilloscopes
with floating references, otherwise this value can be calculated as twice the value of VOD as described in the first description.
Figure 1 illustrates the two different definitions side-by-side for inputs and Figure 2 illustrates the two different definitions side-by-
side for outputs. The VID (or VOD) definition show the DC levels, VIH and VOL (or VOH and VOL), that the non-inverting and inverting
signals toggle between with respect to ground. VSS input and output definitions show that if the inverting signal is considered the
voltage potential reference, the non-inverting signal voltage potential is now increasing and decreasing above and below the non-
inverting reference. Thus the peak-to-peak voltage of the differential signal can be measured.
VID and VOD are often defined as volts (V) and VSS is often defined as volts peak-to-peak (VPP).
30177607
FIGURE 1. Two Different Definitions for Differential Input Signals
30177608
FIGURE 2. Two Different Definitions for Differential Output Signals
Note 25: Refer to Application Note AN-912 Common Data Transmission Parameters and their Definitions for more information.
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LMK00308
