ON Semiconductor MC1495 Wideband Linear FourQuadrant Multiplier LINEAR FOUR-QUADRANT MULTIPLIER The MC1495 is designed for use where the output is a linear product of two input voltages. Maximum versatility is assured by allowing the user to select the level shift method. Typical applications include: multiply, divide*, square root*, mean square*, phase detector, frequency doubler, balanced modulator/demodulator, and electronic gain control. * Wide Bandwidth * Excellent Linearity: 2% max Error on X Input, 4% max Error on Y Input Over Temperature 1% max Error on X Input, 2% max Error on Y Input at + 25C * Adjustable Scale Factor, K * Excellent Temperature Stability * Wide Input Voltage Range: 10 V * 15 V Operation SEMICONDUCTOR TECHNICAL DATA 14 1 D SUFFIX PLASTIC PACKAGE CASE 751A (SO-14) *When used with an operational amplifier. 14 1 P SUFFIX PLASTIC PACKAGE CASE 646 MAXIMUM RATINGS (TA = + 25C, unless otherwise noted.) Rating Applied Voltage (V2-V1, V14-V1, V1-V9, V1-V12, V1-V4, V1-V8, V12-V7, V9-V7, V8-V7, V4-V7) Symbol Value Unit V 30 Vdc ORDERING INFORMATION V12-V9 V4-V8 (6+I13 RX) (6+I3 RY) Vdc Maximum Bias Current I3 I13 10 10 mA Operating Temperature Range MC1495 MC1495B TA Storage Temperature Range Tstg Differential Input Signal Semiconductor Components Industries, LLC, 2001 August, 2001 - Rev. 1 Device Tested Operating Temperature Range MC1495D MC1495P MC1495BP Package SO-14 TA = 0 to + 70C TA = - 40 to +125C Plastic DIP Plastic DIP C 0 to +70 - 40 to +125 C - 65 to +150 1 Publication Order Number: MC1495/D MC1495 ELECTRICAL CHARACTERISTICS (+V = + 32 V , -V = -15 V, TA = + 25C, I3 = I13 = 1.0 mA, RX = RY = 15 k, RL = 11 k, unless otherwise noted.) Characteristics Figure Linearity (Output Error in percent of full scale) TA = + 25C -10 < VX < +10 (VY = 10 V) -10 < VY < +10 (VX = 10 V) TA = TLow to THigh -10 < VX < +10 (VY = 10 V) -10 < VY < +10 (VX = 10 V) 5 Square Mode Error (Accuracy in percent of full scale after Offset and Scale Factor adjustment) TA = + 25C TA = TLow to THigh 5 Scale Factor (Adjustable) - Input Resistance (f = 20 Hz) Differential Output Resistance (f = 20 Hz) K= 2RL Symbol Min Typ Max Unit % ERX ERY - - 1.0 2.0 1.0 2.0 ERX ERY - - 1.5 3.0 2.0 4.0 ESQ % - - 0.75 1.0 - - K - 0.1 - 7 RinX RinY - - 30 20 - - M 8 RO - 300 - k Ibx, Iby - - 2.0 2.0 8.0 12 |Iiox|, |Iioy| - - 0.4 0.4 1.0 2.0 - 2.5 - - 10 20 50 100 - 20 - - - - - 3.0 80 750 30 - - - - 10.5 12 - 13 RX RY Input Bias Current A 6 TA = + 25C TA = TLow to THigh (I + I ) (I + I ) Ibx = 9 12 , Iby = 4 8 2 2 Input Offset Current |I9 - I12| |I4 - I8| A 6 TA = + 25C TA = TLow to THigh Average Temperature Coefficient of Input Offset Current TA = TLow to THigh 6 Output Offset Current |I14 - I2| 6 TA = + 25C TA = TLow to THigh Average Temperature Coefficient of Output Offset Current TA = TLow to THigh 6 Frequency Response 3.0 dB Bandwidth, RL = 11 k 3.0 dB Bandwidth, RL = 50 (Transconductance Bandwidth) 3 Relative Phase Shift Between VX and VY 1% Absolute Error Due to Input-Output Phase Shift nA/C |IOO| |TCIOO| A nA/C 9,10 BW(3dB) TBW(3dB) f f Common Mode Input Swing (Either Input) 11 Common Mode Gain (Either Input) |TClio| Vdc 11 ACM - 50 - 40 - 60 - 50 - - dB Common Mode Quiescent Output Voltage 12 VO1 VO2 - - 21 21 - - Vdc Differential Output Voltage Swing Capability 9 VO - 14 - Vpk Power Supply Sensitivity 12 S+ S- - - 5.0 10 - - mV/V Power Supply Current 12 I7 - 6.0 7.0 mA DC Power Dissipation 12 PD - 135 170 mW NOTES: 1. THigh = +70C for MC1495 = +125C for MC1495B TA = + 25C TA = TLow to THigh CMV MHz MHz kHz kHz TLow = 0C for MC1495 = - 40C for MC1495B http://onsemi.com 2 MC1495 10 X Y 6.0 KXY 4.0 10 1 k= 10 2.0 A V , GAIN (dB) VO , OUTPUT VOLTAGE (V) 8.0 20 + 0 -2.0 0 -10 -4.0 -6.0 VY -20 VX -8.0 -10 -10 -8.0 -6.0 -4.0 -2.0 0 2.0 4.0 VX, INPUT VOLTAGE (V) 6.0 8.0 -30 1.0 10 10 100 f, FREQUENCY (MHz) Figure 1. Multiplier Transfer Characteristic Figure 2. Transconductance Bandwidth + 1 Q5 Y Input 8 4 Q6 Q7 2 14 Output (KXY) - Q8 + Q2 Q1 + 4.0 k 5 6 3 Q3 500 Q4 500 9 12 - 4.0 k 4.0 k 4.0 k 500 1000 500 500 X Input 11 10 13 500 V- 7 This device contains 16 active transistors. Figure 3. Circuit Schematic V+ 0.1 F RY = 27 k RX = 7.5 k 10 k VY Es VY 10 k 4 + - VX VX 10 k 10 V 10 k 9 5 6 10 1 1 + + MC1495 3 + 7 13 k 5.0 k Scale Factor Adjust 3.0 k 10 k 40 k 1 3 14 7 8 6 MC1741C 5 13 1 33 k 12 k 10 k 7 2 2 - Offset Adjust See Figure 13 3.0 k 3.0 k 8 12 +15 V 10 k Output Offset Adjust 4 10 k 2 3 8 6 MC1741C 4 1 VE 5 V0.1 F -15 V NOTE: Adjust "Scale Factor Adjust" for a null in VE.This schematic for illustrative purposes only, not specified for test conditions. Figure 4. Linearity (Using Null Technique) http://onsemi.com 3 MC1495 RY = 15 k RX = 15 k To Pin 4 or 9 4 VY 6 10 9 VZ MC1495 12 X R1 1 9.1 k 11 32 V 0.1 F + RL1 = 11 k 8 Y Offset Adjust (See Figures 13 and 14) 5 2 14 I3 3 Plotter XInput R13 = 13.7 k R3 5.0 k Scale Factor Adjust X-Y Plotter Plotter YInput VO I13 7 13 12 k RL1 = 11 k - 0.1 F -15 V Figure 5. Linearity (Using X-Y Plotter Technique) +32 V RY = 15 k RX = 15 k 5 6 4 10 1 1 I4 9 MC1495 I9 8 3 7 13 0.1 F 0.1 F 10 MC1495 12 14 7 13 12 k Scale Factor Adjust 5.0 k 2 MC1495 0.1 F -15V e1 e2 14 11 k 12 3 7 13 12 k -2 13.75 k 0.1 F RY = 15 k RX = 15 k 4 e2 ein e1 e2 8 - Scale Factor Adjust Figure 8. Output Resistance 11 +32 V 1 9.1 k 2 MC1495 14 11 k 11 k 13 7 3 12 k -2 10 12 0.1 F 13.7 k RO = RL 5 6 9 50 + 1.0 V - e1 1.0 Vrms 20 Hz + -15 V ein = 1.0 Vrms RL = 11 k 11 k 11 k Figure 7. Input Resistance 9.1 k 2 1 1 1 9.1 k 0.1 F +32 V 1 1 1 10 +32 V 5.0 k RinX = RinY = R 9 3 8 12 k RX = 15 k 5 6 8 e2 1.0 M Figure 6. Input and Output Current 4 9 1.0 M -15 V RY = 15 k 1.0 M 5.0 k 5.0 k Scale Factor Adjust 5 6 4 e2 I13 = 1.0 mA 12 k I3 = 1.0 mA e1 5.6 k I14 14 1.0 M e1 I2 2 I8 12 I12 9.1 k 1 RY = 15 k RX = 15 k e1 = 1.0 Vrms 20 Hz 5.0 k R13 13.7 k 0.1 F 0.1 F eo CL < 3.0 pF -15 V Figure 9. Bandwidth (RL = 11 k) http://onsemi.com 4 MC1495 RY = 510 RX = 510 4 ein = 1.0 Vrms ein 5 6 10 +15 V 1 1 1 2 9 50 + - MC1495 8 4 + 9 50 14 12 1.0 V 1.0 k CMVX (f = 20 Hz) 50 3 7 Scale Factor Adjust 5.0 k 15 k 5 6 10 11 MC1495 12 4.3 k 3 7 13 13.7 k 9.1 k 2 11 k 14 11 k S+ = 22 k -15 V 1 11 k 0.1 F VO 1.0 mA VO CMVY VO or 20 log CMVX 5.0 k ACM = 20 log V+ R 2.0 k VO2 VO1 0.1 F 2N2905A or Equivalent 11 k +32 V (V+) 2.0 k 6.2 V + Figure 11. Common Mode Gain and Common Mode Input Swing 15 k 9 8 2 9.1 k -15 V Figure 10. Bandwidth (RL = 50 ) 4 12 k 0.1 F -15V +32 V 13 1.0 mA 5.0 k CL < 3.0 pF +32 V 1 1 1 14 7 12 k eo 0.1F MC1495 3 50 CMVY (f = 20 Hz) 0.1 F R13 13.7k 12 k K = 40 10 12 + 13 15 k 5 6 8 50 - 15 k -15 V (V-) S- = To Pin 8 Y Offset Adjust 0.1 F | (VO1 - VO2)| V+ V+ 15 V 32 V R 22 k 10 k V- To Pin 8 Pot #1 Y Offset Adjust 32 V 2.0 k 5.1 k Pot #2 To Pin 12 X Offset Adjust 2.0 k 10 k Figure 13. Offset Adjust Circuit R 15 V 10 k -15 V V+ V+ 10 k | (VO1 - VO2)| Figure 12. Power Supply Sensitivity R Pot #1 10 k 10 k 5.1 V Pot #2 To Pin 12 X Offset Adjust 5.1 V 2.0 k -15 V Figure 14. Offset Adjust Circuit (Alternate) http://onsemi.com 5 MC1495 0.110 1.8 1.6 1.4 K, SCALE FACTOR ERX , E RY LINEARITY (%) 2.0 ERY 1.2 1.0 0.8 ERX 0.6 0.105 K Adjusted to 0.100 at 25C 0.100 0.095 0.4 0.2 0 -55 -25 0 25 50 75 TA , AMBIENT TEMPERATURE (C) 100 -55 125 1.0 ERROR, PERCENT OF FULL SCALE (%) 0.8 0.6 0.4 0.2 0 10 12 14 16 RX or RY (k) 18 0 25 50 75 100 TA , AMBIENT TEMPERATURE (C) 1.0 0.8 0.6 0.4 0.2 0 20 VX = VY = 5.0 V Max I3 = I13 = 1.0 mAdc 4.0 Figure 17. Error Contributed by Input Differential Amplifier 6.0 8.0 10 RX or RY (k ) 12 14 Figure 18. Error Contributed by Input Differential Amplifier 14 12 10 8.0 Minimum 6.0 4.0 Recommended 2.0 0 0 2.0 4.0 6.0 125 Figure 16. Scale Factor versus Temperature VX = VY = 10 V Max I3 = I13 = 1.0 mAdc |VX| or | VY |, MAXIMUM (Vpk ) ERROR, PERCENT OF FULL SCALE (%) Figure 15. Linearity versus Temperature -25 8.0 10 12 14 |V1| or |V7| (V) Figure 19. Maximum Allowable Input Voltage versus Voltage at Pin 1 or Pin 7 http://onsemi.com 6 16 18 MC1495 OPERATION AND APPLICATIONS INFORMATION Theory of Operation be ignored. Figures 17 and 18 show the error expected from this source as a function of the values of RX and RY with an operating current of 1.0 mA in each side of the differential amplifiers (i.e., I3 = I13 = 1.0 mA). The MC1495 is a monolithic, four-quadrant multiplier which operates on the principle of variable transconductance. A detailed theory of operation is covered in Application Note AN489, Analysis and Basic Operation of the MC1595. The result of this analysis is that the differential output current of the multiplier is given by: IA - IB = I = 3 dB Bandwidth and Phase Shift Bandwidth is primarily determined by the load resistors and the stray multiplier output capacitance and/or the operational amplifier used to level shift the output. If wideband operation is desired, low value load resistors and/or a wideband operational amplifier should be used. Stray output capacitance will depend to a large extent on circuit layout. Phase shift in the multiplier circuit results from two sources: phase shift common to both X and Y channels (due to the load resistor-output capacitance pole mentioned above) and relative phase shift between X and Y channels (due to differences in transadmittance in the X and Y channels). If the input to output phase shift is only 0.6, the output product of two sine waves will exhibit a vector error of 1%. A 3 relative phase shift between VX and VY results in a vector error of 5%. 2VXVY RXRYI3 where, IA and IB are the currents into Pins 14 and 2, respectively, and VX and VY are the X and Y input voltages at the multiplier input terminals. DESIGN CONSIDERATIONS General The MC1495 permits the designer to tailor the multiplier to a specific application by proper selection of external components. External components may be selected to optimize a given parameter (e.g. bandwidth) which may in turn restrict another parameter (e.g. maximum output voltage swing). Each important parameter is discussed in detail in the following paragraphs. Maximum Input Voltage VX(max), VY(max) input voltages must be such that: Linearity, Output Error, ERX or ERY VX(max) <I13 RY VY(max) <I3 RY Linearity error is defined as the maximum deviation of output voltage from a straight line transfer function. It is expressed as error in percent of full scale (see figure below). Exceeding this value will drive one side of the input amplifier to "cutoff" and cause nonlinear operation. Current I3 and I13 are chosen at a convenient value (observing power dissipation limitation) between 0.5 mA and 2.0 mA, approximately 1.0 mA. Then RX and RY can be determined by considering the input signal handling requirements. VO +10 V VE(max) +10V Vx or Vy For VX(max) = VY(max) = 10 V; For example, if the maximum deviation, VE(max), is 100 mV and the full scale output is 10 V, then the percentage error is: ER = 10 V = 10 k. 1.0 mA 2VX VY The equation IA - IB = RX RY I3 RX = RY > VE(max) 100 x 10-3 x 100 = 1.0%. x 100 = VO(max) 10 is derived from IA - IB = Linearity error may be measured by either of the following methods: 1. Using an X-Y plotter with the circuit shown in Figure 5, obtain plots for X and Y similar to the one shown above. 2. Use the circuit of Figure 4. This method nulls the level shifted output of the multiplier with the original input. The peak output of the null operational amplifier will be equal to the error voltage, VE (max). One source of linearity error can arise from large signal nonlinearity in the X and Y input differential amplifiers. To avoid introducing error from this source, the emitter degeneration resistors RX and RY must be chosen large enough so that nonlinear base-emitter voltage variation can 2VX VY 2kT (RX + ) (RY + 2kT ) I3 qI3 qI13 2kT . with the assumption RX >> 2kT and RY >> qI3 qI13 At TA = +25C and I13 = I3 = 1.0 mA, 2kT 2kT = = 52 . qI13 qI3 Therefore, with RX = RY = 10 k the above assumption is valid. Reference to Figure 19 will indicate limitations of VX(max) or VY(max) due to V1 and V7. Exceeding these limits will cause saturation or "cutoff" of the input transistors. See Step 4 of General Design Procedure for further details. http://onsemi.com 7 MC1495 Maximum Output Voltage Swing If an operational amplifier is used for level shift, as shown in Figure 21, the output swing (of the multiplier) is greatly reduced. See Section 3 for further details. The maximum output voltage swing is dependent upon the factors mentioned below and upon the particular circuit being considered. For Figure 20 the maximum output swing is dependent upon V+ for positive swing and upon the voltage at Pin 1 for negative swing. The potential at Pin 1 determines the quiescent level for transistors Q5, Q6, Q7 and Q8. This potential should be related so that negative swing at Pins 2 or 14 does not saturate those transistors. See General Design Procedure for further information regarding selection of these potentials. GENERAL DESIGN PROCEDURE Selection of component values is best demonstrated by the following example. Assume resistive dividers are used at the X and Y-inputs to limit the maximum multiplier input to 5.0 V [VX = VY(max)] for a 10 V input [VX = VY(max)] (see Figure 21). If an overall scale factor of 1/10 is desired, V+ RX 9 VX 12 4 VY 8 10 11 RY RI 5 6 1 + + RL VO 14 - MC1495 - 13 3 I3 R3 Therefore, K = 4/10 for the multiplier (excluding the divider network). Step 1. The fist step is to select current I3 and current I13. There are no restrictions on the selection of either of these currents except the power dissipation of the device. I3 and I13 will normally be 1.0 mA or 2.0 mA. Further, I3 does not have to be equal to I13, and there is normally no need to make them different. For this example, let RL 2 + VX VY (2VX) (2VY) = 4/10 VX VY = 10 10 then, VO = VO = K VX VY 2RL K= RX RY I3 7 R13 I3 = I13 = 1.0 mA. V- Figure 20. Basic Multiplier - 15 V - 15 V VY 10 k 10 k VX 10 k 10 k 4 10 + VY RX 10 k RY 10 k 11 5 6 7 1 R0 3.0 k 2 + 0.1 F R0 3.0 k 3 9 7 + VX + 3 13 I13 I3 R3 Scale Factor Adjust +15 V 8 2 12 R13 12 k Y Offset Adjust 2.0 k 5.1 V 6 RL 5.0 k P4 P1 10 k 5 1 18 k 5.0 k P3 4 MC1741C 14 Output Offset Adjust 20 k RL X Offset Adjust P2 10 k 2.0 k 5.1 V -15 V Figure 21. Multiplier with Operational Amplifier Level Shift http://onsemi.com 8 +15 V 0.1 F MC1495 12 k -10V VX +10V -10V VY +10V R1 3.0 k VO = -VX VY 10 MC1495 diode-drops below the voltage at Pin 1. Thus, the voltage at Pin 1 should be about 2.0 V higher than the maximum input voltage. Therefore, to handle +5.0 V at the inputs, the voltage at Pin 1 must be at least +7.0 V. Let V1 = 9.0 Vdc. Since the current flowing into Pin 1 is always equal to 2I3, the voltage at Pin 1 can be set by placing a resistor (R1) from Pin 1 to the positive supply: To set currents I3 and I13 to the desired value, it is only necessary to connect a resistor between Pin 13 and ground, and between Pin 3 and ground. From the schematic shown in Figure 3, it can be seen that the resistor values necessary are given by: R13 + 500 = |V-| -0.7 V I13 |V-| -0.7 V R3 + 500 = I3 R1 = V+ -V1 2I3 Let V+ = 15 V, then R1 = Let V- = -15 V, then R13 + 500 = 14.3 V or R13 = 13.8 k 1.0 mA R1 = 3.0 k. Let R13 = 12 k. Similarly, R3 = 13.8 k, let R3 = 15 k Note that the voltage at the base of transistors Q5, Q6, Q7 and Q8 is one diode-drop below the voltage at Pin 1. Thus, in order that these transistors stay active, the voltage at Pins 2 and 14 should be approximately halfway between the voltage at Pin 1 and the positive supply voltage. For this example, the voltage at Pins 2 and 14 should be approximately 11 V. Step 5. For dc applications, such as the multiply, divide and square-root functions, it is usually desirable to convert the differential output to a single-ended output voltage referenced to ground. The circuit shown in Figure 22 performs this function. It can be shown that the output voltage of this circuit is given by: However, for applications which require an accurate scale factor, the adjustment of R3 and consequently, I3, offers a convenient method of making a final trim of the scale factor. For this reason, as shown in Figure 21, resistor R3 is shown as a fixed resistor in series with a potentiometer. For applications not requiring an exact scale factor (balanced modulator, frequency doubler, AGC amplifier, etc.) Pins 3 and 13 can be connected together and a single resistor from Pin 3 to ground can be used. In this case, the single resistor would have a value of 1/2 the above calculated value for R13. Step 2. The next step is to select RX and RY. To insure that the input transistors will always be active, the following conditions should be met: VX < I13, RX VO = (I2 -I14) RL VY < I3 RY And since IA -IB = I2 -I14 = A good rule of thumb is to make I3RY 1.5 VY(max) and I13 RX 1.5 VX(max). The larger the I3RY and I13RX product in relation to VY and VX respectively, the more accurate the multiplier will be (see Figures 17 and 18). Let RX = RY then I3RY I13RX 2RL RX RY I3 = 2IX IY 2VXVY = I3RXRY I3 2RL VX VY where, VX VY is the voltage at 4RX RX I3 the input to the voltage dividers. then VO = = 10 k, = 10 V = 10 V V+ since VX(max) = VY(max) = 5.0 V, the value of RX= RY = 10 k is sufficient. Step 3. Now that RX, RY and I3 have been chosen, RL can be determined: K= 15 V -9.0 V (2) (1.0 mA) I2 I14 4 (2) (RL) 4 = , or 10 (10 k) (10 k) (1.0 mA) 10 RO V2 V14 RL Thus RL = 20 k. Step 4. To determine what power supply voltage is necessary for this application, attention must be given to the circuit schematic shown in Figure 3. From the circuit schematic it can be seen that in order to maintain transistors Q1, Q2, Q3 and Q4 in an active region when the maximum input voltages are applied (VX = VY = 10 V or VX = 5.0 V, VY = 5.0 V), their respective collector voltage should be at least a few tenths of a volt higher than the maximum input voltage. It should also be noticed that the collector voltage of transistors Q3 and Q4 is at a potential which is two RO + VO RL Figure 22. Level Shift Circuit The choice of an operational amplifier for this application should have low bias currents, low offset current, and a high common mode input voltage range as well as a high common mode rejection ratio. The MC1456, and MC1741C operational amplifiers meet these requirements. http://onsemi.com 9 MC1495 The versatility of the MC1495 allows the user to to optimize its performance for various input and output signal levels. Referring to Figure 21, the level shift components will be determined. When VX = VY = 0, the currents I2 and I14 will be equal to I13. In Step 3, RL was found to be 20 k and in Step 4, V2 and V14 were found to be approximately 11 V. From this information RO can be found easily from the following equation (neglecting the operational amplifiers bias current): V2 I = RL + 13 OFFSET AND SCALE FACTOR ADJUSTMENT Offset Voltages Within the monolithic multiplier (Figure 3) transistor base- emitter junctions are typically matched within 1.0 mV and resistors are typically matched within 2%. Even with this careful matching, an output error can occur. This output error is comprised of X-input offset voltage, Y-input offset voltage, and output offset voltage. These errors can be adjusted to zero with the techniques shown in Figure 21. Offset terms can be shown analytically by the transfer function: V+ -V2 RO And for this example, 11 V + 1.0 mA = 15 V -11 V 20 k RO Solving for RO: RO = 2.6 k, thus, select RO = 3.0 k For RO = 3.0 k, the voltage at Pins 2 and 14 is calculated to be: V2 = V14 = 10.4 V. VO = K[Vx Viox Vx(off)] [Vy Vioy Vy(off)] VOO The linearity of this circuit (Figure 21) is likely to be as good or better than the circuit of Figure 5. Further improvements are possible as shown in Figure 23 where RY has been increased substantially to improve the Y linearity, and RX decreased somewhat so as not to materially affect the X linearity. This avoids increasing RL significantly in order to maintain a K of 0.1. Where: K Vx Vy Viox Vioy = scale factor = ``x'' input voltage = ``y'' input voltage = ``x'' input offset voltage = ``y'' input offset voltage Vx(off) = ``x'' input offset adjust voltage Vy(off) = ``y'' input offset adjust voltage VOO = output offset voltage. - 15 V - 15 V +15 V 7.5 k VY 10 V VX 10 k 4 10 + 5 11 3.0 k 3.0 k 27 k 6 7 3.0 k 7 1 14 - 3 + 4 10 k 10 k 10 k 9 + 3 8 +15 V 2 12 13 k 5.0 k Scale Factor Adjust 2 + 13 5 1 33 k 12 k 10 k Output Offset Adjust X Offset Adjust Y Offset Adjust 15 k 6 MC1741C MC1495 20 k 15 k 20 k 2.0 k -15 V 2.0 k Figure 23. Multiplier with Improved Linearity http://onsemi.com 10 40 k VO = -VX VY 10 (1) MC1495 X, Y and Output Offset Voltages VO Output Offset Vx VO The ability to accurately adjust the MC1495 depends upon the characteristics of potentiometers P1 through P4. Multi-turn, infinite resolution potentiometers with low temperature coefficients are recommended. Output Offset Vy DC APPLICATIONS X Offset Y Offset Multiply The circuit shown in Figure 21 may be used to multiply signals from dc to 100 kHz. Input levels to the actual multiplier are 5.0 V (max). With resistive voltage dividers the maximum could be very large however, for this application two-to-one dividers have been used so that the maximum input level is 10 V. The maximum output level has also been designed for 10 V (max). For most dc applications, all three offset adjust potentiometers (P1, P2, P4) will be necessary. One or more offset adjust potentiometers can be eliminated for ac applications (see Figures 28, 29, 30, 31). If well regulated supply voltages are available, the offset adjust circuit of Figure 13 is recommended. Otherwise, the circuit of Figure 14 will greatly reduce the sensitivity to power supply changes. Squaring Circuit If the two inputs are tied together, the resultant function is squaring; that is VO = KV2 where K is the scale factor. Note that all error terms can be eliminated with only three adjustment potentiometers, thus eliminating one of the input offset adjustments. Procedures for nulling with adjustments are given as follows: Scale Factor The scale factor K is set by P3 (Figure 21). P3 varies I3 which inversely controls the scale factor K. It should be noted that current I3 is one-half the current through R1. R1 sets the bias level for Q5, Q6, Q7, and Q8 (see Figure 3). Therefore, to be sure that these devices remain active under all conditions of input and output swing, care should be exercised in adjusting P3 over wide voltage ranges (see General Design Procedure). A. AC Procedure: 1. Connect oscillator (1.0 kHz, 15 Vpp) to input. 2. Monitor output at 2.0 kHz with tuned voltmeter and adjust P3 for desired gain. (Be sure to peak response of the voltmeter.) 3. Tune voltmeter to 1.0 kHz and adjust P1 for a minimum output voltage. 4. Ground input and adjust P4 (output offset) for 0 Vdc output. 5. Repeat steps 1 through 4 as necessary. Adjustment Procedures The following adjustment procedure should be used to null the offsets and set the scale factor for the multiply mode of operation, (see Figure 21). 1. X-Input Offset (a) Connect oscillator (1.0 kHz, 5.0 Vpp sinewave) to the Y-input (Pin 4). (b) Connect X-input (Pin 9) to ground. (c) Adjust X offset potentiometer (P2) for an ac null at the output. 2. Y-Input Offset (a) Connect oscillator (1.0 kHz, 5.0 Vpp sinewave) to the X-input (Pin 9). (b) Connect Y-input (Pin 4) to ground. (c) Adjust Y offset potentiometer (P1) for an ac null at the output. 3. Output Offset (a) Connect both X and Y-inputs to ground. (b) Adjust output offset potentiometer (P4) until the output voltage (VO) is 0 Vdc. 4. Scale Factor (a) Apply +10 Vdc to both the X and Y-inputs. (b) Adjust P3 to achieve + 10 V at the output. 5. Repeat steps 1 through 4 as necessary. B. DC Procedure: 1. Set VX = VY = 0 V and adjust P4 (output offset potentiometer) such that VO = 0 Vdc 2. Set VX = VY = 1.0 V and adjust P1 (Y-input offset potentiometer) such that the output voltage is + 0.100 V. 3. Set VX = VY = 10 Vdc and adjust P3 such that the output voltage is + 10 V. 4. Set VX = VY = -10 Vdc. Repeat steps 1 through 3 as necessary. KVX VY I1 X R1 VX I2 VZ R2 + Figure 24. Basic Divide Circuit http://onsemi.com 11 VY MC1495 Divide Circuit or from Equation (5), E R2 E KVX = PED = R1 VZ R1 VZ R2 K VX Consider the circuit shown in Figure 24 in which the multiplier is placed in the feedback path of an operational amplifier. For this configuration, the operational amplifier will maintain a "virtual ground" at the inverting (-) input. Assuming that the bias current of the operational amplifier is negligible, then I1 = I2 and, KVXVY R1 = -VZ R2 From Equation 7, the percentage error is inversely related to voltage VZ (i.e., for increasing values of VZ, the percentage error decreases). A circuit that performs the divide function is shown in Figure 25. Two things should be emphasized concerning Figure 25. 1. The input voltage (VX) must be greater than zero and must be positive. This insures that the current out of Pin 2 of the multiplier will always be in a direction compatible with the polarity of VZ. 2. Pin 2 and 14 of the multiplier have been interchanged in respect to the operational amplifiers input terminals. In this instance, Figure 25 differs from the circuit connection shown in Figure 21; necessitated to insure negative feedback around the loop. (1) Solving for VY, VY = -R1 VZ R2 K VX (2) If R1=R2, VY = -VZ KVX (3) If R1= KR2, VY = -VZ VX (4) Hence, the output voltage is the ratio of VZ to VX and provides a divide function. This analysis is, of course, the ideal condition. If the multiplier error is taken into account, the output voltage is found to be: VY = - E R1 VZ + R2 K VX KVX A suggested adjustment procedure for the divide circuit. 1. Set VZ = 0 V and adjust the output offset potentiometer (P4) until the output voltage (VO) remains at some (not necessarily zero) constant value as VX is varied between +1.0 V and +10 V. 2. Keep VZ at 0 V, set VX at +10 V and adjust the Y input offset potentiometer (P1) until VO = 0 V. 3. Let VX = VZ and adjust the X-input offset potentiometer (P2) until the output voltage remains at some (not necessarily - 10 V) constant value as VZ = VX is varied between +1.0 and +10 V. 4. Keep VX = VZ and adjust the scale factor potentiometer (P3) until the average value of VO is -10 V as VZ = VX is varied between +1.0 V and +10 V. 5. Repeat steps 1 through 4 as necessary to achieve optimum performance. (5) where E is the error voltage at the output of the multiplier. From this equation, it is seen that divide accuracy is strongly dependent upon the accuracy at which the multiplier can be set, particularly at small values of VY. For example, assume that R1 = R2, and K = 1/10. For these conditions the output of the divide circuit is given by: VY = -10 VZ 10 E + VX VX (6) From Equation 6, it is seen that only when VX = 10 V is the error voltage of the divide circuit as low as the error of the multiply circuit. For example, when VX is small, (0.1 V) the error voltage of the divide circuit can be expected to be a hundred times the error of the basic multiplier circuit. In terms of percentage error, percentage error = (7) error x 100% actual http://onsemi.com 12 MC1495 - 15 V 4 RY 10 k RX 10 k 10 k 11 10 + - 15 V 5 3.9 k 6 7 3.0 k 3 14 - + 10 k 10 k 9 10 k + 13 13 k 8 6 VO = 1 18 k 5.0 k To Offset Adjust (See Figure 13) P4 VO 5 - 12 12 k 5.0 k P3 Scale Factor Adjust 2 2 + 3 4 MC1741C MC1495 VX 0.1 F 7 1 +15 V 0.1 F 3.0 k VZ 20 k Output Offset Adjust -10 VZ VX 0 VX +10 V -10 V VZ +10 V Figure 25. Divide Circuit KVO2 + VZ MC1495 AC APPLICATIONS + The applications that follow demonstrate the versatility of the monolithic multiplier. If a potted multiplier is used for these cases, the results generally would not be as good because the potted units have circuits that, although they optimize dc multiplication operation, can hinder ac applications. Frequency doubling often is done with a diode where the fundamental plus a series of harmonics are generated. However, extensive filtering is required to obtain the desired harmonic, and the second harmonic obtained under this technique usually is small in magnitude and requires amplification. When a multiplier is used to double frequency the second harmonic is obtained directly, except for a dc term, which can be removed with ac coupling. + + VO KVO2 = -VZ or VO = |VZ| K Figure 26. Basic Square Root Circuit Square Root A special case of the divide circuit in which the two inputs to the multiplier are connected together is the square root function as indicated in Figure 26. This circuit may suffer from latch-up problems similar to those of the divide circuit. Note that only one polarity of input is allowed and diode clamping (see Figure 27) protects against accidental latch-up. This circuit also may be adjusted in the closed-loop mode as follows: 1. Set VZ to -0.01 V and adjust P4 (output offset) for VO = +0.316 V, being careful to approach the output from the positive side to preclude the effect of the output diode clamping. 2. Set VZ to -0.9 V and adjust P2 (X adjust) for VO = +3.0 V. 3. Set VZ to -10 V and adjust P3 (scale factor adjust) for VO = +10 V. 4. Steps 1 through 3 may be repeated as necessary to achieve desired accuracy. eo = KE2 cos2 t eo = KE2 (1 + cos 2t). 2 A potted multiplier can be used to obtain the double frequency component, but frequency would be limited by its internal level-shift amplifier. In the monolithic units, the amplifier is omitted. In a typical doubler circuit, conventional 15 V supplies are used. An input dynamic range of 5.0 V peak-to-peak is allowed. The circuit generates wave-forms that are double frequency; less than 1% distortion is encountered without filtering. The configuration has been successfully used in excess of 200 kHz; reducing the scale factor by decreasing the load resistors can further expand the bandwidth. Figure 29 represents an application for the monolithic multiplier as a balanced modulator. Here, the audio input signal is 1.6 kHz and the carrier is 40 kHz. http://onsemi.com 13 MC1495 - 15 V RX 10 k 10 k RY 10 k 11 10 + 4 - 15V 3.9 k 5 6 7 3.0 k 3.0 k 1 2 - 3 + 13 13 k 5.0 k Scale Factor Adjust 14 + 3 8 2 12 5 - 6 VO VO = (11 V) 1 13 k 12 k To Offset Adjust (See Figure 13) P3 4 MC1741C + 10 k 0.1 F 7 MC1495 9 +15 V 0.1 F 5.0 k P4 Output Offset Adjust 10 |VZ| VZ 20 k RL -10 VZ +0 V Figure 27. Square Root Circuit RY 8.2 k 5 4 E cos t (< 5.0 Vpp) Offset Adjust 6 VCC +15 V RX 8.2 k 10 11 MC1495 8 12 14 3 6.8 k 13 eY = E cos mt R1 3.3 k eX = E cos ct Offset Y Adjust X C1* 7 *Select 2 eo E cos 2 t 20 1.0 F 4 5 10 11 13 C1* 7 *Select 1.0 F + (B) Figure 28. Frequency Doubler Figure 29. Balanced Modulator 14 RL 3.3 k 14 12 -15 V http://onsemi.com + 1.0 F - 1 3.0 k RL 2 3.3 k MC1495 8 6.8 k When two equal cosine waves are applied to X and Y, the result is a wave shape of twice the input frequency. For this example the input was a 10 kHz signal, output was 20 kHz. 6 9 3 -15 V +15 V RX 8.2 k RY 8.2 k + 1.0 F - R1 2 3.3 k 9 Y R1 1 3.0 k (A) eo MC1495 The defining equation for balanced modulation is modulating signal with the Y-offset adjust potentiometer (see Figure 30). K(Emcos mt) (Ec cos ct) = Here, the identity is: KEc Em [ cos (c + m)t + cos (c - m) t ] 2 Em(1 + m cos mt) Ec cos ct = KEmEccos ct + KEmEcm [ cos(c + m)t + cos (c - m) t ] 2 where c is the carrier frequency, m is the modulator frequency and K is the multiplier gain constant. AC coupling at the output eliminates the need for level translation or an operational amplifier; a higher operating frequency results. A problem common to communications is to extract the intelligence from single-sideband received signal. The ssb signal is of the form: where m indicates the degrees of modulation. Since m is adjustable, via potentiometer P1, 100% modulation is possible. Without extensive tweaking, 96% modulation may be obtained where c and m are the same as in the balanced modulator example. essb = A cos (c + m) t Linear Gain Control To obtain linear gain control, the designer can feed to one of the two MC1495 inputs a signal that will vary the unit's gain. The following example demonstrates the feasibility of this application. Suppose a 200 kHz sinewave, 1.0 V peak-to-peak, is the signal to which a gain control will be added. The dynamic range of the control voltage VC is 0 V to +1.0 V. These must be ascertained and the proper values of RX and RY can be selected for optimum performance. For the 200 kHz operating frequency, load resistors of 100 were chosen to broaden the operating bandwidth of the multiplier, but gain was sacrificed. It may be made up with an amplifier operating at the appropriate frequency (see Figure 31). and if multiplied by the appropriate carrier waveform, cos ct, essbecarrier = AK [cos (2 + )t + cos ( ) t ]. c m c 2 If the frequency of the band-limited carrier signal (c) is ascertained in advance, the designer can insert a low pass filter and obtain the (AK/2) (cosct) term with ease. He/she also can use an operational amplifier for a combination level shift-active filter, as an external component. But in potted multipliers, even if the frequency range can be covered, the operational amplifier is inside and not accessible, so the user must accept the level shifting provided, and still add a low pass filter. Amplitude Modulation The multiplier performs amplitude modulation, similar to balanced modulation, when a dc term is added to the RY 8.2 k 4 eY = E cos mt Offset Adjust 6 10 11 Y 8 X 12 R1 1 3.0 k RL1 2 3.3 k 9 eX = E cos mt % Modulation Adjust 5 VCC = +15 V RX 8.2 k MC1495 RL1 3.3 k 14 3 13 C1* 7 *Select eX, eY < 5.0 Vpp 6.8 k 1.0 F eo -15 V Figure 30. Amplitude Modulation The signal is applied to the unit's Y-input. Since the total input range is limited to 1.0 Vpp, a 2.0 V swing, a current source of 2.0 mA and an RY value of 1.0 k is chosen. This takes best advantage of the dynamic range and insures linear operation in the Y-channel. Since the X-input varies between 0 and +1.0 V, the current source selected was 1.0 mA, and the RX value chosen was 2.0 k. This also insures linear operation over the X-input dynamic range. Choosing RL = 100 assures wide bandwidth operation. http://onsemi.com 15 MC1495 Hence, the scale factor for this configuration is: RL RX RY I3 = 100 (2 k) (1 k) (2 x 103) = 1 V-1 40 2.0 k Y Vin 4 51 VC 1.0 k X 0.1 F Offset Adjust 9 Y 8 X 12 10 11 V-1 +12 V 1.0 k 5 6 2 MC1495 1 k = 40 100 100 14 3 13 7 5.0 k 0.75 0.5 0.25 Amplifier AV = 40 2.0 mA 3.0 k Vin = 1.0 Vpp 200 kHz 1.0 1 1.5 k + + 1.25 V O (Vpp ) K= The 2 in the numerator of the equation is missing in this scale factor expression because the output is single-ended and ac coupled. VO 0 0 0.2 0.4 0.6 0.8 VAGC (V) 1.0 11 k 1.0 F + P3 NOTE: -12 V Linear gain control of a 1.0 Vpp signal is performed with a 0 V to 1.0 V control voltage. If VC is 0.5 V the output will be 0.5 Vpp. Figure 31. Linear Gain Control http://onsemi.com 16 1.2 MC1495 PACKAGE DIMENSIONS D SUFFIX PLASTIC PACKAGE CASE 751A-03 ISSUE F NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. -A- 14 8 -B- 1 P 7 PL 0.25 (0.010) 7 G M B M F R X 45 C -T- SEATING PLANE 0.25 (0.010) M T B J M K D 14 PL S A S http://onsemi.com 17 DIM A B C D F G J K M P R MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0 7 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0 7 0.228 0.244 0.010 0.019 MC1495 PACKAGE DIMENSIONS P SUFFIX PLASTIC PACKAGE CASE 646-06 ISSUE M 14 8 1 7 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. B A F L N C -T- SEATING PLANE J K H G D 14 PL M 0.13 (0.005) M http://onsemi.com 18 DIM A B C D F G H J K L M N INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.290 0.310 --10 0.015 0.039 MILLIMETERS MIN MAX 18.16 18.80 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.37 7.87 --10 0.38 1.01 MC1495 Notes http://onsemi.com 19 MC1495 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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