Wideband Linear
FourQuadrant Multiplier
The MC1495 is designed for use where the output is a linear product
of two input voltages. Maximum versatility is assured by allowing the
user to select the level shift method. Typical applications include:
multiply, divide*, square root*, mean square*, phase detector,
frequency doubler, balanced modulator/demodulator, and electronic
gain control.
•Wide Bandwidth
•Excellent Linearity:
2% max Error on X Input, 4% max Error on Y Input Over
Temperature
1% max Error on X Input, 2% max Error on Y Input at + 25°C
•Adjustable Scale Factor, K
•Excellent Temperature Stability
•Wide Input Voltage Range: ± 10 V
•±15 V Operation
*When used with an operational amplifier.
MAXIMUM RATINGS (TA = + 25°C, unless otherwise noted.)
Rating Symbol Value Unit
Applied Voltage
(V2–V1, V14–V1, V1–V9, V1–V12,
V1–V4, V1–V8, V12–V7, V9–V7,
V8–V7, V4–V7)
∆V 30 Vdc
Differential Input Signal V12–V9
V4–V8±(6+I13 RX)
±(6+I3 RY)Vdc
Maximum Bias Current I3
I13 10
10 mA
Operating Temperature Range
MC1495
MC1495B
TA0 to +70
– 40 to +125
°C
Storage Temperature Range Tstg – 65 to +150 °C
ON Semiconductor
Semiconductor Components Industries, LLC, 2001
August, 2001 – Rev. 1 1Publication Order Number:
MC1495/D
LINEAR
FOUR-QUADRANT
MULTIPLIER
SEMICONDUCTOR
TECHNICAL DATA
MC1495
P SUFFIX
PLASTIC PACKAGE
CASE 646
D SUFFIX
PLASTIC PACKAGE
CASE 751A
(SO-14)
1
14
1
14
ORDERING INFORMATION
Package
Tested Operating
Temperature Range
Device
MC1495D TA = 0° to + 70°C
MC1495P
MC1495BP
SO–14
Plastic DIP
Plastic DIPTA = – 40° to +125°C
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ELECTRICAL CHARACTERISTICS (+V = + 32 V , –V = –15 V, TA = + 25°C, I3 = I13 = 1.0 mA, RX = RY = 15 kΩ, RL = 11 kΩ,
unless otherwise noted.)
Characteristics Figure Symbol Min Typ Max Unit
Linearity (Output Error in percent of full scale)
TA = + 25°C
–10 < VX < +10 (VY = ±10 V)
–10 < VY < +10 (VX = ±10 V)
TA = TLow to THigh
–10 < VX < +10 (VY = ±10 V)
–10 < VY < +10 (VX = ±10 V)
5
ERX
ERY
ERX
ERY
–
–
–
–
±1.0
±2.0
±1.5
±3.0
±1.0
±2.0
±2.0
±4.0
%
Square Mode Error (Accuracy in percent of full scale after
Offset and Scale Factor adjustment)
TA = + 25°C
TA = TLow to THigh
5 ESQ
–
–±0.75
±1.0 –
–
%
Scale Factor (Adjustable) 2RL
K = 13 RX RY
– K – 0.1 –
Input Resistance (f = 20 Hz) 7 RinX
RinY –
–30
20 –
–MΩ
Differential Output Resistance (f = 20 Hz) 8 RO– 300 – kΩ
Input Bias Current
2
(I9 + I12)
2
Ibx = , Iby = (I4 + I8)TA = + 25°C
TA = TLow to THigh
6Ibx, Iby –
–2.0
2.0 8.0
12
µA
Input Offset Current
|I9 – I12|T
A = + 25°C
|I4 – I8|T
A = TLow to THigh
6|Iiox|, |Iioy| –
–0.4
0.4 1.0
2.0
µA
Average Temperature Coefficient of Input Offset Current
TA = TLow to THigh 6 |TClio|– 2.5 – nA/°C
Output Offset Current TA = + 25°C
|I14 – I2|T
A = TLow to THigh 6 |IOO|–10
20 50
100 µA
Average Temperature Coefficient of Output Offset Current
TA = TLow to THigh 6 |TCIOO|– 20 – nA/°C
Frequency Response
3.0 dB Bandwidth, RL = 11 kΩ
3.0 dB Bandwidth, RL = 50 Ω (Transconductance Bandwidth)
3° Relative Phase Shift Between VX and VY
1% Absolute Error Due to Input-Output Phase Shift
9,10 BW(3dB)
TBW(3dB)
fφ
fθ
–
–
–
–
3.0
80
750
30
–
–
–
–
MHz
MHz
kHz
kHz
Common Mode Input Swing
(Either Input) 11 CMV ±10.5 ±12 – Vdc
Common Mode Gain TA = + 25°C
(Either Input) TA = TLow to THigh 11 ACM –50
–40 –60
–50 –
–dB
Common Mode Quiescent
Output Voltage 12 VO1
VO2 –
–21
21 –
–Vdc
Differential Output Voltage Swing Capability 9 VO–±14 – Vpk
Power Supply Sensitivity 12 S+
S––
–5.0
10 –
–mV/V
Power Supply Current 12 I7– 6.0 7.0 mA
DC Power Dissipation 12 PD– 135 170 mW
NOTES: 1.THigh = +70°C for MC1495 TLow = 0°C for MC1495
= +125°C for MC1495B = – 40°C for MC1495B
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k = 1
10
-10 -8.0 -6.0 -4.0 -2.0 0 2.0 4.0 6.0 8.0 10
VX, INPUT VOLTAGE (V)
-10
-8.0
-4.0
-2.0
0
2.0
-6.0
4.0
6.0
8.0
10
, OUTPUT VOLTAGE (V)
O
V
+
X
YKXY
20
10
0
-10
-20
-301.0 10 100 100
0
VYVX
f, FREQUENCY (MHz)
, GAIN (dB)
V
A
Figure 1. Multiplier Transfer Characteristic Figure 2. Transconductance Bandwidth
Figure 3. Circuit Schematic
Figure 4. Linearity (Using Null Technique)
+
-
0.1 µF
VE
V′Y
V′X
10 k
10 k
10 k VX
VY
3.0 k 40 k 10 k
2
3
1
2
14
12 3 13
13 k 12 k
5.0 k
10 V 9
8
5 6 10 1
1
MC1495
Offset Adjust
See Figure 13
Scale
Factor
Adjust
7
-
+
+
+
33 k
Output
Offset
Adjust
7
8
5
1
4
62
3
7
8
6
4
15
Es
MC1741C
NOTE: Adjust “Scale Factor Adjust” for a null in VE.This schematic for
illustrative purposes only, not specified for test conditions.
10 k
3.0 k
3.0 k
0.1 µF
10 k
10 k
10 k
4
RY = 27 k RX = 7.5 k
MC1741C
V-
-15 V
V+
+15 V
1
8
4
5
6
3
V- 7
500 500 500 500 500 500
2
14
9
12
11
10
13
4.0 k
Q4
Q8Q7Q6Q5
+
-
+
-
X Input
Q3Q2
Q1
4.0 k
Y Input
+
-
4.0 k
Output (KXY)
4.0 k
This device contains 16 active transistors.
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RL1 = 11 k
Figure 5. Linearity (Using X-Y Plotter Technique)
RY = 15 k RX = 15 k
To Pin
4 or 9
VY
VZ
Y
X
Offset Adjust
(See Figures 13 and 14)
56 1011
1
2
14
RL1 = 11 k Plotter
YInput
X-Y
Plotter
I13
I3
R3
+-
32 V
R1
9.1 k
R13 = 13.7 k
-15 V
4
9
8
12
3
12 k
5.0 k
Scale
Factor
Adjust
MC1495
0.1 µF
0.1 µF
Plotter
XInput
VO
713
Figure 6. Input and Output Current Figure 7. Input Resistance
Figure 8. Output Resistance Figure 9. Bandwidth (RL = 11 kΩ)
RY = 15 k RX = 15 k
4
9
8
12
I4
I9
I8
I12 3713
12 k
5 6 10 1
1
1
2
14 I14
I2
5.6 k
9.1 k
+32 V
0.1 µF
I13 = 1.0 mA
5.0 k
-15 V
12 k
5.0 k
I3 = 1.0 mA
Scale
Factor
Adjust
5 6 10 1
1
4
9
8
12
3713
1.0 M
1.0 M
e1
e1
1.0 M
1.0 M
e2
e2
-15 V
+
-
9.1 k
11
k
11 k
13.75 k
e1 = 1.0 Vrms
20 Hz
RinX = RinY = R e1
e2-2
1
2
14
MC1495
4
9
8
12
3713
13.7 k
56 10 1
11
2
14
RL = 11 k
9.1 k 56 10 11
4
9
8
12
37
13
9.1 k
11
k
11
k
1
2
14
0.1 µF
RY = 15 k RX = 15 k +32 V
0.1 µF
0.1 µF
12 k
5.0 k
+32 V
0.1 µF
11
k
e1
1.0 Vrms
20 Hz
0.1 µF
12 k
5.0 k
Scale
Factor
Adjust
+32 V
0.1 µF
eo
0.1 µF
12 k
5.0 k
Scale
Factor
Adjust
50
+
-1.0 V
ein
ein = 1.0 Vrms
R13
13.7 k
CL < 3.0 pF
RY = 15 k RX = 15 k RY = 15 k RX = 15 k
-15V -15 V
e2
RO = RL-2
e1
e2
MC1495
MC1495
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or 20 log CMVX
VO
Figure 10. Bandwidth (RL = 50 Ω)Figure 11. Common Mode Gain and
Common Mode Input Swing
ACM = 20 log CMVY
VO
5 6 10 1
1
4
9
8
12
37
13
1.0 k
50
1
2
14
5 6 10 1
1
4
9
12
3
713
9.1 k
11
k
11
k
1
2
14
8
ein = 1.0 Vrms
50
ein
+
-1.0 V
15 k
RY = 510 RX = 510 +15 V
50
R13
13.7k
0.1 µF
eo
CL < 3.0 pF
0.1µF
12 k
5.0 k
Scale
Factor
Adjust
K = 40
+32 V
0.1 µF
VO
15 k
1.0 mA
-15V -15 V
12 k
5.0 k
0.1 µF
5.0 k
12 k
50
50
+
-
+
-
CMVX
(f = 20 Hz)
CMVY
(f = 20 Hz)
+
1.0 mA
MC1495 MC1495
Figure 12. Power Supply Sensitivity Figure 13. Offset Adjust Circuit
56 10 11
4
9
8
12
37 13
-15 V
(V-)
0.1 µF
9.1 k
11
k
13.7 k
15 k 15 k +32 V (V+)
1
2
14
VO2 VO1
2.0 k
4.3 k
22 k
2N2905A
or Equivalent
+32 V
6.2 V
S+ = |∆ (VO1 - VO2)|
∆V+
S- =|∆ (VO1 - VO2)|
∆V-
V+
R
2.0 k
Pot #1 Pot #2
V+15 V 32 V
R 2.0 k 5.1 k
Figure 14. Offset Adjust Circuit (Alternate)
5.1 V
5.1 V
V+
R
10 k
Pot #1
To Pin 8
Y Offset
Adjust
Pot #2 To Pin 12
X Offset
Adjust
-15 V
V+15 V 32 V
R 10 k 22 k
2.0 k
MC1495
11
k
0.1 µF
-15 V
2.0 k
10 k 10 k
To Pin 8
Y Offset
Adjust
To Pin 12
X Offset
Adjust
-15 V
10 k 10 k
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2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0-55 -25 0 25 50 75 100 125
Figure 15. Linearity versus Temperature Figure 16. Scale Factor versus Temperature
Figure 17. Error Contributed by Input
Differential Amplifier Figure 18. Error Contributed by
Input Differential Amplifier
TA , AMBIENT TEMPERATURE (°C)
E , E LINEARITY (%)
RX RY
K Adjusted to 0.100 at 25°C
0.110
0.105
0.100
0.095
-55 -25 0 25 50 75 100 12
5
K, SCALE FACTOR
1.0
0.8
0.6
0.4
0.2
010 12 14 16 18 20
RX or RY (kΩ)
ERROR, PERCENT OF FULL SCALE (%)
1.0
0.8
0.6
0.4
0.2
04.0 6.0 8.0 10 12 14
RX or RY (k Ω)
ERROR, PERCENT OF FULL SCALE (%)
14
12
10
8.0
6.0
4.0
2.0
0
0 2.0 4.0 6.0 8.0 10 12 14 16 18
|V1| or |V7| (V)
|V | or | V |, MAXIMUM (V )
XY pk
ERY
ERX
Minimum
Recommended
TA , AMBIENT TEMPERATURE (°C)
Figure 19. Maximum Allowable Input Voltage versus Voltage at Pin 1 or Pin 7
VX = VY = ± 5.0 V Max
I3 = I13 = 1.0 mAdc
VX = VY = ± 10 V Max
I3 = I13 = 1.0 mAdc
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OPERATION AND APPLICATIONS INFORMATION
Theory of Operation
The MC1495 is a monolithic, four-quadrant multiplier
which operates on the principle of variable
transconductance. A detailed theory of operation is covered
in Application Note AN489, Analysis and Basic Operation
of the MC1595. The result of this analysis is that the
differential output current of the multiplier is given by:
2VXVY
RXRYI3
IA – IB = ∆I =
where, IA and IB are the currents into Pins 14 and 2,
respectively, and VX and VY are the X and Y input voltages
at the multiplier input terminals.
DESIGN CONSIDERATIONS
General
The MC1495 permits the designer to tailor the multiplier
to a specific application by proper selection of external
components. External components may be selected to
optimize a given parameter (e.g. bandwidth) which may in
turn restrict another parameter (e.g. maximum output
voltage swing). Each important parameter is discussed in
detail in the following paragraphs.
Linearity, Output Error, ERX or ERY
Linearity error is defined as the maximum deviation of
output voltage from a straight line transfer function. It is
expressed a s error in percent of full scale (see figure below).
VO
+10 V
VE(max)
+10V
Vx or Vy
For example, if the maximum deviation, VE(max), is
±100 mV and the full scale output is 10 V, then the
percentage error is:
VE(max)
VO(max)
ER = x 100 = 100 x 10–3
10 x 100 = ±1.0%.
Linearity error may be measured by either of the
following methods:
1. Using an X-Y plotter with the circuit shown in
Figure 5, obtain plots for X and Y similar to the one
shown above.
2. Use the circuit of Figure 4. This method nulls the level
shifted output of the multiplier with the original
input. The peak output of the null operational amplifier
will be equal to the error voltage, VE (max).
One source of linearity error can arise from large signal
nonlinearity in the X and Y input differential amplifiers. To
avoid introducing error from this source, the emitter
degeneration resistors RX and RY must be chosen large
enough so that nonlinear base-emitter voltage variation can
be ignored. Figures 17 and 18 show the error expected from
this source as a function of the values of RX and RY with an
operating current of 1.0 mA in each side of the differential
amplifiers (i.e., I3 = I13 = 1.0 mA).
3 dB Bandwidth and Phase Shift
Bandwidth is primarily determined by the load resistors
and the stray multiplier output capacitance and/or the
operational amplifier used to level shift the output. If
wideband operation is desired, low value load resistors
and/or a wideband operational amplifier should be used.
Stray output capacitance will depend to a large extent on
circuit layout.
Phase shift in the multiplier circuit results from two
sources: phase shift common to both X and Y channels (due
to the load resistor-output capacitance pole mentioned
above) and relative phase shift between X and Y channels
(due to differences in transadmittance in the X and Y
channels). If the input to output phase shift is only 0.6°, the
output product of two sine waves will exhibit a vector error
of 1%. A 3° relative phase shift between VX and VY results
in a vector error of 5%.
Maximum Input Voltage
VX(max), VY(max) input voltages must be such that:
VX(max) <I13 RY
VY(max) <I3 RY
Exceeding this value will drive one side of the input
amplifier to “cutoff” and cause nonlinear operation.
Current I3 and I13 are chosen at a convenient value
(observing power dissipation limitation) between 0.5 mA
and 2.0 mA, approximately 1.0 mA. Then RX and R Y can be
determined by considering the input signal handling
requirements.
2VX VY
RX RY I3
1.0 mA
10 V
RX = RY > = 10 kΩ.
The equation IA – IB =
For VX(max) = VY(max) = 10 V;
is derived from IA – IB = 2VX VY
(RX + 2kT
qI13 )(RY + 2kT
qI3)I3
with the assumption RX >> 2kT
qI13 and RY >> 2kT
qI3.
At TA = +25°C and I13 = I3 = 1.0 mA,
2kT
qI13 2kT
qI3
= = 52 Ω.
Therefore, with RX = RY = 10 kΩ the above assumption
is valid. Reference to Figure 19 will indicate limitations of
VX(max) or VY(max) due to V1 and V7. Exceeding these limits
will cause saturation or “cutof f” of the input transistors. See
Step 4 of General Design Procedure for further details.
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Maximum Output Voltage Swing
The maximum output voltage swing is dependent upon
the factors mentioned below and upon the particular circuit
being considered.
For Figure 20 the maximum output swing is dependent
upon V + for positive swing and upon the voltage at Pin 1 for
negative swing. The potential at Pin 1 determines the
quiescent level for transistors Q5, Q6, Q7 and Q8. This
potential should be related so that negative swing at Pins 2
or 14 does not saturate those transistors. See General Design
Procedure for further information regarding selection of
these potentials.
RX RY I3
5610
RXRY
11
RIRL
RL
2
1
14 VO
9
12
4
8
3
I3
13 7
R13
R3
V-
V+
VX
VY
VO = K VX VY
K = 2RL
MC1495
+
+
+
-
-
-
Figure 20. Basic Multiplier
If an operational amplifier is used for level shift, as shown
in Figure 21, the output swing (of the multiplier) is greatly
reduced. See Section 3 for further details.
GENERAL DESIGN PROCEDURE
Selection of component values is best demonstrated by the
following example. Assume resistive dividers are used at the
X and Y-inputs to limit the maximum multiplier input to ±
5.0 V [VX = VY(max)] for a ±10 V input [VX′ = VY′(max)]
(see Figure 21). If an overall scale factor of 1/10 is desired,
VO =VX′ VY′
10 =(2VX) (2VY)
10 = 4/10 VX VY
then,
Therefore, K = 4/10 for the multiplier (excluding the divider
network).
Step 1. The fist step is to select current I3 and current I13.
There are no restrictions on the selection of either of these
currents except the power dissipation of the device. I3 and
I13 will normally be 1.0 mA or 2.0 mA. Further, I3 does not
have t o b e equal to I13, and there is normally no need to make
them different. For this example, let
I3 = I13 = 1.0 mA.
5
RX
10 k
RY
10 k
11
10
RL
18 k
5.0 k
P4
Output
Offset
Adjust
10 k
R13
12 k
I3
4
9
13 8 12
14
2
+
-
+
+
10 k
VY′VY
VX
MC1495 MC1741C
P1
P2
10 k
2.0 k -15 V
+15 V
5.1 V
2
3
7
4
6
5
1
+
-
20 k
RL
0.1 µF+15 V
R0
3.0 k
R0
3.0 k
R1
3.0 k
17
- 15 V - 15 V
3
I13
10 k
10 k
10 k
6
0.1 µF
2.0 k
Y Offset
Adjust
Scale
Factor
Adjust
R3
-10V ≤ VX ≤ +10V
-10V ≤ VY ≤ +10V
12 k
5.0 k
P3X Offset
Adjust
VO = -VX VY
10
VX′
Figure 21. Multiplier with Operational Amplifier Level Shift
5.1 V
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To set currents I3 and I13 to the desired value, it is only
necessary to connect a resistor between Pin 13 and ground,
and between Pin 3 and ground. From the schematic shown
in Figure 3, it can be seen that the resistor values necessary
are given by:
R3 + 500 Ω = I3
|V–| –0.7 V
R13 + 500 Ω = I13
|V–| –0.7 V
Let V– = –15 V, then R13 + 500 = 14.3 V
1.0 mA or R13 = 13.8 k
Ω
Let R13 = 12 kΩ. Similarly, R3 = 13.8 kΩ, let R3 = 15 kΩ
However, for applications which require an accurate scale
factor, the adjustment of R3 and consequently, I3, offers a
convenient method of making a final trim of the scale factor .
For this reason, as shown in Figure 21, resistor R3 is shown
as a fixed resistor in series with a potentiometer.
For applications not requiring an exact scale factor
(balanced modulator, frequency doubler, AGC amplifier,
etc.) Pins 3 and 13 can be connected together and a single
resistor from Pin 3 to ground can be used. In this case, the
single resistor would have a value of 1/2 the above
calculated value for R13.
Step 2 . The next step is to select RX and RY. To insure that
the input transistors will always be active, the following
conditions should be met:
VX
RX< I13,VY
RY< I3
A good rule of thumb is to make I3RY ≥ 1.5 VY(max) and
I13 RX ≥ 1.5 VX(max). The larger the I3RY and I13RX product
in relation to VY and VX respectively, the more accurate the
multiplier will be (see Figures 17 and 18).
Let RX = RY= 10 kΩ,
then I3RY = 10 V
I13RX= 10 V
since VX(max) = VY(max) = 5.0 V, the value of
RX= RY = 10 kΩ is sufficient.
Step 3. Now that RX, RY and I3 have been chosen, RL can
be determined:
K = 2RL
RX RY I3=4
10 =4
10
, or (10 k) (10 k) (1.0 mA)
(2) (RL)
Thus RL = 20 kΩ.
Step 4. To determine what power supply voltage is
necessary for this application, attention must be given to the
circuit schematic shown in Figure 3. From the circuit
schematic it can be seen that in order to maintain transistors
Q1, Q2, Q3 and Q4 in an active region when the maximum
input voltages are applied (VX′ = VY′ = 10 V or VX = 5.0 V,
VY = 5.0 V), their respective collector voltage should be at
least a few tenths of a volt higher than the maximum input
voltage. It should also be noticed that the collector voltage
of transistors Q3 and Q4 is at a potential which is two
diode-drops below the voltage at Pin 1. Thus, the voltage at
Pin 1 should be about 2.0 V higher than the maximum input
voltage. Therefore, to handle +5.0 V at the inputs, the
voltage at Pin 1 must be at least +7.0 V. Let V1 = 9.0 Vdc.
Since the current flowing into Pin 1 is always equal to 2I3,
the voltage at Pin 1 can be set by placing a resistor (R1) from
Pin 1 to the positive supply:
R1 = V+ –V1
2I3
15 V –9.0 V
Let V+ = 15 V, then R1 =(2) (1.0 mA)
R1 = 3.0 kΩ.
Note that the voltage at the base of transistors Q5, Q6, Q7 and
Q8 is one diode-drop below the voltage at Pin 1. Thus, in
order that these transistors stay active, the voltage at Pins 2
and 14 should be approximately halfway between the
voltage at Pin 1 and the positive supply voltage. For this
example, the voltage at Pins 2 and 14 should be
approximately 11 V.
Step 5. For dc applications, such as the multiply, divide
and square-root functions, it is usually desirable to convert
the differential output to a single-ended output voltage
referenced to ground. The circuit shown in Figure 22
performs this function. It can be shown that the output
voltage of this circuit is given by:
VO = (I2 –I14) RL
And since IA –IB = I2 –I14 = 2IX IY
I3=2VXVY
I3RXRY
then VO = 2RL VX′ VY′
4RX RX I3where, VX′ VY′ is the voltage at
the input to the voltage dividers.
Figure 22. Level Shift Circuit
I2
I14
V2
V14
RORO
+
-
RL
RL
V+
VO
The choice of an operational amplifier for this application
should have low bias currents, low offset current, and a high
common mode input voltage range as well as a high common
mode rejection ratio. The MC1456, and MC1741C
operational amplifiers meet these requirements.
MC1495
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10
Referring to Figure 21, the level shift components will be
determined. When V X = VY = 0, the currents I2 and I14 will
be equal to I13. In Step 3, RL was found to be 20 kΩ and in
Step 4, V2 and V14 were found to be approximately 11 V.
From this information RO can be found easily from the
following equation (neglecting the operational amplifiers
bias current):V2
RL+ I13 = V+ –V2
RO
And for this example, 11 V
20 kΩ+ 1.0 mA = 15 V –11 V
RO
Solving for RO: RO = 2.6 kΩ, thus, select RO = 3.0 kΩ
For RO = 3.0 kΩ, the voltage at Pins 2 and 14 is calculated
to be: V2 = V14 = 10.4 V.
The linearity of this circuit (Figure 21) is likely to be as
good or better than the circuit of Figure 5. Further
improvements are possible as shown in Figure 23 where RY
has been increased substantially to improve the Y linearity,
and R X decreased somewhat so as not to materially affect the
X linearity. This avoids increasing RL significantly in order
to maintain a K of 0.1.
The versatility of the MC1495 allows the user to to
optimize its performance for various input and output signal
levels.
OFFSET AND SCALE FACTOR ADJUSTMENT
Offset Voltages
Within the monolithic multiplier (Figure 3) transistor
base- emitter junctions are typically matched within 1.0 mV
and resistors are typically matched within 2%. Even with
this careful matching, an output error can occur. This output
error is comprised of X-input offset voltage, Y-input offset
voltage, and output offset voltage. These errors can be
adjusted to zero with the techniques shown in Figure 21.
Offset terms can be shown analytically by the transfer
function:
VO = K[Vx ± Viox ± Vx(off)] [Vy ±Vioy ± Vy(off)] ± VOO (1)
Where: K = scale factor
Vx= ‘‘x’’ input voltage
Vy= ‘‘y’’ input voltage
Viox = ‘‘x’’ input offset voltage
Vioy = ‘‘y’’ input offset voltage
Vx(off) = ‘‘x’’ input offset adjust voltage
Vy(off) = ‘‘y’’ input offset adjust voltage
VOO = output offset voltage.
Figure 23. Multiplier with Improved Linearity
5
7.5 k 27 k
11
10
33 k
10 k Output
Offset
Adjust
20 k
12 k
4
9
13 8 12
2
14
-
++
+
10 k
VY′
VX′
MC1495 MC1741C
20 k
15 k -15 V
+15 V
2.0 k
2
3
7
4
6
5
1
+
-
40 k
+15 V
3.0 k3.0 k
3.0 k
17
- 15 V - 15 V
3
10 k
10 k
10 k
6
15 k
Y Offset
Adjust
Scale
Factor
Adjust
±10 V VO = -VX VY
10
X Offset
Adjust
2.0 k
13 k
5.0 k
MC1495
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11
X, Y and Output Offset Voltages
VOOutput
Offset
Vx
X Offset Y Offset
Vy
Output
Offset
VO
For most dc applications, all three offset adjust
potentiometers (P1, P2, P4) will be necessary. One or more
offset adjust potentiometers can be eliminated for ac
applications (see Figures 28, 29, 30, 31).
If well regulated supply voltages are available, the offset
adjust circuit of Figure 13 is recommended. Otherwise, the
circuit of Figure 14 will greatly reduce the sensitivity to
power supply changes.
Scale Factor
The scale factor K is set by P3 (Figure 21). P3 varies I3
which inversely controls the scale factor K. It should be
noted that current I3 is one-half the current through R1. R1
sets the bias level for Q5, Q6, Q7, and Q8 (see Figure 3).
Therefore, to be sure that these devices remain active under
all conditions of input and output swing, care should be
exercised in adjusting P3 over wide voltage ranges (see
General Design Procedure).
Adjustment Procedures
The following adjustment procedure should be used to
null the offsets and set the scale factor for the multiply mode
of operation, (see Figure 21).
1. X-Input Offset
(a) Connect oscillator (1.0 kHz, 5.0 Vpp sinewave)
to the Y-input (Pin 4).
(b) Connect X-input (Pin 9) to ground.
(c) Adjust X offset potentiometer (P2) for an ac
null at the output.
2. Y-Input Offset
(a) Connect oscillator (1.0 kHz, 5.0 Vpp sinewave)
to the X-input (Pin 9).
(b) Connect Y-input (Pin 4) to ground.
(c) Adjust Y offset potentiometer (P1) for an ac null
at the output.
3. Output Offset
(a) Connect both X and Y-inputs to ground.
(b) Adjust output offset potentiometer (P4) until
the output voltage (VO) is 0 Vdc.
4. Scale Factor
(a) Apply +10 Vdc to both the X and Y-inputs.
(b) Adjust P3 to achieve + 10 V at the output.
5. Repeat steps 1 through 4 as necessary.
The ability to accurately adjust the MC1495 depends upon
the characteristics of potentiometers P1 through P4.
Multi-turn, infinite resolution potentiometers with low
temperature coefficients are recommended.
DC APPLICATIONS
Multiply
The circuit shown in Figure 21 may be used to multiply
signals from dc to 100 kHz. Input levels to the actual
multiplier are 5.0 V (max). With resistive voltage dividers
the maximum could be very large however, for this
application two-to-one dividers have been used so that the
maximum input level is 10 V. The maximum output level
has also been designed for 10 V (max).
Squaring Circuit
If the two inputs are tied together, the resultant function is
squaring; that is VO = KV2 where K is the scale factor. Note
that all error terms can be eliminated with only three
adjustment potentiometers, thus eliminating one of the input
offset adjustments. Procedures for nulling with adjustments
are given as follows:
A. AC Procedure:
1. Connect oscillator (1.0 kHz, 15 Vpp) to input.
2. Monitor output at 2.0 kHz with tuned voltmeter
and adjust P3 for desired gain. (Be sure to peak
response of the voltmeter.)
3. Tune voltmeter to 1.0 kHz and adjust P1 for a
minimum output voltage.
4. Ground input and adjust P4 (output offset) for
0 Vdc output.
5. Repeat steps 1 through 4 as necessary.
B. DC Procedure:
1. Set VX = VY = 0 V and adjust P4 (output offset
potentiometer) such that VO = 0 Vdc
2. Set VX = VY = 1.0 V and adjust P1 (Y-input offset
potentiometer) such that the output voltage is
+ 0.100 V.
3. Set VX = VY = 10 Vdc and adjust P3 such that
the output voltage is + 10 V.
4. Set VX = VY = –10 Vdc. Repeat steps 1 through
3 as necessary.
Figure 24. Basic Divide Circuit
X
KVX VY
VX
R1
VY
-
+
R2
I2
I1
VZ
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Divide Circuit
Consider the circuit shown in Figure 24 in which the
multiplier is placed in the feedback path of an operational
amplifier. For this configuration, the operational amplifier
will maintain a “virtual ground” at the inverting (–) input.
Assuming that the bias current of the operational amplifier
is negligible, then I1 = I2 and,
(1)
=
KVXVY
R1 –VZ
R2
(2)
Solving for VY,V
Y = –R1
R2 K VZ
VX
–VZ
KVX(3)
If R1=R2, VY =
–VZ
VX(4)
If R1= KR2, VY =
Hence, the output voltage is the ratio of VZ to VX and
provides a divide function. This analysis is, of course, the
ideal condition. If the multiplier error is taken into account,
the output voltage is found to be:
VY = – R1
R2 K VZ
VX+∆E
KVX(5)
where ∆E is the error voltage at the output of the multiplier.
From this equation, it is seen that divide accuracy is strongly
dependent upon the accuracy at which the multiplier can be
set, particularly at small values of VY. For example, assume
that R1 = R2, and K = 1/10. For these conditions the output
of the divide circuit is given by:
VY =–10 VZ
VX+∆E
VX(6)
10
From Equation 6, it is seen that only when VX = 10 V is
the error voltage of the divide circuit as low as the error of
the multiply circuit. For example, when V X is small, (0.1 V)
the error voltage of the divide circuit can be expected to be
a hundred times the error of the basic multiplier circuit.
In terms of percentage error,
percentage error = error
actual x 100%
or from Equation (5),
PED = KVX
∆E
R1
R2 K VZ
VX
=R2
R1 ∆E
VZ(7)
From Equation 7, the percentage error is inversely related
to voltage VZ (i.e., for increasing values of VZ, the
percentage error decreases).
A circuit that performs the divide function is shown in
Figure 25.
Two things should be emphasized concerning Figure 25.
1. The input voltage (V X′) must be greater than zero and
must be positive. This insures that the current out of
Pin 2 of the multiplier will always be in a direction
compatible with the polarity of VZ.
2. Pin 2 and 14 of the multiplier have been interchanged
in respect to the operational amplifiers input
terminals. In this instance, Figure 25 dif fers from the
circuit connection shown in Figure 21; necessitated to
insure negative feedback around the loop.
A suggested adjustment procedure for the divide circuit.
1. Set VZ = 0 V and adjust the output offset
potentiometer (P4) until the output voltage (VO)
remains at some (not necessarily zero) constant value
as VX′ is varied between +1.0 V and +10 V.
2. Keep V Z at 0 V, set VX′ at +10 V and adjust the Y input
offset potentiometer (P1) until VO = 0 V.
3. Let VX′ = VZ and adjust the X-input offset
potentiometer (P 2) until the output voltage remains at
some (not necessarily – 10 V) constant value as VZ =
VX′ is varied between +1.0 and +10 V.
4. Keep VX′ = VZ and adjust the scale factor
potentiometer (P3) until the average value of VO is
–10 V as VZ = VX′ is varied between +1.0 V and
+10 V.
5. Repeat steps 1 through 4 as necessary to achieve
optimum performance.
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P3
Figure 25. Divide Circuit
5
RX
10 k
RY
10 k
11
10
18 k
5.0 k P4
Output
Offset
Adjust
12 k
4
9
13 8 12
2
14
-
++
+
10 k
VX′
MC1495 MC1741C
2
3
7
4
6
5
1
+
-
20 k
0.1 µF+15 V
3.0 k3.0 k3.9 k
17
- 15 V - 15 V
3
10 k
10 k
10 k
6
0.1 µF
Scale
Factor
Adjust
0 ≤ VX′ ≤ +10 V
-10 V ≤ VZ ≤ +10 V
To Offset
Adjust
(See Figure 13)
13 k
VO
-10 VZ
VX
VO =
5.0 k
VZ
Figure 26. Basic Square Root Circuit
-
+
VO
KVO2+
+
+-
KVO2 = -VZ
or
VO =|VZ|
K
VZ
MC1495
Square Root
A special case of the divide circuit in which the two inputs
to the multiplier are connected together is the square root
function as indicated in Figure 26. This circuit may suffer
from latch-up problems similar to those of the divide circuit.
Note that only one polarity of input is allowed and diode
clamping (see Figure 27) protects against accidental
latch-up.
This circuit also may be adjusted in the closed-loop mode
as follows:
1. Set VZ to –0.01 V and adjust P4 (output offset) for
VO = +0.316 V, being careful to approach the output
from the positive side to preclude the effect of the
output diode clamping.
2. Set VZ to –0.9 V and adjust P2 (X adjust) for
VO = +3.0 V.
3. Set VZ to –10 V and adjust P3 (scale factor adjust)
for VO = +10 V.
4. Steps 1 through 3 may be repeated as necessary to
achieve desired accuracy.
AC APPLICATIONS
The applications that follow demonstrate the versatility of
the monolithic multiplier. If a potted multiplier is used for
these cases, the results generally would not be as good
because the potted units have circuits that, although they
optimize dc multiplication operation, can hinder ac
applications.
Frequency doubling often is done with a diode where
the fundamental plus a series of harmonics are
generated. However, extensive filtering is required to obtain
the desired harmonic, and the second harmonic obtained
under this technique usually is small in magnitude and
requires amplification.
When a multiplier is used to double frequency the second
harmonic is obtained directly, except for a dc term, which
can be removed with ac coupling.
eo = KE2 cos2 ωt
eo = KE2
2(1 + cos 2ωt).
A potted multiplier can be used to obtain the double
frequency component, but frequency would be limited by its
internal level-shift amplifier. In the monolithic units, the
amplifier is omitted.
In a typical doubler circuit, conventional ± 15 V supplies
are used. An input dynamic range of 5.0 V peak-to-peak is
allowed. The circuit generates wave-forms that are double
frequency; less than 1% distortion is encountered without
filtering. The configuration has been successfully used in
excess of 200 kHz; reducing the scale factor by decreasing
the load resistors can further expand the bandwidth.
Figure 29 represents an application for the monolithic
multiplier as a balanced modulator. Here, the audio input
signal is 1.6 kHz and the carrier is 40 kHz.
MC1495
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14
P3
Figure 27. Square Root Circuit
5
RX
10 k
RY
10 k
11
10
13 k
5.0 k P4
Output
Offset
Adjust
12 k
4
9
13 8 12
14
2
-
++
+
10 k
MC1495 MC1741C
2
3
7
4
6
5
1
+
-
20 k
RL
0.1 µF+15 V
3.0 k3.0 k3.9 k
17
- 15 V - 15V
3
10 k
6
0.1 µF
Scale
Factor
Adjust
-10 ≤ VZ ≤ +0 V
To Offset
Adjust
(See Figure 13)
13 k
VO
10 |VZ|
√
VO =
(11 V)
5.0 k
VZ
eo≈E2
20 cos 2 ωt
When two equal cosine waves are applied to X and Y, the result
is a wave shape of twice the input frequency. For this example
the input was a 10 kHz signal, output was 20 kHz.
Figure 28. Frequency Doubler
5610
RY
8.2 k
RX
8.2 k
4
9
8
12
3713
1
2
14
E cos ωt
(< 5.0 Vpp)
6.8 k
R1
3.0 k
R1
3.3 k
*Select
Offset
Adjust
MC1495
C1*
1.0 µF
1.0 µF
VCC +15 V
R1
3.3 k
-15 V
+
-
Y
11
5610
RY
8.2 k
RX
8.2 k
4
9
8
12
Figure 29. Balanced Modulator
3713
1
2
14
eY = E cos ωmt
6.8 k
3.0 k
RL
3.3 k
*Select
(A)
+
-
Y
X
Offset
Adjust
C1*
eX = E cos ωct
1.0 µF
1.0 µF
+15 V
(B)
eo
RL
3.3 k
-15 V
+
-
11
MC1495
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The defining equation for balanced modulation is
K(Emcos ωmt) (Ec cos ωct) =
KEc Em
2[ cos (ωc + ωm)t + cos (ωc – ωm) t ]
where ωc is the carrier frequency, ωm is the modulator
frequency and K is the multiplier gain constant.
AC coupling at the output eliminates the need for level
translation or an operational amplifier; a higher operating
frequency results.
A problem common to communications is to extract the
intelligence from single-sideband received signal. The ssb
signal is of the form:
essb = A cos (ωc + ωm) t
and if multiplied by the appropriate carrier waveform, cos
ωct,
essbecarrier = AK
2[cos (2ωc + ωm)t + cos (ωc) t ].
If the frequency of the band-limited carrier signal (ωc) is
ascertained in advance, the designer can insert a low pass
filter and obtain the (AK/2) (cosωct) term with ease. He/she
also can use an operational amplifier for a combination level
shift-active filter, as an external component. But in potted
multipliers, even if the frequency range can be covered, the
operational amplifier is inside and not accessible, so the user
must accept the level shifting provided, and still add a low
pass filter.
Amplitude Modulation
The multiplier performs amplitude modulation, similar to
balanced modulation, when a dc term is added to the
modulating signal with the Y-offset adjust potentiometer
(see Figure 30).
Here, the identity is:
Em(1 + m cos ωmt) Ec cos ωct = KEmEccos ωct +
KEmEcm
2[ cos(ωc + ωm)t + cos (ωc – ωm) t ]
where m indicates the degrees of modulation. Since m is
adjustable, via potentiometer P1, 100% modulation is
possible. Without extensive tweaking, 96% modulation may
be obtained where ωc and ωm are the same as in the balanced
modulator example.
Linear Gain Control
To obtain linear gain control, the designer can feed to one
of the two MC1495 inputs a signal that will vary the unit’s
gain. The following example demonstrates the feasibility of
this application. Suppose a 200 kHz sinewave, 1.0 V
peak-to-peak, is the signal to which a gain control will be
added. The dynamic range of the control voltage VC is 0 V
to +1.0 V. These must be ascertained and the proper values
of R X and R Y can be selected for optimum performance. For
the 200 kHz operating frequency, load resistors of 100 Ω
were chosen to broaden the operating bandwidth of the
multiplier, but gain was sacrificed. It may be made up with
an amplifier operating at the appropriate frequency (see
Figure 31).
Figure 30. Amplitude Modulation
5610
RY
8.2 k
RX
8.2 k
4
9
8
12
3713
1
2
14
6.8 k
R1
3.0 k
RL1
3.3 k
*Select
Y
X
Offset Adjust
MC1495
C1*
1.0 µF
VCC = +15 V
eo
RL1
3.3 k
-15 V
% Modulation Adjust
eY = E cos ωmt
eX = E cos ωmt
eX, eY < 5.0 Vpp
11
The signal is applied to the unit’s Y-input. Since the total
input range is limited to 1.0 Vpp, a 2.0 V swing, a current
source of 2.0 mA and an RY value of 1.0 kΩ is chosen. This
takes best advantage of the dynamic range and insures linear
operation in the Y-channel.
Since the X-input varies between 0 and +1.0 V, the current
source selected was 1.0 mA, and the RX value chosen
was 2.0 kΩ. This also insures linear operation over the
X-input dynamic range. Choosing RL = 100 assures wide
bandwidth operation.
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16
K = RL
RX RY I3
=100
(2 k) (1 k) (2 x 103)V–1
=1
40 V–1
Hence, the scale factor for this configuration is: The 2 in the numerator of the equation is missing in this scale
factor expression because the output is single-ended and ac
coupled.
Figure 31. Linear Gain Control
P3
5
2.0 k 1.0 k
1110
100
11 k
13 7
-
+
MC1495
1.5 k
3
6
3.0 k
5.0 k
Amplifier
AV = 40
Vin
VC
Offset
Adjust
51
1.0 k
0.1 µF
4
9
8
12
Y
Y
X
X
2.0 mA
1.0 µF
-12 V
VO
+12 V
100
1
2
14
+
-
NOTE: Linear gain control of a 1.0 Vpp signal is performed with a 0 V
to 1.0 V control voltage. If VC is 0.5 V the output will be 0.5 Vpp.
1.25
1.0
0.75
0.5
0.25
0
0
0.2 0.4 0.6 0.8 1.0 1.2
Vin = 1.0 Vpp
200 kHz
VAGC (V)
VO(Vpp)
+
k = 1
40
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PACKAGE DIMENSIONS
D SUFFIX
PLASTIC PACKAGE
CASE 751A–03
ISSUE F
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
–A–
–B–
G
P7 PL
14 8
71 M
0.25 (0.010) B M
S
B
M
0.25 (0.010) A S
T
–T–
F
RX 45
SEATING
PLANE D14 PL K
C
J
M
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A8.55 8.75 0.337 0.344
B3.80 4.00 0.150 0.157
C1.35 1.75 0.054 0.068
D0.35 0.49 0.014 0.019
F0.40 1.25 0.016 0.049
G1.27 BSC 0.050 BSC
J0.19 0.25 0.008 0.009
K0.10 0.25 0.004 0.009
M0 7 0 7
P5.80 6.20 0.228 0.244
R0.25 0.50 0.010 0.019
 
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PACKAGE DIMENSIONS
P SUFFIX
PLASTIC PACKAGE
CASE 646–06
ISSUE M
17
14 8
B
ADIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.715 0.770 18.16 18.80
B0.240 0.260 6.10 6.60
C0.145 0.185 3.69 4.69
D0.015 0.021 0.38 0.53
F0.040 0.070 1.02 1.78
G0.100 BSC 2.54 BSC
H0.052 0.095 1.32 2.41
J0.008 0.015 0.20 0.38
K0.115 0.135 2.92 3.43
L
M--- 10 --- 10
N0.015 0.039 0.38 1.01

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
F
HG DK
C
SEATING
PLANE
N
–T–
14 PL
M
0.13 (0.005)
L
M
J0.290 0.310 7.37 7.87
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Notes
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20
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
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alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
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MC1495/D
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