UDA1334ATS/N2 - Philips Semiconductors / NXP Semiconductors

DATA SH EET

Product speciﬁcation

Supersedes data of 2000 Feb 09

File under Integrated Circuits, IC01

2000 Jul 31

INTEGRATED CIRCUITS

UDA1334ATS

Low power audio DAC with PLL

2000 Jul 31 2

Philips Semiconductors Product speciﬁcation

Low power audio DAC with PLL UDA1334ATS

CONTENTS

1 FEATURES

1.1 General

1.2 Multiple format data interface

1.3 DAC digital features

1.4 Advanced audio configuration

1.5 PLL system clock generation

2 APPLICATIONS

3 GENERAL DESCRIPTION

4 ORDERING INFORMATION

5 QUICK REFERENCE DATA

6 BLOCK DIAGRAM

7 PINNING

8 FUNCTIONAL DESCRIPTION

8.1 System clock

8.1.1 Audio mode

8.1.2 Video mode

8.2 Interpolation filter

8.3 Noise shaper

8.4 Filter stream DAC

8.5 Power-on reset

8.6 Feature settings

8.6.1 Digital interface format select

8.6.2 De-emphasis control

8.6.3 Mute control

9 LIMITING VALUES

10 HANDLING

11 THERMAL CHARACTERISTICS

12 QUALITY SPECIFICATION

13 DC CHARACTERISTICS

14 AC CHARACTERISTICS

14.1 Analog

14.2 Timing

15 APPLICATION INFORMATION

16 PACKAGE OUTLINE

17 SOLDERING

17.1 Introduction to soldering surface mount

packages

17.2 Reflow soldering

17.3 Wave soldering

17.4 Manual soldering

17.5 Suitability of surface mount IC packages for

wave and reflow soldering methods

18 DATA SHEET STATUS

19 DEFINITIONS

20 DISCLAIMERS

2000 Jul 31 3

Philips Semiconductors Product speciﬁcation

Low power audio DAC with PLL UDA1334ATS

1 FEATURES

1.1 General

•2.4 to 3.6 V power supply voltage

•On-board PLL to generate the internal system clock:

– OperatesasanasynchronousDAC,regeneratingthe

internal clock from the WS signal (called audio mode)

– Generatesaudio relatedsystem clock(output) based

on32, 48 or 96 kHzsamplingfrequency(calledvideo

mode).

•Integrated digital filter plus DAC

•Supports sample frequencies from 16 to 100 kHz in

asynchronous DAC mode

•No analog post filtering required for DAC

•Easy application

•SSOP16 package.

1.2 Multiple format data interface

•I2S-bus and LSB-justified format compatible

•1fs input data rate.

1.3 DAC digital features

•Digital de-emphasis for 44.1 kHz sampling frequency

•Mute function.

1.4 Advanced audio conﬁguration

•High linearity, wide dynamic range and low distortion.

1.5 PLL system clock generation

•Integrated low jitter PLL for use in applications in which

there is digital audio data present but the system cannot

provide an audio related system clock. This mode is

called audio mode.

•The PLL can generate 256 ×48 kHz and 384 ×48 kHz

from a 27 MHz input clock. This mode is called video

mode.

2 APPLICATIONS

This audio DAC is excellently suitable for digital audio

portable application, specially in applications in which an

audio related system clock is not present.

3 GENERAL DESCRIPTION

The UDA1334ATS is a single chip 2 channel

digital-to-analog converter employing bitstream

conversion techniques, including an on-board PLL.

The extremely low power consumption and low voltage

requirements make the device eminently suitable for use

in low-voltage low-power portable digital audio equipment

which incorporates a playback function.

The UDA1334ATS supports the I2S-bus data format with

word lengths of up to 24 bits and the LSB-justified serial

data format with word lengths of 16, 20 and 24 bits.

The UDA1334ATS has basic features such as

de-emphasis (44.1 kHz sampling frequency, only

supported in audio mode) and mute.

4 ORDERING INFORMATION

TYPE

NUMBER PACKAGE

NAME DESCRIPTION VERSION

UDA1334ATS SSOP16 plastic shrink small outline package; 16 leads; body width 4.4 mm SOT369-1

2000 Jul 31 4

Philips Semiconductors Product speciﬁcation

Low power audio DAC with PLL UDA1334ATS

5 QUICK REFERENCE DATA

Note

1. The output voltage of the DAC scales proportionally to the power supply voltage.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

VDDA DAC analog supply voltage 2.4 3.0 3.6 V

VDDD digital supply voltage 2.4 3.0 3.6 V

IDDA DAC analog supply current audio mode −3.5 −mA

video mode −3.5 −mA

IDDD digital supply current audio mode −2.5 −mA

video mode −4.5 −mA

Tamb ambient temperature −40 −+85 °C

Digital-to-analog converter (VDDA =V

DDD = 3.0 V)

Vo(rms) output voltage (RMS value) at 0 dB (FS) digital input;

note 1 −900 −mV

(THD+N)/S total harmonic distortion-plus-noise to

signal ratio fs= 44.1 kHz; at 0 dB −−90 −dB

fs= 44.1 kHz; at −60 dB;

A-weighted −−40 −dB

fs= 96 kHz; at 0 dB −−85 −dB

fs= 96 kHz; at −60 dB;

A-weighted −−38 −dB

S/N signal-to-noise ratio fs= 44.1 kHz; code = 0;

A-weighted −100 −dB

fs= 96 kHz; code = 0;

A-weighted −98 −dB

αCS channel separation −100 −dB

Power dissipation (at fs= 44.1 kHz)

P power dissipation audio mode −18 −mW

video mode −24 −mW

2000 Jul 31 5

Philips Semiconductors Product speciﬁcation

Low power audio DAC with PLL UDA1334ATS

6 BLOCK DIAGRAM

handbook, full pagewidth

MGL973

DAC

UDA1334ATS

NOISE SHAPER

INTERPOLATION FILTER

DE-EMPHASIS

DAC

DIGITAL INTERFACE PLL

13 12

VOUTR

BCK

VSSA

VOUTL

DATAI

VDDA

VDDD

PLL0

Vref(DAC)

VSSD

SFOR0

SYSCLK/PLL1 8

MUTE 9

DEEM/CLKOUT

SFOR1

Fig.1 Block diagram.

2000 Jul 31 6

Philips Semiconductors Product speciﬁcation

Low power audio DAC with PLL UDA1334ATS

7 PINNING

Note

1. Because of test issues these pads are not 5 V tolerant and both pads should be at power supply voltage level or at

a maximum of 0.5 V above that level.

SYMBOL PIN PAD TYPE DESCRIPTION

BCK 1 5 V tolerant digital input pad bit clock input

WS 2 5 V tolerant digital input pad word select input

DATAI 3 5 V tolerant digital input pad serial data input

VDDD 4 digital supply pad digital supply voltage

VSSD 5 digital ground pad digital ground

SYSCLK/PLL1 6 5 V tolerant digital input pad system clock input in video mode/PLL

mode control 1 input in audio mode

SFOR1 7 5 V tolerant digital input pad serial format select 1 input

MUTE 8 5 V tolerant digital input pad mute control input

DEEM/CLKOUT 9 5 V tolerant digital input/output pad de-emphasis control input in audio

mode/clock output in video mode

PLL0 10 3-level input pad; note 1 PLL mode control 0 input

SFOR0 11 digital input pad; note 1 serial format select 0 input

Vref(DAC) 12 analog pad DAC reference voltage

VDDA 13 analog supply pad DAC analog supply voltage

VOUTL 14 analog output pad DAC output left

VSSA 15 analog ground pad DAC analog ground

VOUTR 16 analog output pad DAC output right

handbook, halfpage

UDA1334ATS

MGL972

VOUTR

BCK

VSSA

VOUTL

DATAI

VDDA

VDDD

Vref(DAC)

VSSD

SFOR0SYSCLK/PLL1

PLL0SFOR1

DEEM/CLKOUTMUTE

Fig.2 Pin configuration.

2000 Jul 31 7

Philips Semiconductors Product speciﬁcation

Low power audio DAC with PLL UDA1334ATS

8 FUNCTIONAL DESCRIPTION

8.1 System clock

The UDA1334ATS incorporates a PLL capable of

generating the system clock. The UDA1334ATS can

operate in 2 modes:

•It operates as an asynchronous DAC, which means the

device regenerates the internal clocks using a PLL from

the incoming WS signal. This mode is called audio

mode.

•It generates the internal clocks from a 27 MHz clock

input, based on 32, 48 and 96 kHz sampling

frequencies. This mode is called video mode.

In video mode, the digital audio input is slave, which

means that the system must generate the BCK and

WS signalsfromthe output clockavailableat pin CLKOUT

of the UDA1334ATS. The digital audio signals should be

frequency locked to the CLKOUT signal.

Remarks:

1. The WS edge MUST fall on the negative edge of the

BCK at all times for proper operation of the digital I/O

data interface

2. For LSB-justified formats it is important to have a WS

signal with a duty factor of 50%.

8.1.1 AUDIO MODE

Audio mode is enabled by setting pin PLL0 to LOW.

De-emphasis can be activated via pin DEEM/CLKOUT

according to Table 5.

In audio mode, pin SYSCLK/PLL1 is used to set the

sampling frequency range as given in Table 1.

Table 1 Sampling frequency range in audio mode

8.1.2 VIDEO MODE

Invideomode, themasterclock is a27 MHzexternal clock

(as is available in video environment). A clock-out signal is

generated at pin DEEM/CLKOUT. The output frequency

can be selected using pin PLL0. The output frequency is

either 12.228 MHz (256 ×48 kHz) with pin PLL0 being at

MID level or 18.432 MHz (384 ×48 kHz) with pin PLL0

being HIGH, as given in Table 2.

Table 2 Clock output selection in video mode

Notes

1. The supported sampling frequencies are:

96, 48 and 24 kHz or 64, 32 and 16 kHz.

2. The supported sampling frequencies are:

96, 48 and 24 kHz; 72 and 36 kHz or 32 kHz.

8.2 Interpolation ﬁlter

The interpolation digital filter interpolates from 1fsto 64fs

by cascading FIR filters (see Table 3).

Table 3 Interpolation ﬁlter characteristics

8.3 Noise shaper

The 5th-order noise shaper operates at 64fs. It shifts

in-band quantization noise to frequencies well above the

audio band. This noise shaping technique enables high

signal-to-noise ratios to be achieved. The noise shaper

output is converted into an analog signal using a

Filter Stream DAC (FSDAC).

SYSCLK/PLL1 SELECTION

LOW fs=16to50kHz

HIGH fs= 50 to 100 kHz

PLL0 SELECTION

MID 12.228 MHz clock; note 1

HIGH 18.432 MHz clock; note 2

LOW audio mode

ITEM CONDITION VALUE (dB)

Pass-band ripple 0fsto 0.45fs±0.02

Stop band >0.55fs−50

Dynamic range 0fsto 0.45fs>114

2000 Jul 31 8

Philips Semiconductors Product speciﬁcation

Low power audio DAC with PLL UDA1334ATS

8.4 Filter stream DAC

The FSDAC is a semi-digital reconstruction filter that

converts the 1-bit data stream of the noise shaper to an

analog output voltage. The filter coefficients are

implemented as current sources and are summed at

virtual ground of the output operational amplifier. In this

way very high signal-to-noise performance and low clock

jitter sensitivity is achieved. No post filter is needed due to

the inherent filter function of the DAC. On-board amplifiers

convert the FSDAC output current to an output voltage

signal capable of driving a line output.

The output voltage of the FSDAC scales proportionally to

the power supply voltage.

8.5 Power-on reset

The UDA1334ATS has an internal Power-on reset circuit

(see Fig.3) which resets the test control block.

The reset time (see Fig.4) is determined by an external

capacitor which is connected between pin Vref(DAC) and

ground. The reset time should be at least 1 µs for

Vref(DAC) < 1.25 V. When VDDA is switched off, the device

will be reset again for Vref(DAC) < 0.75 V.

During the reset time the system clock should be running.

handbook, halfpage

VDDA

Vref(DAC)

3.0 V 13

MGT015

UDA1334ATS

C1 >

10 µF

RESET

CIRCUIT

50 kΩ

Fig.3 Power-on reset circuit.

handbook, halfpage

3.0

VDDD

(V)

1.5

3.0

VDDA

(V)

1.5

3.0

Vref(DAC)

(V)

1.5

1.25

0.75

MGL984

>1 µs

Fig.4 Power-on reset timing.

2000 Jul 31 9

Philips Semiconductors Product speciﬁcation

Low power audio DAC with PLL UDA1334ATS

8.6 Feature settings

8.6.1 DIGITAL INTERFACE FORMAT SELECT

The digital audio interface formats (see Fig.5) can be

selected via pins SFOR1 and SFOR0 as shown in

Table 4.

For the digital audio interface holds that the

BCK frequency can be maximum 64 times WS frequency.

The WS signal must change at the negative edge of the

BCK signal for all digital audio formats.

Table 4 Data format selection

8.6.2 DE-EMPHASIS CONTROL

This function is only available in audio mode. In that case,

pin DEEM/CLKOUT can be used to activate the digital

de-emphasis for 44.1 kHz as given in Table 5.

Table 5 De-emphasis control (audio mode)

8.6.3 MUTE CONTROL

The output signal can be soft muted by setting pin MUTE

to HIGH as given in Table 6.

Table 6 Mute control

SFOR1 SFOR0 INPUT FORMAT

LOW LOW I2S-bus input

LOW HIGH LSB-justiﬁed 16 bits input

HIGH LOW LSB-justiﬁed 20 bits input

HIGH HIGH LSB-justiﬁed 24 bits input

DEEM/CLKOUT FUNCTION

LOW de-emphasis off

HIGH de-emphasis on

MUTE FUNCTION

LOW mute off

HIGH mute on

2000 Jul 31 10

Philips Semiconductors Product speciﬁcation

Low power audio DAC with PLL UDA1334ATS

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ndbook, full pagewidth

MGS752

B5 B6 B7 B8 B9 B10

LEFT

LSB-JUSTIFIED FORMAT 24 BITS

BCK

DATA

RIGHT

1518 1720 1922 212324 2 1

B3 B4

MSB B2 B23 LSB

B5 B6 B7 B8 B9 B10

1518 1720 1922 212324 21

B3 B4

MSB B2 B23 LSB

MSB B2 B3 B4 B5 B6

LEFT

LSB-JUSTIFIED FORMAT 20 BITS

BCK

DATA

RIGHT

1518 1720 19 2 1

B19 LSB

MSB B2 B3 B4 B5 B6

1518 1720 19 2 1

B19 LSB

MSB B2

LEFT

LSB-JUSTIFIED FORMAT 16 BITS

BCK

DATA

RIGHT

15 2 1

B15 LSB

MSB B2

15 2 1

B15 LSB

MSB MSBB2

21> = 812 3

LEFT

I2S-BUS FORMAT

BCK

DATA

RIGHT

3> = 8

MSB B2

Fig.5 Digital audio formats.

2000 Jul 31 11

Philips Semiconductors Product speciﬁcation

Low power audio DAC with PLL UDA1334ATS

9 LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134).

Notes

1. All supply connections must be made to the same power supply.

2. ESD behaviour is tested according to JEDEC II standard.

3. Short-circuit test at Tamb =0°C and VDDA = 3 V. DAC operation after short-circuiting cannot be warranted.

10 HANDLING

Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is

desirable to take normal precautions appropriate to handling MOS devices.

11 THERMAL CHARACTERISTICS

12 QUALITY SPECIFICATION

In accordance with

“SNW-FQ-611-E”

13 DC CHARACTERISTICS

VDDD =V

DDA = 3.0 V; Tamb =25°C; RL=5kΩ; all voltages with respect to ground (pins VSSA and VSSD); unless

otherwise speciﬁed.

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

VDD supply voltage note 1 −4.0 V

Txtal(max) maximum crystal

temperature −150 °C

Tstg storage temperature −65 +125 °C

Tamb ambient temperature −40 +85 °C

Ves electrostatic handling voltage human body model; note 2 −2000 +2000 V

machine model; note 2 −250 +250 V

Isc(DAC) short-circuit current of DAC note 3

output short-circuited to VSSA −450 mA

output short-circuited to VDDA −300 mA

SYMBOL PARAMETER CONDITIONS VALUE UNIT

Rth(j-a) thermal resistance from junction to ambient in free air 145 K/W

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

VDDA DAC analog supply voltage note 1 2.4 3.0 3.6 V

VDDD digital supply voltage note 1 2.4 3.0 3.6 V

IDDA DAC analog supply current audio mode −3.5 −mA

video mode −3.5 −mA

IDDD digital supply current audio mode −2.5 −mA

video mode −4.5 −mA

2000 Jul 31 12

Philips Semiconductors Product speciﬁcation

Low power audio DAC with PLL UDA1334ATS

Notes

1. All supply connections must be made to the same external power supply unit.

2. When the DAC drives a capacitive load above 50 pF, a series resistance of 100 Ω must be used to prevent

oscillations in the output operational amplifier.

14 AC CHARACTERISTICS

14.1 Analog

VDDD =V

DDA = 3.0 V; fi= 1 kHz; Tamb =25°C; RL=5kΩ; all voltages with respect to ground (pins VSSA and VSSD);

unless otherwise speciﬁed.

Digital input pins: TTL compatible

VIH HIGH-level input voltage 2.0 −5.0 V

VIL LOW-level input voltage −0.5 −+0.8 V

ILIinput leakage current −−1µA

iinput capacitance −−10 pF

3-level input: pin PLL0

VIH HIGH-level input voltage 0.9VDDD −VDDD + 0.5 V

VIM MID-level input voltage 0.4VDDD −0.6VDDD V

VIL LOW-level input voltage −0.5 −+0.5 V

Digital output pins

VOH HIGH-level output voltage IOH =−2 mA 0.85VDDD −− V

OL LOW-level output voltage IOL =2mA −−0.4 V

DAC

Vref(DAC) reference voltage with respect to VSSA 0.45VDD 0.5VDD 0.55VDD V

Ro(ref) output resistance on

pin Vref(DAC)

−25 −kΩ

Io(max) maximum output current (THD + N)/S < 0.1%;

RL=5kΩ−1.6 −mA

RLload resistance 3 −− kΩ

Lload capacitance note 2 −−50 pF

SYMBOL PARAMETER CONDITIONS TYP. UNIT

DAC

Vo(rms) output voltage (RMS value) at 0 dB (FS) digital input; note 1 900 mV

∆Vounbalance between channels 0.1 dB

(THD + N)/S total harmonic

distortion-plus-noisetosignal

ratio

fs= 44.1 kHz; at 0 dB −90 dB

fs= 44.1 kHz; at −60 dB; A-weighted −40 dB

fs= 96 kHz; at 0 dB −85 dB

fs= 96 kHz; at −60 dB; A-weighted −38 dB

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

2000 Jul 31 13

Philips Semiconductors Product speciﬁcation

Low power audio DAC with PLL UDA1334ATS

Note

1. The output voltage of the DAC scales proportionally to the analog power supply voltage.

14.2 Timing

VDDD =V

DDA = 2.4 to 3.6 V; Tamb =−20 to +85 °C; RL=5kΩ; all voltages with respect to ground (pins VSSA and VSSD);

unless otherwise speciﬁed; note 1.

Note

1. The typical value of the timing is specified for a sampling frequency of 44.1 kHz.

S/N signal-to-noise ratio fs= 44.1 kHz; code = 0; A-weighted 100 dB

fs= 96 kHz; code = 0; A-weighted 98 dB

αCS channel separation 100 dB

PSRR power supply rejection ratio fripple = 1 kHz; Vripple = 30 mV (p-p) 60 dB

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Output clock timing in video mode (see Fig.6)

Tsys output clock cycle fo= 12.228 MHz −81.38 −ns

fo= 18.432 MHz −54.25 −ns

tCWL output clock LOW time fo= 12.228 MHz 0.3Tsys −0.7Tsys ns

fo= 18.432 MHz 0.4Tsys −0.6Tsys ns

tCWH output clock HIGH time fo= 12.228 MHz 0.3Tsys −0.7Tsys ns

fo= 18.432 MHz 0.4Tsys −0.6Tsys ns

Serial input data timing (see Fig.7)

fBCK bit clock frequency −−64fsHz

tBCKH bit clock HIGH time 50 −−ns

tBCKL bit clock LOW time 50 −−ns

trrise time −−20 ns

tffall time −−20 ns

tsu(DATAI) set-up time data input 20 −−ns

th(DATAI) hold time data input 0 −−ns

tsu(WS) set-up time word select 20 −−ns

th(WS) hold time word select 10 −−ns

SYMBOL PARAMETER CONDITIONS TYP. UNIT

2000 Jul 31 14

Philips Semiconductors Product speciﬁcation

Low power audio DAC with PLL UDA1334ATS

handbook, full pagewidth

MGR984

Tsys

tCWH

tCWL

Fig.6 Output clock timing.

handbook, full pagewidth

MGL880

th(WS)

tsu(WS)

tsu(DATAI) th(DATAI)

tBCKH

tBCKL

Tcy(BCK)

BCK

DATAI

Fig.7 Serial interface timing.

2000 Jul 31 15

Philips Semiconductors Product speciﬁcation

Low power audio DAC with PLL UDA1334ATS

15 APPLICATION INFORMATION

handbook, full pagewidth

MGL971

UDA1334ATS

SYSCLK/PLL1

BCK

DATAI

14 VOUTL R3

100 Ω

220 kΩ

16 VOUTR R4

100 Ω

220 kΩ

SFOR1

SFOR0

DEEM/CLKOUT

PLL0

MUTE

47 µF

(16 V)

47 µF

(16 V)

C3 left

output

right

output

12 Vref(DAC)

47 µF

(16 V)

100 nF

(63 V)

VDDD

VSSD

1 Ω

digital

supply voltage

15 13

VSSA VDDA

1 Ω

47 µF

(16 V)

C10

100 nF

(63 V) 100 nF

(63 V)

analog

supply voltage

47 µF

(16 V)

C1 10 nF

(63 V)

10 nF

(63 V)

Fig.8 Audio mode application diagram.

In audio mode, the system does not need to supply a system clock.

2000 Jul 31 16

Philips Semiconductors Product speciﬁcation

Low power audio DAC with PLL UDA1334ATS

handbook, full pagewidth

MGL974

47 Ω

UDA1334ATS

SYSCLK/PLL1

27 MHz

clock

BCK

DATAI

14 VOUTL R3

100 Ω

220 kΩ

16 VOUTR R4

100 Ω

220 kΩ

SFOR1

SFOR0

audio clock

I2S-bus

(master)

DEEM/CLKOUT

PLL0

MUTE

MPEG

DECODER 47 µF

(16 V)

47 µF

(16 V)

C3 left

output

right

output

12 Vref(DAC)

47 µF

(16 V)

100 nF

(63 V)

VDDD

VSSD

1 Ω

digital

supply voltage

15 13

VSSA VDDA

1 Ω

47 µF

(16 V)

C10

100 nF

(63 V) 100 nF

(63 V)

analog

supply voltage

47 µF

(16 V)

C1 10 nF

(63 V)

10 nF

(63 V)

Fig.9 Video mode application diagram.

In video mode, a clock output signal is generated by the UDA1334ATS which is master for the audio signals in the system; the digital audio interface is

slave, which means the system must generate the BCK and WS signal from the UDA1334ATS output clock.

2000 Jul 31 17

Philips Semiconductors Product speciﬁcation

Low power audio DAC with PLL UDA1334ATS

16 PACKAGE OUTLINE

UNIT A1A2A3bpcD

(1) E(1) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC EIAJ

mm 0.15

0.00 1.4

1.2 0.32

0.20 0.25

0.13 5.30

5.10 4.5

4.3 0.65 6.6

6.2 0.65

0.45 0.48

0.18 10

0.130.2 0.1

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.

0.75

0.45

1.0

SOT369-1 MO-152 95-02-04

99-12-27

yHE

detail X

vMA

(A )

0.25

16 9

pin 1 index

0 2.5 5 mm

scale

SSOP16: plastic shrink small outline package; 16 leads; body width 4.4 mm SOT369-1

max.

1.5

2000 Jul 31 18

Philips Semiconductors Product speciﬁcation

Low power audio DAC with PLL UDA1334ATS

17 SOLDERING

17.1 Introduction to soldering surface mount

packages

Thistextgivesavery brief insight toa complextechnology.

A more in-depth account of soldering ICs can be found in

our

“Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).

There is no soldering method that is ideal for all surface

mount IC packages. Wave soldering is not always suitable

for surface mount ICs, or for printed-circuit boards with

high population densities. In these situations reflow

soldering is often used.

17.2 Reﬂow soldering

Reflow soldering requires solder paste (a suspension of

fine solder particles, flux and binding agent) to be applied

tothe printed-circuit boardby screen printing,stencillingor

pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,

infrared/convection heating in a conveyor type oven.

Throughput times (preheating, soldering and cooling) vary

between 100 and 200 seconds depending on heating

method.

Typical reflow peak temperatures range from

215 to 250 °C. The top-surface temperature of the

packages should preferable be kept below 230 °C.

17.3 Wave soldering

Conventional single wave soldering is not recommended

forsurfacemountdevices(SMDs)orprinted-circuitboards

with a high component density, as solder bridging and

non-wetting can present major problems.

To overcome these problems the double-wave soldering

method was specifically developed.

If wave soldering is used the following conditions must be

observed for optimal results:

•Use a double-wave soldering method comprising a

turbulent wave with high upward pressure followed by a

smooth laminar wave.

•For packages with leads on two sides and a pitch (e):

– larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the

transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the

printed-circuit board.

The footprint must incorporate solder thieves at the

downstream end.

•Forpackageswithleadsonfoursides,thefootprintmust

be placed at a 45°angle to the transport direction of the

printed-circuit board. The footprint must incorporate

solder thieves downstream and at the side corners.

During placement and before soldering, the package must

be fixed with a droplet of adhesive. The adhesive can be

applied by screen printing, pin transfer or syringe

dispensing. The package can be soldered after the

adhesive is cured.

Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal

of corrosive residues in most applications.

17.4 Manual soldering

Fix the component by first soldering two

diagonally-opposite end leads. Use a low voltage (24 V or

less) soldering iron applied to the flat part of the lead.

Contact time must be limited to 10 seconds at up to

300 °C.

When using a dedicated tool, all other leads can be

soldered in one operation within 2 to 5 seconds between

270 and 320 °C.

2000 Jul 31 19

Philips Semiconductors Product speciﬁcation

Low power audio DAC with PLL UDA1334ATS

17.5 Suitability of surface mount IC packages for wave and reﬂow soldering methods

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum

temperature (with respect to time) and body size of the package, there is a risk that internal or external package

cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the

Drypack information in the

“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink

(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.

The package footprint must incorporate solder thieves downstream and at the side corners.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;

it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is

definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

PACKAGE SOLDERING METHOD

WAVE REFLOW(1)

BGA, LFBGA, SQFP, TFBGA not suitable suitable

HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not suitable(2) suitable

PLCC(3), SO, SOJ suitable suitable

LQFP, QFP, TQFP not recommended(3)(4) suitable

SSOP, TSSOP, VSO not recommended(5) suitable

2000 Jul 31 20

Philips Semiconductors Product speciﬁcation

Low power audio DAC with PLL UDA1334ATS

18 DATA SHEET STATUS

Note

1. Please consult the most recently issued data sheet before initiating or completing a design.

DATA SHEET STATUS PRODUCT

STATUS DEFINITIONS (1)

Objective speciﬁcation Development This data sheet contains the design target or goal speciﬁcations for

product development. Speciﬁcation may change in any manner without

notice.

Preliminary speciﬁcation Qualiﬁcation This data sheet contains preliminary data, and supplementary data will be

published at a later date. Philips Semiconductors reserves the right to

make changes at any time without notice in order to improve design and

supply the best possible product.

Product speciﬁcation Production This data sheet contains ﬁnal speciﬁcations. Philips Semiconductors

reserves the right to make changes at any time without notice in order to

improve design and supply the best possible product.

19 DEFINITIONS

Short-form specification  The data in a short-form

specification is extracted from a full data sheet with the

same type number and title. For detailed information see

the relevant data sheet or data handbook.

Limiting values definition Limiting values given are in

accordance with the Absolute Maximum Rating System

(IEC 60134). Stress above one or more of the limiting

values may cause permanent damage to the device.

These are stress ratings only and operation of the device

attheseorat any otherconditionsabovethose given inthe

Characteristics sections of the specification is not implied.

Exposure to limiting values for extended periods may

affect device reliability.

Application information  Applications that are

described herein for any of these products are for

illustrative purposes only. Philips Semiconductors make

norepresentation or warranty thatsuchapplicationswillbe

suitable for the specified use without further testing or

modification.

20 DISCLAIMERS

Life support applications  These products are not

designed for use in life support appliances, devices, or

systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips

Semiconductorscustomers using orsellingtheseproducts

for use in such applications do so at their own risk and

agree to fully indemnify Philips Semiconductors for any

damages resulting from such application.

Right to make changes  Philips Semiconductors

reserves the right to make changes, without notice, in the

products, including circuits, standard cells, and/or

software, described or contained herein in order to

improve design and/or performance. Philips

Semiconductors assumes no responsibility or liability for

theuseofanyoftheseproducts,conveysnolicenceortitle

under any patent, copyright, or mask work right to these

products,andmakes no representationsorwarranties that

these products are free from patent, copyright, or mask

work right infringement, unless otherwise specified.

2000 Jul 31 21

Philips Semiconductors Product speciﬁcation

Low power audio DAC with PLL UDA1334ATS

NOTES

2000 Jul 31 22

Philips Semiconductors Product speciﬁcation

Low power audio DAC with PLL UDA1334ATS

NOTES

2000 Jul 31 23

Philips Semiconductors Product speciﬁcation

Low power audio DAC with PLL UDA1334ATS

NOTES

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed

without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license

under patent- or other industrial or intellectual property rights.

Internet: http://www.semiconductors.philips.com

2000 70

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Printed in The Netherlands 753503/25/02/pp24 Date of release: 2000 Jul 31 Document order number: 9397 750 07238