55 V, EMI Enhanced, Zero Drift, Ultralow Noise,
Rail-to-Rail Output Operational Amplifier
Data Sheet
ADA4522-2
FEATURES
Low offset voltage: 5 µV maximum
Extremely low offset drift: 22 nV/°C maximum
Low voltage noise: 5.8 nV/√Hz typical
117 nV p-p from 0.1 Hz to 10 Hz typical
Low input bias current: 50 pA typical
Unity-gain crossover: 3 MHz
Single-supply operation: input voltage range includes
ground and rail-to-rail output
Wide range of operating voltages
Single-supply operation: 4.5 V to 55 V
Dual-supply operation: ±2.25 V to ±27.5 V
Integrated EMI filters
Unity-gain stable
APPLICATIONS
LCR meter/megohmmeter front-end amplifiers
Load cell and bridge transducers
Magnetic force balance scales
High precision shunt current sensing
Thermocouple/RTD sensors
PLC input and output amplifiers
PIN CONNECTION DIAGRAM
OUT A
1
–IN A
2
+IN A
3
V–
4
V+
8
OUT B
7
–IN B
6
+IN B
5
ADA4522-2
TOP VIEW
(Not to Scale)
13168-001
Figure 1. 8-Lead MSOP (RM Suffix) and 8-Lead SOIC (R Suffix)
Pin Configuration
GENERAL DESCRIPTION
The ADA4522-2 is a dual channel, zero drift op amp with low
noise and power, ground sensing inputs, and rail-to-rail output,
optimized for total accuracy over time, temperature, and voltage
conditions. The wide operating voltage and temperature ranges,
as well as the high open-loop gain and very low dc and ac errors
make the device well suited for amplifying very small input
signals and for accurately reproducing larger signals in a wide
variety of applications.
The ADA4522-2 performance is specified at 5.0 V, 30 V, an d 55 V
power supply voltages and it operates over the range of 4.5 V to
55 V. It is an excellent selection for applications using single-ended
supplies of 5 V, 1 0 V, 12 V, and 30 V, or for applications using
higher single supplies and dual supplies of ±2.5 V, ±5 V, a nd
±15 V. T he ADA4522-2 uses on-chip filtering to achieve high
immunity to electromagnetic interference (EMI).
The ADA4522-2 is fully specified over the extended industrial
temperature range of −40°C to +125°C and is available in 8-lead
MSOP and 8-lead SOIC packages.
100
10
1
0.1
10 100k 1M10k1k100
VOLTAGE NOISE DENSITY (nV/√Hz)
FREQUENCY (Hz)
AV = +100 5V
30V
55V
13168-165
Figure 2. Voltage Noise Density, VSY = ±15 V
Table 1. Zero Drift Op Amps (<0.1 µV/°C)
Supply Voltage 5 V 16 V 30 V 55 V
Single
ADA4528-1
AD8638
ADA4638-1
AD8628
AD8538
ADA4051-1
Dual ADA4528-2 AD8639 ADA4522-2
AD8629
AD8539
ADA4051-2
Quad AD8630
Rev. 0 Document Feedback
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ADA4522-2 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Pin Connection Diagram ................................................................ 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Electrical Characteristics—5.0 V Operation ............................ 3
Electrical Characteristics—30 V Operation ............................. 4
Electrical Characteristics—55 V Operation ............................. 5
Absolute Maximum Ratings ............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution .................................................................................. 7
Pin Configuration and Function Descriptions ............................. 8
Typical Performance Characteristics ............................................. 9
Applications Information .............................................................. 20
Theory of Operation .................................................................. 20
On-Chip Input EMI Filter and Clamp Circuit ....................... 20
Thermal Shutdown .................................................................... 21
Input Protection ......................................................................... 21
Single Supply and Rail-to-Rail Output .................................... 21
Large Signal Transient Response .............................................. 22
Noise Considerations ................................................................. 22
EMI Rejection Ratio .................................................................. 24
Single-Supply Instrumentation Amplifier .............................. 24
Load Cell/Strain Gage Sensor Signal Conditioning .............. 25
Precision Low-Side Current Shunt Sensor.............................. 26
Printed Circuit Board Layout ................................................... 26
Comparator Operation .............................................................. 27
Outline Dimensions ....................................................................... 28
Ordering Guide .......................................................................... 28
REVISION HISTORY
5/15—Revision 0: Initial Version
Rev. 0 | Page 2 of 28
Data Sheet ADA4522-2
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5.0 V OPERATION
VSY = 5.0 V, VCM = VSY/2 V, TA = 25°C, unless otherwise specified.
Table 2.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage VOS VCM = VSY/2 0.7 5 µV
−40°C ≤ TA ≤ +125°C 6.5 µV
Offset Voltage Drift ΔVOS/ΔT 2.5 15 nV/°C
Input Bias Current IB 50 150 pA
−40°C ≤ TA ≤ +85°C 500 pA
−40°C ≤ TA ≤ +125°C 2 nA
Input Offset Current IOS 80 250 pA
−40°C ≤ TA ≤ +85°C 350 pA
−40°C ≤ TA ≤ +125°C 500 pA
Input Voltage Range IVR 0 3.5 V
Common-Mode Rejection Ratio CMRR VCM = 0 V to 3.5 V 135 155 dB
−40°C ≤ TA ≤ +125°C 130 dB
Large Signal Voltage Gain AVO RL = 10 kΩ, VOUT = 0.5 V to 4.5 V 125 145 dB
−40°C ≤ T
A
≤ +125°C
125
dB
Input Resistance
Differential Mode RINDM 30 kΩ
Common Mode RINCM 100 GΩ
Input Capacitance
Differential Mode
C
INDM
7
pF
Common Mode CINCM 35 pF
OUTPUT CHARACTERISTICS
Output Voltage High VOH RL = 10 kΩ to VSY/2 4.97 4.98 V
−40°C ≤ TA ≤ +125°C 4.95 V
Output Voltage Low VOL RL = 10 kΩ to VSY/2 20 30 mV
−40°C ≤ TA ≤ +125°C 50 mV
Continuous Output Current IOUT Dropout voltage = 1 V 14 mA
Short-Circuit Current Source ISC+ 22 mA
T
A
= 125°C
15
mA
Short-Circuit Current Sink ISC− 29 mA
TA = 125°C 19 mA
Closed-Loop Output Impedance ZOUT f = 1 MHz, AV = +1 4 Ω
POWER SUPPLY
Power Supply Rejection Ratio PSRR VSY = 4.5 V to 55 V 150 160 dB
−40°C ≤ TA ≤ +125°C 145 dB
Supply Current per Amplifier ISY IOUT = 0 mA 830 900 µA
−40°C ≤ TA ≤ +125°C 950 µA
DYNAMIC PERFORMANCE
Slew Rate SR+ RL = 10 kΩ, CL = 50 pF, AV = 1 1.4 V/µs
SR−
R
L
= 10 kΩ, C
L
= 50 pF, A
V
= 1
1.3
V/µs
Gain Bandwidth Product GBP VIN = 10 mV p-p, RL = 10 kΩ, CL = 50 pF, AVO = 100 2.7 MHz
Unity-Gain Crossover UGC VIN = 10 mV p-p, RL = 10 kΩ, CL = 50 pF, AVO = 1 3 MHz
−3 dB Closed-Loop Bandwidth f−3dB VIN = 10 mV p-p, RL = 10 kΩ, CL = 50 pF, AV = 1 6.5 MHz
Phase Margin ΦM VIN = 10 mV p-p, RL = 10 kΩ, CL = 50 pF, AVO = 1 64 Degrees
Settling Time to 0.1% tS VIN = 1 V step, RL = 10 kΩ, CL = 50 pF, AV = 1 4 µs
Channel Separation CS VIN = 1 V p-p, f = 10 kHz, RL = 10 kΩ, CL = 50 pF 98 dB
Rev. 0 | Page 3 of 28
ADA4522-2 Data Sheet
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
EMI Rejection Ratio of +IN x EMIRR VIN = 100 mVPEAK, f = 400 MHz 72 dB
VIN = 100 mVPEAK, f = 900 MHz 80 dB
VIN = 100 mVPEAK, f = 1800 MHz 83 dB
VIN = 100 mVPEAK, f = 2400 MHz 85 dB
NOISE PERFORMANCE
Total Harmonic Distortion + Noise THD + N AV = +1, f = 1 kHz, VIN = 0.6 V rms
Bandwidth (BW) = 80 kHz 0.001 %
BW = 500 kHz 0.02 %
Peak-to-Peak Voltage Noise eN p-p AV = 100, f = 0.1 Hz to 10 Hz 117 nV p-p
Voltage Noise Density eN AV = 100, f = 1 kHz 5.8 nV/√Hz
Peak-to-Peak Current Noise iN p-p AV = 100, f = 0.1 Hz to 10 Hz 16 pA p-p
Current Noise Density iN AV = 100, f = 1 kHz 0.8 pA/√Hz
ELECTRICAL CHARACTERISTICS—30 V OPERATION
VSY = 30 V, VCM = VSY/2 V, TA = 25°C, unless otherwise specified.
Table 3.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage VOS VCM = VSY/2 1 5 µV
−40°C ≤ TA ≤ +125°C 7.2 µV
Offset Voltage Drift ΔVOS/ΔT 4 22 nV/°C
Input Bias Current IB 50 150 pA
−40°C ≤ TA ≤ +85°C 500 pA
−40°C ≤ TA ≤ +125°C 3 nA
Input Offset Current
I
OS
80
300
pA
−40°C ≤ TA ≤ +85°C 400 pA
−40°C ≤ TA ≤ +125°C 500 pA
Input Voltage Range IVR 0 28.5 V
Common-Mode Rejection Ratio CMRR VCM = 0 V to 28.5 V 145 160 dB
−40°C ≤ TA ≤ +125°C 140 dB
Large Signal Voltage Gain AVO RL = 10 kΩ, VOUT = 0.5 V to 29.5 V 140 150 dB
−40°C ≤ TA ≤ +125°C 135 dB
Input Resistance
Differential Mode RINDM 30 kΩ
Common Mode RINCM 400 GΩ
Input Capacitance
Differential Mode CINDM 7 pF
Common Mode CINCM 35 pF
OUTPUT CHARACTERISTICS
Output Voltage High VOH RL = 10 kΩ to VSY/2 29.87 29.89 V
−40°C ≤ TA ≤ +125°C 29.80 V
Output Voltage Low VOL RL = 10 kΩ to VSY/2 110 130 mV
−40°C ≤ TA ≤ +125°C 200 mV
Continuous Output Current IOUT Dropout voltage = 1 V 14 mA
Short-Circuit Current Source ISC+ 21 mA
TA = +125°C 15 mA
Short-Circuit Current Sink ISC− 33 mA
TA = +125°C 22 mA
Closed-Loop Output Impedance ZOUT f = 1 MHz, AV = +1 4 Ω
Rev. 0 | Page 4 of 28
Data Sheet ADA4522-2
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
POWER SUPPLY
Power Supply Rejection Ratio PSRR VSY = 4.5 V to 55 V 150 160 dB
−40°C ≤ TA ≤ +125°C 145 dB
Supply Current per Amplifier ISY IOUT = 0 mA 830 900 µA
−40°C ≤ T
A
≤ +125°C
950
µA
DYNAMIC PERFORMANCE
Slew Rate SR+ RL = 10 kΩ, CL = 50 pF, AV = 1 1.8 V/µs
SR− RL = 10 kΩ, CL = 50 pF, AV = 1 0.9 V/µs
Gain Bandwidth Product GBP VIN = 10 mV p-p, RL = 10 kΩ, CL = 50 pF, AVO = 100 2.7 MHz
Unity-Gain Crossover UGC VIN = 10 mV p-p, RL = 10 kΩ, CL = 50 pF, AVO =1 3 MHz
−3 dB Closed-Loop Bandwidth f−3 dB VIN = 10 mV p-p, RL = 10 kΩ, CL = 50 pF, AV = 1 6.5 MHz
Phase Margin ΦM VIN = 10 mV p-p, RL = 10 kΩ, CL = 50 pF, AVO = 1 64 Degrees
Settling Time to 0.1% tS VIN = 10 V step, RL = 10 kΩ, CL = 50 pF, AV = 1 12 µs
Settling Time to 0.01%
t
S
V
IN
= 10 V step, R
L
= 10 kΩ, C
L
= 50 pF, A
V
= 1
14
µs
Channel Separation CS VIN = 10 V p-p, f = 10 kHz, RL = 10 kΩ, CL = 50 pF 98 dB
EMI Rejection Ratio of +IN x EMIRR VIN = 100 mVPEAK, f = 400 MHz 72 dB
VIN = 100 mVPEAK, f = 900 MHz 80 dB
VIN = 100 mVPEAK, f = 1800 MHz 83 dB
V
IN
= 100 mV
PEAK
, f = 2400 MHz
85
dB
NOISE PERFORMANCE
Total Harmonic Distortion + Noise THD + N AV = +1, f = 1 kHz, VIN = 6 V rms
BW = 80 kHz 0.0005 %
BW = 500 kHz 0.004 %
Peak-to-Peak Voltage Noise eN p-p AV = 100, f = 0.1 Hz to 10 Hz 117 nV p-p
Voltage Noise Density eN AV = 100, f = 1 kHz 5.8 nV/√Hz
Peak-to-Peak Current Noise iN p-p AV = 100, f = 0.1 Hz to 10 Hz 16 pA p-p
Current Noise Density iN AV = 100, f = 1 kHz 0.8 pA/√Hz
ELECTRICAL CHARACTERISTICS—55 V OPERATION
VSY = 55 V, VCM = VSY/2 V, TA = 25°C, unless otherwise specified.
Table 4.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage VOS VCM = VSY/2 1.5 7 µV
−40°C ≤ TA ≤ +125°C 10 µV
Offset Voltage Drift ΔVOS/ΔT 6 30 nV/°C
Input Bias Current IB 50 150 pA
−40°C ≤ TA ≤ +85°C 500 pA
−40°C ≤ T
A
≤ +125°C
4.5
nA
Input Offset Current IOS 80 300 pA
−40°C ≤ TA ≤ +85°C 400 pA
−40°C ≤ TA ≤ +125°C 500 pA
Input Voltage Range IVR 0 53.5 V
Common-Mode Rejection Ratio CMRR VCM = 0 V to 53.5 V 140 144 dB
−40°C ≤ TA ≤ +125°C 135 dB
Large Signal Voltage Gain AVO RL = 10 kΩ, VOUT = 0.5 V to 54.5 V 135 137 dB
−40°C ≤ TA ≤ +125°C 125 dB
Input Resistance
Differential Mode RINDM 30 kΩ
Common Mode RINCM 1000 GΩ
Rev. 0 | Page 5 of 28
ADA4522-2 Data Sheet
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
Input Capacitance
Differential Mode CINDM 7 pF
Common Mode CINCM 35 pF
OUTPUT CHARACTERISTICS
Output Voltage High VOH RL = 10 kΩ to VSY/2 54.75 54.8 V
−40°C ≤ TA ≤ +125°C 54.65 V
Output Voltage Low VOL RL = 10 kΩ to VSY/2 200 250 mV
−40°C ≤ TA ≤ +125°C 350 mV
Continuous Output Current IOUT Dropout voltage = 1 V 14 mA
Short-Circuit Current Source ISC+ 21 mA
TA = 125°C 15 mA
Short-Circuit Current Sink ISC− 32 mA
TA = 125°C 22 mA
Closed-Loop Output Impedance
Z
OUT
f = 1 MHz, A
V
= +1
4
Ω
POWER SUPPLY
Power Supply Rejection Ratio
PSRR
V
SY
= 4.5 V to 55 V
150
160
dB
−40°C ≤ TA ≤ +125°C 145 dB
Supply Current per Amplifier ISY IOUT = 0 mA 830 900 µA
−40°C ≤ TA ≤ +125°C 950 µA
DYNAMIC PERFORMANCE
Slew Rate SR+ RL = 10 kΩ, CL = 50 pF, AV = 1 1.7 V/µs
SR- RL = 10 kΩ, CL = 50 pF, AV = 1 0.8 V/µs
Gain Bandwidth Product GBP VIN = 10 mV p-p, RL = 10 kΩ, CL = 50 pF, AVO = 100 2.7 MHz
Unity-Gain Crossover UGC VIN = 10 mV p-p, RL = 10 kΩ, CL = 50 pF, AVO = 1 3 MHz
−3 dB Closed-Loop Bandwidth
f
−3 dB
V
IN
= 10 mV p-p, R
L
= 10 kΩ, C
L
= 50 pF, A
V
= 1
6.5
MHz
Phase Margin ΦM VIN = 10 mV p-p, RL = 10 kΩ, CL = 50 pF, AVO = 1 64 Degrees
Settling Time to 0.1% tS VIN = 10 V step, RL = 10 kΩ, CL = 50 pF, AV = 1 12 µs
Settling Time to 0.01% tS VIN = 10 V step, RL = 10 kΩ, CL = 50 pF, AV = 1 14 µs
Channel Separation CS VIN = 10 V p-p, f = 10 kHz, RL = 10 kΩ, CL = 50 pF 98 dB
EMI Rejection Ratio of +IN x
EMIRR
V
IN
= 100 mV
PEAK
, f = 400 MHz
72
dB
VIN = 100 mVPEAK, f = 900 MHz 80 dB
VIN = 100 mVPEAK, f = 1800 MHz 83 dB
VIN = 100 mVPEAK, f = 2400 MHz 85 dB
NOISE PERFORMANCE
Total Harmonic Distortion + Noise THD + N AV = +1, f = 1 kHz, VIN = 10 V rms
BW = 80 kHz 0.0007 %
BW = 500 kHz 0.003 %
Peak-to-Peak Voltage Noise eN p-p AV = 100, f = 0.1 Hz to 10 Hz 117 nV p-p
Voltage Noise Density
e
N
A
V
= 100, f = 1 kHz
5.8
nV/√Hz
Peak-to-Peak Current Noise iN p-p AV = 100, f = 0.1 Hz to 10 Hz 16 pA p-p
Current Noise Density iN AV = 100, f = 1 kHz 0.8 pA/√Hz
Rev. 0 | Page 6 of 28
Data Sheet ADA4522-2
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Rating
Supply Voltage 60 V
Input Voltage
(V−) − 300 mV to (V+) + 300 mV
Input Current1 ±10 mA
Differential Input Voltage ±5 V
Output Short-Circuit
Duration to Ground
Indefinite
Temperature Range
Storage
−65°C to +150°C
Operating −40°C to +125°C
Junction −65°C to +150°C
Lead Temperature (Soldering,
60 sec)
300°C
1 The input pins have clamp diodes to the power supply pins. Limit the input
current to 10 mA or less whenever input signals exceed the power supply
rail by 0.3 V.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
θJA is specified for the worst case conditions, that is, a device
soldered in a circuit board for surface-mount packages using a
standard 4-layer JEDEC board.
Table 6. Thermal Resistance
Package Type
θ
JA
θ
JC
Unit
8-Lead MSOP (RM-8) 190 44 °C/W
8-Lead SOIC (R-8)
158
43
°C/W
ESD CAUTION
Rev. 0 | Page 7 of 28
ADA4522-2 Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
OUT A 1
–IN A 2
+IN A 3
V– 4
V+
8
OUT B
7
–IN B
6
+IN B
5
ADA4522-2
TOP VIEW
(Not to Scale)
13168-002
Figure 3. Pin Configuration
Table 7. Pin Function Descriptions
Pin No. Mnemonic Description
1
OUT A
Output, Channel A
2 −IN A Inverting Input, Channel A
3 +IN A Noninverting Input, Channel A
4 V− Negative Supply Voltage
5 +IN B Noninverting Input, Channel B
6 −IN B Inverting Input, Channel B
7 OUT B Output, Channel B
8 V+ Positive Supply Voltage
Rev. 0 | Page 8 of 28
Data Sheet ADA4522-2
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
90
0
10
20
30
40
50
60
70
80
–5 –4 –3 –2 –1 0 1 2 3 4 5
NUMBER OF AMPLIFIERS
VOS (µV)
VSY = ±2.5V
VCM = VSY/2
600 CHANNELS
MEAN = 0.10µV
STD DEV. = 0.59µV
13168-003
Figure 4. Input Offset Voltage Distribution, VSY = ±2.5 V
80
0
10
20
30
40
50
60
70
–5 –4 –3 –2 –1 0 1 2 3 4 5
NUMBER OF AMPLIFIERS
VOS (µV)
VSY = ±15V
VCM = VSY/2
600 CHANNELS
MEAN = 0.31µV
STD DEV. = 0.62µV
13168-004
Figure 5. Input Offset Voltage Distribution, VSY = ±15 V
70
0
10
20
30
40
50
60
–5 –4 –3 –2 –1 0 1 2 3 4 5
NUMBER OF AMPLIFIERS
VOS (µV)
VSY = ±27.5V
VCM = VSY/2
600 CHANNELS
MEAN = 0.69µV
STD DEV. = 0.81µV
13168-005
Figure 6. Input Offset Voltage Distribution, VSY = ±27.5 V
35
0
5
10
15
20
25
30
–30 –25 –20 –15 –10 –5 0 5 10 15 2520 30
NUMBER OF AMPLIFIERS
TCVOS (nV/°C)
VSY = ±2.5V
–40°C ≤ TA ≤ +125°C
160 CHANNELS
MEAN = –1.19nV/°C
STD DEV. = 1.82nV/°C
13168-006
Figure 7. Input Offset Voltage Drift Distribution, VSY = ±2.5 V
35
0
5
10
15
20
25
30
–30 –25 –20 –15 –10 –5 0 5 10 15 2520 30
NUMBER OF AMPLIFIERS
TCVOS (nV/°C)
VSY = ±15V
–40°C ≤ TA ≤ +125°C
160 CHANNELS
MEAN = –2.48nV/°C
STD DEV. = 2.65nV/°C
13168-007
Figure 8. Input Offset Voltage Drift Distribution, VSY = ±15 V
35
0
5
10
15
20
25
30
–30 –25 –20 –15 –10 –5 0 5 10 15 2520 30
NUMBER OF AMPLIFIERS
TCVOS (nV/°C)
VSY = ±27.5V
–40°C ≤ TA ≤ +125°C
160 CHANNELS
MEAN = –4.54nV/°C
STD DEV. = 4.01nV/°C
13168-008
Figure 9. Input Offset Voltage Drift Distribution, VSY = ±27.5 V
Rev. 0 | Page 9 of 28
ADA4522-2 Data Sheet
5
–5
–3
1
–1
3
01.0 3.02.0 3.5
VOS (µV)
VCM (V)
VSY = 5V
20 CHANNELS
13168-009
Figure 10. Input Offset Voltage (VOS) vs. Common-Mode Voltage (VCM), VSY = 5 V
5
–5
–3
1
–1
3
05.0 25.015.010.0 20.0 28.5
V
OS
(µV)
V
CM
(V)
V
SY
= 30V
20 CHANNELS
13168-010
Figure 11. Input Offset Voltage (VOS) vs. Common-Mode Voltage (VCM),
VSY = 30 V
5
–5
–3
1
–1
3
05.0 45.025.015.0 35.010.0 50.030.020.0 40.0 53.5
VOS (µV)
VCM (V)
VSY = 55V
20 CHANNELS
13168-011
Figure 12. Input Offset Voltage (VOS) vs. Common-Mode Voltage (VCM),
VSY = 55 V
2000
–500
0
1000
500
1500
00.5 2.51.51.0 3.02.0 3.5
IB (pA)
VCM (V)
+125°C
+85°C
+25°C
–40°C
VSY = 5V
13168-012
Figure 13. Input Bias Current (IB) vs. Common-Mode Voltage (VCM), VSY = 5 V
3000
–500
0
2000
1000
1500
500
2500
05.0 25.015.010.0 20.0 28.5
I
B
(pA)
V
CM
(V)
+125°C
+85°C
+25°C
–40°C
V
SY
= 30V
13168-013
Figure 14. Input Bias Current (IB) vs. Common-Mode Voltage (VCM), VSY = 30 V
5000
–500
0
3500
1500
2500
500
4500
3000
1000
2000
4000
010.0 50.030.020.0 40.05.0 45.025.015.0 35.0 53.5
IB (pA)
VCM (V)
+125°C
+85°C
+25°C
–40°C
VSY = 55V
13168-014
Figure 15. Input Bias Current (IB) vs. Common-Mode Voltage (VCM),
VSY = 55 V
Rev. 0 | Page 10 of 28
Data Sheet ADA4522-2
1600
–400
–200
1200
400
800
0
1000
200
600
1400
–50 010050–25 7525 125
IB (pA)
TEMPERATURE (°C)
VSY = ±2.5V
VCM = VSY/2
IB+
IB–
IOS
13168-015
Figure 16. Input Bias Current (IB) vs. Temperature, VSY = ±2.5 V
2500
–500
0
1500
500
1000
2000
–50 010050–25 7525 125
IB (pA)
TEMPERATURE (°C)
VSY = ±15V
VCM = VSY/2
IB+
IB–
IOS
13168-017
Figure 17. Input Bias Current (IB) vs. Temperature, VSY = ±15 V
VSY = ±2.5V TO ±27.5V
100k
0.1
100
1
10
1k
10k
0.001 0.1 100.01 1100
OUTPUT VOLTAGE (VOH) TO SUPPLY RAIL (mV)
ILOAD (mA)
13168-024
+125°C
+85°C
+25°C
–40°C
Figure 18. Output Voltage High (VOH) to Supply Rail vs. Load Current (ILOAD)
4000
–1000
–500
3000
1000
2000
0
2500
500
1500
3500
–50 010050–25 7525 125
IB (pA)
TEMPERATURE (°C)
VSY = ±27.5V
VCM = VSY/2
IB+
IB–
IOS
13168-016
Figure 19. Input Bias Current (IB) vs. Temperature, VSY = ±27.5 V
1.0
0
0.4
0.2
0.6
0.8
0 5 10 15 20 25 30 35 40 45 50 55 60
ISY PER AMP (mA)
VSY (V)
+125°C
+85°C
+25°C
–40°C
13168-025
Figure 20. Supply Current (ISY) per Amplifier vs. Supply Voltage (VSY)
100k
0.1
100
1
10
1k
10k
0.001 0.1 100.01 1100
OUTPUT VOLTAGE (VOL) TO SUPPLY RAIL (mV)
ILOAD (mA)
VSY = ±2.5V TO ±27.5V
13168-027
+125°C
+85°C
+25°C
–40°C
Figure 21. Output Voltage Low (VOL) to Supply Rail vs. Load Current (ILOAD)
Rev. 0 | Page 11 of 28
ADA4522-2 Data Sheet
150
0
25
100
50
75
125
–50 012510050–25 7525 150
OUTPUT VOLTAGE (V
OH
) TO SUPPLY RAIL (mV)
TEMPERATURE (°C)
R
L
= 2kΩ
V
SY
= ±2.5V
R
L
= 10kΩ
13168-018
Figure 22. Output Voltage High (VOH) to Supply Rail vs. Temperature,
VSY = ±2.5 V
200
0
25
100
50
75
125
150
175
–50 012510050–25 7525 150
OUTPUT VOLTAGE (VOH) TO SUPPLY RAIL (mV)
TEMPERATURE (°C)
RL = 10kΩ
VSY = ±15V
RL = 100kΩ
13168-019
Figure 23. Output Voltage High (VOH) to Supply Rail vs. Temperature, VSY = ±15 V
350
0
50
200
100
150
250
300
–50 012510050–25 7525 150
OUTPUT VOLTAGE (V
OH
) TO SUPPLY RAIL (mV)
TEMPERATURE (°C)
V
SY
= ±27.5V
R
L
= 100kΩ
R
L
= 10kΩ
13168-020
Figure 24. Output Voltage High (VOH) to Supply Rail vs. Temperature,
VSY = ±27.5 V
150
0
25
100
50
75
125
–50 012510050–25 7525 150
OUTPUT VOLTAGE (V
OL
) TO SUPPLY RAIL (mV)
TEMPERATURE (°C)
V
SY
= ±2.5V
R
L
= 10kΩ
R
L
= 2kΩ
13168-021
Figure 25. Output Voltage Low (VOL) to Supply Rail vs. Temperature,
VSY = ±2.5 V
200
0
25
100
50
75
125
150
175
–50 012510050–25 7525 150
OUTPUT VOLTAGE (V
OL
) TO SUPPLY RAIL (mV)
TEMPERATURE (°C)
V
SY
= ±15V
R
L
= 100kΩ
R
L
= 10kΩ
13168-022
Figure 26. Output Voltage Low (VOL) to Supply Rail vs. Temperature, VSY = ±15 V
350
0
50
200
100
150
250
300
–50 012510050–25 7525 150
OUTPUT VOLTAGE (V
OL
) TO SUPPLY RAIL (mV)
TEMPERATURE (°C)
V
SY
= ±27.5V
R
L
= 100kΩ
R
L
= 10kΩ
13168-023
Figure 27. Output Voltage Low (VOL) to Supply Rail vs. Temperature,
VSY = ±27.5 V
Rev. 0 | Page 12 of 28
Data Sheet ADA4522-2
140
0
40
20
80
120
60
100
10 100 1k 10k 100k 1M 10M
CMRR (dB)
FREQUENCY (Hz)
VSY = ±2.5V TO ±27.5V
13168-030
Figure 28. CMRR vs. Frequency
1k
0.001
0.01
1
100
0.1
10
100 1k 10k 100k 1M 10M 100M
OUTPUT IMPEDANCE (Ω)
FREQUENCY (Hz)
AV = +100
AV = +10
AV = +1
13168-031
VSY = ±2.5V TO ±27.5V
Figure 29. Closed-Loop Output Impedance vs. Frequency
120
–40
20
0
–20
60
100
40
80
135
–45
0
45
90
100 1k 10k 100k 1M 10M
OPEN-LOOP GAIN (dB)
PHASE MARGIN (Degrees)
FREQUENCY (Hz)
C
L
= 50pF
C
L
= 100pF
C
L
= 50pF
C
L
= 100pF
13168-026
PHASE
GAIN
V
SY
= ±2.5V TO ±27.5V
R
L
= 10kΩ
Figure 30. Open-Loop Gain and Phase Margin vs. Frequency
140
–20
0
40
20
80
120
60
100
100 1k 10k 100k 1M 10M 100M
PSRR (dB)
FREQUENCY (Hz)
PSRR+
PSRR–
VSY = ±2.5V TO ±27.5V
13168-032
Figure 31. PSRR vs. Frequency
0.840
0.805
0.815
0.810
0.825
0.835
0.820
0.830
–50 –25 025 50 75 100 125 150
ISY PER AMP (mA)
TEMPERATURE (°C)
5V
30V
55V
13168-028
Figure 32. Supply Current (ISY) per Amplifier vs. Temperature
60
–20
10
0
–10
30
50
20
40
100 1k 10k 100k 1M 10M
CLOSED-LOOP GAIN (dB)
FREQUENCY (Hz)
A
V
= +100
A
V
= +10
A
V
= +1
V
SY
= ±2.5V TO ±27.5V
13168-029
Figure 33. Closed-Loop Gain vs. Frequency
Rev. 0 | Page 13 of 28
ADA4522-2 Data Sheet
2.0
–2.0
–1.0
–1.5
0
1.5
1.0
–0.5
0.5
VOLTAGE (V)
TIME (4µs/DIV)
V
SY
= ±2.5V
V
IN
= 2V p-p
A
V
= +1
R
L
= 10kΩ
C
L
= 100pF
R
S_IN+
= 100Ω
R
S_IN–
= 100Ω
13168-034
Figure 34. Large Signal Transient Response, VSY = ±2.5 V
15
–15
–10
–5
0
5
10
VOLTAGE (V)
TIME (10µs/DIV)
V
SY
= ±15V
V
IN
= 20V p-p
A
V
= +1
R
L
= 10kΩ
C
L
= 100pF
R
S_IN+
= 100Ω
R
S_IN–
= 100Ω
13168-035
Figure 35. Large Signal Transient Response, VSY = ±15 V
30
–30
–20
–10
0
10
20
VOLTAGE (V)
TIME (10µs/DIV)
V
SY
= ±27.5V
V
IN
= 50V p-p
A
V
= +1
R
L
= 10kΩ
C
L
= 100pF
R
S_IN+
= 100Ω
R
S_IN–
= 100Ω
13168-036
Figure 36. Large Signal Transient Response, VSY = ±27.5 V
0.08
–0.08
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
VOLTAGE (V)
TIME (400ns/DIV)
V
SY
= ±2.5V
V
IN
= 100mV p-p
A
V
= +1
R
L
= 10kΩ
C
L
= 100pF
13168-037
Figure 37. Small Signal Transient Response, VSY = ±2.5 V
0.08
–0.08
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
VOLTAGE (V)
TIME (400ns/DIV)
V
SY
= ±15V
V
IN
= 100mV p-p
A
V
= +1
R
L
= 10kΩ
C
L
= 100pF
13168-038
Figure 38. Small Signal Transient Response, VSY = ±15 V
0.08
–0.08
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
VOLTAGE (V)
TIME (400ns/DIV)
V
SY
= ±27.5V
V
IN
= 100mV p-p
A
V
= +1
R
L
= 10kΩ
C
L
= 100pF
13168-039
Figure 39. Small Signal Transient Response, VSY = ±27.5 V
Rev. 0 | Page 14 of 28
Data Sheet ADA4522-2
50
45
40
35
30
25
20
15
10
5
0
10 100 1000
OVERSHOOT (%)
LOAD CAPACITANCE (pF)
OS+
V
SY
= ±2.5V
R
L
= 10kΩ
A
V
= +1
V
IN
= 100mV p-p
OS–
13168-040
Figure 40. Small Signal Overshoot vs. Load Capacitance, VSY = ±2.5 V
50
45
40
35
30
25
20
15
10
5
0
10 100 1000
OVERSHOOT (%)
LOAD CAPACITANCE (pF)
OS+
V
SY
= ±15V
R
L
= 10kΩ
A
V
= +1
V
IN
= 100mV p-p
OS–
13168-041
Figure 41. Small Signal Overshoot vs. Load Capacitance, VSY = ±15 V
50
45
40
35
30
25
20
15
10
5
0
10 100 1000
OVERSHOOT (%)
LOAD CAPACITANCE (pF)
OS+
V
SY
= ±27.5V
R
L
= 10kΩ
A
V
= +1
V
IN
= 100mV p-p
OS–
13168-042
Figure 42. Small Signal Overshoot vs. Load Capacitance, VSY = ±27.5 V
0
–140
–120
–100
–80
–60
–40
–20
0.01 11000.1 10
CHANNEL SEPARATION (dB)
FREQUENCY (kHz)
VSY = ±2.5V
AV = –10
RL = 10kΩ
VIN = 0.5V p-p
VIN = 1V p-p
VIN = 2V p-p
13168-043
Figure 43. Channel Separation vs. Frequency, VSY = ±2.5 V
0
–140
–120
–100
–80
–60
–40
–20
0.01 11000.1 10
CHANNEL SEPARATION (dB)
FREQUENCY (kHz)
VSY = ±15V
AV = –10
RL = 10kΩ
VIN = 5V p-p
VIN = 10V p-p
VIN = 25V p-p
13168-044
Figure 44. Channel Separation vs. Frequency, VSY = ±15 V
0
–140
–120
–100
–80
–60
–40
–20
0.01 11000.1 10
CHANNEL SEPARATION (dB)
FREQUENCY (kHz)
V
SY
= ±27.5V
A
V
= –10
R
L
= 10kΩ
V
IN
= 10V p-p
V
IN
= 30V p-p
V
IN
= 50V p-p
13168-045
Figure 45. Channel Separation vs. Frequency, VSY = ±27.5 V
Rev. 0 | Page 15 of 28
ADA4522-2 Data Sheet
100
10
1
0.1
0.01
0.001
0.0001
0.001 10.10.01
THD + N (%)
AMPLITUDE (V rms)
V
SY
= ±2.5V
A
V
= +1
FREQUENCY = 1kHz
R
L
= 10kΩ
80kHz LOW-PASS FILTER
500kHz LOW-PASS FILTER
13168-050
Figure 46. THD + N vs. Amplitude, VSY = ±2.5 V
100
10
1
0.1
0.01
0.001
0.0001
0.001 1010.10.01
THD + N (%)
AMPLITUDE (V rms)
V
SY
= ±15V
A
V
= +1
FREQUENCY = 1kHz
R
L
= 10kΩ
80kHz LOW-PASS FILTER
500kHz LOW-PASS FILTER
13168-051
Figure 47. THD + N vs. Amplitude, VSY = ±15 V
100
10
1
0.1
0.01
0.001
0.0001
0.001 1010.10.01
THD + N (%)
AMPLITUDE (V rms)
V
SY
= ±27.5V
A
V
= +1
FREQUENCY = 1kHz
R
L
= 10kΩ
80kHz LOW-PASS FILTER
500kHz LOW-PASS FILTER
13168-052
Figure 48. THD + N vs. Amplitude, VSY = ±27.5 V
1
0.1
0.01
0.001
0.0001
10 100k10k1k100
THD + N (%)
FREQUENCY (Hz)
VSY = ±2.5V
AV = +1
RL = 10kΩ
VIN = 0.6V rms
80kHz LOW-PASS FILTER
500kHz LOW-PASS FILTER
13168-053
Figure 49. THD + N vs. Frequency, VSY = ±2.5 V
1
0.1
0.01
0.001
0.0001
10 100k10k1k100
THD + N (%)
FREQUENCY (Hz)
VSY = ±15V
AV = +1
RL = 10kΩ
VIN = 6V rms
80kHz LOW-PASS FILTER
500kHz LOW-PASS FILTER
13168-054
Figure 50. THD + N vs. Frequency, VSY = ±15 V
1
0.1
0.01
0.001
0.0001
10 100k10k1k100
THD + N (%)
FREQUENCY (Hz)
VSY = ±27.5V
AV = +1
RL = 10kΩ
VIN = 10V rms
80kHz LOW-PASS FILTER
500kHz LOW-PASS FILTER
13168-055
Figure 51. THD + N vs. Frequency, VSY = ±27.5 V
Rev. 0 | Page 16 of 28
Data Sheet ADA4522-2
0.2
–0.2
–0.6
–1.0
–1.4
0
–0.4
–0.8
–1.2
7
5
3
1
–1
6
4
2
0
INPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
TIME (1µs/DIV)
V
SY
= ±2.5V
V
IN
= 350mV p-p
R
L
= 10kΩ
C
L
= 100pF
A
V
= –10
V
IN
V
OUT
13168-056
Figure 52. Positive Overload Recovery, VSY = ±2.5 V
2
–2
–3
–10
–14
0
–4
–8
–12
35
25
15
5
–5
30
20
10
0
INPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
TIME (4µs/DIV)
VSY = ±15V
VIN = 2V p-p
RL = 10kΩ
CL = 100pF
AV = –10
VIN
VOUT
13168-057
Figure 53. Positive Overload Recovery, VSY = ±15 V
2
–2
–3
–10
–14
0
–4
–8
–12
70
50
30
10
–10
60
40
20
0
INPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
TIME (10µs/DIV)
VSY = ±27.5V
VIN = 4V p-p
RL = 10kΩ
CL = 100pF
AV = –10
VIN
VOUT
13168-058
Figure 54. Positive Overload Recovery, VSY = ±27.5 V
0.4
0
–0.4
–0.8
–1.2
0.2
–0.2
–0.6
–1.0
5
3
1
–1
–3
4
2
0
–2
INPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
TIME (1µs/DIV)
VSY = ±2.5V
VIN = 350mV p-p
RL = 10kΩ
CL = 100pF
AV = –10
VIN
VOUT
13168-059
Figure 55. Negative Overload Recovery, VSY = ±2.5 V
6
2
–2
–6
–10
4
0
–4
–8
20
10
0
–10
–20
15
5
–5
–15
INPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
TIME (2µs/DIV)
V
SY
= ±15V
V
IN
= 2V p-p
R
L
= 10kΩ
C
L
= 100pF
A
V
= –10
V
IN
V
OUT
13168-060
Figure 56. Negative Overload Recovery, VSY = ±15 V
6
2
–2
–6
–10
4
0
–4
–8
40
20
0
–20
–40
30
10
–10
–30
INPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
TIME (4µs/DIV)
V
SY
= ±27.5V
V
IN
= 4V p-p
R
L
= 10kΩ
C
L
= 100pF
A
V
= –10
V
IN
V
OUT
13168-061
Figure 57. Negative Overload Recovery, VSY = ±27.5 V
Rev. 0 | Page 17 of 28
ADA4522-2 Data Sheet
100
10
1
10 100k 100M10k 10M1k100 1M
VOLTAGE NOISE DENSITY (nV/√Hz)
FREQUENCY (Hz)
V
SY
= ±2.5V
A
V
= +1
13168-062
Figure 58. Voltage Noise Density, VSY = ±2.5 V
100
10
1
10 100k 100M10k 10M1k100 1M
VOLTAGE NOISE DENSITY (nV/√Hz)
FREQUENCY (Hz)
V
SY
= ±15V
A
V
= +1
13168-063
Figure 59. Voltage Noise Density, VSY = ±15 V
100
10
1
10 100k 100M10k 10M1k100 1M
VOLTAGE NOISE DENSITY (nV/√Hz)
FREQUENCY (Hz)
V
SY
= ±27.5V
A
V
= +1
13168-064
Figure 60. Voltage Noise Density, VSY = ±27.5 V
100
10
1
0.1
10 100k 1M10k1k100
VOLTAGE NOISE DENSITY (nV/√Hz)
FREQUENCY (Hz)
A
V
= +100 5V
30V
55V
13168-065
Figure 61. Voltage Noise Density, Av = +100
INPUT REFERRED VOLTAGE (nV)
TIME (1s/DIV)
V
SY
= ±15V AND ±27.5V
A
V
= +100
PEAK-TO-PEAK NOISE = 117nV p-p
13168-066
–100
–75
–50
–25
0
25
50
75
100
Figure 62. 0.1 Hz to 10 Hz Noise
100
10
1
10 100k10k1k100
CURRENT NOISE DENSITY (pA/√Hz)
FREQUENCY (Hz)
RS = 100kΩ
AV = +100
VSY = ±2.5V
VSY = ±15V
VSY = ±27.5V
13168-067
Figure 63. Current Noise Density
Rev. 0 | Page 18 of 28
Data Sheet ADA4522-2
INPUT VOLTAGE (1V/DIV)
TIME (2µs/DIV)
V
SY
= ±2.5V
R
L
= 10kΩ
C
L
= 50pF
DUT A
V
= –1
INPUT
OUTPUT
+10mV
0
–10mV
+1V
0
–1V
ERROR BAND
POST GAIN = 10
13168-046
Figure 64. Negative Settling Time to 0.1%, VSY = ±2.5 V
INPUT VOLTAGE (5V/DIV)
TIME (4µs/DIV)
V
SY
= ±15V AND ±27.5V
R
L
= 10kΩ
C
L
= 50pF
DUT A
V
= –1
INPUT
OUTPUT
+50mV
0
–50mV
ERROR BAND
POST GAIN = 10
13168-047
+5V
0
–5V
Figure 65. Negative Settling Time to 0.1%, VSY = ±15 V and ±27.5 V
60
0
10
30
50
20
40
100 1k 10k 100k 1M 10M
OUTPUT VOLTAGE SWING (V p-p)
FREQUENCY (Hz)
RL = 10kΩ
AV= –1
VIN = ±26.0V
VSY = ±27.5V
VIN = ±13.5V
VSY = ±15.0V
VIN = ±1.0V
VSY = ±2.5V
13168-033
Figure 66. Output Voltage Swing vs. Frequency
INPUT VOLTAGE (1V/DIV)
TIME (2µs/DIV)
V
SY
= ±2.5V
R
L
= 10kΩ
C
L
= 50pF
DUT A
V
= –1
INPUT
OUTPUT
+10mV
0
–10mV
ERROR BAND
POST GAIN = 10
13168-048
+1V
0
–1V
Figure 67. Positive Settling Time to 0.1%, VSY = ±2.5 V
INPUT VOLTAGE (5V/DIV)
TIME (4µs/DIV)
V
SY
= ±15V AND ±27.5V
R
L
= 10kΩ
C
L
= 50pF
DUT A
V
= –1
INPUT
OUTPUT
+50mV
0
–50mV
ERROR BAND
POST GAIN = 10
13168-049
+5V
0
–5V
Figure 68. Positive Settling Time to 0.1%, VSY = ±15 V and ±27.5 V
Rev. 0 | Page 19 of 28
ADA4522-2 Data Sheet
APPLICATIONS INFORMATION
The ADA4522-2 is a dual, ultralow noise, high voltage, zero
drift, rail-to-rail output operational amplifier. It features a
patented chopping technique that offers an ultralow input offset
voltage of 5 µV and an input offset voltage drift of 22 nV/°C
maximum. Offset voltage errors due to common-mode voltage
swings and power supply variations are also corrected by the
chopping technique, resulting in a superb typical CMRR figure
of 160 dB and a PSRR figure of 160 dB at a 30 V supply voltage.
The ADA4522-2 has wide operating voltages from ±2.25 V (or
4.5 V) to ±27.5 V (or 55 V). It is a single supply amplifier, where
its input voltage range includes the lower supply rail. It also offers
low broadband noise of 5.8 nV/√Hz (at f = 1 kHz, AV = 100) and
reduced 1/f noise component. These features are ideal for the
amplification of low level signals in high precision applications.
A few examples of such applications are weigh scales, high
precision current sensing, high voltage buffers, signal conditioning
for temperature sensors, among others.
THEORY OF OPERATION
Figure 69 shows the ADA4522-2 architecture block diagram. It
consists of an input EMI filter and clamp circuitry, three gain
stages (Gm1, Gm2, and Gm3), input and output chopping networks
(CHOPIN and CHOPOUT), a clock generator, offset and ripple
correction loop circuitry, frequency compensation capacitors
(C1, C2, and C3), and thermal shutdown circuitry.
An EMI filter and clamp circuit is implemented at the input
front end to protect the internal circuitry against electrostatic
discharge (ESD) stresses and high voltage transients. The ability
of the amplifier to reject EMI is explained in detail in the EMI
Rejection Ratio section.
CHOPIN and CHOPOUT are controlled by a clock generator and
operate at 4.8 MHz. The input baseband signal is initially
modulated by CHOPIN. Next, CHOPOUT demodulates the input
signal and modulates the millivolt-level input offset voltage and
1/f noise of the input transconductance amplifier, Gm1, to the
chopping frequency at 4.8 MHz. The chopping networks
remove the low frequency errors, but in return, the networks
introduce chopping artifacts at the chopping frequency.
Therefore, a patented offset and ripple correction loop,
operating at 800 kHz, is used. This frequency is the switching
frequency of the amplifier. This patented circuitry reduces
chopping artifacts, allowing the ADA4522-2 to have a high
chopping frequency with minimal artifacts.
The thermal shutdown circuit shuts down the circuit when the
die is overheated; this is explained further in the Thermal
Shutdown section.
G
m1
G
m2
G
m3
EMI
FILTER
AND
CLAMP
THERMAL
SHUTDOWN
OFFSET
AND RIPPLE
CORRECTION
LOOP
+INx
–INx
CHOP
IN
CHOP
OUT
C3
OUT
C2
C1
4.8MHz CLOCKS
800kHz CLOCKS
CLOCK
GENERATOR
13168-068
Figure 69. ADA4522-2 Block Diagram
ON-CHIP INPUT EMI FILTER AND CLAMP CIRCUIT
Figure 70 shows the input EMI filter and clamp circuit. The
ADA4522-2 has internal ESD protection diodes (D1, D2, D3,
and D4) that are connected between the inputs and each supply
rail. These diodes protect the input transistors in the event of
electrostatic discharge and are reverse biased during normal
operation. This protection scheme allows voltages as high as
approximately 300 mV beyond the rails to be applied at the
input of either terminal without causing permanent damage.
See Table 5 in the Absolute Maximum Ratings section for more
information.
The EMI filter is composed of two 200 Ω input series resistors
(RS1 and RS2), two common-mode capacitors (CCM1 and CCM2),
and a differential capacitor (CDM). These RC networks set the
−3 dB low-pass cutoff frequencies at 50 MHz for common-
mode signals, and at 33 MHz for differential signals. After the
EMI filter, back to back diodes (D5 and D6) are added to protect
internal circuit devices from high voltage input transients. Each
diode has about 1 V of forward turn on voltage. See the Large
Signal Transient Response section for more information on the
effect of high voltage input transient on the ADA4522-2.
As specified in the Absolute Maximum Ratings table (Table 5), the
maximum input differential voltage is limited to ±5 V. If more than
±5 V is applied, a continuous current larger than ±10 mA flows
through one of the back to back diodes. This compromises long
term reliability and can cause permanent damage to the device.
V+
+INx
–INx
V–
R
S1
200Ω
R
S2
200Ω
D1
D2 D5 D6
D4
D3 C
CM1
C
DM
C
CM2
13168-069
Figure 70. Input EMI Filter and Clamp Circuit
Rev. 0 | Page 20 of 28
Data Sheet ADA4522-2
THERMAL SHUTDOWN
The ADA4522-2 has internal thermal shutdown circuitry for
each channel of the amplifier. The thermal shutdown circuitry
prevents internal devices from being damaged by an overheat
condition in the die. Overheat can occur due to a high ambient
temperature, a high supply voltage, and/or high output currents.
As specified in Table 5, care must be taken to maintain the
junction temperature below 150°C.
Two conditions affect junction temperature (TJ): the total power
dissipation of the device (PD) and the ambient temperature
surrounding the package (TA). Use the following equation to
estimate the approximate junction temperature:
TJ = PD × θJA + TA (1)
where θJA is the thermal resistance between the die and the
ambient environment, as shown in Table 6.
The total power dissipation is the sum of quiescent power of the
device and the power required to drive a load for all channels of
an amplifier. The power dissipation per amplifier (PD_PER_AMP)
for sourcing a load is shown in Equation 2.
PD_PER_AMP = (VSY+ − VSY−) × ISY_PER_AMP + IOUT × (VSY+ − VOUT) (2)
When sinking current, replace (VSY+ − VOUT) in Equation 2 with
(VOUT − VSY−).
Also, take note to include the power dissipation of both
channels of the amplifier when calculating the total power
dissipation for the ADA4522-2.
The thermal shutdown circuitry does not guarantee that the device
is to be free of permanent damage if the junction temperature
exceeds 150°C. However, the internal thermal shutdown function
may help avoid permanent damage or reduce the degree of damage.
Each amplifier channel has thermal shutdown circuitry, composed
of a temperature sensor with hysteresis.
As soon as the junction temperature reaches 190°C, the thermal
shutdown circuitry shuts down the amplifier. Note that either
one of the two thermal shutdown circuitries are activated; this
activation disables the channel. When the amplifier is disabled, the
output becomes open state and the quiescent current of the channel
decreases to 0.1 mA. When the junction temperature cools down to
160°C, the thermal shutdown circuitry enables the amplifier and
the quiescent current increases to its typical value.
When overheating in the die is caused by an undesirable excess
amount of output current, the thermal shutdown circuit repeats
its function. The junction temperature keeps increasing until it
reaches 190°C and one of the channels is disabled. Then, the
junction temperature cools down until it reaches 160°C, and the
channel is enabled again. The process then repeats.
INPUT PROTECTION
When either input of the ADA4522-2 exceeds one of the supply
rails by more than 300 mV, the ESD diodes mentioned in the
On-Chip Input EMI Filter and Clamp Circuit section become
forward-biased and large amounts of current begin to flow
through them. Without current limiting, this excessive fault
current causes permanent damage to the device. If the inputs
are expected to be subject to overvoltage conditions, insert a
resistor in series with each input to limit the input current to
±10 mA maximum. However, consider the resistor thermal
noise effect on the entire circuit.
At ±15 V supply voltage, the broadband voltage noise of the
ADA4522-2 is approximately 7.3 nV/√Hz (at unity gain), and a
1 kΩ resistor has thermal noise of 4 nV/√Hz. Adding a 1 kΩ
resistor increases the total noise to 8.3 nV/√Hz.
SINGLE-SUPPLY AND RAIL-TO-RAIL OUTPUT
The ADA4522-2 is a single-supply amplifier, where its input
voltage range includes the lower supply rail. This is ideal for
applications where the input common-mode voltage is at the
lower supply rail, for example, ground sensing. On the other
hand, the amplifier output is rail-to-rail. Figure 71 shows the
input and output waveforms of the ADA4522-2 configured as a
unity-gain buffer with a supply voltage of ±15 V. With an input
voltage of ±15 V, the low output voltage tracks the input voltage,
whereas the high output swing clamps/distorts when the input
goes out of the input voltage range (−15 V ≤ IVR ≤ +13.5 V).
However, the device does not exhibit phase reversal.
20
10
0
–10
–20
15
5
–5
–15
20
10
0
–10
–20
15
5
–5
–15
INPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
TIME (400s/DIV)
V
SY
= ±15V
A
V
= +1
V
IN
V
OUT
13168-070
Figure 71. No Phase Reversal
Rev. 0 | Page 21 of 28
ADA4522-2 Data Sheet
30
–30
–20
–10
0
10
20
VOLTAGE (V)
TIME (10µs/DIV)
V
SY
= ±27.5V
R
S_IN–
100Ω
R
S_IN+
100Ω
V
SY
+
V
SY
–
ADA4522-2
100pF 10kΩ
V
OUT
V
IN
= 50V p-p
13168-071
Figure 72. Large Signal Transient Response Example
LARGE SIGNAL TRANSIENT RESPONSE
When the ADA4522-2 is configured in a closed-loop configuration
with a large input transient (for example, a step input voltage), the
internal back to back diodes may turn on. Consider a case where
the amplifier is in unity-gain configuration with a step input
waveform. This is shown in Figure 72.
The noninverting input is driven by an input signal source and
the inverting input is driven by the output of the amplifier. The
maximum amplifier output current depends on the input step
function and the external source resistance at the input
terminals of the amplifier.
Case 1
If the external source resistance is low (for example, 100 Ω in
Figure 72) or if the input step function is large, the maximum
amplifier output current is limited to the output short-circuit
current as specified in the Specifications section. The maximum
differential voltage between the input signal and the amplifier
output is then limited by the maximum amplifier output current
multiplied by the total input resistance (internal and external)
and the turn on voltage of the back to back diode (see Figure 70
for the input EMI filter and clamp circuit architecture). When
the noninverting input voltage changes with a step signal, the
inverting input voltage (and, therefore, the output voltage)
follows the change quickly until it reaches the maximum
differential voltage between the input signal and amplifier
output possible. The inverting input voltage then starts slewing
with the slew rate specified in the Specifications section until it
reaches its desired output. Therefore, as seen in Figure 72, there are
two distinctive sections of the rising and falling edge of the
output waveform. With this test condition, the amount and
duration of the input/output current is limited and, therefore,
does not damage the amplifier.
Case 2
If the external source resistance is high or if the input step
function is small, the maximum output current is limited to the
instantaneous difference between the input signal and amplifier
output voltage (which is the change in the step function) divided by
the source resistance. This maximum output current is less than
the amplifier output short-circuit current. The maximum
differential voltage between the input signal and the amplifier
output is then equal to the step function. The output voltage
slews until it reaches its desired output.
Therefore, if desired, reduce the input current by adding a
larger external resistor between the signal source and the
noninverting input. Similarly, to reduce output current, add an
external resistor to the feedback loop between the inverting
input and output. This large signal transient response issue is
typically not a problem when the amplifier is configured in
closed-loop gain, where the input signal source is usually much
smaller and the gain and feedback resistors limit the current.
Back to back diodes are also implemented in many other
amplifiers; these amplifiers show similar slewing behavior.
NOISE CONSIDERATIONS
1/f Noise
1/f noise, also known as pink noise or flicker noise, is inherent
in semiconductor devices and increases as frequency decreases.
At a low frequency, 1/f noise is a major noise contributor and
causes a significant output voltage offset when amplified by the
noise gain of the circuit. However, because the low frequency
1/f noise appears as a slow varying offset to the ADA4522-2, it
is effectively reduced by the chopping technique. This allows
the ADA4522-2 to have a much lower noise at dc and low
frequency in comparison to standard low noise amplifiers that
are susceptible to 1/f noise. Figure 62 shows the 0.1 Hz to 10 Hz
noise to be only 117 nV p-p of noise.
Source Resistance
The ADA4522-2 is one of the lowest noise high voltage zero
drift amplifiers with 5.8 nV/√Hz of broadband noise at 1 kHz
(AV = 100). Therefore, it is important to consider the input
source resistance of choice to maintain a total low noise. The
total input referred broadband noise (eN total) from any
amplifier is primarily a function of three types of noise: input
voltage noise, input current noise, and thermal (Johnson) noise
from the external resistors.
Rev. 0 | Page 22 of 28
Data Sheet ADA4522-2
These uncorrelated noise sources can be summed up in a root
sum squared (rss) manner by using the following equation:
eN total = [eN2 + 4 kTRS + (iN × RS)2]1/2
where:
eN is the input voltage noise density of the amplifier (V/√Hz).
k is the Boltzmann’s constant (1.38 × 10−23 J/K).
T is the temperature in Kelvin (K).
RS is the total input source resistance (Ω).
iN is the input current noise density of the amplifier (A/√Hz).
The total equivalent rms noise over a specific bandwidth is
expressed as
eN RMS = eN total
BW
where BW is the bandwidth in hertz.
This analysis is valid for broadband noise calculation up to a
decade before the switching frequency. If the bandwidth of
concern includes the switching frequency, more complicated
calculations must be made to include the effect of the increase
in noise at the switching frequency.
With a low source resistance of RS < 1 kΩ, the voltage noise of
the amplifier dominates. As the source resistance increases, the
thermal noise of RS dominates. As the source resistance further
increases, where RS > 50 kΩ, the current noise becomes the
main contributor of the total input noise.
Residual Ripple
As shown in Figure 58, Figure 59, and Figure 60, the ADA4522-2
has a flat noise spectrum density at lower frequencies and exhibits
spectrum density bumps and peaks at higher frequencies.
The largest noise bump is centered at 6 MHz; this is due to the
decrease in the input gain at higher frequencies. This is a typical
phenomenon and can also be seen in other amplifiers. In addition
to the noise bump, a sharp peak due to the chopping networks is
seen at 4.8 MHz. However, this magnitude is significantly reduced
by the offset and ripple correction loop. Its magnitude may be
different with different amplifier units or with different circuitries
around the amplifier. This peak can potentially be hidden by the
noise bump and, therefore, may not be detected.
The offset and ripple correction loop, designed to reduce the
4.8 MHz switching artifact, also creates a noise bump centered
at 800 kHz and a noise peak on top of this noise bump. Although
the magnitude of the bump is mostly constant, the magnitude of
the 800 kHz peak is different from unit to unit. Some units may
not exhibit the 800 kHz noise peak, however, for other units,
peaks occur at multiple integrals of 800 kHz, such as 1.6 MHz or
2.4 MHz.
These noise peaks, albeit small in magnitude, can be significant
when the amplifier has a closed-loop frequency that is higher
than the chopping frequency. To suppress the noise spike to a
desired level, one can either configure the amplifier in high gain
configuration or apply a post filter at the output of the amplifier.
Figure 73 shows the voltage noise density of the ADA4522-2 in
different gain configurations. Note that the higher the gain, the
lower the available bandwidth is. The earlier bandwidth roll-off
effectively filters out the higher noise spectrum.
100
10
1
100 1k 10k 100k 1M 10M 100M
VOLTAGE NOISE DENSITY (nV/√Hz)
FREQUENCY (Hz)
V
SY
= ±15V
A
V
= +1
A
V
= +10
A
V
= +100
13168-072
Figure 73. Voltage Noise Density with Various Gains
Figure 74 shows the voltage noise density of the ADA4522-2
without and with post filters at different frequencies. The post
filter serves to roll off the bandwidth before the switching
frequency. In this example, the noise peak at 800 kHz is about
38 nV/√Hz. With a post filter at 80 kHz, the noise peak is
reduced to 4.1 nV/√Hz. With a post filter at 8 kHz, the noise
peak is lower than the noise floor and cannot be detected.
100
10
1
1k 10k 100k 1M 10M 100M
VOLTAGE NOISE DENSITY (nV/√Hz)
FREQUENCY (Hz)
A
V
= +1
A
V
= +1 (POST FILTER AT 80kHz)
A
V
= +1 (POST FILTER AT 8kHz)
13168-073
Figure 74. Voltage Noise Density with Post Filters
Current Noise Density
Figure 75 shows the current noise density of the ADA4522-2 at
unity gain. At 1 kHz, current noise density is about 1.3 pA/√Hz.
Current noise density is determined by measuring the voltage
noise due to current noise flowing through a resistor. Due to the
low current noise density of the amplifier, the voltage noise is
usually measured with a high value resistor; in this case, a
100 kΩ source resistor is used. However, the source resistor
interacts with the input capacitance of the amplifier and board,
causing bandwidth to roll off. Note that Figure 75 shows the
current noise density rolling off much earlier than the unity-
gain bandwidth; this is expected.
Rev. 0 | Page 23 of 28
ADA4522-2 Data Sheet
10
1
0.1
10 100 1k 10k 100k
CURRENT NOISE DENSITY (pA/√Hz)
FREQUENCY (Hz)
VSY = ±2.5V
VSY = ±15V
VSY = ±27.5V
RS = 100kΩ
AV = +1
13168-074
Figure 75. Current Noise Density at Gain = 1
EMI REJECTION RATIO
Circuit performance is often adversely affected by high frequency
EMI. When the signal strength is low and transmission lines are
long, an op amp must accurately amplify the input signals. How-
ever, all op amp pins—the noninverting input, inverting input,
positive supply, negative supply, and output pins—are susceptible to
EMI signals. These high frequency signals are coupled into an op
amp by various means, such as conduction, near field radiation, or
far field radiation. For example, wires and PCB traces can act as
antennas and pick up high frequency EMI signals.
Amplifiers do not amplify EMI or RF signals due to their
relatively low bandwidth. However, due to the nonlinearities of
the input devices, op amps can rectify these out of band signals.
When these high frequency signals are rectified, they appear as
a dc offset at the output.
The ADA4522-2 has integrated EMI filters at its input stage. To
describe the ability of the ADA4522-2 to perform as intended in
the presence of electromagnetic energy, the electromagnetic
interference rejection ratio (EMIRR) of the noninverting pin is
specified in Table 2, Table 3, and Table 4 of the Specifications
section. A mathematical method of measuring EMIRR is
defined as follows:
EMIRR = 20log(VIN_PEAK/∆VOS)
100
50
90
40
80
30
70
20
60
10
0
10M 100M 1G 10G
EMIRR (dB)
FREQUENCY (Hz)
55V
30V
5V
V
IN
= 100mV p-p
13168-075
Figure 76. EMIRR vs. Frequency
CAPACITIVE LOAD STABILITY
The ADA4522-2 can safely drive capacitive loads of up to
250 pF in any configuration. As with most amplifiers, driving
larger capacitive loads than specified may cause excessive
overshoot and ringing, or even oscillation. A heavy capacitive
load reduces phase margin and causes the amplifier frequency
response to peak. Peaking corresponds to overshooting or
ringing in the time domain. Therefore, it is recommended that
external compensation be used if the ADA4522-2 must drive a
load exceeding 250 pF. This compensation is particularly
important in the unity-gain configuration, which is the worst
case for stability.
A quick and easy way to stabilize the op amp for capacitive load
drive is by adding a series resistor, RISO, between the amplifier
output terminal and the load capacitance, as shown in Figure 77.
RISO isolates the amplifier output and feedback network from
the capacitive load. However, with this compensation scheme,
the output impedance as seen by the load increases, and this
reduces gain accuracy.
1/2
–V
SY
V
IN
+V
SY
V
OUT
C
L
ADA4522-2
R
ISO
13168-076
Figure 77. Stability Compensation with Isolating Resistor, RISO
Figure 78 shows the effect on overshoot with different values of
RISO.
60
25
50
55
45
20
40
15
35
10
30
5
0
10 100 1k
OVERSHOOT (%)
LOAD CAPACITANCE (pF)
V
SY
= ±15V
R
L
= 10kΩ
A
V
= +1
V
IN
= 100mV p-p
OS+ (R
ISO
= 0Ω)
OS– (R
ISO
= 0Ω)
OS+ (R
ISO
= 25Ω)
OS– (R
ISO
= 25Ω)
OS+ (R
ISO
= 50Ω)
OS– (R
ISO
= 50Ω)
13168-077
Figure 78. Small Signal Overshoot vs. Load Capacitance with Various Output
Isolating Resistors
SINGLE-SUPPLY INSTRUMENTATION AMPLIFIER
The extremely low offset voltage and drift, high open-loop gain,
high common-mode rejection, and high power supply rejection
of the ADA4522-2 make it an excellent op amp choice as a
discrete, single-supply instrumentation amplifier.
Rev. 0 | Page 24 of 28
Data Sheet ADA4522-2
Figure 79 shows the classic 3-op-amp instrumentation amplifier
using the ADA4522-2. The key to high CMRR for the instrument-
ation amplifier are resistors that are well matched for both the
resistive ratio and relative drift. For true difference amplifica-
tion, matching of the resistor ratio is very important, where
R5/R2 = R6/R4. The resistors are important in determining the
performance over manufacturing tolerances, time, and temp-
erature. Assuming a perfect unity-gain difference amplifier with
infinite common-mode rejection, a 1% tolerance resistor
matching results in only 34 dB of common-mode rejection.
Therefore, at least 0.01% or better resistors are recommended.
V
IN1
V
IN2
A1
A3
A2
R
G1
R
G2
R1
R3
R2
R4
R5
V
OUT
R6
R
G1
= R
G2
, R1 = R3, R2 = R4, R5 = R6
V
OUT
= (V
IN2
– V
IN1
) (1 + R1/R
G1
) (R5/R2)
13168-078
Figure 79. Discrete 3-Op Amp Instrumentation Amplifier
To build a discrete instrumentation amplifier with external
resistors without compromising on noise, pay close attention to
the resistor values chosen. RG1 and RG2 each have thermal noise
that is amplified by the total noise gain of the instrumentation
amplifier and, therefore, must be chosen sufficiently low to
reduce thermal noise contribution at the output while still
providing an accurate measurement. Table 8 shows the external
resistors noise contribution referred to the output (RTO).
Table 8. Thermal Noise Contribution Example
Resistor
Value
(kΩ)
Resistor Thermal
Noise (nV/√Hz)
Thermal Noise
RTO (nV/√Hz)
RG1 0.4 2.57 128.30
RG2 0.4 2.57 128.30
R1 10 12.83 25.66
R2 10 12.83 25.66
R3 10 12.83 25.66
R4 10 12.83 25.66
R5 20 18.14 18.14
R6 20 18.14 18.14
Note that A1 and A2 have a high gain of 1 + R1/RG1. Therefore,
use a high precision, low offset voltage and low noise amplifier
for A1 and A2, such as the ADA4522-2. On the other hand, A3
operates at a much lower gain and has a different set of op amp
requirements. Its input noise, referred to the overall instrumen-
tation amplifier input, is divided by the first stage gain and is not
as important. Note that the input offset voltage and the input
voltage noise of the amplifiers are also amplified by the overall
noise gain.
Understanding how noise impacts a discrete instrumentation
amplifier or a difference amplifier (the second stage of a 3-op-
amp instrumentation amplifier) is important, because they are
commonly used in many different applications. The Load
Cell/Strain Gage Sensor Signal Conditioning section and the
Precision Low-Side Current Shunt Sensor section show the
ADA4522-2 used as a discrete instrumentation or difference
amplifier in an application.
LOAD CELL/STRAIN GAGE SENSOR SIGNAL
CONDITIONING
The ADA4522-2, with its ultralow offset, drift, and noise, is well
suited to signal condition low level sensor output with high gain
and accuracy. A weigh scale/load cell is an example of an
application with such requirements. Figure 80 shows a config-
uration for a single supply, precision, weigh scale measurement
system. The ADA4522-2 is used at the front end for amplification
of the low level signal from the load cell.
Current flowing through a PCB trace produces an IR voltage
drop; with longer traces, this voltage drop can be several
millivolts or more, introducing a considerable error. A 1 inch
long, 0.005 inch wide trace of 1 oz copper has a resistance of
approximately 100 mΩ at room temperature. With a load
current of 10 mA, the resistance can introduce a 1 mV error.
Therefore, a 6-wire load cell is used in the circuit. It has two
sense pins, in addition to excitation, ground, and two output
connections. The sense pins are connected to the high side
(excitation pin) and low side (ground pin) of the Wheatstone
bridge. The voltage across the bridge can then be accurately
measured regardless of voltage drop due to wire resistance. The
two sense pins are also connected to the ADC reference inputs
for a ratiometric configuration that is immune to low frequency
changes in the power supply excitation voltage.
The ADA4522-2 is configured as the first stage of a 3-op-amp
instrumentation amplifier. It amplifies the low level amplitude
signal from the load cell by a factor of 1 + 2R1/RG. Capacitors
C1 and C2 are placed in the feedback loops of the amplifiers
and interact with R1 and R2 to perform low-pass filtering. This
limits the amount of noise entering the Σ-∆ ADC. In addition,
C3, C4, C5, R3, and R4 provide further common-mode and
differential mode filtering to reduce noise and unwanted signals.
Rev. 0 | Page 25 of 28
ADA4522-2 Data Sheet
OUT+
SENSE–
SENSE+
OUT–
VEXC
1/2
V+
R1 11.3kΩ
C1 3.3µF
1/2
ADA4522-2
R2 11.3kΩ
C2 3.3µF
RG
60.4Ω
R3
1kΩ
R4
1kΩ
C4
1µF
C5
10µF
C3
1µF AIN+
REFIN–
REFIN+
DOUT/
RDY
DIN
AIN–
GND
VDD
+5V
AD7791
100pF
1µF
100pF
SCLK
CS
LOAD
CELL
13168-079
Figure 80. Precision Weigh Scale Measurement System
PRECISION LOW-SIDE CURRENT SHUNT SENSOR
Many applications require the sensing of signals near the
positive or negative rails. Current shunt sensors are one such
application and are mostly used for feedback control systems.
They are also used in a variety of other applications, including
power metering, battery fuel gauging, and feedback controls in
industrial applications. In such applications, it is desirable to use
a shunt with very low resistance to minimize series voltage
drop. This not only minimizes wasted power, but also allows the
measurement of high currents while saving power.
A typical shunt may be 100 mΩ. At a measured current of 1 A,
the voltage produced from the shunt is 100 mV, and the
amplifier error sources are not critical. However, at low
measured current in the 1 mA range, the 100 µV generated
across the shunt demands a very low offset voltage and drift
amplifier to maintain absolute accuracy. The unique attributes
of a zero drift amplifier provide a solution. Figure 81 shows a
low-side current sensing circuit using the ADA4522-2. The
ADA4522-2 is configured as a difference amplifier with a gain
of 1000. Although the ADA4522-2 has high common-mode
rejection, the CMR of the system is limited by the external
resistors. Therefore, as mentioned in the Single-Supply
Instrumentation Amplifier section, the key to high CMR for the
system is resistors that are well matched from both the resistive
ratio and relative drift, where R1/R2 = R3/R4.
R2
100kΩ
V
SY
V
SY
V
OUT
*
*V
OUT
= AMPLIFIER GAIN × VOLTAGE ACROSS R
S
= 1000 × R
S
× I
= 100 × I
R
L
R
S
0.1Ω
R1
100Ω
I
ADA4522-2
R4
100kΩ R3
100Ω
I
1/2
13168-080
Figure 81. Low-Side Current Sensing
PRINTED CIRCUIT BOARD LAYOUT
The ADA4522-2 is a high precision device with ultralow offset
voltage and noise. Therefore, take care in the design of the
printed circuit board (PCB) layout to achieve optimum
performance of the ADA4522-2 at the board level.
To avoid leakage currents, keep the surface of the board clean
and free of moisture.
Properly bypassing the power supplies and keeping the supply
traces short minimizes power supply disturbances caused by
output current variation. Connect bypass capacitors as close as
possible to the device supply pins. Stray capacitances are a
concern at the outputs and the inputs of the amplifier. It is
recommended that signal traces be kept at a distance of at least
5 mm from supply lines to minimize coupling.
A potential source of offset error is the Seebeck voltage on the
circuit board. The Seebeck voltage occurs at the junction of two
dissimilar metals and is a function of the temperature of the
junction. The most common metallic junctions on a circuit board
are solder to board traces and solder to component leads.
Figure 82 shows a cross section of a surface-mount component
soldered to a PCB. A variation in temperature across the board
(where TA1 ≠ TA2) causes a mismatch in the Seebeck voltages at the
solder joints, thereby resulting in thermal voltage errors that
degrade the performance of the ultralow offset voltage of the
ADA4522-2.
SOLDER
+
+
+
+
COMPONENT
LEAD
COPPER
TRACE
VSC1
VTS1
TA1
SURFACE-MOUNT
COMPONENT
PC BOARD
TA2
VSC2
VTS2
IF TA1 ≠ TA2, THEN
VTS1 + VSC1 ≠ VTS2 + VSC2
13168-081
Figure 82. Mismatch in Seebeck Voltages Causes Seebeck Voltage Error
Rev. 0 | Page 26 of 28
Data Sheet ADA4522-2
To minimize these thermocouple effects, orient resistors so that
heat sources warm both ends equally. Where possible, it is
recommended that the input signal paths contain matching
numbers and types of components to match the number and type
of thermocouple junctions. For example, dummy components,
such as zero value resistors, can be used to match the thermo-
electric error source (real resistors in the opposite input path).
Place matching components in close proximity and orient them
in the same manner to ensure equal Seebeck voltages, thus
cancelling thermal errors. Additionally, use leads that are of equal
length to keep thermal conduction in equilibrium. Keep heat
sources on the PCB as far away from amplifier input circuitry as is
practical.
It is highly recommended to use a ground plane. A ground
plane helps distribute heat throughout the board, maintain a
constant temperature across the board, and reduce EMI noise
pick up.
COMPARATOR OPERATION
An op amps is designed to operate in a closed-loop configuration
with feedback from its output to its inverting input. In contrast to
op amps, comparators are designed to operate in an open-loop
configuration and to drive logic circuits. Although op amps are
different from comparators, occasionally an unused section of a
dual op amp is used as a comparator to save board space and
cost; however, this is not recommended for the ADA4522-2.
Figure 83 and Figure 84 show the ADA4522-2 configured as a
comparator, with 10 kΩ resistors in series with the input pins. Any
unused channels are configured as buffers with the input voltage
kept at the midpoint of the power supplies. The ADA4522-2 has
input devices that are protected from large differential input
voltages by Diode D5 and D6, as shown in Figure 70. These
diodes consist of substrate PNP bipolar transistors, and conduct
whenever the differential input voltage exceeds approximately
600 mV; however, these diodes also allow a current path from
the input to the lower supply rail, resulting in an increase in the
total supply current of the system. Both comparator configurations
yield the same result. At 30 V of power supply, ISY+ remains at
1.55 mA per dual amplifier, but ISY− increases close to 2 mA in
magnitude per dual amplifier.
1/2
ADA4522-2
A1
10kΩ
10kΩ
ISY+
+VSY
VOUT
–VSY
ISY–
A2
13168-082
Figure 83. Comparator Configuration A
1/2
A1
10kΩ
10kΩ
I
SY
+
+V
SY
V
OUT
–V
SY
I
SY
–
A2
ADA4522-2
13168-083
Figure 84. Comparator Configuration B
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
0 6 12 18 24 30410 16 22 282 8 14 20 26
ISY PER DUAL AMPLIFIER (mA)
VSY (V)
ISY+
ISY–
13168-084
Figure 85. Supply Current (ISY) per Dual Amplifier vs. Supply Voltage (VSY)
(ADA4522-2 as a Comparator)
Note that 10 kΩ resistors are used in series with the input of the
op amp. If smaller resistor values are used, the supply current of the
system increases much more. For more details on op amps as
comparators, see AN-849 Application Note, Using Op Amps as
Comparators.
Rev. 0 | Page 27 of 28
ADA4522-2 Data Sheet
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-187-AA
6°
0°
0.80
0.55
0.40
4
8
1
5
0.65 BSC
0.40
0.25
1.10 MAX
3.20
3.00
2.80
COPLANARITY
0.10
0.23
0.09
3.20
3.00
2.80
5.15
4.90
4.65
PIN 1
IDENTIFIER
15° MAX
0.95
0.85
0.75
0.15
0.05
10-07-2009-B
Figure 86. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-A A
012407-A
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099) 45°
8°
0°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
4
1
8 5
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2441)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
Figure 87. 8-Lead Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option Branding
ADA4522-2ARMZ −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 A39
ADA4522-2ARMZ-R7 −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 A39
ADA4522-2ARMZ-RL −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 A39
ADA4522-2ARZ −40°C to +125°C 8-Lead Small Outline Package [SOIC_N] R-8
ADA4522-2ARZ-R7
−40°C to +125°C
8-Lead Small Outline Package [SOIC_N]
R-8
ADA4522-2ARZ-RL −40°C to +125°C 8-Lead Small Outline Package [SOIC_N] R-8
1 Z = RoHS Compliant Part.
©2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D13168-0-5/15(0)
Rev. 0 | Page 28 of 28
